drivers/net/ethernet/realtek/r8169.c

   1 /*
   2  * r8169.c: RealTek 8169/8168/8101 ethernet driver.
   3  *
   4  * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
   5  * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
   6  * Copyright (c) a lot of people too. Please respect their work.
   7  *
   8  * See MAINTAINERS file for support contact information.
   9  */
  10
  11 #include <linux/module.h>
  12 #include <linux/moduleparam.h>
  13 #include <linux/pci.h>
  14 #include <linux/netdevice.h>
  15 #include <linux/etherdevice.h>
  16 #include <linux/delay.h>
  17 #include <linux/ethtool.h>
  18 #include <linux/phy.h>
  19 #include <linux/if_vlan.h>
  20 #include <linux/crc32.h>
  21 #include <linux/in.h>
  22 #include <linux/io.h>
  23 #include <linux/ip.h>
  24 #include <linux/tcp.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/dma-mapping.h>
  27 #include <linux/pm_runtime.h>
  28 #include <linux/firmware.h>
  29 #include <linux/prefetch.h>
  30 #include <linux/ipv6.h>
  31 #include <net/ip6_checksum.h>
  32
  33 #define MODULENAME "r8169"
  34
  35 #define FIRMWARE_8168D_1        "rtl_nic/rtl8168d-1.fw"
  36 #define FIRMWARE_8168D_2        "rtl_nic/rtl8168d-2.fw"
  37 #define FIRMWARE_8168E_1        "rtl_nic/rtl8168e-1.fw"
  38 #define FIRMWARE_8168E_2        "rtl_nic/rtl8168e-2.fw"
  39 #define FIRMWARE_8168E_3        "rtl_nic/rtl8168e-3.fw"
  40 #define FIRMWARE_8168F_1        "rtl_nic/rtl8168f-1.fw"
  41 #define FIRMWARE_8168F_2        "rtl_nic/rtl8168f-2.fw"
  42 #define FIRMWARE_8105E_1        "rtl_nic/rtl8105e-1.fw"
  43 #define FIRMWARE_8402_1         "rtl_nic/rtl8402-1.fw"
  44 #define FIRMWARE_8411_1         "rtl_nic/rtl8411-1.fw"
  45 #define FIRMWARE_8411_2         "rtl_nic/rtl8411-2.fw"
  46 #define FIRMWARE_8106E_1        "rtl_nic/rtl8106e-1.fw"
  47 #define FIRMWARE_8106E_2        "rtl_nic/rtl8106e-2.fw"
  48 #define FIRMWARE_8168G_2        "rtl_nic/rtl8168g-2.fw"
  49 #define FIRMWARE_8168G_3        "rtl_nic/rtl8168g-3.fw"
  50 #define FIRMWARE_8168H_1        "rtl_nic/rtl8168h-1.fw"
  51 #define FIRMWARE_8168H_2        "rtl_nic/rtl8168h-2.fw"
  52 #define FIRMWARE_8107E_1        "rtl_nic/rtl8107e-1.fw"
  53 #define FIRMWARE_8107E_2        "rtl_nic/rtl8107e-2.fw"
  54
  55 #define R8169_MSG_DEFAULT \
  56         (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
  57
  58 #define TX_SLOTS_AVAIL(tp) \
  59         (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx)
  60
  61 /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
  62 #define TX_FRAGS_READY_FOR(tp,nr_frags) \
  63         (TX_SLOTS_AVAIL(tp) >= (nr_frags + 1))
  64
  65 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
  66    The RTL chips use a 64 element hash table based on the Ethernet CRC. */
  67 static const int multicast_filter_limit = 32;
  68
  69 #define TX_DMA_BURST    7       /* Maximum PCI burst, '7' is unlimited */
  70 #define InterFrameGap   0x03    /* 3 means InterFrameGap = the shortest one */
  71
  72 #define R8169_REGS_SIZE         256
  73 #define R8169_RX_BUF_SIZE       (SZ_16K - 1)
  74 #define NUM_TX_DESC     64      /* Number of Tx descriptor registers */
  75 #define NUM_RX_DESC     256U    /* Number of Rx descriptor registers */
  76 #define R8169_TX_RING_BYTES     (NUM_TX_DESC * sizeof(struct TxDesc))
  77 #define R8169_RX_RING_BYTES     (NUM_RX_DESC * sizeof(struct RxDesc))
  78
  79 #define RTL8169_TX_TIMEOUT      (6*HZ)
  80
  81 /* write/read MMIO register */
  82 #define RTL_W8(tp, reg, val8)   writeb((val8), tp->mmio_addr + (reg))
  83 #define RTL_W16(tp, reg, val16) writew((val16), tp->mmio_addr + (reg))
  84 #define RTL_W32(tp, reg, val32) writel((val32), tp->mmio_addr + (reg))
  85 #define RTL_R8(tp, reg)         readb(tp->mmio_addr + (reg))
  86 #define RTL_R16(tp, reg)                readw(tp->mmio_addr + (reg))
  87 #define RTL_R32(tp, reg)                readl(tp->mmio_addr + (reg))
  88
  89 enum mac_version {
  90         RTL_GIGA_MAC_VER_01 = 0,
  91         RTL_GIGA_MAC_VER_02,
  92         RTL_GIGA_MAC_VER_03,
  93         RTL_GIGA_MAC_VER_04,
  94         RTL_GIGA_MAC_VER_05,
  95         RTL_GIGA_MAC_VER_06,
  96         RTL_GIGA_MAC_VER_07,
  97         RTL_GIGA_MAC_VER_08,
  98         RTL_GIGA_MAC_VER_09,
  99         RTL_GIGA_MAC_VER_10,
 100         RTL_GIGA_MAC_VER_11,
 101         RTL_GIGA_MAC_VER_12,
 102         RTL_GIGA_MAC_VER_13,
 103         RTL_GIGA_MAC_VER_14,
 104         RTL_GIGA_MAC_VER_15,
 105         RTL_GIGA_MAC_VER_16,
 106         RTL_GIGA_MAC_VER_17,
 107         RTL_GIGA_MAC_VER_18,
 108         RTL_GIGA_MAC_VER_19,
 109         RTL_GIGA_MAC_VER_20,
 110         RTL_GIGA_MAC_VER_21,
 111         RTL_GIGA_MAC_VER_22,
 112         RTL_GIGA_MAC_VER_23,
 113         RTL_GIGA_MAC_VER_24,
 114         RTL_GIGA_MAC_VER_25,
 115         RTL_GIGA_MAC_VER_26,
 116         RTL_GIGA_MAC_VER_27,
 117         RTL_GIGA_MAC_VER_28,
 118         RTL_GIGA_MAC_VER_29,
 119         RTL_GIGA_MAC_VER_30,
 120         RTL_GIGA_MAC_VER_31,
 121         RTL_GIGA_MAC_VER_32,
 122         RTL_GIGA_MAC_VER_33,
 123         RTL_GIGA_MAC_VER_34,
 124         RTL_GIGA_MAC_VER_35,
 125         RTL_GIGA_MAC_VER_36,
 126         RTL_GIGA_MAC_VER_37,
 127         RTL_GIGA_MAC_VER_38,
 128         RTL_GIGA_MAC_VER_39,
 129         RTL_GIGA_MAC_VER_40,
 130         RTL_GIGA_MAC_VER_41,
 131         RTL_GIGA_MAC_VER_42,
 132         RTL_GIGA_MAC_VER_43,
 133         RTL_GIGA_MAC_VER_44,
 134         RTL_GIGA_MAC_VER_45,
 135         RTL_GIGA_MAC_VER_46,
 136         RTL_GIGA_MAC_VER_47,
 137         RTL_GIGA_MAC_VER_48,
 138         RTL_GIGA_MAC_VER_49,
 139         RTL_GIGA_MAC_VER_50,
 140         RTL_GIGA_MAC_VER_51,
 141         RTL_GIGA_MAC_NONE   = 0xff,
 142 };
 143
 144 #define JUMBO_1K        ETH_DATA_LEN
 145 #define JUMBO_4K        (4*1024 - ETH_HLEN - 2)
 146 #define JUMBO_6K        (6*1024 - ETH_HLEN - 2)
 147 #define JUMBO_7K        (7*1024 - ETH_HLEN - 2)
 148 #define JUMBO_9K        (9*1024 - ETH_HLEN - 2)
 149
 150 #define _R(NAME, FW, SZ) {      \
 151         .name = NAME,           \
 152         .fw_name = FW,          \
 153         .jumbo_max = SZ,        \
 154 }
 155
 156 static const struct {
 157         const char *name;
 158         const char *fw_name;
 159         u16 jumbo_max;
 160 } rtl_chip_infos[] = {
 161         /* PCI devices. */
 162         [RTL_GIGA_MAC_VER_01] =
 163                 _R("RTL8169",           NULL, JUMBO_7K),
 164         [RTL_GIGA_MAC_VER_02] =
 165                 _R("RTL8169s",          NULL, JUMBO_7K),
 166         [RTL_GIGA_MAC_VER_03] =
 167                 _R("RTL8110s",          NULL, JUMBO_7K),
 168         [RTL_GIGA_MAC_VER_04] =
 169                 _R("RTL8169sb/8110sb",  NULL, JUMBO_7K),
 170         [RTL_GIGA_MAC_VER_05] =
 171                 _R("RTL8169sc/8110sc",  NULL, JUMBO_7K),
 172         [RTL_GIGA_MAC_VER_06] =
 173                 _R("RTL8169sc/8110sc",  NULL, JUMBO_7K),
 174         /* PCI-E devices. */
 175         [RTL_GIGA_MAC_VER_07] =
 176                 _R("RTL8102e",          NULL, JUMBO_1K),
 177         [RTL_GIGA_MAC_VER_08] =
 178                 _R("RTL8102e",          NULL, JUMBO_1K),
 179         [RTL_GIGA_MAC_VER_09] =
 180                 _R("RTL8102e",          NULL, JUMBO_1K),
 181         [RTL_GIGA_MAC_VER_10] =
 182                 _R("RTL8101e",          NULL, JUMBO_1K),
 183         [RTL_GIGA_MAC_VER_11] =
 184                 _R("RTL8168b/8111b",    NULL, JUMBO_4K),
 185         [RTL_GIGA_MAC_VER_12] =
 186                 _R("RTL8168b/8111b",    NULL, JUMBO_4K),
 187         [RTL_GIGA_MAC_VER_13] =
 188                 _R("RTL8101e",          NULL, JUMBO_1K),
 189         [RTL_GIGA_MAC_VER_14] =
 190                 _R("RTL8100e",          NULL, JUMBO_1K),
 191         [RTL_GIGA_MAC_VER_15] =
 192                 _R("RTL8100e",          NULL, JUMBO_1K),
 193         [RTL_GIGA_MAC_VER_16] =
 194                 _R("RTL8101e",          NULL, JUMBO_1K),
 195         [RTL_GIGA_MAC_VER_17] =
 196                 _R("RTL8168b/8111b",    NULL, JUMBO_4K),
 197         [RTL_GIGA_MAC_VER_18] =
 198                 _R("RTL8168cp/8111cp",  NULL, JUMBO_6K),
 199         [RTL_GIGA_MAC_VER_19] =
 200                 _R("RTL8168c/8111c",    NULL, JUMBO_6K),
 201         [RTL_GIGA_MAC_VER_20] =
 202                 _R("RTL8168c/8111c",    NULL, JUMBO_6K),
 203         [RTL_GIGA_MAC_VER_21] =
 204                 _R("RTL8168c/8111c",    NULL, JUMBO_6K),
 205         [RTL_GIGA_MAC_VER_22] =
 206                 _R("RTL8168c/8111c",    NULL, JUMBO_6K),
 207         [RTL_GIGA_MAC_VER_23] =
 208                 _R("RTL8168cp/8111cp",  NULL, JUMBO_6K),
 209         [RTL_GIGA_MAC_VER_24] =
 210                 _R("RTL8168cp/8111cp",  NULL, JUMBO_6K),
 211         [RTL_GIGA_MAC_VER_25] =
 212                 _R("RTL8168d/8111d",    FIRMWARE_8168D_1, JUMBO_9K),
 213         [RTL_GIGA_MAC_VER_26] =
 214                 _R("RTL8168d/8111d",    FIRMWARE_8168D_2, JUMBO_9K),
 215         [RTL_GIGA_MAC_VER_27] =
 216                 _R("RTL8168dp/8111dp",  NULL, JUMBO_9K),
 217         [RTL_GIGA_MAC_VER_28] =
 218                 _R("RTL8168dp/8111dp",  NULL, JUMBO_9K),
 219         [RTL_GIGA_MAC_VER_29] =
 220                 _R("RTL8105e",          FIRMWARE_8105E_1, JUMBO_1K),
 221         [RTL_GIGA_MAC_VER_30] =
 222                 _R("RTL8105e",          FIRMWARE_8105E_1, JUMBO_1K),
 223         [RTL_GIGA_MAC_VER_31] =
 224                 _R("RTL8168dp/8111dp",  NULL, JUMBO_9K),
 225         [RTL_GIGA_MAC_VER_32] =
 226                 _R("RTL8168e/8111e",    FIRMWARE_8168E_1, JUMBO_9K),
 227         [RTL_GIGA_MAC_VER_33] =
 228                 _R("RTL8168e/8111e",    FIRMWARE_8168E_2, JUMBO_9K),
 229         [RTL_GIGA_MAC_VER_34] =
 230                 _R("RTL8168evl/8111evl", FIRMWARE_8168E_3, JUMBO_9K),
 231         [RTL_GIGA_MAC_VER_35] =
 232                 _R("RTL8168f/8111f",    FIRMWARE_8168F_1, JUMBO_9K),
 233         [RTL_GIGA_MAC_VER_36] =
 234                 _R("RTL8168f/8111f",    FIRMWARE_8168F_2, JUMBO_9K),
 235         [RTL_GIGA_MAC_VER_37] =
 236                 _R("RTL8402",           FIRMWARE_8402_1,  JUMBO_1K),
 237         [RTL_GIGA_MAC_VER_38] =
 238                 _R("RTL8411",           FIRMWARE_8411_1,  JUMBO_9K),
 239         [RTL_GIGA_MAC_VER_39] =
 240                 _R("RTL8106e",          FIRMWARE_8106E_1, JUMBO_1K),
 241         [RTL_GIGA_MAC_VER_40] =
 242                 _R("RTL8168g/8111g",    FIRMWARE_8168G_2, JUMBO_9K),
 243         [RTL_GIGA_MAC_VER_41] =
 244                 _R("RTL8168g/8111g",    NULL, JUMBO_9K),
 245         [RTL_GIGA_MAC_VER_42] =
 246                 _R("RTL8168g/8111g",    FIRMWARE_8168G_3, JUMBO_9K),
 247         [RTL_GIGA_MAC_VER_43] =
 248                 _R("RTL8106e",          FIRMWARE_8106E_2, JUMBO_1K),
 249         [RTL_GIGA_MAC_VER_44] =
 250                 _R("RTL8411",           FIRMWARE_8411_2,  JUMBO_9K),
 251         [RTL_GIGA_MAC_VER_45] =
 252                 _R("RTL8168h/8111h",    FIRMWARE_8168H_1, JUMBO_9K),
 253         [RTL_GIGA_MAC_VER_46] =
 254                 _R("RTL8168h/8111h",    FIRMWARE_8168H_2, JUMBO_9K),
 255         [RTL_GIGA_MAC_VER_47] =
 256                 _R("RTL8107e",          FIRMWARE_8107E_1, JUMBO_1K),
 257         [RTL_GIGA_MAC_VER_48] =
 258                 _R("RTL8107e",          FIRMWARE_8107E_2, JUMBO_1K),
 259         [RTL_GIGA_MAC_VER_49] =
 260                 _R("RTL8168ep/8111ep",  NULL, JUMBO_9K),
 261         [RTL_GIGA_MAC_VER_50] =
 262                 _R("RTL8168ep/8111ep",  NULL, JUMBO_9K),
 263         [RTL_GIGA_MAC_VER_51] =
 264                 _R("RTL8168ep/8111ep",  NULL, JUMBO_9K),
 265 };
 266 #undef _R
 267
 268 enum cfg_version {
 269         RTL_CFG_0 = 0x00,
 270         RTL_CFG_1,
 271         RTL_CFG_2
 272 };
 273
 274 static const struct pci_device_id rtl8169_pci_tbl[] = {
 275         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8129), 0, 0, RTL_CFG_0 },
 276         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8136), 0, 0, RTL_CFG_2 },
 277         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8161), 0, 0, RTL_CFG_1 },
 278         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8167), 0, 0, RTL_CFG_0 },
 279         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8168), 0, 0, RTL_CFG_1 },
 280         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8169), 0, 0, RTL_CFG_0 },
 281         { PCI_VENDOR_ID_DLINK,                  0x4300,
 282                 PCI_VENDOR_ID_DLINK, 0x4b10,             0, 0, RTL_CFG_1 },
 283         { PCI_DEVICE(PCI_VENDOR_ID_DLINK,       0x4300), 0, 0, RTL_CFG_0 },
 284         { PCI_DEVICE(PCI_VENDOR_ID_DLINK,       0x4302), 0, 0, RTL_CFG_0 },
 285         { PCI_DEVICE(PCI_VENDOR_ID_AT,          0xc107), 0, 0, RTL_CFG_0 },
 286         { PCI_DEVICE(0x16ec,                    0x0116), 0, 0, RTL_CFG_0 },
 287         { PCI_VENDOR_ID_LINKSYS,                0x1032,
 288                 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
 289         { 0x0001,                               0x8168,
 290                 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
 291         {0,},
 292 };
 293
 294 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
 295
 296 static int use_dac = -1;
 297 static struct {
 298         u32 msg_enable;
 299 } debug = { -1 };
 300
 301 enum rtl_registers {
 302         MAC0            = 0,    /* Ethernet hardware address. */
 303         MAC4            = 4,
 304         MAR0            = 8,    /* Multicast filter. */
 305         CounterAddrLow          = 0x10,
 306         CounterAddrHigh         = 0x14,
 307         TxDescStartAddrLow      = 0x20,
 308         TxDescStartAddrHigh     = 0x24,
 309         TxHDescStartAddrLow     = 0x28,
 310         TxHDescStartAddrHigh    = 0x2c,
 311         FLASH           = 0x30,
 312         ERSR            = 0x36,
 313         ChipCmd         = 0x37,
 314         TxPoll          = 0x38,
 315         IntrMask        = 0x3c,
 316         IntrStatus      = 0x3e,
 317
 318         TxConfig        = 0x40,
 319 #define TXCFG_AUTO_FIFO                 (1 << 7)        /* 8111e-vl */
 320 #define TXCFG_EMPTY                     (1 << 11)       /* 8111e-vl */
 321
 322         RxConfig        = 0x44,
 323 #define RX128_INT_EN                    (1 << 15)       /* 8111c and later */
 324 #define RX_MULTI_EN                     (1 << 14)       /* 8111c only */
 325 #define RXCFG_FIFO_SHIFT                13
 326                                         /* No threshold before first PCI xfer */
 327 #define RX_FIFO_THRESH                  (7 << RXCFG_FIFO_SHIFT)
 328 #define RX_EARLY_OFF                    (1 << 11)
 329 #define RXCFG_DMA_SHIFT                 8
 330                                         /* Unlimited maximum PCI burst. */
 331 #define RX_DMA_BURST                    (7 << RXCFG_DMA_SHIFT)
 332
 333         RxMissed        = 0x4c,
 334         Cfg9346         = 0x50,
 335         Config0         = 0x51,
 336         Config1         = 0x52,
 337         Config2         = 0x53,
 338 #define PME_SIGNAL                      (1 << 5)        /* 8168c and later */
 339
 340         Config3         = 0x54,
 341         Config4         = 0x55,
 342         Config5         = 0x56,
 343         MultiIntr       = 0x5c,
 344         PHYAR           = 0x60,
 345         PHYstatus       = 0x6c,
 346         RxMaxSize       = 0xda,
 347         CPlusCmd        = 0xe0,
 348         IntrMitigate    = 0xe2,
 349
 350 #define RTL_COALESCE_MASK       0x0f
 351 #define RTL_COALESCE_SHIFT      4
 352 #define RTL_COALESCE_T_MAX      (RTL_COALESCE_MASK)
 353 #define RTL_COALESCE_FRAME_MAX  (RTL_COALESCE_MASK << 2)
 354
 355         RxDescAddrLow   = 0xe4,
 356         RxDescAddrHigh  = 0xe8,
 357         EarlyTxThres    = 0xec, /* 8169. Unit of 32 bytes. */
 358
 359 #define NoEarlyTx       0x3f    /* Max value : no early transmit. */
 360
 361         MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
 362
 363 #define TxPacketMax     (8064 >> 7)
 364 #define EarlySize       0x27
 365
 366         FuncEvent       = 0xf0,
 367         FuncEventMask   = 0xf4,
 368         FuncPresetState = 0xf8,
 369         IBCR0           = 0xf8,
 370         IBCR2           = 0xf9,
 371         IBIMR0          = 0xfa,
 372         IBISR0          = 0xfb,
 373         FuncForceEvent  = 0xfc,
 374 };
 375
 376 enum rtl8168_8101_registers {
 377         CSIDR                   = 0x64,
 378         CSIAR                   = 0x68,
 379 #define CSIAR_FLAG                      0x80000000
 380 #define CSIAR_WRITE_CMD                 0x80000000
 381 #define CSIAR_BYTE_ENABLE               0x0000f000
 382 #define CSIAR_ADDR_MASK                 0x00000fff
 383         PMCH                    = 0x6f,
 384         EPHYAR                  = 0x80,
 385 #define EPHYAR_FLAG                     0x80000000
 386 #define EPHYAR_WRITE_CMD                0x80000000
 387 #define EPHYAR_REG_MASK                 0x1f
 388 #define EPHYAR_REG_SHIFT                16
 389 #define EPHYAR_DATA_MASK                0xffff
 390         DLLPR                   = 0xd0,
 391 #define PFM_EN                          (1 << 6)
 392 #define TX_10M_PS_EN                    (1 << 7)
 393         DBG_REG                 = 0xd1,
 394 #define FIX_NAK_1                       (1 << 4)
 395 #define FIX_NAK_2                       (1 << 3)
 396         TWSI                    = 0xd2,
 397         MCU                     = 0xd3,
 398 #define NOW_IS_OOB                      (1 << 7)
 399 #define TX_EMPTY                        (1 << 5)
 400 #define RX_EMPTY                        (1 << 4)
 401 #define RXTX_EMPTY                      (TX_EMPTY | RX_EMPTY)
 402 #define EN_NDP                          (1 << 3)
 403 #define EN_OOB_RESET                    (1 << 2)
 404 #define LINK_LIST_RDY                   (1 << 1)
 405         EFUSEAR                 = 0xdc,
 406 #define EFUSEAR_FLAG                    0x80000000
 407 #define EFUSEAR_WRITE_CMD               0x80000000
 408 #define EFUSEAR_READ_CMD                0x00000000
 409 #define EFUSEAR_REG_MASK                0x03ff
 410 #define EFUSEAR_REG_SHIFT               8
 411 #define EFUSEAR_DATA_MASK               0xff
 412         MISC_1                  = 0xf2,
 413 #define PFM_D3COLD_EN                   (1 << 6)
 414 };
 415
 416 enum rtl8168_registers {
 417         LED_FREQ                = 0x1a,
 418         EEE_LED                 = 0x1b,
 419         ERIDR                   = 0x70,
 420         ERIAR                   = 0x74,
 421 #define ERIAR_FLAG                      0x80000000
 422 #define ERIAR_WRITE_CMD                 0x80000000
 423 #define ERIAR_READ_CMD                  0x00000000
 424 #define ERIAR_ADDR_BYTE_ALIGN           4
 425 #define ERIAR_TYPE_SHIFT                16
 426 #define ERIAR_EXGMAC                    (0x00 << ERIAR_TYPE_SHIFT)
 427 #define ERIAR_MSIX                      (0x01 << ERIAR_TYPE_SHIFT)
 428 #define ERIAR_ASF                       (0x02 << ERIAR_TYPE_SHIFT)
 429 #define ERIAR_OOB                       (0x02 << ERIAR_TYPE_SHIFT)
 430 #define ERIAR_MASK_SHIFT                12
 431 #define ERIAR_MASK_0001                 (0x1 << ERIAR_MASK_SHIFT)
 432 #define ERIAR_MASK_0011                 (0x3 << ERIAR_MASK_SHIFT)
 433 #define ERIAR_MASK_0100                 (0x4 << ERIAR_MASK_SHIFT)
 434 #define ERIAR_MASK_0101                 (0x5 << ERIAR_MASK_SHIFT)
 435 #define ERIAR_MASK_1111                 (0xf << ERIAR_MASK_SHIFT)
 436         EPHY_RXER_NUM           = 0x7c,
 437         OCPDR                   = 0xb0, /* OCP GPHY access */
 438 #define OCPDR_WRITE_CMD                 0x80000000
 439 #define OCPDR_READ_CMD                  0x00000000
 440 #define OCPDR_REG_MASK                  0x7f
 441 #define OCPDR_GPHY_REG_SHIFT            16
 442 #define OCPDR_DATA_MASK                 0xffff
 443         OCPAR                   = 0xb4,
 444 #define OCPAR_FLAG                      0x80000000
 445 #define OCPAR_GPHY_WRITE_CMD            0x8000f060
 446 #define OCPAR_GPHY_READ_CMD             0x0000f060
 447         GPHY_OCP                = 0xb8,
 448         RDSAR1                  = 0xd0, /* 8168c only. Undocumented on 8168dp */
 449         MISC                    = 0xf0, /* 8168e only. */
 450 #define TXPLA_RST                       (1 << 29)
 451 #define DISABLE_LAN_EN                  (1 << 23) /* Enable GPIO pin */
 452 #define PWM_EN                          (1 << 22)
 453 #define RXDV_GATED_EN                   (1 << 19)
 454 #define EARLY_TALLY_EN                  (1 << 16)
 455 };
 456
 457 enum rtl_register_content {
 458         /* InterruptStatusBits */
 459         SYSErr          = 0x8000,
 460         PCSTimeout      = 0x4000,
 461         SWInt           = 0x0100,
 462         TxDescUnavail   = 0x0080,
 463         RxFIFOOver      = 0x0040,
 464         LinkChg         = 0x0020,
 465         RxOverflow      = 0x0010,
 466         TxErr           = 0x0008,
 467         TxOK            = 0x0004,
 468         RxErr           = 0x0002,
 469         RxOK            = 0x0001,
 470
 471         /* RxStatusDesc */
 472         RxBOVF  = (1 << 24),
 473         RxFOVF  = (1 << 23),
 474         RxRWT   = (1 << 22),
 475         RxRES   = (1 << 21),
 476         RxRUNT  = (1 << 20),
 477         RxCRC   = (1 << 19),
 478
 479         /* ChipCmdBits */
 480         StopReq         = 0x80,
 481         CmdReset        = 0x10,
 482         CmdRxEnb        = 0x08,
 483         CmdTxEnb        = 0x04,
 484         RxBufEmpty      = 0x01,
 485
 486         /* TXPoll register p.5 */
 487         HPQ             = 0x80,         /* Poll cmd on the high prio queue */
 488         NPQ             = 0x40,         /* Poll cmd on the low prio queue */
 489         FSWInt          = 0x01,         /* Forced software interrupt */
 490
 491         /* Cfg9346Bits */
 492         Cfg9346_Lock    = 0x00,
 493         Cfg9346_Unlock  = 0xc0,
 494
 495         /* rx_mode_bits */
 496         AcceptErr       = 0x20,
 497         AcceptRunt      = 0x10,
 498         AcceptBroadcast = 0x08,
 499         AcceptMulticast = 0x04,
 500         AcceptMyPhys    = 0x02,
 501         AcceptAllPhys   = 0x01,
 502 #define RX_CONFIG_ACCEPT_MASK           0x3f
 503
 504         /* TxConfigBits */
 505         TxInterFrameGapShift = 24,
 506         TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
 507
 508         /* Config1 register p.24 */
 509         LEDS1           = (1 << 7),
 510         LEDS0           = (1 << 6),
 511         Speed_down      = (1 << 4),
 512         MEMMAP          = (1 << 3),
 513         IOMAP           = (1 << 2),
 514         VPD             = (1 << 1),
 515         PMEnable        = (1 << 0),     /* Power Management Enable */
 516
 517         /* Config2 register p. 25 */
 518         ClkReqEn        = (1 << 7),     /* Clock Request Enable */
 519         MSIEnable       = (1 << 5),     /* 8169 only. Reserved in the 8168. */
 520         PCI_Clock_66MHz = 0x01,
 521         PCI_Clock_33MHz = 0x00,
 522
 523         /* Config3 register p.25 */
 524         MagicPacket     = (1 << 5),     /* Wake up when receives a Magic Packet */
 525         LinkUp          = (1 << 4),     /* Wake up when the cable connection is re-established */
 526         Jumbo_En0       = (1 << 2),     /* 8168 only. Reserved in the 8168b */
 527         Rdy_to_L23      = (1 << 1),     /* L23 Enable */
 528         Beacon_en       = (1 << 0),     /* 8168 only. Reserved in the 8168b */
 529
 530         /* Config4 register */
 531         Jumbo_En1       = (1 << 1),     /* 8168 only. Reserved in the 8168b */
 532
 533         /* Config5 register p.27 */
 534         BWF             = (1 << 6),     /* Accept Broadcast wakeup frame */
 535         MWF             = (1 << 5),     /* Accept Multicast wakeup frame */
 536         UWF             = (1 << 4),     /* Accept Unicast wakeup frame */
 537         Spi_en          = (1 << 3),
 538         LanWake         = (1 << 1),     /* LanWake enable/disable */
 539         PMEStatus       = (1 << 0),     /* PME status can be reset by PCI RST# */
 540         ASPM_en         = (1 << 0),     /* ASPM enable */
 541
 542         /* CPlusCmd p.31 */
 543         EnableBist      = (1 << 15),    // 8168 8101
 544         Mac_dbgo_oe     = (1 << 14),    // 8168 8101
 545         Normal_mode     = (1 << 13),    // unused
 546         Force_half_dup  = (1 << 12),    // 8168 8101
 547         Force_rxflow_en = (1 << 11),    // 8168 8101
 548         Force_txflow_en = (1 << 10),    // 8168 8101
 549         Cxpl_dbg_sel    = (1 << 9),     // 8168 8101
 550         ASF             = (1 << 8),     // 8168 8101
 551         PktCntrDisable  = (1 << 7),     // 8168 8101
 552         Mac_dbgo_sel    = 0x001c,       // 8168
 553         RxVlan          = (1 << 6),
 554         RxChkSum        = (1 << 5),
 555         PCIDAC          = (1 << 4),
 556         PCIMulRW        = (1 << 3),
 557 #define INTT_MASK       GENMASK(1, 0)
 558         INTT_0          = 0x0000,       // 8168
 559         INTT_1          = 0x0001,       // 8168
 560         INTT_2          = 0x0002,       // 8168
 561         INTT_3          = 0x0003,       // 8168
 562
 563         /* rtl8169_PHYstatus */
 564         TBI_Enable      = 0x80,
 565         TxFlowCtrl      = 0x40,
 566         RxFlowCtrl      = 0x20,
 567         _1000bpsF       = 0x10,
 568         _100bps         = 0x08,
 569         _10bps          = 0x04,
 570         LinkStatus      = 0x02,
 571         FullDup         = 0x01,
 572
 573         /* _TBICSRBit */
 574         TBILinkOK       = 0x02000000,
 575
 576         /* ResetCounterCommand */
 577         CounterReset    = 0x1,
 578
 579         /* DumpCounterCommand */
 580         CounterDump     = 0x8,
 581
 582         /* magic enable v2 */
 583         MagicPacket_v2  = (1 << 16),    /* Wake up when receives a Magic Packet */
 584 };
 585
 586 enum rtl_desc_bit {
 587         /* First doubleword. */
 588         DescOwn         = (1 << 31), /* Descriptor is owned by NIC */
 589         RingEnd         = (1 << 30), /* End of descriptor ring */
 590         FirstFrag       = (1 << 29), /* First segment of a packet */
 591         LastFrag        = (1 << 28), /* Final segment of a packet */
 592 };
 593
 594 /* Generic case. */
 595 enum rtl_tx_desc_bit {
 596         /* First doubleword. */
 597         TD_LSO          = (1 << 27),            /* Large Send Offload */
 598 #define TD_MSS_MAX                      0x07ffu /* MSS value */
 599
 600         /* Second doubleword. */
 601         TxVlanTag       = (1 << 17),            /* Add VLAN tag */
 602 };
 603
 604 /* 8169, 8168b and 810x except 8102e. */
 605 enum rtl_tx_desc_bit_0 {
 606         /* First doubleword. */
 607 #define TD0_MSS_SHIFT                   16      /* MSS position (11 bits) */
 608         TD0_TCP_CS      = (1 << 16),            /* Calculate TCP/IP checksum */
 609         TD0_UDP_CS      = (1 << 17),            /* Calculate UDP/IP checksum */
 610         TD0_IP_CS       = (1 << 18),            /* Calculate IP checksum */
 611 };
 612
 613 /* 8102e, 8168c and beyond. */
 614 enum rtl_tx_desc_bit_1 {
 615         /* First doubleword. */
 616         TD1_GTSENV4     = (1 << 26),            /* Giant Send for IPv4 */
 617         TD1_GTSENV6     = (1 << 25),            /* Giant Send for IPv6 */
 618 #define GTTCPHO_SHIFT                   18
 619 #define GTTCPHO_MAX                     0x7fU
 620
 621         /* Second doubleword. */
 622 #define TCPHO_SHIFT                     18
 623 #define TCPHO_MAX                       0x3ffU
 624 #define TD1_MSS_SHIFT                   18      /* MSS position (11 bits) */
 625         TD1_IPv6_CS     = (1 << 28),            /* Calculate IPv6 checksum */
 626         TD1_IPv4_CS     = (1 << 29),            /* Calculate IPv4 checksum */
 627         TD1_TCP_CS      = (1 << 30),            /* Calculate TCP/IP checksum */
 628         TD1_UDP_CS      = (1 << 31),            /* Calculate UDP/IP checksum */
 629 };
 630
 631 enum rtl_rx_desc_bit {
 632         /* Rx private */
 633         PID1            = (1 << 18), /* Protocol ID bit 1/2 */
 634         PID0            = (1 << 17), /* Protocol ID bit 0/2 */
 635
 636 #define RxProtoUDP      (PID1)
 637 #define RxProtoTCP      (PID0)
 638 #define RxProtoIP       (PID1 | PID0)
 639 #define RxProtoMask     RxProtoIP
 640
 641         IPFail          = (1 << 16), /* IP checksum failed */
 642         UDPFail         = (1 << 15), /* UDP/IP checksum failed */
 643         TCPFail         = (1 << 14), /* TCP/IP checksum failed */
 644         RxVlanTag       = (1 << 16), /* VLAN tag available */
 645 };
 646
 647 #define RsvdMask        0x3fffc000
 648 #define CPCMD_QUIRK_MASK        (Normal_mode | RxVlan | RxChkSum | INTT_MASK)
 649
 650 struct TxDesc {
 651         __le32 opts1;
 652         __le32 opts2;
 653         __le64 addr;
 654 };
 655
 656 struct RxDesc {
 657         __le32 opts1;
 658         __le32 opts2;
 659         __le64 addr;
 660 };
 661
 662 struct ring_info {
 663         struct sk_buff  *skb;
 664         u32             len;
 665         u8              __pad[sizeof(void *) - sizeof(u32)];
 666 };
 667
 668 struct rtl8169_counters {
 669         __le64  tx_packets;
 670         __le64  rx_packets;
 671         __le64  tx_errors;
 672         __le32  rx_errors;
 673         __le16  rx_missed;
 674         __le16  align_errors;
 675         __le32  tx_one_collision;
 676         __le32  tx_multi_collision;
 677         __le64  rx_unicast;
 678         __le64  rx_broadcast;
 679         __le32  rx_multicast;
 680         __le16  tx_aborted;
 681         __le16  tx_underun;
 682 };
 683
 684 struct rtl8169_tc_offsets {
 685         bool    inited;
 686         __le64  tx_errors;
 687         __le32  tx_multi_collision;
 688         __le16  tx_aborted;
 689 };
 690
 691 enum rtl_flag {
 692         RTL_FLAG_TASK_ENABLED,
 693         RTL_FLAG_TASK_SLOW_PENDING,
 694         RTL_FLAG_TASK_RESET_PENDING,
 695         RTL_FLAG_MAX
 696 };
 697
 698 struct rtl8169_stats {
 699         u64                     packets;
 700         u64                     bytes;
 701         struct u64_stats_sync   syncp;
 702 };
 703
 704 struct rtl8169_private {
 705         void __iomem *mmio_addr;        /* memory map physical address */
 706         struct pci_dev *pci_dev;
 707         struct net_device *dev;
 708         struct napi_struct napi;
 709         u32 msg_enable;
 710         u16 mac_version;
 711         u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
 712         u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
 713         u32 dirty_tx;
 714         struct rtl8169_stats rx_stats;
 715         struct rtl8169_stats tx_stats;
 716         struct TxDesc *TxDescArray;     /* 256-aligned Tx descriptor ring */
 717         struct RxDesc *RxDescArray;     /* 256-aligned Rx descriptor ring */
 718         dma_addr_t TxPhyAddr;
 719         dma_addr_t RxPhyAddr;
 720         void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
 721         struct ring_info tx_skb[NUM_TX_DESC];   /* Tx data buffers */
 722         u16 cp_cmd;
 723
 724         u16 event_slow;
 725         const struct rtl_coalesce_info *coalesce_info;
 726
 727         struct mdio_ops {
 728                 void (*write)(struct rtl8169_private *, int, int);
 729                 int (*read)(struct rtl8169_private *, int);
 730         } mdio_ops;
 731
 732         struct jumbo_ops {
 733                 void (*enable)(struct rtl8169_private *);
 734                 void (*disable)(struct rtl8169_private *);
 735         } jumbo_ops;
 736
 737         void (*hw_start)(struct rtl8169_private *tp);
 738         bool (*tso_csum)(struct rtl8169_private *, struct sk_buff *, u32 *);
 739
 740         struct {
 741                 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
 742                 struct mutex mutex;
 743                 struct work_struct work;
 744         } wk;
 745
 746         unsigned supports_gmii:1;
 747         struct mii_bus *mii_bus;
 748         dma_addr_t counters_phys_addr;
 749         struct rtl8169_counters *counters;
 750         struct rtl8169_tc_offsets tc_offset;
 751         u32 saved_wolopts;
 752
 753         struct rtl_fw {
 754                 const struct firmware *fw;
 755
 756 #define RTL_VER_SIZE            32
 757
 758                 char version[RTL_VER_SIZE];
 759
 760                 struct rtl_fw_phy_action {
 761                         __le32 *code;
 762                         size_t size;
 763                 } phy_action;
 764         } *rtl_fw;
 765 #define RTL_FIRMWARE_UNKNOWN    ERR_PTR(-EAGAIN)
 766
 767         u32 ocp_base;
 768 };
 769
 770 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
 771 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
 772 module_param(use_dac, int, 0);
 773 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
 774 module_param_named(debug, debug.msg_enable, int, 0);
 775 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
 776 MODULE_LICENSE("GPL");
 777 MODULE_FIRMWARE(FIRMWARE_8168D_1);
 778 MODULE_FIRMWARE(FIRMWARE_8168D_2);
 779 MODULE_FIRMWARE(FIRMWARE_8168E_1);
 780 MODULE_FIRMWARE(FIRMWARE_8168E_2);
 781 MODULE_FIRMWARE(FIRMWARE_8168E_3);
 782 MODULE_FIRMWARE(FIRMWARE_8105E_1);
 783 MODULE_FIRMWARE(FIRMWARE_8168F_1);
 784 MODULE_FIRMWARE(FIRMWARE_8168F_2);
 785 MODULE_FIRMWARE(FIRMWARE_8402_1);
 786 MODULE_FIRMWARE(FIRMWARE_8411_1);
 787 MODULE_FIRMWARE(FIRMWARE_8411_2);
 788 MODULE_FIRMWARE(FIRMWARE_8106E_1);
 789 MODULE_FIRMWARE(FIRMWARE_8106E_2);
 790 MODULE_FIRMWARE(FIRMWARE_8168G_2);
 791 MODULE_FIRMWARE(FIRMWARE_8168G_3);
 792 MODULE_FIRMWARE(FIRMWARE_8168H_1);
 793 MODULE_FIRMWARE(FIRMWARE_8168H_2);
 794 MODULE_FIRMWARE(FIRMWARE_8107E_1);
 795 MODULE_FIRMWARE(FIRMWARE_8107E_2);
 796
 797 static inline struct device *tp_to_dev(struct rtl8169_private *tp)
 798 {
 799         return &tp->pci_dev->dev;
 800 }
 801
 802 static void rtl_lock_work(struct rtl8169_private *tp)
 803 {
 804         mutex_lock(&tp->wk.mutex);
 805 }
 806
 807 static void rtl_unlock_work(struct rtl8169_private *tp)
 808 {
 809         mutex_unlock(&tp->wk.mutex);
 810 }
 811
 812 static void rtl_tx_performance_tweak(struct rtl8169_private *tp, u16 force)
 813 {
 814         pcie_capability_clear_and_set_word(tp->pci_dev, PCI_EXP_DEVCTL,
 815                                            PCI_EXP_DEVCTL_READRQ, force);
 816 }
 817
 818 struct rtl_cond {
 819         bool (*check)(struct rtl8169_private *);
 820         const char *msg;
 821 };
 822
 823 static void rtl_udelay(unsigned int d)
 824 {
 825         udelay(d);
 826 }
 827
 828 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,
 829                           void (*delay)(unsigned int), unsigned int d, int n,
 830                           bool high)
 831 {
 832         int i;
 833
 834         for (i = 0; i < n; i++) {
 835                 delay(d);
 836                 if (c->check(tp) == high)
 837                         return true;
 838         }
 839         netif_err(tp, drv, tp->dev, "%s == %d (loop: %d, delay: %d).\n",
 840                   c->msg, !high, n, d);
 841         return false;
 842 }
 843
 844 static bool rtl_udelay_loop_wait_high(struct rtl8169_private *tp,
 845                                       const struct rtl_cond *c,
 846                                       unsigned int d, int n)
 847 {
 848         return rtl_loop_wait(tp, c, rtl_udelay, d, n, true);
 849 }
 850
 851 static bool rtl_udelay_loop_wait_low(struct rtl8169_private *tp,
 852                                      const struct rtl_cond *c,
 853                                      unsigned int d, int n)
 854 {
 855         return rtl_loop_wait(tp, c, rtl_udelay, d, n, false);
 856 }
 857
 858 static bool rtl_msleep_loop_wait_high(struct rtl8169_private *tp,
 859                                       const struct rtl_cond *c,
 860                                       unsigned int d, int n)
 861 {
 862         return rtl_loop_wait(tp, c, msleep, d, n, true);
 863 }
 864
 865 static bool rtl_msleep_loop_wait_low(struct rtl8169_private *tp,
 866                                      const struct rtl_cond *c,
 867                                      unsigned int d, int n)
 868 {
 869         return rtl_loop_wait(tp, c, msleep, d, n, false);
 870 }
 871
 872 #define DECLARE_RTL_COND(name)                          \
 873 static bool name ## _check(struct rtl8169_private *);   \
 874                                                         \
 875 static const struct rtl_cond name = {                   \
 876         .check  = name ## _check,                       \
 877         .msg    = #name                                 \
 878 };                                                      \
 879                                                         \
 880 static bool name ## _check(struct rtl8169_private *tp)
 881
 882 static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg)
 883 {
 884         if (reg & 0xffff0001) {
 885                 netif_err(tp, drv, tp->dev, "Invalid ocp reg %x!\n", reg);
 886                 return true;
 887         }
 888         return false;
 889 }
 890
 891 DECLARE_RTL_COND(rtl_ocp_gphy_cond)
 892 {
 893         return RTL_R32(tp, GPHY_OCP) & OCPAR_FLAG;
 894 }
 895
 896 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
 897 {
 898         if (rtl_ocp_reg_failure(tp, reg))
 899                 return;
 900
 901         RTL_W32(tp, GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);
 902
 903         rtl_udelay_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);
 904 }
 905
 906 static u16 r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
 907 {
 908         if (rtl_ocp_reg_failure(tp, reg))
 909                 return 0;
 910
 911         RTL_W32(tp, GPHY_OCP, reg << 15);
 912
 913         return rtl_udelay_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?
 914                 (RTL_R32(tp, GPHY_OCP) & 0xffff) : ~0;
 915 }
 916
 917 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
 918 {
 919         if (rtl_ocp_reg_failure(tp, reg))
 920                 return;
 921
 922         RTL_W32(tp, OCPDR, OCPAR_FLAG | (reg << 15) | data);
 923 }
 924
 925 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
 926 {
 927         if (rtl_ocp_reg_failure(tp, reg))
 928                 return 0;
 929
 930         RTL_W32(tp, OCPDR, reg << 15);
 931
 932         return RTL_R32(tp, OCPDR);
 933 }
 934
 935 #define OCP_STD_PHY_BASE        0xa400
 936
 937 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)
 938 {
 939         if (reg == 0x1f) {
 940                 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;
 941                 return;
 942         }
 943
 944         if (tp->ocp_base != OCP_STD_PHY_BASE)
 945                 reg -= 0x10;
 946
 947         r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);
 948 }
 949
 950 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)
 951 {
 952         if (tp->ocp_base != OCP_STD_PHY_BASE)
 953                 reg -= 0x10;
 954
 955         return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);
 956 }
 957
 958 static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value)
 959 {
 960         if (reg == 0x1f) {
 961                 tp->ocp_base = value << 4;
 962                 return;
 963         }
 964
 965         r8168_mac_ocp_write(tp, tp->ocp_base + reg, value);
 966 }
 967
 968 static int mac_mcu_read(struct rtl8169_private *tp, int reg)
 969 {
 970         return r8168_mac_ocp_read(tp, tp->ocp_base + reg);
 971 }
 972
 973 DECLARE_RTL_COND(rtl_phyar_cond)
 974 {
 975         return RTL_R32(tp, PHYAR) & 0x80000000;
 976 }
 977
 978 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)
 979 {
 980         RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
 981
 982         rtl_udelay_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);
 983         /*
 984          * According to hardware specs a 20us delay is required after write
 985          * complete indication, but before sending next command.
 986          */
 987         udelay(20);
 988 }
 989
 990 static int r8169_mdio_read(struct rtl8169_private *tp, int reg)
 991 {
 992         int value;
 993
 994         RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16);
 995
 996         value = rtl_udelay_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?
 997                 RTL_R32(tp, PHYAR) & 0xffff : ~0;
 998
 999         /*
1000          * According to hardware specs a 20us delay is required after read
1001          * complete indication, but before sending next command.
1002          */
1003         udelay(20);
1004
1005         return value;
1006 }
1007
1008 DECLARE_RTL_COND(rtl_ocpar_cond)
1009 {
1010         return RTL_R32(tp, OCPAR) & OCPAR_FLAG;
1011 }
1012
1013 static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data)
1014 {
1015         RTL_W32(tp, OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
1016         RTL_W32(tp, OCPAR, OCPAR_GPHY_WRITE_CMD);
1017         RTL_W32(tp, EPHY_RXER_NUM, 0);
1018
1019         rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100);
1020 }
1021
1022 static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value)
1023 {
1024         r8168dp_1_mdio_access(tp, reg,
1025                               OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK));
1026 }
1027
1028 static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg)
1029 {
1030         r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD);
1031
1032         mdelay(1);
1033         RTL_W32(tp, OCPAR, OCPAR_GPHY_READ_CMD);
1034         RTL_W32(tp, EPHY_RXER_NUM, 0);
1035
1036         return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ?
1037                 RTL_R32(tp, OCPDR) & OCPDR_DATA_MASK : ~0;
1038 }
1039
1040 #define R8168DP_1_MDIO_ACCESS_BIT       0x00020000
1041
1042 static void r8168dp_2_mdio_start(struct rtl8169_private *tp)
1043 {
1044         RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
1045 }
1046
1047 static void r8168dp_2_mdio_stop(struct rtl8169_private *tp)
1048 {
1049         RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
1050 }
1051
1052 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)
1053 {
1054         r8168dp_2_mdio_start(tp);
1055
1056         r8169_mdio_write(tp, reg, value);
1057
1058         r8168dp_2_mdio_stop(tp);
1059 }
1060
1061 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)
1062 {
1063         int value;
1064
1065         r8168dp_2_mdio_start(tp);
1066
1067         value = r8169_mdio_read(tp, reg);
1068
1069         r8168dp_2_mdio_stop(tp);
1070
1071         return value;
1072 }
1073
1074 static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
1075 {
1076         tp->mdio_ops.write(tp, location, val);
1077 }
1078
1079 static int rtl_readphy(struct rtl8169_private *tp, int location)
1080 {
1081         return tp->mdio_ops.read(tp, location);
1082 }
1083
1084 static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
1085 {
1086         rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
1087 }
1088
1089 static void rtl_w0w1_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
1090 {
1091         int val;
1092
1093         val = rtl_readphy(tp, reg_addr);
1094         rtl_writephy(tp, reg_addr, (val & ~m) | p);
1095 }
1096
1097 DECLARE_RTL_COND(rtl_ephyar_cond)
1098 {
1099         return RTL_R32(tp, EPHYAR) & EPHYAR_FLAG;
1100 }
1101
1102 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)
1103 {
1104         RTL_W32(tp, EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1105                 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1106
1107         rtl_udelay_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);
1108
1109         udelay(10);
1110 }
1111
1112 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)
1113 {
1114         RTL_W32(tp, EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1115
1116         return rtl_udelay_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?
1117                 RTL_R32(tp, EPHYAR) & EPHYAR_DATA_MASK : ~0;
1118 }
1119
1120 DECLARE_RTL_COND(rtl_eriar_cond)
1121 {
1122         return RTL_R32(tp, ERIAR) & ERIAR_FLAG;
1123 }
1124
1125 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1126                           u32 val, int type)
1127 {
1128         BUG_ON((addr & 3) || (mask == 0));
1129         RTL_W32(tp, ERIDR, val);
1130         RTL_W32(tp, ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
1131
1132         rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);
1133 }
1134
1135 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
1136 {
1137         RTL_W32(tp, ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
1138
1139         return rtl_udelay_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?
1140                 RTL_R32(tp, ERIDR) : ~0;
1141 }
1142
1143 static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 mask, u32 p,
1144                          u32 m, int type)
1145 {
1146         u32 val;
1147
1148         val = rtl_eri_read(tp, addr, type);
1149         rtl_eri_write(tp, addr, mask, (val & ~m) | p, type);
1150 }
1151
1152 static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1153 {
1154         RTL_W32(tp, OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1155         return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?
1156                 RTL_R32(tp, OCPDR) : ~0;
1157 }
1158
1159 static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1160 {
1161         return rtl_eri_read(tp, reg, ERIAR_OOB);
1162 }
1163
1164 static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1165 {
1166         switch (tp->mac_version) {
1167         case RTL_GIGA_MAC_VER_27:
1168         case RTL_GIGA_MAC_VER_28:
1169         case RTL_GIGA_MAC_VER_31:
1170                 return r8168dp_ocp_read(tp, mask, reg);
1171         case RTL_GIGA_MAC_VER_49:
1172         case RTL_GIGA_MAC_VER_50:
1173         case RTL_GIGA_MAC_VER_51:
1174                 return r8168ep_ocp_read(tp, mask, reg);
1175         default:
1176                 BUG();
1177                 return ~0;
1178         }
1179 }
1180
1181 static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1182                               u32 data)
1183 {
1184         RTL_W32(tp, OCPDR, data);
1185         RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1186         rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);
1187 }
1188
1189 static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1190                               u32 data)
1191 {
1192         rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT,
1193                       data, ERIAR_OOB);
1194 }
1195
1196 static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
1197 {
1198         switch (tp->mac_version) {
1199         case RTL_GIGA_MAC_VER_27:
1200         case RTL_GIGA_MAC_VER_28:
1201         case RTL_GIGA_MAC_VER_31:
1202                 r8168dp_ocp_write(tp, mask, reg, data);
1203                 break;
1204         case RTL_GIGA_MAC_VER_49:
1205         case RTL_GIGA_MAC_VER_50:
1206         case RTL_GIGA_MAC_VER_51:
1207                 r8168ep_ocp_write(tp, mask, reg, data);
1208                 break;
1209         default:
1210                 BUG();
1211                 break;
1212         }
1213 }
1214
1215 static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
1216 {
1217         rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd, ERIAR_EXGMAC);
1218
1219         ocp_write(tp, 0x1, 0x30, 0x00000001);
1220 }
1221
1222 #define OOB_CMD_RESET           0x00
1223 #define OOB_CMD_DRIVER_START    0x05
1224 #define OOB_CMD_DRIVER_STOP     0x06
1225
1226 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
1227 {
1228         return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
1229 }
1230
1231 DECLARE_RTL_COND(rtl_ocp_read_cond)
1232 {
1233         u16 reg;
1234
1235         reg = rtl8168_get_ocp_reg(tp);
1236
1237         return ocp_read(tp, 0x0f, reg) & 0x00000800;
1238 }
1239
1240 DECLARE_RTL_COND(rtl_ep_ocp_read_cond)
1241 {
1242         return ocp_read(tp, 0x0f, 0x124) & 0x00000001;
1243 }
1244
1245 DECLARE_RTL_COND(rtl_ocp_tx_cond)
1246 {
1247         return RTL_R8(tp, IBISR0) & 0x20;
1248 }
1249
1250 static void rtl8168ep_stop_cmac(struct rtl8169_private *tp)
1251 {
1252         RTL_W8(tp, IBCR2, RTL_R8(tp, IBCR2) & ~0x01);
1253         rtl_msleep_loop_wait_high(tp, &rtl_ocp_tx_cond, 50, 2000);
1254         RTL_W8(tp, IBISR0, RTL_R8(tp, IBISR0) | 0x20);
1255         RTL_W8(tp, IBCR0, RTL_R8(tp, IBCR0) & ~0x01);
1256 }
1257
1258 static void rtl8168dp_driver_start(struct rtl8169_private *tp)
1259 {
1260         rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
1261         rtl_msleep_loop_wait_high(tp, &rtl_ocp_read_cond, 10, 10);
1262 }
1263
1264 static void rtl8168ep_driver_start(struct rtl8169_private *tp)
1265 {
1266         ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START);
1267         ocp_write(tp, 0x01, 0x30, ocp_read(tp, 0x01, 0x30) | 0x01);
1268         rtl_msleep_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10, 10);
1269 }
1270
1271 static void rtl8168_driver_start(struct rtl8169_private *tp)
1272 {
1273         switch (tp->mac_version) {
1274         case RTL_GIGA_MAC_VER_27:
1275         case RTL_GIGA_MAC_VER_28:
1276         case RTL_GIGA_MAC_VER_31:
1277                 rtl8168dp_driver_start(tp);
1278                 break;
1279         case RTL_GIGA_MAC_VER_49:
1280         case RTL_GIGA_MAC_VER_50:
1281         case RTL_GIGA_MAC_VER_51:
1282                 rtl8168ep_driver_start(tp);
1283                 break;
1284         default:
1285                 BUG();
1286                 break;
1287         }
1288 }
1289
1290 static void rtl8168dp_driver_stop(struct rtl8169_private *tp)
1291 {
1292         rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
1293         rtl_msleep_loop_wait_low(tp, &rtl_ocp_read_cond, 10, 10);
1294 }
1295
1296 static void rtl8168ep_driver_stop(struct rtl8169_private *tp)
1297 {
1298         rtl8168ep_stop_cmac(tp);
1299         ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP);
1300         ocp_write(tp, 0x01, 0x30, ocp_read(tp, 0x01, 0x30) | 0x01);
1301         rtl_msleep_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10, 10);
1302 }
1303
1304 static void rtl8168_driver_stop(struct rtl8169_private *tp)
1305 {
1306         switch (tp->mac_version) {
1307         case RTL_GIGA_MAC_VER_27:
1308         case RTL_GIGA_MAC_VER_28:
1309         case RTL_GIGA_MAC_VER_31:
1310                 rtl8168dp_driver_stop(tp);
1311                 break;
1312         case RTL_GIGA_MAC_VER_49:
1313         case RTL_GIGA_MAC_VER_50:
1314         case RTL_GIGA_MAC_VER_51:
1315                 rtl8168ep_driver_stop(tp);
1316                 break;
1317         default:
1318                 BUG();
1319                 break;
1320         }
1321 }
1322
1323 static bool r8168dp_check_dash(struct rtl8169_private *tp)
1324 {
1325         u16 reg = rtl8168_get_ocp_reg(tp);
1326
1327         return !!(ocp_read(tp, 0x0f, reg) & 0x00008000);
1328 }
1329
1330 static bool r8168ep_check_dash(struct rtl8169_private *tp)
1331 {
1332         return !!(ocp_read(tp, 0x0f, 0x128) & 0x00000001);
1333 }
1334
1335 static bool r8168_check_dash(struct rtl8169_private *tp)
1336 {
1337         switch (tp->mac_version) {
1338         case RTL_GIGA_MAC_VER_27:
1339         case RTL_GIGA_MAC_VER_28:
1340         case RTL_GIGA_MAC_VER_31:
1341                 return r8168dp_check_dash(tp);
1342         case RTL_GIGA_MAC_VER_49:
1343         case RTL_GIGA_MAC_VER_50:
1344         case RTL_GIGA_MAC_VER_51:
1345                 return r8168ep_check_dash(tp);
1346         default:
1347                 return false;
1348         }
1349 }
1350
1351 struct exgmac_reg {
1352         u16 addr;
1353         u16 mask;
1354         u32 val;
1355 };
1356
1357 static void rtl_write_exgmac_batch(struct rtl8169_private *tp,
1358                                    const struct exgmac_reg *r, int len)
1359 {
1360         while (len-- > 0) {
1361                 rtl_eri_write(tp, r->addr, r->mask, r->val, ERIAR_EXGMAC);
1362                 r++;
1363         }
1364 }
1365
1366 DECLARE_RTL_COND(rtl_efusear_cond)
1367 {
1368         return RTL_R32(tp, EFUSEAR) & EFUSEAR_FLAG;
1369 }
1370
1371 static u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)
1372 {
1373         RTL_W32(tp, EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1374
1375         return rtl_udelay_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?
1376                 RTL_R32(tp, EFUSEAR) & EFUSEAR_DATA_MASK : ~0;
1377 }
1378
1379 static u16 rtl_get_events(struct rtl8169_private *tp)
1380 {
1381         return RTL_R16(tp, IntrStatus);
1382 }
1383
1384 static void rtl_ack_events(struct rtl8169_private *tp, u16 bits)
1385 {
1386         RTL_W16(tp, IntrStatus, bits);
1387         mmiowb();
1388 }
1389
1390 static void rtl_irq_disable(struct rtl8169_private *tp)
1391 {
1392         RTL_W16(tp, IntrMask, 0);
1393         mmiowb();
1394 }
1395
1396 static void rtl_irq_enable(struct rtl8169_private *tp, u16 bits)
1397 {
1398         RTL_W16(tp, IntrMask, bits);
1399 }
1400
1401 #define RTL_EVENT_NAPI_RX       (RxOK | RxErr)
1402 #define RTL_EVENT_NAPI_TX       (TxOK | TxErr)
1403 #define RTL_EVENT_NAPI          (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX)
1404
1405 static void rtl_irq_enable_all(struct rtl8169_private *tp)
1406 {
1407         rtl_irq_enable(tp, RTL_EVENT_NAPI | tp->event_slow);
1408 }
1409
1410 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1411 {
1412         rtl_irq_disable(tp);
1413         rtl_ack_events(tp, RTL_EVENT_NAPI | tp->event_slow);
1414         RTL_R8(tp, ChipCmd);
1415 }
1416
1417 static void rtl_link_chg_patch(struct rtl8169_private *tp)
1418 {
1419         struct net_device *dev = tp->dev;
1420         struct phy_device *phydev = dev->phydev;
1421
1422         if (!netif_running(dev))
1423                 return;
1424
1425         if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
1426             tp->mac_version == RTL_GIGA_MAC_VER_38) {
1427                 if (phydev->speed == SPEED_1000) {
1428                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1429                                       ERIAR_EXGMAC);
1430                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1431                                       ERIAR_EXGMAC);
1432                 } else if (phydev->speed == SPEED_100) {
1433                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1434                                       ERIAR_EXGMAC);
1435                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1436                                       ERIAR_EXGMAC);
1437                 } else {
1438                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1439                                       ERIAR_EXGMAC);
1440                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1441                                       ERIAR_EXGMAC);
1442                 }
1443                 /* Reset packet filter */
1444                 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01,
1445                              ERIAR_EXGMAC);
1446                 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00,
1447                              ERIAR_EXGMAC);
1448         } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1449                    tp->mac_version == RTL_GIGA_MAC_VER_36) {
1450                 if (phydev->speed == SPEED_1000) {
1451                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1452                                       ERIAR_EXGMAC);
1453                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1454                                       ERIAR_EXGMAC);
1455                 } else {
1456                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1457                                       ERIAR_EXGMAC);
1458                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1459                                       ERIAR_EXGMAC);
1460                 }
1461         } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
1462                 if (phydev->speed == SPEED_10) {
1463                         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02,
1464                                       ERIAR_EXGMAC);
1465                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060,
1466                                       ERIAR_EXGMAC);
1467                 } else {
1468                         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000,
1469                                       ERIAR_EXGMAC);
1470                 }
1471         }
1472 }
1473
1474 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1475
1476 static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
1477 {
1478         u8 options;
1479         u32 wolopts = 0;
1480
1481         options = RTL_R8(tp, Config1);
1482         if (!(options & PMEnable))
1483                 return 0;
1484
1485         options = RTL_R8(tp, Config3);
1486         if (options & LinkUp)
1487                 wolopts |= WAKE_PHY;
1488         switch (tp->mac_version) {
1489         case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
1490         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
1491                 if (rtl_eri_read(tp, 0xdc, ERIAR_EXGMAC) & MagicPacket_v2)
1492                         wolopts |= WAKE_MAGIC;
1493                 break;
1494         default:
1495                 if (options & MagicPacket)
1496                         wolopts |= WAKE_MAGIC;
1497                 break;
1498         }
1499
1500         options = RTL_R8(tp, Config5);
1501         if (options & UWF)
1502                 wolopts |= WAKE_UCAST;
1503         if (options & BWF)
1504                 wolopts |= WAKE_BCAST;
1505         if (options & MWF)
1506                 wolopts |= WAKE_MCAST;
1507
1508         return wolopts;
1509 }
1510
1511 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1512 {
1513         struct rtl8169_private *tp = netdev_priv(dev);
1514
1515         rtl_lock_work(tp);
1516         wol->supported = WAKE_ANY;
1517         wol->wolopts = tp->saved_wolopts;
1518         rtl_unlock_work(tp);
1519 }
1520
1521 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1522 {
1523         unsigned int i, tmp;
1524         static const struct {
1525                 u32 opt;
1526                 u16 reg;
1527                 u8  mask;
1528         } cfg[] = {
1529                 { WAKE_PHY,   Config3, LinkUp },
1530                 { WAKE_UCAST, Config5, UWF },
1531                 { WAKE_BCAST, Config5, BWF },
1532                 { WAKE_MCAST, Config5, MWF },
1533                 { WAKE_ANY,   Config5, LanWake },
1534                 { WAKE_MAGIC, Config3, MagicPacket }
1535         };
1536         u8 options;
1537
1538         RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
1539
1540         switch (tp->mac_version) {
1541         case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
1542         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
1543                 tmp = ARRAY_SIZE(cfg) - 1;
1544                 if (wolopts & WAKE_MAGIC)
1545                         rtl_w0w1_eri(tp,
1546                                      0x0dc,
1547                                      ERIAR_MASK_0100,
1548                                      MagicPacket_v2,
1549                                      0x0000,
1550                                      ERIAR_EXGMAC);
1551                 else
1552                         rtl_w0w1_eri(tp,
1553                                      0x0dc,
1554                                      ERIAR_MASK_0100,
1555                                      0x0000,
1556                                      MagicPacket_v2,
1557                                      ERIAR_EXGMAC);
1558                 break;
1559         default:
1560                 tmp = ARRAY_SIZE(cfg);
1561                 break;
1562         }
1563
1564         for (i = 0; i < tmp; i++) {
1565                 options = RTL_R8(tp, cfg[i].reg) & ~cfg[i].mask;
1566                 if (wolopts & cfg[i].opt)
1567                         options |= cfg[i].mask;
1568                 RTL_W8(tp, cfg[i].reg, options);
1569         }
1570
1571         switch (tp->mac_version) {
1572         case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_17:
1573                 options = RTL_R8(tp, Config1) & ~PMEnable;
1574                 if (wolopts)
1575                         options |= PMEnable;
1576                 RTL_W8(tp, Config1, options);
1577                 break;
1578         default:
1579                 options = RTL_R8(tp, Config2) & ~PME_SIGNAL;
1580                 if (wolopts)
1581                         options |= PME_SIGNAL;
1582                 RTL_W8(tp, Config2, options);
1583                 break;
1584         }
1585
1586         RTL_W8(tp, Cfg9346, Cfg9346_Lock);
1587 }
1588
1589 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1590 {
1591         struct rtl8169_private *tp = netdev_priv(dev);
1592         struct device *d = tp_to_dev(tp);
1593
1594         if (wol->wolopts & ~WAKE_ANY)
1595                 return -EINVAL;
1596
1597         pm_runtime_get_noresume(d);
1598
1599         rtl_lock_work(tp);
1600
1601         tp->saved_wolopts = wol->wolopts;
1602
1603         if (pm_runtime_active(d))
1604                 __rtl8169_set_wol(tp, tp->saved_wolopts);
1605
1606         rtl_unlock_work(tp);
1607
1608         device_set_wakeup_enable(d, tp->saved_wolopts);
1609
1610         pm_runtime_put_noidle(d);
1611
1612         return 0;
1613 }
1614
1615 static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp)
1616 {
1617         return rtl_chip_infos[tp->mac_version].fw_name;
1618 }
1619
1620 static void rtl8169_get_drvinfo(struct net_device *dev,
1621                                 struct ethtool_drvinfo *info)
1622 {
1623         struct rtl8169_private *tp = netdev_priv(dev);
1624         struct rtl_fw *rtl_fw = tp->rtl_fw;
1625
1626         strlcpy(info->driver, MODULENAME, sizeof(info->driver));
1627         strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1628         BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
1629         if (!IS_ERR_OR_NULL(rtl_fw))
1630                 strlcpy(info->fw_version, rtl_fw->version,
1631                         sizeof(info->fw_version));
1632 }
1633
1634 static int rtl8169_get_regs_len(struct net_device *dev)
1635 {
1636         return R8169_REGS_SIZE;
1637 }
1638
1639 static netdev_features_t rtl8169_fix_features(struct net_device *dev,
1640         netdev_features_t features)
1641 {
1642         struct rtl8169_private *tp = netdev_priv(dev);
1643
1644         if (dev->mtu > TD_MSS_MAX)
1645                 features &= ~NETIF_F_ALL_TSO;
1646
1647         if (dev->mtu > JUMBO_1K &&
1648             tp->mac_version > RTL_GIGA_MAC_VER_06)
1649                 features &= ~NETIF_F_IP_CSUM;
1650
1651         return features;
1652 }
1653
1654 static int rtl8169_set_features(struct net_device *dev,
1655                                 netdev_features_t features)
1656 {
1657         struct rtl8169_private *tp = netdev_priv(dev);
1658         u32 rx_config;
1659
1660         rtl_lock_work(tp);
1661
1662         rx_config = RTL_R32(tp, RxConfig);
1663         if (features & NETIF_F_RXALL)
1664                 rx_config |= (AcceptErr | AcceptRunt);
1665         else
1666                 rx_config &= ~(AcceptErr | AcceptRunt);
1667
1668         RTL_W32(tp, RxConfig, rx_config);
1669
1670         if (features & NETIF_F_RXCSUM)
1671                 tp->cp_cmd |= RxChkSum;
1672         else
1673                 tp->cp_cmd &= ~RxChkSum;
1674
1675         if (features & NETIF_F_HW_VLAN_CTAG_RX)
1676                 tp->cp_cmd |= RxVlan;
1677         else
1678                 tp->cp_cmd &= ~RxVlan;
1679
1680         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1681         RTL_R16(tp, CPlusCmd);
1682
1683         rtl_unlock_work(tp);
1684
1685         return 0;
1686 }
1687
1688 static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb)
1689 {
1690         return (skb_vlan_tag_present(skb)) ?
1691                 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00;
1692 }
1693
1694 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1695 {
1696         u32 opts2 = le32_to_cpu(desc->opts2);
1697
1698         if (opts2 & RxVlanTag)
1699                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff));
1700 }
1701
1702 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1703                              void *p)
1704 {
1705         struct rtl8169_private *tp = netdev_priv(dev);
1706         u32 __iomem *data = tp->mmio_addr;
1707         u32 *dw = p;
1708         int i;
1709
1710         rtl_lock_work(tp);
1711         for (i = 0; i < R8169_REGS_SIZE; i += 4)
1712                 memcpy_fromio(dw++, data++, 4);
1713         rtl_unlock_work(tp);
1714 }
1715
1716 static u32 rtl8169_get_msglevel(struct net_device *dev)
1717 {
1718         struct rtl8169_private *tp = netdev_priv(dev);
1719
1720         return tp->msg_enable;
1721 }
1722
1723 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1724 {
1725         struct rtl8169_private *tp = netdev_priv(dev);
1726
1727         tp->msg_enable = value;
1728 }
1729
1730 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1731         "tx_packets",
1732         "rx_packets",
1733         "tx_errors",
1734         "rx_errors",
1735         "rx_missed",
1736         "align_errors",
1737         "tx_single_collisions",
1738         "tx_multi_collisions",
1739         "unicast",
1740         "broadcast",
1741         "multicast",
1742         "tx_aborted",
1743         "tx_underrun",
1744 };
1745
1746 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1747 {
1748         switch (sset) {
1749         case ETH_SS_STATS:
1750                 return ARRAY_SIZE(rtl8169_gstrings);
1751         default:
1752                 return -EOPNOTSUPP;
1753         }
1754 }
1755
1756 DECLARE_RTL_COND(rtl_counters_cond)
1757 {
1758         return RTL_R32(tp, CounterAddrLow) & (CounterReset | CounterDump);
1759 }
1760
1761 static bool rtl8169_do_counters(struct rtl8169_private *tp, u32 counter_cmd)
1762 {
1763         dma_addr_t paddr = tp->counters_phys_addr;
1764         u32 cmd;
1765
1766         RTL_W32(tp, CounterAddrHigh, (u64)paddr >> 32);
1767         RTL_R32(tp, CounterAddrHigh);
1768         cmd = (u64)paddr & DMA_BIT_MASK(32);
1769         RTL_W32(tp, CounterAddrLow, cmd);
1770         RTL_W32(tp, CounterAddrLow, cmd | counter_cmd);
1771
1772         return rtl_udelay_loop_wait_low(tp, &rtl_counters_cond, 10, 1000);
1773 }
1774
1775 static bool rtl8169_reset_counters(struct rtl8169_private *tp)
1776 {
1777         /*
1778          * Versions prior to RTL_GIGA_MAC_VER_19 don't support resetting the
1779          * tally counters.
1780          */
1781         if (tp->mac_version < RTL_GIGA_MAC_VER_19)
1782                 return true;
1783
1784         return rtl8169_do_counters(tp, CounterReset);
1785 }
1786
1787 static bool rtl8169_update_counters(struct rtl8169_private *tp)
1788 {
1789         /*
1790          * Some chips are unable to dump tally counters when the receiver
1791          * is disabled.
1792          */
1793         if ((RTL_R8(tp, ChipCmd) & CmdRxEnb) == 0)
1794                 return true;
1795
1796         return rtl8169_do_counters(tp, CounterDump);
1797 }
1798
1799 static bool rtl8169_init_counter_offsets(struct rtl8169_private *tp)
1800 {
1801         struct rtl8169_counters *counters = tp->counters;
1802         bool ret = false;
1803
1804         /*
1805          * rtl8169_init_counter_offsets is called from rtl_open.  On chip
1806          * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only
1807          * reset by a power cycle, while the counter values collected by the
1808          * driver are reset at every driver unload/load cycle.
1809          *
1810          * To make sure the HW values returned by @get_stats64 match the SW
1811          * values, we collect the initial values at first open(*) and use them
1812          * as offsets to normalize the values returned by @get_stats64.
1813          *
1814          * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one
1815          * for the reason stated in rtl8169_update_counters; CmdRxEnb is only
1816          * set at open time by rtl_hw_start.
1817          */
1818
1819         if (tp->tc_offset.inited)
1820                 return true;
1821
1822         /* If both, reset and update fail, propagate to caller. */
1823         if (rtl8169_reset_counters(tp))
1824                 ret = true;
1825
1826         if (rtl8169_update_counters(tp))
1827                 ret = true;
1828
1829         tp->tc_offset.tx_errors = counters->tx_errors;
1830         tp->tc_offset.tx_multi_collision = counters->tx_multi_collision;
1831         tp->tc_offset.tx_aborted = counters->tx_aborted;
1832         tp->tc_offset.inited = true;
1833
1834         return ret;
1835 }
1836
1837 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1838                                       struct ethtool_stats *stats, u64 *data)
1839 {
1840         struct rtl8169_private *tp = netdev_priv(dev);
1841         struct device *d = tp_to_dev(tp);
1842         struct rtl8169_counters *counters = tp->counters;
1843
1844         ASSERT_RTNL();
1845
1846         pm_runtime_get_noresume(d);
1847
1848         if (pm_runtime_active(d))
1849                 rtl8169_update_counters(tp);
1850
1851         pm_runtime_put_noidle(d);
1852
1853         data[0] = le64_to_cpu(counters->tx_packets);
1854         data[1] = le64_to_cpu(counters->rx_packets);
1855         data[2] = le64_to_cpu(counters->tx_errors);
1856         data[3] = le32_to_cpu(counters->rx_errors);
1857         data[4] = le16_to_cpu(counters->rx_missed);
1858         data[5] = le16_to_cpu(counters->align_errors);
1859         data[6] = le32_to_cpu(counters->tx_one_collision);
1860         data[7] = le32_to_cpu(counters->tx_multi_collision);
1861         data[8] = le64_to_cpu(counters->rx_unicast);
1862         data[9] = le64_to_cpu(counters->rx_broadcast);
1863         data[10] = le32_to_cpu(counters->rx_multicast);
1864         data[11] = le16_to_cpu(counters->tx_aborted);
1865         data[12] = le16_to_cpu(counters->tx_underun);
1866 }
1867
1868 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1869 {
1870         switch(stringset) {
1871         case ETH_SS_STATS:
1872                 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1873                 break;
1874         }
1875 }
1876
1877 /*
1878  * Interrupt coalescing
1879  *
1880  * > 1 - the availability of the IntrMitigate (0xe2) register through the
1881  * >     8169, 8168 and 810x line of chipsets
1882  *
1883  * 8169, 8168, and 8136(810x) serial chipsets support it.
1884  *
1885  * > 2 - the Tx timer unit at gigabit speed
1886  *
1887  * The unit of the timer depends on both the speed and the setting of CPlusCmd
1888  * (0xe0) bit 1 and bit 0.
1889  *
1890  * For 8169
1891  * bit[1:0] \ speed        1000M           100M            10M
1892  * 0 0                     320ns           2.56us          40.96us
1893  * 0 1                     2.56us          20.48us         327.7us
1894  * 1 0                     5.12us          40.96us         655.4us
1895  * 1 1                     10.24us         81.92us         1.31ms
1896  *
1897  * For the other
1898  * bit[1:0] \ speed        1000M           100M            10M
1899  * 0 0                     5us             2.56us          40.96us
1900  * 0 1                     40us            20.48us         327.7us
1901  * 1 0                     80us            40.96us         655.4us
1902  * 1 1                     160us           81.92us         1.31ms
1903  */
1904
1905 /* rx/tx scale factors for one particular CPlusCmd[0:1] value */
1906 struct rtl_coalesce_scale {
1907         /* Rx / Tx */
1908         u32 nsecs[2];
1909 };
1910
1911 /* rx/tx scale factors for all CPlusCmd[0:1] cases */
1912 struct rtl_coalesce_info {
1913         u32 speed;
1914         struct rtl_coalesce_scale scalev[4];    /* each CPlusCmd[0:1] case */
1915 };
1916
1917 /* produce (r,t) pairs with each being in series of *1, *8, *8*2, *8*2*2 */
1918 #define rxtx_x1822(r, t) {              \
1919         {{(r),          (t)}},          \
1920         {{(r)*8,        (t)*8}},        \
1921         {{(r)*8*2,      (t)*8*2}},      \
1922         {{(r)*8*2*2,    (t)*8*2*2}},    \
1923 }
1924 static const struct rtl_coalesce_info rtl_coalesce_info_8169[] = {
1925         /* speed        delays:     rx00   tx00 */
1926         { SPEED_10,     rxtx_x1822(40960, 40960)        },
1927         { SPEED_100,    rxtx_x1822( 2560,  2560)        },
1928         { SPEED_1000,   rxtx_x1822(  320,   320)        },
1929         { 0 },
1930 };
1931
1932 static const struct rtl_coalesce_info rtl_coalesce_info_8168_8136[] = {
1933         /* speed        delays:     rx00   tx00 */
1934         { SPEED_10,     rxtx_x1822(40960, 40960)        },
1935         { SPEED_100,    rxtx_x1822( 2560,  2560)        },
1936         { SPEED_1000,   rxtx_x1822( 5000,  5000)        },
1937         { 0 },
1938 };
1939 #undef rxtx_x1822
1940
1941 /* get rx/tx scale vector corresponding to current speed */
1942 static const struct rtl_coalesce_info *rtl_coalesce_info(struct net_device *dev)
1943 {
1944         struct rtl8169_private *tp = netdev_priv(dev);
1945         struct ethtool_link_ksettings ecmd;
1946         const struct rtl_coalesce_info *ci;
1947         int rc;
1948
1949         rc = phy_ethtool_get_link_ksettings(dev, &ecmd);
1950         if (rc < 0)
1951                 return ERR_PTR(rc);
1952
1953         for (ci = tp->coalesce_info; ci->speed != 0; ci++) {
1954                 if (ecmd.base.speed == ci->speed) {
1955                         return ci;
1956                 }
1957         }
1958
1959         return ERR_PTR(-ELNRNG);
1960 }
1961
1962 static int rtl_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1963 {
1964         struct rtl8169_private *tp = netdev_priv(dev);
1965         const struct rtl_coalesce_info *ci;
1966         const struct rtl_coalesce_scale *scale;
1967         struct {
1968                 u32 *max_frames;
1969                 u32 *usecs;
1970         } coal_settings [] = {
1971                 { &ec->rx_max_coalesced_frames, &ec->rx_coalesce_usecs },
1972                 { &ec->tx_max_coalesced_frames, &ec->tx_coalesce_usecs }
1973         }, *p = coal_settings;
1974         int i;
1975         u16 w;
1976
1977         memset(ec, 0, sizeof(*ec));
1978
1979         /* get rx/tx scale corresponding to current speed and CPlusCmd[0:1] */
1980         ci = rtl_coalesce_info(dev);
1981         if (IS_ERR(ci))
1982                 return PTR_ERR(ci);
1983
1984         scale = &ci->scalev[tp->cp_cmd & INTT_MASK];
1985
1986         /* read IntrMitigate and adjust according to scale */
1987         for (w = RTL_R16(tp, IntrMitigate); w; w >>= RTL_COALESCE_SHIFT, p++) {
1988                 *p->max_frames = (w & RTL_COALESCE_MASK) << 2;
1989                 w >>= RTL_COALESCE_SHIFT;
1990                 *p->usecs = w & RTL_COALESCE_MASK;
1991         }
1992
1993         for (i = 0; i < 2; i++) {
1994                 p = coal_settings + i;
1995                 *p->usecs = (*p->usecs * scale->nsecs[i]) / 1000;
1996
1997                 /*
1998                  * ethtool_coalesce says it is illegal to set both usecs and
1999                  * max_frames to 0.
2000                  */
2001                 if (!*p->usecs && !*p->max_frames)
2002                         *p->max_frames = 1;
2003         }
2004
2005         return 0;
2006 }
2007
2008 /* choose appropriate scale factor and CPlusCmd[0:1] for (speed, nsec) */
2009 static const struct rtl_coalesce_scale *rtl_coalesce_choose_scale(
2010                         struct net_device *dev, u32 nsec, u16 *cp01)
2011 {
2012         const struct rtl_coalesce_info *ci;
2013         u16 i;
2014
2015         ci = rtl_coalesce_info(dev);
2016         if (IS_ERR(ci))
2017                 return ERR_CAST(ci);
2018
2019         for (i = 0; i < 4; i++) {
2020                 u32 rxtx_maxscale = max(ci->scalev[i].nsecs[0],
2021                                         ci->scalev[i].nsecs[1]);
2022                 if (nsec <= rxtx_maxscale * RTL_COALESCE_T_MAX) {
2023                         *cp01 = i;
2024                         return &ci->scalev[i];
2025                 }
2026         }
2027
2028         return ERR_PTR(-EINVAL);
2029 }
2030
2031 static int rtl_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
2032 {
2033         struct rtl8169_private *tp = netdev_priv(dev);
2034         const struct rtl_coalesce_scale *scale;
2035         struct {
2036                 u32 frames;
2037                 u32 usecs;
2038         } coal_settings [] = {
2039                 { ec->rx_max_coalesced_frames, ec->rx_coalesce_usecs },
2040                 { ec->tx_max_coalesced_frames, ec->tx_coalesce_usecs }
2041         }, *p = coal_settings;
2042         u16 w = 0, cp01;
2043         int i;
2044
2045         scale = rtl_coalesce_choose_scale(dev,
2046                         max(p[0].usecs, p[1].usecs) * 1000, &cp01);
2047         if (IS_ERR(scale))
2048                 return PTR_ERR(scale);
2049
2050         for (i = 0; i < 2; i++, p++) {
2051                 u32 units;
2052
2053                 /*
2054                  * accept max_frames=1 we returned in rtl_get_coalesce.
2055                  * accept it not only when usecs=0 because of e.g. the following scenario:
2056                  *
2057                  * - both rx_usecs=0 & rx_frames=0 in hardware (no delay on RX)
2058                  * - rtl_get_coalesce returns rx_usecs=0, rx_frames=1
2059                  * - then user does `ethtool -C eth0 rx-usecs 100`
2060                  *
2061                  * since ethtool sends to kernel whole ethtool_coalesce
2062                  * settings, if we do not handle rx_usecs=!0, rx_frames=1
2063                  * we'll reject it below in `frames % 4 != 0`.
2064                  */
2065                 if (p->frames == 1) {
2066                         p->frames = 0;
2067                 }
2068
2069                 units = p->usecs * 1000 / scale->nsecs[i];
2070                 if (p->frames > RTL_COALESCE_FRAME_MAX || p->frames % 4)
2071                         return -EINVAL;
2072
2073                 w <<= RTL_COALESCE_SHIFT;
2074                 w |= units;
2075                 w <<= RTL_COALESCE_SHIFT;
2076                 w |= p->frames >> 2;
2077         }
2078
2079         rtl_lock_work(tp);
2080
2081         RTL_W16(tp, IntrMitigate, swab16(w));
2082
2083         tp->cp_cmd = (tp->cp_cmd & ~INTT_MASK) | cp01;
2084         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
2085         RTL_R16(tp, CPlusCmd);
2086
2087         rtl_unlock_work(tp);
2088
2089         return 0;
2090 }
2091
2092 static const struct ethtool_ops rtl8169_ethtool_ops = {
2093         .get_drvinfo            = rtl8169_get_drvinfo,
2094         .get_regs_len           = rtl8169_get_regs_len,
2095         .get_link               = ethtool_op_get_link,
2096         .get_coalesce           = rtl_get_coalesce,
2097         .set_coalesce           = rtl_set_coalesce,
2098         .get_msglevel           = rtl8169_get_msglevel,
2099         .set_msglevel           = rtl8169_set_msglevel,
2100         .get_regs               = rtl8169_get_regs,
2101         .get_wol                = rtl8169_get_wol,
2102         .set_wol                = rtl8169_set_wol,
2103         .get_strings            = rtl8169_get_strings,
2104         .get_sset_count         = rtl8169_get_sset_count,
2105         .get_ethtool_stats      = rtl8169_get_ethtool_stats,
2106         .get_ts_info            = ethtool_op_get_ts_info,
2107         .nway_reset             = phy_ethtool_nway_reset,
2108         .get_link_ksettings     = phy_ethtool_get_link_ksettings,
2109         .set_link_ksettings     = phy_ethtool_set_link_ksettings,
2110 };
2111
2112 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
2113                                     u8 default_version)
2114 {
2115         /*
2116          * The driver currently handles the 8168Bf and the 8168Be identically
2117          * but they can be identified more specifically through the test below
2118          * if needed:
2119          *
2120          * (RTL_R32(tp, TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
2121          *
2122          * Same thing for the 8101Eb and the 8101Ec:
2123          *
2124          * (RTL_R32(tp, TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
2125          */
2126         static const struct rtl_mac_info {
2127                 u32 mask;
2128                 u32 val;
2129                 int mac_version;
2130         } mac_info[] = {
2131                 /* 8168EP family. */
2132                 { 0x7cf00000, 0x50200000,       RTL_GIGA_MAC_VER_51 },
2133                 { 0x7cf00000, 0x50100000,       RTL_GIGA_MAC_VER_50 },
2134                 { 0x7cf00000, 0x50000000,       RTL_GIGA_MAC_VER_49 },
2135
2136                 /* 8168H family. */
2137                 { 0x7cf00000, 0x54100000,       RTL_GIGA_MAC_VER_46 },
2138                 { 0x7cf00000, 0x54000000,       RTL_GIGA_MAC_VER_45 },
2139
2140                 /* 8168G family. */
2141                 { 0x7cf00000, 0x5c800000,       RTL_GIGA_MAC_VER_44 },
2142                 { 0x7cf00000, 0x50900000,       RTL_GIGA_MAC_VER_42 },
2143                 { 0x7cf00000, 0x4c100000,       RTL_GIGA_MAC_VER_41 },
2144                 { 0x7cf00000, 0x4c000000,       RTL_GIGA_MAC_VER_40 },
2145
2146                 /* 8168F family. */
2147                 { 0x7c800000, 0x48800000,       RTL_GIGA_MAC_VER_38 },
2148                 { 0x7cf00000, 0x48100000,       RTL_GIGA_MAC_VER_36 },
2149                 { 0x7cf00000, 0x48000000,       RTL_GIGA_MAC_VER_35 },
2150
2151                 /* 8168E family. */
2152                 { 0x7c800000, 0x2c800000,       RTL_GIGA_MAC_VER_34 },
2153                 { 0x7cf00000, 0x2c100000,       RTL_GIGA_MAC_VER_32 },
2154                 { 0x7c800000, 0x2c000000,       RTL_GIGA_MAC_VER_33 },
2155
2156                 /* 8168D family. */
2157                 { 0x7cf00000, 0x28100000,       RTL_GIGA_MAC_VER_25 },
2158                 { 0x7c800000, 0x28000000,       RTL_GIGA_MAC_VER_26 },
2159
2160                 /* 8168DP family. */
2161                 { 0x7cf00000, 0x28800000,       RTL_GIGA_MAC_VER_27 },
2162                 { 0x7cf00000, 0x28a00000,       RTL_GIGA_MAC_VER_28 },
2163                 { 0x7cf00000, 0x28b00000,       RTL_GIGA_MAC_VER_31 },
2164
2165                 /* 8168C family. */
2166                 { 0x7cf00000, 0x3c900000,       RTL_GIGA_MAC_VER_23 },
2167                 { 0x7cf00000, 0x3c800000,       RTL_GIGA_MAC_VER_18 },
2168                 { 0x7c800000, 0x3c800000,       RTL_GIGA_MAC_VER_24 },
2169                 { 0x7cf00000, 0x3c000000,       RTL_GIGA_MAC_VER_19 },
2170                 { 0x7cf00000, 0x3c200000,       RTL_GIGA_MAC_VER_20 },
2171                 { 0x7cf00000, 0x3c300000,       RTL_GIGA_MAC_VER_21 },
2172                 { 0x7c800000, 0x3c000000,       RTL_GIGA_MAC_VER_22 },
2173
2174                 /* 8168B family. */
2175                 { 0x7cf00000, 0x38000000,       RTL_GIGA_MAC_VER_12 },
2176                 { 0x7c800000, 0x38000000,       RTL_GIGA_MAC_VER_17 },
2177                 { 0x7c800000, 0x30000000,       RTL_GIGA_MAC_VER_11 },
2178
2179                 /* 8101 family. */
2180                 { 0x7c800000, 0x44800000,       RTL_GIGA_MAC_VER_39 },
2181                 { 0x7c800000, 0x44000000,       RTL_GIGA_MAC_VER_37 },
2182                 { 0x7cf00000, 0x40900000,       RTL_GIGA_MAC_VER_29 },
2183                 { 0x7c800000, 0x40800000,       RTL_GIGA_MAC_VER_30 },
2184                 { 0x7cf00000, 0x34900000,       RTL_GIGA_MAC_VER_08 },
2185                 { 0x7cf00000, 0x24900000,       RTL_GIGA_MAC_VER_08 },
2186                 { 0x7cf00000, 0x34800000,       RTL_GIGA_MAC_VER_07 },
2187                 { 0x7cf00000, 0x24800000,       RTL_GIGA_MAC_VER_07 },
2188                 { 0x7cf00000, 0x34000000,       RTL_GIGA_MAC_VER_13 },
2189                 { 0x7cf00000, 0x34300000,       RTL_GIGA_MAC_VER_10 },
2190                 { 0x7cf00000, 0x34200000,       RTL_GIGA_MAC_VER_16 },
2191                 { 0x7c800000, 0x34800000,       RTL_GIGA_MAC_VER_09 },
2192                 { 0x7c800000, 0x24800000,       RTL_GIGA_MAC_VER_09 },
2193                 { 0x7c800000, 0x34000000,       RTL_GIGA_MAC_VER_16 },
2194                 /* FIXME: where did these entries come from ? -- FR */
2195                 { 0xfc800000, 0x38800000,       RTL_GIGA_MAC_VER_15 },
2196                 { 0xfc800000, 0x30800000,       RTL_GIGA_MAC_VER_14 },
2197
2198                 /* 8110 family. */
2199                 { 0xfc800000, 0x98000000,       RTL_GIGA_MAC_VER_06 },
2200                 { 0xfc800000, 0x18000000,       RTL_GIGA_MAC_VER_05 },
2201                 { 0xfc800000, 0x10000000,       RTL_GIGA_MAC_VER_04 },
2202                 { 0xfc800000, 0x04000000,       RTL_GIGA_MAC_VER_03 },
2203                 { 0xfc800000, 0x00800000,       RTL_GIGA_MAC_VER_02 },
2204                 { 0xfc800000, 0x00000000,       RTL_GIGA_MAC_VER_01 },
2205
2206                 /* Catch-all */
2207                 { 0x00000000, 0x00000000,       RTL_GIGA_MAC_NONE   }
2208         };
2209         const struct rtl_mac_info *p = mac_info;
2210         u32 reg;
2211
2212         reg = RTL_R32(tp, TxConfig);
2213         while ((reg & p->mask) != p->val)
2214                 p++;
2215         tp->mac_version = p->mac_version;
2216
2217         if (tp->mac_version == RTL_GIGA_MAC_NONE) {
2218                 dev_notice(tp_to_dev(tp),
2219                            "unknown MAC, using family default\n");
2220                 tp->mac_version = default_version;
2221         } else if (tp->mac_version == RTL_GIGA_MAC_VER_42) {
2222                 tp->mac_version = tp->supports_gmii ?
2223                                   RTL_GIGA_MAC_VER_42 :
2224                                   RTL_GIGA_MAC_VER_43;
2225         } else if (tp->mac_version == RTL_GIGA_MAC_VER_45) {
2226                 tp->mac_version = tp->supports_gmii ?
2227                                   RTL_GIGA_MAC_VER_45 :
2228                                   RTL_GIGA_MAC_VER_47;
2229         } else if (tp->mac_version == RTL_GIGA_MAC_VER_46) {
2230                 tp->mac_version = tp->supports_gmii ?
2231                                   RTL_GIGA_MAC_VER_46 :
2232                                   RTL_GIGA_MAC_VER_48;
2233         }
2234 }
2235
2236 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
2237 {
2238         netif_dbg(tp, drv, tp->dev, "mac_version = 0x%02x\n", tp->mac_version);
2239 }
2240
2241 struct phy_reg {
2242         u16 reg;
2243         u16 val;
2244 };
2245
2246 static void rtl_writephy_batch(struct rtl8169_private *tp,
2247                                const struct phy_reg *regs, int len)
2248 {
2249         while (len-- > 0) {
2250                 rtl_writephy(tp, regs->reg, regs->val);
2251                 regs++;
2252         }
2253 }
2254
2255 #define PHY_READ                0x00000000
2256 #define PHY_DATA_OR             0x10000000
2257 #define PHY_DATA_AND            0x20000000
2258 #define PHY_BJMPN               0x30000000
2259 #define PHY_MDIO_CHG            0x40000000
2260 #define PHY_CLEAR_READCOUNT     0x70000000
2261 #define PHY_WRITE               0x80000000
2262 #define PHY_READCOUNT_EQ_SKIP   0x90000000
2263 #define PHY_COMP_EQ_SKIPN       0xa0000000
2264 #define PHY_COMP_NEQ_SKIPN      0xb0000000
2265 #define PHY_WRITE_PREVIOUS      0xc0000000
2266 #define PHY_SKIPN               0xd0000000
2267 #define PHY_DELAY_MS            0xe0000000
2268
2269 struct fw_info {
2270         u32     magic;
2271         char    version[RTL_VER_SIZE];
2272         __le32  fw_start;
2273         __le32  fw_len;
2274         u8      chksum;
2275 } __packed;
2276
2277 #define FW_OPCODE_SIZE  sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
2278
2279 static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2280 {
2281         const struct firmware *fw = rtl_fw->fw;
2282         struct fw_info *fw_info = (struct fw_info *)fw->data;
2283         struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2284         char *version = rtl_fw->version;
2285         bool rc = false;
2286
2287         if (fw->size < FW_OPCODE_SIZE)
2288                 goto out;
2289
2290         if (!fw_info->magic) {
2291                 size_t i, size, start;
2292                 u8 checksum = 0;
2293
2294                 if (fw->size < sizeof(*fw_info))
2295                         goto out;
2296
2297                 for (i = 0; i < fw->size; i++)
2298                         checksum += fw->data[i];
2299                 if (checksum != 0)
2300                         goto out;
2301
2302                 start = le32_to_cpu(fw_info->fw_start);
2303                 if (start > fw->size)
2304                         goto out;
2305
2306                 size = le32_to_cpu(fw_info->fw_len);
2307                 if (size > (fw->size - start) / FW_OPCODE_SIZE)
2308                         goto out;
2309
2310                 memcpy(version, fw_info->version, RTL_VER_SIZE);
2311
2312                 pa->code = (__le32 *)(fw->data + start);
2313                 pa->size = size;
2314         } else {
2315                 if (fw->size % FW_OPCODE_SIZE)
2316                         goto out;
2317
2318                 strlcpy(version, rtl_lookup_firmware_name(tp), RTL_VER_SIZE);
2319
2320                 pa->code = (__le32 *)fw->data;
2321                 pa->size = fw->size / FW_OPCODE_SIZE;
2322         }
2323         version[RTL_VER_SIZE - 1] = 0;
2324
2325         rc = true;
2326 out:
2327         return rc;
2328 }
2329
2330 static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev,
2331                            struct rtl_fw_phy_action *pa)
2332 {
2333         bool rc = false;
2334         size_t index;
2335
2336         for (index = 0; index < pa->size; index++) {
2337                 u32 action = le32_to_cpu(pa->code[index]);
2338                 u32 regno = (action & 0x0fff0000) >> 16;
2339
2340                 switch(action & 0xf0000000) {
2341                 case PHY_READ:
2342                 case PHY_DATA_OR:
2343                 case PHY_DATA_AND:
2344                 case PHY_MDIO_CHG:
2345                 case PHY_CLEAR_READCOUNT:
2346                 case PHY_WRITE:
2347                 case PHY_WRITE_PREVIOUS:
2348                 case PHY_DELAY_MS:
2349                         break;
2350
2351                 case PHY_BJMPN:
2352                         if (regno > index) {
2353                                 netif_err(tp, ifup, tp->dev,
2354                                           "Out of range of firmware\n");
2355                                 goto out;
2356                         }
2357                         break;
2358                 case PHY_READCOUNT_EQ_SKIP:
2359                         if (index + 2 >= pa->size) {
2360                                 netif_err(tp, ifup, tp->dev,
2361                                           "Out of range of firmware\n");
2362                                 goto out;
2363                         }
2364                         break;
2365                 case PHY_COMP_EQ_SKIPN:
2366                 case PHY_COMP_NEQ_SKIPN:
2367                 case PHY_SKIPN:
2368                         if (index + 1 + regno >= pa->size) {
2369                                 netif_err(tp, ifup, tp->dev,
2370                                           "Out of range of firmware\n");
2371                                 goto out;
2372                         }
2373                         break;
2374
2375                 default:
2376                         netif_err(tp, ifup, tp->dev,
2377                                   "Invalid action 0x%08x\n", action);
2378                         goto out;
2379                 }
2380         }
2381         rc = true;
2382 out:
2383         return rc;
2384 }
2385
2386 static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2387 {
2388         struct net_device *dev = tp->dev;
2389         int rc = -EINVAL;
2390
2391         if (!rtl_fw_format_ok(tp, rtl_fw)) {
2392                 netif_err(tp, ifup, dev, "invalid firmware\n");
2393                 goto out;
2394         }
2395
2396         if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action))
2397                 rc = 0;
2398 out:
2399         return rc;
2400 }
2401
2402 static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2403 {
2404         struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2405         struct mdio_ops org, *ops = &tp->mdio_ops;
2406         u32 predata, count;
2407         size_t index;
2408
2409         predata = count = 0;
2410         org.write = ops->write;
2411         org.read = ops->read;
2412
2413         for (index = 0; index < pa->size; ) {
2414                 u32 action = le32_to_cpu(pa->code[index]);
2415                 u32 data = action & 0x0000ffff;
2416                 u32 regno = (action & 0x0fff0000) >> 16;
2417
2418                 if (!action)
2419                         break;
2420
2421                 switch(action & 0xf0000000) {
2422                 case PHY_READ:
2423                         predata = rtl_readphy(tp, regno);
2424                         count++;
2425                         index++;
2426                         break;
2427                 case PHY_DATA_OR:
2428                         predata |= data;
2429                         index++;
2430                         break;
2431                 case PHY_DATA_AND:
2432                         predata &= data;
2433                         index++;
2434                         break;
2435                 case PHY_BJMPN:
2436                         index -= regno;
2437                         break;
2438                 case PHY_MDIO_CHG:
2439                         if (data == 0) {
2440                                 ops->write = org.write;
2441                                 ops->read = org.read;
2442                         } else if (data == 1) {
2443                                 ops->write = mac_mcu_write;
2444                                 ops->read = mac_mcu_read;
2445                         }
2446
2447                         index++;
2448                         break;
2449                 case PHY_CLEAR_READCOUNT:
2450                         count = 0;
2451                         index++;
2452                         break;
2453                 case PHY_WRITE:
2454                         rtl_writephy(tp, regno, data);
2455                         index++;
2456                         break;
2457                 case PHY_READCOUNT_EQ_SKIP:
2458                         index += (count == data) ? 2 : 1;
2459                         break;
2460                 case PHY_COMP_EQ_SKIPN:
2461                         if (predata == data)
2462                                 index += regno;
2463                         index++;
2464                         break;
2465                 case PHY_COMP_NEQ_SKIPN:
2466                         if (predata != data)
2467                                 index += regno;
2468                         index++;
2469                         break;
2470                 case PHY_WRITE_PREVIOUS:
2471                         rtl_writephy(tp, regno, predata);
2472                         index++;
2473                         break;
2474                 case PHY_SKIPN:
2475                         index += regno + 1;
2476                         break;
2477                 case PHY_DELAY_MS:
2478                         mdelay(data);
2479                         index++;
2480                         break;
2481
2482                 default:
2483                         BUG();
2484                 }
2485         }
2486
2487         ops->write = org.write;
2488         ops->read = org.read;
2489 }
2490
2491 static void rtl_release_firmware(struct rtl8169_private *tp)
2492 {
2493         if (!IS_ERR_OR_NULL(tp->rtl_fw)) {
2494                 release_firmware(tp->rtl_fw->fw);
2495                 kfree(tp->rtl_fw);
2496         }
2497         tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
2498 }
2499
2500 static void rtl_apply_firmware(struct rtl8169_private *tp)
2501 {
2502         struct rtl_fw *rtl_fw = tp->rtl_fw;
2503
2504         /* TODO: release firmware once rtl_phy_write_fw signals failures. */
2505         if (!IS_ERR_OR_NULL(rtl_fw))
2506                 rtl_phy_write_fw(tp, rtl_fw);
2507 }
2508
2509 static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
2510 {
2511         if (rtl_readphy(tp, reg) != val)
2512                 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
2513         else
2514                 rtl_apply_firmware(tp);
2515 }
2516
2517 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
2518 {
2519         static const struct phy_reg phy_reg_init[] = {
2520                 { 0x1f, 0x0001 },
2521                 { 0x06, 0x006e },
2522                 { 0x08, 0x0708 },
2523                 { 0x15, 0x4000 },
2524                 { 0x18, 0x65c7 },
2525
2526                 { 0x1f, 0x0001 },
2527                 { 0x03, 0x00a1 },
2528                 { 0x02, 0x0008 },
2529                 { 0x01, 0x0120 },
2530                 { 0x00, 0x1000 },
2531                 { 0x04, 0x0800 },
2532                 { 0x04, 0x0000 },
2533
2534                 { 0x03, 0xff41 },
2535                 { 0x02, 0xdf60 },
2536                 { 0x01, 0x0140 },
2537                 { 0x00, 0x0077 },
2538                 { 0x04, 0x7800 },
2539                 { 0x04, 0x7000 },
2540
2541                 { 0x03, 0x802f },
2542                 { 0x02, 0x4f02 },
2543                 { 0x01, 0x0409 },
2544                 { 0x00, 0xf0f9 },
2545                 { 0x04, 0x9800 },
2546                 { 0x04, 0x9000 },
2547
2548                 { 0x03, 0xdf01 },
2549                 { 0x02, 0xdf20 },
2550                 { 0x01, 0xff95 },
2551                 { 0x00, 0xba00 },
2552                 { 0x04, 0xa800 },
2553                 { 0x04, 0xa000 },
2554
2555                 { 0x03, 0xff41 },
2556                 { 0x02, 0xdf20 },
2557                 { 0x01, 0x0140 },
2558                 { 0x00, 0x00bb },
2559                 { 0x04, 0xb800 },
2560                 { 0x04, 0xb000 },
2561
2562                 { 0x03, 0xdf41 },
2563                 { 0x02, 0xdc60 },
2564                 { 0x01, 0x6340 },
2565                 { 0x00, 0x007d },
2566                 { 0x04, 0xd800 },
2567                 { 0x04, 0xd000 },
2568
2569                 { 0x03, 0xdf01 },
2570                 { 0x02, 0xdf20 },
2571                 { 0x01, 0x100a },
2572                 { 0x00, 0xa0ff },
2573                 { 0x04, 0xf800 },
2574                 { 0x04, 0xf000 },
2575
2576                 { 0x1f, 0x0000 },
2577                 { 0x0b, 0x0000 },
2578                 { 0x00, 0x9200 }
2579         };
2580
2581         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2582 }
2583
2584 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
2585 {
2586         static const struct phy_reg phy_reg_init[] = {
2587                 { 0x1f, 0x0002 },
2588                 { 0x01, 0x90d0 },
2589                 { 0x1f, 0x0000 }
2590         };
2591
2592         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2593 }
2594
2595 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2596 {
2597         struct pci_dev *pdev = tp->pci_dev;
2598
2599         if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
2600             (pdev->subsystem_device != 0xe000))
2601                 return;
2602
2603         rtl_writephy(tp, 0x1f, 0x0001);
2604         rtl_writephy(tp, 0x10, 0xf01b);
2605         rtl_writephy(tp, 0x1f, 0x0000);
2606 }
2607
2608 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2609 {
2610         static const struct phy_reg phy_reg_init[] = {
2611                 { 0x1f, 0x0001 },
2612                 { 0x04, 0x0000 },
2613                 { 0x03, 0x00a1 },
2614                 { 0x02, 0x0008 },
2615                 { 0x01, 0x0120 },
2616                 { 0x00, 0x1000 },
2617                 { 0x04, 0x0800 },
2618                 { 0x04, 0x9000 },
2619                 { 0x03, 0x802f },
2620                 { 0x02, 0x4f02 },
2621                 { 0x01, 0x0409 },
2622                 { 0x00, 0xf099 },
2623                 { 0x04, 0x9800 },
2624                 { 0x04, 0xa000 },
2625                 { 0x03, 0xdf01 },
2626                 { 0x02, 0xdf20 },
2627                 { 0x01, 0xff95 },
2628                 { 0x00, 0xba00 },
2629                 { 0x04, 0xa800 },
2630                 { 0x04, 0xf000 },
2631                 { 0x03, 0xdf01 },
2632                 { 0x02, 0xdf20 },
2633                 { 0x01, 0x101a },
2634                 { 0x00, 0xa0ff },
2635                 { 0x04, 0xf800 },
2636                 { 0x04, 0x0000 },
2637                 { 0x1f, 0x0000 },
2638
2639                 { 0x1f, 0x0001 },
2640                 { 0x10, 0xf41b },
2641                 { 0x14, 0xfb54 },
2642                 { 0x18, 0xf5c7 },
2643                 { 0x1f, 0x0000 },
2644
2645                 { 0x1f, 0x0001 },
2646                 { 0x17, 0x0cc0 },
2647                 { 0x1f, 0x0000 }
2648         };
2649
2650         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2651
2652         rtl8169scd_hw_phy_config_quirk(tp);
2653 }
2654
2655 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
2656 {
2657         static const struct phy_reg phy_reg_init[] = {
2658                 { 0x1f, 0x0001 },
2659                 { 0x04, 0x0000 },
2660                 { 0x03, 0x00a1 },
2661                 { 0x02, 0x0008 },
2662                 { 0x01, 0x0120 },
2663                 { 0x00, 0x1000 },
2664                 { 0x04, 0x0800 },
2665                 { 0x04, 0x9000 },
2666                 { 0x03, 0x802f },
2667                 { 0x02, 0x4f02 },
2668                 { 0x01, 0x0409 },
2669                 { 0x00, 0xf099 },
2670                 { 0x04, 0x9800 },
2671                 { 0x04, 0xa000 },
2672                 { 0x03, 0xdf01 },
2673                 { 0x02, 0xdf20 },
2674                 { 0x01, 0xff95 },
2675                 { 0x00, 0xba00 },
2676                 { 0x04, 0xa800 },
2677                 { 0x04, 0xf000 },
2678                 { 0x03, 0xdf01 },
2679                 { 0x02, 0xdf20 },
2680                 { 0x01, 0x101a },
2681                 { 0x00, 0xa0ff },
2682                 { 0x04, 0xf800 },
2683                 { 0x04, 0x0000 },
2684                 { 0x1f, 0x0000 },
2685
2686                 { 0x1f, 0x0001 },
2687                 { 0x0b, 0x8480 },
2688                 { 0x1f, 0x0000 },
2689
2690                 { 0x1f, 0x0001 },
2691                 { 0x18, 0x67c7 },
2692                 { 0x04, 0x2000 },
2693                 { 0x03, 0x002f },
2694                 { 0x02, 0x4360 },
2695                 { 0x01, 0x0109 },
2696                 { 0x00, 0x3022 },
2697                 { 0x04, 0x2800 },
2698                 { 0x1f, 0x0000 },
2699
2700                 { 0x1f, 0x0001 },
2701                 { 0x17, 0x0cc0 },
2702                 { 0x1f, 0x0000 }
2703         };
2704
2705         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2706 }
2707
2708 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
2709 {
2710         static const struct phy_reg phy_reg_init[] = {
2711                 { 0x10, 0xf41b },
2712                 { 0x1f, 0x0000 }
2713         };
2714
2715         rtl_writephy(tp, 0x1f, 0x0001);
2716         rtl_patchphy(tp, 0x16, 1 << 0);
2717
2718         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2719 }
2720
2721 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
2722 {
2723         static const struct phy_reg phy_reg_init[] = {
2724                 { 0x1f, 0x0001 },
2725                 { 0x10, 0xf41b },
2726                 { 0x1f, 0x0000 }
2727         };
2728
2729         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2730 }
2731
2732 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
2733 {
2734         static const struct phy_reg phy_reg_init[] = {
2735                 { 0x1f, 0x0000 },
2736                 { 0x1d, 0x0f00 },
2737                 { 0x1f, 0x0002 },
2738                 { 0x0c, 0x1ec8 },
2739                 { 0x1f, 0x0000 }
2740         };
2741
2742         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2743 }
2744
2745 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
2746 {
2747         static const struct phy_reg phy_reg_init[] = {
2748                 { 0x1f, 0x0001 },
2749                 { 0x1d, 0x3d98 },
2750                 { 0x1f, 0x0000 }
2751         };
2752
2753         rtl_writephy(tp, 0x1f, 0x0000);
2754         rtl_patchphy(tp, 0x14, 1 << 5);
2755         rtl_patchphy(tp, 0x0d, 1 << 5);
2756
2757         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2758 }
2759
2760 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
2761 {
2762         static const struct phy_reg phy_reg_init[] = {
2763                 { 0x1f, 0x0001 },
2764                 { 0x12, 0x2300 },
2765                 { 0x1f, 0x0002 },
2766                 { 0x00, 0x88d4 },
2767                 { 0x01, 0x82b1 },
2768                 { 0x03, 0x7002 },
2769                 { 0x08, 0x9e30 },
2770                 { 0x09, 0x01f0 },
2771                 { 0x0a, 0x5500 },
2772                 { 0x0c, 0x00c8 },
2773                 { 0x1f, 0x0003 },
2774                 { 0x12, 0xc096 },
2775                 { 0x16, 0x000a },
2776                 { 0x1f, 0x0000 },
2777                 { 0x1f, 0x0000 },
2778                 { 0x09, 0x2000 },
2779                 { 0x09, 0x0000 }
2780         };
2781
2782         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2783
2784         rtl_patchphy(tp, 0x14, 1 << 5);
2785         rtl_patchphy(tp, 0x0d, 1 << 5);
2786         rtl_writephy(tp, 0x1f, 0x0000);
2787 }
2788
2789 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
2790 {
2791         static const struct phy_reg phy_reg_init[] = {
2792                 { 0x1f, 0x0001 },
2793                 { 0x12, 0x2300 },
2794                 { 0x03, 0x802f },
2795                 { 0x02, 0x4f02 },
2796                 { 0x01, 0x0409 },
2797                 { 0x00, 0xf099 },
2798                 { 0x04, 0x9800 },
2799                 { 0x04, 0x9000 },
2800                 { 0x1d, 0x3d98 },
2801                 { 0x1f, 0x0002 },
2802                 { 0x0c, 0x7eb8 },
2803                 { 0x06, 0x0761 },
2804                 { 0x1f, 0x0003 },
2805                 { 0x16, 0x0f0a },
2806                 { 0x1f, 0x0000 }
2807         };
2808
2809         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2810
2811         rtl_patchphy(tp, 0x16, 1 << 0);
2812         rtl_patchphy(tp, 0x14, 1 << 5);
2813         rtl_patchphy(tp, 0x0d, 1 << 5);
2814         rtl_writephy(tp, 0x1f, 0x0000);
2815 }
2816
2817 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
2818 {
2819         static const struct phy_reg phy_reg_init[] = {
2820                 { 0x1f, 0x0001 },
2821                 { 0x12, 0x2300 },
2822                 { 0x1d, 0x3d98 },
2823                 { 0x1f, 0x0002 },
2824                 { 0x0c, 0x7eb8 },
2825                 { 0x06, 0x5461 },
2826                 { 0x1f, 0x0003 },
2827                 { 0x16, 0x0f0a },
2828                 { 0x1f, 0x0000 }
2829         };
2830
2831         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2832
2833         rtl_patchphy(tp, 0x16, 1 << 0);
2834         rtl_patchphy(tp, 0x14, 1 << 5);
2835         rtl_patchphy(tp, 0x0d, 1 << 5);
2836         rtl_writephy(tp, 0x1f, 0x0000);
2837 }
2838
2839 static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
2840 {
2841         rtl8168c_3_hw_phy_config(tp);
2842 }
2843
2844 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
2845 {
2846         static const struct phy_reg phy_reg_init_0[] = {
2847                 /* Channel Estimation */
2848                 { 0x1f, 0x0001 },
2849                 { 0x06, 0x4064 },
2850                 { 0x07, 0x2863 },
2851                 { 0x08, 0x059c },
2852                 { 0x09, 0x26b4 },
2853                 { 0x0a, 0x6a19 },
2854                 { 0x0b, 0xdcc8 },
2855                 { 0x10, 0xf06d },
2856                 { 0x14, 0x7f68 },
2857                 { 0x18, 0x7fd9 },
2858                 { 0x1c, 0xf0ff },
2859                 { 0x1d, 0x3d9c },
2860                 { 0x1f, 0x0003 },
2861                 { 0x12, 0xf49f },
2862                 { 0x13, 0x070b },
2863                 { 0x1a, 0x05ad },
2864                 { 0x14, 0x94c0 },
2865
2866                 /*
2867                  * Tx Error Issue
2868                  * Enhance line driver power
2869                  */
2870                 { 0x1f, 0x0002 },
2871                 { 0x06, 0x5561 },
2872                 { 0x1f, 0x0005 },
2873                 { 0x05, 0x8332 },
2874                 { 0x06, 0x5561 },
2875
2876                 /*
2877                  * Can not link to 1Gbps with bad cable
2878                  * Decrease SNR threshold form 21.07dB to 19.04dB
2879                  */
2880                 { 0x1f, 0x0001 },
2881                 { 0x17, 0x0cc0 },
2882
2883                 { 0x1f, 0x0000 },
2884                 { 0x0d, 0xf880 }
2885         };
2886
2887         rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2888
2889         /*
2890          * Rx Error Issue
2891          * Fine Tune Switching regulator parameter
2892          */
2893         rtl_writephy(tp, 0x1f, 0x0002);
2894         rtl_w0w1_phy(tp, 0x0b, 0x0010, 0x00ef);
2895         rtl_w0w1_phy(tp, 0x0c, 0xa200, 0x5d00);
2896
2897         if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
2898                 static const struct phy_reg phy_reg_init[] = {
2899                         { 0x1f, 0x0002 },
2900                         { 0x05, 0x669a },
2901                         { 0x1f, 0x0005 },
2902                         { 0x05, 0x8330 },
2903                         { 0x06, 0x669a },
2904                         { 0x1f, 0x0002 }
2905                 };
2906                 int val;
2907
2908                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2909
2910                 val = rtl_readphy(tp, 0x0d);
2911
2912                 if ((val & 0x00ff) != 0x006c) {
2913                         static const u32 set[] = {
2914                                 0x0065, 0x0066, 0x0067, 0x0068,
2915                                 0x0069, 0x006a, 0x006b, 0x006c
2916                         };
2917                         int i;
2918
2919                         rtl_writephy(tp, 0x1f, 0x0002);
2920
2921                         val &= 0xff00;
2922                         for (i = 0; i < ARRAY_SIZE(set); i++)
2923                                 rtl_writephy(tp, 0x0d, val | set[i]);
2924                 }
2925         } else {
2926                 static const struct phy_reg phy_reg_init[] = {
2927                         { 0x1f, 0x0002 },
2928                         { 0x05, 0x6662 },
2929                         { 0x1f, 0x0005 },
2930                         { 0x05, 0x8330 },
2931                         { 0x06, 0x6662 }
2932                 };
2933
2934                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2935         }
2936
2937         /* RSET couple improve */
2938         rtl_writephy(tp, 0x1f, 0x0002);
2939         rtl_patchphy(tp, 0x0d, 0x0300);
2940         rtl_patchphy(tp, 0x0f, 0x0010);
2941
2942         /* Fine tune PLL performance */
2943         rtl_writephy(tp, 0x1f, 0x0002);
2944         rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
2945         rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
2946
2947         rtl_writephy(tp, 0x1f, 0x0005);
2948         rtl_writephy(tp, 0x05, 0x001b);
2949
2950         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
2951
2952         rtl_writephy(tp, 0x1f, 0x0000);
2953 }
2954
2955 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
2956 {
2957         static const struct phy_reg phy_reg_init_0[] = {
2958                 /* Channel Estimation */
2959                 { 0x1f, 0x0001 },
2960                 { 0x06, 0x4064 },
2961                 { 0x07, 0x2863 },
2962                 { 0x08, 0x059c },
2963                 { 0x09, 0x26b4 },
2964                 { 0x0a, 0x6a19 },
2965                 { 0x0b, 0xdcc8 },
2966                 { 0x10, 0xf06d },
2967                 { 0x14, 0x7f68 },
2968                 { 0x18, 0x7fd9 },
2969                 { 0x1c, 0xf0ff },
2970                 { 0x1d, 0x3d9c },
2971                 { 0x1f, 0x0003 },
2972                 { 0x12, 0xf49f },
2973                 { 0x13, 0x070b },
2974                 { 0x1a, 0x05ad },
2975                 { 0x14, 0x94c0 },
2976
2977                 /*
2978                  * Tx Error Issue
2979                  * Enhance line driver power
2980                  */
2981                 { 0x1f, 0x0002 },
2982                 { 0x06, 0x5561 },
2983                 { 0x1f, 0x0005 },
2984                 { 0x05, 0x8332 },
2985                 { 0x06, 0x5561 },
2986
2987                 /*
2988                  * Can not link to 1Gbps with bad cable
2989                  * Decrease SNR threshold form 21.07dB to 19.04dB
2990                  */
2991                 { 0x1f, 0x0001 },
2992                 { 0x17, 0x0cc0 },
2993
2994                 { 0x1f, 0x0000 },
2995                 { 0x0d, 0xf880 }
2996         };
2997
2998         rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2999
3000         if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
3001                 static const struct phy_reg phy_reg_init[] = {
3002                         { 0x1f, 0x0002 },
3003                         { 0x05, 0x669a },
3004                         { 0x1f, 0x0005 },
3005                         { 0x05, 0x8330 },
3006                         { 0x06, 0x669a },
3007
3008                         { 0x1f, 0x0002 }
3009                 };
3010                 int val;
3011
3012                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3013
3014                 val = rtl_readphy(tp, 0x0d);
3015                 if ((val & 0x00ff) != 0x006c) {
3016                         static const u32 set[] = {
3017                                 0x0065, 0x0066, 0x0067, 0x0068,
3018                                 0x0069, 0x006a, 0x006b, 0x006c
3019                         };
3020                         int i;
3021
3022                         rtl_writephy(tp, 0x1f, 0x0002);
3023
3024                         val &= 0xff00;
3025                         for (i = 0; i < ARRAY_SIZE(set); i++)
3026                                 rtl_writephy(tp, 0x0d, val | set[i]);
3027                 }
3028         } else {
3029                 static const struct phy_reg phy_reg_init[] = {
3030                         { 0x1f, 0x0002 },
3031                         { 0x05, 0x2642 },
3032                         { 0x1f, 0x0005 },
3033                         { 0x05, 0x8330 },
3034                         { 0x06, 0x2642 }
3035                 };
3036
3037                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3038         }
3039
3040         /* Fine tune PLL performance */
3041         rtl_writephy(tp, 0x1f, 0x0002);
3042         rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
3043         rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
3044
3045         /* Switching regulator Slew rate */
3046         rtl_writephy(tp, 0x1f, 0x0002);
3047         rtl_patchphy(tp, 0x0f, 0x0017);
3048
3049         rtl_writephy(tp, 0x1f, 0x0005);
3050         rtl_writephy(tp, 0x05, 0x001b);
3051
3052         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
3053
3054         rtl_writephy(tp, 0x1f, 0x0000);
3055 }
3056
3057 static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
3058 {
3059         static const struct phy_reg phy_reg_init[] = {
3060                 { 0x1f, 0x0002 },
3061                 { 0x10, 0x0008 },
3062                 { 0x0d, 0x006c },
3063
3064                 { 0x1f, 0x0000 },
3065                 { 0x0d, 0xf880 },
3066
3067                 { 0x1f, 0x0001 },
3068                 { 0x17, 0x0cc0 },
3069
3070                 { 0x1f, 0x0001 },
3071                 { 0x0b, 0xa4d8 },
3072                 { 0x09, 0x281c },
3073                 { 0x07, 0x2883 },
3074                 { 0x0a, 0x6b35 },
3075                 { 0x1d, 0x3da4 },
3076                 { 0x1c, 0xeffd },
3077                 { 0x14, 0x7f52 },
3078                 { 0x18, 0x7fc6 },
3079                 { 0x08, 0x0601 },
3080                 { 0x06, 0x4063 },
3081                 { 0x10, 0xf074 },
3082                 { 0x1f, 0x0003 },
3083                 { 0x13, 0x0789 },
3084                 { 0x12, 0xf4bd },
3085                 { 0x1a, 0x04fd },
3086                 { 0x14, 0x84b0 },
3087                 { 0x1f, 0x0000 },
3088                 { 0x00, 0x9200 },
3089
3090                 { 0x1f, 0x0005 },
3091                 { 0x01, 0x0340 },
3092                 { 0x1f, 0x0001 },
3093                 { 0x04, 0x4000 },
3094                 { 0x03, 0x1d21 },
3095                 { 0x02, 0x0c32 },
3096                 { 0x01, 0x0200 },
3097                 { 0x00, 0x5554 },
3098                 { 0x04, 0x4800 },
3099                 { 0x04, 0x4000 },
3100                 { 0x04, 0xf000 },
3101                 { 0x03, 0xdf01 },
3102                 { 0x02, 0xdf20 },
3103                 { 0x01, 0x101a },
3104                 { 0x00, 0xa0ff },
3105                 { 0x04, 0xf800 },
3106                 { 0x04, 0xf000 },
3107                 { 0x1f, 0x0000 },
3108
3109                 { 0x1f, 0x0007 },
3110                 { 0x1e, 0x0023 },
3111                 { 0x16, 0x0000 },
3112                 { 0x1f, 0x0000 }
3113         };
3114
3115         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3116 }
3117
3118 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
3119 {
3120         static const struct phy_reg phy_reg_init[] = {
3121                 { 0x1f, 0x0001 },
3122                 { 0x17, 0x0cc0 },
3123
3124                 { 0x1f, 0x0007 },
3125                 { 0x1e, 0x002d },
3126                 { 0x18, 0x0040 },
3127                 { 0x1f, 0x0000 }
3128         };
3129
3130         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3131         rtl_patchphy(tp, 0x0d, 1 << 5);
3132 }
3133
3134 static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
3135 {
3136         static const struct phy_reg phy_reg_init[] = {
3137                 /* Enable Delay cap */
3138                 { 0x1f, 0x0005 },
3139                 { 0x05, 0x8b80 },
3140                 { 0x06, 0xc896 },
3141                 { 0x1f, 0x0000 },
3142
3143                 /* Channel estimation fine tune */
3144                 { 0x1f, 0x0001 },
3145                 { 0x0b, 0x6c20 },
3146                 { 0x07, 0x2872 },
3147                 { 0x1c, 0xefff },
3148                 { 0x1f, 0x0003 },
3149                 { 0x14, 0x6420 },
3150                 { 0x1f, 0x0000 },
3151
3152                 /* Update PFM & 10M TX idle timer */
3153                 { 0x1f, 0x0007 },
3154                 { 0x1e, 0x002f },
3155                 { 0x15, 0x1919 },
3156                 { 0x1f, 0x0000 },
3157
3158                 { 0x1f, 0x0007 },
3159                 { 0x1e, 0x00ac },
3160                 { 0x18, 0x0006 },
3161                 { 0x1f, 0x0000 }
3162         };
3163
3164         rtl_apply_firmware(tp);
3165
3166         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3167
3168         /* DCO enable for 10M IDLE Power */
3169         rtl_writephy(tp, 0x1f, 0x0007);
3170         rtl_writephy(tp, 0x1e, 0x0023);
3171         rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
3172         rtl_writephy(tp, 0x1f, 0x0000);
3173
3174         /* For impedance matching */
3175         rtl_writephy(tp, 0x1f, 0x0002);
3176         rtl_w0w1_phy(tp, 0x08, 0x8000, 0x7f00);
3177         rtl_writephy(tp, 0x1f, 0x0000);
3178
3179         /* PHY auto speed down */
3180         rtl_writephy(tp, 0x1f, 0x0007);
3181         rtl_writephy(tp, 0x1e, 0x002d);
3182         rtl_w0w1_phy(tp, 0x18, 0x0050, 0x0000);
3183         rtl_writephy(tp, 0x1f, 0x0000);
3184         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3185
3186         rtl_writephy(tp, 0x1f, 0x0005);
3187         rtl_writephy(tp, 0x05, 0x8b86);
3188         rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3189         rtl_writephy(tp, 0x1f, 0x0000);
3190
3191         rtl_writephy(tp, 0x1f, 0x0005);
3192         rtl_writephy(tp, 0x05, 0x8b85);
3193         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
3194         rtl_writephy(tp, 0x1f, 0x0007);
3195         rtl_writephy(tp, 0x1e, 0x0020);
3196         rtl_w0w1_phy(tp, 0x15, 0x0000, 0x1100);
3197         rtl_writephy(tp, 0x1f, 0x0006);
3198         rtl_writephy(tp, 0x00, 0x5a00);
3199         rtl_writephy(tp, 0x1f, 0x0000);
3200         rtl_writephy(tp, 0x0d, 0x0007);
3201         rtl_writephy(tp, 0x0e, 0x003c);
3202         rtl_writephy(tp, 0x0d, 0x4007);
3203         rtl_writephy(tp, 0x0e, 0x0000);
3204         rtl_writephy(tp, 0x0d, 0x0000);
3205 }
3206
3207 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, u8 *addr)
3208 {
3209         const u16 w[] = {
3210                 addr[0] | (addr[1] << 8),
3211                 addr[2] | (addr[3] << 8),
3212                 addr[4] | (addr[5] << 8)
3213         };
3214         const struct exgmac_reg e[] = {
3215                 { .addr = 0xe0, ERIAR_MASK_1111, .val = w[0] | (w[1] << 16) },
3216                 { .addr = 0xe4, ERIAR_MASK_1111, .val = w[2] },
3217                 { .addr = 0xf0, ERIAR_MASK_1111, .val = w[0] << 16 },
3218                 { .addr = 0xf4, ERIAR_MASK_1111, .val = w[1] | (w[2] << 16) }
3219         };
3220
3221         rtl_write_exgmac_batch(tp, e, ARRAY_SIZE(e));
3222 }
3223
3224 static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
3225 {
3226         static const struct phy_reg phy_reg_init[] = {
3227                 /* Enable Delay cap */
3228                 { 0x1f, 0x0004 },
3229                 { 0x1f, 0x0007 },
3230                 { 0x1e, 0x00ac },
3231                 { 0x18, 0x0006 },
3232                 { 0x1f, 0x0002 },
3233                 { 0x1f, 0x0000 },
3234                 { 0x1f, 0x0000 },
3235
3236                 /* Channel estimation fine tune */
3237                 { 0x1f, 0x0003 },
3238                 { 0x09, 0xa20f },
3239                 { 0x1f, 0x0000 },
3240                 { 0x1f, 0x0000 },
3241
3242                 /* Green Setting */
3243                 { 0x1f, 0x0005 },
3244                 { 0x05, 0x8b5b },
3245                 { 0x06, 0x9222 },
3246                 { 0x05, 0x8b6d },
3247                 { 0x06, 0x8000 },
3248                 { 0x05, 0x8b76 },
3249                 { 0x06, 0x8000 },
3250                 { 0x1f, 0x0000 }
3251         };
3252
3253         rtl_apply_firmware(tp);
3254
3255         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3256
3257         /* For 4-corner performance improve */
3258         rtl_writephy(tp, 0x1f, 0x0005);
3259         rtl_writephy(tp, 0x05, 0x8b80);
3260         rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
3261         rtl_writephy(tp, 0x1f, 0x0000);
3262
3263         /* PHY auto speed down */
3264         rtl_writephy(tp, 0x1f, 0x0004);
3265         rtl_writephy(tp, 0x1f, 0x0007);
3266         rtl_writephy(tp, 0x1e, 0x002d);
3267         rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
3268         rtl_writephy(tp, 0x1f, 0x0002);
3269         rtl_writephy(tp, 0x1f, 0x0000);
3270         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3271
3272         /* improve 10M EEE waveform */
3273         rtl_writephy(tp, 0x1f, 0x0005);
3274         rtl_writephy(tp, 0x05, 0x8b86);
3275         rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3276         rtl_writephy(tp, 0x1f, 0x0000);
3277
3278         /* Improve 2-pair detection performance */
3279         rtl_writephy(tp, 0x1f, 0x0005);
3280         rtl_writephy(tp, 0x05, 0x8b85);
3281         rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3282         rtl_writephy(tp, 0x1f, 0x0000);
3283
3284         /* EEE setting */
3285         rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_1111, 0x0003, 0x0000, ERIAR_EXGMAC);
3286         rtl_writephy(tp, 0x1f, 0x0005);
3287         rtl_writephy(tp, 0x05, 0x8b85);
3288         rtl_w0w1_phy(tp, 0x06, 0x2000, 0x0000);
3289         rtl_writephy(tp, 0x1f, 0x0004);
3290         rtl_writephy(tp, 0x1f, 0x0007);
3291         rtl_writephy(tp, 0x1e, 0x0020);
3292         rtl_w0w1_phy(tp, 0x15, 0x0100, 0x0000);
3293         rtl_writephy(tp, 0x1f, 0x0002);
3294         rtl_writephy(tp, 0x1f, 0x0000);
3295         rtl_writephy(tp, 0x0d, 0x0007);
3296         rtl_writephy(tp, 0x0e, 0x003c);
3297         rtl_writephy(tp, 0x0d, 0x4007);
3298         rtl_writephy(tp, 0x0e, 0x0006);
3299         rtl_writephy(tp, 0x0d, 0x0000);
3300
3301         /* Green feature */
3302         rtl_writephy(tp, 0x1f, 0x0003);
3303         rtl_w0w1_phy(tp, 0x19, 0x0001, 0x0000);
3304         rtl_w0w1_phy(tp, 0x10, 0x0400, 0x0000);
3305         rtl_writephy(tp, 0x1f, 0x0000);
3306         rtl_writephy(tp, 0x1f, 0x0005);
3307         rtl_w0w1_phy(tp, 0x01, 0x0100, 0x0000);
3308         rtl_writephy(tp, 0x1f, 0x0000);
3309
3310         /* Broken BIOS workaround: feed GigaMAC registers with MAC address. */
3311         rtl_rar_exgmac_set(tp, tp->dev->dev_addr);
3312 }
3313
3314 static void rtl8168f_hw_phy_config(struct rtl8169_private *tp)
3315 {
3316         /* For 4-corner performance improve */
3317         rtl_writephy(tp, 0x1f, 0x0005);
3318         rtl_writephy(tp, 0x05, 0x8b80);
3319         rtl_w0w1_phy(tp, 0x06, 0x0006, 0x0000);
3320         rtl_writephy(tp, 0x1f, 0x0000);
3321
3322         /* PHY auto speed down */
3323         rtl_writephy(tp, 0x1f, 0x0007);
3324         rtl_writephy(tp, 0x1e, 0x002d);
3325         rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
3326         rtl_writephy(tp, 0x1f, 0x0000);
3327         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3328
3329         /* Improve 10M EEE waveform */
3330         rtl_writephy(tp, 0x1f, 0x0005);
3331         rtl_writephy(tp, 0x05, 0x8b86);
3332         rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3333         rtl_writephy(tp, 0x1f, 0x0000);
3334 }
3335
3336 static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp)
3337 {
3338         static const struct phy_reg phy_reg_init[] = {
3339                 /* Channel estimation fine tune */
3340                 { 0x1f, 0x0003 },
3341                 { 0x09, 0xa20f },
3342                 { 0x1f, 0x0000 },
3343
3344                 /* Modify green table for giga & fnet */
3345                 { 0x1f, 0x0005 },
3346                 { 0x05, 0x8b55 },
3347                 { 0x06, 0x0000 },
3348                 { 0x05, 0x8b5e },
3349                 { 0x06, 0x0000 },
3350                 { 0x05, 0x8b67 },
3351                 { 0x06, 0x0000 },
3352                 { 0x05, 0x8b70 },
3353                 { 0x06, 0x0000 },
3354                 { 0x1f, 0x0000 },
3355                 { 0x1f, 0x0007 },
3356                 { 0x1e, 0x0078 },
3357                 { 0x17, 0x0000 },
3358                 { 0x19, 0x00fb },
3359                 { 0x1f, 0x0000 },
3360
3361                 /* Modify green table for 10M */
3362                 { 0x1f, 0x0005 },
3363                 { 0x05, 0x8b79 },
3364                 { 0x06, 0xaa00 },
3365                 { 0x1f, 0x0000 },
3366
3367                 /* Disable hiimpedance detection (RTCT) */
3368                 { 0x1f, 0x0003 },
3369                 { 0x01, 0x328a },
3370                 { 0x1f, 0x0000 }
3371         };
3372
3373         rtl_apply_firmware(tp);
3374
3375         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3376
3377         rtl8168f_hw_phy_config(tp);
3378
3379         /* Improve 2-pair detection performance */
3380         rtl_writephy(tp, 0x1f, 0x0005);
3381         rtl_writephy(tp, 0x05, 0x8b85);
3382         rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3383         rtl_writephy(tp, 0x1f, 0x0000);
3384 }
3385
3386 static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp)
3387 {
3388         rtl_apply_firmware(tp);
3389
3390         rtl8168f_hw_phy_config(tp);
3391 }
3392
3393 static void rtl8411_hw_phy_config(struct rtl8169_private *tp)
3394 {
3395         static const struct phy_reg phy_reg_init[] = {
3396                 /* Channel estimation fine tune */
3397                 { 0x1f, 0x0003 },
3398                 { 0x09, 0xa20f },
3399                 { 0x1f, 0x0000 },
3400
3401                 /* Modify green table for giga & fnet */
3402                 { 0x1f, 0x0005 },
3403                 { 0x05, 0x8b55 },
3404                 { 0x06, 0x0000 },
3405                 { 0x05, 0x8b5e },
3406                 { 0x06, 0x0000 },
3407                 { 0x05, 0x8b67 },
3408                 { 0x06, 0x0000 },
3409                 { 0x05, 0x8b70 },
3410                 { 0x06, 0x0000 },
3411                 { 0x1f, 0x0000 },
3412                 { 0x1f, 0x0007 },
3413                 { 0x1e, 0x0078 },
3414                 { 0x17, 0x0000 },
3415                 { 0x19, 0x00aa },
3416                 { 0x1f, 0x0000 },
3417
3418                 /* Modify green table for 10M */
3419                 { 0x1f, 0x0005 },
3420                 { 0x05, 0x8b79 },
3421                 { 0x06, 0xaa00 },
3422                 { 0x1f, 0x0000 },
3423
3424                 /* Disable hiimpedance detection (RTCT) */
3425                 { 0x1f, 0x0003 },
3426                 { 0x01, 0x328a },
3427                 { 0x1f, 0x0000 }
3428         };
3429
3430
3431         rtl_apply_firmware(tp);
3432
3433         rtl8168f_hw_phy_config(tp);
3434
3435         /* Improve 2-pair detection performance */
3436         rtl_writephy(tp, 0x1f, 0x0005);
3437         rtl_writephy(tp, 0x05, 0x8b85);
3438         rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3439         rtl_writephy(tp, 0x1f, 0x0000);
3440
3441         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3442
3443         /* Modify green table for giga */
3444         rtl_writephy(tp, 0x1f, 0x0005);
3445         rtl_writephy(tp, 0x05, 0x8b54);
3446         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
3447         rtl_writephy(tp, 0x05, 0x8b5d);
3448         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
3449         rtl_writephy(tp, 0x05, 0x8a7c);
3450         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3451         rtl_writephy(tp, 0x05, 0x8a7f);
3452         rtl_w0w1_phy(tp, 0x06, 0x0100, 0x0000);
3453         rtl_writephy(tp, 0x05, 0x8a82);
3454         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3455         rtl_writephy(tp, 0x05, 0x8a85);
3456         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3457         rtl_writephy(tp, 0x05, 0x8a88);
3458         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3459         rtl_writephy(tp, 0x1f, 0x0000);
3460
3461         /* uc same-seed solution */
3462         rtl_writephy(tp, 0x1f, 0x0005);
3463         rtl_writephy(tp, 0x05, 0x8b85);
3464         rtl_w0w1_phy(tp, 0x06, 0x8000, 0x0000);
3465         rtl_writephy(tp, 0x1f, 0x0000);
3466
3467         /* eee setting */
3468         rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x00, 0x03, ERIAR_EXGMAC);
3469         rtl_writephy(tp, 0x1f, 0x0005);
3470         rtl_writephy(tp, 0x05, 0x8b85);
3471         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
3472         rtl_writephy(tp, 0x1f, 0x0004);
3473         rtl_writephy(tp, 0x1f, 0x0007);
3474         rtl_writephy(tp, 0x1e, 0x0020);
3475         rtl_w0w1_phy(tp, 0x15, 0x0000, 0x0100);
3476         rtl_writephy(tp, 0x1f, 0x0000);
3477         rtl_writephy(tp, 0x0d, 0x0007);
3478         rtl_writephy(tp, 0x0e, 0x003c);
3479         rtl_writephy(tp, 0x0d, 0x4007);
3480         rtl_writephy(tp, 0x0e, 0x0000);
3481         rtl_writephy(tp, 0x0d, 0x0000);
3482
3483         /* Green feature */
3484         rtl_writephy(tp, 0x1f, 0x0003);
3485         rtl_w0w1_phy(tp, 0x19, 0x0000, 0x0001);
3486         rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0400);
3487         rtl_writephy(tp, 0x1f, 0x0000);
3488 }
3489
3490 static void rtl8168g_1_hw_phy_config(struct rtl8169_private *tp)
3491 {
3492         rtl_apply_firmware(tp);
3493
3494         rtl_writephy(tp, 0x1f, 0x0a46);
3495         if (rtl_readphy(tp, 0x10) & 0x0100) {
3496                 rtl_writephy(tp, 0x1f, 0x0bcc);
3497                 rtl_w0w1_phy(tp, 0x12, 0x0000, 0x8000);
3498         } else {
3499                 rtl_writephy(tp, 0x1f, 0x0bcc);
3500                 rtl_w0w1_phy(tp, 0x12, 0x8000, 0x0000);
3501         }
3502
3503         rtl_writephy(tp, 0x1f, 0x0a46);
3504         if (rtl_readphy(tp, 0x13) & 0x0100) {
3505                 rtl_writephy(tp, 0x1f, 0x0c41);
3506                 rtl_w0w1_phy(tp, 0x15, 0x0002, 0x0000);
3507         } else {
3508                 rtl_writephy(tp, 0x1f, 0x0c41);
3509                 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x0002);
3510         }
3511
3512         /* Enable PHY auto speed down */
3513         rtl_writephy(tp, 0x1f, 0x0a44);
3514         rtl_w0w1_phy(tp, 0x11, 0x000c, 0x0000);
3515
3516         rtl_writephy(tp, 0x1f, 0x0bcc);
3517         rtl_w0w1_phy(tp, 0x14, 0x0100, 0x0000);
3518         rtl_writephy(tp, 0x1f, 0x0a44);
3519         rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
3520         rtl_writephy(tp, 0x1f, 0x0a43);
3521         rtl_writephy(tp, 0x13, 0x8084);
3522         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
3523         rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
3524
3525         /* EEE auto-fallback function */
3526         rtl_writephy(tp, 0x1f, 0x0a4b);
3527         rtl_w0w1_phy(tp, 0x11, 0x0004, 0x0000);
3528
3529         /* Enable UC LPF tune function */
3530         rtl_writephy(tp, 0x1f, 0x0a43);
3531         rtl_writephy(tp, 0x13, 0x8012);
3532         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3533
3534         rtl_writephy(tp, 0x1f, 0x0c42);
3535         rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
3536
3537         /* Improve SWR Efficiency */
3538         rtl_writephy(tp, 0x1f, 0x0bcd);
3539         rtl_writephy(tp, 0x14, 0x5065);
3540         rtl_writephy(tp, 0x14, 0xd065);
3541         rtl_writephy(tp, 0x1f, 0x0bc8);
3542         rtl_writephy(tp, 0x11, 0x5655);
3543         rtl_writephy(tp, 0x1f, 0x0bcd);
3544         rtl_writephy(tp, 0x14, 0x1065);
3545         rtl_writephy(tp, 0x14, 0x9065);
3546         rtl_writephy(tp, 0x14, 0x1065);
3547
3548         /* Check ALDPS bit, disable it if enabled */
3549         rtl_writephy(tp, 0x1f, 0x0a43);
3550         if (rtl_readphy(tp, 0x10) & 0x0004)
3551                 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
3552
3553         rtl_writephy(tp, 0x1f, 0x0000);
3554 }
3555
3556 static void rtl8168g_2_hw_phy_config(struct rtl8169_private *tp)
3557 {
3558         rtl_apply_firmware(tp);
3559 }
3560
3561 static void rtl8168h_1_hw_phy_config(struct rtl8169_private *tp)
3562 {
3563         u16 dout_tapbin;
3564         u32 data;
3565
3566         rtl_apply_firmware(tp);
3567
3568         /* CHN EST parameters adjust - giga master */
3569         rtl_writephy(tp, 0x1f, 0x0a43);
3570         rtl_writephy(tp, 0x13, 0x809b);
3571         rtl_w0w1_phy(tp, 0x14, 0x8000, 0xf800);
3572         rtl_writephy(tp, 0x13, 0x80a2);
3573         rtl_w0w1_phy(tp, 0x14, 0x8000, 0xff00);
3574         rtl_writephy(tp, 0x13, 0x80a4);
3575         rtl_w0w1_phy(tp, 0x14, 0x8500, 0xff00);
3576         rtl_writephy(tp, 0x13, 0x809c);
3577         rtl_w0w1_phy(tp, 0x14, 0xbd00, 0xff00);
3578         rtl_writephy(tp, 0x1f, 0x0000);
3579
3580         /* CHN EST parameters adjust - giga slave */
3581         rtl_writephy(tp, 0x1f, 0x0a43);
3582         rtl_writephy(tp, 0x13, 0x80ad);
3583         rtl_w0w1_phy(tp, 0x14, 0x7000, 0xf800);
3584         rtl_writephy(tp, 0x13, 0x80b4);
3585         rtl_w0w1_phy(tp, 0x14, 0x5000, 0xff00);
3586         rtl_writephy(tp, 0x13, 0x80ac);
3587         rtl_w0w1_phy(tp, 0x14, 0x4000, 0xff00);
3588         rtl_writephy(tp, 0x1f, 0x0000);
3589
3590         /* CHN EST parameters adjust - fnet */
3591         rtl_writephy(tp, 0x1f, 0x0a43);
3592         rtl_writephy(tp, 0x13, 0x808e);
3593         rtl_w0w1_phy(tp, 0x14, 0x1200, 0xff00);
3594         rtl_writephy(tp, 0x13, 0x8090);
3595         rtl_w0w1_phy(tp, 0x14, 0xe500, 0xff00);
3596         rtl_writephy(tp, 0x13, 0x8092);
3597         rtl_w0w1_phy(tp, 0x14, 0x9f00, 0xff00);
3598         rtl_writephy(tp, 0x1f, 0x0000);
3599
3600         /* enable R-tune & PGA-retune function */
3601         dout_tapbin = 0;
3602         rtl_writephy(tp, 0x1f, 0x0a46);
3603         data = rtl_readphy(tp, 0x13);
3604         data &= 3;
3605         data <<= 2;
3606         dout_tapbin |= data;
3607         data = rtl_readphy(tp, 0x12);
3608         data &= 0xc000;
3609         data >>= 14;
3610         dout_tapbin |= data;
3611         dout_tapbin = ~(dout_tapbin^0x08);
3612         dout_tapbin <<= 12;
3613         dout_tapbin &= 0xf000;
3614         rtl_writephy(tp, 0x1f, 0x0a43);
3615         rtl_writephy(tp, 0x13, 0x827a);
3616         rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3617         rtl_writephy(tp, 0x13, 0x827b);
3618         rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3619         rtl_writephy(tp, 0x13, 0x827c);
3620         rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3621         rtl_writephy(tp, 0x13, 0x827d);
3622         rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3623
3624         rtl_writephy(tp, 0x1f, 0x0a43);
3625         rtl_writephy(tp, 0x13, 0x0811);
3626         rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
3627         rtl_writephy(tp, 0x1f, 0x0a42);
3628         rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
3629         rtl_writephy(tp, 0x1f, 0x0000);
3630
3631         /* enable GPHY 10M */
3632         rtl_writephy(tp, 0x1f, 0x0a44);
3633         rtl_w0w1_phy(tp, 0x11, 0x0800, 0x0000);
3634         rtl_writephy(tp, 0x1f, 0x0000);
3635
3636         /* SAR ADC performance */
3637         rtl_writephy(tp, 0x1f, 0x0bca);
3638         rtl_w0w1_phy(tp, 0x17, 0x4000, 0x3000);
3639         rtl_writephy(tp, 0x1f, 0x0000);
3640
3641         rtl_writephy(tp, 0x1f, 0x0a43);
3642         rtl_writephy(tp, 0x13, 0x803f);
3643         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3644         rtl_writephy(tp, 0x13, 0x8047);
3645         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3646         rtl_writephy(tp, 0x13, 0x804f);
3647         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3648         rtl_writephy(tp, 0x13, 0x8057);
3649         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3650         rtl_writephy(tp, 0x13, 0x805f);
3651         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3652         rtl_writephy(tp, 0x13, 0x8067);
3653         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3654         rtl_writephy(tp, 0x13, 0x806f);
3655         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3656         rtl_writephy(tp, 0x1f, 0x0000);
3657
3658         /* disable phy pfm mode */
3659         rtl_writephy(tp, 0x1f, 0x0a44);
3660         rtl_w0w1_phy(tp, 0x11, 0x0000, 0x0080);
3661         rtl_writephy(tp, 0x1f, 0x0000);
3662
3663         /* Check ALDPS bit, disable it if enabled */
3664         rtl_writephy(tp, 0x1f, 0x0a43);
3665         if (rtl_readphy(tp, 0x10) & 0x0004)
3666                 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
3667
3668         rtl_writephy(tp, 0x1f, 0x0000);
3669 }
3670
3671 static void rtl8168h_2_hw_phy_config(struct rtl8169_private *tp)
3672 {
3673         u16 ioffset_p3, ioffset_p2, ioffset_p1, ioffset_p0;
3674         u16 rlen;
3675         u32 data;
3676
3677         rtl_apply_firmware(tp);
3678
3679         /* CHIN EST parameter update */
3680         rtl_writephy(tp, 0x1f, 0x0a43);
3681         rtl_writephy(tp, 0x13, 0x808a);
3682         rtl_w0w1_phy(tp, 0x14, 0x000a, 0x003f);
3683         rtl_writephy(tp, 0x1f, 0x0000);
3684
3685         /* enable R-tune & PGA-retune function */
3686         rtl_writephy(tp, 0x1f, 0x0a43);
3687         rtl_writephy(tp, 0x13, 0x0811);
3688         rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
3689         rtl_writephy(tp, 0x1f, 0x0a42);
3690         rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
3691         rtl_writephy(tp, 0x1f, 0x0000);
3692
3693         /* enable GPHY 10M */
3694         rtl_writephy(tp, 0x1f, 0x0a44);
3695         rtl_w0w1_phy(tp, 0x11, 0x0800, 0x0000);
3696         rtl_writephy(tp, 0x1f, 0x0000);
3697
3698         r8168_mac_ocp_write(tp, 0xdd02, 0x807d);
3699         data = r8168_mac_ocp_read(tp, 0xdd02);
3700         ioffset_p3 = ((data & 0x80)>>7);
3701         ioffset_p3 <<= 3;
3702
3703         data = r8168_mac_ocp_read(tp, 0xdd00);
3704         ioffset_p3 |= ((data & (0xe000))>>13);
3705         ioffset_p2 = ((data & (0x1e00))>>9);
3706         ioffset_p1 = ((data & (0x01e0))>>5);
3707         ioffset_p0 = ((data & 0x0010)>>4);
3708         ioffset_p0 <<= 3;
3709         ioffset_p0 |= (data & (0x07));
3710         data = (ioffset_p3<<12)|(ioffset_p2<<8)|(ioffset_p1<<4)|(ioffset_p0);
3711
3712         if ((ioffset_p3 != 0x0f) || (ioffset_p2 != 0x0f) ||
3713             (ioffset_p1 != 0x0f) || (ioffset_p0 != 0x0f)) {
3714                 rtl_writephy(tp, 0x1f, 0x0bcf);
3715                 rtl_writephy(tp, 0x16, data);
3716                 rtl_writephy(tp, 0x1f, 0x0000);
3717         }
3718
3719         /* Modify rlen (TX LPF corner frequency) level */
3720         rtl_writephy(tp, 0x1f, 0x0bcd);
3721         data = rtl_readphy(tp, 0x16);
3722         data &= 0x000f;
3723         rlen = 0;
3724         if (data > 3)
3725                 rlen = data - 3;
3726         data = rlen | (rlen<<4) | (rlen<<8) | (rlen<<12);
3727         rtl_writephy(tp, 0x17, data);
3728         rtl_writephy(tp, 0x1f, 0x0bcd);
3729         rtl_writephy(tp, 0x1f, 0x0000);
3730
3731         /* disable phy pfm mode */
3732         rtl_writephy(tp, 0x1f, 0x0a44);
3733         rtl_w0w1_phy(tp, 0x11, 0x0000, 0x0080);
3734         rtl_writephy(tp, 0x1f, 0x0000);
3735
3736         /* Check ALDPS bit, disable it if enabled */
3737         rtl_writephy(tp, 0x1f, 0x0a43);
3738         if (rtl_readphy(tp, 0x10) & 0x0004)
3739                 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
3740
3741         rtl_writephy(tp, 0x1f, 0x0000);
3742 }
3743
3744 static void rtl8168ep_1_hw_phy_config(struct rtl8169_private *tp)
3745 {
3746         /* Enable PHY auto speed down */
3747         rtl_writephy(tp, 0x1f, 0x0a44);
3748         rtl_w0w1_phy(tp, 0x11, 0x000c, 0x0000);
3749         rtl_writephy(tp, 0x1f, 0x0000);
3750
3751         /* patch 10M & ALDPS */
3752         rtl_writephy(tp, 0x1f, 0x0bcc);
3753         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x0100);
3754         rtl_writephy(tp, 0x1f, 0x0a44);
3755         rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
3756         rtl_writephy(tp, 0x1f, 0x0a43);
3757         rtl_writephy(tp, 0x13, 0x8084);
3758         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
3759         rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
3760         rtl_writephy(tp, 0x1f, 0x0000);
3761
3762         /* Enable EEE auto-fallback function */
3763         rtl_writephy(tp, 0x1f, 0x0a4b);
3764         rtl_w0w1_phy(tp, 0x11, 0x0004, 0x0000);
3765         rtl_writephy(tp, 0x1f, 0x0000);
3766
3767         /* Enable UC LPF tune function */
3768         rtl_writephy(tp, 0x1f, 0x0a43);
3769         rtl_writephy(tp, 0x13, 0x8012);
3770         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3771         rtl_writephy(tp, 0x1f, 0x0000);
3772
3773         /* set rg_sel_sdm_rate */
3774         rtl_writephy(tp, 0x1f, 0x0c42);
3775         rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
3776         rtl_writephy(tp, 0x1f, 0x0000);
3777
3778         /* Check ALDPS bit, disable it if enabled */
3779         rtl_writephy(tp, 0x1f, 0x0a43);
3780         if (rtl_readphy(tp, 0x10) & 0x0004)
3781                 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
3782
3783         rtl_writephy(tp, 0x1f, 0x0000);
3784 }
3785
3786 static void rtl8168ep_2_hw_phy_config(struct rtl8169_private *tp)
3787 {
3788         /* patch 10M & ALDPS */
3789         rtl_writephy(tp, 0x1f, 0x0bcc);
3790         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x0100);
3791         rtl_writephy(tp, 0x1f, 0x0a44);
3792         rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
3793         rtl_writephy(tp, 0x1f, 0x0a43);
3794         rtl_writephy(tp, 0x13, 0x8084);
3795         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
3796         rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
3797         rtl_writephy(tp, 0x1f, 0x0000);
3798
3799         /* Enable UC LPF tune function */
3800         rtl_writephy(tp, 0x1f, 0x0a43);
3801         rtl_writephy(tp, 0x13, 0x8012);
3802         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3803         rtl_writephy(tp, 0x1f, 0x0000);
3804
3805         /* Set rg_sel_sdm_rate */
3806         rtl_writephy(tp, 0x1f, 0x0c42);
3807         rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
3808         rtl_writephy(tp, 0x1f, 0x0000);
3809
3810         /* Channel estimation parameters */
3811         rtl_writephy(tp, 0x1f, 0x0a43);
3812         rtl_writephy(tp, 0x13, 0x80f3);
3813         rtl_w0w1_phy(tp, 0x14, 0x8b00, ~0x8bff);
3814         rtl_writephy(tp, 0x13, 0x80f0);
3815         rtl_w0w1_phy(tp, 0x14, 0x3a00, ~0x3aff);
3816         rtl_writephy(tp, 0x13, 0x80ef);
3817         rtl_w0w1_phy(tp, 0x14, 0x0500, ~0x05ff);
3818         rtl_writephy(tp, 0x13, 0x80f6);
3819         rtl_w0w1_phy(tp, 0x14, 0x6e00, ~0x6eff);
3820         rtl_writephy(tp, 0x13, 0x80ec);
3821         rtl_w0w1_phy(tp, 0x14, 0x6800, ~0x68ff);
3822         rtl_writephy(tp, 0x13, 0x80ed);
3823         rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
3824         rtl_writephy(tp, 0x13, 0x80f2);
3825         rtl_w0w1_phy(tp, 0x14, 0xf400, ~0xf4ff);
3826         rtl_writephy(tp, 0x13, 0x80f4);
3827         rtl_w0w1_phy(tp, 0x14, 0x8500, ~0x85ff);
3828         rtl_writephy(tp, 0x1f, 0x0a43);
3829         rtl_writephy(tp, 0x13, 0x8110);
3830         rtl_w0w1_phy(tp, 0x14, 0xa800, ~0xa8ff);
3831         rtl_writephy(tp, 0x13, 0x810f);
3832         rtl_w0w1_phy(tp, 0x14, 0x1d00, ~0x1dff);
3833         rtl_writephy(tp, 0x13, 0x8111);
3834         rtl_w0w1_phy(tp, 0x14, 0xf500, ~0xf5ff);
3835         rtl_writephy(tp, 0x13, 0x8113);
3836         rtl_w0w1_phy(tp, 0x14, 0x6100, ~0x61ff);
3837         rtl_writephy(tp, 0x13, 0x8115);
3838         rtl_w0w1_phy(tp, 0x14, 0x9200, ~0x92ff);
3839         rtl_writephy(tp, 0x13, 0x810e);
3840         rtl_w0w1_phy(tp, 0x14, 0x0400, ~0x04ff);
3841         rtl_writephy(tp, 0x13, 0x810c);
3842         rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
3843         rtl_writephy(tp, 0x13, 0x810b);
3844         rtl_w0w1_phy(tp, 0x14, 0x5a00, ~0x5aff);
3845         rtl_writephy(tp, 0x1f, 0x0a43);
3846         rtl_writephy(tp, 0x13, 0x80d1);
3847         rtl_w0w1_phy(tp, 0x14, 0xff00, ~0xffff);
3848         rtl_writephy(tp, 0x13, 0x80cd);
3849         rtl_w0w1_phy(tp, 0x14, 0x9e00, ~0x9eff);
3850         rtl_writephy(tp, 0x13, 0x80d3);
3851         rtl_w0w1_phy(tp, 0x14, 0x0e00, ~0x0eff);
3852         rtl_writephy(tp, 0x13, 0x80d5);
3853         rtl_w0w1_phy(tp, 0x14, 0xca00, ~0xcaff);
3854         rtl_writephy(tp, 0x13, 0x80d7);
3855         rtl_w0w1_phy(tp, 0x14, 0x8400, ~0x84ff);
3856
3857         /* Force PWM-mode */
3858         rtl_writephy(tp, 0x1f, 0x0bcd);
3859         rtl_writephy(tp, 0x14, 0x5065);
3860         rtl_writephy(tp, 0x14, 0xd065);
3861         rtl_writephy(tp, 0x1f, 0x0bc8);
3862         rtl_writephy(tp, 0x12, 0x00ed);
3863         rtl_writephy(tp, 0x1f, 0x0bcd);
3864         rtl_writephy(tp, 0x14, 0x1065);
3865         rtl_writephy(tp, 0x14, 0x9065);
3866         rtl_writephy(tp, 0x14, 0x1065);
3867         rtl_writephy(tp, 0x1f, 0x0000);
3868
3869         /* Check ALDPS bit, disable it if enabled */
3870         rtl_writephy(tp, 0x1f, 0x0a43);
3871         if (rtl_readphy(tp, 0x10) & 0x0004)
3872                 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
3873
3874         rtl_writephy(tp, 0x1f, 0x0000);
3875 }
3876
3877 static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
3878 {
3879         static const struct phy_reg phy_reg_init[] = {
3880                 { 0x1f, 0x0003 },
3881                 { 0x08, 0x441d },
3882                 { 0x01, 0x9100 },
3883                 { 0x1f, 0x0000 }
3884         };
3885
3886         rtl_writephy(tp, 0x1f, 0x0000);
3887         rtl_patchphy(tp, 0x11, 1 << 12);
3888         rtl_patchphy(tp, 0x19, 1 << 13);
3889         rtl_patchphy(tp, 0x10, 1 << 15);
3890
3891         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3892 }
3893
3894 static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
3895 {
3896         static const struct phy_reg phy_reg_init[] = {
3897                 { 0x1f, 0x0005 },
3898                 { 0x1a, 0x0000 },
3899                 { 0x1f, 0x0000 },
3900
3901                 { 0x1f, 0x0004 },
3902                 { 0x1c, 0x0000 },
3903                 { 0x1f, 0x0000 },
3904
3905                 { 0x1f, 0x0001 },
3906                 { 0x15, 0x7701 },
3907                 { 0x1f, 0x0000 }
3908         };
3909
3910         /* Disable ALDPS before ram code */
3911         rtl_writephy(tp, 0x1f, 0x0000);
3912         rtl_writephy(tp, 0x18, 0x0310);
3913         msleep(100);
3914
3915         rtl_apply_firmware(tp);
3916
3917         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3918 }
3919
3920 static void rtl8402_hw_phy_config(struct rtl8169_private *tp)
3921 {
3922         /* Disable ALDPS before setting firmware */
3923         rtl_writephy(tp, 0x1f, 0x0000);
3924         rtl_writephy(tp, 0x18, 0x0310);
3925         msleep(20);
3926
3927         rtl_apply_firmware(tp);
3928
3929         /* EEE setting */
3930         rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
3931         rtl_writephy(tp, 0x1f, 0x0004);
3932         rtl_writephy(tp, 0x10, 0x401f);
3933         rtl_writephy(tp, 0x19, 0x7030);
3934         rtl_writephy(tp, 0x1f, 0x0000);
3935 }
3936
3937 static void rtl8106e_hw_phy_config(struct rtl8169_private *tp)
3938 {
3939         static const struct phy_reg phy_reg_init[] = {
3940                 { 0x1f, 0x0004 },
3941                 { 0x10, 0xc07f },
3942                 { 0x19, 0x7030 },
3943                 { 0x1f, 0x0000 }
3944         };
3945
3946         /* Disable ALDPS before ram code */
3947         rtl_writephy(tp, 0x1f, 0x0000);
3948         rtl_writephy(tp, 0x18, 0x0310);
3949         msleep(100);
3950
3951         rtl_apply_firmware(tp);
3952
3953         rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
3954         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3955
3956         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
3957 }
3958
3959 static void rtl_hw_phy_config(struct net_device *dev)
3960 {
3961         struct rtl8169_private *tp = netdev_priv(dev);
3962
3963         rtl8169_print_mac_version(tp);
3964
3965         switch (tp->mac_version) {
3966         case RTL_GIGA_MAC_VER_01:
3967                 break;
3968         case RTL_GIGA_MAC_VER_02:
3969         case RTL_GIGA_MAC_VER_03:
3970                 rtl8169s_hw_phy_config(tp);
3971                 break;
3972         case RTL_GIGA_MAC_VER_04:
3973                 rtl8169sb_hw_phy_config(tp);
3974                 break;
3975         case RTL_GIGA_MAC_VER_05:
3976                 rtl8169scd_hw_phy_config(tp);
3977                 break;
3978         case RTL_GIGA_MAC_VER_06:
3979                 rtl8169sce_hw_phy_config(tp);
3980                 break;
3981         case RTL_GIGA_MAC_VER_07:
3982         case RTL_GIGA_MAC_VER_08:
3983         case RTL_GIGA_MAC_VER_09:
3984                 rtl8102e_hw_phy_config(tp);
3985                 break;
3986         case RTL_GIGA_MAC_VER_11:
3987                 rtl8168bb_hw_phy_config(tp);
3988                 break;
3989         case RTL_GIGA_MAC_VER_12:
3990                 rtl8168bef_hw_phy_config(tp);
3991                 break;
3992         case RTL_GIGA_MAC_VER_17:
3993                 rtl8168bef_hw_phy_config(tp);
3994                 break;
3995         case RTL_GIGA_MAC_VER_18:
3996                 rtl8168cp_1_hw_phy_config(tp);
3997                 break;
3998         case RTL_GIGA_MAC_VER_19:
3999                 rtl8168c_1_hw_phy_config(tp);
4000                 break;
4001         case RTL_GIGA_MAC_VER_20:
4002                 rtl8168c_2_hw_phy_config(tp);
4003                 break;
4004         case RTL_GIGA_MAC_VER_21:
4005                 rtl8168c_3_hw_phy_config(tp);
4006                 break;
4007         case RTL_GIGA_MAC_VER_22:
4008                 rtl8168c_4_hw_phy_config(tp);
4009                 break;
4010         case RTL_GIGA_MAC_VER_23:
4011         case RTL_GIGA_MAC_VER_24:
4012                 rtl8168cp_2_hw_phy_config(tp);
4013                 break;
4014         case RTL_GIGA_MAC_VER_25:
4015                 rtl8168d_1_hw_phy_config(tp);
4016                 break;
4017         case RTL_GIGA_MAC_VER_26:
4018                 rtl8168d_2_hw_phy_config(tp);
4019                 break;
4020         case RTL_GIGA_MAC_VER_27:
4021                 rtl8168d_3_hw_phy_config(tp);
4022                 break;
4023         case RTL_GIGA_MAC_VER_28:
4024                 rtl8168d_4_hw_phy_config(tp);
4025                 break;
4026         case RTL_GIGA_MAC_VER_29:
4027         case RTL_GIGA_MAC_VER_30:
4028                 rtl8105e_hw_phy_config(tp);
4029                 break;
4030         case RTL_GIGA_MAC_VER_31:
4031                 /* None. */
4032                 break;
4033         case RTL_GIGA_MAC_VER_32:
4034         case RTL_GIGA_MAC_VER_33:
4035                 rtl8168e_1_hw_phy_config(tp);
4036                 break;
4037         case RTL_GIGA_MAC_VER_34:
4038                 rtl8168e_2_hw_phy_config(tp);
4039                 break;
4040         case RTL_GIGA_MAC_VER_35:
4041                 rtl8168f_1_hw_phy_config(tp);
4042                 break;
4043         case RTL_GIGA_MAC_VER_36:
4044                 rtl8168f_2_hw_phy_config(tp);
4045                 break;
4046
4047         case RTL_GIGA_MAC_VER_37:
4048                 rtl8402_hw_phy_config(tp);
4049                 break;
4050
4051         case RTL_GIGA_MAC_VER_38:
4052                 rtl8411_hw_phy_config(tp);
4053                 break;
4054
4055         case RTL_GIGA_MAC_VER_39:
4056                 rtl8106e_hw_phy_config(tp);
4057                 break;
4058
4059         case RTL_GIGA_MAC_VER_40:
4060                 rtl8168g_1_hw_phy_config(tp);
4061                 break;
4062         case RTL_GIGA_MAC_VER_42:
4063         case RTL_GIGA_MAC_VER_43:
4064         case RTL_GIGA_MAC_VER_44:
4065                 rtl8168g_2_hw_phy_config(tp);
4066                 break;
4067         case RTL_GIGA_MAC_VER_45:
4068         case RTL_GIGA_MAC_VER_47:
4069                 rtl8168h_1_hw_phy_config(tp);
4070                 break;
4071         case RTL_GIGA_MAC_VER_46:
4072         case RTL_GIGA_MAC_VER_48:
4073                 rtl8168h_2_hw_phy_config(tp);
4074                 break;
4075
4076         case RTL_GIGA_MAC_VER_49:
4077                 rtl8168ep_1_hw_phy_config(tp);
4078                 break;
4079         case RTL_GIGA_MAC_VER_50:
4080         case RTL_GIGA_MAC_VER_51:
4081                 rtl8168ep_2_hw_phy_config(tp);
4082                 break;
4083
4084         case RTL_GIGA_MAC_VER_41:
4085         default:
4086                 break;
4087         }
4088 }
4089
4090 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
4091 {
4092         if (!test_and_set_bit(flag, tp->wk.flags))
4093                 schedule_work(&tp->wk.work);
4094 }
4095
4096 static bool rtl_tbi_enabled(struct rtl8169_private *tp)
4097 {
4098         return (tp->mac_version == RTL_GIGA_MAC_VER_01) &&
4099                (RTL_R8(tp, PHYstatus) & TBI_Enable);
4100 }
4101
4102 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
4103 {
4104         rtl_hw_phy_config(dev);
4105
4106         if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
4107                 netif_dbg(tp, drv, dev,
4108                           "Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
4109                 RTL_W8(tp, 0x82, 0x01);
4110         }
4111
4112         pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
4113
4114         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
4115                 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4116
4117         if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
4118                 netif_dbg(tp, drv, dev,
4119                           "Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
4120                 RTL_W8(tp, 0x82, 0x01);
4121                 netif_dbg(tp, drv, dev,
4122                           "Set PHY Reg 0x0bh = 0x00h\n");
4123                 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
4124         }
4125
4126         /* We may have called phy_speed_down before */
4127         phy_speed_up(dev->phydev);
4128
4129         genphy_soft_reset(dev->phydev);
4130 }
4131
4132 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
4133 {
4134         rtl_lock_work(tp);
4135
4136         RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
4137
4138         RTL_W32(tp, MAC4, addr[4] | addr[5] << 8);
4139         RTL_R32(tp, MAC4);
4140
4141         RTL_W32(tp, MAC0, addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24);
4142         RTL_R32(tp, MAC0);
4143
4144         if (tp->mac_version == RTL_GIGA_MAC_VER_34)
4145                 rtl_rar_exgmac_set(tp, addr);
4146
4147         RTL_W8(tp, Cfg9346, Cfg9346_Lock);
4148
4149         rtl_unlock_work(tp);
4150 }
4151
4152 static int rtl_set_mac_address(struct net_device *dev, void *p)
4153 {
4154         struct rtl8169_private *tp = netdev_priv(dev);
4155         struct device *d = tp_to_dev(tp);
4156         int ret;
4157
4158         ret = eth_mac_addr(dev, p);
4159         if (ret)
4160                 return ret;
4161
4162         pm_runtime_get_noresume(d);
4163
4164         if (pm_runtime_active(d))
4165                 rtl_rar_set(tp, dev->dev_addr);
4166
4167         pm_runtime_put_noidle(d);
4168
4169         return 0;
4170 }
4171
4172 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
4173 {
4174         if (!netif_running(dev))
4175                 return -ENODEV;
4176
4177         return phy_mii_ioctl(dev->phydev, ifr, cmd);
4178 }
4179
4180 static void rtl_init_mdio_ops(struct rtl8169_private *tp)
4181 {
4182         struct mdio_ops *ops = &tp->mdio_ops;
4183
4184         switch (tp->mac_version) {
4185         case RTL_GIGA_MAC_VER_27:
4186                 ops->write      = r8168dp_1_mdio_write;
4187                 ops->read       = r8168dp_1_mdio_read;
4188                 break;
4189         case RTL_GIGA_MAC_VER_28:
4190         case RTL_GIGA_MAC_VER_31:
4191                 ops->write      = r8168dp_2_mdio_write;
4192                 ops->read       = r8168dp_2_mdio_read;
4193                 break;
4194         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
4195                 ops->write      = r8168g_mdio_write;
4196                 ops->read       = r8168g_mdio_read;
4197                 break;
4198         default:
4199                 ops->write      = r8169_mdio_write;
4200                 ops->read       = r8169_mdio_read;
4201                 break;
4202         }
4203 }
4204
4205 static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
4206 {
4207         switch (tp->mac_version) {
4208         case RTL_GIGA_MAC_VER_25:
4209         case RTL_GIGA_MAC_VER_26:
4210         case RTL_GIGA_MAC_VER_29:
4211         case RTL_GIGA_MAC_VER_30:
4212         case RTL_GIGA_MAC_VER_32:
4213         case RTL_GIGA_MAC_VER_33:
4214         case RTL_GIGA_MAC_VER_34:
4215         case RTL_GIGA_MAC_VER_37 ... RTL_GIGA_MAC_VER_51:
4216                 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) |
4217                         AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
4218                 break;
4219         default:
4220                 break;
4221         }
4222 }
4223
4224 static bool rtl_wol_pll_power_down(struct rtl8169_private *tp)
4225 {
4226         if (!netif_running(tp->dev) || !__rtl8169_get_wol(tp))
4227                 return false;
4228
4229         phy_speed_down(tp->dev->phydev, false);
4230         rtl_wol_suspend_quirk(tp);
4231
4232         return true;
4233 }
4234
4235 static void r8168_pll_power_down(struct rtl8169_private *tp)
4236 {
4237         if (r8168_check_dash(tp))
4238                 return;
4239
4240         if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
4241             tp->mac_version == RTL_GIGA_MAC_VER_33)
4242                 rtl_ephy_write(tp, 0x19, 0xff64);
4243
4244         if (rtl_wol_pll_power_down(tp))
4245                 return;
4246
4247         switch (tp->mac_version) {
4248         case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_33:
4249         case RTL_GIGA_MAC_VER_37:
4250         case RTL_GIGA_MAC_VER_39:
4251         case RTL_GIGA_MAC_VER_43:
4252         case RTL_GIGA_MAC_VER_44:
4253         case RTL_GIGA_MAC_VER_45:
4254         case RTL_GIGA_MAC_VER_46:
4255         case RTL_GIGA_MAC_VER_47:
4256         case RTL_GIGA_MAC_VER_48:
4257         case RTL_GIGA_MAC_VER_50:
4258         case RTL_GIGA_MAC_VER_51:
4259                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80);
4260                 break;
4261         case RTL_GIGA_MAC_VER_40:
4262         case RTL_GIGA_MAC_VER_41:
4263         case RTL_GIGA_MAC_VER_49:
4264                 rtl_w0w1_eri(tp, 0x1a8, ERIAR_MASK_1111, 0x00000000,
4265                              0xfc000000, ERIAR_EXGMAC);
4266                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80);
4267                 break;
4268         }
4269 }
4270
4271 static void r8168_pll_power_up(struct rtl8169_private *tp)
4272 {
4273         switch (tp->mac_version) {
4274         case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_33:
4275         case RTL_GIGA_MAC_VER_37:
4276         case RTL_GIGA_MAC_VER_39:
4277         case RTL_GIGA_MAC_VER_43:
4278                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0x80);
4279                 break;
4280         case RTL_GIGA_MAC_VER_44:
4281         case RTL_GIGA_MAC_VER_45:
4282         case RTL_GIGA_MAC_VER_46:
4283         case RTL_GIGA_MAC_VER_47:
4284         case RTL_GIGA_MAC_VER_48:
4285         case RTL_GIGA_MAC_VER_50:
4286         case RTL_GIGA_MAC_VER_51:
4287                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0);
4288                 break;
4289         case RTL_GIGA_MAC_VER_40:
4290         case RTL_GIGA_MAC_VER_41:
4291         case RTL_GIGA_MAC_VER_49:
4292                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0);
4293                 rtl_w0w1_eri(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000,
4294                              0x00000000, ERIAR_EXGMAC);
4295                 break;
4296         }
4297
4298         phy_resume(tp->dev->phydev);
4299         /* give MAC/PHY some time to resume */
4300         msleep(20);
4301 }
4302
4303 static void rtl_pll_power_down(struct rtl8169_private *tp)
4304 {
4305         switch (tp->mac_version) {
4306         case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_06:
4307         case RTL_GIGA_MAC_VER_13 ... RTL_GIGA_MAC_VER_15:
4308                 break;
4309         default:
4310                 r8168_pll_power_down(tp);
4311         }
4312 }
4313
4314 static void rtl_pll_power_up(struct rtl8169_private *tp)
4315 {
4316         switch (tp->mac_version) {
4317         case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_06:
4318         case RTL_GIGA_MAC_VER_13 ... RTL_GIGA_MAC_VER_15:
4319                 break;
4320         default:
4321                 r8168_pll_power_up(tp);
4322         }
4323 }
4324
4325 static void rtl_init_rxcfg(struct rtl8169_private *tp)
4326 {
4327         switch (tp->mac_version) {
4328         case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_06:
4329         case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
4330                 RTL_W32(tp, RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
4331                 break;
4332         case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
4333         case RTL_GIGA_MAC_VER_34:
4334         case RTL_GIGA_MAC_VER_35:
4335                 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
4336                 break;
4337         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
4338                 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF);
4339                 break;
4340         default:
4341                 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_DMA_BURST);
4342                 break;
4343         }
4344 }
4345
4346 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
4347 {
4348         tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0;
4349 }
4350
4351 static void rtl_hw_jumbo_enable(struct rtl8169_private *tp)
4352 {
4353         if (tp->jumbo_ops.enable) {
4354                 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
4355                 tp->jumbo_ops.enable(tp);
4356                 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
4357         }
4358 }
4359
4360 static void rtl_hw_jumbo_disable(struct rtl8169_private *tp)
4361 {
4362         if (tp->jumbo_ops.disable) {
4363                 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
4364                 tp->jumbo_ops.disable(tp);
4365                 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
4366         }
4367 }
4368
4369 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
4370 {
4371         RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
4372         RTL_W8(tp, Config4, RTL_R8(tp, Config4) | Jumbo_En1);
4373         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_512B);
4374 }
4375
4376 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
4377 {
4378         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
4379         RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~Jumbo_En1);
4380         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4381 }
4382
4383 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
4384 {
4385         RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
4386 }
4387
4388 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
4389 {
4390         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
4391 }
4392
4393 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
4394 {
4395         RTL_W8(tp, MaxTxPacketSize, 0x3f);
4396         RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
4397         RTL_W8(tp, Config4, RTL_R8(tp, Config4) | 0x01);
4398         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_512B);
4399 }
4400
4401 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
4402 {
4403         RTL_W8(tp, MaxTxPacketSize, 0x0c);
4404         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
4405         RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~0x01);
4406         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4407 }
4408
4409 static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp)
4410 {
4411         rtl_tx_performance_tweak(tp,
4412                 PCI_EXP_DEVCTL_READRQ_512B | PCI_EXP_DEVCTL_NOSNOOP_EN);
4413 }
4414
4415 static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp)
4416 {
4417         rtl_tx_performance_tweak(tp,
4418                 PCI_EXP_DEVCTL_READRQ_4096B | PCI_EXP_DEVCTL_NOSNOOP_EN);
4419 }
4420
4421 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
4422 {
4423         r8168b_0_hw_jumbo_enable(tp);
4424
4425         RTL_W8(tp, Config4, RTL_R8(tp, Config4) | (1 << 0));
4426 }
4427
4428 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
4429 {
4430         r8168b_0_hw_jumbo_disable(tp);
4431
4432         RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0));
4433 }
4434
4435 static void rtl_init_jumbo_ops(struct rtl8169_private *tp)
4436 {
4437         struct jumbo_ops *ops = &tp->jumbo_ops;
4438
4439         switch (tp->mac_version) {
4440         case RTL_GIGA_MAC_VER_11:
4441                 ops->disable    = r8168b_0_hw_jumbo_disable;
4442                 ops->enable     = r8168b_0_hw_jumbo_enable;
4443                 break;
4444         case RTL_GIGA_MAC_VER_12:
4445         case RTL_GIGA_MAC_VER_17:
4446                 ops->disable    = r8168b_1_hw_jumbo_disable;
4447                 ops->enable     = r8168b_1_hw_jumbo_enable;
4448                 break;
4449         case RTL_GIGA_MAC_VER_18: /* Wild guess. Needs info from Realtek. */
4450         case RTL_GIGA_MAC_VER_19:
4451         case RTL_GIGA_MAC_VER_20:
4452         case RTL_GIGA_MAC_VER_21: /* Wild guess. Needs info from Realtek. */
4453         case RTL_GIGA_MAC_VER_22:
4454         case RTL_GIGA_MAC_VER_23:
4455         case RTL_GIGA_MAC_VER_24:
4456         case RTL_GIGA_MAC_VER_25:
4457         case RTL_GIGA_MAC_VER_26:
4458                 ops->disable    = r8168c_hw_jumbo_disable;
4459                 ops->enable     = r8168c_hw_jumbo_enable;
4460                 break;
4461         case RTL_GIGA_MAC_VER_27:
4462         case RTL_GIGA_MAC_VER_28:
4463                 ops->disable    = r8168dp_hw_jumbo_disable;
4464                 ops->enable     = r8168dp_hw_jumbo_enable;
4465                 break;
4466         case RTL_GIGA_MAC_VER_31: /* Wild guess. Needs info from Realtek. */
4467         case RTL_GIGA_MAC_VER_32:
4468         case RTL_GIGA_MAC_VER_33:
4469         case RTL_GIGA_MAC_VER_34:
4470                 ops->disable    = r8168e_hw_jumbo_disable;
4471                 ops->enable     = r8168e_hw_jumbo_enable;
4472                 break;
4473
4474         /*
4475          * No action needed for jumbo frames with 8169.
4476          * No jumbo for 810x at all.
4477          */
4478         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
4479         default:
4480                 ops->disable    = NULL;
4481                 ops->enable     = NULL;
4482                 break;
4483         }
4484 }
4485
4486 DECLARE_RTL_COND(rtl_chipcmd_cond)
4487 {
4488         return RTL_R8(tp, ChipCmd) & CmdReset;
4489 }
4490
4491 static void rtl_hw_reset(struct rtl8169_private *tp)
4492 {
4493         RTL_W8(tp, ChipCmd, CmdReset);
4494
4495         rtl_udelay_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100);
4496 }
4497
4498 static void rtl_request_uncached_firmware(struct rtl8169_private *tp)
4499 {
4500         struct rtl_fw *rtl_fw;
4501         const char *name;
4502         int rc = -ENOMEM;
4503
4504         name = rtl_lookup_firmware_name(tp);
4505         if (!name)
4506                 goto out_no_firmware;
4507
4508         rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
4509         if (!rtl_fw)
4510                 goto err_warn;
4511
4512         rc = request_firmware(&rtl_fw->fw, name, tp_to_dev(tp));
4513         if (rc < 0)
4514                 goto err_free;
4515
4516         rc = rtl_check_firmware(tp, rtl_fw);
4517         if (rc < 0)
4518                 goto err_release_firmware;
4519
4520         tp->rtl_fw = rtl_fw;
4521 out:
4522         return;
4523
4524 err_release_firmware:
4525         release_firmware(rtl_fw->fw);
4526 err_free:
4527         kfree(rtl_fw);
4528 err_warn:
4529         netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n",
4530                    name, rc);
4531 out_no_firmware:
4532         tp->rtl_fw = NULL;
4533         goto out;
4534 }
4535
4536 static void rtl_request_firmware(struct rtl8169_private *tp)
4537 {
4538         if (IS_ERR(tp->rtl_fw))
4539                 rtl_request_uncached_firmware(tp);
4540 }
4541
4542 static void rtl_rx_close(struct rtl8169_private *tp)
4543 {
4544         RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
4545 }
4546
4547 DECLARE_RTL_COND(rtl_npq_cond)
4548 {
4549         return RTL_R8(tp, TxPoll) & NPQ;
4550 }
4551
4552 DECLARE_RTL_COND(rtl_txcfg_empty_cond)
4553 {
4554         return RTL_R32(tp, TxConfig) & TXCFG_EMPTY;
4555 }
4556
4557 static void rtl8169_hw_reset(struct rtl8169_private *tp)
4558 {
4559         /* Disable interrupts */
4560         rtl8169_irq_mask_and_ack(tp);
4561
4562         rtl_rx_close(tp);
4563
4564         switch (tp->mac_version) {
4565         case RTL_GIGA_MAC_VER_27:
4566         case RTL_GIGA_MAC_VER_28:
4567         case RTL_GIGA_MAC_VER_31:
4568                 rtl_udelay_loop_wait_low(tp, &rtl_npq_cond, 20, 42*42);
4569                 break;
4570         case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
4571         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
4572                 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
4573                 rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);
4574                 break;
4575         default:
4576                 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
4577                 udelay(100);
4578                 break;
4579         }
4580
4581         rtl_hw_reset(tp);
4582 }
4583
4584 static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
4585 {
4586         /* Set DMA burst size and Interframe Gap Time */
4587         RTL_W32(tp, TxConfig, (TX_DMA_BURST << TxDMAShift) |
4588                 (InterFrameGap << TxInterFrameGapShift));
4589 }
4590
4591 static void rtl_set_rx_max_size(struct rtl8169_private *tp)
4592 {
4593         /* Low hurts. Let's disable the filtering. */
4594         RTL_W16(tp, RxMaxSize, R8169_RX_BUF_SIZE + 1);
4595 }
4596
4597 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp)
4598 {
4599         /*
4600          * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
4601          * register to be written before TxDescAddrLow to work.
4602          * Switching from MMIO to I/O access fixes the issue as well.
4603          */
4604         RTL_W32(tp, TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
4605         RTL_W32(tp, TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
4606         RTL_W32(tp, RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
4607         RTL_W32(tp, RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
4608 }
4609
4610 static void rtl8169_set_magic_reg(struct rtl8169_private *tp, unsigned mac_version)
4611 {
4612         static const struct rtl_cfg2_info {
4613                 u32 mac_version;
4614                 u32 clk;
4615                 u32 val;
4616         } cfg2_info [] = {
4617                 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
4618                 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
4619                 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
4620                 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
4621         };
4622         const struct rtl_cfg2_info *p = cfg2_info;
4623         unsigned int i;
4624         u32 clk;
4625
4626         clk = RTL_R8(tp, Config2) & PCI_Clock_66MHz;
4627         for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
4628                 if ((p->mac_version == mac_version) && (p->clk == clk)) {
4629                         RTL_W32(tp, 0x7c, p->val);
4630                         break;
4631                 }
4632         }
4633 }
4634
4635 static void rtl_set_rx_mode(struct net_device *dev)
4636 {
4637         struct rtl8169_private *tp = netdev_priv(dev);
4638         u32 mc_filter[2];       /* Multicast hash filter */
4639         int rx_mode;
4640         u32 tmp = 0;
4641
4642         if (dev->flags & IFF_PROMISC) {
4643                 /* Unconditionally log net taps. */
4644                 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
4645                 rx_mode =
4646                     AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
4647                     AcceptAllPhys;
4648                 mc_filter[1] = mc_filter[0] = 0xffffffff;
4649         } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
4650                    (dev->flags & IFF_ALLMULTI)) {
4651                 /* Too many to filter perfectly -- accept all multicasts. */
4652                 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
4653                 mc_filter[1] = mc_filter[0] = 0xffffffff;
4654         } else {
4655                 struct netdev_hw_addr *ha;
4656
4657                 rx_mode = AcceptBroadcast | AcceptMyPhys;
4658                 mc_filter[1] = mc_filter[0] = 0;
4659                 netdev_for_each_mc_addr(ha, dev) {
4660                         int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
4661                         mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
4662                         rx_mode |= AcceptMulticast;
4663                 }
4664         }
4665
4666         if (dev->features & NETIF_F_RXALL)
4667                 rx_mode |= (AcceptErr | AcceptRunt);
4668
4669         tmp = (RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK) | rx_mode;
4670
4671         if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
4672                 u32 data = mc_filter[0];
4673
4674                 mc_filter[0] = swab32(mc_filter[1]);
4675                 mc_filter[1] = swab32(data);
4676         }
4677
4678         if (tp->mac_version == RTL_GIGA_MAC_VER_35)
4679                 mc_filter[1] = mc_filter[0] = 0xffffffff;
4680
4681         RTL_W32(tp, MAR0 + 4, mc_filter[1]);
4682         RTL_W32(tp, MAR0 + 0, mc_filter[0]);
4683
4684         RTL_W32(tp, RxConfig, tmp);
4685 }
4686
4687 static void rtl_hw_start(struct  rtl8169_private *tp)
4688 {
4689         RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
4690
4691         tp->hw_start(tp);
4692
4693         rtl_set_rx_max_size(tp);
4694         rtl_set_rx_tx_desc_registers(tp);
4695         rtl_set_rx_tx_config_registers(tp);
4696         RTL_W8(tp, Cfg9346, Cfg9346_Lock);
4697
4698         /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
4699         RTL_R8(tp, IntrMask);
4700         RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb);
4701         rtl_set_rx_mode(tp->dev);
4702         /* no early-rx interrupts */
4703         RTL_W16(tp, MultiIntr, RTL_R16(tp, MultiIntr) & 0xf000);
4704         rtl_irq_enable_all(tp);
4705 }
4706
4707 static void rtl_hw_start_8169(struct rtl8169_private *tp)
4708 {
4709         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
4710                 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4711
4712         RTL_W8(tp, EarlyTxThres, NoEarlyTx);
4713
4714         tp->cp_cmd |= PCIMulRW;
4715
4716         if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4717             tp->mac_version == RTL_GIGA_MAC_VER_03) {
4718                 netif_dbg(tp, drv, tp->dev,
4719                           "Set MAC Reg C+CR Offset 0xe0. Bit 3 and Bit 14 MUST be 1\n");
4720                 tp->cp_cmd |= (1 << 14);
4721         }
4722
4723         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4724
4725         rtl8169_set_magic_reg(tp, tp->mac_version);
4726
4727         /*
4728          * Undocumented corner. Supposedly:
4729          * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
4730          */
4731         RTL_W16(tp, IntrMitigate, 0x0000);
4732
4733         RTL_W32(tp, RxMissed, 0);
4734 }
4735
4736 DECLARE_RTL_COND(rtl_csiar_cond)
4737 {
4738         return RTL_R32(tp, CSIAR) & CSIAR_FLAG;
4739 }
4740
4741 static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)
4742 {
4743         u32 func = PCI_FUNC(tp->pci_dev->devfn);
4744
4745         RTL_W32(tp, CSIDR, value);
4746         RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
4747                 CSIAR_BYTE_ENABLE | func << 16);
4748
4749         rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
4750 }
4751
4752 static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)
4753 {
4754         u32 func = PCI_FUNC(tp->pci_dev->devfn);
4755
4756         RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) | func << 16 |
4757                 CSIAR_BYTE_ENABLE);
4758
4759         return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
4760                 RTL_R32(tp, CSIDR) : ~0;
4761 }
4762
4763 static void rtl_csi_access_enable(struct rtl8169_private *tp, u8 val)
4764 {
4765         struct pci_dev *pdev = tp->pci_dev;
4766         u32 csi;
4767
4768         /* According to Realtek the value at config space address 0x070f
4769          * controls the L0s/L1 entrance latency. We try standard ECAM access
4770          * first and if it fails fall back to CSI.
4771          */
4772         if (pdev->cfg_size > 0x070f &&
4773             pci_write_config_byte(pdev, 0x070f, val) == PCIBIOS_SUCCESSFUL)
4774                 return;
4775
4776         netdev_notice_once(tp->dev,
4777                 "No native access to PCI extended config space, falling back to CSI\n");
4778         csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff;
4779         rtl_csi_write(tp, 0x070c, csi | val << 24);
4780 }
4781
4782 static void rtl_set_def_aspm_entry_latency(struct rtl8169_private *tp)
4783 {
4784         rtl_csi_access_enable(tp, 0x27);
4785 }
4786
4787 struct ephy_info {
4788         unsigned int offset;
4789         u16 mask;
4790         u16 bits;
4791 };
4792
4793 static void rtl_ephy_init(struct rtl8169_private *tp, const struct ephy_info *e,
4794                           int len)
4795 {
4796         u16 w;
4797
4798         while (len-- > 0) {
4799                 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits;
4800                 rtl_ephy_write(tp, e->offset, w);
4801                 e++;
4802         }
4803 }
4804
4805 static void rtl_disable_clock_request(struct rtl8169_private *tp)
4806 {
4807         pcie_capability_clear_word(tp->pci_dev, PCI_EXP_LNKCTL,
4808                                    PCI_EXP_LNKCTL_CLKREQ_EN);
4809 }
4810
4811 static void rtl_enable_clock_request(struct rtl8169_private *tp)
4812 {
4813         pcie_capability_set_word(tp->pci_dev, PCI_EXP_LNKCTL,
4814                                  PCI_EXP_LNKCTL_CLKREQ_EN);
4815 }
4816
4817 static void rtl_pcie_state_l2l3_enable(struct rtl8169_private *tp, bool enable)
4818 {
4819         u8 data;
4820
4821         data = RTL_R8(tp, Config3);
4822
4823         if (enable)
4824                 data |= Rdy_to_L23;
4825         else
4826                 data &= ~Rdy_to_L23;
4827
4828         RTL_W8(tp, Config3, data);
4829 }
4830
4831 static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable)
4832 {
4833         if (enable) {
4834                 RTL_W8(tp, Config2, RTL_R8(tp, Config2) | ClkReqEn);
4835                 RTL_W8(tp, Config5, RTL_R8(tp, Config5) | ASPM_en);
4836         } else {
4837                 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
4838                 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
4839         }
4840 }
4841
4842 static void rtl_hw_start_8168bb(struct rtl8169_private *tp)
4843 {
4844         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4845
4846         tp->cp_cmd &= CPCMD_QUIRK_MASK;
4847         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4848
4849         if (tp->dev->mtu <= ETH_DATA_LEN) {
4850                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B |
4851                                          PCI_EXP_DEVCTL_NOSNOOP_EN);
4852         }
4853 }
4854
4855 static void rtl_hw_start_8168bef(struct rtl8169_private *tp)
4856 {
4857         rtl_hw_start_8168bb(tp);
4858
4859         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4860
4861         RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0));
4862 }
4863
4864 static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)
4865 {
4866         RTL_W8(tp, Config1, RTL_R8(tp, Config1) | Speed_down);
4867
4868         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4869
4870         if (tp->dev->mtu <= ETH_DATA_LEN)
4871                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4872
4873         rtl_disable_clock_request(tp);
4874
4875         tp->cp_cmd &= CPCMD_QUIRK_MASK;
4876         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4877 }
4878
4879 static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp)
4880 {
4881         static const struct ephy_info e_info_8168cp[] = {
4882                 { 0x01, 0,      0x0001 },
4883                 { 0x02, 0x0800, 0x1000 },
4884                 { 0x03, 0,      0x0042 },
4885                 { 0x06, 0x0080, 0x0000 },
4886                 { 0x07, 0,      0x2000 }
4887         };
4888
4889         rtl_set_def_aspm_entry_latency(tp);
4890
4891         rtl_ephy_init(tp, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
4892
4893         __rtl_hw_start_8168cp(tp);
4894 }
4895
4896 static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)
4897 {
4898         rtl_set_def_aspm_entry_latency(tp);
4899
4900         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4901
4902         if (tp->dev->mtu <= ETH_DATA_LEN)
4903                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4904
4905         tp->cp_cmd &= CPCMD_QUIRK_MASK;
4906         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4907 }
4908
4909 static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)
4910 {
4911         rtl_set_def_aspm_entry_latency(tp);
4912
4913         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4914
4915         /* Magic. */
4916         RTL_W8(tp, DBG_REG, 0x20);
4917
4918         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4919
4920         if (tp->dev->mtu <= ETH_DATA_LEN)
4921                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4922
4923         tp->cp_cmd &= CPCMD_QUIRK_MASK;
4924         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4925 }
4926
4927 static void rtl_hw_start_8168c_1(struct rtl8169_private *tp)
4928 {
4929         static const struct ephy_info e_info_8168c_1[] = {
4930                 { 0x02, 0x0800, 0x1000 },
4931                 { 0x03, 0,      0x0002 },
4932                 { 0x06, 0x0080, 0x0000 }
4933         };
4934
4935         rtl_set_def_aspm_entry_latency(tp);
4936
4937         RTL_W8(tp, DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
4938
4939         rtl_ephy_init(tp, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
4940
4941         __rtl_hw_start_8168cp(tp);
4942 }
4943
4944 static void rtl_hw_start_8168c_2(struct rtl8169_private *tp)
4945 {
4946         static const struct ephy_info e_info_8168c_2[] = {
4947                 { 0x01, 0,      0x0001 },
4948                 { 0x03, 0x0400, 0x0220 }
4949         };
4950
4951         rtl_set_def_aspm_entry_latency(tp);
4952
4953         rtl_ephy_init(tp, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
4954
4955         __rtl_hw_start_8168cp(tp);
4956 }
4957
4958 static void rtl_hw_start_8168c_3(struct rtl8169_private *tp)
4959 {
4960         rtl_hw_start_8168c_2(tp);
4961 }
4962
4963 static void rtl_hw_start_8168c_4(struct rtl8169_private *tp)
4964 {
4965         rtl_set_def_aspm_entry_latency(tp);
4966
4967         __rtl_hw_start_8168cp(tp);
4968 }
4969
4970 static void rtl_hw_start_8168d(struct rtl8169_private *tp)
4971 {
4972         rtl_set_def_aspm_entry_latency(tp);
4973
4974         rtl_disable_clock_request(tp);
4975
4976         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4977
4978         if (tp->dev->mtu <= ETH_DATA_LEN)
4979                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4980
4981         tp->cp_cmd &= CPCMD_QUIRK_MASK;
4982         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4983 }
4984
4985 static void rtl_hw_start_8168dp(struct rtl8169_private *tp)
4986 {
4987         rtl_set_def_aspm_entry_latency(tp);
4988
4989         if (tp->dev->mtu <= ETH_DATA_LEN)
4990                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4991
4992         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4993
4994         rtl_disable_clock_request(tp);
4995 }
4996
4997 static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
4998 {
4999         static const struct ephy_info e_info_8168d_4[] = {
5000                 { 0x0b, 0x0000, 0x0048 },
5001                 { 0x19, 0x0020, 0x0050 },
5002                 { 0x0c, 0x0100, 0x0020 }
5003         };
5004
5005         rtl_set_def_aspm_entry_latency(tp);
5006
5007         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5008
5009         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
5010
5011         rtl_ephy_init(tp, e_info_8168d_4, ARRAY_SIZE(e_info_8168d_4));
5012
5013         rtl_enable_clock_request(tp);
5014 }
5015
5016 static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)
5017 {
5018         static const struct ephy_info e_info_8168e_1[] = {
5019                 { 0x00, 0x0200, 0x0100 },
5020                 { 0x00, 0x0000, 0x0004 },
5021                 { 0x06, 0x0002, 0x0001 },
5022                 { 0x06, 0x0000, 0x0030 },
5023                 { 0x07, 0x0000, 0x2000 },
5024                 { 0x00, 0x0000, 0x0020 },
5025                 { 0x03, 0x5800, 0x2000 },
5026                 { 0x03, 0x0000, 0x0001 },
5027                 { 0x01, 0x0800, 0x1000 },
5028                 { 0x07, 0x0000, 0x4000 },
5029                 { 0x1e, 0x0000, 0x2000 },
5030                 { 0x19, 0xffff, 0xfe6c },
5031                 { 0x0a, 0x0000, 0x0040 }
5032         };
5033
5034         rtl_set_def_aspm_entry_latency(tp);
5035
5036         rtl_ephy_init(tp, e_info_8168e_1, ARRAY_SIZE(e_info_8168e_1));
5037
5038         if (tp->dev->mtu <= ETH_DATA_LEN)
5039                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5040
5041         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
5042
5043         rtl_disable_clock_request(tp);
5044
5045         /* Reset tx FIFO pointer */
5046         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | TXPLA_RST);
5047         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~TXPLA_RST);
5048
5049         RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
5050 }
5051
5052 static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
5053 {
5054         static const struct ephy_info e_info_8168e_2[] = {
5055                 { 0x09, 0x0000, 0x0080 },
5056                 { 0x19, 0x0000, 0x0224 }
5057         };
5058
5059         rtl_set_def_aspm_entry_latency(tp);
5060
5061         rtl_ephy_init(tp, e_info_8168e_2, ARRAY_SIZE(e_info_8168e_2));
5062
5063         if (tp->dev->mtu <= ETH_DATA_LEN)
5064                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5065
5066         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5067         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5068         rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
5069         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5070         rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
5071         rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060, ERIAR_EXGMAC);
5072         rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5073         rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
5074
5075         RTL_W8(tp, MaxTxPacketSize, EarlySize);
5076
5077         rtl_disable_clock_request(tp);
5078
5079         RTL_W32(tp, TxConfig, RTL_R32(tp, TxConfig) | TXCFG_AUTO_FIFO);
5080         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
5081
5082         /* Adjust EEE LED frequency */
5083         RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
5084
5085         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
5086         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
5087         RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
5088
5089         rtl_hw_aspm_clkreq_enable(tp, true);
5090 }
5091
5092 static void rtl_hw_start_8168f(struct rtl8169_private *tp)
5093 {
5094         rtl_set_def_aspm_entry_latency(tp);
5095
5096         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5097
5098         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5099         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5100         rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
5101         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5102         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5103         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5104         rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5105         rtl_w0w1_eri(tp, 0x1d0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5106         rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
5107         rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060, ERIAR_EXGMAC);
5108
5109         RTL_W8(tp, MaxTxPacketSize, EarlySize);
5110
5111         rtl_disable_clock_request(tp);
5112
5113         RTL_W32(tp, TxConfig, RTL_R32(tp, TxConfig) | TXCFG_AUTO_FIFO);
5114         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
5115         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
5116         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
5117         RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
5118 }
5119
5120 static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
5121 {
5122         static const struct ephy_info e_info_8168f_1[] = {
5123                 { 0x06, 0x00c0, 0x0020 },
5124                 { 0x08, 0x0001, 0x0002 },
5125                 { 0x09, 0x0000, 0x0080 },
5126                 { 0x19, 0x0000, 0x0224 }
5127         };
5128
5129         rtl_hw_start_8168f(tp);
5130
5131         rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
5132
5133         rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
5134
5135         /* Adjust EEE LED frequency */
5136         RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
5137 }
5138
5139 static void rtl_hw_start_8411(struct rtl8169_private *tp)
5140 {
5141         static const struct ephy_info e_info_8168f_1[] = {
5142                 { 0x06, 0x00c0, 0x0020 },
5143                 { 0x0f, 0xffff, 0x5200 },
5144                 { 0x1e, 0x0000, 0x4000 },
5145                 { 0x19, 0x0000, 0x0224 }
5146         };
5147
5148         rtl_hw_start_8168f(tp);
5149         rtl_pcie_state_l2l3_enable(tp, false);
5150
5151         rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
5152
5153         rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0x0000, ERIAR_EXGMAC);
5154 }
5155
5156 static void rtl_hw_start_8168g(struct rtl8169_private *tp)
5157 {
5158         RTL_W32(tp, TxConfig, RTL_R32(tp, TxConfig) | TXCFG_AUTO_FIFO);
5159
5160         rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x080002, ERIAR_EXGMAC);
5161         rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
5162         rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
5163         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5164
5165         rtl_set_def_aspm_entry_latency(tp);
5166
5167         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5168
5169         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5170         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5171         rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f, ERIAR_EXGMAC);
5172
5173         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
5174         RTL_W8(tp, MaxTxPacketSize, EarlySize);
5175
5176         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5177         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5178
5179         /* Adjust EEE LED frequency */
5180         RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
5181
5182         rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06, ERIAR_EXGMAC);
5183         rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC);
5184
5185         rtl_pcie_state_l2l3_enable(tp, false);
5186 }
5187
5188 static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
5189 {
5190         static const struct ephy_info e_info_8168g_1[] = {
5191                 { 0x00, 0x0000, 0x0008 },
5192                 { 0x0c, 0x37d0, 0x0820 },
5193                 { 0x1e, 0x0000, 0x0001 },
5194                 { 0x19, 0x8000, 0x0000 }
5195         };
5196
5197         rtl_hw_start_8168g(tp);
5198
5199         /* disable aspm and clock request before access ephy */
5200         rtl_hw_aspm_clkreq_enable(tp, false);
5201         rtl_ephy_init(tp, e_info_8168g_1, ARRAY_SIZE(e_info_8168g_1));
5202         rtl_hw_aspm_clkreq_enable(tp, true);
5203 }
5204
5205 static void rtl_hw_start_8168g_2(struct rtl8169_private *tp)
5206 {
5207         static const struct ephy_info e_info_8168g_2[] = {
5208                 { 0x00, 0x0000, 0x0008 },
5209                 { 0x0c, 0x3df0, 0x0200 },
5210                 { 0x19, 0xffff, 0xfc00 },
5211                 { 0x1e, 0xffff, 0x20eb }
5212         };
5213
5214         rtl_hw_start_8168g(tp);
5215
5216         /* disable aspm and clock request before access ephy */
5217         RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
5218         RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
5219         rtl_ephy_init(tp, e_info_8168g_2, ARRAY_SIZE(e_info_8168g_2));
5220 }
5221
5222 static void rtl_hw_start_8411_2(struct rtl8169_private *tp)
5223 {
5224         static const struct ephy_info e_info_8411_2[] = {
5225                 { 0x00, 0x0000, 0x0008 },
5226                 { 0x0c, 0x3df0, 0x0200 },
5227                 { 0x0f, 0xffff, 0x5200 },
5228                 { 0x19, 0x0020, 0x0000 },
5229                 { 0x1e, 0x0000, 0x2000 }
5230         };
5231
5232         rtl_hw_start_8168g(tp);
5233
5234         /* disable aspm and clock request before access ephy */
5235         rtl_hw_aspm_clkreq_enable(tp, false);
5236         rtl_ephy_init(tp, e_info_8411_2, ARRAY_SIZE(e_info_8411_2));
5237         rtl_hw_aspm_clkreq_enable(tp, true);
5238 }
5239
5240 static void rtl_hw_start_8168h_1(struct rtl8169_private *tp)
5241 {
5242         int rg_saw_cnt;
5243         u32 data;
5244         static const struct ephy_info e_info_8168h_1[] = {
5245                 { 0x1e, 0x0800, 0x0001 },
5246                 { 0x1d, 0x0000, 0x0800 },
5247                 { 0x05, 0xffff, 0x2089 },
5248                 { 0x06, 0xffff, 0x5881 },
5249                 { 0x04, 0xffff, 0x154a },
5250                 { 0x01, 0xffff, 0x068b }
5251         };
5252
5253         /* disable aspm and clock request before access ephy */
5254         rtl_hw_aspm_clkreq_enable(tp, false);
5255         rtl_ephy_init(tp, e_info_8168h_1, ARRAY_SIZE(e_info_8168h_1));
5256
5257         RTL_W32(tp, TxConfig, RTL_R32(tp, TxConfig) | TXCFG_AUTO_FIFO);
5258
5259         rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x00080002, ERIAR_EXGMAC);
5260         rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
5261         rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
5262         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5263
5264         rtl_set_def_aspm_entry_latency(tp);
5265
5266         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5267
5268         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5269         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5270
5271         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_1111, 0x0010, 0x00, ERIAR_EXGMAC);
5272
5273         rtl_w0w1_eri(tp, 0xd4, ERIAR_MASK_1111, 0x1f00, 0x00, ERIAR_EXGMAC);
5274
5275         rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87, ERIAR_EXGMAC);
5276
5277         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
5278         RTL_W8(tp, MaxTxPacketSize, EarlySize);
5279
5280         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5281         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5282
5283         /* Adjust EEE LED frequency */
5284         RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
5285
5286         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5287         RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
5288
5289         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
5290
5291         rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC);
5292
5293         rtl_pcie_state_l2l3_enable(tp, false);
5294
5295         rtl_writephy(tp, 0x1f, 0x0c42);
5296         rg_saw_cnt = (rtl_readphy(tp, 0x13) & 0x3fff);
5297         rtl_writephy(tp, 0x1f, 0x0000);
5298         if (rg_saw_cnt > 0) {
5299                 u16 sw_cnt_1ms_ini;
5300
5301                 sw_cnt_1ms_ini = 16000000/rg_saw_cnt;
5302                 sw_cnt_1ms_ini &= 0x0fff;
5303                 data = r8168_mac_ocp_read(tp, 0xd412);
5304                 data &= ~0x0fff;
5305                 data |= sw_cnt_1ms_ini;
5306                 r8168_mac_ocp_write(tp, 0xd412, data);
5307         }
5308
5309         data = r8168_mac_ocp_read(tp, 0xe056);
5310         data &= ~0xf0;
5311         data |= 0x70;
5312         r8168_mac_ocp_write(tp, 0xe056, data);
5313
5314         data = r8168_mac_ocp_read(tp, 0xe052);
5315         data &= ~0x6000;
5316         data |= 0x8008;
5317         r8168_mac_ocp_write(tp, 0xe052, data);
5318
5319         data = r8168_mac_ocp_read(tp, 0xe0d6);
5320         data &= ~0x01ff;
5321         data |= 0x017f;
5322         r8168_mac_ocp_write(tp, 0xe0d6, data);
5323
5324         data = r8168_mac_ocp_read(tp, 0xd420);
5325         data &= ~0x0fff;
5326         data |= 0x047f;
5327         r8168_mac_ocp_write(tp, 0xd420, data);
5328
5329         r8168_mac_ocp_write(tp, 0xe63e, 0x0001);
5330         r8168_mac_ocp_write(tp, 0xe63e, 0x0000);
5331         r8168_mac_ocp_write(tp, 0xc094, 0x0000);
5332         r8168_mac_ocp_write(tp, 0xc09e, 0x0000);
5333
5334         rtl_hw_aspm_clkreq_enable(tp, true);
5335 }
5336
5337 static void rtl_hw_start_8168ep(struct rtl8169_private *tp)
5338 {
5339         rtl8168ep_stop_cmac(tp);
5340
5341         RTL_W32(tp, TxConfig, RTL_R32(tp, TxConfig) | TXCFG_AUTO_FIFO);
5342
5343         rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x00080002, ERIAR_EXGMAC);
5344         rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x2f, ERIAR_EXGMAC);
5345         rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x5f, ERIAR_EXGMAC);
5346         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5347
5348         rtl_set_def_aspm_entry_latency(tp);
5349
5350         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5351
5352         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5353         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5354
5355         rtl_w0w1_eri(tp, 0xd4, ERIAR_MASK_1111, 0x1f80, 0x00, ERIAR_EXGMAC);
5356
5357         rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87, ERIAR_EXGMAC);
5358
5359         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
5360         RTL_W8(tp, MaxTxPacketSize, EarlySize);
5361
5362         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5363         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5364
5365         /* Adjust EEE LED frequency */
5366         RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
5367
5368         rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06, ERIAR_EXGMAC);
5369
5370         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
5371
5372         rtl_pcie_state_l2l3_enable(tp, false);
5373 }
5374
5375 static void rtl_hw_start_8168ep_1(struct rtl8169_private *tp)
5376 {
5377         static const struct ephy_info e_info_8168ep_1[] = {
5378                 { 0x00, 0xffff, 0x10ab },
5379                 { 0x06, 0xffff, 0xf030 },
5380                 { 0x08, 0xffff, 0x2006 },
5381                 { 0x0d, 0xffff, 0x1666 },
5382                 { 0x0c, 0x3ff0, 0x0000 }
5383         };
5384
5385         /* disable aspm and clock request before access ephy */
5386         rtl_hw_aspm_clkreq_enable(tp, false);
5387         rtl_ephy_init(tp, e_info_8168ep_1, ARRAY_SIZE(e_info_8168ep_1));
5388
5389         rtl_hw_start_8168ep(tp);
5390
5391         rtl_hw_aspm_clkreq_enable(tp, true);
5392 }
5393
5394 static void rtl_hw_start_8168ep_2(struct rtl8169_private *tp)
5395 {
5396         static const struct ephy_info e_info_8168ep_2[] = {
5397                 { 0x00, 0xffff, 0x10a3 },
5398                 { 0x19, 0xffff, 0xfc00 },
5399                 { 0x1e, 0xffff, 0x20ea }
5400         };
5401
5402         /* disable aspm and clock request before access ephy */
5403         rtl_hw_aspm_clkreq_enable(tp, false);
5404         rtl_ephy_init(tp, e_info_8168ep_2, ARRAY_SIZE(e_info_8168ep_2));
5405
5406         rtl_hw_start_8168ep(tp);
5407
5408         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5409         RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
5410
5411         rtl_hw_aspm_clkreq_enable(tp, true);
5412 }
5413
5414 static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp)
5415 {
5416         u32 data;
5417         static const struct ephy_info e_info_8168ep_3[] = {
5418                 { 0x00, 0xffff, 0x10a3 },
5419                 { 0x19, 0xffff, 0x7c00 },
5420                 { 0x1e, 0xffff, 0x20eb },
5421                 { 0x0d, 0xffff, 0x1666 }
5422         };
5423
5424         /* disable aspm and clock request before access ephy */
5425         rtl_hw_aspm_clkreq_enable(tp, false);
5426         rtl_ephy_init(tp, e_info_8168ep_3, ARRAY_SIZE(e_info_8168ep_3));
5427
5428         rtl_hw_start_8168ep(tp);
5429
5430         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5431         RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
5432
5433         data = r8168_mac_ocp_read(tp, 0xd3e2);
5434         data &= 0xf000;
5435         data |= 0x0271;
5436         r8168_mac_ocp_write(tp, 0xd3e2, data);
5437
5438         data = r8168_mac_ocp_read(tp, 0xd3e4);
5439         data &= 0xff00;
5440         r8168_mac_ocp_write(tp, 0xd3e4, data);
5441
5442         data = r8168_mac_ocp_read(tp, 0xe860);
5443         data |= 0x0080;
5444         r8168_mac_ocp_write(tp, 0xe860, data);
5445
5446         rtl_hw_aspm_clkreq_enable(tp, true);
5447 }
5448
5449 static void rtl_hw_start_8168(struct rtl8169_private *tp)
5450 {
5451         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
5452
5453         tp->cp_cmd &= ~INTT_MASK;
5454         tp->cp_cmd |= PktCntrDisable | INTT_1;
5455         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
5456
5457         RTL_W16(tp, IntrMitigate, 0x5151);
5458
5459         /* Work around for RxFIFO overflow. */
5460         if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
5461                 tp->event_slow |= RxFIFOOver | PCSTimeout;
5462                 tp->event_slow &= ~RxOverflow;
5463         }
5464
5465         switch (tp->mac_version) {
5466         case RTL_GIGA_MAC_VER_11:
5467                 rtl_hw_start_8168bb(tp);
5468                 break;
5469
5470         case RTL_GIGA_MAC_VER_12:
5471         case RTL_GIGA_MAC_VER_17:
5472                 rtl_hw_start_8168bef(tp);
5473                 break;
5474
5475         case RTL_GIGA_MAC_VER_18:
5476                 rtl_hw_start_8168cp_1(tp);
5477                 break;
5478
5479         case RTL_GIGA_MAC_VER_19:
5480                 rtl_hw_start_8168c_1(tp);
5481                 break;
5482
5483         case RTL_GIGA_MAC_VER_20:
5484                 rtl_hw_start_8168c_2(tp);
5485                 break;
5486
5487         case RTL_GIGA_MAC_VER_21:
5488                 rtl_hw_start_8168c_3(tp);
5489                 break;
5490
5491         case RTL_GIGA_MAC_VER_22:
5492                 rtl_hw_start_8168c_4(tp);
5493                 break;
5494
5495         case RTL_GIGA_MAC_VER_23:
5496                 rtl_hw_start_8168cp_2(tp);
5497                 break;
5498
5499         case RTL_GIGA_MAC_VER_24:
5500                 rtl_hw_start_8168cp_3(tp);
5501                 break;
5502
5503         case RTL_GIGA_MAC_VER_25:
5504         case RTL_GIGA_MAC_VER_26:
5505         case RTL_GIGA_MAC_VER_27:
5506                 rtl_hw_start_8168d(tp);
5507                 break;
5508
5509         case RTL_GIGA_MAC_VER_28:
5510                 rtl_hw_start_8168d_4(tp);
5511                 break;
5512
5513         case RTL_GIGA_MAC_VER_31:
5514                 rtl_hw_start_8168dp(tp);
5515                 break;
5516
5517         case RTL_GIGA_MAC_VER_32:
5518         case RTL_GIGA_MAC_VER_33:
5519                 rtl_hw_start_8168e_1(tp);
5520                 break;
5521         case RTL_GIGA_MAC_VER_34:
5522                 rtl_hw_start_8168e_2(tp);
5523                 break;
5524
5525         case RTL_GIGA_MAC_VER_35:
5526         case RTL_GIGA_MAC_VER_36:
5527                 rtl_hw_start_8168f_1(tp);
5528                 break;
5529
5530         case RTL_GIGA_MAC_VER_38:
5531                 rtl_hw_start_8411(tp);
5532                 break;
5533
5534         case RTL_GIGA_MAC_VER_40:
5535         case RTL_GIGA_MAC_VER_41:
5536                 rtl_hw_start_8168g_1(tp);
5537                 break;
5538         case RTL_GIGA_MAC_VER_42:
5539                 rtl_hw_start_8168g_2(tp);
5540                 break;
5541
5542         case RTL_GIGA_MAC_VER_44:
5543                 rtl_hw_start_8411_2(tp);
5544                 break;
5545
5546         case RTL_GIGA_MAC_VER_45:
5547         case RTL_GIGA_MAC_VER_46:
5548                 rtl_hw_start_8168h_1(tp);
5549                 break;
5550
5551         case RTL_GIGA_MAC_VER_49:
5552                 rtl_hw_start_8168ep_1(tp);
5553                 break;
5554
5555         case RTL_GIGA_MAC_VER_50:
5556                 rtl_hw_start_8168ep_2(tp);
5557                 break;
5558
5559         case RTL_GIGA_MAC_VER_51:
5560                 rtl_hw_start_8168ep_3(tp);
5561                 break;
5562
5563         default:
5564                 netif_err(tp, drv, tp->dev,
5565                           "unknown chipset (mac_version = %d)\n",
5566                           tp->mac_version);
5567                 break;
5568         }
5569 }
5570
5571 static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)
5572 {
5573         static const struct ephy_info e_info_8102e_1[] = {
5574                 { 0x01, 0, 0x6e65 },
5575                 { 0x02, 0, 0x091f },
5576                 { 0x03, 0, 0xc2f9 },
5577                 { 0x06, 0, 0xafb5 },
5578                 { 0x07, 0, 0x0e00 },
5579                 { 0x19, 0, 0xec80 },
5580                 { 0x01, 0, 0x2e65 },
5581                 { 0x01, 0, 0x6e65 }
5582         };
5583         u8 cfg1;
5584
5585         rtl_set_def_aspm_entry_latency(tp);
5586
5587         RTL_W8(tp, DBG_REG, FIX_NAK_1);
5588
5589         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5590
5591         RTL_W8(tp, Config1,
5592                LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
5593         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
5594
5595         cfg1 = RTL_R8(tp, Config1);
5596         if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
5597                 RTL_W8(tp, Config1, cfg1 & ~LEDS0);
5598
5599         rtl_ephy_init(tp, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
5600 }
5601
5602 static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)
5603 {
5604         rtl_set_def_aspm_entry_latency(tp);
5605
5606         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5607
5608         RTL_W8(tp, Config1, MEMMAP | IOMAP | VPD | PMEnable);
5609         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
5610 }
5611
5612 static void rtl_hw_start_8102e_3(struct rtl8169_private *tp)
5613 {
5614         rtl_hw_start_8102e_2(tp);
5615
5616         rtl_ephy_write(tp, 0x03, 0xc2f9);
5617 }
5618
5619 static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)
5620 {
5621         static const struct ephy_info e_info_8105e_1[] = {
5622                 { 0x07, 0, 0x4000 },
5623                 { 0x19, 0, 0x0200 },
5624                 { 0x19, 0, 0x0020 },
5625                 { 0x1e, 0, 0x2000 },
5626                 { 0x03, 0, 0x0001 },
5627                 { 0x19, 0, 0x0100 },
5628                 { 0x19, 0, 0x0004 },
5629                 { 0x0a, 0, 0x0020 }
5630         };
5631
5632         /* Force LAN exit from ASPM if Rx/Tx are not idle */
5633         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
5634
5635         /* Disable Early Tally Counter */
5636         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) & ~0x010000);
5637
5638         RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
5639         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
5640
5641         rtl_ephy_init(tp, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
5642
5643         rtl_pcie_state_l2l3_enable(tp, false);
5644 }
5645
5646 static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)
5647 {
5648         rtl_hw_start_8105e_1(tp);
5649         rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000);
5650 }
5651
5652 static void rtl_hw_start_8402(struct rtl8169_private *tp)
5653 {
5654         static const struct ephy_info e_info_8402[] = {
5655                 { 0x19, 0xffff, 0xff64 },
5656                 { 0x1e, 0, 0x4000 }
5657         };
5658
5659         rtl_set_def_aspm_entry_latency(tp);
5660
5661         /* Force LAN exit from ASPM if Rx/Tx are not idle */
5662         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
5663
5664         RTL_W32(tp, TxConfig, RTL_R32(tp, TxConfig) | TXCFG_AUTO_FIFO);
5665         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
5666
5667         rtl_ephy_init(tp, e_info_8402, ARRAY_SIZE(e_info_8402));
5668
5669         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5670
5671         rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00000002, ERIAR_EXGMAC);
5672         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00000006, ERIAR_EXGMAC);
5673         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5674         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5675         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5676         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5677         rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0e00, 0xff00, ERIAR_EXGMAC);
5678
5679         rtl_pcie_state_l2l3_enable(tp, false);
5680 }
5681
5682 static void rtl_hw_start_8106(struct rtl8169_private *tp)
5683 {
5684         /* Force LAN exit from ASPM if Rx/Tx are not idle */
5685         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
5686
5687         RTL_W32(tp, MISC, (RTL_R32(tp, MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);
5688         RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
5689         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5690
5691         rtl_pcie_state_l2l3_enable(tp, false);
5692 }
5693
5694 static void rtl_hw_start_8101(struct rtl8169_private *tp)
5695 {
5696         if (tp->mac_version >= RTL_GIGA_MAC_VER_30)
5697                 tp->event_slow &= ~RxFIFOOver;
5698
5699         if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
5700             tp->mac_version == RTL_GIGA_MAC_VER_16)
5701                 pcie_capability_set_word(tp->pci_dev, PCI_EXP_DEVCTL,
5702                                          PCI_EXP_DEVCTL_NOSNOOP_EN);
5703
5704         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
5705
5706         tp->cp_cmd &= CPCMD_QUIRK_MASK;
5707         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
5708
5709         switch (tp->mac_version) {
5710         case RTL_GIGA_MAC_VER_07:
5711                 rtl_hw_start_8102e_1(tp);
5712                 break;
5713
5714         case RTL_GIGA_MAC_VER_08:
5715                 rtl_hw_start_8102e_3(tp);
5716                 break;
5717
5718         case RTL_GIGA_MAC_VER_09:
5719                 rtl_hw_start_8102e_2(tp);
5720                 break;
5721
5722         case RTL_GIGA_MAC_VER_29:
5723                 rtl_hw_start_8105e_1(tp);
5724                 break;
5725         case RTL_GIGA_MAC_VER_30:
5726                 rtl_hw_start_8105e_2(tp);
5727                 break;
5728
5729         case RTL_GIGA_MAC_VER_37:
5730                 rtl_hw_start_8402(tp);
5731                 break;
5732
5733         case RTL_GIGA_MAC_VER_39:
5734                 rtl_hw_start_8106(tp);
5735                 break;
5736         case RTL_GIGA_MAC_VER_43:
5737                 rtl_hw_start_8168g_2(tp);
5738                 break;
5739         case RTL_GIGA_MAC_VER_47:
5740         case RTL_GIGA_MAC_VER_48:
5741                 rtl_hw_start_8168h_1(tp);
5742                 break;
5743         }
5744
5745         RTL_W16(tp, IntrMitigate, 0x0000);
5746 }
5747
5748 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
5749 {
5750         struct rtl8169_private *tp = netdev_priv(dev);
5751
5752         if (new_mtu > ETH_DATA_LEN)
5753                 rtl_hw_jumbo_enable(tp);
5754         else
5755                 rtl_hw_jumbo_disable(tp);
5756
5757         dev->mtu = new_mtu;
5758         netdev_update_features(dev);
5759
5760         return 0;
5761 }
5762
5763 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
5764 {
5765         desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
5766         desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
5767 }
5768
5769 static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
5770                                      void **data_buff, struct RxDesc *desc)
5771 {
5772         dma_unmap_single(tp_to_dev(tp), le64_to_cpu(desc->addr),
5773                          R8169_RX_BUF_SIZE, DMA_FROM_DEVICE);
5774
5775         kfree(*data_buff);
5776         *data_buff = NULL;
5777         rtl8169_make_unusable_by_asic(desc);
5778 }
5779
5780 static inline void rtl8169_mark_to_asic(struct RxDesc *desc)
5781 {
5782         u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
5783
5784         /* Force memory writes to complete before releasing descriptor */
5785         dma_wmb();
5786
5787         desc->opts1 = cpu_to_le32(DescOwn | eor | R8169_RX_BUF_SIZE);
5788 }
5789
5790 static inline void *rtl8169_align(void *data)
5791 {
5792         return (void *)ALIGN((long)data, 16);
5793 }
5794
5795 static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
5796                                              struct RxDesc *desc)
5797 {
5798         void *data;
5799         dma_addr_t mapping;
5800         struct device *d = tp_to_dev(tp);
5801         int node = dev_to_node(d);
5802
5803         data = kmalloc_node(R8169_RX_BUF_SIZE, GFP_KERNEL, node);
5804         if (!data)
5805                 return NULL;
5806
5807         if (rtl8169_align(data) != data) {
5808                 kfree(data);
5809                 data = kmalloc_node(R8169_RX_BUF_SIZE + 15, GFP_KERNEL, node);
5810                 if (!data)
5811                         return NULL;
5812         }
5813
5814         mapping = dma_map_single(d, rtl8169_align(data), R8169_RX_BUF_SIZE,
5815                                  DMA_FROM_DEVICE);
5816         if (unlikely(dma_mapping_error(d, mapping))) {
5817                 if (net_ratelimit())
5818                         netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
5819                 goto err_out;
5820         }
5821
5822         desc->addr = cpu_to_le64(mapping);
5823         rtl8169_mark_to_asic(desc);
5824         return data;
5825
5826 err_out:
5827         kfree(data);
5828         return NULL;
5829 }
5830
5831 static void rtl8169_rx_clear(struct rtl8169_private *tp)
5832 {
5833         unsigned int i;
5834
5835         for (i = 0; i < NUM_RX_DESC; i++) {
5836                 if (tp->Rx_databuff[i]) {
5837                         rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
5838                                             tp->RxDescArray + i);
5839                 }
5840         }
5841 }
5842
5843 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
5844 {
5845         desc->opts1 |= cpu_to_le32(RingEnd);
5846 }
5847
5848 static int rtl8169_rx_fill(struct rtl8169_private *tp)
5849 {
5850         unsigned int i;
5851
5852         for (i = 0; i < NUM_RX_DESC; i++) {
5853                 void *data;
5854
5855                 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
5856                 if (!data) {
5857                         rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
5858                         goto err_out;
5859                 }
5860                 tp->Rx_databuff[i] = data;
5861         }
5862
5863         rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
5864         return 0;
5865
5866 err_out:
5867         rtl8169_rx_clear(tp);
5868         return -ENOMEM;
5869 }
5870
5871 static int rtl8169_init_ring(struct rtl8169_private *tp)
5872 {
5873         rtl8169_init_ring_indexes(tp);
5874
5875         memset(tp->tx_skb, 0, sizeof(tp->tx_skb));
5876         memset(tp->Rx_databuff, 0, sizeof(tp->Rx_databuff));
5877
5878         return rtl8169_rx_fill(tp);
5879 }
5880
5881 static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
5882                                  struct TxDesc *desc)
5883 {
5884         unsigned int len = tx_skb->len;
5885
5886         dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
5887
5888         desc->opts1 = 0x00;
5889         desc->opts2 = 0x00;
5890         desc->addr = 0x00;
5891         tx_skb->len = 0;
5892 }
5893
5894 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
5895                                    unsigned int n)
5896 {
5897         unsigned int i;
5898
5899         for (i = 0; i < n; i++) {
5900                 unsigned int entry = (start + i) % NUM_TX_DESC;
5901                 struct ring_info *tx_skb = tp->tx_skb + entry;
5902                 unsigned int len = tx_skb->len;
5903
5904                 if (len) {
5905                         struct sk_buff *skb = tx_skb->skb;
5906
5907                         rtl8169_unmap_tx_skb(tp_to_dev(tp), tx_skb,
5908                                              tp->TxDescArray + entry);
5909                         if (skb) {
5910                                 dev_consume_skb_any(skb);
5911                                 tx_skb->skb = NULL;
5912                         }
5913                 }
5914         }
5915 }
5916
5917 static void rtl8169_tx_clear(struct rtl8169_private *tp)
5918 {
5919         rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
5920         tp->cur_tx = tp->dirty_tx = 0;
5921 }
5922
5923 static void rtl_reset_work(struct rtl8169_private *tp)
5924 {
5925         struct net_device *dev = tp->dev;
5926         int i;
5927
5928         napi_disable(&tp->napi);
5929         netif_stop_queue(dev);
5930         synchronize_sched();
5931
5932         rtl8169_hw_reset(tp);
5933
5934         for (i = 0; i < NUM_RX_DESC; i++)
5935                 rtl8169_mark_to_asic(tp->RxDescArray + i);
5936
5937         rtl8169_tx_clear(tp);
5938         rtl8169_init_ring_indexes(tp);
5939
5940         napi_enable(&tp->napi);
5941         rtl_hw_start(tp);
5942         netif_wake_queue(dev);
5943 }
5944
5945 static void rtl8169_tx_timeout(struct net_device *dev)
5946 {
5947         struct rtl8169_private *tp = netdev_priv(dev);
5948
5949         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
5950 }
5951
5952 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
5953                               u32 *opts)
5954 {
5955         struct skb_shared_info *info = skb_shinfo(skb);
5956         unsigned int cur_frag, entry;
5957         struct TxDesc *uninitialized_var(txd);
5958         struct device *d = tp_to_dev(tp);
5959
5960         entry = tp->cur_tx;
5961         for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
5962                 const skb_frag_t *frag = info->frags + cur_frag;
5963                 dma_addr_t mapping;
5964                 u32 status, len;
5965                 void *addr;
5966
5967                 entry = (entry + 1) % NUM_TX_DESC;
5968
5969                 txd = tp->TxDescArray + entry;
5970                 len = skb_frag_size(frag);
5971                 addr = skb_frag_address(frag);
5972                 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
5973                 if (unlikely(dma_mapping_error(d, mapping))) {
5974                         if (net_ratelimit())
5975                                 netif_err(tp, drv, tp->dev,
5976                                           "Failed to map TX fragments DMA!\n");
5977                         goto err_out;
5978                 }
5979
5980                 /* Anti gcc 2.95.3 bugware (sic) */
5981                 status = opts[0] | len |
5982                         (RingEnd * !((entry + 1) % NUM_TX_DESC));
5983
5984                 txd->opts1 = cpu_to_le32(status);
5985                 txd->opts2 = cpu_to_le32(opts[1]);
5986                 txd->addr = cpu_to_le64(mapping);
5987
5988                 tp->tx_skb[entry].len = len;
5989         }
5990
5991         if (cur_frag) {
5992                 tp->tx_skb[entry].skb = skb;
5993                 txd->opts1 |= cpu_to_le32(LastFrag);
5994         }
5995
5996         return cur_frag;
5997
5998 err_out:
5999         rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
6000         return -EIO;
6001 }
6002
6003 static bool rtl_test_hw_pad_bug(struct rtl8169_private *tp, struct sk_buff *skb)
6004 {
6005         return skb->len < ETH_ZLEN && tp->mac_version == RTL_GIGA_MAC_VER_34;
6006 }
6007
6008 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
6009                                       struct net_device *dev);
6010 /* r8169_csum_workaround()
6011  * The hw limites the value the transport offset. When the offset is out of the
6012  * range, calculate the checksum by sw.
6013  */
6014 static void r8169_csum_workaround(struct rtl8169_private *tp,
6015                                   struct sk_buff *skb)
6016 {
6017         if (skb_shinfo(skb)->gso_size) {
6018                 netdev_features_t features = tp->dev->features;
6019                 struct sk_buff *segs, *nskb;
6020
6021                 features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
6022                 segs = skb_gso_segment(skb, features);
6023                 if (IS_ERR(segs) || !segs)
6024                         goto drop;
6025
6026                 do {
6027                         nskb = segs;
6028                         segs = segs->next;
6029                         nskb->next = NULL;
6030                         rtl8169_start_xmit(nskb, tp->dev);
6031                 } while (segs);
6032
6033                 dev_consume_skb_any(skb);
6034         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
6035                 if (skb_checksum_help(skb) < 0)
6036                         goto drop;
6037
6038                 rtl8169_start_xmit(skb, tp->dev);
6039         } else {
6040                 struct net_device_stats *stats;
6041
6042 drop:
6043                 stats = &tp->dev->stats;
6044                 stats->tx_dropped++;
6045                 dev_kfree_skb_any(skb);
6046         }
6047 }
6048
6049 /* msdn_giant_send_check()
6050  * According to the document of microsoft, the TCP Pseudo Header excludes the
6051  * packet length for IPv6 TCP large packets.
6052  */
6053 static int msdn_giant_send_check(struct sk_buff *skb)
6054 {
6055         const struct ipv6hdr *ipv6h;
6056         struct tcphdr *th;
6057         int ret;
6058
6059         ret = skb_cow_head(skb, 0);
6060         if (ret)
6061                 return ret;
6062
6063         ipv6h = ipv6_hdr(skb);
6064         th = tcp_hdr(skb);
6065
6066         th->check = 0;
6067         th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0);
6068
6069         return ret;
6070 }
6071
6072 static bool rtl8169_tso_csum_v1(struct rtl8169_private *tp,
6073                                 struct sk_buff *skb, u32 *opts)
6074 {
6075         u32 mss = skb_shinfo(skb)->gso_size;
6076
6077         if (mss) {
6078                 opts[0] |= TD_LSO;
6079                 opts[0] |= min(mss, TD_MSS_MAX) << TD0_MSS_SHIFT;
6080         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
6081                 const struct iphdr *ip = ip_hdr(skb);
6082
6083                 if (ip->protocol == IPPROTO_TCP)
6084                         opts[0] |= TD0_IP_CS | TD0_TCP_CS;
6085                 else if (ip->protocol == IPPROTO_UDP)
6086                         opts[0] |= TD0_IP_CS | TD0_UDP_CS;
6087                 else
6088                         WARN_ON_ONCE(1);
6089         }
6090
6091         return true;
6092 }
6093
6094 static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp,
6095                                 struct sk_buff *skb, u32 *opts)
6096 {
6097         u32 transport_offset = (u32)skb_transport_offset(skb);
6098         u32 mss = skb_shinfo(skb)->gso_size;
6099
6100         if (mss) {
6101                 if (transport_offset > GTTCPHO_MAX) {
6102                         netif_warn(tp, tx_err, tp->dev,
6103                                    "Invalid transport offset 0x%x for TSO\n",
6104                                    transport_offset);
6105                         return false;
6106                 }
6107
6108                 switch (vlan_get_protocol(skb)) {
6109                 case htons(ETH_P_IP):
6110                         opts[0] |= TD1_GTSENV4;
6111                         break;
6112
6113                 case htons(ETH_P_IPV6):
6114                         if (msdn_giant_send_check(skb))
6115                                 return false;
6116
6117                         opts[0] |= TD1_GTSENV6;
6118                         break;
6119
6120                 default:
6121                         WARN_ON_ONCE(1);
6122                         break;
6123                 }
6124
6125                 opts[0] |= transport_offset << GTTCPHO_SHIFT;
6126                 opts[1] |= min(mss, TD_MSS_MAX) << TD1_MSS_SHIFT;
6127         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
6128                 u8 ip_protocol;
6129
6130                 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
6131                         return !(skb_checksum_help(skb) || eth_skb_pad(skb));
6132
6133                 if (transport_offset > TCPHO_MAX) {
6134                         netif_warn(tp, tx_err, tp->dev,
6135                                    "Invalid transport offset 0x%x\n",
6136                                    transport_offset);
6137                         return false;
6138                 }
6139
6140                 switch (vlan_get_protocol(skb)) {
6141                 case htons(ETH_P_IP):
6142                         opts[1] |= TD1_IPv4_CS;
6143                         ip_protocol = ip_hdr(skb)->protocol;
6144                         break;
6145
6146                 case htons(ETH_P_IPV6):
6147                         opts[1] |= TD1_IPv6_CS;
6148                         ip_protocol = ipv6_hdr(skb)->nexthdr;
6149                         break;
6150
6151                 default:
6152                         ip_protocol = IPPROTO_RAW;
6153                         break;
6154                 }
6155
6156                 if (ip_protocol == IPPROTO_TCP)
6157                         opts[1] |= TD1_TCP_CS;
6158                 else if (ip_protocol == IPPROTO_UDP)
6159                         opts[1] |= TD1_UDP_CS;
6160                 else
6161                         WARN_ON_ONCE(1);
6162
6163                 opts[1] |= transport_offset << TCPHO_SHIFT;
6164         } else {
6165                 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
6166                         return !eth_skb_pad(skb);
6167         }
6168
6169         return true;
6170 }
6171
6172 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
6173                                       struct net_device *dev)
6174 {
6175         struct rtl8169_private *tp = netdev_priv(dev);
6176         unsigned int entry = tp->cur_tx % NUM_TX_DESC;
6177         struct TxDesc *txd = tp->TxDescArray + entry;
6178         struct device *d = tp_to_dev(tp);
6179         dma_addr_t mapping;
6180         u32 status, len;
6181         u32 opts[2];
6182         int frags;
6183
6184         if (unlikely(!TX_FRAGS_READY_FOR(tp, skb_shinfo(skb)->nr_frags))) {
6185                 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
6186                 goto err_stop_0;
6187         }
6188
6189         if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
6190                 goto err_stop_0;
6191
6192         opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(skb));
6193         opts[0] = DescOwn;
6194
6195         if (!tp->tso_csum(tp, skb, opts)) {
6196                 r8169_csum_workaround(tp, skb);
6197                 return NETDEV_TX_OK;
6198         }
6199
6200         len = skb_headlen(skb);
6201         mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
6202         if (unlikely(dma_mapping_error(d, mapping))) {
6203                 if (net_ratelimit())
6204                         netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
6205                 goto err_dma_0;
6206         }
6207
6208         tp->tx_skb[entry].len = len;
6209         txd->addr = cpu_to_le64(mapping);
6210
6211         frags = rtl8169_xmit_frags(tp, skb, opts);
6212         if (frags < 0)
6213                 goto err_dma_1;
6214         else if (frags)
6215                 opts[0] |= FirstFrag;
6216         else {
6217                 opts[0] |= FirstFrag | LastFrag;
6218                 tp->tx_skb[entry].skb = skb;
6219         }
6220
6221         txd->opts2 = cpu_to_le32(opts[1]);
6222
6223         skb_tx_timestamp(skb);
6224
6225         /* Force memory writes to complete before releasing descriptor */
6226         dma_wmb();
6227
6228         /* Anti gcc 2.95.3 bugware (sic) */
6229         status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
6230         txd->opts1 = cpu_to_le32(status);
6231
6232         /* Force all memory writes to complete before notifying device */
6233         wmb();
6234
6235         tp->cur_tx += frags + 1;
6236
6237         RTL_W8(tp, TxPoll, NPQ);
6238
6239         mmiowb();
6240
6241         if (!TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
6242                 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
6243                  * not miss a ring update when it notices a stopped queue.
6244                  */
6245                 smp_wmb();
6246                 netif_stop_queue(dev);
6247                 /* Sync with rtl_tx:
6248                  * - publish queue status and cur_tx ring index (write barrier)
6249                  * - refresh dirty_tx ring index (read barrier).
6250                  * May the current thread have a pessimistic view of the ring
6251                  * status and forget to wake up queue, a racing rtl_tx thread
6252                  * can't.
6253                  */
6254                 smp_mb();
6255                 if (TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS))
6256                         netif_wake_queue(dev);
6257         }
6258
6259         return NETDEV_TX_OK;
6260
6261 err_dma_1:
6262         rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
6263 err_dma_0:
6264         dev_kfree_skb_any(skb);
6265         dev->stats.tx_dropped++;
6266         return NETDEV_TX_OK;
6267
6268 err_stop_0:
6269         netif_stop_queue(dev);
6270         dev->stats.tx_dropped++;
6271         return NETDEV_TX_BUSY;
6272 }
6273
6274 static void rtl8169_pcierr_interrupt(struct net_device *dev)
6275 {
6276         struct rtl8169_private *tp = netdev_priv(dev);
6277         struct pci_dev *pdev = tp->pci_dev;
6278         u16 pci_status, pci_cmd;
6279
6280         pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
6281         pci_read_config_word(pdev, PCI_STATUS, &pci_status);
6282
6283         netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
6284                   pci_cmd, pci_status);
6285
6286         /*
6287          * The recovery sequence below admits a very elaborated explanation:
6288          * - it seems to work;
6289          * - I did not see what else could be done;
6290          * - it makes iop3xx happy.
6291          *
6292          * Feel free to adjust to your needs.
6293          */
6294         if (pdev->broken_parity_status)
6295                 pci_cmd &= ~PCI_COMMAND_PARITY;
6296         else
6297                 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
6298
6299         pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
6300
6301         pci_write_config_word(pdev, PCI_STATUS,
6302                 pci_status & (PCI_STATUS_DETECTED_PARITY |
6303                 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
6304                 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
6305
6306         /* The infamous DAC f*ckup only happens at boot time */
6307         if ((tp->cp_cmd & PCIDAC) && !tp->cur_rx) {
6308                 netif_info(tp, intr, dev, "disabling PCI DAC\n");
6309                 tp->cp_cmd &= ~PCIDAC;
6310                 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
6311                 dev->features &= ~NETIF_F_HIGHDMA;
6312         }
6313
6314         rtl8169_hw_reset(tp);
6315
6316         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
6317 }
6318
6319 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp)
6320 {
6321         unsigned int dirty_tx, tx_left;
6322
6323         dirty_tx = tp->dirty_tx;
6324         smp_rmb();
6325         tx_left = tp->cur_tx - dirty_tx;
6326
6327         while (tx_left > 0) {
6328                 unsigned int entry = dirty_tx % NUM_TX_DESC;
6329                 struct ring_info *tx_skb = tp->tx_skb + entry;
6330                 u32 status;
6331
6332                 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
6333                 if (status & DescOwn)
6334                         break;
6335
6336                 /* This barrier is needed to keep us from reading
6337                  * any other fields out of the Tx descriptor until
6338                  * we know the status of DescOwn
6339                  */
6340                 dma_rmb();
6341
6342                 rtl8169_unmap_tx_skb(tp_to_dev(tp), tx_skb,
6343                                      tp->TxDescArray + entry);
6344                 if (status & LastFrag) {
6345                         u64_stats_update_begin(&tp->tx_stats.syncp);
6346                         tp->tx_stats.packets++;
6347                         tp->tx_stats.bytes += tx_skb->skb->len;
6348                         u64_stats_update_end(&tp->tx_stats.syncp);
6349                         dev_consume_skb_any(tx_skb->skb);
6350                         tx_skb->skb = NULL;
6351                 }
6352                 dirty_tx++;
6353                 tx_left--;
6354         }
6355
6356         if (tp->dirty_tx != dirty_tx) {
6357                 tp->dirty_tx = dirty_tx;
6358                 /* Sync with rtl8169_start_xmit:
6359                  * - publish dirty_tx ring index (write barrier)
6360                  * - refresh cur_tx ring index and queue status (read barrier)
6361                  * May the current thread miss the stopped queue condition,
6362                  * a racing xmit thread can only have a right view of the
6363                  * ring status.
6364                  */
6365                 smp_mb();
6366                 if (netif_queue_stopped(dev) &&
6367                     TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
6368                         netif_wake_queue(dev);
6369                 }
6370                 /*
6371                  * 8168 hack: TxPoll requests are lost when the Tx packets are
6372                  * too close. Let's kick an extra TxPoll request when a burst
6373                  * of start_xmit activity is detected (if it is not detected,
6374                  * it is slow enough). -- FR
6375                  */
6376                 if (tp->cur_tx != dirty_tx)
6377                         RTL_W8(tp, TxPoll, NPQ);
6378         }
6379 }
6380
6381 static inline int rtl8169_fragmented_frame(u32 status)
6382 {
6383         return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
6384 }
6385
6386 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
6387 {
6388         u32 status = opts1 & RxProtoMask;
6389
6390         if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
6391             ((status == RxProtoUDP) && !(opts1 & UDPFail)))
6392                 skb->ip_summed = CHECKSUM_UNNECESSARY;
6393         else
6394                 skb_checksum_none_assert(skb);
6395 }
6396
6397 static struct sk_buff *rtl8169_try_rx_copy(void *data,
6398                                            struct rtl8169_private *tp,
6399                                            int pkt_size,
6400                                            dma_addr_t addr)
6401 {
6402         struct sk_buff *skb;
6403         struct device *d = tp_to_dev(tp);
6404
6405         data = rtl8169_align(data);
6406         dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
6407         prefetch(data);
6408         skb = napi_alloc_skb(&tp->napi, pkt_size);
6409         if (skb)
6410                 skb_copy_to_linear_data(skb, data, pkt_size);
6411         dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
6412
6413         return skb;
6414 }
6415
6416 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget)
6417 {
6418         unsigned int cur_rx, rx_left;
6419         unsigned int count;
6420
6421         cur_rx = tp->cur_rx;
6422
6423         for (rx_left = min(budget, NUM_RX_DESC); rx_left > 0; rx_left--, cur_rx++) {
6424                 unsigned int entry = cur_rx % NUM_RX_DESC;
6425                 struct RxDesc *desc = tp->RxDescArray + entry;
6426                 u32 status;
6427
6428                 status = le32_to_cpu(desc->opts1);
6429                 if (status & DescOwn)
6430                         break;
6431
6432                 /* This barrier is needed to keep us from reading
6433                  * any other fields out of the Rx descriptor until
6434                  * we know the status of DescOwn
6435                  */
6436                 dma_rmb();
6437
6438                 if (unlikely(status & RxRES)) {
6439                         netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
6440                                    status);
6441                         dev->stats.rx_errors++;
6442                         if (status & (RxRWT | RxRUNT))
6443                                 dev->stats.rx_length_errors++;
6444                         if (status & RxCRC)
6445                                 dev->stats.rx_crc_errors++;
6446                         /* RxFOVF is a reserved bit on later chip versions */
6447                         if (tp->mac_version == RTL_GIGA_MAC_VER_01 &&
6448                             status & RxFOVF) {
6449                                 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
6450                                 dev->stats.rx_fifo_errors++;
6451                         } else if (status & (RxRUNT | RxCRC) &&
6452                                    !(status & RxRWT) &&
6453                                    dev->features & NETIF_F_RXALL) {
6454                                 goto process_pkt;
6455                         }
6456                 } else {
6457                         struct sk_buff *skb;
6458                         dma_addr_t addr;
6459                         int pkt_size;
6460
6461 process_pkt:
6462                         addr = le64_to_cpu(desc->addr);
6463                         if (likely(!(dev->features & NETIF_F_RXFCS)))
6464                                 pkt_size = (status & 0x00003fff) - 4;
6465                         else
6466                                 pkt_size = status & 0x00003fff;
6467
6468                         /*
6469                          * The driver does not support incoming fragmented
6470                          * frames. They are seen as a symptom of over-mtu
6471                          * sized frames.
6472                          */
6473                         if (unlikely(rtl8169_fragmented_frame(status))) {
6474                                 dev->stats.rx_dropped++;
6475                                 dev->stats.rx_length_errors++;
6476                                 goto release_descriptor;
6477                         }
6478
6479                         skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
6480                                                   tp, pkt_size, addr);
6481                         if (!skb) {
6482                                 dev->stats.rx_dropped++;
6483                                 goto release_descriptor;
6484                         }
6485
6486                         rtl8169_rx_csum(skb, status);
6487                         skb_put(skb, pkt_size);
6488                         skb->protocol = eth_type_trans(skb, dev);
6489
6490                         rtl8169_rx_vlan_tag(desc, skb);
6491
6492                         if (skb->pkt_type == PACKET_MULTICAST)
6493                                 dev->stats.multicast++;
6494
6495                         napi_gro_receive(&tp->napi, skb);
6496
6497                         u64_stats_update_begin(&tp->rx_stats.syncp);
6498                         tp->rx_stats.packets++;
6499                         tp->rx_stats.bytes += pkt_size;
6500                         u64_stats_update_end(&tp->rx_stats.syncp);
6501                 }
6502 release_descriptor:
6503                 desc->opts2 = 0;
6504                 rtl8169_mark_to_asic(desc);
6505         }
6506
6507         count = cur_rx - tp->cur_rx;
6508         tp->cur_rx = cur_rx;
6509
6510         return count;
6511 }
6512
6513 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
6514 {
6515         struct rtl8169_private *tp = dev_instance;
6516         u16 status = rtl_get_events(tp);
6517
6518         if (status == 0xffff || !(status & (RTL_EVENT_NAPI | tp->event_slow)))
6519                 return IRQ_NONE;
6520
6521         rtl_irq_disable(tp);
6522         napi_schedule_irqoff(&tp->napi);
6523
6524         return IRQ_HANDLED;
6525 }
6526
6527 /*
6528  * Workqueue context.
6529  */
6530 static void rtl_slow_event_work(struct rtl8169_private *tp)
6531 {
6532         struct net_device *dev = tp->dev;
6533         u16 status;
6534
6535         status = rtl_get_events(tp) & tp->event_slow;
6536         rtl_ack_events(tp, status);
6537
6538         if (unlikely(status & RxFIFOOver)) {
6539                 switch (tp->mac_version) {
6540                 /* Work around for rx fifo overflow */
6541                 case RTL_GIGA_MAC_VER_11:
6542                         netif_stop_queue(dev);
6543                         /* XXX - Hack alert. See rtl_task(). */
6544                         set_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags);
6545                 default:
6546                         break;
6547                 }
6548         }
6549
6550         if (unlikely(status & SYSErr))
6551                 rtl8169_pcierr_interrupt(dev);
6552
6553         if (status & LinkChg)
6554                 phy_mac_interrupt(dev->phydev);
6555
6556         rtl_irq_enable_all(tp);
6557 }
6558
6559 static void rtl_task(struct work_struct *work)
6560 {
6561         static const struct {
6562                 int bitnr;
6563                 void (*action)(struct rtl8169_private *);
6564         } rtl_work[] = {
6565                 /* XXX - keep rtl_slow_event_work() as first element. */
6566                 { RTL_FLAG_TASK_SLOW_PENDING,   rtl_slow_event_work },
6567                 { RTL_FLAG_TASK_RESET_PENDING,  rtl_reset_work },
6568         };
6569         struct rtl8169_private *tp =
6570                 container_of(work, struct rtl8169_private, wk.work);
6571         struct net_device *dev = tp->dev;
6572         int i;
6573
6574         rtl_lock_work(tp);
6575
6576         if (!netif_running(dev) ||
6577             !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
6578                 goto out_unlock;
6579
6580         for (i = 0; i < ARRAY_SIZE(rtl_work); i++) {
6581                 bool pending;
6582
6583                 pending = test_and_clear_bit(rtl_work[i].bitnr, tp->wk.flags);
6584                 if (pending)
6585                         rtl_work[i].action(tp);
6586         }
6587
6588 out_unlock:
6589         rtl_unlock_work(tp);
6590 }
6591
6592 static int rtl8169_poll(struct napi_struct *napi, int budget)
6593 {
6594         struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
6595         struct net_device *dev = tp->dev;
6596         u16 enable_mask = RTL_EVENT_NAPI | tp->event_slow;
6597         int work_done= 0;
6598         u16 status;
6599
6600         status = rtl_get_events(tp);
6601         rtl_ack_events(tp, status & ~tp->event_slow);
6602
6603         if (status & RTL_EVENT_NAPI_RX)
6604                 work_done = rtl_rx(dev, tp, (u32) budget);
6605
6606         if (status & RTL_EVENT_NAPI_TX)
6607                 rtl_tx(dev, tp);
6608
6609         if (status & tp->event_slow) {
6610                 enable_mask &= ~tp->event_slow;
6611
6612                 rtl_schedule_task(tp, RTL_FLAG_TASK_SLOW_PENDING);
6613         }
6614
6615         if (work_done < budget) {
6616                 napi_complete_done(napi, work_done);
6617
6618                 rtl_irq_enable(tp, enable_mask);
6619                 mmiowb();
6620         }
6621
6622         return work_done;
6623 }
6624
6625 static void rtl8169_rx_missed(struct net_device *dev)
6626 {
6627         struct rtl8169_private *tp = netdev_priv(dev);
6628
6629         if (tp->mac_version > RTL_GIGA_MAC_VER_06)
6630                 return;
6631
6632         dev->stats.rx_missed_errors += RTL_R32(tp, RxMissed) & 0xffffff;
6633         RTL_W32(tp, RxMissed, 0);
6634 }
6635
6636 static void r8169_phylink_handler(struct net_device *ndev)
6637 {
6638         struct rtl8169_private *tp = netdev_priv(ndev);
6639
6640         if (netif_carrier_ok(ndev)) {
6641                 rtl_link_chg_patch(tp);
6642                 pm_request_resume(&tp->pci_dev->dev);
6643         } else {
6644                 pm_runtime_idle(&tp->pci_dev->dev);
6645         }
6646
6647         if (net_ratelimit())
6648                 phy_print_status(ndev->phydev);
6649 }
6650
6651 static int r8169_phy_connect(struct rtl8169_private *tp)
6652 {
6653         struct phy_device *phydev = mdiobus_get_phy(tp->mii_bus, 0);
6654         phy_interface_t phy_mode;
6655         int ret;
6656
6657         phy_mode = tp->supports_gmii ? PHY_INTERFACE_MODE_GMII :
6658                    PHY_INTERFACE_MODE_MII;
6659
6660         ret = phy_connect_direct(tp->dev, phydev, r8169_phylink_handler,
6661                                  phy_mode);
6662         if (ret)
6663                 return ret;
6664
6665         if (!tp->supports_gmii)
6666                 phy_set_max_speed(phydev, SPEED_100);
6667
6668         /* Ensure to advertise everything, incl. pause */
6669         phydev->advertising = phydev->supported;
6670
6671         phy_attached_info(phydev);
6672
6673         return 0;
6674 }
6675
6676 static void rtl8169_down(struct net_device *dev)
6677 {
6678         struct rtl8169_private *tp = netdev_priv(dev);
6679
6680         phy_stop(dev->phydev);
6681
6682         napi_disable(&tp->napi);
6683         netif_stop_queue(dev);
6684
6685         rtl8169_hw_reset(tp);
6686         /*
6687          * At this point device interrupts can not be enabled in any function,
6688          * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task)
6689          * and napi is disabled (rtl8169_poll).
6690          */
6691         rtl8169_rx_missed(dev);
6692
6693         /* Give a racing hard_start_xmit a few cycles to complete. */
6694         synchronize_sched();
6695
6696         rtl8169_tx_clear(tp);
6697
6698         rtl8169_rx_clear(tp);
6699
6700         rtl_pll_power_down(tp);
6701 }
6702
6703 static int rtl8169_close(struct net_device *dev)
6704 {
6705         struct rtl8169_private *tp = netdev_priv(dev);
6706         struct pci_dev *pdev = tp->pci_dev;
6707
6708         pm_runtime_get_sync(&pdev->dev);
6709
6710         /* Update counters before going down */
6711         rtl8169_update_counters(tp);
6712
6713         rtl_lock_work(tp);
6714         clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6715
6716         rtl8169_down(dev);
6717         rtl_unlock_work(tp);
6718
6719         cancel_work_sync(&tp->wk.work);
6720
6721         phy_disconnect(dev->phydev);
6722
6723         pci_free_irq(pdev, 0, tp);
6724
6725         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6726                           tp->RxPhyAddr);
6727         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6728                           tp->TxPhyAddr);
6729         tp->TxDescArray = NULL;
6730         tp->RxDescArray = NULL;
6731
6732         pm_runtime_put_sync(&pdev->dev);
6733
6734         return 0;
6735 }
6736
6737 #ifdef CONFIG_NET_POLL_CONTROLLER
6738 static void rtl8169_netpoll(struct net_device *dev)
6739 {
6740         struct rtl8169_private *tp = netdev_priv(dev);
6741
6742         rtl8169_interrupt(pci_irq_vector(tp->pci_dev, 0), tp);
6743 }
6744 #endif
6745
6746 static int rtl_open(struct net_device *dev)
6747 {
6748         struct rtl8169_private *tp = netdev_priv(dev);
6749         struct pci_dev *pdev = tp->pci_dev;
6750         int retval = -ENOMEM;
6751
6752         pm_runtime_get_sync(&pdev->dev);
6753
6754         /*
6755          * Rx and Tx descriptors needs 256 bytes alignment.
6756          * dma_alloc_coherent provides more.
6757          */
6758         tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
6759                                              &tp->TxPhyAddr, GFP_KERNEL);
6760         if (!tp->TxDescArray)
6761                 goto err_pm_runtime_put;
6762
6763         tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
6764                                              &tp->RxPhyAddr, GFP_KERNEL);
6765         if (!tp->RxDescArray)
6766                 goto err_free_tx_0;
6767
6768         retval = rtl8169_init_ring(tp);
6769         if (retval < 0)
6770                 goto err_free_rx_1;
6771
6772         INIT_WORK(&tp->wk.work, rtl_task);
6773
6774         smp_mb();
6775
6776         rtl_request_firmware(tp);
6777
6778         retval = pci_request_irq(pdev, 0, rtl8169_interrupt, NULL, tp,
6779                                  dev->name);
6780         if (retval < 0)
6781                 goto err_release_fw_2;
6782
6783         retval = r8169_phy_connect(tp);
6784         if (retval)
6785                 goto err_free_irq;
6786
6787         rtl_lock_work(tp);
6788
6789         set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6790
6791         napi_enable(&tp->napi);
6792
6793         rtl8169_init_phy(dev, tp);
6794
6795         rtl_pll_power_up(tp);
6796
6797         rtl_hw_start(tp);
6798
6799         if (!rtl8169_init_counter_offsets(tp))
6800                 netif_warn(tp, hw, dev, "counter reset/update failed\n");
6801
6802         phy_start(dev->phydev);
6803         netif_start_queue(dev);
6804
6805         rtl_unlock_work(tp);
6806
6807         pm_runtime_put_sync(&pdev->dev);
6808 out:
6809         return retval;
6810
6811 err_free_irq:
6812         pci_free_irq(pdev, 0, tp);
6813 err_release_fw_2:
6814         rtl_release_firmware(tp);
6815         rtl8169_rx_clear(tp);
6816 err_free_rx_1:
6817         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6818                           tp->RxPhyAddr);
6819         tp->RxDescArray = NULL;
6820 err_free_tx_0:
6821         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6822                           tp->TxPhyAddr);
6823         tp->TxDescArray = NULL;
6824 err_pm_runtime_put:
6825         pm_runtime_put_noidle(&pdev->dev);
6826         goto out;
6827 }
6828
6829 static void
6830 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
6831 {
6832         struct rtl8169_private *tp = netdev_priv(dev);
6833         struct pci_dev *pdev = tp->pci_dev;
6834         struct rtl8169_counters *counters = tp->counters;
6835         unsigned int start;
6836
6837         pm_runtime_get_noresume(&pdev->dev);
6838
6839         if (netif_running(dev) && pm_runtime_active(&pdev->dev))
6840                 rtl8169_rx_missed(dev);
6841
6842         do {
6843                 start = u64_stats_fetch_begin_irq(&tp->rx_stats.syncp);
6844                 stats->rx_packets = tp->rx_stats.packets;
6845                 stats->rx_bytes = tp->rx_stats.bytes;
6846         } while (u64_stats_fetch_retry_irq(&tp->rx_stats.syncp, start));
6847
6848         do {
6849                 start = u64_stats_fetch_begin_irq(&tp->tx_stats.syncp);
6850                 stats->tx_packets = tp->tx_stats.packets;
6851                 stats->tx_bytes = tp->tx_stats.bytes;
6852         } while (u64_stats_fetch_retry_irq(&tp->tx_stats.syncp, start));
6853
6854         stats->rx_dropped       = dev->stats.rx_dropped;
6855         stats->tx_dropped       = dev->stats.tx_dropped;
6856         stats->rx_length_errors = dev->stats.rx_length_errors;
6857         stats->rx_errors        = dev->stats.rx_errors;
6858         stats->rx_crc_errors    = dev->stats.rx_crc_errors;
6859         stats->rx_fifo_errors   = dev->stats.rx_fifo_errors;
6860         stats->rx_missed_errors = dev->stats.rx_missed_errors;
6861         stats->multicast        = dev->stats.multicast;
6862
6863         /*
6864          * Fetch additonal counter values missing in stats collected by driver
6865          * from tally counters.
6866          */
6867         if (pm_runtime_active(&pdev->dev))
6868                 rtl8169_update_counters(tp);
6869
6870         /*
6871          * Subtract values fetched during initalization.
6872          * See rtl8169_init_counter_offsets for a description why we do that.
6873          */
6874         stats->tx_errors = le64_to_cpu(counters->tx_errors) -
6875                 le64_to_cpu(tp->tc_offset.tx_errors);
6876         stats->collisions = le32_to_cpu(counters->tx_multi_collision) -
6877                 le32_to_cpu(tp->tc_offset.tx_multi_collision);
6878         stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) -
6879                 le16_to_cpu(tp->tc_offset.tx_aborted);
6880
6881         pm_runtime_put_noidle(&pdev->dev);
6882 }
6883
6884 static void rtl8169_net_suspend(struct net_device *dev)
6885 {
6886         struct rtl8169_private *tp = netdev_priv(dev);
6887
6888         if (!netif_running(dev))
6889                 return;
6890
6891         phy_stop(dev->phydev);
6892         netif_device_detach(dev);
6893         netif_stop_queue(dev);
6894
6895         rtl_lock_work(tp);
6896         napi_disable(&tp->napi);
6897         clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6898         rtl_unlock_work(tp);
6899
6900         rtl_pll_power_down(tp);
6901 }
6902
6903 #ifdef CONFIG_PM
6904
6905 static int rtl8169_suspend(struct device *device)
6906 {
6907         struct pci_dev *pdev = to_pci_dev(device);
6908         struct net_device *dev = pci_get_drvdata(pdev);
6909
6910         rtl8169_net_suspend(dev);
6911
6912         return 0;
6913 }
6914
6915 static void __rtl8169_resume(struct net_device *dev)
6916 {
6917         struct rtl8169_private *tp = netdev_priv(dev);
6918
6919         netif_device_attach(dev);
6920
6921         rtl_pll_power_up(tp);
6922         rtl8169_init_phy(dev, tp);
6923
6924         phy_start(tp->dev->phydev);
6925
6926         rtl_lock_work(tp);
6927         napi_enable(&tp->napi);
6928         set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6929         rtl_unlock_work(tp);
6930
6931         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
6932 }
6933
6934 static int rtl8169_resume(struct device *device)
6935 {
6936         struct pci_dev *pdev = to_pci_dev(device);
6937         struct net_device *dev = pci_get_drvdata(pdev);
6938
6939         if (netif_running(dev))
6940                 __rtl8169_resume(dev);
6941
6942         return 0;
6943 }
6944
6945 static int rtl8169_runtime_suspend(struct device *device)
6946 {
6947         struct pci_dev *pdev = to_pci_dev(device);
6948         struct net_device *dev = pci_get_drvdata(pdev);
6949         struct rtl8169_private *tp = netdev_priv(dev);
6950
6951         if (!tp->TxDescArray)
6952                 return 0;
6953
6954         rtl_lock_work(tp);
6955         __rtl8169_set_wol(tp, WAKE_ANY);
6956         rtl_unlock_work(tp);
6957
6958         rtl8169_net_suspend(dev);
6959
6960         /* Update counters before going runtime suspend */
6961         rtl8169_rx_missed(dev);
6962         rtl8169_update_counters(tp);
6963
6964         return 0;
6965 }
6966
6967 static int rtl8169_runtime_resume(struct device *device)
6968 {
6969         struct pci_dev *pdev = to_pci_dev(device);
6970         struct net_device *dev = pci_get_drvdata(pdev);
6971         struct rtl8169_private *tp = netdev_priv(dev);
6972         rtl_rar_set(tp, dev->dev_addr);
6973
6974         if (!tp->TxDescArray)
6975                 return 0;
6976
6977         rtl_lock_work(tp);
6978         __rtl8169_set_wol(tp, tp->saved_wolopts);
6979         rtl_unlock_work(tp);
6980
6981         __rtl8169_resume(dev);
6982
6983         return 0;
6984 }
6985
6986 static int rtl8169_runtime_idle(struct device *device)
6987 {
6988         struct pci_dev *pdev = to_pci_dev(device);
6989         struct net_device *dev = pci_get_drvdata(pdev);
6990
6991         if (!netif_running(dev) || !netif_carrier_ok(dev))
6992                 pm_schedule_suspend(device, 10000);
6993
6994         return -EBUSY;
6995 }
6996
6997 static const struct dev_pm_ops rtl8169_pm_ops = {
6998         .suspend                = rtl8169_suspend,
6999         .resume                 = rtl8169_resume,
7000         .freeze                 = rtl8169_suspend,
7001         .thaw                   = rtl8169_resume,
7002         .poweroff               = rtl8169_suspend,
7003         .restore                = rtl8169_resume,
7004         .runtime_suspend        = rtl8169_runtime_suspend,
7005         .runtime_resume         = rtl8169_runtime_resume,
7006         .runtime_idle           = rtl8169_runtime_idle,
7007 };
7008
7009 #define RTL8169_PM_OPS  (&rtl8169_pm_ops)
7010
7011 #else /* !CONFIG_PM */
7012
7013 #define RTL8169_PM_OPS  NULL
7014
7015 #endif /* !CONFIG_PM */
7016
7017 static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
7018 {
7019         /* WoL fails with 8168b when the receiver is disabled. */
7020         switch (tp->mac_version) {
7021         case RTL_GIGA_MAC_VER_11:
7022         case RTL_GIGA_MAC_VER_12:
7023         case RTL_GIGA_MAC_VER_17:
7024                 pci_clear_master(tp->pci_dev);
7025
7026                 RTL_W8(tp, ChipCmd, CmdRxEnb);
7027                 /* PCI commit */
7028                 RTL_R8(tp, ChipCmd);
7029                 break;
7030         default:
7031                 break;
7032         }
7033 }
7034
7035 static void rtl_shutdown(struct pci_dev *pdev)
7036 {
7037         struct net_device *dev = pci_get_drvdata(pdev);
7038         struct rtl8169_private *tp = netdev_priv(dev);
7039
7040         rtl8169_net_suspend(dev);
7041
7042         /* Restore original MAC address */
7043         rtl_rar_set(tp, dev->perm_addr);
7044
7045         rtl8169_hw_reset(tp);
7046
7047         if (system_state == SYSTEM_POWER_OFF) {
7048                 if (tp->saved_wolopts) {
7049                         rtl_wol_suspend_quirk(tp);
7050                         rtl_wol_shutdown_quirk(tp);
7051                 }
7052
7053                 pci_wake_from_d3(pdev, true);
7054                 pci_set_power_state(pdev, PCI_D3hot);
7055         }
7056 }
7057
7058 static void rtl_remove_one(struct pci_dev *pdev)
7059 {
7060         struct net_device *dev = pci_get_drvdata(pdev);
7061         struct rtl8169_private *tp = netdev_priv(dev);
7062
7063         if (r8168_check_dash(tp))
7064                 rtl8168_driver_stop(tp);
7065
7066         netif_napi_del(&tp->napi);
7067
7068         unregister_netdev(dev);
7069         mdiobus_unregister(tp->mii_bus);
7070
7071         rtl_release_firmware(tp);
7072
7073         if (pci_dev_run_wake(pdev))
7074                 pm_runtime_get_noresume(&pdev->dev);
7075
7076         /* restore original MAC address */
7077         rtl_rar_set(tp, dev->perm_addr);
7078 }
7079
7080 static const struct net_device_ops rtl_netdev_ops = {
7081         .ndo_open               = rtl_open,
7082         .ndo_stop               = rtl8169_close,
7083         .ndo_get_stats64        = rtl8169_get_stats64,
7084         .ndo_start_xmit         = rtl8169_start_xmit,
7085         .ndo_tx_timeout         = rtl8169_tx_timeout,
7086         .ndo_validate_addr      = eth_validate_addr,
7087         .ndo_change_mtu         = rtl8169_change_mtu,
7088         .ndo_fix_features       = rtl8169_fix_features,
7089         .ndo_set_features       = rtl8169_set_features,
7090         .ndo_set_mac_address    = rtl_set_mac_address,
7091         .ndo_do_ioctl           = rtl8169_ioctl,
7092         .ndo_set_rx_mode        = rtl_set_rx_mode,
7093 #ifdef CONFIG_NET_POLL_CONTROLLER
7094         .ndo_poll_controller    = rtl8169_netpoll,
7095 #endif
7096
7097 };
7098
7099 static const struct rtl_cfg_info {
7100         void (*hw_start)(struct rtl8169_private *tp);
7101         u16 event_slow;
7102         unsigned int has_gmii:1;
7103         const struct rtl_coalesce_info *coalesce_info;
7104         u8 default_ver;
7105 } rtl_cfg_infos [] = {
7106         [RTL_CFG_0] = {
7107                 .hw_start       = rtl_hw_start_8169,
7108                 .event_slow     = SYSErr | LinkChg | RxOverflow | RxFIFOOver,
7109                 .has_gmii       = 1,
7110                 .coalesce_info  = rtl_coalesce_info_8169,
7111                 .default_ver    = RTL_GIGA_MAC_VER_01,
7112         },
7113         [RTL_CFG_1] = {
7114                 .hw_start       = rtl_hw_start_8168,
7115                 .event_slow     = SYSErr | LinkChg | RxOverflow,
7116                 .has_gmii       = 1,
7117                 .coalesce_info  = rtl_coalesce_info_8168_8136,
7118                 .default_ver    = RTL_GIGA_MAC_VER_11,
7119         },
7120         [RTL_CFG_2] = {
7121                 .hw_start       = rtl_hw_start_8101,
7122                 .event_slow     = SYSErr | LinkChg | RxOverflow | RxFIFOOver |
7123                                   PCSTimeout,
7124                 .coalesce_info  = rtl_coalesce_info_8168_8136,
7125                 .default_ver    = RTL_GIGA_MAC_VER_13,
7126         }
7127 };
7128
7129 static int rtl_alloc_irq(struct rtl8169_private *tp)
7130 {
7131         unsigned int flags;
7132
7133         if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
7134                 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
7135                 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~MSIEnable);
7136                 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
7137                 flags = PCI_IRQ_LEGACY;
7138         } else {
7139                 flags = PCI_IRQ_ALL_TYPES;
7140         }
7141
7142         return pci_alloc_irq_vectors(tp->pci_dev, 1, 1, flags);
7143 }
7144
7145 DECLARE_RTL_COND(rtl_link_list_ready_cond)
7146 {
7147         return RTL_R8(tp, MCU) & LINK_LIST_RDY;
7148 }
7149
7150 DECLARE_RTL_COND(rtl_rxtx_empty_cond)
7151 {
7152         return (RTL_R8(tp, MCU) & RXTX_EMPTY) == RXTX_EMPTY;
7153 }
7154
7155 static int r8169_mdio_read_reg(struct mii_bus *mii_bus, int phyaddr, int phyreg)
7156 {
7157         struct rtl8169_private *tp = mii_bus->priv;
7158
7159         if (phyaddr > 0)
7160                 return -ENODEV;
7161
7162         return rtl_readphy(tp, phyreg);
7163 }
7164
7165 static int r8169_mdio_write_reg(struct mii_bus *mii_bus, int phyaddr,
7166                                 int phyreg, u16 val)
7167 {
7168         struct rtl8169_private *tp = mii_bus->priv;
7169
7170         if (phyaddr > 0)
7171                 return -ENODEV;
7172
7173         rtl_writephy(tp, phyreg, val);
7174
7175         return 0;
7176 }
7177
7178 static int r8169_mdio_register(struct rtl8169_private *tp)
7179 {
7180         struct pci_dev *pdev = tp->pci_dev;
7181         struct phy_device *phydev;
7182         struct mii_bus *new_bus;
7183         int ret;
7184
7185         new_bus = devm_mdiobus_alloc(&pdev->dev);
7186         if (!new_bus)
7187                 return -ENOMEM;
7188
7189         new_bus->name = "r8169";
7190         new_bus->priv = tp;
7191         new_bus->parent = &pdev->dev;
7192         new_bus->irq[0] = PHY_IGNORE_INTERRUPT;
7193         snprintf(new_bus->id, MII_BUS_ID_SIZE, "r8169-%x",
7194                  PCI_DEVID(pdev->bus->number, pdev->devfn));
7195
7196         new_bus->read = r8169_mdio_read_reg;
7197         new_bus->write = r8169_mdio_write_reg;
7198
7199         ret = mdiobus_register(new_bus);
7200         if (ret)
7201                 return ret;
7202
7203         phydev = mdiobus_get_phy(new_bus, 0);
7204         if (!phydev) {
7205                 mdiobus_unregister(new_bus);
7206                 return -ENODEV;
7207         }
7208
7209         /* PHY will be woken up in rtl_open() */
7210         phy_suspend(phydev);
7211
7212         tp->mii_bus = new_bus;
7213
7214         return 0;
7215 }
7216
7217 static void rtl_hw_init_8168g(struct rtl8169_private *tp)
7218 {
7219         u32 data;
7220
7221         tp->ocp_base = OCP_STD_PHY_BASE;
7222
7223         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN);
7224
7225         if (!rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42))
7226                 return;
7227
7228         if (!rtl_udelay_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42))
7229                 return;
7230
7231         RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
7232         msleep(1);
7233         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
7234
7235         data = r8168_mac_ocp_read(tp, 0xe8de);
7236         data &= ~(1 << 14);
7237         r8168_mac_ocp_write(tp, 0xe8de, data);
7238
7239         if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
7240                 return;
7241
7242         data = r8168_mac_ocp_read(tp, 0xe8de);
7243         data |= (1 << 15);
7244         r8168_mac_ocp_write(tp, 0xe8de, data);
7245
7246         if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
7247                 return;
7248 }
7249
7250 static void rtl_hw_init_8168ep(struct rtl8169_private *tp)
7251 {
7252         rtl8168ep_stop_cmac(tp);
7253         rtl_hw_init_8168g(tp);
7254 }
7255
7256 static void rtl_hw_initialize(struct rtl8169_private *tp)
7257 {
7258         switch (tp->mac_version) {
7259         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_48:
7260                 rtl_hw_init_8168g(tp);
7261                 break;
7262         case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_51:
7263                 rtl_hw_init_8168ep(tp);
7264                 break;
7265         default:
7266                 break;
7267         }
7268 }
7269
7270 /* Versions RTL8102e and from RTL8168c onwards support csum_v2 */
7271 static bool rtl_chip_supports_csum_v2(struct rtl8169_private *tp)
7272 {
7273         switch (tp->mac_version) {
7274         case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_06:
7275         case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
7276                 return false;
7277         default:
7278                 return true;
7279         }
7280 }
7281
7282 static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
7283 {
7284         const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
7285         struct rtl8169_private *tp;
7286         struct net_device *dev;
7287         int chipset, region, i;
7288         int rc;
7289
7290         dev = devm_alloc_etherdev(&pdev->dev, sizeof (*tp));
7291         if (!dev)
7292                 return -ENOMEM;
7293
7294         SET_NETDEV_DEV(dev, &pdev->dev);
7295         dev->netdev_ops = &rtl_netdev_ops;
7296         tp = netdev_priv(dev);
7297         tp->dev = dev;
7298         tp->pci_dev = pdev;
7299         tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
7300         tp->supports_gmii = cfg->has_gmii;
7301
7302         /* enable device (incl. PCI PM wakeup and hotplug setup) */
7303         rc = pcim_enable_device(pdev);
7304         if (rc < 0) {
7305                 dev_err(&pdev->dev, "enable failure\n");
7306                 return rc;
7307         }
7308
7309         if (pcim_set_mwi(pdev) < 0)
7310                 dev_info(&pdev->dev, "Mem-Wr-Inval unavailable\n");
7311
7312         /* use first MMIO region */
7313         region = ffs(pci_select_bars(pdev, IORESOURCE_MEM)) - 1;
7314         if (region < 0) {
7315                 dev_err(&pdev->dev, "no MMIO resource found\n");
7316                 return -ENODEV;
7317         }
7318
7319         /* check for weird/broken PCI region reporting */
7320         if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
7321                 dev_err(&pdev->dev, "Invalid PCI region size(s), aborting\n");
7322                 return -ENODEV;
7323         }
7324
7325         rc = pcim_iomap_regions(pdev, BIT(region), MODULENAME);
7326         if (rc < 0) {
7327                 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
7328                 return rc;
7329         }
7330
7331         tp->mmio_addr = pcim_iomap_table(pdev)[region];
7332
7333         if (!pci_is_pcie(pdev))
7334                 dev_info(&pdev->dev, "not PCI Express\n");
7335
7336         /* Identify chip attached to board */
7337         rtl8169_get_mac_version(tp, cfg->default_ver);
7338
7339         if (rtl_tbi_enabled(tp)) {
7340                 dev_err(&pdev->dev, "TBI fiber mode not supported\n");
7341                 return -ENODEV;
7342         }
7343
7344         tp->cp_cmd = RTL_R16(tp, CPlusCmd);
7345
7346         if ((sizeof(dma_addr_t) > 4) &&
7347             (use_dac == 1 || (use_dac == -1 && pci_is_pcie(pdev) &&
7348                               tp->mac_version >= RTL_GIGA_MAC_VER_18)) &&
7349             !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) &&
7350             !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
7351
7352                 /* CPlusCmd Dual Access Cycle is only needed for non-PCIe */
7353                 if (!pci_is_pcie(pdev))
7354                         tp->cp_cmd |= PCIDAC;
7355                 dev->features |= NETIF_F_HIGHDMA;
7356         } else {
7357                 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
7358                 if (rc < 0) {
7359                         dev_err(&pdev->dev, "DMA configuration failed\n");
7360                         return rc;
7361                 }
7362         }
7363
7364         rtl_init_rxcfg(tp);
7365
7366         rtl_irq_disable(tp);
7367
7368         rtl_hw_initialize(tp);
7369
7370         rtl_hw_reset(tp);
7371
7372         rtl_ack_events(tp, 0xffff);
7373
7374         pci_set_master(pdev);
7375
7376         rtl_init_mdio_ops(tp);
7377         rtl_init_jumbo_ops(tp);
7378
7379         rtl8169_print_mac_version(tp);
7380
7381         chipset = tp->mac_version;
7382
7383         rc = rtl_alloc_irq(tp);
7384         if (rc < 0) {
7385                 dev_err(&pdev->dev, "Can't allocate interrupt\n");
7386                 return rc;
7387         }
7388
7389         tp->saved_wolopts = __rtl8169_get_wol(tp);
7390
7391         mutex_init(&tp->wk.mutex);
7392         u64_stats_init(&tp->rx_stats.syncp);
7393         u64_stats_init(&tp->tx_stats.syncp);
7394
7395         /* Get MAC address */
7396         switch (tp->mac_version) {
7397                 u8 mac_addr[ETH_ALEN] __aligned(4);
7398         case RTL_GIGA_MAC_VER_35 ... RTL_GIGA_MAC_VER_38:
7399         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
7400                 *(u32 *)&mac_addr[0] = rtl_eri_read(tp, 0xe0, ERIAR_EXGMAC);
7401                 *(u16 *)&mac_addr[4] = rtl_eri_read(tp, 0xe4, ERIAR_EXGMAC);
7402
7403                 if (is_valid_ether_addr(mac_addr))
7404                         rtl_rar_set(tp, mac_addr);
7405                 break;
7406         default:
7407                 break;
7408         }
7409         for (i = 0; i < ETH_ALEN; i++)
7410                 dev->dev_addr[i] = RTL_R8(tp, MAC0 + i);
7411
7412         dev->ethtool_ops = &rtl8169_ethtool_ops;
7413         dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
7414
7415         netif_napi_add(dev, &tp->napi, rtl8169_poll, NAPI_POLL_WEIGHT);
7416
7417         /* don't enable SG, IP_CSUM and TSO by default - it might not work
7418          * properly for all devices */
7419         dev->features |= NETIF_F_RXCSUM |
7420                 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
7421
7422         dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
7423                 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_TX |
7424                 NETIF_F_HW_VLAN_CTAG_RX;
7425         dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
7426                 NETIF_F_HIGHDMA;
7427         dev->priv_flags |= IFF_LIVE_ADDR_CHANGE;
7428
7429         tp->cp_cmd |= RxChkSum | RxVlan;
7430
7431         /*
7432          * Pretend we are using VLANs; This bypasses a nasty bug where
7433          * Interrupts stop flowing on high load on 8110SCd controllers.
7434          */
7435         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
7436                 /* Disallow toggling */
7437                 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX;
7438
7439         if (rtl_chip_supports_csum_v2(tp)) {
7440                 tp->tso_csum = rtl8169_tso_csum_v2;
7441                 dev->hw_features |= NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
7442         } else {
7443                 tp->tso_csum = rtl8169_tso_csum_v1;
7444         }
7445
7446         dev->hw_features |= NETIF_F_RXALL;
7447         dev->hw_features |= NETIF_F_RXFCS;
7448
7449         /* MTU range: 60 - hw-specific max */
7450         dev->min_mtu = ETH_ZLEN;
7451         dev->max_mtu = rtl_chip_infos[chipset].jumbo_max;
7452
7453         tp->hw_start = cfg->hw_start;
7454         tp->event_slow = cfg->event_slow;
7455         tp->coalesce_info = cfg->coalesce_info;
7456
7457         tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
7458
7459         tp->counters = dmam_alloc_coherent (&pdev->dev, sizeof(*tp->counters),
7460                                             &tp->counters_phys_addr,
7461                                             GFP_KERNEL);
7462         if (!tp->counters)
7463                 return -ENOMEM;
7464
7465         pci_set_drvdata(pdev, dev);
7466
7467         rc = r8169_mdio_register(tp);
7468         if (rc)
7469                 return rc;
7470
7471         /* chip gets powered up in rtl_open() */
7472         rtl_pll_power_down(tp);
7473
7474         rc = register_netdev(dev);
7475         if (rc)
7476                 goto err_mdio_unregister;
7477
7478         netif_info(tp, probe, dev, "%s, %pM, XID %08x, IRQ %d\n",
7479                    rtl_chip_infos[chipset].name, dev->dev_addr,
7480                    (u32)(RTL_R32(tp, TxConfig) & 0xfcf0f8ff),
7481                    pci_irq_vector(pdev, 0));
7482         if (rtl_chip_infos[chipset].jumbo_max != JUMBO_1K) {
7483                 netif_info(tp, probe, dev, "jumbo features [frames: %d bytes, "
7484                            "tx checksumming: %s]\n",
7485                            rtl_chip_infos[chipset].jumbo_max,
7486                           tp->mac_version <= RTL_GIGA_MAC_VER_06 ? "ok" : "ko");
7487         }
7488
7489         if (r8168_check_dash(tp))
7490                 rtl8168_driver_start(tp);
7491
7492         if (pci_dev_run_wake(pdev))
7493                 pm_runtime_put_sync(&pdev->dev);
7494
7495         return 0;
7496
7497 err_mdio_unregister:
7498         mdiobus_unregister(tp->mii_bus);
7499         return rc;
7500 }
7501
7502 static struct pci_driver rtl8169_pci_driver = {
7503         .name           = MODULENAME,
7504         .id_table       = rtl8169_pci_tbl,
7505         .probe          = rtl_init_one,
7506         .remove         = rtl_remove_one,
7507         .shutdown       = rtl_shutdown,
7508         .driver.pm      = RTL8169_PM_OPS,
7509 };
7510
7511 module_pci_driver(rtl8169_pci_driver);