1 // SPDX-License-Identifier: GPL-2.0-only
3 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
5 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
6 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
7 * Copyright (c) a lot of people too. Please respect their work.
9 * See MAINTAINERS file for support contact information.
12 #include <linux/module.h>
13 #include <linux/moduleparam.h>
14 #include <linux/pci.h>
15 #include <linux/netdevice.h>
16 #include <linux/etherdevice.h>
17 #include <linux/clk.h>
18 #include <linux/delay.h>
19 #include <linux/ethtool.h>
20 #include <linux/phy.h>
21 #include <linux/if_vlan.h>
22 #include <linux/crc32.h>
26 #include <linux/tcp.h>
27 #include <linux/interrupt.h>
28 #include <linux/dma-mapping.h>
29 #include <linux/pm_runtime.h>
30 #include <linux/firmware.h>
31 #include <linux/prefetch.h>
32 #include <linux/pci-aspm.h>
33 #include <linux/ipv6.h>
34 #include <net/ip6_checksum.h>
36 #define MODULENAME "r8169"
38 #define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
39 #define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
40 #define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw"
41 #define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw"
42 #define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw"
43 #define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw"
44 #define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw"
45 #define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw"
46 #define FIRMWARE_8402_1 "rtl_nic/rtl8402-1.fw"
47 #define FIRMWARE_8411_1 "rtl_nic/rtl8411-1.fw"
48 #define FIRMWARE_8411_2 "rtl_nic/rtl8411-2.fw"
49 #define FIRMWARE_8106E_1 "rtl_nic/rtl8106e-1.fw"
50 #define FIRMWARE_8106E_2 "rtl_nic/rtl8106e-2.fw"
51 #define FIRMWARE_8168G_2 "rtl_nic/rtl8168g-2.fw"
52 #define FIRMWARE_8168G_3 "rtl_nic/rtl8168g-3.fw"
53 #define FIRMWARE_8168H_1 "rtl_nic/rtl8168h-1.fw"
54 #define FIRMWARE_8168H_2 "rtl_nic/rtl8168h-2.fw"
55 #define FIRMWARE_8107E_1 "rtl_nic/rtl8107e-1.fw"
56 #define FIRMWARE_8107E_2 "rtl_nic/rtl8107e-2.fw"
58 #define R8169_MSG_DEFAULT \
59 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
61 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
62 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
63 static const int multicast_filter_limit = 32;
65 #define TX_DMA_BURST 7 /* Maximum PCI burst, '7' is unlimited */
66 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
68 #define R8169_REGS_SIZE 256
69 #define R8169_RX_BUF_SIZE (SZ_16K - 1)
70 #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
71 #define NUM_RX_DESC 256U /* Number of Rx descriptor registers */
72 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
73 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
75 /* write/read MMIO register */
76 #define RTL_W8(tp, reg, val8) writeb((val8), tp->mmio_addr + (reg))
77 #define RTL_W16(tp, reg, val16) writew((val16), tp->mmio_addr + (reg))
78 #define RTL_W32(tp, reg, val32) writel((val32), tp->mmio_addr + (reg))
79 #define RTL_R8(tp, reg) readb(tp->mmio_addr + (reg))
80 #define RTL_R16(tp, reg) readw(tp->mmio_addr + (reg))
81 #define RTL_R32(tp, reg) readl(tp->mmio_addr + (reg))
84 RTL_GIGA_MAC_VER_01 = 0,
138 #define JUMBO_1K ETH_DATA_LEN
139 #define JUMBO_4K (4*1024 - ETH_HLEN - 2)
140 #define JUMBO_6K (6*1024 - ETH_HLEN - 2)
141 #define JUMBO_7K (7*1024 - ETH_HLEN - 2)
142 #define JUMBO_9K (9*1024 - ETH_HLEN - 2)
144 static const struct {
147 } rtl_chip_infos[] = {
149 [RTL_GIGA_MAC_VER_01] = {"RTL8169" },
150 [RTL_GIGA_MAC_VER_02] = {"RTL8169s" },
151 [RTL_GIGA_MAC_VER_03] = {"RTL8110s" },
152 [RTL_GIGA_MAC_VER_04] = {"RTL8169sb/8110sb" },
153 [RTL_GIGA_MAC_VER_05] = {"RTL8169sc/8110sc" },
154 [RTL_GIGA_MAC_VER_06] = {"RTL8169sc/8110sc" },
156 [RTL_GIGA_MAC_VER_07] = {"RTL8102e" },
157 [RTL_GIGA_MAC_VER_08] = {"RTL8102e" },
158 [RTL_GIGA_MAC_VER_09] = {"RTL8102e" },
159 [RTL_GIGA_MAC_VER_10] = {"RTL8101e" },
160 [RTL_GIGA_MAC_VER_11] = {"RTL8168b/8111b" },
161 [RTL_GIGA_MAC_VER_12] = {"RTL8168b/8111b" },
162 [RTL_GIGA_MAC_VER_13] = {"RTL8101e" },
163 [RTL_GIGA_MAC_VER_14] = {"RTL8100e" },
164 [RTL_GIGA_MAC_VER_15] = {"RTL8100e" },
165 [RTL_GIGA_MAC_VER_16] = {"RTL8101e" },
166 [RTL_GIGA_MAC_VER_17] = {"RTL8168b/8111b" },
167 [RTL_GIGA_MAC_VER_18] = {"RTL8168cp/8111cp" },
168 [RTL_GIGA_MAC_VER_19] = {"RTL8168c/8111c" },
169 [RTL_GIGA_MAC_VER_20] = {"RTL8168c/8111c" },
170 [RTL_GIGA_MAC_VER_21] = {"RTL8168c/8111c" },
171 [RTL_GIGA_MAC_VER_22] = {"RTL8168c/8111c" },
172 [RTL_GIGA_MAC_VER_23] = {"RTL8168cp/8111cp" },
173 [RTL_GIGA_MAC_VER_24] = {"RTL8168cp/8111cp" },
174 [RTL_GIGA_MAC_VER_25] = {"RTL8168d/8111d", FIRMWARE_8168D_1},
175 [RTL_GIGA_MAC_VER_26] = {"RTL8168d/8111d", FIRMWARE_8168D_2},
176 [RTL_GIGA_MAC_VER_27] = {"RTL8168dp/8111dp" },
177 [RTL_GIGA_MAC_VER_28] = {"RTL8168dp/8111dp" },
178 [RTL_GIGA_MAC_VER_29] = {"RTL8105e", FIRMWARE_8105E_1},
179 [RTL_GIGA_MAC_VER_30] = {"RTL8105e", FIRMWARE_8105E_1},
180 [RTL_GIGA_MAC_VER_31] = {"RTL8168dp/8111dp" },
181 [RTL_GIGA_MAC_VER_32] = {"RTL8168e/8111e", FIRMWARE_8168E_1},
182 [RTL_GIGA_MAC_VER_33] = {"RTL8168e/8111e", FIRMWARE_8168E_2},
183 [RTL_GIGA_MAC_VER_34] = {"RTL8168evl/8111evl", FIRMWARE_8168E_3},
184 [RTL_GIGA_MAC_VER_35] = {"RTL8168f/8111f", FIRMWARE_8168F_1},
185 [RTL_GIGA_MAC_VER_36] = {"RTL8168f/8111f", FIRMWARE_8168F_2},
186 [RTL_GIGA_MAC_VER_37] = {"RTL8402", FIRMWARE_8402_1 },
187 [RTL_GIGA_MAC_VER_38] = {"RTL8411", FIRMWARE_8411_1 },
188 [RTL_GIGA_MAC_VER_39] = {"RTL8106e", FIRMWARE_8106E_1},
189 [RTL_GIGA_MAC_VER_40] = {"RTL8168g/8111g", FIRMWARE_8168G_2},
190 [RTL_GIGA_MAC_VER_41] = {"RTL8168g/8111g" },
191 [RTL_GIGA_MAC_VER_42] = {"RTL8168g/8111g", FIRMWARE_8168G_3},
192 [RTL_GIGA_MAC_VER_43] = {"RTL8106e", FIRMWARE_8106E_2},
193 [RTL_GIGA_MAC_VER_44] = {"RTL8411", FIRMWARE_8411_2 },
194 [RTL_GIGA_MAC_VER_45] = {"RTL8168h/8111h", FIRMWARE_8168H_1},
195 [RTL_GIGA_MAC_VER_46] = {"RTL8168h/8111h", FIRMWARE_8168H_2},
196 [RTL_GIGA_MAC_VER_47] = {"RTL8107e", FIRMWARE_8107E_1},
197 [RTL_GIGA_MAC_VER_48] = {"RTL8107e", FIRMWARE_8107E_2},
198 [RTL_GIGA_MAC_VER_49] = {"RTL8168ep/8111ep" },
199 [RTL_GIGA_MAC_VER_50] = {"RTL8168ep/8111ep" },
200 [RTL_GIGA_MAC_VER_51] = {"RTL8168ep/8111ep" },
209 static const struct pci_device_id rtl8169_pci_tbl[] = {
210 { PCI_VDEVICE(REALTEK, 0x2502), RTL_CFG_1 },
211 { PCI_VDEVICE(REALTEK, 0x2600), RTL_CFG_1 },
212 { PCI_VDEVICE(REALTEK, 0x8129), RTL_CFG_0 },
213 { PCI_VDEVICE(REALTEK, 0x8136), RTL_CFG_2 },
214 { PCI_VDEVICE(REALTEK, 0x8161), RTL_CFG_1 },
215 { PCI_VDEVICE(REALTEK, 0x8167), RTL_CFG_0 },
216 { PCI_VDEVICE(REALTEK, 0x8168), RTL_CFG_1 },
217 { PCI_VDEVICE(NCUBE, 0x8168), RTL_CFG_1 },
218 { PCI_VDEVICE(REALTEK, 0x8169), RTL_CFG_0 },
219 { PCI_VENDOR_ID_DLINK, 0x4300,
220 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0, RTL_CFG_1 },
221 { PCI_VDEVICE(DLINK, 0x4300), RTL_CFG_0 },
222 { PCI_VDEVICE(DLINK, 0x4302), RTL_CFG_0 },
223 { PCI_VDEVICE(AT, 0xc107), RTL_CFG_0 },
224 { PCI_VDEVICE(USR, 0x0116), RTL_CFG_0 },
225 { PCI_VENDOR_ID_LINKSYS, 0x1032,
226 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
228 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
232 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
239 MAC0 = 0, /* Ethernet hardware address. */
241 MAR0 = 8, /* Multicast filter. */
242 CounterAddrLow = 0x10,
243 CounterAddrHigh = 0x14,
244 TxDescStartAddrLow = 0x20,
245 TxDescStartAddrHigh = 0x24,
246 TxHDescStartAddrLow = 0x28,
247 TxHDescStartAddrHigh = 0x2c,
256 #define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */
257 #define TXCFG_EMPTY (1 << 11) /* 8111e-vl */
260 #define RX128_INT_EN (1 << 15) /* 8111c and later */
261 #define RX_MULTI_EN (1 << 14) /* 8111c only */
262 #define RXCFG_FIFO_SHIFT 13
263 /* No threshold before first PCI xfer */
264 #define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT)
265 #define RX_EARLY_OFF (1 << 11)
266 #define RXCFG_DMA_SHIFT 8
267 /* Unlimited maximum PCI burst. */
268 #define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT)
275 #define PME_SIGNAL (1 << 5) /* 8168c and later */
287 #define RTL_COALESCE_MASK 0x0f
288 #define RTL_COALESCE_SHIFT 4
289 #define RTL_COALESCE_T_MAX (RTL_COALESCE_MASK)
290 #define RTL_COALESCE_FRAME_MAX (RTL_COALESCE_MASK << 2)
292 RxDescAddrLow = 0xe4,
293 RxDescAddrHigh = 0xe8,
294 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */
296 #define NoEarlyTx 0x3f /* Max value : no early transmit. */
298 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
300 #define TxPacketMax (8064 >> 7)
301 #define EarlySize 0x27
304 FuncEventMask = 0xf4,
305 FuncPresetState = 0xf8,
310 FuncForceEvent = 0xfc,
313 enum rtl8168_8101_registers {
316 #define CSIAR_FLAG 0x80000000
317 #define CSIAR_WRITE_CMD 0x80000000
318 #define CSIAR_BYTE_ENABLE 0x0000f000
319 #define CSIAR_ADDR_MASK 0x00000fff
322 #define EPHYAR_FLAG 0x80000000
323 #define EPHYAR_WRITE_CMD 0x80000000
324 #define EPHYAR_REG_MASK 0x1f
325 #define EPHYAR_REG_SHIFT 16
326 #define EPHYAR_DATA_MASK 0xffff
328 #define PFM_EN (1 << 6)
329 #define TX_10M_PS_EN (1 << 7)
331 #define FIX_NAK_1 (1 << 4)
332 #define FIX_NAK_2 (1 << 3)
335 #define NOW_IS_OOB (1 << 7)
336 #define TX_EMPTY (1 << 5)
337 #define RX_EMPTY (1 << 4)
338 #define RXTX_EMPTY (TX_EMPTY | RX_EMPTY)
339 #define EN_NDP (1 << 3)
340 #define EN_OOB_RESET (1 << 2)
341 #define LINK_LIST_RDY (1 << 1)
343 #define EFUSEAR_FLAG 0x80000000
344 #define EFUSEAR_WRITE_CMD 0x80000000
345 #define EFUSEAR_READ_CMD 0x00000000
346 #define EFUSEAR_REG_MASK 0x03ff
347 #define EFUSEAR_REG_SHIFT 8
348 #define EFUSEAR_DATA_MASK 0xff
350 #define PFM_D3COLD_EN (1 << 6)
353 enum rtl8168_registers {
358 #define ERIAR_FLAG 0x80000000
359 #define ERIAR_WRITE_CMD 0x80000000
360 #define ERIAR_READ_CMD 0x00000000
361 #define ERIAR_ADDR_BYTE_ALIGN 4
362 #define ERIAR_TYPE_SHIFT 16
363 #define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT)
364 #define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT)
365 #define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT)
366 #define ERIAR_OOB (0x02 << ERIAR_TYPE_SHIFT)
367 #define ERIAR_MASK_SHIFT 12
368 #define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT)
369 #define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT)
370 #define ERIAR_MASK_0100 (0x4 << ERIAR_MASK_SHIFT)
371 #define ERIAR_MASK_0101 (0x5 << ERIAR_MASK_SHIFT)
372 #define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT)
373 EPHY_RXER_NUM = 0x7c,
374 OCPDR = 0xb0, /* OCP GPHY access */
375 #define OCPDR_WRITE_CMD 0x80000000
376 #define OCPDR_READ_CMD 0x00000000
377 #define OCPDR_REG_MASK 0x7f
378 #define OCPDR_GPHY_REG_SHIFT 16
379 #define OCPDR_DATA_MASK 0xffff
381 #define OCPAR_FLAG 0x80000000
382 #define OCPAR_GPHY_WRITE_CMD 0x8000f060
383 #define OCPAR_GPHY_READ_CMD 0x0000f060
385 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */
386 MISC = 0xf0, /* 8168e only. */
387 #define TXPLA_RST (1 << 29)
388 #define DISABLE_LAN_EN (1 << 23) /* Enable GPIO pin */
389 #define PWM_EN (1 << 22)
390 #define RXDV_GATED_EN (1 << 19)
391 #define EARLY_TALLY_EN (1 << 16)
394 enum rtl_register_content {
395 /* InterruptStatusBits */
399 TxDescUnavail = 0x0080,
423 /* TXPoll register p.5 */
424 HPQ = 0x80, /* Poll cmd on the high prio queue */
425 NPQ = 0x40, /* Poll cmd on the low prio queue */
426 FSWInt = 0x01, /* Forced software interrupt */
430 Cfg9346_Unlock = 0xc0,
435 AcceptBroadcast = 0x08,
436 AcceptMulticast = 0x04,
438 AcceptAllPhys = 0x01,
439 #define RX_CONFIG_ACCEPT_MASK 0x3f
442 TxInterFrameGapShift = 24,
443 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
445 /* Config1 register p.24 */
448 Speed_down = (1 << 4),
452 PMEnable = (1 << 0), /* Power Management Enable */
454 /* Config2 register p. 25 */
455 ClkReqEn = (1 << 7), /* Clock Request Enable */
456 MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */
457 PCI_Clock_66MHz = 0x01,
458 PCI_Clock_33MHz = 0x00,
460 /* Config3 register p.25 */
461 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
462 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
463 Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */
464 Rdy_to_L23 = (1 << 1), /* L23 Enable */
465 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
467 /* Config4 register */
468 Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */
470 /* Config5 register p.27 */
471 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
472 MWF = (1 << 5), /* Accept Multicast wakeup frame */
473 UWF = (1 << 4), /* Accept Unicast wakeup frame */
475 LanWake = (1 << 1), /* LanWake enable/disable */
476 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
477 ASPM_en = (1 << 0), /* ASPM enable */
480 EnableBist = (1 << 15), // 8168 8101
481 Mac_dbgo_oe = (1 << 14), // 8168 8101
482 Normal_mode = (1 << 13), // unused
483 Force_half_dup = (1 << 12), // 8168 8101
484 Force_rxflow_en = (1 << 11), // 8168 8101
485 Force_txflow_en = (1 << 10), // 8168 8101
486 Cxpl_dbg_sel = (1 << 9), // 8168 8101
487 ASF = (1 << 8), // 8168 8101
488 PktCntrDisable = (1 << 7), // 8168 8101
489 Mac_dbgo_sel = 0x001c, // 8168
494 #define INTT_MASK GENMASK(1, 0)
496 /* rtl8169_PHYstatus */
507 TBILinkOK = 0x02000000,
509 /* ResetCounterCommand */
512 /* DumpCounterCommand */
515 /* magic enable v2 */
516 MagicPacket_v2 = (1 << 16), /* Wake up when receives a Magic Packet */
520 /* First doubleword. */
521 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
522 RingEnd = (1 << 30), /* End of descriptor ring */
523 FirstFrag = (1 << 29), /* First segment of a packet */
524 LastFrag = (1 << 28), /* Final segment of a packet */
528 enum rtl_tx_desc_bit {
529 /* First doubleword. */
530 TD_LSO = (1 << 27), /* Large Send Offload */
531 #define TD_MSS_MAX 0x07ffu /* MSS value */
533 /* Second doubleword. */
534 TxVlanTag = (1 << 17), /* Add VLAN tag */
537 /* 8169, 8168b and 810x except 8102e. */
538 enum rtl_tx_desc_bit_0 {
539 /* First doubleword. */
540 #define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */
541 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */
542 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */
543 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */
546 /* 8102e, 8168c and beyond. */
547 enum rtl_tx_desc_bit_1 {
548 /* First doubleword. */
549 TD1_GTSENV4 = (1 << 26), /* Giant Send for IPv4 */
550 TD1_GTSENV6 = (1 << 25), /* Giant Send for IPv6 */
551 #define GTTCPHO_SHIFT 18
552 #define GTTCPHO_MAX 0x7fU
554 /* Second doubleword. */
555 #define TCPHO_SHIFT 18
556 #define TCPHO_MAX 0x3ffU
557 #define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */
558 TD1_IPv6_CS = (1 << 28), /* Calculate IPv6 checksum */
559 TD1_IPv4_CS = (1 << 29), /* Calculate IPv4 checksum */
560 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */
561 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */
564 enum rtl_rx_desc_bit {
566 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
567 PID0 = (1 << 17), /* Protocol ID bit 0/2 */
569 #define RxProtoUDP (PID1)
570 #define RxProtoTCP (PID0)
571 #define RxProtoIP (PID1 | PID0)
572 #define RxProtoMask RxProtoIP
574 IPFail = (1 << 16), /* IP checksum failed */
575 UDPFail = (1 << 15), /* UDP/IP checksum failed */
576 TCPFail = (1 << 14), /* TCP/IP checksum failed */
577 RxVlanTag = (1 << 16), /* VLAN tag available */
580 #define RsvdMask 0x3fffc000
581 #define CPCMD_QUIRK_MASK (Normal_mode | RxVlan | RxChkSum | INTT_MASK)
600 struct rtl8169_counters {
607 __le32 tx_one_collision;
608 __le32 tx_multi_collision;
616 struct rtl8169_tc_offsets {
619 __le32 tx_multi_collision;
624 RTL_FLAG_TASK_ENABLED = 0,
625 RTL_FLAG_TASK_RESET_PENDING,
629 struct rtl8169_stats {
632 struct u64_stats_sync syncp;
635 struct rtl8169_private {
636 void __iomem *mmio_addr; /* memory map physical address */
637 struct pci_dev *pci_dev;
638 struct net_device *dev;
639 struct phy_device *phydev;
640 struct napi_struct napi;
642 enum mac_version mac_version;
643 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
644 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
646 struct rtl8169_stats rx_stats;
647 struct rtl8169_stats tx_stats;
648 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
649 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
650 dma_addr_t TxPhyAddr;
651 dma_addr_t RxPhyAddr;
652 void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
653 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
657 const struct rtl_coalesce_info *coalesce_info;
661 void (*write)(struct rtl8169_private *, int, int);
662 int (*read)(struct rtl8169_private *, int);
666 void (*enable)(struct rtl8169_private *);
667 void (*disable)(struct rtl8169_private *);
670 void (*hw_start)(struct rtl8169_private *tp);
671 bool (*tso_csum)(struct rtl8169_private *, struct sk_buff *, u32 *);
674 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
676 struct work_struct work;
679 unsigned irq_enabled:1;
680 unsigned supports_gmii:1;
681 dma_addr_t counters_phys_addr;
682 struct rtl8169_counters *counters;
683 struct rtl8169_tc_offsets tc_offset;
688 const struct firmware *fw;
690 #define RTL_VER_SIZE 32
692 char version[RTL_VER_SIZE];
694 struct rtl_fw_phy_action {
703 typedef void (*rtl_generic_fct)(struct rtl8169_private *tp);
705 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
706 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
707 module_param_named(debug, debug.msg_enable, int, 0);
708 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
709 MODULE_SOFTDEP("pre: realtek");
710 MODULE_LICENSE("GPL");
711 MODULE_FIRMWARE(FIRMWARE_8168D_1);
712 MODULE_FIRMWARE(FIRMWARE_8168D_2);
713 MODULE_FIRMWARE(FIRMWARE_8168E_1);
714 MODULE_FIRMWARE(FIRMWARE_8168E_2);
715 MODULE_FIRMWARE(FIRMWARE_8168E_3);
716 MODULE_FIRMWARE(FIRMWARE_8105E_1);
717 MODULE_FIRMWARE(FIRMWARE_8168F_1);
718 MODULE_FIRMWARE(FIRMWARE_8168F_2);
719 MODULE_FIRMWARE(FIRMWARE_8402_1);
720 MODULE_FIRMWARE(FIRMWARE_8411_1);
721 MODULE_FIRMWARE(FIRMWARE_8411_2);
722 MODULE_FIRMWARE(FIRMWARE_8106E_1);
723 MODULE_FIRMWARE(FIRMWARE_8106E_2);
724 MODULE_FIRMWARE(FIRMWARE_8168G_2);
725 MODULE_FIRMWARE(FIRMWARE_8168G_3);
726 MODULE_FIRMWARE(FIRMWARE_8168H_1);
727 MODULE_FIRMWARE(FIRMWARE_8168H_2);
728 MODULE_FIRMWARE(FIRMWARE_8107E_1);
729 MODULE_FIRMWARE(FIRMWARE_8107E_2);
731 static inline struct device *tp_to_dev(struct rtl8169_private *tp)
733 return &tp->pci_dev->dev;
736 static void rtl_lock_work(struct rtl8169_private *tp)
738 mutex_lock(&tp->wk.mutex);
741 static void rtl_unlock_work(struct rtl8169_private *tp)
743 mutex_unlock(&tp->wk.mutex);
746 static void rtl_lock_config_regs(struct rtl8169_private *tp)
748 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
751 static void rtl_unlock_config_regs(struct rtl8169_private *tp)
753 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
756 static void rtl_tx_performance_tweak(struct rtl8169_private *tp, u16 force)
758 pcie_capability_clear_and_set_word(tp->pci_dev, PCI_EXP_DEVCTL,
759 PCI_EXP_DEVCTL_READRQ, force);
763 bool (*check)(struct rtl8169_private *);
767 static void rtl_udelay(unsigned int d)
772 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,
773 void (*delay)(unsigned int), unsigned int d, int n,
778 for (i = 0; i < n; i++) {
779 if (c->check(tp) == high)
783 netif_err(tp, drv, tp->dev, "%s == %d (loop: %d, delay: %d).\n",
784 c->msg, !high, n, d);
788 static bool rtl_udelay_loop_wait_high(struct rtl8169_private *tp,
789 const struct rtl_cond *c,
790 unsigned int d, int n)
792 return rtl_loop_wait(tp, c, rtl_udelay, d, n, true);
795 static bool rtl_udelay_loop_wait_low(struct rtl8169_private *tp,
796 const struct rtl_cond *c,
797 unsigned int d, int n)
799 return rtl_loop_wait(tp, c, rtl_udelay, d, n, false);
802 static bool rtl_msleep_loop_wait_high(struct rtl8169_private *tp,
803 const struct rtl_cond *c,
804 unsigned int d, int n)
806 return rtl_loop_wait(tp, c, msleep, d, n, true);
809 static bool rtl_msleep_loop_wait_low(struct rtl8169_private *tp,
810 const struct rtl_cond *c,
811 unsigned int d, int n)
813 return rtl_loop_wait(tp, c, msleep, d, n, false);
816 #define DECLARE_RTL_COND(name) \
817 static bool name ## _check(struct rtl8169_private *); \
819 static const struct rtl_cond name = { \
820 .check = name ## _check, \
824 static bool name ## _check(struct rtl8169_private *tp)
826 static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg)
828 if (reg & 0xffff0001) {
829 netif_err(tp, drv, tp->dev, "Invalid ocp reg %x!\n", reg);
835 DECLARE_RTL_COND(rtl_ocp_gphy_cond)
837 return RTL_R32(tp, GPHY_OCP) & OCPAR_FLAG;
840 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
842 if (rtl_ocp_reg_failure(tp, reg))
845 RTL_W32(tp, GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);
847 rtl_udelay_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);
850 static u16 r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
852 if (rtl_ocp_reg_failure(tp, reg))
855 RTL_W32(tp, GPHY_OCP, reg << 15);
857 return rtl_udelay_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?
858 (RTL_R32(tp, GPHY_OCP) & 0xffff) : ~0;
861 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
863 if (rtl_ocp_reg_failure(tp, reg))
866 RTL_W32(tp, OCPDR, OCPAR_FLAG | (reg << 15) | data);
869 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
871 if (rtl_ocp_reg_failure(tp, reg))
874 RTL_W32(tp, OCPDR, reg << 15);
876 return RTL_R32(tp, OCPDR);
879 #define OCP_STD_PHY_BASE 0xa400
881 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)
884 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;
888 if (tp->ocp_base != OCP_STD_PHY_BASE)
891 r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);
894 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)
896 if (tp->ocp_base != OCP_STD_PHY_BASE)
899 return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);
902 static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value)
905 tp->ocp_base = value << 4;
909 r8168_mac_ocp_write(tp, tp->ocp_base + reg, value);
912 static int mac_mcu_read(struct rtl8169_private *tp, int reg)
914 return r8168_mac_ocp_read(tp, tp->ocp_base + reg);
917 DECLARE_RTL_COND(rtl_phyar_cond)
919 return RTL_R32(tp, PHYAR) & 0x80000000;
922 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)
924 RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
926 rtl_udelay_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);
928 * According to hardware specs a 20us delay is required after write
929 * complete indication, but before sending next command.
934 static int r8169_mdio_read(struct rtl8169_private *tp, int reg)
938 RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16);
940 value = rtl_udelay_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?
941 RTL_R32(tp, PHYAR) & 0xffff : ~0;
944 * According to hardware specs a 20us delay is required after read
945 * complete indication, but before sending next command.
952 DECLARE_RTL_COND(rtl_ocpar_cond)
954 return RTL_R32(tp, OCPAR) & OCPAR_FLAG;
957 static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data)
959 RTL_W32(tp, OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
960 RTL_W32(tp, OCPAR, OCPAR_GPHY_WRITE_CMD);
961 RTL_W32(tp, EPHY_RXER_NUM, 0);
963 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100);
966 static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value)
968 r8168dp_1_mdio_access(tp, reg,
969 OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK));
972 static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg)
974 r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD);
977 RTL_W32(tp, OCPAR, OCPAR_GPHY_READ_CMD);
978 RTL_W32(tp, EPHY_RXER_NUM, 0);
980 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ?
981 RTL_R32(tp, OCPDR) & OCPDR_DATA_MASK : ~0;
984 #define R8168DP_1_MDIO_ACCESS_BIT 0x00020000
986 static void r8168dp_2_mdio_start(struct rtl8169_private *tp)
988 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
991 static void r8168dp_2_mdio_stop(struct rtl8169_private *tp)
993 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
996 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)
998 r8168dp_2_mdio_start(tp);
1000 r8169_mdio_write(tp, reg, value);
1002 r8168dp_2_mdio_stop(tp);
1005 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)
1009 r8168dp_2_mdio_start(tp);
1011 value = r8169_mdio_read(tp, reg);
1013 r8168dp_2_mdio_stop(tp);
1018 static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
1020 tp->mdio_ops.write(tp, location, val);
1023 static int rtl_readphy(struct rtl8169_private *tp, int location)
1025 return tp->mdio_ops.read(tp, location);
1028 static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
1030 rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
1033 static void rtl_w0w1_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
1037 val = rtl_readphy(tp, reg_addr);
1038 rtl_writephy(tp, reg_addr, (val & ~m) | p);
1041 DECLARE_RTL_COND(rtl_ephyar_cond)
1043 return RTL_R32(tp, EPHYAR) & EPHYAR_FLAG;
1046 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)
1048 RTL_W32(tp, EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1049 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1051 rtl_udelay_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);
1056 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)
1058 RTL_W32(tp, EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1060 return rtl_udelay_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?
1061 RTL_R32(tp, EPHYAR) & EPHYAR_DATA_MASK : ~0;
1064 DECLARE_RTL_COND(rtl_eriar_cond)
1066 return RTL_R32(tp, ERIAR) & ERIAR_FLAG;
1069 static void _rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1072 BUG_ON((addr & 3) || (mask == 0));
1073 RTL_W32(tp, ERIDR, val);
1074 RTL_W32(tp, ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
1076 rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);
1079 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1082 _rtl_eri_write(tp, addr, mask, val, ERIAR_EXGMAC);
1085 static u32 _rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
1087 RTL_W32(tp, ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
1089 return rtl_udelay_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?
1090 RTL_R32(tp, ERIDR) : ~0;
1093 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr)
1095 return _rtl_eri_read(tp, addr, ERIAR_EXGMAC);
1098 static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 mask, u32 p,
1103 val = rtl_eri_read(tp, addr);
1104 rtl_eri_write(tp, addr, mask, (val & ~m) | p);
1107 static void rtl_eri_set_bits(struct rtl8169_private *tp, int addr, u32 mask,
1110 rtl_w0w1_eri(tp, addr, mask, p, 0);
1113 static void rtl_eri_clear_bits(struct rtl8169_private *tp, int addr, u32 mask,
1116 rtl_w0w1_eri(tp, addr, mask, 0, m);
1119 static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1121 RTL_W32(tp, OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1122 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?
1123 RTL_R32(tp, OCPDR) : ~0;
1126 static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1128 return _rtl_eri_read(tp, reg, ERIAR_OOB);
1131 static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1134 RTL_W32(tp, OCPDR, data);
1135 RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1136 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);
1139 static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1142 _rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT,
1146 static void r8168dp_oob_notify(struct rtl8169_private *tp, u8 cmd)
1148 rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd);
1150 r8168dp_ocp_write(tp, 0x1, 0x30, 0x00000001);
1153 #define OOB_CMD_RESET 0x00
1154 #define OOB_CMD_DRIVER_START 0x05
1155 #define OOB_CMD_DRIVER_STOP 0x06
1157 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
1159 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
1162 DECLARE_RTL_COND(rtl_dp_ocp_read_cond)
1166 reg = rtl8168_get_ocp_reg(tp);
1168 return r8168dp_ocp_read(tp, 0x0f, reg) & 0x00000800;
1171 DECLARE_RTL_COND(rtl_ep_ocp_read_cond)
1173 return r8168ep_ocp_read(tp, 0x0f, 0x124) & 0x00000001;
1176 DECLARE_RTL_COND(rtl_ocp_tx_cond)
1178 return RTL_R8(tp, IBISR0) & 0x20;
1181 static void rtl8168ep_stop_cmac(struct rtl8169_private *tp)
1183 RTL_W8(tp, IBCR2, RTL_R8(tp, IBCR2) & ~0x01);
1184 rtl_msleep_loop_wait_high(tp, &rtl_ocp_tx_cond, 50, 2000);
1185 RTL_W8(tp, IBISR0, RTL_R8(tp, IBISR0) | 0x20);
1186 RTL_W8(tp, IBCR0, RTL_R8(tp, IBCR0) & ~0x01);
1189 static void rtl8168dp_driver_start(struct rtl8169_private *tp)
1191 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_START);
1192 rtl_msleep_loop_wait_high(tp, &rtl_dp_ocp_read_cond, 10, 10);
1195 static void rtl8168ep_driver_start(struct rtl8169_private *tp)
1197 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START);
1198 r8168ep_ocp_write(tp, 0x01, 0x30,
1199 r8168ep_ocp_read(tp, 0x01, 0x30) | 0x01);
1200 rtl_msleep_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10, 10);
1203 static void rtl8168_driver_start(struct rtl8169_private *tp)
1205 switch (tp->mac_version) {
1206 case RTL_GIGA_MAC_VER_27:
1207 case RTL_GIGA_MAC_VER_28:
1208 case RTL_GIGA_MAC_VER_31:
1209 rtl8168dp_driver_start(tp);
1211 case RTL_GIGA_MAC_VER_49:
1212 case RTL_GIGA_MAC_VER_50:
1213 case RTL_GIGA_MAC_VER_51:
1214 rtl8168ep_driver_start(tp);
1222 static void rtl8168dp_driver_stop(struct rtl8169_private *tp)
1224 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_STOP);
1225 rtl_msleep_loop_wait_low(tp, &rtl_dp_ocp_read_cond, 10, 10);
1228 static void rtl8168ep_driver_stop(struct rtl8169_private *tp)
1230 rtl8168ep_stop_cmac(tp);
1231 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP);
1232 r8168ep_ocp_write(tp, 0x01, 0x30,
1233 r8168ep_ocp_read(tp, 0x01, 0x30) | 0x01);
1234 rtl_msleep_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10, 10);
1237 static void rtl8168_driver_stop(struct rtl8169_private *tp)
1239 switch (tp->mac_version) {
1240 case RTL_GIGA_MAC_VER_27:
1241 case RTL_GIGA_MAC_VER_28:
1242 case RTL_GIGA_MAC_VER_31:
1243 rtl8168dp_driver_stop(tp);
1245 case RTL_GIGA_MAC_VER_49:
1246 case RTL_GIGA_MAC_VER_50:
1247 case RTL_GIGA_MAC_VER_51:
1248 rtl8168ep_driver_stop(tp);
1256 static bool r8168dp_check_dash(struct rtl8169_private *tp)
1258 u16 reg = rtl8168_get_ocp_reg(tp);
1260 return !!(r8168dp_ocp_read(tp, 0x0f, reg) & 0x00008000);
1263 static bool r8168ep_check_dash(struct rtl8169_private *tp)
1265 return !!(r8168ep_ocp_read(tp, 0x0f, 0x128) & 0x00000001);
1268 static bool r8168_check_dash(struct rtl8169_private *tp)
1270 switch (tp->mac_version) {
1271 case RTL_GIGA_MAC_VER_27:
1272 case RTL_GIGA_MAC_VER_28:
1273 case RTL_GIGA_MAC_VER_31:
1274 return r8168dp_check_dash(tp);
1275 case RTL_GIGA_MAC_VER_49:
1276 case RTL_GIGA_MAC_VER_50:
1277 case RTL_GIGA_MAC_VER_51:
1278 return r8168ep_check_dash(tp);
1284 static void rtl_reset_packet_filter(struct rtl8169_private *tp)
1286 rtl_eri_clear_bits(tp, 0xdc, ERIAR_MASK_0001, BIT(0));
1287 rtl_eri_set_bits(tp, 0xdc, ERIAR_MASK_0001, BIT(0));
1290 DECLARE_RTL_COND(rtl_efusear_cond)
1292 return RTL_R32(tp, EFUSEAR) & EFUSEAR_FLAG;
1295 static u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)
1297 RTL_W32(tp, EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1299 return rtl_udelay_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?
1300 RTL_R32(tp, EFUSEAR) & EFUSEAR_DATA_MASK : ~0;
1303 static void rtl_ack_events(struct rtl8169_private *tp, u16 bits)
1305 RTL_W16(tp, IntrStatus, bits);
1308 static void rtl_irq_disable(struct rtl8169_private *tp)
1310 RTL_W16(tp, IntrMask, 0);
1311 tp->irq_enabled = 0;
1314 #define RTL_EVENT_NAPI_RX (RxOK | RxErr)
1315 #define RTL_EVENT_NAPI_TX (TxOK | TxErr)
1316 #define RTL_EVENT_NAPI (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX)
1318 static void rtl_irq_enable(struct rtl8169_private *tp)
1320 tp->irq_enabled = 1;
1321 RTL_W16(tp, IntrMask, tp->irq_mask);
1324 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1326 rtl_irq_disable(tp);
1327 rtl_ack_events(tp, 0xffff);
1329 RTL_R8(tp, ChipCmd);
1332 static void rtl_link_chg_patch(struct rtl8169_private *tp)
1334 struct net_device *dev = tp->dev;
1335 struct phy_device *phydev = tp->phydev;
1337 if (!netif_running(dev))
1340 if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
1341 tp->mac_version == RTL_GIGA_MAC_VER_38) {
1342 if (phydev->speed == SPEED_1000) {
1343 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011);
1344 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
1345 } else if (phydev->speed == SPEED_100) {
1346 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1347 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
1349 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1350 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f);
1352 rtl_reset_packet_filter(tp);
1353 } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1354 tp->mac_version == RTL_GIGA_MAC_VER_36) {
1355 if (phydev->speed == SPEED_1000) {
1356 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011);
1357 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
1359 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1360 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f);
1362 } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
1363 if (phydev->speed == SPEED_10) {
1364 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02);
1365 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060a);
1367 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000);
1372 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1374 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1376 struct rtl8169_private *tp = netdev_priv(dev);
1379 wol->supported = WAKE_ANY;
1380 wol->wolopts = tp->saved_wolopts;
1381 rtl_unlock_work(tp);
1384 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1386 unsigned int i, tmp;
1387 static const struct {
1392 { WAKE_PHY, Config3, LinkUp },
1393 { WAKE_UCAST, Config5, UWF },
1394 { WAKE_BCAST, Config5, BWF },
1395 { WAKE_MCAST, Config5, MWF },
1396 { WAKE_ANY, Config5, LanWake },
1397 { WAKE_MAGIC, Config3, MagicPacket }
1401 rtl_unlock_config_regs(tp);
1403 switch (tp->mac_version) {
1404 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
1405 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
1406 tmp = ARRAY_SIZE(cfg) - 1;
1407 if (wolopts & WAKE_MAGIC)
1408 rtl_eri_set_bits(tp, 0x0dc, ERIAR_MASK_0100,
1411 rtl_eri_clear_bits(tp, 0x0dc, ERIAR_MASK_0100,
1415 tmp = ARRAY_SIZE(cfg);
1419 for (i = 0; i < tmp; i++) {
1420 options = RTL_R8(tp, cfg[i].reg) & ~cfg[i].mask;
1421 if (wolopts & cfg[i].opt)
1422 options |= cfg[i].mask;
1423 RTL_W8(tp, cfg[i].reg, options);
1426 switch (tp->mac_version) {
1427 case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_17:
1428 options = RTL_R8(tp, Config1) & ~PMEnable;
1430 options |= PMEnable;
1431 RTL_W8(tp, Config1, options);
1434 options = RTL_R8(tp, Config2) & ~PME_SIGNAL;
1436 options |= PME_SIGNAL;
1437 RTL_W8(tp, Config2, options);
1441 rtl_lock_config_regs(tp);
1443 device_set_wakeup_enable(tp_to_dev(tp), wolopts);
1446 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1448 struct rtl8169_private *tp = netdev_priv(dev);
1449 struct device *d = tp_to_dev(tp);
1451 if (wol->wolopts & ~WAKE_ANY)
1454 pm_runtime_get_noresume(d);
1458 tp->saved_wolopts = wol->wolopts;
1460 if (pm_runtime_active(d))
1461 __rtl8169_set_wol(tp, tp->saved_wolopts);
1463 rtl_unlock_work(tp);
1465 pm_runtime_put_noidle(d);
1470 static void rtl8169_get_drvinfo(struct net_device *dev,
1471 struct ethtool_drvinfo *info)
1473 struct rtl8169_private *tp = netdev_priv(dev);
1474 struct rtl_fw *rtl_fw = tp->rtl_fw;
1476 strlcpy(info->driver, MODULENAME, sizeof(info->driver));
1477 strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1478 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
1480 strlcpy(info->fw_version, rtl_fw->version,
1481 sizeof(info->fw_version));
1484 static int rtl8169_get_regs_len(struct net_device *dev)
1486 return R8169_REGS_SIZE;
1489 static netdev_features_t rtl8169_fix_features(struct net_device *dev,
1490 netdev_features_t features)
1492 struct rtl8169_private *tp = netdev_priv(dev);
1494 if (dev->mtu > TD_MSS_MAX)
1495 features &= ~NETIF_F_ALL_TSO;
1497 if (dev->mtu > JUMBO_1K &&
1498 tp->mac_version > RTL_GIGA_MAC_VER_06)
1499 features &= ~NETIF_F_IP_CSUM;
1504 static int rtl8169_set_features(struct net_device *dev,
1505 netdev_features_t features)
1507 struct rtl8169_private *tp = netdev_priv(dev);
1512 rx_config = RTL_R32(tp, RxConfig);
1513 if (features & NETIF_F_RXALL)
1514 rx_config |= (AcceptErr | AcceptRunt);
1516 rx_config &= ~(AcceptErr | AcceptRunt);
1518 RTL_W32(tp, RxConfig, rx_config);
1520 if (features & NETIF_F_RXCSUM)
1521 tp->cp_cmd |= RxChkSum;
1523 tp->cp_cmd &= ~RxChkSum;
1525 if (features & NETIF_F_HW_VLAN_CTAG_RX)
1526 tp->cp_cmd |= RxVlan;
1528 tp->cp_cmd &= ~RxVlan;
1530 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1531 RTL_R16(tp, CPlusCmd);
1533 rtl_unlock_work(tp);
1538 static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb)
1540 return (skb_vlan_tag_present(skb)) ?
1541 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00;
1544 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1546 u32 opts2 = le32_to_cpu(desc->opts2);
1548 if (opts2 & RxVlanTag)
1549 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff));
1552 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1555 struct rtl8169_private *tp = netdev_priv(dev);
1556 u32 __iomem *data = tp->mmio_addr;
1561 for (i = 0; i < R8169_REGS_SIZE; i += 4)
1562 memcpy_fromio(dw++, data++, 4);
1563 rtl_unlock_work(tp);
1566 static u32 rtl8169_get_msglevel(struct net_device *dev)
1568 struct rtl8169_private *tp = netdev_priv(dev);
1570 return tp->msg_enable;
1573 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1575 struct rtl8169_private *tp = netdev_priv(dev);
1577 tp->msg_enable = value;
1580 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1587 "tx_single_collisions",
1588 "tx_multi_collisions",
1596 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1600 return ARRAY_SIZE(rtl8169_gstrings);
1606 DECLARE_RTL_COND(rtl_counters_cond)
1608 return RTL_R32(tp, CounterAddrLow) & (CounterReset | CounterDump);
1611 static bool rtl8169_do_counters(struct rtl8169_private *tp, u32 counter_cmd)
1613 dma_addr_t paddr = tp->counters_phys_addr;
1616 RTL_W32(tp, CounterAddrHigh, (u64)paddr >> 32);
1617 RTL_R32(tp, CounterAddrHigh);
1618 cmd = (u64)paddr & DMA_BIT_MASK(32);
1619 RTL_W32(tp, CounterAddrLow, cmd);
1620 RTL_W32(tp, CounterAddrLow, cmd | counter_cmd);
1622 return rtl_udelay_loop_wait_low(tp, &rtl_counters_cond, 10, 1000);
1625 static bool rtl8169_reset_counters(struct rtl8169_private *tp)
1628 * Versions prior to RTL_GIGA_MAC_VER_19 don't support resetting the
1631 if (tp->mac_version < RTL_GIGA_MAC_VER_19)
1634 return rtl8169_do_counters(tp, CounterReset);
1637 static bool rtl8169_update_counters(struct rtl8169_private *tp)
1639 u8 val = RTL_R8(tp, ChipCmd);
1642 * Some chips are unable to dump tally counters when the receiver
1643 * is disabled. If 0xff chip may be in a PCI power-save state.
1645 if (!(val & CmdRxEnb) || val == 0xff)
1648 return rtl8169_do_counters(tp, CounterDump);
1651 static bool rtl8169_init_counter_offsets(struct rtl8169_private *tp)
1653 struct rtl8169_counters *counters = tp->counters;
1657 * rtl8169_init_counter_offsets is called from rtl_open. On chip
1658 * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only
1659 * reset by a power cycle, while the counter values collected by the
1660 * driver are reset at every driver unload/load cycle.
1662 * To make sure the HW values returned by @get_stats64 match the SW
1663 * values, we collect the initial values at first open(*) and use them
1664 * as offsets to normalize the values returned by @get_stats64.
1666 * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one
1667 * for the reason stated in rtl8169_update_counters; CmdRxEnb is only
1668 * set at open time by rtl_hw_start.
1671 if (tp->tc_offset.inited)
1674 /* If both, reset and update fail, propagate to caller. */
1675 if (rtl8169_reset_counters(tp))
1678 if (rtl8169_update_counters(tp))
1681 tp->tc_offset.tx_errors = counters->tx_errors;
1682 tp->tc_offset.tx_multi_collision = counters->tx_multi_collision;
1683 tp->tc_offset.tx_aborted = counters->tx_aborted;
1684 tp->tc_offset.inited = true;
1689 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1690 struct ethtool_stats *stats, u64 *data)
1692 struct rtl8169_private *tp = netdev_priv(dev);
1693 struct device *d = tp_to_dev(tp);
1694 struct rtl8169_counters *counters = tp->counters;
1698 pm_runtime_get_noresume(d);
1700 if (pm_runtime_active(d))
1701 rtl8169_update_counters(tp);
1703 pm_runtime_put_noidle(d);
1705 data[0] = le64_to_cpu(counters->tx_packets);
1706 data[1] = le64_to_cpu(counters->rx_packets);
1707 data[2] = le64_to_cpu(counters->tx_errors);
1708 data[3] = le32_to_cpu(counters->rx_errors);
1709 data[4] = le16_to_cpu(counters->rx_missed);
1710 data[5] = le16_to_cpu(counters->align_errors);
1711 data[6] = le32_to_cpu(counters->tx_one_collision);
1712 data[7] = le32_to_cpu(counters->tx_multi_collision);
1713 data[8] = le64_to_cpu(counters->rx_unicast);
1714 data[9] = le64_to_cpu(counters->rx_broadcast);
1715 data[10] = le32_to_cpu(counters->rx_multicast);
1716 data[11] = le16_to_cpu(counters->tx_aborted);
1717 data[12] = le16_to_cpu(counters->tx_underun);
1720 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1724 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1730 * Interrupt coalescing
1732 * > 1 - the availability of the IntrMitigate (0xe2) register through the
1733 * > 8169, 8168 and 810x line of chipsets
1735 * 8169, 8168, and 8136(810x) serial chipsets support it.
1737 * > 2 - the Tx timer unit at gigabit speed
1739 * The unit of the timer depends on both the speed and the setting of CPlusCmd
1740 * (0xe0) bit 1 and bit 0.
1743 * bit[1:0] \ speed 1000M 100M 10M
1744 * 0 0 320ns 2.56us 40.96us
1745 * 0 1 2.56us 20.48us 327.7us
1746 * 1 0 5.12us 40.96us 655.4us
1747 * 1 1 10.24us 81.92us 1.31ms
1750 * bit[1:0] \ speed 1000M 100M 10M
1751 * 0 0 5us 2.56us 40.96us
1752 * 0 1 40us 20.48us 327.7us
1753 * 1 0 80us 40.96us 655.4us
1754 * 1 1 160us 81.92us 1.31ms
1757 /* rx/tx scale factors for one particular CPlusCmd[0:1] value */
1758 struct rtl_coalesce_scale {
1763 /* rx/tx scale factors for all CPlusCmd[0:1] cases */
1764 struct rtl_coalesce_info {
1766 struct rtl_coalesce_scale scalev[4]; /* each CPlusCmd[0:1] case */
1769 /* produce (r,t) pairs with each being in series of *1, *8, *8*2, *8*2*2 */
1770 #define rxtx_x1822(r, t) { \
1773 {{(r)*8*2, (t)*8*2}}, \
1774 {{(r)*8*2*2, (t)*8*2*2}}, \
1776 static const struct rtl_coalesce_info rtl_coalesce_info_8169[] = {
1777 /* speed delays: rx00 tx00 */
1778 { SPEED_10, rxtx_x1822(40960, 40960) },
1779 { SPEED_100, rxtx_x1822( 2560, 2560) },
1780 { SPEED_1000, rxtx_x1822( 320, 320) },
1784 static const struct rtl_coalesce_info rtl_coalesce_info_8168_8136[] = {
1785 /* speed delays: rx00 tx00 */
1786 { SPEED_10, rxtx_x1822(40960, 40960) },
1787 { SPEED_100, rxtx_x1822( 2560, 2560) },
1788 { SPEED_1000, rxtx_x1822( 5000, 5000) },
1793 /* get rx/tx scale vector corresponding to current speed */
1794 static const struct rtl_coalesce_info *rtl_coalesce_info(struct net_device *dev)
1796 struct rtl8169_private *tp = netdev_priv(dev);
1797 struct ethtool_link_ksettings ecmd;
1798 const struct rtl_coalesce_info *ci;
1801 rc = phy_ethtool_get_link_ksettings(dev, &ecmd);
1805 for (ci = tp->coalesce_info; ci->speed != 0; ci++) {
1806 if (ecmd.base.speed == ci->speed) {
1811 return ERR_PTR(-ELNRNG);
1814 static int rtl_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1816 struct rtl8169_private *tp = netdev_priv(dev);
1817 const struct rtl_coalesce_info *ci;
1818 const struct rtl_coalesce_scale *scale;
1822 } coal_settings [] = {
1823 { &ec->rx_max_coalesced_frames, &ec->rx_coalesce_usecs },
1824 { &ec->tx_max_coalesced_frames, &ec->tx_coalesce_usecs }
1825 }, *p = coal_settings;
1829 memset(ec, 0, sizeof(*ec));
1831 /* get rx/tx scale corresponding to current speed and CPlusCmd[0:1] */
1832 ci = rtl_coalesce_info(dev);
1836 scale = &ci->scalev[tp->cp_cmd & INTT_MASK];
1838 /* read IntrMitigate and adjust according to scale */
1839 for (w = RTL_R16(tp, IntrMitigate); w; w >>= RTL_COALESCE_SHIFT, p++) {
1840 *p->max_frames = (w & RTL_COALESCE_MASK) << 2;
1841 w >>= RTL_COALESCE_SHIFT;
1842 *p->usecs = w & RTL_COALESCE_MASK;
1845 for (i = 0; i < 2; i++) {
1846 p = coal_settings + i;
1847 *p->usecs = (*p->usecs * scale->nsecs[i]) / 1000;
1850 * ethtool_coalesce says it is illegal to set both usecs and
1853 if (!*p->usecs && !*p->max_frames)
1860 /* choose appropriate scale factor and CPlusCmd[0:1] for (speed, nsec) */
1861 static const struct rtl_coalesce_scale *rtl_coalesce_choose_scale(
1862 struct net_device *dev, u32 nsec, u16 *cp01)
1864 const struct rtl_coalesce_info *ci;
1867 ci = rtl_coalesce_info(dev);
1869 return ERR_CAST(ci);
1871 for (i = 0; i < 4; i++) {
1872 u32 rxtx_maxscale = max(ci->scalev[i].nsecs[0],
1873 ci->scalev[i].nsecs[1]);
1874 if (nsec <= rxtx_maxscale * RTL_COALESCE_T_MAX) {
1876 return &ci->scalev[i];
1880 return ERR_PTR(-EINVAL);
1883 static int rtl_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1885 struct rtl8169_private *tp = netdev_priv(dev);
1886 const struct rtl_coalesce_scale *scale;
1890 } coal_settings [] = {
1891 { ec->rx_max_coalesced_frames, ec->rx_coalesce_usecs },
1892 { ec->tx_max_coalesced_frames, ec->tx_coalesce_usecs }
1893 }, *p = coal_settings;
1897 scale = rtl_coalesce_choose_scale(dev,
1898 max(p[0].usecs, p[1].usecs) * 1000, &cp01);
1900 return PTR_ERR(scale);
1902 for (i = 0; i < 2; i++, p++) {
1906 * accept max_frames=1 we returned in rtl_get_coalesce.
1907 * accept it not only when usecs=0 because of e.g. the following scenario:
1909 * - both rx_usecs=0 & rx_frames=0 in hardware (no delay on RX)
1910 * - rtl_get_coalesce returns rx_usecs=0, rx_frames=1
1911 * - then user does `ethtool -C eth0 rx-usecs 100`
1913 * since ethtool sends to kernel whole ethtool_coalesce
1914 * settings, if we do not handle rx_usecs=!0, rx_frames=1
1915 * we'll reject it below in `frames % 4 != 0`.
1917 if (p->frames == 1) {
1921 units = p->usecs * 1000 / scale->nsecs[i];
1922 if (p->frames > RTL_COALESCE_FRAME_MAX || p->frames % 4)
1925 w <<= RTL_COALESCE_SHIFT;
1927 w <<= RTL_COALESCE_SHIFT;
1928 w |= p->frames >> 2;
1933 RTL_W16(tp, IntrMitigate, swab16(w));
1935 tp->cp_cmd = (tp->cp_cmd & ~INTT_MASK) | cp01;
1936 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1937 RTL_R16(tp, CPlusCmd);
1939 rtl_unlock_work(tp);
1944 static int rtl_get_eee_supp(struct rtl8169_private *tp)
1946 struct phy_device *phydev = tp->phydev;
1949 switch (tp->mac_version) {
1950 case RTL_GIGA_MAC_VER_34:
1951 case RTL_GIGA_MAC_VER_35:
1952 case RTL_GIGA_MAC_VER_36:
1953 case RTL_GIGA_MAC_VER_38:
1954 ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE);
1956 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
1957 phy_write(phydev, 0x1f, 0x0a5c);
1958 ret = phy_read(phydev, 0x12);
1959 phy_write(phydev, 0x1f, 0x0000);
1962 ret = -EPROTONOSUPPORT;
1969 static int rtl_get_eee_lpadv(struct rtl8169_private *tp)
1971 struct phy_device *phydev = tp->phydev;
1974 switch (tp->mac_version) {
1975 case RTL_GIGA_MAC_VER_34:
1976 case RTL_GIGA_MAC_VER_35:
1977 case RTL_GIGA_MAC_VER_36:
1978 case RTL_GIGA_MAC_VER_38:
1979 ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE);
1981 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
1982 phy_write(phydev, 0x1f, 0x0a5d);
1983 ret = phy_read(phydev, 0x11);
1984 phy_write(phydev, 0x1f, 0x0000);
1987 ret = -EPROTONOSUPPORT;
1994 static int rtl_get_eee_adv(struct rtl8169_private *tp)
1996 struct phy_device *phydev = tp->phydev;
1999 switch (tp->mac_version) {
2000 case RTL_GIGA_MAC_VER_34:
2001 case RTL_GIGA_MAC_VER_35:
2002 case RTL_GIGA_MAC_VER_36:
2003 case RTL_GIGA_MAC_VER_38:
2004 ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV);
2006 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
2007 phy_write(phydev, 0x1f, 0x0a5d);
2008 ret = phy_read(phydev, 0x10);
2009 phy_write(phydev, 0x1f, 0x0000);
2012 ret = -EPROTONOSUPPORT;
2019 static int rtl_set_eee_adv(struct rtl8169_private *tp, int val)
2021 struct phy_device *phydev = tp->phydev;
2024 switch (tp->mac_version) {
2025 case RTL_GIGA_MAC_VER_34:
2026 case RTL_GIGA_MAC_VER_35:
2027 case RTL_GIGA_MAC_VER_36:
2028 case RTL_GIGA_MAC_VER_38:
2029 ret = phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);
2031 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
2032 phy_write(phydev, 0x1f, 0x0a5d);
2033 phy_write(phydev, 0x10, val);
2034 phy_write(phydev, 0x1f, 0x0000);
2037 ret = -EPROTONOSUPPORT;
2044 static int rtl8169_get_eee(struct net_device *dev, struct ethtool_eee *data)
2046 struct rtl8169_private *tp = netdev_priv(dev);
2047 struct device *d = tp_to_dev(tp);
2050 pm_runtime_get_noresume(d);
2052 if (!pm_runtime_active(d)) {
2057 /* Get Supported EEE */
2058 ret = rtl_get_eee_supp(tp);
2061 data->supported = mmd_eee_cap_to_ethtool_sup_t(ret);
2063 /* Get advertisement EEE */
2064 ret = rtl_get_eee_adv(tp);
2067 data->advertised = mmd_eee_adv_to_ethtool_adv_t(ret);
2068 data->eee_enabled = !!data->advertised;
2070 /* Get LP advertisement EEE */
2071 ret = rtl_get_eee_lpadv(tp);
2074 data->lp_advertised = mmd_eee_adv_to_ethtool_adv_t(ret);
2075 data->eee_active = !!(data->advertised & data->lp_advertised);
2077 pm_runtime_put_noidle(d);
2078 return ret < 0 ? ret : 0;
2081 static int rtl8169_set_eee(struct net_device *dev, struct ethtool_eee *data)
2083 struct rtl8169_private *tp = netdev_priv(dev);
2084 struct device *d = tp_to_dev(tp);
2085 int old_adv, adv = 0, cap, ret;
2087 pm_runtime_get_noresume(d);
2089 if (!dev->phydev || !pm_runtime_active(d)) {
2094 if (dev->phydev->autoneg == AUTONEG_DISABLE ||
2095 dev->phydev->duplex != DUPLEX_FULL) {
2096 ret = -EPROTONOSUPPORT;
2100 /* Get Supported EEE */
2101 ret = rtl_get_eee_supp(tp);
2106 ret = rtl_get_eee_adv(tp);
2111 if (data->eee_enabled) {
2112 adv = !data->advertised ? cap :
2113 ethtool_adv_to_mmd_eee_adv_t(data->advertised) & cap;
2114 /* Mask prohibited EEE modes */
2115 adv &= ~dev->phydev->eee_broken_modes;
2118 if (old_adv != adv) {
2119 ret = rtl_set_eee_adv(tp, adv);
2123 /* Restart autonegotiation so the new modes get sent to the
2126 ret = phy_restart_aneg(dev->phydev);
2130 pm_runtime_put_noidle(d);
2131 return ret < 0 ? ret : 0;
2134 static const struct ethtool_ops rtl8169_ethtool_ops = {
2135 .get_drvinfo = rtl8169_get_drvinfo,
2136 .get_regs_len = rtl8169_get_regs_len,
2137 .get_link = ethtool_op_get_link,
2138 .get_coalesce = rtl_get_coalesce,
2139 .set_coalesce = rtl_set_coalesce,
2140 .get_msglevel = rtl8169_get_msglevel,
2141 .set_msglevel = rtl8169_set_msglevel,
2142 .get_regs = rtl8169_get_regs,
2143 .get_wol = rtl8169_get_wol,
2144 .set_wol = rtl8169_set_wol,
2145 .get_strings = rtl8169_get_strings,
2146 .get_sset_count = rtl8169_get_sset_count,
2147 .get_ethtool_stats = rtl8169_get_ethtool_stats,
2148 .get_ts_info = ethtool_op_get_ts_info,
2149 .nway_reset = phy_ethtool_nway_reset,
2150 .get_eee = rtl8169_get_eee,
2151 .set_eee = rtl8169_set_eee,
2152 .get_link_ksettings = phy_ethtool_get_link_ksettings,
2153 .set_link_ksettings = phy_ethtool_set_link_ksettings,
2156 static void rtl_enable_eee(struct rtl8169_private *tp)
2158 int supported = rtl_get_eee_supp(tp);
2161 rtl_set_eee_adv(tp, supported);
2164 static void rtl8169_get_mac_version(struct rtl8169_private *tp)
2167 * The driver currently handles the 8168Bf and the 8168Be identically
2168 * but they can be identified more specifically through the test below
2171 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
2173 * Same thing for the 8101Eb and the 8101Ec:
2175 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
2177 static const struct rtl_mac_info {
2182 /* 8168EP family. */
2183 { 0x7cf, 0x502, RTL_GIGA_MAC_VER_51 },
2184 { 0x7cf, 0x501, RTL_GIGA_MAC_VER_50 },
2185 { 0x7cf, 0x500, RTL_GIGA_MAC_VER_49 },
2188 { 0x7cf, 0x541, RTL_GIGA_MAC_VER_46 },
2189 { 0x7cf, 0x540, RTL_GIGA_MAC_VER_45 },
2192 { 0x7cf, 0x5c8, RTL_GIGA_MAC_VER_44 },
2193 { 0x7cf, 0x509, RTL_GIGA_MAC_VER_42 },
2194 { 0x7cf, 0x4c1, RTL_GIGA_MAC_VER_41 },
2195 { 0x7cf, 0x4c0, RTL_GIGA_MAC_VER_40 },
2198 { 0x7c8, 0x488, RTL_GIGA_MAC_VER_38 },
2199 { 0x7cf, 0x481, RTL_GIGA_MAC_VER_36 },
2200 { 0x7cf, 0x480, RTL_GIGA_MAC_VER_35 },
2203 { 0x7c8, 0x2c8, RTL_GIGA_MAC_VER_34 },
2204 { 0x7cf, 0x2c1, RTL_GIGA_MAC_VER_32 },
2205 { 0x7c8, 0x2c0, RTL_GIGA_MAC_VER_33 },
2208 { 0x7cf, 0x281, RTL_GIGA_MAC_VER_25 },
2209 { 0x7c8, 0x280, RTL_GIGA_MAC_VER_26 },
2211 /* 8168DP family. */
2212 { 0x7cf, 0x288, RTL_GIGA_MAC_VER_27 },
2213 { 0x7cf, 0x28a, RTL_GIGA_MAC_VER_28 },
2214 { 0x7cf, 0x28b, RTL_GIGA_MAC_VER_31 },
2217 { 0x7cf, 0x3c9, RTL_GIGA_MAC_VER_23 },
2218 { 0x7cf, 0x3c8, RTL_GIGA_MAC_VER_18 },
2219 { 0x7c8, 0x3c8, RTL_GIGA_MAC_VER_24 },
2220 { 0x7cf, 0x3c0, RTL_GIGA_MAC_VER_19 },
2221 { 0x7cf, 0x3c2, RTL_GIGA_MAC_VER_20 },
2222 { 0x7cf, 0x3c3, RTL_GIGA_MAC_VER_21 },
2223 { 0x7c8, 0x3c0, RTL_GIGA_MAC_VER_22 },
2226 { 0x7cf, 0x380, RTL_GIGA_MAC_VER_12 },
2227 { 0x7c8, 0x380, RTL_GIGA_MAC_VER_17 },
2228 { 0x7c8, 0x300, RTL_GIGA_MAC_VER_11 },
2231 { 0x7c8, 0x448, RTL_GIGA_MAC_VER_39 },
2232 { 0x7c8, 0x440, RTL_GIGA_MAC_VER_37 },
2233 { 0x7cf, 0x409, RTL_GIGA_MAC_VER_29 },
2234 { 0x7c8, 0x408, RTL_GIGA_MAC_VER_30 },
2235 { 0x7cf, 0x349, RTL_GIGA_MAC_VER_08 },
2236 { 0x7cf, 0x249, RTL_GIGA_MAC_VER_08 },
2237 { 0x7cf, 0x348, RTL_GIGA_MAC_VER_07 },
2238 { 0x7cf, 0x248, RTL_GIGA_MAC_VER_07 },
2239 { 0x7cf, 0x340, RTL_GIGA_MAC_VER_13 },
2240 { 0x7cf, 0x343, RTL_GIGA_MAC_VER_10 },
2241 { 0x7cf, 0x342, RTL_GIGA_MAC_VER_16 },
2242 { 0x7c8, 0x348, RTL_GIGA_MAC_VER_09 },
2243 { 0x7c8, 0x248, RTL_GIGA_MAC_VER_09 },
2244 { 0x7c8, 0x340, RTL_GIGA_MAC_VER_16 },
2245 /* FIXME: where did these entries come from ? -- FR */
2246 { 0xfc8, 0x388, RTL_GIGA_MAC_VER_15 },
2247 { 0xfc8, 0x308, RTL_GIGA_MAC_VER_14 },
2250 { 0xfc8, 0x980, RTL_GIGA_MAC_VER_06 },
2251 { 0xfc8, 0x180, RTL_GIGA_MAC_VER_05 },
2252 { 0xfc8, 0x100, RTL_GIGA_MAC_VER_04 },
2253 { 0xfc8, 0x040, RTL_GIGA_MAC_VER_03 },
2254 { 0xfc8, 0x008, RTL_GIGA_MAC_VER_02 },
2255 { 0xfc8, 0x000, RTL_GIGA_MAC_VER_01 },
2258 { 0x000, 0x000, RTL_GIGA_MAC_NONE }
2260 const struct rtl_mac_info *p = mac_info;
2261 u16 reg = RTL_R32(tp, TxConfig) >> 20;
2263 while ((reg & p->mask) != p->val)
2265 tp->mac_version = p->mac_version;
2267 if (tp->mac_version == RTL_GIGA_MAC_NONE) {
2268 dev_err(tp_to_dev(tp), "unknown chip XID %03x\n", reg & 0xfcf);
2269 } else if (!tp->supports_gmii) {
2270 if (tp->mac_version == RTL_GIGA_MAC_VER_42)
2271 tp->mac_version = RTL_GIGA_MAC_VER_43;
2272 else if (tp->mac_version == RTL_GIGA_MAC_VER_45)
2273 tp->mac_version = RTL_GIGA_MAC_VER_47;
2274 else if (tp->mac_version == RTL_GIGA_MAC_VER_46)
2275 tp->mac_version = RTL_GIGA_MAC_VER_48;
2284 static void __rtl_writephy_batch(struct rtl8169_private *tp,
2285 const struct phy_reg *regs, int len)
2288 rtl_writephy(tp, regs->reg, regs->val);
2293 #define rtl_writephy_batch(tp, a) __rtl_writephy_batch(tp, a, ARRAY_SIZE(a))
2295 #define PHY_READ 0x00000000
2296 #define PHY_DATA_OR 0x10000000
2297 #define PHY_DATA_AND 0x20000000
2298 #define PHY_BJMPN 0x30000000
2299 #define PHY_MDIO_CHG 0x40000000
2300 #define PHY_CLEAR_READCOUNT 0x70000000
2301 #define PHY_WRITE 0x80000000
2302 #define PHY_READCOUNT_EQ_SKIP 0x90000000
2303 #define PHY_COMP_EQ_SKIPN 0xa0000000
2304 #define PHY_COMP_NEQ_SKIPN 0xb0000000
2305 #define PHY_WRITE_PREVIOUS 0xc0000000
2306 #define PHY_SKIPN 0xd0000000
2307 #define PHY_DELAY_MS 0xe0000000
2311 char version[RTL_VER_SIZE];
2317 #define FW_OPCODE_SIZE sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
2319 static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2321 const struct firmware *fw = rtl_fw->fw;
2322 struct fw_info *fw_info = (struct fw_info *)fw->data;
2323 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2324 char *version = rtl_fw->version;
2327 if (fw->size < FW_OPCODE_SIZE)
2330 if (!fw_info->magic) {
2331 size_t i, size, start;
2334 if (fw->size < sizeof(*fw_info))
2337 for (i = 0; i < fw->size; i++)
2338 checksum += fw->data[i];
2342 start = le32_to_cpu(fw_info->fw_start);
2343 if (start > fw->size)
2346 size = le32_to_cpu(fw_info->fw_len);
2347 if (size > (fw->size - start) / FW_OPCODE_SIZE)
2350 memcpy(version, fw_info->version, RTL_VER_SIZE);
2352 pa->code = (__le32 *)(fw->data + start);
2355 if (fw->size % FW_OPCODE_SIZE)
2358 strlcpy(version, tp->fw_name, RTL_VER_SIZE);
2360 pa->code = (__le32 *)fw->data;
2361 pa->size = fw->size / FW_OPCODE_SIZE;
2363 version[RTL_VER_SIZE - 1] = 0;
2370 static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev,
2371 struct rtl_fw_phy_action *pa)
2376 for (index = 0; index < pa->size; index++) {
2377 u32 action = le32_to_cpu(pa->code[index]);
2378 u32 regno = (action & 0x0fff0000) >> 16;
2380 switch(action & 0xf0000000) {
2385 case PHY_CLEAR_READCOUNT:
2387 case PHY_WRITE_PREVIOUS:
2392 if (regno > index) {
2393 netif_err(tp, ifup, tp->dev,
2394 "Out of range of firmware\n");
2398 case PHY_READCOUNT_EQ_SKIP:
2399 if (index + 2 >= pa->size) {
2400 netif_err(tp, ifup, tp->dev,
2401 "Out of range of firmware\n");
2405 case PHY_COMP_EQ_SKIPN:
2406 case PHY_COMP_NEQ_SKIPN:
2408 if (index + 1 + regno >= pa->size) {
2409 netif_err(tp, ifup, tp->dev,
2410 "Out of range of firmware\n");
2416 netif_err(tp, ifup, tp->dev,
2417 "Invalid action 0x%08x\n", action);
2426 static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2428 struct net_device *dev = tp->dev;
2431 if (!rtl_fw_format_ok(tp, rtl_fw)) {
2432 netif_err(tp, ifup, dev, "invalid firmware\n");
2436 if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action))
2442 static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2444 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2445 struct mdio_ops org, *ops = &tp->mdio_ops;
2449 predata = count = 0;
2450 org.write = ops->write;
2451 org.read = ops->read;
2453 for (index = 0; index < pa->size; ) {
2454 u32 action = le32_to_cpu(pa->code[index]);
2455 u32 data = action & 0x0000ffff;
2456 u32 regno = (action & 0x0fff0000) >> 16;
2461 switch(action & 0xf0000000) {
2463 predata = rtl_readphy(tp, regno);
2480 ops->write = org.write;
2481 ops->read = org.read;
2482 } else if (data == 1) {
2483 ops->write = mac_mcu_write;
2484 ops->read = mac_mcu_read;
2489 case PHY_CLEAR_READCOUNT:
2494 rtl_writephy(tp, regno, data);
2497 case PHY_READCOUNT_EQ_SKIP:
2498 index += (count == data) ? 2 : 1;
2500 case PHY_COMP_EQ_SKIPN:
2501 if (predata == data)
2505 case PHY_COMP_NEQ_SKIPN:
2506 if (predata != data)
2510 case PHY_WRITE_PREVIOUS:
2511 rtl_writephy(tp, regno, predata);
2527 ops->write = org.write;
2528 ops->read = org.read;
2531 static void rtl_release_firmware(struct rtl8169_private *tp)
2534 release_firmware(tp->rtl_fw->fw);
2540 static void rtl_apply_firmware(struct rtl8169_private *tp)
2542 /* TODO: release firmware once rtl_phy_write_fw signals failures. */
2544 rtl_phy_write_fw(tp, tp->rtl_fw);
2547 static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
2549 if (rtl_readphy(tp, reg) != val)
2550 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
2552 rtl_apply_firmware(tp);
2555 static void rtl8168_config_eee_mac(struct rtl8169_private *tp)
2557 /* Adjust EEE LED frequency */
2558 if (tp->mac_version != RTL_GIGA_MAC_VER_38)
2559 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
2561 rtl_eri_set_bits(tp, 0x1b0, ERIAR_MASK_1111, 0x0003);
2564 static void rtl8168f_config_eee_phy(struct rtl8169_private *tp)
2566 struct phy_device *phydev = tp->phydev;
2568 phy_write(phydev, 0x1f, 0x0007);
2569 phy_write(phydev, 0x1e, 0x0020);
2570 phy_set_bits(phydev, 0x15, BIT(8));
2572 phy_write(phydev, 0x1f, 0x0005);
2573 phy_write(phydev, 0x05, 0x8b85);
2574 phy_set_bits(phydev, 0x06, BIT(13));
2576 phy_write(phydev, 0x1f, 0x0000);
2579 static void rtl8168g_config_eee_phy(struct rtl8169_private *tp)
2581 phy_write(tp->phydev, 0x1f, 0x0a43);
2582 phy_set_bits(tp->phydev, 0x11, BIT(4));
2583 phy_write(tp->phydev, 0x1f, 0x0000);
2586 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
2588 static const struct phy_reg phy_reg_init[] = {
2650 rtl_writephy_batch(tp, phy_reg_init);
2653 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
2655 static const struct phy_reg phy_reg_init[] = {
2661 rtl_writephy_batch(tp, phy_reg_init);
2664 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2666 struct pci_dev *pdev = tp->pci_dev;
2668 if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
2669 (pdev->subsystem_device != 0xe000))
2672 rtl_writephy(tp, 0x1f, 0x0001);
2673 rtl_writephy(tp, 0x10, 0xf01b);
2674 rtl_writephy(tp, 0x1f, 0x0000);
2677 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2679 static const struct phy_reg phy_reg_init[] = {
2719 rtl_writephy_batch(tp, phy_reg_init);
2721 rtl8169scd_hw_phy_config_quirk(tp);
2724 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
2726 static const struct phy_reg phy_reg_init[] = {
2774 rtl_writephy_batch(tp, phy_reg_init);
2777 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
2779 static const struct phy_reg phy_reg_init[] = {
2784 rtl_writephy(tp, 0x1f, 0x0001);
2785 rtl_patchphy(tp, 0x16, 1 << 0);
2787 rtl_writephy_batch(tp, phy_reg_init);
2790 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
2792 static const struct phy_reg phy_reg_init[] = {
2798 rtl_writephy_batch(tp, phy_reg_init);
2801 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
2803 static const struct phy_reg phy_reg_init[] = {
2811 rtl_writephy_batch(tp, phy_reg_init);
2814 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
2816 static const struct phy_reg phy_reg_init[] = {
2822 rtl_writephy(tp, 0x1f, 0x0000);
2823 rtl_patchphy(tp, 0x14, 1 << 5);
2824 rtl_patchphy(tp, 0x0d, 1 << 5);
2826 rtl_writephy_batch(tp, phy_reg_init);
2829 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
2831 static const struct phy_reg phy_reg_init[] = {
2851 rtl_writephy_batch(tp, phy_reg_init);
2853 rtl_patchphy(tp, 0x14, 1 << 5);
2854 rtl_patchphy(tp, 0x0d, 1 << 5);
2855 rtl_writephy(tp, 0x1f, 0x0000);
2858 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
2860 static const struct phy_reg phy_reg_init[] = {
2878 rtl_writephy_batch(tp, phy_reg_init);
2880 rtl_patchphy(tp, 0x16, 1 << 0);
2881 rtl_patchphy(tp, 0x14, 1 << 5);
2882 rtl_patchphy(tp, 0x0d, 1 << 5);
2883 rtl_writephy(tp, 0x1f, 0x0000);
2886 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
2888 static const struct phy_reg phy_reg_init[] = {
2900 rtl_writephy_batch(tp, phy_reg_init);
2902 rtl_patchphy(tp, 0x16, 1 << 0);
2903 rtl_patchphy(tp, 0x14, 1 << 5);
2904 rtl_patchphy(tp, 0x0d, 1 << 5);
2905 rtl_writephy(tp, 0x1f, 0x0000);
2908 static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
2910 rtl8168c_3_hw_phy_config(tp);
2913 static const struct phy_reg rtl8168d_1_phy_reg_init_0[] = {
2914 /* Channel Estimation */
2935 * Enhance line driver power
2944 * Can not link to 1Gbps with bad cable
2945 * Decrease SNR threshold form 21.07dB to 19.04dB
2954 static const struct phy_reg rtl8168d_1_phy_reg_init_1[] = {
2963 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
2965 rtl_writephy_batch(tp, rtl8168d_1_phy_reg_init_0);
2969 * Fine Tune Switching regulator parameter
2971 rtl_writephy(tp, 0x1f, 0x0002);
2972 rtl_w0w1_phy(tp, 0x0b, 0x0010, 0x00ef);
2973 rtl_w0w1_phy(tp, 0x0c, 0xa200, 0x5d00);
2975 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
2978 rtl_writephy_batch(tp, rtl8168d_1_phy_reg_init_1);
2980 val = rtl_readphy(tp, 0x0d);
2982 if ((val & 0x00ff) != 0x006c) {
2983 static const u32 set[] = {
2984 0x0065, 0x0066, 0x0067, 0x0068,
2985 0x0069, 0x006a, 0x006b, 0x006c
2989 rtl_writephy(tp, 0x1f, 0x0002);
2992 for (i = 0; i < ARRAY_SIZE(set); i++)
2993 rtl_writephy(tp, 0x0d, val | set[i]);
2996 static const struct phy_reg phy_reg_init[] = {
3004 rtl_writephy_batch(tp, phy_reg_init);
3007 /* RSET couple improve */
3008 rtl_writephy(tp, 0x1f, 0x0002);
3009 rtl_patchphy(tp, 0x0d, 0x0300);
3010 rtl_patchphy(tp, 0x0f, 0x0010);
3012 /* Fine tune PLL performance */
3013 rtl_writephy(tp, 0x1f, 0x0002);
3014 rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
3015 rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
3017 rtl_writephy(tp, 0x1f, 0x0005);
3018 rtl_writephy(tp, 0x05, 0x001b);
3020 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
3022 rtl_writephy(tp, 0x1f, 0x0000);
3025 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
3027 rtl_writephy_batch(tp, rtl8168d_1_phy_reg_init_0);
3029 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
3032 rtl_writephy_batch(tp, rtl8168d_1_phy_reg_init_1);
3034 val = rtl_readphy(tp, 0x0d);
3035 if ((val & 0x00ff) != 0x006c) {
3036 static const u32 set[] = {
3037 0x0065, 0x0066, 0x0067, 0x0068,
3038 0x0069, 0x006a, 0x006b, 0x006c
3042 rtl_writephy(tp, 0x1f, 0x0002);
3045 for (i = 0; i < ARRAY_SIZE(set); i++)
3046 rtl_writephy(tp, 0x0d, val | set[i]);
3049 static const struct phy_reg phy_reg_init[] = {
3057 rtl_writephy_batch(tp, phy_reg_init);
3060 /* Fine tune PLL performance */
3061 rtl_writephy(tp, 0x1f, 0x0002);
3062 rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
3063 rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
3065 /* Switching regulator Slew rate */
3066 rtl_writephy(tp, 0x1f, 0x0002);
3067 rtl_patchphy(tp, 0x0f, 0x0017);
3069 rtl_writephy(tp, 0x1f, 0x0005);
3070 rtl_writephy(tp, 0x05, 0x001b);
3072 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
3074 rtl_writephy(tp, 0x1f, 0x0000);
3077 static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
3079 static const struct phy_reg phy_reg_init[] = {
3135 rtl_writephy_batch(tp, phy_reg_init);
3138 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
3140 static const struct phy_reg phy_reg_init[] = {
3150 rtl_writephy_batch(tp, phy_reg_init);
3151 rtl_patchphy(tp, 0x0d, 1 << 5);
3154 static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
3156 static const struct phy_reg phy_reg_init[] = {
3157 /* Enable Delay cap */
3163 /* Channel estimation fine tune */
3172 /* Update PFM & 10M TX idle timer */
3184 rtl_apply_firmware(tp);
3186 rtl_writephy_batch(tp, phy_reg_init);
3188 /* DCO enable for 10M IDLE Power */
3189 rtl_writephy(tp, 0x1f, 0x0007);
3190 rtl_writephy(tp, 0x1e, 0x0023);
3191 rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
3192 rtl_writephy(tp, 0x1f, 0x0000);
3194 /* For impedance matching */
3195 rtl_writephy(tp, 0x1f, 0x0002);
3196 rtl_w0w1_phy(tp, 0x08, 0x8000, 0x7f00);
3197 rtl_writephy(tp, 0x1f, 0x0000);
3199 /* PHY auto speed down */
3200 rtl_writephy(tp, 0x1f, 0x0007);
3201 rtl_writephy(tp, 0x1e, 0x002d);
3202 rtl_w0w1_phy(tp, 0x18, 0x0050, 0x0000);
3203 rtl_writephy(tp, 0x1f, 0x0000);
3204 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3206 rtl_writephy(tp, 0x1f, 0x0005);
3207 rtl_writephy(tp, 0x05, 0x8b86);
3208 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3209 rtl_writephy(tp, 0x1f, 0x0000);
3211 rtl_writephy(tp, 0x1f, 0x0005);
3212 rtl_writephy(tp, 0x05, 0x8b85);
3213 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
3214 rtl_writephy(tp, 0x1f, 0x0007);
3215 rtl_writephy(tp, 0x1e, 0x0020);
3216 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x1100);
3217 rtl_writephy(tp, 0x1f, 0x0006);
3218 rtl_writephy(tp, 0x00, 0x5a00);
3219 rtl_writephy(tp, 0x1f, 0x0000);
3220 rtl_writephy(tp, 0x0d, 0x0007);
3221 rtl_writephy(tp, 0x0e, 0x003c);
3222 rtl_writephy(tp, 0x0d, 0x4007);
3223 rtl_writephy(tp, 0x0e, 0x0000);
3224 rtl_writephy(tp, 0x0d, 0x0000);
3227 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, u8 *addr)
3230 addr[0] | (addr[1] << 8),
3231 addr[2] | (addr[3] << 8),
3232 addr[4] | (addr[5] << 8)
3235 rtl_eri_write(tp, 0xe0, ERIAR_MASK_1111, w[0] | (w[1] << 16));
3236 rtl_eri_write(tp, 0xe4, ERIAR_MASK_1111, w[2]);
3237 rtl_eri_write(tp, 0xf0, ERIAR_MASK_1111, w[0] << 16);
3238 rtl_eri_write(tp, 0xf4, ERIAR_MASK_1111, w[1] | (w[2] << 16));
3241 static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
3243 static const struct phy_reg phy_reg_init[] = {
3244 /* Enable Delay cap */
3253 /* Channel estimation fine tune */
3270 rtl_apply_firmware(tp);
3272 rtl_writephy_batch(tp, phy_reg_init);
3274 /* For 4-corner performance improve */
3275 rtl_writephy(tp, 0x1f, 0x0005);
3276 rtl_writephy(tp, 0x05, 0x8b80);
3277 rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
3278 rtl_writephy(tp, 0x1f, 0x0000);
3280 /* PHY auto speed down */
3281 rtl_writephy(tp, 0x1f, 0x0004);
3282 rtl_writephy(tp, 0x1f, 0x0007);
3283 rtl_writephy(tp, 0x1e, 0x002d);
3284 rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
3285 rtl_writephy(tp, 0x1f, 0x0002);
3286 rtl_writephy(tp, 0x1f, 0x0000);
3287 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3289 /* improve 10M EEE waveform */
3290 rtl_writephy(tp, 0x1f, 0x0005);
3291 rtl_writephy(tp, 0x05, 0x8b86);
3292 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3293 rtl_writephy(tp, 0x1f, 0x0000);
3295 /* Improve 2-pair detection performance */
3296 rtl_writephy(tp, 0x1f, 0x0005);
3297 rtl_writephy(tp, 0x05, 0x8b85);
3298 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3299 rtl_writephy(tp, 0x1f, 0x0000);
3301 rtl8168f_config_eee_phy(tp);
3305 rtl_writephy(tp, 0x1f, 0x0003);
3306 rtl_w0w1_phy(tp, 0x19, 0x0001, 0x0000);
3307 rtl_w0w1_phy(tp, 0x10, 0x0400, 0x0000);
3308 rtl_writephy(tp, 0x1f, 0x0000);
3309 rtl_writephy(tp, 0x1f, 0x0005);
3310 rtl_w0w1_phy(tp, 0x01, 0x0100, 0x0000);
3311 rtl_writephy(tp, 0x1f, 0x0000);
3313 /* Broken BIOS workaround: feed GigaMAC registers with MAC address. */
3314 rtl_rar_exgmac_set(tp, tp->dev->dev_addr);
3317 static void rtl8168f_hw_phy_config(struct rtl8169_private *tp)
3319 /* For 4-corner performance improve */
3320 rtl_writephy(tp, 0x1f, 0x0005);
3321 rtl_writephy(tp, 0x05, 0x8b80);
3322 rtl_w0w1_phy(tp, 0x06, 0x0006, 0x0000);
3323 rtl_writephy(tp, 0x1f, 0x0000);
3325 /* PHY auto speed down */
3326 rtl_writephy(tp, 0x1f, 0x0007);
3327 rtl_writephy(tp, 0x1e, 0x002d);
3328 rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
3329 rtl_writephy(tp, 0x1f, 0x0000);
3330 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3332 /* Improve 10M EEE waveform */
3333 rtl_writephy(tp, 0x1f, 0x0005);
3334 rtl_writephy(tp, 0x05, 0x8b86);
3335 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3336 rtl_writephy(tp, 0x1f, 0x0000);
3338 rtl8168f_config_eee_phy(tp);
3342 static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp)
3344 static const struct phy_reg phy_reg_init[] = {
3345 /* Channel estimation fine tune */
3350 /* Modify green table for giga & fnet */
3367 /* Modify green table for 10M */
3373 /* Disable hiimpedance detection (RTCT) */
3379 rtl_apply_firmware(tp);
3381 rtl_writephy_batch(tp, phy_reg_init);
3383 rtl8168f_hw_phy_config(tp);
3385 /* Improve 2-pair detection performance */
3386 rtl_writephy(tp, 0x1f, 0x0005);
3387 rtl_writephy(tp, 0x05, 0x8b85);
3388 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3389 rtl_writephy(tp, 0x1f, 0x0000);
3392 static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp)
3394 rtl_apply_firmware(tp);
3396 rtl8168f_hw_phy_config(tp);
3399 static void rtl8411_hw_phy_config(struct rtl8169_private *tp)
3401 static const struct phy_reg phy_reg_init[] = {
3402 /* Channel estimation fine tune */
3407 /* Modify green table for giga & fnet */
3424 /* Modify green table for 10M */
3430 /* Disable hiimpedance detection (RTCT) */
3437 rtl_apply_firmware(tp);
3439 rtl8168f_hw_phy_config(tp);
3441 /* Improve 2-pair detection performance */
3442 rtl_writephy(tp, 0x1f, 0x0005);
3443 rtl_writephy(tp, 0x05, 0x8b85);
3444 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3445 rtl_writephy(tp, 0x1f, 0x0000);
3447 rtl_writephy_batch(tp, phy_reg_init);
3449 /* Modify green table for giga */
3450 rtl_writephy(tp, 0x1f, 0x0005);
3451 rtl_writephy(tp, 0x05, 0x8b54);
3452 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
3453 rtl_writephy(tp, 0x05, 0x8b5d);
3454 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
3455 rtl_writephy(tp, 0x05, 0x8a7c);
3456 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3457 rtl_writephy(tp, 0x05, 0x8a7f);
3458 rtl_w0w1_phy(tp, 0x06, 0x0100, 0x0000);
3459 rtl_writephy(tp, 0x05, 0x8a82);
3460 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3461 rtl_writephy(tp, 0x05, 0x8a85);
3462 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3463 rtl_writephy(tp, 0x05, 0x8a88);
3464 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3465 rtl_writephy(tp, 0x1f, 0x0000);
3467 /* uc same-seed solution */
3468 rtl_writephy(tp, 0x1f, 0x0005);
3469 rtl_writephy(tp, 0x05, 0x8b85);
3470 rtl_w0w1_phy(tp, 0x06, 0x8000, 0x0000);
3471 rtl_writephy(tp, 0x1f, 0x0000);
3474 rtl_writephy(tp, 0x1f, 0x0003);
3475 rtl_w0w1_phy(tp, 0x19, 0x0000, 0x0001);
3476 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0400);
3477 rtl_writephy(tp, 0x1f, 0x0000);
3480 static void rtl8168g_disable_aldps(struct rtl8169_private *tp)
3482 phy_write(tp->phydev, 0x1f, 0x0a43);
3483 phy_clear_bits(tp->phydev, 0x10, BIT(2));
3486 static void rtl8168g_phy_adjust_10m_aldps(struct rtl8169_private *tp)
3488 struct phy_device *phydev = tp->phydev;
3490 phy_write(phydev, 0x1f, 0x0bcc);
3491 phy_clear_bits(phydev, 0x14, BIT(8));
3493 phy_write(phydev, 0x1f, 0x0a44);
3494 phy_set_bits(phydev, 0x11, BIT(7) | BIT(6));
3496 phy_write(phydev, 0x1f, 0x0a43);
3497 phy_write(phydev, 0x13, 0x8084);
3498 phy_clear_bits(phydev, 0x14, BIT(14) | BIT(13));
3499 phy_set_bits(phydev, 0x10, BIT(12) | BIT(1) | BIT(0));
3501 phy_write(phydev, 0x1f, 0x0000);
3504 static void rtl8168g_1_hw_phy_config(struct rtl8169_private *tp)
3506 rtl_apply_firmware(tp);
3508 rtl_writephy(tp, 0x1f, 0x0a46);
3509 if (rtl_readphy(tp, 0x10) & 0x0100) {
3510 rtl_writephy(tp, 0x1f, 0x0bcc);
3511 rtl_w0w1_phy(tp, 0x12, 0x0000, 0x8000);
3513 rtl_writephy(tp, 0x1f, 0x0bcc);
3514 rtl_w0w1_phy(tp, 0x12, 0x8000, 0x0000);
3517 rtl_writephy(tp, 0x1f, 0x0a46);
3518 if (rtl_readphy(tp, 0x13) & 0x0100) {
3519 rtl_writephy(tp, 0x1f, 0x0c41);
3520 rtl_w0w1_phy(tp, 0x15, 0x0002, 0x0000);
3522 rtl_writephy(tp, 0x1f, 0x0c41);
3523 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x0002);
3526 /* Enable PHY auto speed down */
3527 rtl_writephy(tp, 0x1f, 0x0a44);
3528 rtl_w0w1_phy(tp, 0x11, 0x000c, 0x0000);
3530 rtl8168g_phy_adjust_10m_aldps(tp);
3532 /* EEE auto-fallback function */
3533 rtl_writephy(tp, 0x1f, 0x0a4b);
3534 rtl_w0w1_phy(tp, 0x11, 0x0004, 0x0000);
3536 /* Enable UC LPF tune function */
3537 rtl_writephy(tp, 0x1f, 0x0a43);
3538 rtl_writephy(tp, 0x13, 0x8012);
3539 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3541 rtl_writephy(tp, 0x1f, 0x0c42);
3542 rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
3544 /* Improve SWR Efficiency */
3545 rtl_writephy(tp, 0x1f, 0x0bcd);
3546 rtl_writephy(tp, 0x14, 0x5065);
3547 rtl_writephy(tp, 0x14, 0xd065);
3548 rtl_writephy(tp, 0x1f, 0x0bc8);
3549 rtl_writephy(tp, 0x11, 0x5655);
3550 rtl_writephy(tp, 0x1f, 0x0bcd);
3551 rtl_writephy(tp, 0x14, 0x1065);
3552 rtl_writephy(tp, 0x14, 0x9065);
3553 rtl_writephy(tp, 0x14, 0x1065);
3555 rtl8168g_disable_aldps(tp);
3556 rtl8168g_config_eee_phy(tp);
3560 static void rtl8168g_2_hw_phy_config(struct rtl8169_private *tp)
3562 rtl_apply_firmware(tp);
3563 rtl8168g_config_eee_phy(tp);
3567 static void rtl8168h_1_hw_phy_config(struct rtl8169_private *tp)
3572 rtl_apply_firmware(tp);
3574 /* CHN EST parameters adjust - giga master */
3575 rtl_writephy(tp, 0x1f, 0x0a43);
3576 rtl_writephy(tp, 0x13, 0x809b);
3577 rtl_w0w1_phy(tp, 0x14, 0x8000, 0xf800);
3578 rtl_writephy(tp, 0x13, 0x80a2);
3579 rtl_w0w1_phy(tp, 0x14, 0x8000, 0xff00);
3580 rtl_writephy(tp, 0x13, 0x80a4);
3581 rtl_w0w1_phy(tp, 0x14, 0x8500, 0xff00);
3582 rtl_writephy(tp, 0x13, 0x809c);
3583 rtl_w0w1_phy(tp, 0x14, 0xbd00, 0xff00);
3584 rtl_writephy(tp, 0x1f, 0x0000);
3586 /* CHN EST parameters adjust - giga slave */
3587 rtl_writephy(tp, 0x1f, 0x0a43);
3588 rtl_writephy(tp, 0x13, 0x80ad);
3589 rtl_w0w1_phy(tp, 0x14, 0x7000, 0xf800);
3590 rtl_writephy(tp, 0x13, 0x80b4);
3591 rtl_w0w1_phy(tp, 0x14, 0x5000, 0xff00);
3592 rtl_writephy(tp, 0x13, 0x80ac);
3593 rtl_w0w1_phy(tp, 0x14, 0x4000, 0xff00);
3594 rtl_writephy(tp, 0x1f, 0x0000);
3596 /* CHN EST parameters adjust - fnet */
3597 rtl_writephy(tp, 0x1f, 0x0a43);
3598 rtl_writephy(tp, 0x13, 0x808e);
3599 rtl_w0w1_phy(tp, 0x14, 0x1200, 0xff00);
3600 rtl_writephy(tp, 0x13, 0x8090);
3601 rtl_w0w1_phy(tp, 0x14, 0xe500, 0xff00);
3602 rtl_writephy(tp, 0x13, 0x8092);
3603 rtl_w0w1_phy(tp, 0x14, 0x9f00, 0xff00);
3604 rtl_writephy(tp, 0x1f, 0x0000);
3606 /* enable R-tune & PGA-retune function */
3608 rtl_writephy(tp, 0x1f, 0x0a46);
3609 data = rtl_readphy(tp, 0x13);
3612 dout_tapbin |= data;
3613 data = rtl_readphy(tp, 0x12);
3616 dout_tapbin |= data;
3617 dout_tapbin = ~(dout_tapbin^0x08);
3619 dout_tapbin &= 0xf000;
3620 rtl_writephy(tp, 0x1f, 0x0a43);
3621 rtl_writephy(tp, 0x13, 0x827a);
3622 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3623 rtl_writephy(tp, 0x13, 0x827b);
3624 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3625 rtl_writephy(tp, 0x13, 0x827c);
3626 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3627 rtl_writephy(tp, 0x13, 0x827d);
3628 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3630 rtl_writephy(tp, 0x1f, 0x0a43);
3631 rtl_writephy(tp, 0x13, 0x0811);
3632 rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
3633 rtl_writephy(tp, 0x1f, 0x0a42);
3634 rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
3635 rtl_writephy(tp, 0x1f, 0x0000);
3637 /* enable GPHY 10M */
3638 rtl_writephy(tp, 0x1f, 0x0a44);
3639 rtl_w0w1_phy(tp, 0x11, 0x0800, 0x0000);
3640 rtl_writephy(tp, 0x1f, 0x0000);
3642 /* SAR ADC performance */
3643 rtl_writephy(tp, 0x1f, 0x0bca);
3644 rtl_w0w1_phy(tp, 0x17, 0x4000, 0x3000);
3645 rtl_writephy(tp, 0x1f, 0x0000);
3647 rtl_writephy(tp, 0x1f, 0x0a43);
3648 rtl_writephy(tp, 0x13, 0x803f);
3649 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3650 rtl_writephy(tp, 0x13, 0x8047);
3651 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3652 rtl_writephy(tp, 0x13, 0x804f);
3653 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3654 rtl_writephy(tp, 0x13, 0x8057);
3655 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3656 rtl_writephy(tp, 0x13, 0x805f);
3657 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3658 rtl_writephy(tp, 0x13, 0x8067);
3659 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3660 rtl_writephy(tp, 0x13, 0x806f);
3661 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3662 rtl_writephy(tp, 0x1f, 0x0000);
3664 /* disable phy pfm mode */
3665 rtl_writephy(tp, 0x1f, 0x0a44);
3666 rtl_w0w1_phy(tp, 0x11, 0x0000, 0x0080);
3667 rtl_writephy(tp, 0x1f, 0x0000);
3669 rtl8168g_disable_aldps(tp);
3670 rtl8168g_config_eee_phy(tp);
3674 static void rtl8168h_2_hw_phy_config(struct rtl8169_private *tp)
3676 u16 ioffset_p3, ioffset_p2, ioffset_p1, ioffset_p0;
3680 rtl_apply_firmware(tp);
3682 /* CHIN EST parameter update */
3683 rtl_writephy(tp, 0x1f, 0x0a43);
3684 rtl_writephy(tp, 0x13, 0x808a);
3685 rtl_w0w1_phy(tp, 0x14, 0x000a, 0x003f);
3686 rtl_writephy(tp, 0x1f, 0x0000);
3688 /* enable R-tune & PGA-retune function */
3689 rtl_writephy(tp, 0x1f, 0x0a43);
3690 rtl_writephy(tp, 0x13, 0x0811);
3691 rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
3692 rtl_writephy(tp, 0x1f, 0x0a42);
3693 rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
3694 rtl_writephy(tp, 0x1f, 0x0000);
3696 /* enable GPHY 10M */
3697 rtl_writephy(tp, 0x1f, 0x0a44);
3698 rtl_w0w1_phy(tp, 0x11, 0x0800, 0x0000);
3699 rtl_writephy(tp, 0x1f, 0x0000);
3701 r8168_mac_ocp_write(tp, 0xdd02, 0x807d);
3702 data = r8168_mac_ocp_read(tp, 0xdd02);
3703 ioffset_p3 = ((data & 0x80)>>7);
3706 data = r8168_mac_ocp_read(tp, 0xdd00);
3707 ioffset_p3 |= ((data & (0xe000))>>13);
3708 ioffset_p2 = ((data & (0x1e00))>>9);
3709 ioffset_p1 = ((data & (0x01e0))>>5);
3710 ioffset_p0 = ((data & 0x0010)>>4);
3712 ioffset_p0 |= (data & (0x07));
3713 data = (ioffset_p3<<12)|(ioffset_p2<<8)|(ioffset_p1<<4)|(ioffset_p0);
3715 if ((ioffset_p3 != 0x0f) || (ioffset_p2 != 0x0f) ||
3716 (ioffset_p1 != 0x0f) || (ioffset_p0 != 0x0f)) {
3717 rtl_writephy(tp, 0x1f, 0x0bcf);
3718 rtl_writephy(tp, 0x16, data);
3719 rtl_writephy(tp, 0x1f, 0x0000);
3722 /* Modify rlen (TX LPF corner frequency) level */
3723 rtl_writephy(tp, 0x1f, 0x0bcd);
3724 data = rtl_readphy(tp, 0x16);
3729 data = rlen | (rlen<<4) | (rlen<<8) | (rlen<<12);
3730 rtl_writephy(tp, 0x17, data);
3731 rtl_writephy(tp, 0x1f, 0x0bcd);
3732 rtl_writephy(tp, 0x1f, 0x0000);
3734 /* disable phy pfm mode */
3735 rtl_writephy(tp, 0x1f, 0x0a44);
3736 rtl_w0w1_phy(tp, 0x11, 0x0000, 0x0080);
3737 rtl_writephy(tp, 0x1f, 0x0000);
3739 rtl8168g_disable_aldps(tp);
3740 rtl8168g_config_eee_phy(tp);
3744 static void rtl8168ep_1_hw_phy_config(struct rtl8169_private *tp)
3746 /* Enable PHY auto speed down */
3747 rtl_writephy(tp, 0x1f, 0x0a44);
3748 rtl_w0w1_phy(tp, 0x11, 0x000c, 0x0000);
3749 rtl_writephy(tp, 0x1f, 0x0000);
3751 rtl8168g_phy_adjust_10m_aldps(tp);
3753 /* Enable EEE auto-fallback function */
3754 rtl_writephy(tp, 0x1f, 0x0a4b);
3755 rtl_w0w1_phy(tp, 0x11, 0x0004, 0x0000);
3756 rtl_writephy(tp, 0x1f, 0x0000);
3758 /* Enable UC LPF tune function */
3759 rtl_writephy(tp, 0x1f, 0x0a43);
3760 rtl_writephy(tp, 0x13, 0x8012);
3761 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3762 rtl_writephy(tp, 0x1f, 0x0000);
3764 /* set rg_sel_sdm_rate */
3765 rtl_writephy(tp, 0x1f, 0x0c42);
3766 rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
3767 rtl_writephy(tp, 0x1f, 0x0000);
3769 rtl8168g_disable_aldps(tp);
3770 rtl8168g_config_eee_phy(tp);
3774 static void rtl8168ep_2_hw_phy_config(struct rtl8169_private *tp)
3776 rtl8168g_phy_adjust_10m_aldps(tp);
3778 /* Enable UC LPF tune function */
3779 rtl_writephy(tp, 0x1f, 0x0a43);
3780 rtl_writephy(tp, 0x13, 0x8012);
3781 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3782 rtl_writephy(tp, 0x1f, 0x0000);
3784 /* Set rg_sel_sdm_rate */
3785 rtl_writephy(tp, 0x1f, 0x0c42);
3786 rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
3787 rtl_writephy(tp, 0x1f, 0x0000);
3789 /* Channel estimation parameters */
3790 rtl_writephy(tp, 0x1f, 0x0a43);
3791 rtl_writephy(tp, 0x13, 0x80f3);
3792 rtl_w0w1_phy(tp, 0x14, 0x8b00, ~0x8bff);
3793 rtl_writephy(tp, 0x13, 0x80f0);
3794 rtl_w0w1_phy(tp, 0x14, 0x3a00, ~0x3aff);
3795 rtl_writephy(tp, 0x13, 0x80ef);
3796 rtl_w0w1_phy(tp, 0x14, 0x0500, ~0x05ff);
3797 rtl_writephy(tp, 0x13, 0x80f6);
3798 rtl_w0w1_phy(tp, 0x14, 0x6e00, ~0x6eff);
3799 rtl_writephy(tp, 0x13, 0x80ec);
3800 rtl_w0w1_phy(tp, 0x14, 0x6800, ~0x68ff);
3801 rtl_writephy(tp, 0x13, 0x80ed);
3802 rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
3803 rtl_writephy(tp, 0x13, 0x80f2);
3804 rtl_w0w1_phy(tp, 0x14, 0xf400, ~0xf4ff);
3805 rtl_writephy(tp, 0x13, 0x80f4);
3806 rtl_w0w1_phy(tp, 0x14, 0x8500, ~0x85ff);
3807 rtl_writephy(tp, 0x1f, 0x0a43);
3808 rtl_writephy(tp, 0x13, 0x8110);
3809 rtl_w0w1_phy(tp, 0x14, 0xa800, ~0xa8ff);
3810 rtl_writephy(tp, 0x13, 0x810f);
3811 rtl_w0w1_phy(tp, 0x14, 0x1d00, ~0x1dff);
3812 rtl_writephy(tp, 0x13, 0x8111);
3813 rtl_w0w1_phy(tp, 0x14, 0xf500, ~0xf5ff);
3814 rtl_writephy(tp, 0x13, 0x8113);
3815 rtl_w0w1_phy(tp, 0x14, 0x6100, ~0x61ff);
3816 rtl_writephy(tp, 0x13, 0x8115);
3817 rtl_w0w1_phy(tp, 0x14, 0x9200, ~0x92ff);
3818 rtl_writephy(tp, 0x13, 0x810e);
3819 rtl_w0w1_phy(tp, 0x14, 0x0400, ~0x04ff);
3820 rtl_writephy(tp, 0x13, 0x810c);
3821 rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
3822 rtl_writephy(tp, 0x13, 0x810b);
3823 rtl_w0w1_phy(tp, 0x14, 0x5a00, ~0x5aff);
3824 rtl_writephy(tp, 0x1f, 0x0a43);
3825 rtl_writephy(tp, 0x13, 0x80d1);
3826 rtl_w0w1_phy(tp, 0x14, 0xff00, ~0xffff);
3827 rtl_writephy(tp, 0x13, 0x80cd);
3828 rtl_w0w1_phy(tp, 0x14, 0x9e00, ~0x9eff);
3829 rtl_writephy(tp, 0x13, 0x80d3);
3830 rtl_w0w1_phy(tp, 0x14, 0x0e00, ~0x0eff);
3831 rtl_writephy(tp, 0x13, 0x80d5);
3832 rtl_w0w1_phy(tp, 0x14, 0xca00, ~0xcaff);
3833 rtl_writephy(tp, 0x13, 0x80d7);
3834 rtl_w0w1_phy(tp, 0x14, 0x8400, ~0x84ff);
3836 /* Force PWM-mode */
3837 rtl_writephy(tp, 0x1f, 0x0bcd);
3838 rtl_writephy(tp, 0x14, 0x5065);
3839 rtl_writephy(tp, 0x14, 0xd065);
3840 rtl_writephy(tp, 0x1f, 0x0bc8);
3841 rtl_writephy(tp, 0x12, 0x00ed);
3842 rtl_writephy(tp, 0x1f, 0x0bcd);
3843 rtl_writephy(tp, 0x14, 0x1065);
3844 rtl_writephy(tp, 0x14, 0x9065);
3845 rtl_writephy(tp, 0x14, 0x1065);
3846 rtl_writephy(tp, 0x1f, 0x0000);
3848 rtl8168g_disable_aldps(tp);
3849 rtl8168g_config_eee_phy(tp);
3853 static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
3855 static const struct phy_reg phy_reg_init[] = {
3862 rtl_writephy(tp, 0x1f, 0x0000);
3863 rtl_patchphy(tp, 0x11, 1 << 12);
3864 rtl_patchphy(tp, 0x19, 1 << 13);
3865 rtl_patchphy(tp, 0x10, 1 << 15);
3867 rtl_writephy_batch(tp, phy_reg_init);
3870 static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
3872 static const struct phy_reg phy_reg_init[] = {
3886 /* Disable ALDPS before ram code */
3887 rtl_writephy(tp, 0x1f, 0x0000);
3888 rtl_writephy(tp, 0x18, 0x0310);
3891 rtl_apply_firmware(tp);
3893 rtl_writephy_batch(tp, phy_reg_init);
3896 static void rtl8402_hw_phy_config(struct rtl8169_private *tp)
3898 /* Disable ALDPS before setting firmware */
3899 rtl_writephy(tp, 0x1f, 0x0000);
3900 rtl_writephy(tp, 0x18, 0x0310);
3903 rtl_apply_firmware(tp);
3906 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000);
3907 rtl_writephy(tp, 0x1f, 0x0004);
3908 rtl_writephy(tp, 0x10, 0x401f);
3909 rtl_writephy(tp, 0x19, 0x7030);
3910 rtl_writephy(tp, 0x1f, 0x0000);
3913 static void rtl8106e_hw_phy_config(struct rtl8169_private *tp)
3915 static const struct phy_reg phy_reg_init[] = {
3922 /* Disable ALDPS before ram code */
3923 rtl_writephy(tp, 0x1f, 0x0000);
3924 rtl_writephy(tp, 0x18, 0x0310);
3927 rtl_apply_firmware(tp);
3929 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000);
3930 rtl_writephy_batch(tp, phy_reg_init);
3932 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000);
3935 static void rtl_hw_phy_config(struct net_device *dev)
3937 static const rtl_generic_fct phy_configs[] = {
3939 [RTL_GIGA_MAC_VER_01] = NULL,
3940 [RTL_GIGA_MAC_VER_02] = rtl8169s_hw_phy_config,
3941 [RTL_GIGA_MAC_VER_03] = rtl8169s_hw_phy_config,
3942 [RTL_GIGA_MAC_VER_04] = rtl8169sb_hw_phy_config,
3943 [RTL_GIGA_MAC_VER_05] = rtl8169scd_hw_phy_config,
3944 [RTL_GIGA_MAC_VER_06] = rtl8169sce_hw_phy_config,
3945 /* PCI-E devices. */
3946 [RTL_GIGA_MAC_VER_07] = rtl8102e_hw_phy_config,
3947 [RTL_GIGA_MAC_VER_08] = rtl8102e_hw_phy_config,
3948 [RTL_GIGA_MAC_VER_09] = rtl8102e_hw_phy_config,
3949 [RTL_GIGA_MAC_VER_10] = NULL,
3950 [RTL_GIGA_MAC_VER_11] = rtl8168bb_hw_phy_config,
3951 [RTL_GIGA_MAC_VER_12] = rtl8168bef_hw_phy_config,
3952 [RTL_GIGA_MAC_VER_13] = NULL,
3953 [RTL_GIGA_MAC_VER_14] = NULL,
3954 [RTL_GIGA_MAC_VER_15] = NULL,
3955 [RTL_GIGA_MAC_VER_16] = NULL,
3956 [RTL_GIGA_MAC_VER_17] = rtl8168bef_hw_phy_config,
3957 [RTL_GIGA_MAC_VER_18] = rtl8168cp_1_hw_phy_config,
3958 [RTL_GIGA_MAC_VER_19] = rtl8168c_1_hw_phy_config,
3959 [RTL_GIGA_MAC_VER_20] = rtl8168c_2_hw_phy_config,
3960 [RTL_GIGA_MAC_VER_21] = rtl8168c_3_hw_phy_config,
3961 [RTL_GIGA_MAC_VER_22] = rtl8168c_4_hw_phy_config,
3962 [RTL_GIGA_MAC_VER_23] = rtl8168cp_2_hw_phy_config,
3963 [RTL_GIGA_MAC_VER_24] = rtl8168cp_2_hw_phy_config,
3964 [RTL_GIGA_MAC_VER_25] = rtl8168d_1_hw_phy_config,
3965 [RTL_GIGA_MAC_VER_26] = rtl8168d_2_hw_phy_config,
3966 [RTL_GIGA_MAC_VER_27] = rtl8168d_3_hw_phy_config,
3967 [RTL_GIGA_MAC_VER_28] = rtl8168d_4_hw_phy_config,
3968 [RTL_GIGA_MAC_VER_29] = rtl8105e_hw_phy_config,
3969 [RTL_GIGA_MAC_VER_30] = rtl8105e_hw_phy_config,
3970 [RTL_GIGA_MAC_VER_31] = NULL,
3971 [RTL_GIGA_MAC_VER_32] = rtl8168e_1_hw_phy_config,
3972 [RTL_GIGA_MAC_VER_33] = rtl8168e_1_hw_phy_config,
3973 [RTL_GIGA_MAC_VER_34] = rtl8168e_2_hw_phy_config,
3974 [RTL_GIGA_MAC_VER_35] = rtl8168f_1_hw_phy_config,
3975 [RTL_GIGA_MAC_VER_36] = rtl8168f_2_hw_phy_config,
3976 [RTL_GIGA_MAC_VER_37] = rtl8402_hw_phy_config,
3977 [RTL_GIGA_MAC_VER_38] = rtl8411_hw_phy_config,
3978 [RTL_GIGA_MAC_VER_39] = rtl8106e_hw_phy_config,
3979 [RTL_GIGA_MAC_VER_40] = rtl8168g_1_hw_phy_config,
3980 [RTL_GIGA_MAC_VER_41] = NULL,
3981 [RTL_GIGA_MAC_VER_42] = rtl8168g_2_hw_phy_config,
3982 [RTL_GIGA_MAC_VER_43] = rtl8168g_2_hw_phy_config,
3983 [RTL_GIGA_MAC_VER_44] = rtl8168g_2_hw_phy_config,
3984 [RTL_GIGA_MAC_VER_45] = rtl8168h_1_hw_phy_config,
3985 [RTL_GIGA_MAC_VER_46] = rtl8168h_2_hw_phy_config,
3986 [RTL_GIGA_MAC_VER_47] = rtl8168h_1_hw_phy_config,
3987 [RTL_GIGA_MAC_VER_48] = rtl8168h_2_hw_phy_config,
3988 [RTL_GIGA_MAC_VER_49] = rtl8168ep_1_hw_phy_config,
3989 [RTL_GIGA_MAC_VER_50] = rtl8168ep_2_hw_phy_config,
3990 [RTL_GIGA_MAC_VER_51] = rtl8168ep_2_hw_phy_config,
3992 struct rtl8169_private *tp = netdev_priv(dev);
3994 if (phy_configs[tp->mac_version])
3995 phy_configs[tp->mac_version](tp);
3998 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
4000 if (!test_and_set_bit(flag, tp->wk.flags))
4001 schedule_work(&tp->wk.work);
4004 static bool rtl_tbi_enabled(struct rtl8169_private *tp)
4006 return (tp->mac_version == RTL_GIGA_MAC_VER_01) &&
4007 (RTL_R8(tp, PHYstatus) & TBI_Enable);
4010 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
4012 rtl_hw_phy_config(dev);
4014 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
4015 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
4016 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4017 netif_dbg(tp, drv, dev,
4018 "Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
4019 RTL_W8(tp, 0x82, 0x01);
4022 /* We may have called phy_speed_down before */
4023 phy_speed_up(tp->phydev);
4025 genphy_soft_reset(tp->phydev);
4028 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
4032 rtl_unlock_config_regs(tp);
4034 RTL_W32(tp, MAC4, addr[4] | addr[5] << 8);
4037 RTL_W32(tp, MAC0, addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24);
4040 if (tp->mac_version == RTL_GIGA_MAC_VER_34)
4041 rtl_rar_exgmac_set(tp, addr);
4043 rtl_lock_config_regs(tp);
4045 rtl_unlock_work(tp);
4048 static int rtl_set_mac_address(struct net_device *dev, void *p)
4050 struct rtl8169_private *tp = netdev_priv(dev);
4051 struct device *d = tp_to_dev(tp);
4054 ret = eth_mac_addr(dev, p);
4058 pm_runtime_get_noresume(d);
4060 if (pm_runtime_active(d))
4061 rtl_rar_set(tp, dev->dev_addr);
4063 pm_runtime_put_noidle(d);
4068 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
4070 struct rtl8169_private *tp = netdev_priv(dev);
4072 if (!netif_running(dev))
4075 return phy_mii_ioctl(tp->phydev, ifr, cmd);
4078 static void rtl_init_mdio_ops(struct rtl8169_private *tp)
4080 struct mdio_ops *ops = &tp->mdio_ops;
4082 switch (tp->mac_version) {
4083 case RTL_GIGA_MAC_VER_27:
4084 ops->write = r8168dp_1_mdio_write;
4085 ops->read = r8168dp_1_mdio_read;
4087 case RTL_GIGA_MAC_VER_28:
4088 case RTL_GIGA_MAC_VER_31:
4089 ops->write = r8168dp_2_mdio_write;
4090 ops->read = r8168dp_2_mdio_read;
4092 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
4093 ops->write = r8168g_mdio_write;
4094 ops->read = r8168g_mdio_read;
4097 ops->write = r8169_mdio_write;
4098 ops->read = r8169_mdio_read;
4103 static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
4105 switch (tp->mac_version) {
4106 case RTL_GIGA_MAC_VER_25:
4107 case RTL_GIGA_MAC_VER_26:
4108 case RTL_GIGA_MAC_VER_29:
4109 case RTL_GIGA_MAC_VER_30:
4110 case RTL_GIGA_MAC_VER_32:
4111 case RTL_GIGA_MAC_VER_33:
4112 case RTL_GIGA_MAC_VER_34:
4113 case RTL_GIGA_MAC_VER_37 ... RTL_GIGA_MAC_VER_51:
4114 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) |
4115 AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
4122 static void r8168_pll_power_down(struct rtl8169_private *tp)
4124 if (r8168_check_dash(tp))
4127 if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
4128 tp->mac_version == RTL_GIGA_MAC_VER_33)
4129 rtl_ephy_write(tp, 0x19, 0xff64);
4131 if (device_may_wakeup(tp_to_dev(tp))) {
4132 phy_speed_down(tp->phydev, false);
4133 rtl_wol_suspend_quirk(tp);
4137 switch (tp->mac_version) {
4138 case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_33:
4139 case RTL_GIGA_MAC_VER_37:
4140 case RTL_GIGA_MAC_VER_39:
4141 case RTL_GIGA_MAC_VER_43:
4142 case RTL_GIGA_MAC_VER_44:
4143 case RTL_GIGA_MAC_VER_45:
4144 case RTL_GIGA_MAC_VER_46:
4145 case RTL_GIGA_MAC_VER_47:
4146 case RTL_GIGA_MAC_VER_48:
4147 case RTL_GIGA_MAC_VER_50:
4148 case RTL_GIGA_MAC_VER_51:
4149 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80);
4151 case RTL_GIGA_MAC_VER_40:
4152 case RTL_GIGA_MAC_VER_41:
4153 case RTL_GIGA_MAC_VER_49:
4154 rtl_eri_clear_bits(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000);
4155 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80);
4162 static void r8168_pll_power_up(struct rtl8169_private *tp)
4164 switch (tp->mac_version) {
4165 case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_33:
4166 case RTL_GIGA_MAC_VER_37:
4167 case RTL_GIGA_MAC_VER_39:
4168 case RTL_GIGA_MAC_VER_43:
4169 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0x80);
4171 case RTL_GIGA_MAC_VER_44:
4172 case RTL_GIGA_MAC_VER_45:
4173 case RTL_GIGA_MAC_VER_46:
4174 case RTL_GIGA_MAC_VER_47:
4175 case RTL_GIGA_MAC_VER_48:
4176 case RTL_GIGA_MAC_VER_50:
4177 case RTL_GIGA_MAC_VER_51:
4178 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0);
4180 case RTL_GIGA_MAC_VER_40:
4181 case RTL_GIGA_MAC_VER_41:
4182 case RTL_GIGA_MAC_VER_49:
4183 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0);
4184 rtl_eri_set_bits(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000);
4190 phy_resume(tp->phydev);
4191 /* give MAC/PHY some time to resume */
4195 static void rtl_pll_power_down(struct rtl8169_private *tp)
4197 switch (tp->mac_version) {
4198 case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_06:
4199 case RTL_GIGA_MAC_VER_13 ... RTL_GIGA_MAC_VER_15:
4202 r8168_pll_power_down(tp);
4206 static void rtl_pll_power_up(struct rtl8169_private *tp)
4208 switch (tp->mac_version) {
4209 case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_06:
4210 case RTL_GIGA_MAC_VER_13 ... RTL_GIGA_MAC_VER_15:
4213 r8168_pll_power_up(tp);
4217 static void rtl_init_rxcfg(struct rtl8169_private *tp)
4219 switch (tp->mac_version) {
4220 case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_06:
4221 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
4222 RTL_W32(tp, RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
4224 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
4225 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36:
4226 case RTL_GIGA_MAC_VER_38:
4227 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
4229 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
4230 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF);
4233 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_DMA_BURST);
4238 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
4240 tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0;
4243 static void rtl_hw_jumbo_enable(struct rtl8169_private *tp)
4245 if (tp->jumbo_ops.enable) {
4246 rtl_unlock_config_regs(tp);
4247 tp->jumbo_ops.enable(tp);
4248 rtl_lock_config_regs(tp);
4252 static void rtl_hw_jumbo_disable(struct rtl8169_private *tp)
4254 if (tp->jumbo_ops.disable) {
4255 rtl_unlock_config_regs(tp);
4256 tp->jumbo_ops.disable(tp);
4257 rtl_lock_config_regs(tp);
4261 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
4263 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
4264 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | Jumbo_En1);
4265 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_512B);
4268 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
4270 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
4271 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~Jumbo_En1);
4272 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4275 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
4277 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
4280 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
4282 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
4285 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
4287 RTL_W8(tp, MaxTxPacketSize, 0x3f);
4288 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
4289 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | 0x01);
4290 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_512B);
4293 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
4295 RTL_W8(tp, MaxTxPacketSize, 0x0c);
4296 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
4297 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~0x01);
4298 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4301 static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp)
4303 rtl_tx_performance_tweak(tp,
4304 PCI_EXP_DEVCTL_READRQ_512B | PCI_EXP_DEVCTL_NOSNOOP_EN);
4307 static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp)
4309 rtl_tx_performance_tweak(tp,
4310 PCI_EXP_DEVCTL_READRQ_4096B | PCI_EXP_DEVCTL_NOSNOOP_EN);
4313 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
4315 r8168b_0_hw_jumbo_enable(tp);
4317 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | (1 << 0));
4320 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
4322 r8168b_0_hw_jumbo_disable(tp);
4324 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0));
4327 static void rtl_init_jumbo_ops(struct rtl8169_private *tp)
4329 struct jumbo_ops *ops = &tp->jumbo_ops;
4331 switch (tp->mac_version) {
4332 case RTL_GIGA_MAC_VER_11:
4333 ops->disable = r8168b_0_hw_jumbo_disable;
4334 ops->enable = r8168b_0_hw_jumbo_enable;
4336 case RTL_GIGA_MAC_VER_12:
4337 case RTL_GIGA_MAC_VER_17:
4338 ops->disable = r8168b_1_hw_jumbo_disable;
4339 ops->enable = r8168b_1_hw_jumbo_enable;
4341 case RTL_GIGA_MAC_VER_18: /* Wild guess. Needs info from Realtek. */
4342 case RTL_GIGA_MAC_VER_19:
4343 case RTL_GIGA_MAC_VER_20:
4344 case RTL_GIGA_MAC_VER_21: /* Wild guess. Needs info from Realtek. */
4345 case RTL_GIGA_MAC_VER_22:
4346 case RTL_GIGA_MAC_VER_23:
4347 case RTL_GIGA_MAC_VER_24:
4348 case RTL_GIGA_MAC_VER_25:
4349 case RTL_GIGA_MAC_VER_26:
4350 ops->disable = r8168c_hw_jumbo_disable;
4351 ops->enable = r8168c_hw_jumbo_enable;
4353 case RTL_GIGA_MAC_VER_27:
4354 case RTL_GIGA_MAC_VER_28:
4355 ops->disable = r8168dp_hw_jumbo_disable;
4356 ops->enable = r8168dp_hw_jumbo_enable;
4358 case RTL_GIGA_MAC_VER_31: /* Wild guess. Needs info from Realtek. */
4359 case RTL_GIGA_MAC_VER_32:
4360 case RTL_GIGA_MAC_VER_33:
4361 case RTL_GIGA_MAC_VER_34:
4362 ops->disable = r8168e_hw_jumbo_disable;
4363 ops->enable = r8168e_hw_jumbo_enable;
4367 * No action needed for jumbo frames with 8169.
4368 * No jumbo for 810x at all.
4370 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
4372 ops->disable = NULL;
4378 DECLARE_RTL_COND(rtl_chipcmd_cond)
4380 return RTL_R8(tp, ChipCmd) & CmdReset;
4383 static void rtl_hw_reset(struct rtl8169_private *tp)
4385 RTL_W8(tp, ChipCmd, CmdReset);
4387 rtl_udelay_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100);
4390 static void rtl_request_firmware(struct rtl8169_private *tp)
4392 struct rtl_fw *rtl_fw;
4395 /* firmware loaded already or no firmware available */
4396 if (tp->rtl_fw || !tp->fw_name)
4399 rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
4403 rc = request_firmware(&rtl_fw->fw, tp->fw_name, tp_to_dev(tp));
4407 rc = rtl_check_firmware(tp, rtl_fw);
4409 goto err_release_firmware;
4411 tp->rtl_fw = rtl_fw;
4415 err_release_firmware:
4416 release_firmware(rtl_fw->fw);
4420 netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n",
4424 static void rtl_rx_close(struct rtl8169_private *tp)
4426 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
4429 DECLARE_RTL_COND(rtl_npq_cond)
4431 return RTL_R8(tp, TxPoll) & NPQ;
4434 DECLARE_RTL_COND(rtl_txcfg_empty_cond)
4436 return RTL_R32(tp, TxConfig) & TXCFG_EMPTY;
4439 static void rtl8169_hw_reset(struct rtl8169_private *tp)
4441 /* Disable interrupts */
4442 rtl8169_irq_mask_and_ack(tp);
4446 switch (tp->mac_version) {
4447 case RTL_GIGA_MAC_VER_27:
4448 case RTL_GIGA_MAC_VER_28:
4449 case RTL_GIGA_MAC_VER_31:
4450 rtl_udelay_loop_wait_low(tp, &rtl_npq_cond, 20, 42*42);
4452 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
4453 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
4454 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
4455 rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);
4458 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
4466 static void rtl_set_tx_config_registers(struct rtl8169_private *tp)
4468 u32 val = TX_DMA_BURST << TxDMAShift |
4469 InterFrameGap << TxInterFrameGapShift;
4471 if (tp->mac_version >= RTL_GIGA_MAC_VER_34 &&
4472 tp->mac_version != RTL_GIGA_MAC_VER_39)
4473 val |= TXCFG_AUTO_FIFO;
4475 RTL_W32(tp, TxConfig, val);
4478 static void rtl_set_rx_max_size(struct rtl8169_private *tp)
4480 /* Low hurts. Let's disable the filtering. */
4481 RTL_W16(tp, RxMaxSize, R8169_RX_BUF_SIZE + 1);
4484 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp)
4487 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
4488 * register to be written before TxDescAddrLow to work.
4489 * Switching from MMIO to I/O access fixes the issue as well.
4491 RTL_W32(tp, TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
4492 RTL_W32(tp, TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
4493 RTL_W32(tp, RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
4494 RTL_W32(tp, RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
4497 static void rtl8169_set_magic_reg(struct rtl8169_private *tp, unsigned mac_version)
4501 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
4503 else if (tp->mac_version == RTL_GIGA_MAC_VER_06)
4508 if (RTL_R8(tp, Config2) & PCI_Clock_66MHz)
4511 RTL_W32(tp, 0x7c, val);
4514 static void rtl_set_rx_mode(struct net_device *dev)
4516 struct rtl8169_private *tp = netdev_priv(dev);
4517 u32 mc_filter[2]; /* Multicast hash filter */
4521 if (dev->flags & IFF_PROMISC) {
4522 /* Unconditionally log net taps. */
4523 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
4525 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
4527 mc_filter[1] = mc_filter[0] = 0xffffffff;
4528 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
4529 (dev->flags & IFF_ALLMULTI)) {
4530 /* Too many to filter perfectly -- accept all multicasts. */
4531 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
4532 mc_filter[1] = mc_filter[0] = 0xffffffff;
4534 struct netdev_hw_addr *ha;
4536 rx_mode = AcceptBroadcast | AcceptMyPhys;
4537 mc_filter[1] = mc_filter[0] = 0;
4538 netdev_for_each_mc_addr(ha, dev) {
4539 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
4540 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
4541 rx_mode |= AcceptMulticast;
4545 if (dev->features & NETIF_F_RXALL)
4546 rx_mode |= (AcceptErr | AcceptRunt);
4548 tmp = (RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK) | rx_mode;
4550 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
4551 u32 data = mc_filter[0];
4553 mc_filter[0] = swab32(mc_filter[1]);
4554 mc_filter[1] = swab32(data);
4557 if (tp->mac_version == RTL_GIGA_MAC_VER_35)
4558 mc_filter[1] = mc_filter[0] = 0xffffffff;
4560 RTL_W32(tp, MAR0 + 4, mc_filter[1]);
4561 RTL_W32(tp, MAR0 + 0, mc_filter[0]);
4563 RTL_W32(tp, RxConfig, tmp);
4566 static void rtl_hw_start(struct rtl8169_private *tp)
4568 rtl_unlock_config_regs(tp);
4572 rtl_set_rx_max_size(tp);
4573 rtl_set_rx_tx_desc_registers(tp);
4574 rtl_lock_config_regs(tp);
4576 /* disable interrupt coalescing */
4577 RTL_W16(tp, IntrMitigate, 0x0000);
4578 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
4579 RTL_R8(tp, IntrMask);
4580 RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb);
4582 rtl_set_tx_config_registers(tp);
4584 rtl_set_rx_mode(tp->dev);
4585 /* no early-rx interrupts */
4586 RTL_W16(tp, MultiIntr, RTL_R16(tp, MultiIntr) & 0xf000);
4590 static void rtl_hw_start_8169(struct rtl8169_private *tp)
4592 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
4593 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4595 RTL_W8(tp, EarlyTxThres, NoEarlyTx);
4597 tp->cp_cmd |= PCIMulRW;
4599 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4600 tp->mac_version == RTL_GIGA_MAC_VER_03) {
4601 netif_dbg(tp, drv, tp->dev,
4602 "Set MAC Reg C+CR Offset 0xe0. Bit 3 and Bit 14 MUST be 1\n");
4603 tp->cp_cmd |= (1 << 14);
4606 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4608 rtl8169_set_magic_reg(tp, tp->mac_version);
4610 RTL_W32(tp, RxMissed, 0);
4613 DECLARE_RTL_COND(rtl_csiar_cond)
4615 return RTL_R32(tp, CSIAR) & CSIAR_FLAG;
4618 static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)
4620 u32 func = PCI_FUNC(tp->pci_dev->devfn);
4622 RTL_W32(tp, CSIDR, value);
4623 RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
4624 CSIAR_BYTE_ENABLE | func << 16);
4626 rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
4629 static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)
4631 u32 func = PCI_FUNC(tp->pci_dev->devfn);
4633 RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) | func << 16 |
4636 return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
4637 RTL_R32(tp, CSIDR) : ~0;
4640 static void rtl_csi_access_enable(struct rtl8169_private *tp, u8 val)
4642 struct pci_dev *pdev = tp->pci_dev;
4645 /* According to Realtek the value at config space address 0x070f
4646 * controls the L0s/L1 entrance latency. We try standard ECAM access
4647 * first and if it fails fall back to CSI.
4649 if (pdev->cfg_size > 0x070f &&
4650 pci_write_config_byte(pdev, 0x070f, val) == PCIBIOS_SUCCESSFUL)
4653 netdev_notice_once(tp->dev,
4654 "No native access to PCI extended config space, falling back to CSI\n");
4655 csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff;
4656 rtl_csi_write(tp, 0x070c, csi | val << 24);
4659 static void rtl_set_def_aspm_entry_latency(struct rtl8169_private *tp)
4661 rtl_csi_access_enable(tp, 0x27);
4665 unsigned int offset;
4670 static void __rtl_ephy_init(struct rtl8169_private *tp,
4671 const struct ephy_info *e, int len)
4676 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits;
4677 rtl_ephy_write(tp, e->offset, w);
4682 #define rtl_ephy_init(tp, a) __rtl_ephy_init(tp, a, ARRAY_SIZE(a))
4684 static void rtl_disable_clock_request(struct rtl8169_private *tp)
4686 pcie_capability_clear_word(tp->pci_dev, PCI_EXP_LNKCTL,
4687 PCI_EXP_LNKCTL_CLKREQ_EN);
4690 static void rtl_enable_clock_request(struct rtl8169_private *tp)
4692 pcie_capability_set_word(tp->pci_dev, PCI_EXP_LNKCTL,
4693 PCI_EXP_LNKCTL_CLKREQ_EN);
4696 static void rtl_pcie_state_l2l3_disable(struct rtl8169_private *tp)
4698 /* work around an issue when PCI reset occurs during L2/L3 state */
4699 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Rdy_to_L23);
4702 static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable)
4705 RTL_W8(tp, Config5, RTL_R8(tp, Config5) | ASPM_en);
4706 RTL_W8(tp, Config2, RTL_R8(tp, Config2) | ClkReqEn);
4708 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
4709 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
4715 static void rtl_set_fifo_size(struct rtl8169_private *tp, u16 rx_stat,
4716 u16 tx_stat, u16 rx_dyn, u16 tx_dyn)
4718 /* Usage of dynamic vs. static FIFO is controlled by bit
4719 * TXCFG_AUTO_FIFO. Exact meaning of FIFO values isn't known.
4721 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, (rx_stat << 16) | rx_dyn);
4722 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, (tx_stat << 16) | tx_dyn);
4725 static void rtl8168g_set_pause_thresholds(struct rtl8169_private *tp,
4728 /* FIFO thresholds for pause flow control */
4729 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, low);
4730 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, high);
4733 static void rtl_hw_start_8168bb(struct rtl8169_private *tp)
4735 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4737 tp->cp_cmd &= CPCMD_QUIRK_MASK;
4738 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4740 if (tp->dev->mtu <= ETH_DATA_LEN) {
4741 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B |
4742 PCI_EXP_DEVCTL_NOSNOOP_EN);
4746 static void rtl_hw_start_8168bef(struct rtl8169_private *tp)
4748 rtl_hw_start_8168bb(tp);
4750 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4752 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0));
4755 static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)
4757 RTL_W8(tp, Config1, RTL_R8(tp, Config1) | Speed_down);
4759 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4761 if (tp->dev->mtu <= ETH_DATA_LEN)
4762 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4764 rtl_disable_clock_request(tp);
4766 tp->cp_cmd &= CPCMD_QUIRK_MASK;
4767 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4770 static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp)
4772 static const struct ephy_info e_info_8168cp[] = {
4773 { 0x01, 0, 0x0001 },
4774 { 0x02, 0x0800, 0x1000 },
4775 { 0x03, 0, 0x0042 },
4776 { 0x06, 0x0080, 0x0000 },
4780 rtl_set_def_aspm_entry_latency(tp);
4782 rtl_ephy_init(tp, e_info_8168cp);
4784 __rtl_hw_start_8168cp(tp);
4787 static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)
4789 rtl_set_def_aspm_entry_latency(tp);
4791 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4793 if (tp->dev->mtu <= ETH_DATA_LEN)
4794 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4796 tp->cp_cmd &= CPCMD_QUIRK_MASK;
4797 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4800 static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)
4802 rtl_set_def_aspm_entry_latency(tp);
4804 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4807 RTL_W8(tp, DBG_REG, 0x20);
4809 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4811 if (tp->dev->mtu <= ETH_DATA_LEN)
4812 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4814 tp->cp_cmd &= CPCMD_QUIRK_MASK;
4815 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4818 static void rtl_hw_start_8168c_1(struct rtl8169_private *tp)
4820 static const struct ephy_info e_info_8168c_1[] = {
4821 { 0x02, 0x0800, 0x1000 },
4822 { 0x03, 0, 0x0002 },
4823 { 0x06, 0x0080, 0x0000 }
4826 rtl_set_def_aspm_entry_latency(tp);
4828 RTL_W8(tp, DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
4830 rtl_ephy_init(tp, e_info_8168c_1);
4832 __rtl_hw_start_8168cp(tp);
4835 static void rtl_hw_start_8168c_2(struct rtl8169_private *tp)
4837 static const struct ephy_info e_info_8168c_2[] = {
4838 { 0x01, 0, 0x0001 },
4839 { 0x03, 0x0400, 0x0220 }
4842 rtl_set_def_aspm_entry_latency(tp);
4844 rtl_ephy_init(tp, e_info_8168c_2);
4846 __rtl_hw_start_8168cp(tp);
4849 static void rtl_hw_start_8168c_3(struct rtl8169_private *tp)
4851 rtl_hw_start_8168c_2(tp);
4854 static void rtl_hw_start_8168c_4(struct rtl8169_private *tp)
4856 rtl_set_def_aspm_entry_latency(tp);
4858 __rtl_hw_start_8168cp(tp);
4861 static void rtl_hw_start_8168d(struct rtl8169_private *tp)
4863 rtl_set_def_aspm_entry_latency(tp);
4865 rtl_disable_clock_request(tp);
4867 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4869 if (tp->dev->mtu <= ETH_DATA_LEN)
4870 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4872 tp->cp_cmd &= CPCMD_QUIRK_MASK;
4873 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4876 static void rtl_hw_start_8168dp(struct rtl8169_private *tp)
4878 rtl_set_def_aspm_entry_latency(tp);
4880 if (tp->dev->mtu <= ETH_DATA_LEN)
4881 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4883 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4885 rtl_disable_clock_request(tp);
4888 static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
4890 static const struct ephy_info e_info_8168d_4[] = {
4891 { 0x0b, 0x0000, 0x0048 },
4892 { 0x19, 0x0020, 0x0050 },
4893 { 0x0c, 0x0100, 0x0020 }
4896 rtl_set_def_aspm_entry_latency(tp);
4898 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4900 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4902 rtl_ephy_init(tp, e_info_8168d_4);
4904 rtl_enable_clock_request(tp);
4907 static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)
4909 static const struct ephy_info e_info_8168e_1[] = {
4910 { 0x00, 0x0200, 0x0100 },
4911 { 0x00, 0x0000, 0x0004 },
4912 { 0x06, 0x0002, 0x0001 },
4913 { 0x06, 0x0000, 0x0030 },
4914 { 0x07, 0x0000, 0x2000 },
4915 { 0x00, 0x0000, 0x0020 },
4916 { 0x03, 0x5800, 0x2000 },
4917 { 0x03, 0x0000, 0x0001 },
4918 { 0x01, 0x0800, 0x1000 },
4919 { 0x07, 0x0000, 0x4000 },
4920 { 0x1e, 0x0000, 0x2000 },
4921 { 0x19, 0xffff, 0xfe6c },
4922 { 0x0a, 0x0000, 0x0040 }
4925 rtl_set_def_aspm_entry_latency(tp);
4927 rtl_ephy_init(tp, e_info_8168e_1);
4929 if (tp->dev->mtu <= ETH_DATA_LEN)
4930 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4932 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4934 rtl_disable_clock_request(tp);
4936 /* Reset tx FIFO pointer */
4937 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | TXPLA_RST);
4938 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~TXPLA_RST);
4940 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
4943 static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
4945 static const struct ephy_info e_info_8168e_2[] = {
4946 { 0x09, 0x0000, 0x0080 },
4947 { 0x19, 0x0000, 0x0224 }
4950 rtl_set_def_aspm_entry_latency(tp);
4952 rtl_ephy_init(tp, e_info_8168e_2);
4954 if (tp->dev->mtu <= ETH_DATA_LEN)
4955 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4957 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
4958 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
4959 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06);
4960 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050);
4961 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060);
4962 rtl_eri_set_bits(tp, 0x1b0, ERIAR_MASK_0001, BIT(4));
4963 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00);
4965 RTL_W8(tp, MaxTxPacketSize, EarlySize);
4967 rtl_disable_clock_request(tp);
4969 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
4971 rtl8168_config_eee_mac(tp);
4973 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
4974 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
4975 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
4977 rtl_hw_aspm_clkreq_enable(tp, true);
4980 static void rtl_hw_start_8168f(struct rtl8169_private *tp)
4982 rtl_set_def_aspm_entry_latency(tp);
4984 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4986 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
4987 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
4988 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06);
4989 rtl_reset_packet_filter(tp);
4990 rtl_eri_set_bits(tp, 0x1b0, ERIAR_MASK_0001, BIT(4));
4991 rtl_eri_set_bits(tp, 0x1d0, ERIAR_MASK_0001, BIT(4));
4992 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050);
4993 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060);
4995 RTL_W8(tp, MaxTxPacketSize, EarlySize);
4997 rtl_disable_clock_request(tp);
4999 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
5000 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
5001 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
5002 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
5004 rtl8168_config_eee_mac(tp);
5007 static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
5009 static const struct ephy_info e_info_8168f_1[] = {
5010 { 0x06, 0x00c0, 0x0020 },
5011 { 0x08, 0x0001, 0x0002 },
5012 { 0x09, 0x0000, 0x0080 },
5013 { 0x19, 0x0000, 0x0224 }
5016 rtl_hw_start_8168f(tp);
5018 rtl_ephy_init(tp, e_info_8168f_1);
5020 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00);
5023 static void rtl_hw_start_8411(struct rtl8169_private *tp)
5025 static const struct ephy_info e_info_8168f_1[] = {
5026 { 0x06, 0x00c0, 0x0020 },
5027 { 0x0f, 0xffff, 0x5200 },
5028 { 0x1e, 0x0000, 0x4000 },
5029 { 0x19, 0x0000, 0x0224 }
5032 rtl_hw_start_8168f(tp);
5033 rtl_pcie_state_l2l3_disable(tp);
5035 rtl_ephy_init(tp, e_info_8168f_1);
5037 rtl_eri_set_bits(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00);
5040 static void rtl_hw_start_8168g(struct rtl8169_private *tp)
5042 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
5043 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48);
5045 rtl_set_def_aspm_entry_latency(tp);
5047 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5049 rtl_reset_packet_filter(tp);
5050 rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f);
5052 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
5053 RTL_W8(tp, MaxTxPacketSize, EarlySize);
5055 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
5056 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
5058 rtl8168_config_eee_mac(tp);
5060 rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06);
5061 rtl_eri_clear_bits(tp, 0x1b0, ERIAR_MASK_0011, BIT(12));
5063 rtl_pcie_state_l2l3_disable(tp);
5066 static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
5068 static const struct ephy_info e_info_8168g_1[] = {
5069 { 0x00, 0x0000, 0x0008 },
5070 { 0x0c, 0x37d0, 0x0820 },
5071 { 0x1e, 0x0000, 0x0001 },
5072 { 0x19, 0x8000, 0x0000 }
5075 rtl_hw_start_8168g(tp);
5077 /* disable aspm and clock request before access ephy */
5078 rtl_hw_aspm_clkreq_enable(tp, false);
5079 rtl_ephy_init(tp, e_info_8168g_1);
5080 rtl_hw_aspm_clkreq_enable(tp, true);
5083 static void rtl_hw_start_8168g_2(struct rtl8169_private *tp)
5085 static const struct ephy_info e_info_8168g_2[] = {
5086 { 0x00, 0x0000, 0x0008 },
5087 { 0x0c, 0x3df0, 0x0200 },
5088 { 0x19, 0xffff, 0xfc00 },
5089 { 0x1e, 0xffff, 0x20eb }
5092 rtl_hw_start_8168g(tp);
5094 /* disable aspm and clock request before access ephy */
5095 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
5096 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
5097 rtl_ephy_init(tp, e_info_8168g_2);
5100 static void rtl_hw_start_8411_2(struct rtl8169_private *tp)
5102 static const struct ephy_info e_info_8411_2[] = {
5103 { 0x00, 0x0000, 0x0008 },
5104 { 0x0c, 0x3df0, 0x0200 },
5105 { 0x0f, 0xffff, 0x5200 },
5106 { 0x19, 0x0020, 0x0000 },
5107 { 0x1e, 0x0000, 0x2000 }
5110 rtl_hw_start_8168g(tp);
5112 /* disable aspm and clock request before access ephy */
5113 rtl_hw_aspm_clkreq_enable(tp, false);
5114 rtl_ephy_init(tp, e_info_8411_2);
5115 rtl_hw_aspm_clkreq_enable(tp, true);
5118 static void rtl_hw_start_8168h_1(struct rtl8169_private *tp)
5122 static const struct ephy_info e_info_8168h_1[] = {
5123 { 0x1e, 0x0800, 0x0001 },
5124 { 0x1d, 0x0000, 0x0800 },
5125 { 0x05, 0xffff, 0x2089 },
5126 { 0x06, 0xffff, 0x5881 },
5127 { 0x04, 0xffff, 0x154a },
5128 { 0x01, 0xffff, 0x068b }
5131 /* disable aspm and clock request before access ephy */
5132 rtl_hw_aspm_clkreq_enable(tp, false);
5133 rtl_ephy_init(tp, e_info_8168h_1);
5135 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
5136 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48);
5138 rtl_set_def_aspm_entry_latency(tp);
5140 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5142 rtl_reset_packet_filter(tp);
5144 rtl_eri_set_bits(tp, 0xdc, ERIAR_MASK_1111, BIT(4));
5146 rtl_eri_set_bits(tp, 0xd4, ERIAR_MASK_1111, 0x1f00);
5148 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);
5150 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
5151 RTL_W8(tp, MaxTxPacketSize, EarlySize);
5153 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
5154 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
5156 rtl8168_config_eee_mac(tp);
5158 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5159 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
5161 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
5163 rtl_eri_clear_bits(tp, 0x1b0, ERIAR_MASK_0011, BIT(12));
5165 rtl_pcie_state_l2l3_disable(tp);
5167 rtl_writephy(tp, 0x1f, 0x0c42);
5168 rg_saw_cnt = (rtl_readphy(tp, 0x13) & 0x3fff);
5169 rtl_writephy(tp, 0x1f, 0x0000);
5170 if (rg_saw_cnt > 0) {
5173 sw_cnt_1ms_ini = 16000000/rg_saw_cnt;
5174 sw_cnt_1ms_ini &= 0x0fff;
5175 data = r8168_mac_ocp_read(tp, 0xd412);
5177 data |= sw_cnt_1ms_ini;
5178 r8168_mac_ocp_write(tp, 0xd412, data);
5181 data = r8168_mac_ocp_read(tp, 0xe056);
5184 r8168_mac_ocp_write(tp, 0xe056, data);
5186 data = r8168_mac_ocp_read(tp, 0xe052);
5189 r8168_mac_ocp_write(tp, 0xe052, data);
5191 data = r8168_mac_ocp_read(tp, 0xe0d6);
5194 r8168_mac_ocp_write(tp, 0xe0d6, data);
5196 data = r8168_mac_ocp_read(tp, 0xd420);
5199 r8168_mac_ocp_write(tp, 0xd420, data);
5201 r8168_mac_ocp_write(tp, 0xe63e, 0x0001);
5202 r8168_mac_ocp_write(tp, 0xe63e, 0x0000);
5203 r8168_mac_ocp_write(tp, 0xc094, 0x0000);
5204 r8168_mac_ocp_write(tp, 0xc09e, 0x0000);
5206 rtl_hw_aspm_clkreq_enable(tp, true);
5209 static void rtl_hw_start_8168ep(struct rtl8169_private *tp)
5211 rtl8168ep_stop_cmac(tp);
5213 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
5214 rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f);
5216 rtl_set_def_aspm_entry_latency(tp);
5218 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5220 rtl_reset_packet_filter(tp);
5222 rtl_eri_set_bits(tp, 0xd4, ERIAR_MASK_1111, 0x1f80);
5224 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);
5226 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
5227 RTL_W8(tp, MaxTxPacketSize, EarlySize);
5229 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
5230 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
5232 rtl8168_config_eee_mac(tp);
5234 rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06);
5236 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
5238 rtl_pcie_state_l2l3_disable(tp);
5241 static void rtl_hw_start_8168ep_1(struct rtl8169_private *tp)
5243 static const struct ephy_info e_info_8168ep_1[] = {
5244 { 0x00, 0xffff, 0x10ab },
5245 { 0x06, 0xffff, 0xf030 },
5246 { 0x08, 0xffff, 0x2006 },
5247 { 0x0d, 0xffff, 0x1666 },
5248 { 0x0c, 0x3ff0, 0x0000 }
5251 /* disable aspm and clock request before access ephy */
5252 rtl_hw_aspm_clkreq_enable(tp, false);
5253 rtl_ephy_init(tp, e_info_8168ep_1);
5255 rtl_hw_start_8168ep(tp);
5257 rtl_hw_aspm_clkreq_enable(tp, true);
5260 static void rtl_hw_start_8168ep_2(struct rtl8169_private *tp)
5262 static const struct ephy_info e_info_8168ep_2[] = {
5263 { 0x00, 0xffff, 0x10a3 },
5264 { 0x19, 0xffff, 0xfc00 },
5265 { 0x1e, 0xffff, 0x20ea }
5268 /* disable aspm and clock request before access ephy */
5269 rtl_hw_aspm_clkreq_enable(tp, false);
5270 rtl_ephy_init(tp, e_info_8168ep_2);
5272 rtl_hw_start_8168ep(tp);
5274 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5275 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
5277 rtl_hw_aspm_clkreq_enable(tp, true);
5280 static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp)
5283 static const struct ephy_info e_info_8168ep_3[] = {
5284 { 0x00, 0xffff, 0x10a3 },
5285 { 0x19, 0xffff, 0x7c00 },
5286 { 0x1e, 0xffff, 0x20eb },
5287 { 0x0d, 0xffff, 0x1666 }
5290 /* disable aspm and clock request before access ephy */
5291 rtl_hw_aspm_clkreq_enable(tp, false);
5292 rtl_ephy_init(tp, e_info_8168ep_3);
5294 rtl_hw_start_8168ep(tp);
5296 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5297 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
5299 data = r8168_mac_ocp_read(tp, 0xd3e2);
5302 r8168_mac_ocp_write(tp, 0xd3e2, data);
5304 data = r8168_mac_ocp_read(tp, 0xd3e4);
5306 r8168_mac_ocp_write(tp, 0xd3e4, data);
5308 data = r8168_mac_ocp_read(tp, 0xe860);
5310 r8168_mac_ocp_write(tp, 0xe860, data);
5312 rtl_hw_aspm_clkreq_enable(tp, true);
5315 static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)
5317 static const struct ephy_info e_info_8102e_1[] = {
5318 { 0x01, 0, 0x6e65 },
5319 { 0x02, 0, 0x091f },
5320 { 0x03, 0, 0xc2f9 },
5321 { 0x06, 0, 0xafb5 },
5322 { 0x07, 0, 0x0e00 },
5323 { 0x19, 0, 0xec80 },
5324 { 0x01, 0, 0x2e65 },
5329 rtl_set_def_aspm_entry_latency(tp);
5331 RTL_W8(tp, DBG_REG, FIX_NAK_1);
5333 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5336 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
5337 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
5339 cfg1 = RTL_R8(tp, Config1);
5340 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
5341 RTL_W8(tp, Config1, cfg1 & ~LEDS0);
5343 rtl_ephy_init(tp, e_info_8102e_1);
5346 static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)
5348 rtl_set_def_aspm_entry_latency(tp);
5350 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5352 RTL_W8(tp, Config1, MEMMAP | IOMAP | VPD | PMEnable);
5353 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
5356 static void rtl_hw_start_8102e_3(struct rtl8169_private *tp)
5358 rtl_hw_start_8102e_2(tp);
5360 rtl_ephy_write(tp, 0x03, 0xc2f9);
5363 static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)
5365 static const struct ephy_info e_info_8105e_1[] = {
5366 { 0x07, 0, 0x4000 },
5367 { 0x19, 0, 0x0200 },
5368 { 0x19, 0, 0x0020 },
5369 { 0x1e, 0, 0x2000 },
5370 { 0x03, 0, 0x0001 },
5371 { 0x19, 0, 0x0100 },
5372 { 0x19, 0, 0x0004 },
5376 /* Force LAN exit from ASPM if Rx/Tx are not idle */
5377 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
5379 /* Disable Early Tally Counter */
5380 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) & ~0x010000);
5382 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
5383 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
5385 rtl_ephy_init(tp, e_info_8105e_1);
5387 rtl_pcie_state_l2l3_disable(tp);
5390 static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)
5392 rtl_hw_start_8105e_1(tp);
5393 rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000);
5396 static void rtl_hw_start_8402(struct rtl8169_private *tp)
5398 static const struct ephy_info e_info_8402[] = {
5399 { 0x19, 0xffff, 0xff64 },
5403 rtl_set_def_aspm_entry_latency(tp);
5405 /* Force LAN exit from ASPM if Rx/Tx are not idle */
5406 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
5408 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
5410 rtl_ephy_init(tp, e_info_8402);
5412 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5414 rtl_set_fifo_size(tp, 0x00, 0x00, 0x02, 0x06);
5415 rtl_reset_packet_filter(tp);
5416 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
5417 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
5418 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0e00, 0xff00);
5420 rtl_pcie_state_l2l3_disable(tp);
5423 static void rtl_hw_start_8106(struct rtl8169_private *tp)
5425 rtl_hw_aspm_clkreq_enable(tp, false);
5427 /* Force LAN exit from ASPM if Rx/Tx are not idle */
5428 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
5430 RTL_W32(tp, MISC, (RTL_R32(tp, MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);
5431 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
5432 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5434 rtl_pcie_state_l2l3_disable(tp);
5435 rtl_hw_aspm_clkreq_enable(tp, true);
5438 static void rtl_hw_config(struct rtl8169_private *tp)
5440 static const rtl_generic_fct hw_configs[] = {
5441 [RTL_GIGA_MAC_VER_07] = rtl_hw_start_8102e_1,
5442 [RTL_GIGA_MAC_VER_08] = rtl_hw_start_8102e_3,
5443 [RTL_GIGA_MAC_VER_09] = rtl_hw_start_8102e_2,
5444 [RTL_GIGA_MAC_VER_10] = NULL,
5445 [RTL_GIGA_MAC_VER_11] = rtl_hw_start_8168bb,
5446 [RTL_GIGA_MAC_VER_12] = rtl_hw_start_8168bef,
5447 [RTL_GIGA_MAC_VER_13] = NULL,
5448 [RTL_GIGA_MAC_VER_14] = NULL,
5449 [RTL_GIGA_MAC_VER_15] = NULL,
5450 [RTL_GIGA_MAC_VER_16] = NULL,
5451 [RTL_GIGA_MAC_VER_17] = rtl_hw_start_8168bef,
5452 [RTL_GIGA_MAC_VER_18] = rtl_hw_start_8168cp_1,
5453 [RTL_GIGA_MAC_VER_19] = rtl_hw_start_8168c_1,
5454 [RTL_GIGA_MAC_VER_20] = rtl_hw_start_8168c_2,
5455 [RTL_GIGA_MAC_VER_21] = rtl_hw_start_8168c_3,
5456 [RTL_GIGA_MAC_VER_22] = rtl_hw_start_8168c_4,
5457 [RTL_GIGA_MAC_VER_23] = rtl_hw_start_8168cp_2,
5458 [RTL_GIGA_MAC_VER_24] = rtl_hw_start_8168cp_3,
5459 [RTL_GIGA_MAC_VER_25] = rtl_hw_start_8168d,
5460 [RTL_GIGA_MAC_VER_26] = rtl_hw_start_8168d,
5461 [RTL_GIGA_MAC_VER_27] = rtl_hw_start_8168d,
5462 [RTL_GIGA_MAC_VER_28] = rtl_hw_start_8168d_4,
5463 [RTL_GIGA_MAC_VER_29] = rtl_hw_start_8105e_1,
5464 [RTL_GIGA_MAC_VER_30] = rtl_hw_start_8105e_2,
5465 [RTL_GIGA_MAC_VER_31] = rtl_hw_start_8168dp,
5466 [RTL_GIGA_MAC_VER_32] = rtl_hw_start_8168e_1,
5467 [RTL_GIGA_MAC_VER_33] = rtl_hw_start_8168e_1,
5468 [RTL_GIGA_MAC_VER_34] = rtl_hw_start_8168e_2,
5469 [RTL_GIGA_MAC_VER_35] = rtl_hw_start_8168f_1,
5470 [RTL_GIGA_MAC_VER_36] = rtl_hw_start_8168f_1,
5471 [RTL_GIGA_MAC_VER_37] = rtl_hw_start_8402,
5472 [RTL_GIGA_MAC_VER_38] = rtl_hw_start_8411,
5473 [RTL_GIGA_MAC_VER_39] = rtl_hw_start_8106,
5474 [RTL_GIGA_MAC_VER_40] = rtl_hw_start_8168g_1,
5475 [RTL_GIGA_MAC_VER_41] = rtl_hw_start_8168g_1,
5476 [RTL_GIGA_MAC_VER_42] = rtl_hw_start_8168g_2,
5477 [RTL_GIGA_MAC_VER_43] = rtl_hw_start_8168g_2,
5478 [RTL_GIGA_MAC_VER_44] = rtl_hw_start_8411_2,
5479 [RTL_GIGA_MAC_VER_45] = rtl_hw_start_8168h_1,
5480 [RTL_GIGA_MAC_VER_46] = rtl_hw_start_8168h_1,
5481 [RTL_GIGA_MAC_VER_47] = rtl_hw_start_8168h_1,
5482 [RTL_GIGA_MAC_VER_48] = rtl_hw_start_8168h_1,
5483 [RTL_GIGA_MAC_VER_49] = rtl_hw_start_8168ep_1,
5484 [RTL_GIGA_MAC_VER_50] = rtl_hw_start_8168ep_2,
5485 [RTL_GIGA_MAC_VER_51] = rtl_hw_start_8168ep_3,
5488 if (hw_configs[tp->mac_version])
5489 hw_configs[tp->mac_version](tp);
5492 static void rtl_hw_start_8168(struct rtl8169_private *tp)
5494 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
5496 /* Workaround for RxFIFO overflow. */
5497 if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
5498 tp->irq_mask |= RxFIFOOver;
5499 tp->irq_mask &= ~RxOverflow;
5505 static void rtl_hw_start_8101(struct rtl8169_private *tp)
5507 if (tp->mac_version >= RTL_GIGA_MAC_VER_30)
5508 tp->irq_mask &= ~RxFIFOOver;
5510 if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
5511 tp->mac_version == RTL_GIGA_MAC_VER_16)
5512 pcie_capability_set_word(tp->pci_dev, PCI_EXP_DEVCTL,
5513 PCI_EXP_DEVCTL_NOSNOOP_EN);
5515 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
5517 tp->cp_cmd &= CPCMD_QUIRK_MASK;
5518 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
5523 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
5525 struct rtl8169_private *tp = netdev_priv(dev);
5527 if (new_mtu > ETH_DATA_LEN)
5528 rtl_hw_jumbo_enable(tp);
5530 rtl_hw_jumbo_disable(tp);
5533 netdev_update_features(dev);
5538 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
5540 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
5541 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
5544 static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
5545 void **data_buff, struct RxDesc *desc)
5547 dma_unmap_single(tp_to_dev(tp), le64_to_cpu(desc->addr),
5548 R8169_RX_BUF_SIZE, DMA_FROM_DEVICE);
5552 rtl8169_make_unusable_by_asic(desc);
5555 static inline void rtl8169_mark_to_asic(struct RxDesc *desc)
5557 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
5559 /* Force memory writes to complete before releasing descriptor */
5562 desc->opts1 = cpu_to_le32(DescOwn | eor | R8169_RX_BUF_SIZE);
5565 static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
5566 struct RxDesc *desc)
5570 struct device *d = tp_to_dev(tp);
5571 int node = dev_to_node(d);
5573 data = kmalloc_node(R8169_RX_BUF_SIZE, GFP_KERNEL, node);
5577 /* Memory should be properly aligned, but better check. */
5578 if (!IS_ALIGNED((unsigned long)data, 8)) {
5579 netdev_err_once(tp->dev, "RX buffer not 8-byte-aligned\n");
5583 mapping = dma_map_single(d, data, R8169_RX_BUF_SIZE, DMA_FROM_DEVICE);
5584 if (unlikely(dma_mapping_error(d, mapping))) {
5585 if (net_ratelimit())
5586 netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
5590 desc->addr = cpu_to_le64(mapping);
5591 rtl8169_mark_to_asic(desc);
5599 static void rtl8169_rx_clear(struct rtl8169_private *tp)
5603 for (i = 0; i < NUM_RX_DESC; i++) {
5604 if (tp->Rx_databuff[i]) {
5605 rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
5606 tp->RxDescArray + i);
5611 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
5613 desc->opts1 |= cpu_to_le32(RingEnd);
5616 static int rtl8169_rx_fill(struct rtl8169_private *tp)
5620 for (i = 0; i < NUM_RX_DESC; i++) {
5623 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
5625 rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
5628 tp->Rx_databuff[i] = data;
5631 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
5635 rtl8169_rx_clear(tp);
5639 static int rtl8169_init_ring(struct rtl8169_private *tp)
5641 rtl8169_init_ring_indexes(tp);
5643 memset(tp->tx_skb, 0, sizeof(tp->tx_skb));
5644 memset(tp->Rx_databuff, 0, sizeof(tp->Rx_databuff));
5646 return rtl8169_rx_fill(tp);
5649 static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
5650 struct TxDesc *desc)
5652 unsigned int len = tx_skb->len;
5654 dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
5662 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
5667 for (i = 0; i < n; i++) {
5668 unsigned int entry = (start + i) % NUM_TX_DESC;
5669 struct ring_info *tx_skb = tp->tx_skb + entry;
5670 unsigned int len = tx_skb->len;
5673 struct sk_buff *skb = tx_skb->skb;
5675 rtl8169_unmap_tx_skb(tp_to_dev(tp), tx_skb,
5676 tp->TxDescArray + entry);
5678 dev_consume_skb_any(skb);
5685 static void rtl8169_tx_clear(struct rtl8169_private *tp)
5687 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
5688 tp->cur_tx = tp->dirty_tx = 0;
5689 netdev_reset_queue(tp->dev);
5692 static void rtl_reset_work(struct rtl8169_private *tp)
5694 struct net_device *dev = tp->dev;
5697 napi_disable(&tp->napi);
5698 netif_stop_queue(dev);
5701 rtl8169_hw_reset(tp);
5703 for (i = 0; i < NUM_RX_DESC; i++)
5704 rtl8169_mark_to_asic(tp->RxDescArray + i);
5706 rtl8169_tx_clear(tp);
5707 rtl8169_init_ring_indexes(tp);
5709 napi_enable(&tp->napi);
5711 netif_wake_queue(dev);
5714 static void rtl8169_tx_timeout(struct net_device *dev)
5716 struct rtl8169_private *tp = netdev_priv(dev);
5718 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
5721 static __le32 rtl8169_get_txd_opts1(u32 opts0, u32 len, unsigned int entry)
5723 u32 status = opts0 | len;
5725 if (entry == NUM_TX_DESC - 1)
5728 return cpu_to_le32(status);
5731 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
5734 struct skb_shared_info *info = skb_shinfo(skb);
5735 unsigned int cur_frag, entry;
5736 struct TxDesc *uninitialized_var(txd);
5737 struct device *d = tp_to_dev(tp);
5740 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
5741 const skb_frag_t *frag = info->frags + cur_frag;
5746 entry = (entry + 1) % NUM_TX_DESC;
5748 txd = tp->TxDescArray + entry;
5749 len = skb_frag_size(frag);
5750 addr = skb_frag_address(frag);
5751 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
5752 if (unlikely(dma_mapping_error(d, mapping))) {
5753 if (net_ratelimit())
5754 netif_err(tp, drv, tp->dev,
5755 "Failed to map TX fragments DMA!\n");
5759 txd->opts1 = rtl8169_get_txd_opts1(opts[0], len, entry);
5760 txd->opts2 = cpu_to_le32(opts[1]);
5761 txd->addr = cpu_to_le64(mapping);
5763 tp->tx_skb[entry].len = len;
5767 tp->tx_skb[entry].skb = skb;
5768 txd->opts1 |= cpu_to_le32(LastFrag);
5774 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
5778 static bool rtl_test_hw_pad_bug(struct rtl8169_private *tp, struct sk_buff *skb)
5780 return skb->len < ETH_ZLEN && tp->mac_version == RTL_GIGA_MAC_VER_34;
5783 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
5784 struct net_device *dev);
5785 /* r8169_csum_workaround()
5786 * The hw limites the value the transport offset. When the offset is out of the
5787 * range, calculate the checksum by sw.
5789 static void r8169_csum_workaround(struct rtl8169_private *tp,
5790 struct sk_buff *skb)
5792 if (skb_shinfo(skb)->gso_size) {
5793 netdev_features_t features = tp->dev->features;
5794 struct sk_buff *segs, *nskb;
5796 features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
5797 segs = skb_gso_segment(skb, features);
5798 if (IS_ERR(segs) || !segs)
5805 rtl8169_start_xmit(nskb, tp->dev);
5808 dev_consume_skb_any(skb);
5809 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5810 if (skb_checksum_help(skb) < 0)
5813 rtl8169_start_xmit(skb, tp->dev);
5815 struct net_device_stats *stats;
5818 stats = &tp->dev->stats;
5819 stats->tx_dropped++;
5820 dev_kfree_skb_any(skb);
5824 /* msdn_giant_send_check()
5825 * According to the document of microsoft, the TCP Pseudo Header excludes the
5826 * packet length for IPv6 TCP large packets.
5828 static int msdn_giant_send_check(struct sk_buff *skb)
5830 const struct ipv6hdr *ipv6h;
5834 ret = skb_cow_head(skb, 0);
5838 ipv6h = ipv6_hdr(skb);
5842 th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0);
5847 static bool rtl8169_tso_csum_v1(struct rtl8169_private *tp,
5848 struct sk_buff *skb, u32 *opts)
5850 u32 mss = skb_shinfo(skb)->gso_size;
5854 opts[0] |= min(mss, TD_MSS_MAX) << TD0_MSS_SHIFT;
5855 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5856 const struct iphdr *ip = ip_hdr(skb);
5858 if (ip->protocol == IPPROTO_TCP)
5859 opts[0] |= TD0_IP_CS | TD0_TCP_CS;
5860 else if (ip->protocol == IPPROTO_UDP)
5861 opts[0] |= TD0_IP_CS | TD0_UDP_CS;
5869 static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp,
5870 struct sk_buff *skb, u32 *opts)
5872 u32 transport_offset = (u32)skb_transport_offset(skb);
5873 u32 mss = skb_shinfo(skb)->gso_size;
5876 if (transport_offset > GTTCPHO_MAX) {
5877 netif_warn(tp, tx_err, tp->dev,
5878 "Invalid transport offset 0x%x for TSO\n",
5883 switch (vlan_get_protocol(skb)) {
5884 case htons(ETH_P_IP):
5885 opts[0] |= TD1_GTSENV4;
5888 case htons(ETH_P_IPV6):
5889 if (msdn_giant_send_check(skb))
5892 opts[0] |= TD1_GTSENV6;
5900 opts[0] |= transport_offset << GTTCPHO_SHIFT;
5901 opts[1] |= min(mss, TD_MSS_MAX) << TD1_MSS_SHIFT;
5902 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5905 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
5906 return !(skb_checksum_help(skb) || eth_skb_pad(skb));
5908 if (transport_offset > TCPHO_MAX) {
5909 netif_warn(tp, tx_err, tp->dev,
5910 "Invalid transport offset 0x%x\n",
5915 switch (vlan_get_protocol(skb)) {
5916 case htons(ETH_P_IP):
5917 opts[1] |= TD1_IPv4_CS;
5918 ip_protocol = ip_hdr(skb)->protocol;
5921 case htons(ETH_P_IPV6):
5922 opts[1] |= TD1_IPv6_CS;
5923 ip_protocol = ipv6_hdr(skb)->nexthdr;
5927 ip_protocol = IPPROTO_RAW;
5931 if (ip_protocol == IPPROTO_TCP)
5932 opts[1] |= TD1_TCP_CS;
5933 else if (ip_protocol == IPPROTO_UDP)
5934 opts[1] |= TD1_UDP_CS;
5938 opts[1] |= transport_offset << TCPHO_SHIFT;
5940 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
5941 return !eth_skb_pad(skb);
5947 static bool rtl_tx_slots_avail(struct rtl8169_private *tp,
5948 unsigned int nr_frags)
5950 unsigned int slots_avail = tp->dirty_tx + NUM_TX_DESC - tp->cur_tx;
5952 /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
5953 return slots_avail > nr_frags;
5956 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
5957 struct net_device *dev)
5959 struct rtl8169_private *tp = netdev_priv(dev);
5960 unsigned int entry = tp->cur_tx % NUM_TX_DESC;
5961 struct TxDesc *txd = tp->TxDescArray + entry;
5962 struct device *d = tp_to_dev(tp);
5967 if (unlikely(!rtl_tx_slots_avail(tp, skb_shinfo(skb)->nr_frags))) {
5968 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
5972 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
5975 opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(skb));
5978 if (!tp->tso_csum(tp, skb, opts)) {
5979 r8169_csum_workaround(tp, skb);
5980 return NETDEV_TX_OK;
5983 len = skb_headlen(skb);
5984 mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
5985 if (unlikely(dma_mapping_error(d, mapping))) {
5986 if (net_ratelimit())
5987 netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
5991 tp->tx_skb[entry].len = len;
5992 txd->addr = cpu_to_le64(mapping);
5994 frags = rtl8169_xmit_frags(tp, skb, opts);
5998 opts[0] |= FirstFrag;
6000 opts[0] |= FirstFrag | LastFrag;
6001 tp->tx_skb[entry].skb = skb;
6004 txd->opts2 = cpu_to_le32(opts[1]);
6006 netdev_sent_queue(dev, skb->len);
6008 skb_tx_timestamp(skb);
6010 /* Force memory writes to complete before releasing descriptor */
6013 txd->opts1 = rtl8169_get_txd_opts1(opts[0], len, entry);
6015 /* Force all memory writes to complete before notifying device */
6018 tp->cur_tx += frags + 1;
6020 RTL_W8(tp, TxPoll, NPQ);
6022 if (!rtl_tx_slots_avail(tp, MAX_SKB_FRAGS)) {
6023 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
6024 * not miss a ring update when it notices a stopped queue.
6027 netif_stop_queue(dev);
6028 /* Sync with rtl_tx:
6029 * - publish queue status and cur_tx ring index (write barrier)
6030 * - refresh dirty_tx ring index (read barrier).
6031 * May the current thread have a pessimistic view of the ring
6032 * status and forget to wake up queue, a racing rtl_tx thread
6036 if (rtl_tx_slots_avail(tp, MAX_SKB_FRAGS))
6037 netif_start_queue(dev);
6040 return NETDEV_TX_OK;
6043 rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
6045 dev_kfree_skb_any(skb);
6046 dev->stats.tx_dropped++;
6047 return NETDEV_TX_OK;
6050 netif_stop_queue(dev);
6051 dev->stats.tx_dropped++;
6052 return NETDEV_TX_BUSY;
6055 static void rtl8169_pcierr_interrupt(struct net_device *dev)
6057 struct rtl8169_private *tp = netdev_priv(dev);
6058 struct pci_dev *pdev = tp->pci_dev;
6059 u16 pci_status, pci_cmd;
6061 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
6062 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
6064 netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
6065 pci_cmd, pci_status);
6068 * The recovery sequence below admits a very elaborated explanation:
6069 * - it seems to work;
6070 * - I did not see what else could be done;
6071 * - it makes iop3xx happy.
6073 * Feel free to adjust to your needs.
6075 if (pdev->broken_parity_status)
6076 pci_cmd &= ~PCI_COMMAND_PARITY;
6078 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
6080 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
6082 pci_write_config_word(pdev, PCI_STATUS,
6083 pci_status & (PCI_STATUS_DETECTED_PARITY |
6084 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
6085 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
6087 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
6090 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp,
6093 unsigned int dirty_tx, tx_left, bytes_compl = 0, pkts_compl = 0;
6095 dirty_tx = tp->dirty_tx;
6097 tx_left = tp->cur_tx - dirty_tx;
6099 while (tx_left > 0) {
6100 unsigned int entry = dirty_tx % NUM_TX_DESC;
6101 struct ring_info *tx_skb = tp->tx_skb + entry;
6104 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
6105 if (status & DescOwn)
6108 /* This barrier is needed to keep us from reading
6109 * any other fields out of the Tx descriptor until
6110 * we know the status of DescOwn
6114 rtl8169_unmap_tx_skb(tp_to_dev(tp), tx_skb,
6115 tp->TxDescArray + entry);
6116 if (status & LastFrag) {
6118 bytes_compl += tx_skb->skb->len;
6119 napi_consume_skb(tx_skb->skb, budget);
6126 if (tp->dirty_tx != dirty_tx) {
6127 netdev_completed_queue(dev, pkts_compl, bytes_compl);
6129 u64_stats_update_begin(&tp->tx_stats.syncp);
6130 tp->tx_stats.packets += pkts_compl;
6131 tp->tx_stats.bytes += bytes_compl;
6132 u64_stats_update_end(&tp->tx_stats.syncp);
6134 tp->dirty_tx = dirty_tx;
6135 /* Sync with rtl8169_start_xmit:
6136 * - publish dirty_tx ring index (write barrier)
6137 * - refresh cur_tx ring index and queue status (read barrier)
6138 * May the current thread miss the stopped queue condition,
6139 * a racing xmit thread can only have a right view of the
6143 if (netif_queue_stopped(dev) &&
6144 rtl_tx_slots_avail(tp, MAX_SKB_FRAGS)) {
6145 netif_wake_queue(dev);
6148 * 8168 hack: TxPoll requests are lost when the Tx packets are
6149 * too close. Let's kick an extra TxPoll request when a burst
6150 * of start_xmit activity is detected (if it is not detected,
6151 * it is slow enough). -- FR
6153 if (tp->cur_tx != dirty_tx)
6154 RTL_W8(tp, TxPoll, NPQ);
6158 static inline int rtl8169_fragmented_frame(u32 status)
6160 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
6163 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
6165 u32 status = opts1 & RxProtoMask;
6167 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
6168 ((status == RxProtoUDP) && !(opts1 & UDPFail)))
6169 skb->ip_summed = CHECKSUM_UNNECESSARY;
6171 skb_checksum_none_assert(skb);
6174 static struct sk_buff *rtl8169_try_rx_copy(void *data,
6175 struct rtl8169_private *tp,
6179 struct sk_buff *skb;
6180 struct device *d = tp_to_dev(tp);
6182 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
6184 skb = napi_alloc_skb(&tp->napi, pkt_size);
6186 skb_copy_to_linear_data(skb, data, pkt_size);
6187 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
6192 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget)
6194 unsigned int cur_rx, rx_left;
6197 cur_rx = tp->cur_rx;
6199 for (rx_left = min(budget, NUM_RX_DESC); rx_left > 0; rx_left--, cur_rx++) {
6200 unsigned int entry = cur_rx % NUM_RX_DESC;
6201 struct RxDesc *desc = tp->RxDescArray + entry;
6204 status = le32_to_cpu(desc->opts1);
6205 if (status & DescOwn)
6208 /* This barrier is needed to keep us from reading
6209 * any other fields out of the Rx descriptor until
6210 * we know the status of DescOwn
6214 if (unlikely(status & RxRES)) {
6215 netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
6217 dev->stats.rx_errors++;
6218 if (status & (RxRWT | RxRUNT))
6219 dev->stats.rx_length_errors++;
6221 dev->stats.rx_crc_errors++;
6222 /* RxFOVF is a reserved bit on later chip versions */
6223 if (tp->mac_version == RTL_GIGA_MAC_VER_01 &&
6225 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
6226 dev->stats.rx_fifo_errors++;
6227 } else if (status & (RxRUNT | RxCRC) &&
6228 !(status & RxRWT) &&
6229 dev->features & NETIF_F_RXALL) {
6233 struct sk_buff *skb;
6238 addr = le64_to_cpu(desc->addr);
6239 if (likely(!(dev->features & NETIF_F_RXFCS)))
6240 pkt_size = (status & 0x00003fff) - 4;
6242 pkt_size = status & 0x00003fff;
6245 * The driver does not support incoming fragmented
6246 * frames. They are seen as a symptom of over-mtu
6249 if (unlikely(rtl8169_fragmented_frame(status))) {
6250 dev->stats.rx_dropped++;
6251 dev->stats.rx_length_errors++;
6252 goto release_descriptor;
6255 skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
6256 tp, pkt_size, addr);
6258 dev->stats.rx_dropped++;
6259 goto release_descriptor;
6262 rtl8169_rx_csum(skb, status);
6263 skb_put(skb, pkt_size);
6264 skb->protocol = eth_type_trans(skb, dev);
6266 rtl8169_rx_vlan_tag(desc, skb);
6268 if (skb->pkt_type == PACKET_MULTICAST)
6269 dev->stats.multicast++;
6271 napi_gro_receive(&tp->napi, skb);
6273 u64_stats_update_begin(&tp->rx_stats.syncp);
6274 tp->rx_stats.packets++;
6275 tp->rx_stats.bytes += pkt_size;
6276 u64_stats_update_end(&tp->rx_stats.syncp);
6280 rtl8169_mark_to_asic(desc);
6283 count = cur_rx - tp->cur_rx;
6284 tp->cur_rx = cur_rx;
6289 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
6291 struct rtl8169_private *tp = dev_instance;
6292 u16 status = RTL_R16(tp, IntrStatus);
6294 if (!tp->irq_enabled || status == 0xffff || !(status & tp->irq_mask))
6297 if (unlikely(status & SYSErr)) {
6298 rtl8169_pcierr_interrupt(tp->dev);
6302 if (status & LinkChg)
6303 phy_mac_interrupt(tp->phydev);
6305 if (unlikely(status & RxFIFOOver &&
6306 tp->mac_version == RTL_GIGA_MAC_VER_11)) {
6307 netif_stop_queue(tp->dev);
6308 /* XXX - Hack alert. See rtl_task(). */
6309 set_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags);
6312 rtl_irq_disable(tp);
6313 napi_schedule_irqoff(&tp->napi);
6315 rtl_ack_events(tp, status);
6320 static void rtl_task(struct work_struct *work)
6322 static const struct {
6324 void (*action)(struct rtl8169_private *);
6326 { RTL_FLAG_TASK_RESET_PENDING, rtl_reset_work },
6328 struct rtl8169_private *tp =
6329 container_of(work, struct rtl8169_private, wk.work);
6330 struct net_device *dev = tp->dev;
6335 if (!netif_running(dev) ||
6336 !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
6339 for (i = 0; i < ARRAY_SIZE(rtl_work); i++) {
6342 pending = test_and_clear_bit(rtl_work[i].bitnr, tp->wk.flags);
6344 rtl_work[i].action(tp);
6348 rtl_unlock_work(tp);
6351 static int rtl8169_poll(struct napi_struct *napi, int budget)
6353 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
6354 struct net_device *dev = tp->dev;
6357 work_done = rtl_rx(dev, tp, (u32) budget);
6359 rtl_tx(dev, tp, budget);
6361 if (work_done < budget) {
6362 napi_complete_done(napi, work_done);
6369 static void rtl8169_rx_missed(struct net_device *dev)
6371 struct rtl8169_private *tp = netdev_priv(dev);
6373 if (tp->mac_version > RTL_GIGA_MAC_VER_06)
6376 dev->stats.rx_missed_errors += RTL_R32(tp, RxMissed) & 0xffffff;
6377 RTL_W32(tp, RxMissed, 0);
6380 static void r8169_phylink_handler(struct net_device *ndev)
6382 struct rtl8169_private *tp = netdev_priv(ndev);
6384 if (netif_carrier_ok(ndev)) {
6385 rtl_link_chg_patch(tp);
6386 pm_request_resume(&tp->pci_dev->dev);
6388 pm_runtime_idle(&tp->pci_dev->dev);
6391 if (net_ratelimit())
6392 phy_print_status(tp->phydev);
6395 static int r8169_phy_connect(struct rtl8169_private *tp)
6397 struct phy_device *phydev = tp->phydev;
6398 phy_interface_t phy_mode;
6401 phy_mode = tp->supports_gmii ? PHY_INTERFACE_MODE_GMII :
6402 PHY_INTERFACE_MODE_MII;
6404 ret = phy_connect_direct(tp->dev, phydev, r8169_phylink_handler,
6409 if (!tp->supports_gmii)
6410 phy_set_max_speed(phydev, SPEED_100);
6412 phy_support_asym_pause(phydev);
6414 phy_attached_info(phydev);
6419 static void rtl8169_down(struct net_device *dev)
6421 struct rtl8169_private *tp = netdev_priv(dev);
6423 phy_stop(tp->phydev);
6425 napi_disable(&tp->napi);
6426 netif_stop_queue(dev);
6428 rtl8169_hw_reset(tp);
6430 * At this point device interrupts can not be enabled in any function,
6431 * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task)
6432 * and napi is disabled (rtl8169_poll).
6434 rtl8169_rx_missed(dev);
6436 /* Give a racing hard_start_xmit a few cycles to complete. */
6439 rtl8169_tx_clear(tp);
6441 rtl8169_rx_clear(tp);
6443 rtl_pll_power_down(tp);
6446 static int rtl8169_close(struct net_device *dev)
6448 struct rtl8169_private *tp = netdev_priv(dev);
6449 struct pci_dev *pdev = tp->pci_dev;
6451 pm_runtime_get_sync(&pdev->dev);
6453 /* Update counters before going down */
6454 rtl8169_update_counters(tp);
6457 /* Clear all task flags */
6458 bitmap_zero(tp->wk.flags, RTL_FLAG_MAX);
6461 rtl_unlock_work(tp);
6463 cancel_work_sync(&tp->wk.work);
6465 phy_disconnect(tp->phydev);
6467 pci_free_irq(pdev, 0, tp);
6469 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6471 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6473 tp->TxDescArray = NULL;
6474 tp->RxDescArray = NULL;
6476 pm_runtime_put_sync(&pdev->dev);
6481 #ifdef CONFIG_NET_POLL_CONTROLLER
6482 static void rtl8169_netpoll(struct net_device *dev)
6484 struct rtl8169_private *tp = netdev_priv(dev);
6486 rtl8169_interrupt(pci_irq_vector(tp->pci_dev, 0), tp);
6490 static int rtl_open(struct net_device *dev)
6492 struct rtl8169_private *tp = netdev_priv(dev);
6493 struct pci_dev *pdev = tp->pci_dev;
6494 int retval = -ENOMEM;
6496 pm_runtime_get_sync(&pdev->dev);
6499 * Rx and Tx descriptors needs 256 bytes alignment.
6500 * dma_alloc_coherent provides more.
6502 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
6503 &tp->TxPhyAddr, GFP_KERNEL);
6504 if (!tp->TxDescArray)
6505 goto err_pm_runtime_put;
6507 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
6508 &tp->RxPhyAddr, GFP_KERNEL);
6509 if (!tp->RxDescArray)
6512 retval = rtl8169_init_ring(tp);
6516 rtl_request_firmware(tp);
6518 retval = pci_request_irq(pdev, 0, rtl8169_interrupt, NULL, tp,
6521 goto err_release_fw_2;
6523 retval = r8169_phy_connect(tp);
6529 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6531 napi_enable(&tp->napi);
6533 rtl8169_init_phy(dev, tp);
6535 rtl_pll_power_up(tp);
6539 if (!rtl8169_init_counter_offsets(tp))
6540 netif_warn(tp, hw, dev, "counter reset/update failed\n");
6542 phy_start(tp->phydev);
6543 netif_start_queue(dev);
6545 rtl_unlock_work(tp);
6547 pm_runtime_put_sync(&pdev->dev);
6552 pci_free_irq(pdev, 0, tp);
6554 rtl_release_firmware(tp);
6555 rtl8169_rx_clear(tp);
6557 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6559 tp->RxDescArray = NULL;
6561 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6563 tp->TxDescArray = NULL;
6565 pm_runtime_put_noidle(&pdev->dev);
6570 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
6572 struct rtl8169_private *tp = netdev_priv(dev);
6573 struct pci_dev *pdev = tp->pci_dev;
6574 struct rtl8169_counters *counters = tp->counters;
6577 pm_runtime_get_noresume(&pdev->dev);
6579 if (netif_running(dev) && pm_runtime_active(&pdev->dev))
6580 rtl8169_rx_missed(dev);
6583 start = u64_stats_fetch_begin_irq(&tp->rx_stats.syncp);
6584 stats->rx_packets = tp->rx_stats.packets;
6585 stats->rx_bytes = tp->rx_stats.bytes;
6586 } while (u64_stats_fetch_retry_irq(&tp->rx_stats.syncp, start));
6589 start = u64_stats_fetch_begin_irq(&tp->tx_stats.syncp);
6590 stats->tx_packets = tp->tx_stats.packets;
6591 stats->tx_bytes = tp->tx_stats.bytes;
6592 } while (u64_stats_fetch_retry_irq(&tp->tx_stats.syncp, start));
6594 stats->rx_dropped = dev->stats.rx_dropped;
6595 stats->tx_dropped = dev->stats.tx_dropped;
6596 stats->rx_length_errors = dev->stats.rx_length_errors;
6597 stats->rx_errors = dev->stats.rx_errors;
6598 stats->rx_crc_errors = dev->stats.rx_crc_errors;
6599 stats->rx_fifo_errors = dev->stats.rx_fifo_errors;
6600 stats->rx_missed_errors = dev->stats.rx_missed_errors;
6601 stats->multicast = dev->stats.multicast;
6604 * Fetch additonal counter values missing in stats collected by driver
6605 * from tally counters.
6607 if (pm_runtime_active(&pdev->dev))
6608 rtl8169_update_counters(tp);
6611 * Subtract values fetched during initalization.
6612 * See rtl8169_init_counter_offsets for a description why we do that.
6614 stats->tx_errors = le64_to_cpu(counters->tx_errors) -
6615 le64_to_cpu(tp->tc_offset.tx_errors);
6616 stats->collisions = le32_to_cpu(counters->tx_multi_collision) -
6617 le32_to_cpu(tp->tc_offset.tx_multi_collision);
6618 stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) -
6619 le16_to_cpu(tp->tc_offset.tx_aborted);
6621 pm_runtime_put_noidle(&pdev->dev);
6624 static void rtl8169_net_suspend(struct net_device *dev)
6626 struct rtl8169_private *tp = netdev_priv(dev);
6628 if (!netif_running(dev))
6631 phy_stop(tp->phydev);
6632 netif_device_detach(dev);
6635 napi_disable(&tp->napi);
6636 /* Clear all task flags */
6637 bitmap_zero(tp->wk.flags, RTL_FLAG_MAX);
6639 rtl_unlock_work(tp);
6641 rtl_pll_power_down(tp);
6646 static int rtl8169_suspend(struct device *device)
6648 struct net_device *dev = dev_get_drvdata(device);
6649 struct rtl8169_private *tp = netdev_priv(dev);
6651 rtl8169_net_suspend(dev);
6652 clk_disable_unprepare(tp->clk);
6657 static void __rtl8169_resume(struct net_device *dev)
6659 struct rtl8169_private *tp = netdev_priv(dev);
6661 netif_device_attach(dev);
6663 rtl_pll_power_up(tp);
6664 rtl8169_init_phy(dev, tp);
6666 phy_start(tp->phydev);
6669 napi_enable(&tp->napi);
6670 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6672 rtl_unlock_work(tp);
6675 static int rtl8169_resume(struct device *device)
6677 struct net_device *dev = dev_get_drvdata(device);
6678 struct rtl8169_private *tp = netdev_priv(dev);
6680 clk_prepare_enable(tp->clk);
6682 if (netif_running(dev))
6683 __rtl8169_resume(dev);
6688 static int rtl8169_runtime_suspend(struct device *device)
6690 struct net_device *dev = dev_get_drvdata(device);
6691 struct rtl8169_private *tp = netdev_priv(dev);
6693 if (!tp->TxDescArray)
6697 __rtl8169_set_wol(tp, WAKE_ANY);
6698 rtl_unlock_work(tp);
6700 rtl8169_net_suspend(dev);
6702 /* Update counters before going runtime suspend */
6703 rtl8169_rx_missed(dev);
6704 rtl8169_update_counters(tp);
6709 static int rtl8169_runtime_resume(struct device *device)
6711 struct net_device *dev = dev_get_drvdata(device);
6712 struct rtl8169_private *tp = netdev_priv(dev);
6713 rtl_rar_set(tp, dev->dev_addr);
6715 if (!tp->TxDescArray)
6719 __rtl8169_set_wol(tp, tp->saved_wolopts);
6720 rtl_unlock_work(tp);
6722 __rtl8169_resume(dev);
6727 static int rtl8169_runtime_idle(struct device *device)
6729 struct net_device *dev = dev_get_drvdata(device);
6731 if (!netif_running(dev) || !netif_carrier_ok(dev))
6732 pm_schedule_suspend(device, 10000);
6737 static const struct dev_pm_ops rtl8169_pm_ops = {
6738 .suspend = rtl8169_suspend,
6739 .resume = rtl8169_resume,
6740 .freeze = rtl8169_suspend,
6741 .thaw = rtl8169_resume,
6742 .poweroff = rtl8169_suspend,
6743 .restore = rtl8169_resume,
6744 .runtime_suspend = rtl8169_runtime_suspend,
6745 .runtime_resume = rtl8169_runtime_resume,
6746 .runtime_idle = rtl8169_runtime_idle,
6749 #define RTL8169_PM_OPS (&rtl8169_pm_ops)
6751 #else /* !CONFIG_PM */
6753 #define RTL8169_PM_OPS NULL
6755 #endif /* !CONFIG_PM */
6757 static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
6759 /* WoL fails with 8168b when the receiver is disabled. */
6760 switch (tp->mac_version) {
6761 case RTL_GIGA_MAC_VER_11:
6762 case RTL_GIGA_MAC_VER_12:
6763 case RTL_GIGA_MAC_VER_17:
6764 pci_clear_master(tp->pci_dev);
6766 RTL_W8(tp, ChipCmd, CmdRxEnb);
6768 RTL_R8(tp, ChipCmd);
6775 static void rtl_shutdown(struct pci_dev *pdev)
6777 struct net_device *dev = pci_get_drvdata(pdev);
6778 struct rtl8169_private *tp = netdev_priv(dev);
6780 rtl8169_net_suspend(dev);
6782 /* Restore original MAC address */
6783 rtl_rar_set(tp, dev->perm_addr);
6785 rtl8169_hw_reset(tp);
6787 if (system_state == SYSTEM_POWER_OFF) {
6788 if (tp->saved_wolopts) {
6789 rtl_wol_suspend_quirk(tp);
6790 rtl_wol_shutdown_quirk(tp);
6793 pci_wake_from_d3(pdev, true);
6794 pci_set_power_state(pdev, PCI_D3hot);
6798 static void rtl_remove_one(struct pci_dev *pdev)
6800 struct net_device *dev = pci_get_drvdata(pdev);
6801 struct rtl8169_private *tp = netdev_priv(dev);
6803 if (r8168_check_dash(tp))
6804 rtl8168_driver_stop(tp);
6806 netif_napi_del(&tp->napi);
6808 unregister_netdev(dev);
6809 mdiobus_unregister(tp->phydev->mdio.bus);
6811 rtl_release_firmware(tp);
6813 if (pci_dev_run_wake(pdev))
6814 pm_runtime_get_noresume(&pdev->dev);
6816 /* restore original MAC address */
6817 rtl_rar_set(tp, dev->perm_addr);
6820 static const struct net_device_ops rtl_netdev_ops = {
6821 .ndo_open = rtl_open,
6822 .ndo_stop = rtl8169_close,
6823 .ndo_get_stats64 = rtl8169_get_stats64,
6824 .ndo_start_xmit = rtl8169_start_xmit,
6825 .ndo_tx_timeout = rtl8169_tx_timeout,
6826 .ndo_validate_addr = eth_validate_addr,
6827 .ndo_change_mtu = rtl8169_change_mtu,
6828 .ndo_fix_features = rtl8169_fix_features,
6829 .ndo_set_features = rtl8169_set_features,
6830 .ndo_set_mac_address = rtl_set_mac_address,
6831 .ndo_do_ioctl = rtl8169_ioctl,
6832 .ndo_set_rx_mode = rtl_set_rx_mode,
6833 #ifdef CONFIG_NET_POLL_CONTROLLER
6834 .ndo_poll_controller = rtl8169_netpoll,
6839 static const struct rtl_cfg_info {
6840 void (*hw_start)(struct rtl8169_private *tp);
6842 unsigned int has_gmii:1;
6843 const struct rtl_coalesce_info *coalesce_info;
6844 } rtl_cfg_infos [] = {
6846 .hw_start = rtl_hw_start_8169,
6847 .irq_mask = SYSErr | LinkChg | RxOverflow | RxFIFOOver,
6849 .coalesce_info = rtl_coalesce_info_8169,
6852 .hw_start = rtl_hw_start_8168,
6853 .irq_mask = LinkChg | RxOverflow,
6855 .coalesce_info = rtl_coalesce_info_8168_8136,
6858 .hw_start = rtl_hw_start_8101,
6859 .irq_mask = LinkChg | RxOverflow | RxFIFOOver,
6860 .coalesce_info = rtl_coalesce_info_8168_8136,
6864 static int rtl_alloc_irq(struct rtl8169_private *tp)
6868 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
6869 rtl_unlock_config_regs(tp);
6870 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~MSIEnable);
6871 rtl_lock_config_regs(tp);
6872 flags = PCI_IRQ_LEGACY;
6874 flags = PCI_IRQ_ALL_TYPES;
6877 return pci_alloc_irq_vectors(tp->pci_dev, 1, 1, flags);
6880 static void rtl_read_mac_address(struct rtl8169_private *tp,
6881 u8 mac_addr[ETH_ALEN])
6885 /* Get MAC address */
6886 switch (tp->mac_version) {
6887 case RTL_GIGA_MAC_VER_35 ... RTL_GIGA_MAC_VER_38:
6888 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
6889 value = rtl_eri_read(tp, 0xe0);
6890 mac_addr[0] = (value >> 0) & 0xff;
6891 mac_addr[1] = (value >> 8) & 0xff;
6892 mac_addr[2] = (value >> 16) & 0xff;
6893 mac_addr[3] = (value >> 24) & 0xff;
6895 value = rtl_eri_read(tp, 0xe4);
6896 mac_addr[4] = (value >> 0) & 0xff;
6897 mac_addr[5] = (value >> 8) & 0xff;
6904 DECLARE_RTL_COND(rtl_link_list_ready_cond)
6906 return RTL_R8(tp, MCU) & LINK_LIST_RDY;
6909 DECLARE_RTL_COND(rtl_rxtx_empty_cond)
6911 return (RTL_R8(tp, MCU) & RXTX_EMPTY) == RXTX_EMPTY;
6914 static int r8169_mdio_read_reg(struct mii_bus *mii_bus, int phyaddr, int phyreg)
6916 struct rtl8169_private *tp = mii_bus->priv;
6921 return rtl_readphy(tp, phyreg);
6924 static int r8169_mdio_write_reg(struct mii_bus *mii_bus, int phyaddr,
6925 int phyreg, u16 val)
6927 struct rtl8169_private *tp = mii_bus->priv;
6932 rtl_writephy(tp, phyreg, val);
6937 static int r8169_mdio_register(struct rtl8169_private *tp)
6939 struct pci_dev *pdev = tp->pci_dev;
6940 struct mii_bus *new_bus;
6943 new_bus = devm_mdiobus_alloc(&pdev->dev);
6947 new_bus->name = "r8169";
6949 new_bus->parent = &pdev->dev;
6950 new_bus->irq[0] = PHY_IGNORE_INTERRUPT;
6951 snprintf(new_bus->id, MII_BUS_ID_SIZE, "r8169-%x", pci_dev_id(pdev));
6953 new_bus->read = r8169_mdio_read_reg;
6954 new_bus->write = r8169_mdio_write_reg;
6956 ret = mdiobus_register(new_bus);
6960 tp->phydev = mdiobus_get_phy(new_bus, 0);
6962 mdiobus_unregister(new_bus);
6966 /* PHY will be woken up in rtl_open() */
6967 phy_suspend(tp->phydev);
6972 static void rtl_hw_init_8168g(struct rtl8169_private *tp)
6976 tp->ocp_base = OCP_STD_PHY_BASE;
6978 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN);
6980 if (!rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42))
6983 if (!rtl_udelay_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42))
6986 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
6988 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
6990 data = r8168_mac_ocp_read(tp, 0xe8de);
6992 r8168_mac_ocp_write(tp, 0xe8de, data);
6994 if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
6997 data = r8168_mac_ocp_read(tp, 0xe8de);
6999 r8168_mac_ocp_write(tp, 0xe8de, data);
7001 rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42);
7004 static void rtl_hw_initialize(struct rtl8169_private *tp)
7006 switch (tp->mac_version) {
7007 case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_51:
7008 rtl8168ep_stop_cmac(tp);
7010 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_48:
7011 rtl_hw_init_8168g(tp);
7018 /* Versions RTL8102e and from RTL8168c onwards support csum_v2 */
7019 static bool rtl_chip_supports_csum_v2(struct rtl8169_private *tp)
7021 switch (tp->mac_version) {
7022 case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_06:
7023 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
7030 static int rtl_jumbo_max(struct rtl8169_private *tp)
7032 /* Non-GBit versions don't support jumbo frames */
7033 if (!tp->supports_gmii)
7036 switch (tp->mac_version) {
7038 case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_06:
7041 case RTL_GIGA_MAC_VER_11:
7042 case RTL_GIGA_MAC_VER_12:
7043 case RTL_GIGA_MAC_VER_17:
7046 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
7053 static void rtl_disable_clk(void *data)
7055 clk_disable_unprepare(data);
7058 static int rtl_get_ether_clk(struct rtl8169_private *tp)
7060 struct device *d = tp_to_dev(tp);
7064 clk = devm_clk_get(d, "ether_clk");
7068 /* clk-core allows NULL (for suspend / resume) */
7070 else if (rc != -EPROBE_DEFER)
7071 dev_err(d, "failed to get clk: %d\n", rc);
7074 rc = clk_prepare_enable(clk);
7076 dev_err(d, "failed to enable clk: %d\n", rc);
7078 rc = devm_add_action_or_reset(d, rtl_disable_clk, clk);
7084 static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
7086 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
7087 /* align to u16 for is_valid_ether_addr() */
7088 u8 mac_addr[ETH_ALEN] __aligned(2) = {};
7089 struct rtl8169_private *tp;
7090 struct net_device *dev;
7091 int chipset, region, i;
7094 dev = devm_alloc_etherdev(&pdev->dev, sizeof (*tp));
7098 SET_NETDEV_DEV(dev, &pdev->dev);
7099 dev->netdev_ops = &rtl_netdev_ops;
7100 tp = netdev_priv(dev);
7103 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
7104 tp->supports_gmii = cfg->has_gmii;
7106 /* Get the *optional* external "ether_clk" used on some boards */
7107 rc = rtl_get_ether_clk(tp);
7111 /* Disable ASPM completely as that cause random device stop working
7112 * problems as well as full system hangs for some PCIe devices users.
7114 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1);
7116 /* enable device (incl. PCI PM wakeup and hotplug setup) */
7117 rc = pcim_enable_device(pdev);
7119 dev_err(&pdev->dev, "enable failure\n");
7123 if (pcim_set_mwi(pdev) < 0)
7124 dev_info(&pdev->dev, "Mem-Wr-Inval unavailable\n");
7126 /* use first MMIO region */
7127 region = ffs(pci_select_bars(pdev, IORESOURCE_MEM)) - 1;
7129 dev_err(&pdev->dev, "no MMIO resource found\n");
7133 /* check for weird/broken PCI region reporting */
7134 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
7135 dev_err(&pdev->dev, "Invalid PCI region size(s), aborting\n");
7139 rc = pcim_iomap_regions(pdev, BIT(region), MODULENAME);
7141 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
7145 tp->mmio_addr = pcim_iomap_table(pdev)[region];
7147 /* Identify chip attached to board */
7148 rtl8169_get_mac_version(tp);
7149 if (tp->mac_version == RTL_GIGA_MAC_NONE)
7152 if (rtl_tbi_enabled(tp)) {
7153 dev_err(&pdev->dev, "TBI fiber mode not supported\n");
7157 tp->cp_cmd = RTL_R16(tp, CPlusCmd);
7159 if (sizeof(dma_addr_t) > 4 && tp->mac_version >= RTL_GIGA_MAC_VER_18 &&
7160 !dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) {
7161 dev->features |= NETIF_F_HIGHDMA;
7163 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
7165 dev_err(&pdev->dev, "DMA configuration failed\n");
7172 rtl8169_irq_mask_and_ack(tp);
7174 rtl_hw_initialize(tp);
7178 pci_set_master(pdev);
7180 rtl_init_mdio_ops(tp);
7181 rtl_init_jumbo_ops(tp);
7183 chipset = tp->mac_version;
7185 rc = rtl_alloc_irq(tp);
7187 dev_err(&pdev->dev, "Can't allocate interrupt\n");
7191 mutex_init(&tp->wk.mutex);
7192 INIT_WORK(&tp->wk.work, rtl_task);
7193 u64_stats_init(&tp->rx_stats.syncp);
7194 u64_stats_init(&tp->tx_stats.syncp);
7196 /* get MAC address */
7197 rc = eth_platform_get_mac_address(&pdev->dev, mac_addr);
7199 rtl_read_mac_address(tp, mac_addr);
7201 if (is_valid_ether_addr(mac_addr))
7202 rtl_rar_set(tp, mac_addr);
7204 for (i = 0; i < ETH_ALEN; i++)
7205 dev->dev_addr[i] = RTL_R8(tp, MAC0 + i);
7207 dev->ethtool_ops = &rtl8169_ethtool_ops;
7209 netif_napi_add(dev, &tp->napi, rtl8169_poll, NAPI_POLL_WEIGHT);
7211 /* don't enable SG, IP_CSUM and TSO by default - it might not work
7212 * properly for all devices */
7213 dev->features |= NETIF_F_RXCSUM |
7214 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
7216 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
7217 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_TX |
7218 NETIF_F_HW_VLAN_CTAG_RX;
7219 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
7221 dev->priv_flags |= IFF_LIVE_ADDR_CHANGE;
7223 tp->cp_cmd |= RxChkSum | RxVlan;
7226 * Pretend we are using VLANs; This bypasses a nasty bug where
7227 * Interrupts stop flowing on high load on 8110SCd controllers.
7229 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
7230 /* Disallow toggling */
7231 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX;
7233 if (rtl_chip_supports_csum_v2(tp)) {
7234 tp->tso_csum = rtl8169_tso_csum_v2;
7235 dev->hw_features |= NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
7237 tp->tso_csum = rtl8169_tso_csum_v1;
7240 dev->hw_features |= NETIF_F_RXALL;
7241 dev->hw_features |= NETIF_F_RXFCS;
7243 /* MTU range: 60 - hw-specific max */
7244 dev->min_mtu = ETH_ZLEN;
7245 jumbo_max = rtl_jumbo_max(tp);
7246 dev->max_mtu = jumbo_max;
7248 tp->hw_start = cfg->hw_start;
7249 tp->irq_mask = RTL_EVENT_NAPI | cfg->irq_mask;
7250 tp->coalesce_info = cfg->coalesce_info;
7252 tp->fw_name = rtl_chip_infos[chipset].fw_name;
7254 tp->counters = dmam_alloc_coherent (&pdev->dev, sizeof(*tp->counters),
7255 &tp->counters_phys_addr,
7260 pci_set_drvdata(pdev, dev);
7262 rc = r8169_mdio_register(tp);
7266 /* chip gets powered up in rtl_open() */
7267 rtl_pll_power_down(tp);
7269 rc = register_netdev(dev);
7271 goto err_mdio_unregister;
7273 netif_info(tp, probe, dev, "%s, %pM, XID %03x, IRQ %d\n",
7274 rtl_chip_infos[chipset].name, dev->dev_addr,
7275 (RTL_R32(tp, TxConfig) >> 20) & 0xfcf,
7276 pci_irq_vector(pdev, 0));
7278 if (jumbo_max > JUMBO_1K)
7279 netif_info(tp, probe, dev,
7280 "jumbo features [frames: %d bytes, tx checksumming: %s]\n",
7281 jumbo_max, tp->mac_version <= RTL_GIGA_MAC_VER_06 ?
7284 if (r8168_check_dash(tp))
7285 rtl8168_driver_start(tp);
7287 if (pci_dev_run_wake(pdev))
7288 pm_runtime_put_sync(&pdev->dev);
7292 err_mdio_unregister:
7293 mdiobus_unregister(tp->phydev->mdio.bus);
7297 static struct pci_driver rtl8169_pci_driver = {
7299 .id_table = rtl8169_pci_tbl,
7300 .probe = rtl_init_one,
7301 .remove = rtl_remove_one,
7302 .shutdown = rtl_shutdown,
7303 .driver.pm = RTL8169_PM_OPS,
7306 module_pci_driver(rtl8169_pci_driver);