drivers/net/ethernet/realtek/r8169.c

   1 /*
   2  * r8169.c: RealTek 8169/8168/8101 ethernet driver.
   3  *
   4  * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
   5  * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
   6  * Copyright (c) a lot of people too. Please respect their work.
   7  *
   8  * See MAINTAINERS file for support contact information.
   9  */
  10
  11 #include <linux/module.h>
  12 #include <linux/moduleparam.h>
  13 #include <linux/pci.h>
  14 #include <linux/netdevice.h>
  15 #include <linux/etherdevice.h>
  16 #include <linux/clk.h>
  17 #include <linux/delay.h>
  18 #include <linux/ethtool.h>
  19 #include <linux/phy.h>
  20 #include <linux/if_vlan.h>
  21 #include <linux/crc32.h>
  22 #include <linux/in.h>
  23 #include <linux/io.h>
  24 #include <linux/ip.h>
  25 #include <linux/tcp.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/dma-mapping.h>
  28 #include <linux/pm_runtime.h>
  29 #include <linux/firmware.h>
  30 #include <linux/prefetch.h>
  31 #include <linux/ipv6.h>
  32 #include <net/ip6_checksum.h>
  33
  34 #define MODULENAME "r8169"
  35
  36 #define FIRMWARE_8168D_1        "rtl_nic/rtl8168d-1.fw"
  37 #define FIRMWARE_8168D_2        "rtl_nic/rtl8168d-2.fw"
  38 #define FIRMWARE_8168E_1        "rtl_nic/rtl8168e-1.fw"
  39 #define FIRMWARE_8168E_2        "rtl_nic/rtl8168e-2.fw"
  40 #define FIRMWARE_8168E_3        "rtl_nic/rtl8168e-3.fw"
  41 #define FIRMWARE_8168F_1        "rtl_nic/rtl8168f-1.fw"
  42 #define FIRMWARE_8168F_2        "rtl_nic/rtl8168f-2.fw"
  43 #define FIRMWARE_8105E_1        "rtl_nic/rtl8105e-1.fw"
  44 #define FIRMWARE_8402_1         "rtl_nic/rtl8402-1.fw"
  45 #define FIRMWARE_8411_1         "rtl_nic/rtl8411-1.fw"
  46 #define FIRMWARE_8411_2         "rtl_nic/rtl8411-2.fw"
  47 #define FIRMWARE_8106E_1        "rtl_nic/rtl8106e-1.fw"
  48 #define FIRMWARE_8106E_2        "rtl_nic/rtl8106e-2.fw"
  49 #define FIRMWARE_8168G_2        "rtl_nic/rtl8168g-2.fw"
  50 #define FIRMWARE_8168G_3        "rtl_nic/rtl8168g-3.fw"
  51 #define FIRMWARE_8168H_1        "rtl_nic/rtl8168h-1.fw"
  52 #define FIRMWARE_8168H_2        "rtl_nic/rtl8168h-2.fw"
  53 #define FIRMWARE_8107E_1        "rtl_nic/rtl8107e-1.fw"
  54 #define FIRMWARE_8107E_2        "rtl_nic/rtl8107e-2.fw"
  55
  56 #define R8169_MSG_DEFAULT \
  57         (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
  58
  59 #define TX_SLOTS_AVAIL(tp) \
  60         (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx)
  61
  62 /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
  63 #define TX_FRAGS_READY_FOR(tp,nr_frags) \
  64         (TX_SLOTS_AVAIL(tp) >= (nr_frags + 1))
  65
  66 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
  67    The RTL chips use a 64 element hash table based on the Ethernet CRC. */
  68 static const int multicast_filter_limit = 32;
  69
  70 #define TX_DMA_BURST    7       /* Maximum PCI burst, '7' is unlimited */
  71 #define InterFrameGap   0x03    /* 3 means InterFrameGap = the shortest one */
  72
  73 #define R8169_REGS_SIZE         256
  74 #define R8169_RX_BUF_SIZE       (SZ_16K - 1)
  75 #define NUM_TX_DESC     64      /* Number of Tx descriptor registers */
  76 #define NUM_RX_DESC     256U    /* Number of Rx descriptor registers */
  77 #define R8169_TX_RING_BYTES     (NUM_TX_DESC * sizeof(struct TxDesc))
  78 #define R8169_RX_RING_BYTES     (NUM_RX_DESC * sizeof(struct RxDesc))
  79
  80 /* write/read MMIO register */
  81 #define RTL_W8(tp, reg, val8)   writeb((val8), tp->mmio_addr + (reg))
  82 #define RTL_W16(tp, reg, val16) writew((val16), tp->mmio_addr + (reg))
  83 #define RTL_W32(tp, reg, val32) writel((val32), tp->mmio_addr + (reg))
  84 #define RTL_R8(tp, reg)         readb(tp->mmio_addr + (reg))
  85 #define RTL_R16(tp, reg)                readw(tp->mmio_addr + (reg))
  86 #define RTL_R32(tp, reg)                readl(tp->mmio_addr + (reg))
  87
  88 enum mac_version {
  89         RTL_GIGA_MAC_VER_01 = 0,
  90         RTL_GIGA_MAC_VER_02,
  91         RTL_GIGA_MAC_VER_03,
  92         RTL_GIGA_MAC_VER_04,
  93         RTL_GIGA_MAC_VER_05,
  94         RTL_GIGA_MAC_VER_06,
  95         RTL_GIGA_MAC_VER_07,
  96         RTL_GIGA_MAC_VER_08,
  97         RTL_GIGA_MAC_VER_09,
  98         RTL_GIGA_MAC_VER_10,
  99         RTL_GIGA_MAC_VER_11,
 100         RTL_GIGA_MAC_VER_12,
 101         RTL_GIGA_MAC_VER_13,
 102         RTL_GIGA_MAC_VER_14,
 103         RTL_GIGA_MAC_VER_15,
 104         RTL_GIGA_MAC_VER_16,
 105         RTL_GIGA_MAC_VER_17,
 106         RTL_GIGA_MAC_VER_18,
 107         RTL_GIGA_MAC_VER_19,
 108         RTL_GIGA_MAC_VER_20,
 109         RTL_GIGA_MAC_VER_21,
 110         RTL_GIGA_MAC_VER_22,
 111         RTL_GIGA_MAC_VER_23,
 112         RTL_GIGA_MAC_VER_24,
 113         RTL_GIGA_MAC_VER_25,
 114         RTL_GIGA_MAC_VER_26,
 115         RTL_GIGA_MAC_VER_27,
 116         RTL_GIGA_MAC_VER_28,
 117         RTL_GIGA_MAC_VER_29,
 118         RTL_GIGA_MAC_VER_30,
 119         RTL_GIGA_MAC_VER_31,
 120         RTL_GIGA_MAC_VER_32,
 121         RTL_GIGA_MAC_VER_33,
 122         RTL_GIGA_MAC_VER_34,
 123         RTL_GIGA_MAC_VER_35,
 124         RTL_GIGA_MAC_VER_36,
 125         RTL_GIGA_MAC_VER_37,
 126         RTL_GIGA_MAC_VER_38,
 127         RTL_GIGA_MAC_VER_39,
 128         RTL_GIGA_MAC_VER_40,
 129         RTL_GIGA_MAC_VER_41,
 130         RTL_GIGA_MAC_VER_42,
 131         RTL_GIGA_MAC_VER_43,
 132         RTL_GIGA_MAC_VER_44,
 133         RTL_GIGA_MAC_VER_45,
 134         RTL_GIGA_MAC_VER_46,
 135         RTL_GIGA_MAC_VER_47,
 136         RTL_GIGA_MAC_VER_48,
 137         RTL_GIGA_MAC_VER_49,
 138         RTL_GIGA_MAC_VER_50,
 139         RTL_GIGA_MAC_VER_51,
 140         RTL_GIGA_MAC_NONE   = 0xff,
 141 };
 142
 143 #define JUMBO_1K        ETH_DATA_LEN
 144 #define JUMBO_4K        (4*1024 - ETH_HLEN - 2)
 145 #define JUMBO_6K        (6*1024 - ETH_HLEN - 2)
 146 #define JUMBO_7K        (7*1024 - ETH_HLEN - 2)
 147 #define JUMBO_9K        (9*1024 - ETH_HLEN - 2)
 148
 149 static const struct {
 150         const char *name;
 151         const char *fw_name;
 152 } rtl_chip_infos[] = {
 153         /* PCI devices. */
 154         [RTL_GIGA_MAC_VER_01] = {"RTL8169"                              },
 155         [RTL_GIGA_MAC_VER_02] = {"RTL8169s"                             },
 156         [RTL_GIGA_MAC_VER_03] = {"RTL8110s"                             },
 157         [RTL_GIGA_MAC_VER_04] = {"RTL8169sb/8110sb"                     },
 158         [RTL_GIGA_MAC_VER_05] = {"RTL8169sc/8110sc"                     },
 159         [RTL_GIGA_MAC_VER_06] = {"RTL8169sc/8110sc"                     },
 160         /* PCI-E devices. */
 161         [RTL_GIGA_MAC_VER_07] = {"RTL8102e"                             },
 162         [RTL_GIGA_MAC_VER_08] = {"RTL8102e"                             },
 163         [RTL_GIGA_MAC_VER_09] = {"RTL8102e"                             },
 164         [RTL_GIGA_MAC_VER_10] = {"RTL8101e"                             },
 165         [RTL_GIGA_MAC_VER_11] = {"RTL8168b/8111b"                       },
 166         [RTL_GIGA_MAC_VER_12] = {"RTL8168b/8111b"                       },
 167         [RTL_GIGA_MAC_VER_13] = {"RTL8101e"                             },
 168         [RTL_GIGA_MAC_VER_14] = {"RTL8100e"                             },
 169         [RTL_GIGA_MAC_VER_15] = {"RTL8100e"                             },
 170         [RTL_GIGA_MAC_VER_16] = {"RTL8101e"                             },
 171         [RTL_GIGA_MAC_VER_17] = {"RTL8168b/8111b"                       },
 172         [RTL_GIGA_MAC_VER_18] = {"RTL8168cp/8111cp"                     },
 173         [RTL_GIGA_MAC_VER_19] = {"RTL8168c/8111c"                       },
 174         [RTL_GIGA_MAC_VER_20] = {"RTL8168c/8111c"                       },
 175         [RTL_GIGA_MAC_VER_21] = {"RTL8168c/8111c"                       },
 176         [RTL_GIGA_MAC_VER_22] = {"RTL8168c/8111c"                       },
 177         [RTL_GIGA_MAC_VER_23] = {"RTL8168cp/8111cp"                     },
 178         [RTL_GIGA_MAC_VER_24] = {"RTL8168cp/8111cp"                     },
 179         [RTL_GIGA_MAC_VER_25] = {"RTL8168d/8111d",      FIRMWARE_8168D_1},
 180         [RTL_GIGA_MAC_VER_26] = {"RTL8168d/8111d",      FIRMWARE_8168D_2},
 181         [RTL_GIGA_MAC_VER_27] = {"RTL8168dp/8111dp"                     },
 182         [RTL_GIGA_MAC_VER_28] = {"RTL8168dp/8111dp"                     },
 183         [RTL_GIGA_MAC_VER_29] = {"RTL8105e",            FIRMWARE_8105E_1},
 184         [RTL_GIGA_MAC_VER_30] = {"RTL8105e",            FIRMWARE_8105E_1},
 185         [RTL_GIGA_MAC_VER_31] = {"RTL8168dp/8111dp"                     },
 186         [RTL_GIGA_MAC_VER_32] = {"RTL8168e/8111e",      FIRMWARE_8168E_1},
 187         [RTL_GIGA_MAC_VER_33] = {"RTL8168e/8111e",      FIRMWARE_8168E_2},
 188         [RTL_GIGA_MAC_VER_34] = {"RTL8168evl/8111evl",  FIRMWARE_8168E_3},
 189         [RTL_GIGA_MAC_VER_35] = {"RTL8168f/8111f",      FIRMWARE_8168F_1},
 190         [RTL_GIGA_MAC_VER_36] = {"RTL8168f/8111f",      FIRMWARE_8168F_2},
 191         [RTL_GIGA_MAC_VER_37] = {"RTL8402",             FIRMWARE_8402_1 },
 192         [RTL_GIGA_MAC_VER_38] = {"RTL8411",             FIRMWARE_8411_1 },
 193         [RTL_GIGA_MAC_VER_39] = {"RTL8106e",            FIRMWARE_8106E_1},
 194         [RTL_GIGA_MAC_VER_40] = {"RTL8168g/8111g",      FIRMWARE_8168G_2},
 195         [RTL_GIGA_MAC_VER_41] = {"RTL8168g/8111g"                       },
 196         [RTL_GIGA_MAC_VER_42] = {"RTL8168g/8111g",      FIRMWARE_8168G_3},
 197         [RTL_GIGA_MAC_VER_43] = {"RTL8106e",            FIRMWARE_8106E_2},
 198         [RTL_GIGA_MAC_VER_44] = {"RTL8411",             FIRMWARE_8411_2 },
 199         [RTL_GIGA_MAC_VER_45] = {"RTL8168h/8111h",      FIRMWARE_8168H_1},
 200         [RTL_GIGA_MAC_VER_46] = {"RTL8168h/8111h",      FIRMWARE_8168H_2},
 201         [RTL_GIGA_MAC_VER_47] = {"RTL8107e",            FIRMWARE_8107E_1},
 202         [RTL_GIGA_MAC_VER_48] = {"RTL8107e",            FIRMWARE_8107E_2},
 203         [RTL_GIGA_MAC_VER_49] = {"RTL8168ep/8111ep"                     },
 204         [RTL_GIGA_MAC_VER_50] = {"RTL8168ep/8111ep"                     },
 205         [RTL_GIGA_MAC_VER_51] = {"RTL8168ep/8111ep"                     },
 206 };
 207
 208 enum cfg_version {
 209         RTL_CFG_0 = 0x00,
 210         RTL_CFG_1,
 211         RTL_CFG_2
 212 };
 213
 214 static const struct pci_device_id rtl8169_pci_tbl[] = {
 215         { PCI_VDEVICE(REALTEK,  0x8129), RTL_CFG_0 },
 216         { PCI_VDEVICE(REALTEK,  0x8136), RTL_CFG_2 },
 217         { PCI_VDEVICE(REALTEK,  0x8161), RTL_CFG_1 },
 218         { PCI_VDEVICE(REALTEK,  0x8167), RTL_CFG_0 },
 219         { PCI_VDEVICE(REALTEK,  0x8168), RTL_CFG_1 },
 220         { PCI_VDEVICE(NCUBE,    0x8168), RTL_CFG_1 },
 221         { PCI_VDEVICE(REALTEK,  0x8169), RTL_CFG_0 },
 222         { PCI_VENDOR_ID_DLINK,  0x4300,
 223                 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0, RTL_CFG_1 },
 224         { PCI_VDEVICE(DLINK,    0x4300), RTL_CFG_0 },
 225         { PCI_VDEVICE(DLINK,    0x4302), RTL_CFG_0 },
 226         { PCI_VDEVICE(AT,       0xc107), RTL_CFG_0 },
 227         { PCI_VDEVICE(USR,      0x0116), RTL_CFG_0 },
 228         { PCI_VENDOR_ID_LINKSYS,                0x1032,
 229                 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
 230         { 0x0001,                               0x8168,
 231                 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
 232         {}
 233 };
 234
 235 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
 236
 237 static int use_dac = -1;
 238 static struct {
 239         u32 msg_enable;
 240 } debug = { -1 };
 241
 242 enum rtl_registers {
 243         MAC0            = 0,    /* Ethernet hardware address. */
 244         MAC4            = 4,
 245         MAR0            = 8,    /* Multicast filter. */
 246         CounterAddrLow          = 0x10,
 247         CounterAddrHigh         = 0x14,
 248         TxDescStartAddrLow      = 0x20,
 249         TxDescStartAddrHigh     = 0x24,
 250         TxHDescStartAddrLow     = 0x28,
 251         TxHDescStartAddrHigh    = 0x2c,
 252         FLASH           = 0x30,
 253         ERSR            = 0x36,
 254         ChipCmd         = 0x37,
 255         TxPoll          = 0x38,
 256         IntrMask        = 0x3c,
 257         IntrStatus      = 0x3e,
 258
 259         TxConfig        = 0x40,
 260 #define TXCFG_AUTO_FIFO                 (1 << 7)        /* 8111e-vl */
 261 #define TXCFG_EMPTY                     (1 << 11)       /* 8111e-vl */
 262
 263         RxConfig        = 0x44,
 264 #define RX128_INT_EN                    (1 << 15)       /* 8111c and later */
 265 #define RX_MULTI_EN                     (1 << 14)       /* 8111c only */
 266 #define RXCFG_FIFO_SHIFT                13
 267                                         /* No threshold before first PCI xfer */
 268 #define RX_FIFO_THRESH                  (7 << RXCFG_FIFO_SHIFT)
 269 #define RX_EARLY_OFF                    (1 << 11)
 270 #define RXCFG_DMA_SHIFT                 8
 271                                         /* Unlimited maximum PCI burst. */
 272 #define RX_DMA_BURST                    (7 << RXCFG_DMA_SHIFT)
 273
 274         RxMissed        = 0x4c,
 275         Cfg9346         = 0x50,
 276         Config0         = 0x51,
 277         Config1         = 0x52,
 278         Config2         = 0x53,
 279 #define PME_SIGNAL                      (1 << 5)        /* 8168c and later */
 280
 281         Config3         = 0x54,
 282         Config4         = 0x55,
 283         Config5         = 0x56,
 284         MultiIntr       = 0x5c,
 285         PHYAR           = 0x60,
 286         PHYstatus       = 0x6c,
 287         RxMaxSize       = 0xda,
 288         CPlusCmd        = 0xe0,
 289         IntrMitigate    = 0xe2,
 290
 291 #define RTL_COALESCE_MASK       0x0f
 292 #define RTL_COALESCE_SHIFT      4
 293 #define RTL_COALESCE_T_MAX      (RTL_COALESCE_MASK)
 294 #define RTL_COALESCE_FRAME_MAX  (RTL_COALESCE_MASK << 2)
 295
 296         RxDescAddrLow   = 0xe4,
 297         RxDescAddrHigh  = 0xe8,
 298         EarlyTxThres    = 0xec, /* 8169. Unit of 32 bytes. */
 299
 300 #define NoEarlyTx       0x3f    /* Max value : no early transmit. */
 301
 302         MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
 303
 304 #define TxPacketMax     (8064 >> 7)
 305 #define EarlySize       0x27
 306
 307         FuncEvent       = 0xf0,
 308         FuncEventMask   = 0xf4,
 309         FuncPresetState = 0xf8,
 310         IBCR0           = 0xf8,
 311         IBCR2           = 0xf9,
 312         IBIMR0          = 0xfa,
 313         IBISR0          = 0xfb,
 314         FuncForceEvent  = 0xfc,
 315 };
 316
 317 enum rtl8168_8101_registers {
 318         CSIDR                   = 0x64,
 319         CSIAR                   = 0x68,
 320 #define CSIAR_FLAG                      0x80000000
 321 #define CSIAR_WRITE_CMD                 0x80000000
 322 #define CSIAR_BYTE_ENABLE               0x0000f000
 323 #define CSIAR_ADDR_MASK                 0x00000fff
 324         PMCH                    = 0x6f,
 325         EPHYAR                  = 0x80,
 326 #define EPHYAR_FLAG                     0x80000000
 327 #define EPHYAR_WRITE_CMD                0x80000000
 328 #define EPHYAR_REG_MASK                 0x1f
 329 #define EPHYAR_REG_SHIFT                16
 330 #define EPHYAR_DATA_MASK                0xffff
 331         DLLPR                   = 0xd0,
 332 #define PFM_EN                          (1 << 6)
 333 #define TX_10M_PS_EN                    (1 << 7)
 334         DBG_REG                 = 0xd1,
 335 #define FIX_NAK_1                       (1 << 4)
 336 #define FIX_NAK_2                       (1 << 3)
 337         TWSI                    = 0xd2,
 338         MCU                     = 0xd3,
 339 #define NOW_IS_OOB                      (1 << 7)
 340 #define TX_EMPTY                        (1 << 5)
 341 #define RX_EMPTY                        (1 << 4)
 342 #define RXTX_EMPTY                      (TX_EMPTY | RX_EMPTY)
 343 #define EN_NDP                          (1 << 3)
 344 #define EN_OOB_RESET                    (1 << 2)
 345 #define LINK_LIST_RDY                   (1 << 1)
 346         EFUSEAR                 = 0xdc,
 347 #define EFUSEAR_FLAG                    0x80000000
 348 #define EFUSEAR_WRITE_CMD               0x80000000
 349 #define EFUSEAR_READ_CMD                0x00000000
 350 #define EFUSEAR_REG_MASK                0x03ff
 351 #define EFUSEAR_REG_SHIFT               8
 352 #define EFUSEAR_DATA_MASK               0xff
 353         MISC_1                  = 0xf2,
 354 #define PFM_D3COLD_EN                   (1 << 6)
 355 };
 356
 357 enum rtl8168_registers {
 358         LED_FREQ                = 0x1a,
 359         EEE_LED                 = 0x1b,
 360         ERIDR                   = 0x70,
 361         ERIAR                   = 0x74,
 362 #define ERIAR_FLAG                      0x80000000
 363 #define ERIAR_WRITE_CMD                 0x80000000
 364 #define ERIAR_READ_CMD                  0x00000000
 365 #define ERIAR_ADDR_BYTE_ALIGN           4
 366 #define ERIAR_TYPE_SHIFT                16
 367 #define ERIAR_EXGMAC                    (0x00 << ERIAR_TYPE_SHIFT)
 368 #define ERIAR_MSIX                      (0x01 << ERIAR_TYPE_SHIFT)
 369 #define ERIAR_ASF                       (0x02 << ERIAR_TYPE_SHIFT)
 370 #define ERIAR_OOB                       (0x02 << ERIAR_TYPE_SHIFT)
 371 #define ERIAR_MASK_SHIFT                12
 372 #define ERIAR_MASK_0001                 (0x1 << ERIAR_MASK_SHIFT)
 373 #define ERIAR_MASK_0011                 (0x3 << ERIAR_MASK_SHIFT)
 374 #define ERIAR_MASK_0100                 (0x4 << ERIAR_MASK_SHIFT)
 375 #define ERIAR_MASK_0101                 (0x5 << ERIAR_MASK_SHIFT)
 376 #define ERIAR_MASK_1111                 (0xf << ERIAR_MASK_SHIFT)
 377         EPHY_RXER_NUM           = 0x7c,
 378         OCPDR                   = 0xb0, /* OCP GPHY access */
 379 #define OCPDR_WRITE_CMD                 0x80000000
 380 #define OCPDR_READ_CMD                  0x00000000
 381 #define OCPDR_REG_MASK                  0x7f
 382 #define OCPDR_GPHY_REG_SHIFT            16
 383 #define OCPDR_DATA_MASK                 0xffff
 384         OCPAR                   = 0xb4,
 385 #define OCPAR_FLAG                      0x80000000
 386 #define OCPAR_GPHY_WRITE_CMD            0x8000f060
 387 #define OCPAR_GPHY_READ_CMD             0x0000f060
 388         GPHY_OCP                = 0xb8,
 389         RDSAR1                  = 0xd0, /* 8168c only. Undocumented on 8168dp */
 390         MISC                    = 0xf0, /* 8168e only. */
 391 #define TXPLA_RST                       (1 << 29)
 392 #define DISABLE_LAN_EN                  (1 << 23) /* Enable GPIO pin */
 393 #define PWM_EN                          (1 << 22)
 394 #define RXDV_GATED_EN                   (1 << 19)
 395 #define EARLY_TALLY_EN                  (1 << 16)
 396 };
 397
 398 enum rtl_register_content {
 399         /* InterruptStatusBits */
 400         SYSErr          = 0x8000,
 401         PCSTimeout      = 0x4000,
 402         SWInt           = 0x0100,
 403         TxDescUnavail   = 0x0080,
 404         RxFIFOOver      = 0x0040,
 405         LinkChg         = 0x0020,
 406         RxOverflow      = 0x0010,
 407         TxErr           = 0x0008,
 408         TxOK            = 0x0004,
 409         RxErr           = 0x0002,
 410         RxOK            = 0x0001,
 411
 412         /* RxStatusDesc */
 413         RxBOVF  = (1 << 24),
 414         RxFOVF  = (1 << 23),
 415         RxRWT   = (1 << 22),
 416         RxRES   = (1 << 21),
 417         RxRUNT  = (1 << 20),
 418         RxCRC   = (1 << 19),
 419
 420         /* ChipCmdBits */
 421         StopReq         = 0x80,
 422         CmdReset        = 0x10,
 423         CmdRxEnb        = 0x08,
 424         CmdTxEnb        = 0x04,
 425         RxBufEmpty      = 0x01,
 426
 427         /* TXPoll register p.5 */
 428         HPQ             = 0x80,         /* Poll cmd on the high prio queue */
 429         NPQ             = 0x40,         /* Poll cmd on the low prio queue */
 430         FSWInt          = 0x01,         /* Forced software interrupt */
 431
 432         /* Cfg9346Bits */
 433         Cfg9346_Lock    = 0x00,
 434         Cfg9346_Unlock  = 0xc0,
 435
 436         /* rx_mode_bits */
 437         AcceptErr       = 0x20,
 438         AcceptRunt      = 0x10,
 439         AcceptBroadcast = 0x08,
 440         AcceptMulticast = 0x04,
 441         AcceptMyPhys    = 0x02,
 442         AcceptAllPhys   = 0x01,
 443 #define RX_CONFIG_ACCEPT_MASK           0x3f
 444
 445         /* TxConfigBits */
 446         TxInterFrameGapShift = 24,
 447         TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
 448
 449         /* Config1 register p.24 */
 450         LEDS1           = (1 << 7),
 451         LEDS0           = (1 << 6),
 452         Speed_down      = (1 << 4),
 453         MEMMAP          = (1 << 3),
 454         IOMAP           = (1 << 2),
 455         VPD             = (1 << 1),
 456         PMEnable        = (1 << 0),     /* Power Management Enable */
 457
 458         /* Config2 register p. 25 */
 459         ClkReqEn        = (1 << 7),     /* Clock Request Enable */
 460         MSIEnable       = (1 << 5),     /* 8169 only. Reserved in the 8168. */
 461         PCI_Clock_66MHz = 0x01,
 462         PCI_Clock_33MHz = 0x00,
 463
 464         /* Config3 register p.25 */
 465         MagicPacket     = (1 << 5),     /* Wake up when receives a Magic Packet */
 466         LinkUp          = (1 << 4),     /* Wake up when the cable connection is re-established */
 467         Jumbo_En0       = (1 << 2),     /* 8168 only. Reserved in the 8168b */
 468         Rdy_to_L23      = (1 << 1),     /* L23 Enable */
 469         Beacon_en       = (1 << 0),     /* 8168 only. Reserved in the 8168b */
 470
 471         /* Config4 register */
 472         Jumbo_En1       = (1 << 1),     /* 8168 only. Reserved in the 8168b */
 473
 474         /* Config5 register p.27 */
 475         BWF             = (1 << 6),     /* Accept Broadcast wakeup frame */
 476         MWF             = (1 << 5),     /* Accept Multicast wakeup frame */
 477         UWF             = (1 << 4),     /* Accept Unicast wakeup frame */
 478         Spi_en          = (1 << 3),
 479         LanWake         = (1 << 1),     /* LanWake enable/disable */
 480         PMEStatus       = (1 << 0),     /* PME status can be reset by PCI RST# */
 481         ASPM_en         = (1 << 0),     /* ASPM enable */
 482
 483         /* CPlusCmd p.31 */
 484         EnableBist      = (1 << 15),    // 8168 8101
 485         Mac_dbgo_oe     = (1 << 14),    // 8168 8101
 486         Normal_mode     = (1 << 13),    // unused
 487         Force_half_dup  = (1 << 12),    // 8168 8101
 488         Force_rxflow_en = (1 << 11),    // 8168 8101
 489         Force_txflow_en = (1 << 10),    // 8168 8101
 490         Cxpl_dbg_sel    = (1 << 9),     // 8168 8101
 491         ASF             = (1 << 8),     // 8168 8101
 492         PktCntrDisable  = (1 << 7),     // 8168 8101
 493         Mac_dbgo_sel    = 0x001c,       // 8168
 494         RxVlan          = (1 << 6),
 495         RxChkSum        = (1 << 5),
 496         PCIDAC          = (1 << 4),
 497         PCIMulRW        = (1 << 3),
 498 #define INTT_MASK       GENMASK(1, 0)
 499         INTT_0          = 0x0000,       // 8168
 500         INTT_1          = 0x0001,       // 8168
 501         INTT_2          = 0x0002,       // 8168
 502         INTT_3          = 0x0003,       // 8168
 503
 504         /* rtl8169_PHYstatus */
 505         TBI_Enable      = 0x80,
 506         TxFlowCtrl      = 0x40,
 507         RxFlowCtrl      = 0x20,
 508         _1000bpsF       = 0x10,
 509         _100bps         = 0x08,
 510         _10bps          = 0x04,
 511         LinkStatus      = 0x02,
 512         FullDup         = 0x01,
 513
 514         /* _TBICSRBit */
 515         TBILinkOK       = 0x02000000,
 516
 517         /* ResetCounterCommand */
 518         CounterReset    = 0x1,
 519
 520         /* DumpCounterCommand */
 521         CounterDump     = 0x8,
 522
 523         /* magic enable v2 */
 524         MagicPacket_v2  = (1 << 16),    /* Wake up when receives a Magic Packet */
 525 };
 526
 527 enum rtl_desc_bit {
 528         /* First doubleword. */
 529         DescOwn         = (1 << 31), /* Descriptor is owned by NIC */
 530         RingEnd         = (1 << 30), /* End of descriptor ring */
 531         FirstFrag       = (1 << 29), /* First segment of a packet */
 532         LastFrag        = (1 << 28), /* Final segment of a packet */
 533 };
 534
 535 /* Generic case. */
 536 enum rtl_tx_desc_bit {
 537         /* First doubleword. */
 538         TD_LSO          = (1 << 27),            /* Large Send Offload */
 539 #define TD_MSS_MAX                      0x07ffu /* MSS value */
 540
 541         /* Second doubleword. */
 542         TxVlanTag       = (1 << 17),            /* Add VLAN tag */
 543 };
 544
 545 /* 8169, 8168b and 810x except 8102e. */
 546 enum rtl_tx_desc_bit_0 {
 547         /* First doubleword. */
 548 #define TD0_MSS_SHIFT                   16      /* MSS position (11 bits) */
 549         TD0_TCP_CS      = (1 << 16),            /* Calculate TCP/IP checksum */
 550         TD0_UDP_CS      = (1 << 17),            /* Calculate UDP/IP checksum */
 551         TD0_IP_CS       = (1 << 18),            /* Calculate IP checksum */
 552 };
 553
 554 /* 8102e, 8168c and beyond. */
 555 enum rtl_tx_desc_bit_1 {
 556         /* First doubleword. */
 557         TD1_GTSENV4     = (1 << 26),            /* Giant Send for IPv4 */
 558         TD1_GTSENV6     = (1 << 25),            /* Giant Send for IPv6 */
 559 #define GTTCPHO_SHIFT                   18
 560 #define GTTCPHO_MAX                     0x7fU
 561
 562         /* Second doubleword. */
 563 #define TCPHO_SHIFT                     18
 564 #define TCPHO_MAX                       0x3ffU
 565 #define TD1_MSS_SHIFT                   18      /* MSS position (11 bits) */
 566         TD1_IPv6_CS     = (1 << 28),            /* Calculate IPv6 checksum */
 567         TD1_IPv4_CS     = (1 << 29),            /* Calculate IPv4 checksum */
 568         TD1_TCP_CS      = (1 << 30),            /* Calculate TCP/IP checksum */
 569         TD1_UDP_CS      = (1 << 31),            /* Calculate UDP/IP checksum */
 570 };
 571
 572 enum rtl_rx_desc_bit {
 573         /* Rx private */
 574         PID1            = (1 << 18), /* Protocol ID bit 1/2 */
 575         PID0            = (1 << 17), /* Protocol ID bit 0/2 */
 576
 577 #define RxProtoUDP      (PID1)
 578 #define RxProtoTCP      (PID0)
 579 #define RxProtoIP       (PID1 | PID0)
 580 #define RxProtoMask     RxProtoIP
 581
 582         IPFail          = (1 << 16), /* IP checksum failed */
 583         UDPFail         = (1 << 15), /* UDP/IP checksum failed */
 584         TCPFail         = (1 << 14), /* TCP/IP checksum failed */
 585         RxVlanTag       = (1 << 16), /* VLAN tag available */
 586 };
 587
 588 #define RsvdMask        0x3fffc000
 589 #define CPCMD_QUIRK_MASK        (Normal_mode | RxVlan | RxChkSum | INTT_MASK)
 590
 591 struct TxDesc {
 592         __le32 opts1;
 593         __le32 opts2;
 594         __le64 addr;
 595 };
 596
 597 struct RxDesc {
 598         __le32 opts1;
 599         __le32 opts2;
 600         __le64 addr;
 601 };
 602
 603 struct ring_info {
 604         struct sk_buff  *skb;
 605         u32             len;
 606 };
 607
 608 struct rtl8169_counters {
 609         __le64  tx_packets;
 610         __le64  rx_packets;
 611         __le64  tx_errors;
 612         __le32  rx_errors;
 613         __le16  rx_missed;
 614         __le16  align_errors;
 615         __le32  tx_one_collision;
 616         __le32  tx_multi_collision;
 617         __le64  rx_unicast;
 618         __le64  rx_broadcast;
 619         __le32  rx_multicast;
 620         __le16  tx_aborted;
 621         __le16  tx_underun;
 622 };
 623
 624 struct rtl8169_tc_offsets {
 625         bool    inited;
 626         __le64  tx_errors;
 627         __le32  tx_multi_collision;
 628         __le16  tx_aborted;
 629 };
 630
 631 enum rtl_flag {
 632         RTL_FLAG_TASK_ENABLED = 0,
 633         RTL_FLAG_TASK_RESET_PENDING,
 634         RTL_FLAG_MAX
 635 };
 636
 637 struct rtl8169_stats {
 638         u64                     packets;
 639         u64                     bytes;
 640         struct u64_stats_sync   syncp;
 641 };
 642
 643 struct rtl8169_private {
 644         void __iomem *mmio_addr;        /* memory map physical address */
 645         struct pci_dev *pci_dev;
 646         struct net_device *dev;
 647         struct napi_struct napi;
 648         u32 msg_enable;
 649         u16 mac_version;
 650         u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
 651         u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
 652         u32 dirty_tx;
 653         struct rtl8169_stats rx_stats;
 654         struct rtl8169_stats tx_stats;
 655         struct TxDesc *TxDescArray;     /* 256-aligned Tx descriptor ring */
 656         struct RxDesc *RxDescArray;     /* 256-aligned Rx descriptor ring */
 657         dma_addr_t TxPhyAddr;
 658         dma_addr_t RxPhyAddr;
 659         void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
 660         struct ring_info tx_skb[NUM_TX_DESC];   /* Tx data buffers */
 661         u16 cp_cmd;
 662
 663         u16 irq_mask;
 664         const struct rtl_coalesce_info *coalesce_info;
 665         struct clk *clk;
 666
 667         struct mdio_ops {
 668                 void (*write)(struct rtl8169_private *, int, int);
 669                 int (*read)(struct rtl8169_private *, int);
 670         } mdio_ops;
 671
 672         struct jumbo_ops {
 673                 void (*enable)(struct rtl8169_private *);
 674                 void (*disable)(struct rtl8169_private *);
 675         } jumbo_ops;
 676
 677         void (*hw_start)(struct rtl8169_private *tp);
 678         bool (*tso_csum)(struct rtl8169_private *, struct sk_buff *, u32 *);
 679
 680         struct {
 681                 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
 682                 struct mutex mutex;
 683                 struct work_struct work;
 684         } wk;
 685
 686         unsigned supports_gmii:1;
 687         struct mii_bus *mii_bus;
 688         dma_addr_t counters_phys_addr;
 689         struct rtl8169_counters *counters;
 690         struct rtl8169_tc_offsets tc_offset;
 691         u32 saved_wolopts;
 692
 693         struct rtl_fw {
 694                 const struct firmware *fw;
 695
 696 #define RTL_VER_SIZE            32
 697
 698                 char version[RTL_VER_SIZE];
 699
 700                 struct rtl_fw_phy_action {
 701                         __le32 *code;
 702                         size_t size;
 703                 } phy_action;
 704         } *rtl_fw;
 705 #define RTL_FIRMWARE_UNKNOWN    ERR_PTR(-EAGAIN)
 706
 707         u32 ocp_base;
 708 };
 709
 710 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
 711 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
 712 module_param(use_dac, int, 0);
 713 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
 714 module_param_named(debug, debug.msg_enable, int, 0);
 715 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
 716 MODULE_LICENSE("GPL");
 717 MODULE_FIRMWARE(FIRMWARE_8168D_1);
 718 MODULE_FIRMWARE(FIRMWARE_8168D_2);
 719 MODULE_FIRMWARE(FIRMWARE_8168E_1);
 720 MODULE_FIRMWARE(FIRMWARE_8168E_2);
 721 MODULE_FIRMWARE(FIRMWARE_8168E_3);
 722 MODULE_FIRMWARE(FIRMWARE_8105E_1);
 723 MODULE_FIRMWARE(FIRMWARE_8168F_1);
 724 MODULE_FIRMWARE(FIRMWARE_8168F_2);
 725 MODULE_FIRMWARE(FIRMWARE_8402_1);
 726 MODULE_FIRMWARE(FIRMWARE_8411_1);
 727 MODULE_FIRMWARE(FIRMWARE_8411_2);
 728 MODULE_FIRMWARE(FIRMWARE_8106E_1);
 729 MODULE_FIRMWARE(FIRMWARE_8106E_2);
 730 MODULE_FIRMWARE(FIRMWARE_8168G_2);
 731 MODULE_FIRMWARE(FIRMWARE_8168G_3);
 732 MODULE_FIRMWARE(FIRMWARE_8168H_1);
 733 MODULE_FIRMWARE(FIRMWARE_8168H_2);
 734 MODULE_FIRMWARE(FIRMWARE_8107E_1);
 735 MODULE_FIRMWARE(FIRMWARE_8107E_2);
 736
 737 static inline struct device *tp_to_dev(struct rtl8169_private *tp)
 738 {
 739         return &tp->pci_dev->dev;
 740 }
 741
 742 static void rtl_lock_work(struct rtl8169_private *tp)
 743 {
 744         mutex_lock(&tp->wk.mutex);
 745 }
 746
 747 static void rtl_unlock_work(struct rtl8169_private *tp)
 748 {
 749         mutex_unlock(&tp->wk.mutex);
 750 }
 751
 752 static void rtl_tx_performance_tweak(struct rtl8169_private *tp, u16 force)
 753 {
 754         pcie_capability_clear_and_set_word(tp->pci_dev, PCI_EXP_DEVCTL,
 755                                            PCI_EXP_DEVCTL_READRQ, force);
 756 }
 757
 758 struct rtl_cond {
 759         bool (*check)(struct rtl8169_private *);
 760         const char *msg;
 761 };
 762
 763 static void rtl_udelay(unsigned int d)
 764 {
 765         udelay(d);
 766 }
 767
 768 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,
 769                           void (*delay)(unsigned int), unsigned int d, int n,
 770                           bool high)
 771 {
 772         int i;
 773
 774         for (i = 0; i < n; i++) {
 775                 delay(d);
 776                 if (c->check(tp) == high)
 777                         return true;
 778         }
 779         netif_err(tp, drv, tp->dev, "%s == %d (loop: %d, delay: %d).\n",
 780                   c->msg, !high, n, d);
 781         return false;
 782 }
 783
 784 static bool rtl_udelay_loop_wait_high(struct rtl8169_private *tp,
 785                                       const struct rtl_cond *c,
 786                                       unsigned int d, int n)
 787 {
 788         return rtl_loop_wait(tp, c, rtl_udelay, d, n, true);
 789 }
 790
 791 static bool rtl_udelay_loop_wait_low(struct rtl8169_private *tp,
 792                                      const struct rtl_cond *c,
 793                                      unsigned int d, int n)
 794 {
 795         return rtl_loop_wait(tp, c, rtl_udelay, d, n, false);
 796 }
 797
 798 static bool rtl_msleep_loop_wait_high(struct rtl8169_private *tp,
 799                                       const struct rtl_cond *c,
 800                                       unsigned int d, int n)
 801 {
 802         return rtl_loop_wait(tp, c, msleep, d, n, true);
 803 }
 804
 805 static bool rtl_msleep_loop_wait_low(struct rtl8169_private *tp,
 806                                      const struct rtl_cond *c,
 807                                      unsigned int d, int n)
 808 {
 809         return rtl_loop_wait(tp, c, msleep, d, n, false);
 810 }
 811
 812 #define DECLARE_RTL_COND(name)                          \
 813 static bool name ## _check(struct rtl8169_private *);   \
 814                                                         \
 815 static const struct rtl_cond name = {                   \
 816         .check  = name ## _check,                       \
 817         .msg    = #name                                 \
 818 };                                                      \
 819                                                         \
 820 static bool name ## _check(struct rtl8169_private *tp)
 821
 822 static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg)
 823 {
 824         if (reg & 0xffff0001) {
 825                 netif_err(tp, drv, tp->dev, "Invalid ocp reg %x!\n", reg);
 826                 return true;
 827         }
 828         return false;
 829 }
 830
 831 DECLARE_RTL_COND(rtl_ocp_gphy_cond)
 832 {
 833         return RTL_R32(tp, GPHY_OCP) & OCPAR_FLAG;
 834 }
 835
 836 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
 837 {
 838         if (rtl_ocp_reg_failure(tp, reg))
 839                 return;
 840
 841         RTL_W32(tp, GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);
 842
 843         rtl_udelay_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);
 844 }
 845
 846 static u16 r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
 847 {
 848         if (rtl_ocp_reg_failure(tp, reg))
 849                 return 0;
 850
 851         RTL_W32(tp, GPHY_OCP, reg << 15);
 852
 853         return rtl_udelay_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?
 854                 (RTL_R32(tp, GPHY_OCP) & 0xffff) : ~0;
 855 }
 856
 857 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
 858 {
 859         if (rtl_ocp_reg_failure(tp, reg))
 860                 return;
 861
 862         RTL_W32(tp, OCPDR, OCPAR_FLAG | (reg << 15) | data);
 863 }
 864
 865 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
 866 {
 867         if (rtl_ocp_reg_failure(tp, reg))
 868                 return 0;
 869
 870         RTL_W32(tp, OCPDR, reg << 15);
 871
 872         return RTL_R32(tp, OCPDR);
 873 }
 874
 875 #define OCP_STD_PHY_BASE        0xa400
 876
 877 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)
 878 {
 879         if (reg == 0x1f) {
 880                 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;
 881                 return;
 882         }
 883
 884         if (tp->ocp_base != OCP_STD_PHY_BASE)
 885                 reg -= 0x10;
 886
 887         r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);
 888 }
 889
 890 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)
 891 {
 892         if (tp->ocp_base != OCP_STD_PHY_BASE)
 893                 reg -= 0x10;
 894
 895         return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);
 896 }
 897
 898 static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value)
 899 {
 900         if (reg == 0x1f) {
 901                 tp->ocp_base = value << 4;
 902                 return;
 903         }
 904
 905         r8168_mac_ocp_write(tp, tp->ocp_base + reg, value);
 906 }
 907
 908 static int mac_mcu_read(struct rtl8169_private *tp, int reg)
 909 {
 910         return r8168_mac_ocp_read(tp, tp->ocp_base + reg);
 911 }
 912
 913 DECLARE_RTL_COND(rtl_phyar_cond)
 914 {
 915         return RTL_R32(tp, PHYAR) & 0x80000000;
 916 }
 917
 918 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)
 919 {
 920         RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
 921
 922         rtl_udelay_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);
 923         /*
 924          * According to hardware specs a 20us delay is required after write
 925          * complete indication, but before sending next command.
 926          */
 927         udelay(20);
 928 }
 929
 930 static int r8169_mdio_read(struct rtl8169_private *tp, int reg)
 931 {
 932         int value;
 933
 934         RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16);
 935
 936         value = rtl_udelay_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?
 937                 RTL_R32(tp, PHYAR) & 0xffff : ~0;
 938
 939         /*
 940          * According to hardware specs a 20us delay is required after read
 941          * complete indication, but before sending next command.
 942          */
 943         udelay(20);
 944
 945         return value;
 946 }
 947
 948 DECLARE_RTL_COND(rtl_ocpar_cond)
 949 {
 950         return RTL_R32(tp, OCPAR) & OCPAR_FLAG;
 951 }
 952
 953 static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data)
 954 {
 955         RTL_W32(tp, OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
 956         RTL_W32(tp, OCPAR, OCPAR_GPHY_WRITE_CMD);
 957         RTL_W32(tp, EPHY_RXER_NUM, 0);
 958
 959         rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100);
 960 }
 961
 962 static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value)
 963 {
 964         r8168dp_1_mdio_access(tp, reg,
 965                               OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK));
 966 }
 967
 968 static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg)
 969 {
 970         r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD);
 971
 972         mdelay(1);
 973         RTL_W32(tp, OCPAR, OCPAR_GPHY_READ_CMD);
 974         RTL_W32(tp, EPHY_RXER_NUM, 0);
 975
 976         return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ?
 977                 RTL_R32(tp, OCPDR) & OCPDR_DATA_MASK : ~0;
 978 }
 979
 980 #define R8168DP_1_MDIO_ACCESS_BIT       0x00020000
 981
 982 static void r8168dp_2_mdio_start(struct rtl8169_private *tp)
 983 {
 984         RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
 985 }
 986
 987 static void r8168dp_2_mdio_stop(struct rtl8169_private *tp)
 988 {
 989         RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
 990 }
 991
 992 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)
 993 {
 994         r8168dp_2_mdio_start(tp);
 995
 996         r8169_mdio_write(tp, reg, value);
 997
 998         r8168dp_2_mdio_stop(tp);
 999 }
1000
1001 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)
1002 {
1003         int value;
1004
1005         r8168dp_2_mdio_start(tp);
1006
1007         value = r8169_mdio_read(tp, reg);
1008
1009         r8168dp_2_mdio_stop(tp);
1010
1011         return value;
1012 }
1013
1014 static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
1015 {
1016         tp->mdio_ops.write(tp, location, val);
1017 }
1018
1019 static int rtl_readphy(struct rtl8169_private *tp, int location)
1020 {
1021         return tp->mdio_ops.read(tp, location);
1022 }
1023
1024 static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
1025 {
1026         rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
1027 }
1028
1029 static void rtl_w0w1_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
1030 {
1031         int val;
1032
1033         val = rtl_readphy(tp, reg_addr);
1034         rtl_writephy(tp, reg_addr, (val & ~m) | p);
1035 }
1036
1037 DECLARE_RTL_COND(rtl_ephyar_cond)
1038 {
1039         return RTL_R32(tp, EPHYAR) & EPHYAR_FLAG;
1040 }
1041
1042 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)
1043 {
1044         RTL_W32(tp, EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1045                 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1046
1047         rtl_udelay_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);
1048
1049         udelay(10);
1050 }
1051
1052 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)
1053 {
1054         RTL_W32(tp, EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1055
1056         return rtl_udelay_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?
1057                 RTL_R32(tp, EPHYAR) & EPHYAR_DATA_MASK : ~0;
1058 }
1059
1060 DECLARE_RTL_COND(rtl_eriar_cond)
1061 {
1062         return RTL_R32(tp, ERIAR) & ERIAR_FLAG;
1063 }
1064
1065 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1066                           u32 val, int type)
1067 {
1068         BUG_ON((addr & 3) || (mask == 0));
1069         RTL_W32(tp, ERIDR, val);
1070         RTL_W32(tp, ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
1071
1072         rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);
1073 }
1074
1075 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
1076 {
1077         RTL_W32(tp, ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
1078
1079         return rtl_udelay_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?
1080                 RTL_R32(tp, ERIDR) : ~0;
1081 }
1082
1083 static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 mask, u32 p,
1084                          u32 m, int type)
1085 {
1086         u32 val;
1087
1088         val = rtl_eri_read(tp, addr, type);
1089         rtl_eri_write(tp, addr, mask, (val & ~m) | p, type);
1090 }
1091
1092 static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1093 {
1094         RTL_W32(tp, OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1095         return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?
1096                 RTL_R32(tp, OCPDR) : ~0;
1097 }
1098
1099 static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1100 {
1101         return rtl_eri_read(tp, reg, ERIAR_OOB);
1102 }
1103
1104 static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1105                               u32 data)
1106 {
1107         RTL_W32(tp, OCPDR, data);
1108         RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1109         rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);
1110 }
1111
1112 static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1113                               u32 data)
1114 {
1115         rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT,
1116                       data, ERIAR_OOB);
1117 }
1118
1119 static void r8168dp_oob_notify(struct rtl8169_private *tp, u8 cmd)
1120 {
1121         rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd, ERIAR_EXGMAC);
1122
1123         r8168dp_ocp_write(tp, 0x1, 0x30, 0x00000001);
1124 }
1125
1126 #define OOB_CMD_RESET           0x00
1127 #define OOB_CMD_DRIVER_START    0x05
1128 #define OOB_CMD_DRIVER_STOP     0x06
1129
1130 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
1131 {
1132         return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
1133 }
1134
1135 DECLARE_RTL_COND(rtl_dp_ocp_read_cond)
1136 {
1137         u16 reg;
1138
1139         reg = rtl8168_get_ocp_reg(tp);
1140
1141         return r8168dp_ocp_read(tp, 0x0f, reg) & 0x00000800;
1142 }
1143
1144 DECLARE_RTL_COND(rtl_ep_ocp_read_cond)
1145 {
1146         return r8168ep_ocp_read(tp, 0x0f, 0x124) & 0x00000001;
1147 }
1148
1149 DECLARE_RTL_COND(rtl_ocp_tx_cond)
1150 {
1151         return RTL_R8(tp, IBISR0) & 0x20;
1152 }
1153
1154 static void rtl8168ep_stop_cmac(struct rtl8169_private *tp)
1155 {
1156         RTL_W8(tp, IBCR2, RTL_R8(tp, IBCR2) & ~0x01);
1157         rtl_msleep_loop_wait_high(tp, &rtl_ocp_tx_cond, 50, 2000);
1158         RTL_W8(tp, IBISR0, RTL_R8(tp, IBISR0) | 0x20);
1159         RTL_W8(tp, IBCR0, RTL_R8(tp, IBCR0) & ~0x01);
1160 }
1161
1162 static void rtl8168dp_driver_start(struct rtl8169_private *tp)
1163 {
1164         r8168dp_oob_notify(tp, OOB_CMD_DRIVER_START);
1165         rtl_msleep_loop_wait_high(tp, &rtl_dp_ocp_read_cond, 10, 10);
1166 }
1167
1168 static void rtl8168ep_driver_start(struct rtl8169_private *tp)
1169 {
1170         r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START);
1171         r8168ep_ocp_write(tp, 0x01, 0x30,
1172                           r8168ep_ocp_read(tp, 0x01, 0x30) | 0x01);
1173         rtl_msleep_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10, 10);
1174 }
1175
1176 static void rtl8168_driver_start(struct rtl8169_private *tp)
1177 {
1178         switch (tp->mac_version) {
1179         case RTL_GIGA_MAC_VER_27:
1180         case RTL_GIGA_MAC_VER_28:
1181         case RTL_GIGA_MAC_VER_31:
1182                 rtl8168dp_driver_start(tp);
1183                 break;
1184         case RTL_GIGA_MAC_VER_49:
1185         case RTL_GIGA_MAC_VER_50:
1186         case RTL_GIGA_MAC_VER_51:
1187                 rtl8168ep_driver_start(tp);
1188                 break;
1189         default:
1190                 BUG();
1191                 break;
1192         }
1193 }
1194
1195 static void rtl8168dp_driver_stop(struct rtl8169_private *tp)
1196 {
1197         r8168dp_oob_notify(tp, OOB_CMD_DRIVER_STOP);
1198         rtl_msleep_loop_wait_low(tp, &rtl_dp_ocp_read_cond, 10, 10);
1199 }
1200
1201 static void rtl8168ep_driver_stop(struct rtl8169_private *tp)
1202 {
1203         rtl8168ep_stop_cmac(tp);
1204         r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP);
1205         r8168ep_ocp_write(tp, 0x01, 0x30,
1206                           r8168ep_ocp_read(tp, 0x01, 0x30) | 0x01);
1207         rtl_msleep_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10, 10);
1208 }
1209
1210 static void rtl8168_driver_stop(struct rtl8169_private *tp)
1211 {
1212         switch (tp->mac_version) {
1213         case RTL_GIGA_MAC_VER_27:
1214         case RTL_GIGA_MAC_VER_28:
1215         case RTL_GIGA_MAC_VER_31:
1216                 rtl8168dp_driver_stop(tp);
1217                 break;
1218         case RTL_GIGA_MAC_VER_49:
1219         case RTL_GIGA_MAC_VER_50:
1220         case RTL_GIGA_MAC_VER_51:
1221                 rtl8168ep_driver_stop(tp);
1222                 break;
1223         default:
1224                 BUG();
1225                 break;
1226         }
1227 }
1228
1229 static bool r8168dp_check_dash(struct rtl8169_private *tp)
1230 {
1231         u16 reg = rtl8168_get_ocp_reg(tp);
1232
1233         return !!(r8168dp_ocp_read(tp, 0x0f, reg) & 0x00008000);
1234 }
1235
1236 static bool r8168ep_check_dash(struct rtl8169_private *tp)
1237 {
1238         return !!(r8168ep_ocp_read(tp, 0x0f, 0x128) & 0x00000001);
1239 }
1240
1241 static bool r8168_check_dash(struct rtl8169_private *tp)
1242 {
1243         switch (tp->mac_version) {
1244         case RTL_GIGA_MAC_VER_27:
1245         case RTL_GIGA_MAC_VER_28:
1246         case RTL_GIGA_MAC_VER_31:
1247                 return r8168dp_check_dash(tp);
1248         case RTL_GIGA_MAC_VER_49:
1249         case RTL_GIGA_MAC_VER_50:
1250         case RTL_GIGA_MAC_VER_51:
1251                 return r8168ep_check_dash(tp);
1252         default:
1253                 return false;
1254         }
1255 }
1256
1257 struct exgmac_reg {
1258         u16 addr;
1259         u16 mask;
1260         u32 val;
1261 };
1262
1263 static void rtl_write_exgmac_batch(struct rtl8169_private *tp,
1264                                    const struct exgmac_reg *r, int len)
1265 {
1266         while (len-- > 0) {
1267                 rtl_eri_write(tp, r->addr, r->mask, r->val, ERIAR_EXGMAC);
1268                 r++;
1269         }
1270 }
1271
1272 DECLARE_RTL_COND(rtl_efusear_cond)
1273 {
1274         return RTL_R32(tp, EFUSEAR) & EFUSEAR_FLAG;
1275 }
1276
1277 static u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)
1278 {
1279         RTL_W32(tp, EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1280
1281         return rtl_udelay_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?
1282                 RTL_R32(tp, EFUSEAR) & EFUSEAR_DATA_MASK : ~0;
1283 }
1284
1285 static u16 rtl_get_events(struct rtl8169_private *tp)
1286 {
1287         return RTL_R16(tp, IntrStatus);
1288 }
1289
1290 static void rtl_ack_events(struct rtl8169_private *tp, u16 bits)
1291 {
1292         RTL_W16(tp, IntrStatus, bits);
1293         mmiowb();
1294 }
1295
1296 static void rtl_irq_disable(struct rtl8169_private *tp)
1297 {
1298         RTL_W16(tp, IntrMask, 0);
1299         mmiowb();
1300 }
1301
1302 #define RTL_EVENT_NAPI_RX       (RxOK | RxErr)
1303 #define RTL_EVENT_NAPI_TX       (TxOK | TxErr)
1304 #define RTL_EVENT_NAPI          (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX)
1305
1306 static void rtl_irq_enable(struct rtl8169_private *tp)
1307 {
1308         RTL_W16(tp, IntrMask, tp->irq_mask);
1309 }
1310
1311 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1312 {
1313         rtl_irq_disable(tp);
1314         rtl_ack_events(tp, 0xffff);
1315         /* PCI commit */
1316         RTL_R8(tp, ChipCmd);
1317 }
1318
1319 static void rtl_link_chg_patch(struct rtl8169_private *tp)
1320 {
1321         struct net_device *dev = tp->dev;
1322         struct phy_device *phydev = dev->phydev;
1323
1324         if (!netif_running(dev))
1325                 return;
1326
1327         if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
1328             tp->mac_version == RTL_GIGA_MAC_VER_38) {
1329                 if (phydev->speed == SPEED_1000) {
1330                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1331                                       ERIAR_EXGMAC);
1332                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1333                                       ERIAR_EXGMAC);
1334                 } else if (phydev->speed == SPEED_100) {
1335                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1336                                       ERIAR_EXGMAC);
1337                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1338                                       ERIAR_EXGMAC);
1339                 } else {
1340                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1341                                       ERIAR_EXGMAC);
1342                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1343                                       ERIAR_EXGMAC);
1344                 }
1345                 /* Reset packet filter */
1346                 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01,
1347                              ERIAR_EXGMAC);
1348                 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00,
1349                              ERIAR_EXGMAC);
1350         } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1351                    tp->mac_version == RTL_GIGA_MAC_VER_36) {
1352                 if (phydev->speed == SPEED_1000) {
1353                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1354                                       ERIAR_EXGMAC);
1355                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1356                                       ERIAR_EXGMAC);
1357                 } else {
1358                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1359                                       ERIAR_EXGMAC);
1360                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1361                                       ERIAR_EXGMAC);
1362                 }
1363         } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
1364                 if (phydev->speed == SPEED_10) {
1365                         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02,
1366                                       ERIAR_EXGMAC);
1367                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060,
1368                                       ERIAR_EXGMAC);
1369                 } else {
1370                         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000,
1371                                       ERIAR_EXGMAC);
1372                 }
1373         }
1374 }
1375
1376 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1377
1378 static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
1379 {
1380         u8 options;
1381         u32 wolopts = 0;
1382
1383         options = RTL_R8(tp, Config1);
1384         if (!(options & PMEnable))
1385                 return 0;
1386
1387         options = RTL_R8(tp, Config3);
1388         if (options & LinkUp)
1389                 wolopts |= WAKE_PHY;
1390         switch (tp->mac_version) {
1391         case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
1392         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
1393                 if (rtl_eri_read(tp, 0xdc, ERIAR_EXGMAC) & MagicPacket_v2)
1394                         wolopts |= WAKE_MAGIC;
1395                 break;
1396         default:
1397                 if (options & MagicPacket)
1398                         wolopts |= WAKE_MAGIC;
1399                 break;
1400         }
1401
1402         options = RTL_R8(tp, Config5);
1403         if (options & UWF)
1404                 wolopts |= WAKE_UCAST;
1405         if (options & BWF)
1406                 wolopts |= WAKE_BCAST;
1407         if (options & MWF)
1408                 wolopts |= WAKE_MCAST;
1409
1410         return wolopts;
1411 }
1412
1413 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1414 {
1415         struct rtl8169_private *tp = netdev_priv(dev);
1416
1417         rtl_lock_work(tp);
1418         wol->supported = WAKE_ANY;
1419         wol->wolopts = tp->saved_wolopts;
1420         rtl_unlock_work(tp);
1421 }
1422
1423 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1424 {
1425         unsigned int i, tmp;
1426         static const struct {
1427                 u32 opt;
1428                 u16 reg;
1429                 u8  mask;
1430         } cfg[] = {
1431                 { WAKE_PHY,   Config3, LinkUp },
1432                 { WAKE_UCAST, Config5, UWF },
1433                 { WAKE_BCAST, Config5, BWF },
1434                 { WAKE_MCAST, Config5, MWF },
1435                 { WAKE_ANY,   Config5, LanWake },
1436                 { WAKE_MAGIC, Config3, MagicPacket }
1437         };
1438         u8 options;
1439
1440         RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
1441
1442         switch (tp->mac_version) {
1443         case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
1444         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
1445                 tmp = ARRAY_SIZE(cfg) - 1;
1446                 if (wolopts & WAKE_MAGIC)
1447                         rtl_w0w1_eri(tp,
1448                                      0x0dc,
1449                                      ERIAR_MASK_0100,
1450                                      MagicPacket_v2,
1451                                      0x0000,
1452                                      ERIAR_EXGMAC);
1453                 else
1454                         rtl_w0w1_eri(tp,
1455                                      0x0dc,
1456                                      ERIAR_MASK_0100,
1457                                      0x0000,
1458                                      MagicPacket_v2,
1459                                      ERIAR_EXGMAC);
1460                 break;
1461         default:
1462                 tmp = ARRAY_SIZE(cfg);
1463                 break;
1464         }
1465
1466         for (i = 0; i < tmp; i++) {
1467                 options = RTL_R8(tp, cfg[i].reg) & ~cfg[i].mask;
1468                 if (wolopts & cfg[i].opt)
1469                         options |= cfg[i].mask;
1470                 RTL_W8(tp, cfg[i].reg, options);
1471         }
1472
1473         switch (tp->mac_version) {
1474         case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_17:
1475                 options = RTL_R8(tp, Config1) & ~PMEnable;
1476                 if (wolopts)
1477                         options |= PMEnable;
1478                 RTL_W8(tp, Config1, options);
1479                 break;
1480         default:
1481                 options = RTL_R8(tp, Config2) & ~PME_SIGNAL;
1482                 if (wolopts)
1483                         options |= PME_SIGNAL;
1484                 RTL_W8(tp, Config2, options);
1485                 break;
1486         }
1487
1488         RTL_W8(tp, Cfg9346, Cfg9346_Lock);
1489 }
1490
1491 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1492 {
1493         struct rtl8169_private *tp = netdev_priv(dev);
1494         struct device *d = tp_to_dev(tp);
1495
1496         if (wol->wolopts & ~WAKE_ANY)
1497                 return -EINVAL;
1498
1499         pm_runtime_get_noresume(d);
1500
1501         rtl_lock_work(tp);
1502
1503         tp->saved_wolopts = wol->wolopts;
1504
1505         if (pm_runtime_active(d))
1506                 __rtl8169_set_wol(tp, tp->saved_wolopts);
1507
1508         rtl_unlock_work(tp);
1509
1510         device_set_wakeup_enable(d, tp->saved_wolopts);
1511
1512         pm_runtime_put_noidle(d);
1513
1514         return 0;
1515 }
1516
1517 static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp)
1518 {
1519         return rtl_chip_infos[tp->mac_version].fw_name;
1520 }
1521
1522 static void rtl8169_get_drvinfo(struct net_device *dev,
1523                                 struct ethtool_drvinfo *info)
1524 {
1525         struct rtl8169_private *tp = netdev_priv(dev);
1526         struct rtl_fw *rtl_fw = tp->rtl_fw;
1527
1528         strlcpy(info->driver, MODULENAME, sizeof(info->driver));
1529         strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1530         BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
1531         if (!IS_ERR_OR_NULL(rtl_fw))
1532                 strlcpy(info->fw_version, rtl_fw->version,
1533                         sizeof(info->fw_version));
1534 }
1535
1536 static int rtl8169_get_regs_len(struct net_device *dev)
1537 {
1538         return R8169_REGS_SIZE;
1539 }
1540
1541 static netdev_features_t rtl8169_fix_features(struct net_device *dev,
1542         netdev_features_t features)
1543 {
1544         struct rtl8169_private *tp = netdev_priv(dev);
1545
1546         if (dev->mtu > TD_MSS_MAX)
1547                 features &= ~NETIF_F_ALL_TSO;
1548
1549         if (dev->mtu > JUMBO_1K &&
1550             tp->mac_version > RTL_GIGA_MAC_VER_06)
1551                 features &= ~NETIF_F_IP_CSUM;
1552
1553         return features;
1554 }
1555
1556 static int rtl8169_set_features(struct net_device *dev,
1557                                 netdev_features_t features)
1558 {
1559         struct rtl8169_private *tp = netdev_priv(dev);
1560         u32 rx_config;
1561
1562         rtl_lock_work(tp);
1563
1564         rx_config = RTL_R32(tp, RxConfig);
1565         if (features & NETIF_F_RXALL)
1566                 rx_config |= (AcceptErr | AcceptRunt);
1567         else
1568                 rx_config &= ~(AcceptErr | AcceptRunt);
1569
1570         RTL_W32(tp, RxConfig, rx_config);
1571
1572         if (features & NETIF_F_RXCSUM)
1573                 tp->cp_cmd |= RxChkSum;
1574         else
1575                 tp->cp_cmd &= ~RxChkSum;
1576
1577         if (features & NETIF_F_HW_VLAN_CTAG_RX)
1578                 tp->cp_cmd |= RxVlan;
1579         else
1580                 tp->cp_cmd &= ~RxVlan;
1581
1582         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1583         RTL_R16(tp, CPlusCmd);
1584
1585         rtl_unlock_work(tp);
1586
1587         return 0;
1588 }
1589
1590 static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb)
1591 {
1592         return (skb_vlan_tag_present(skb)) ?
1593                 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00;
1594 }
1595
1596 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1597 {
1598         u32 opts2 = le32_to_cpu(desc->opts2);
1599
1600         if (opts2 & RxVlanTag)
1601                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff));
1602 }
1603
1604 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1605                              void *p)
1606 {
1607         struct rtl8169_private *tp = netdev_priv(dev);
1608         u32 __iomem *data = tp->mmio_addr;
1609         u32 *dw = p;
1610         int i;
1611
1612         rtl_lock_work(tp);
1613         for (i = 0; i < R8169_REGS_SIZE; i += 4)
1614                 memcpy_fromio(dw++, data++, 4);
1615         rtl_unlock_work(tp);
1616 }
1617
1618 static u32 rtl8169_get_msglevel(struct net_device *dev)
1619 {
1620         struct rtl8169_private *tp = netdev_priv(dev);
1621
1622         return tp->msg_enable;
1623 }
1624
1625 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1626 {
1627         struct rtl8169_private *tp = netdev_priv(dev);
1628
1629         tp->msg_enable = value;
1630 }
1631
1632 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1633         "tx_packets",
1634         "rx_packets",
1635         "tx_errors",
1636         "rx_errors",
1637         "rx_missed",
1638         "align_errors",
1639         "tx_single_collisions",
1640         "tx_multi_collisions",
1641         "unicast",
1642         "broadcast",
1643         "multicast",
1644         "tx_aborted",
1645         "tx_underrun",
1646 };
1647
1648 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1649 {
1650         switch (sset) {
1651         case ETH_SS_STATS:
1652                 return ARRAY_SIZE(rtl8169_gstrings);
1653         default:
1654                 return -EOPNOTSUPP;
1655         }
1656 }
1657
1658 DECLARE_RTL_COND(rtl_counters_cond)
1659 {
1660         return RTL_R32(tp, CounterAddrLow) & (CounterReset | CounterDump);
1661 }
1662
1663 static bool rtl8169_do_counters(struct rtl8169_private *tp, u32 counter_cmd)
1664 {
1665         dma_addr_t paddr = tp->counters_phys_addr;
1666         u32 cmd;
1667
1668         RTL_W32(tp, CounterAddrHigh, (u64)paddr >> 32);
1669         RTL_R32(tp, CounterAddrHigh);
1670         cmd = (u64)paddr & DMA_BIT_MASK(32);
1671         RTL_W32(tp, CounterAddrLow, cmd);
1672         RTL_W32(tp, CounterAddrLow, cmd | counter_cmd);
1673
1674         return rtl_udelay_loop_wait_low(tp, &rtl_counters_cond, 10, 1000);
1675 }
1676
1677 static bool rtl8169_reset_counters(struct rtl8169_private *tp)
1678 {
1679         /*
1680          * Versions prior to RTL_GIGA_MAC_VER_19 don't support resetting the
1681          * tally counters.
1682          */
1683         if (tp->mac_version < RTL_GIGA_MAC_VER_19)
1684                 return true;
1685
1686         return rtl8169_do_counters(tp, CounterReset);
1687 }
1688
1689 static bool rtl8169_update_counters(struct rtl8169_private *tp)
1690 {
1691         /*
1692          * Some chips are unable to dump tally counters when the receiver
1693          * is disabled.
1694          */
1695         if ((RTL_R8(tp, ChipCmd) & CmdRxEnb) == 0)
1696                 return true;
1697
1698         return rtl8169_do_counters(tp, CounterDump);
1699 }
1700
1701 static bool rtl8169_init_counter_offsets(struct rtl8169_private *tp)
1702 {
1703         struct rtl8169_counters *counters = tp->counters;
1704         bool ret = false;
1705
1706         /*
1707          * rtl8169_init_counter_offsets is called from rtl_open.  On chip
1708          * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only
1709          * reset by a power cycle, while the counter values collected by the
1710          * driver are reset at every driver unload/load cycle.
1711          *
1712          * To make sure the HW values returned by @get_stats64 match the SW
1713          * values, we collect the initial values at first open(*) and use them
1714          * as offsets to normalize the values returned by @get_stats64.
1715          *
1716          * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one
1717          * for the reason stated in rtl8169_update_counters; CmdRxEnb is only
1718          * set at open time by rtl_hw_start.
1719          */
1720
1721         if (tp->tc_offset.inited)
1722                 return true;
1723
1724         /* If both, reset and update fail, propagate to caller. */
1725         if (rtl8169_reset_counters(tp))
1726                 ret = true;
1727
1728         if (rtl8169_update_counters(tp))
1729                 ret = true;
1730
1731         tp->tc_offset.tx_errors = counters->tx_errors;
1732         tp->tc_offset.tx_multi_collision = counters->tx_multi_collision;
1733         tp->tc_offset.tx_aborted = counters->tx_aborted;
1734         tp->tc_offset.inited = true;
1735
1736         return ret;
1737 }
1738
1739 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1740                                       struct ethtool_stats *stats, u64 *data)
1741 {
1742         struct rtl8169_private *tp = netdev_priv(dev);
1743         struct device *d = tp_to_dev(tp);
1744         struct rtl8169_counters *counters = tp->counters;
1745
1746         ASSERT_RTNL();
1747
1748         pm_runtime_get_noresume(d);
1749
1750         if (pm_runtime_active(d))
1751                 rtl8169_update_counters(tp);
1752
1753         pm_runtime_put_noidle(d);
1754
1755         data[0] = le64_to_cpu(counters->tx_packets);
1756         data[1] = le64_to_cpu(counters->rx_packets);
1757         data[2] = le64_to_cpu(counters->tx_errors);
1758         data[3] = le32_to_cpu(counters->rx_errors);
1759         data[4] = le16_to_cpu(counters->rx_missed);
1760         data[5] = le16_to_cpu(counters->align_errors);
1761         data[6] = le32_to_cpu(counters->tx_one_collision);
1762         data[7] = le32_to_cpu(counters->tx_multi_collision);
1763         data[8] = le64_to_cpu(counters->rx_unicast);
1764         data[9] = le64_to_cpu(counters->rx_broadcast);
1765         data[10] = le32_to_cpu(counters->rx_multicast);
1766         data[11] = le16_to_cpu(counters->tx_aborted);
1767         data[12] = le16_to_cpu(counters->tx_underun);
1768 }
1769
1770 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1771 {
1772         switch(stringset) {
1773         case ETH_SS_STATS:
1774                 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1775                 break;
1776         }
1777 }
1778
1779 /*
1780  * Interrupt coalescing
1781  *
1782  * > 1 - the availability of the IntrMitigate (0xe2) register through the
1783  * >     8169, 8168 and 810x line of chipsets
1784  *
1785  * 8169, 8168, and 8136(810x) serial chipsets support it.
1786  *
1787  * > 2 - the Tx timer unit at gigabit speed
1788  *
1789  * The unit of the timer depends on both the speed and the setting of CPlusCmd
1790  * (0xe0) bit 1 and bit 0.
1791  *
1792  * For 8169
1793  * bit[1:0] \ speed        1000M           100M            10M
1794  * 0 0                     320ns           2.56us          40.96us
1795  * 0 1                     2.56us          20.48us         327.7us
1796  * 1 0                     5.12us          40.96us         655.4us
1797  * 1 1                     10.24us         81.92us         1.31ms
1798  *
1799  * For the other
1800  * bit[1:0] \ speed        1000M           100M            10M
1801  * 0 0                     5us             2.56us          40.96us
1802  * 0 1                     40us            20.48us         327.7us
1803  * 1 0                     80us            40.96us         655.4us
1804  * 1 1                     160us           81.92us         1.31ms
1805  */
1806
1807 /* rx/tx scale factors for one particular CPlusCmd[0:1] value */
1808 struct rtl_coalesce_scale {
1809         /* Rx / Tx */
1810         u32 nsecs[2];
1811 };
1812
1813 /* rx/tx scale factors for all CPlusCmd[0:1] cases */
1814 struct rtl_coalesce_info {
1815         u32 speed;
1816         struct rtl_coalesce_scale scalev[4];    /* each CPlusCmd[0:1] case */
1817 };
1818
1819 /* produce (r,t) pairs with each being in series of *1, *8, *8*2, *8*2*2 */
1820 #define rxtx_x1822(r, t) {              \
1821         {{(r),          (t)}},          \
1822         {{(r)*8,        (t)*8}},        \
1823         {{(r)*8*2,      (t)*8*2}},      \
1824         {{(r)*8*2*2,    (t)*8*2*2}},    \
1825 }
1826 static const struct rtl_coalesce_info rtl_coalesce_info_8169[] = {
1827         /* speed        delays:     rx00   tx00 */
1828         { SPEED_10,     rxtx_x1822(40960, 40960)        },
1829         { SPEED_100,    rxtx_x1822( 2560,  2560)        },
1830         { SPEED_1000,   rxtx_x1822(  320,   320)        },
1831         { 0 },
1832 };
1833
1834 static const struct rtl_coalesce_info rtl_coalesce_info_8168_8136[] = {
1835         /* speed        delays:     rx00   tx00 */
1836         { SPEED_10,     rxtx_x1822(40960, 40960)        },
1837         { SPEED_100,    rxtx_x1822( 2560,  2560)        },
1838         { SPEED_1000,   rxtx_x1822( 5000,  5000)        },
1839         { 0 },
1840 };
1841 #undef rxtx_x1822
1842
1843 /* get rx/tx scale vector corresponding to current speed */
1844 static const struct rtl_coalesce_info *rtl_coalesce_info(struct net_device *dev)
1845 {
1846         struct rtl8169_private *tp = netdev_priv(dev);
1847         struct ethtool_link_ksettings ecmd;
1848         const struct rtl_coalesce_info *ci;
1849         int rc;
1850
1851         rc = phy_ethtool_get_link_ksettings(dev, &ecmd);
1852         if (rc < 0)
1853                 return ERR_PTR(rc);
1854
1855         for (ci = tp->coalesce_info; ci->speed != 0; ci++) {
1856                 if (ecmd.base.speed == ci->speed) {
1857                         return ci;
1858                 }
1859         }
1860
1861         return ERR_PTR(-ELNRNG);
1862 }
1863
1864 static int rtl_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1865 {
1866         struct rtl8169_private *tp = netdev_priv(dev);
1867         const struct rtl_coalesce_info *ci;
1868         const struct rtl_coalesce_scale *scale;
1869         struct {
1870                 u32 *max_frames;
1871                 u32 *usecs;
1872         } coal_settings [] = {
1873                 { &ec->rx_max_coalesced_frames, &ec->rx_coalesce_usecs },
1874                 { &ec->tx_max_coalesced_frames, &ec->tx_coalesce_usecs }
1875         }, *p = coal_settings;
1876         int i;
1877         u16 w;
1878
1879         memset(ec, 0, sizeof(*ec));
1880
1881         /* get rx/tx scale corresponding to current speed and CPlusCmd[0:1] */
1882         ci = rtl_coalesce_info(dev);
1883         if (IS_ERR(ci))
1884                 return PTR_ERR(ci);
1885
1886         scale = &ci->scalev[tp->cp_cmd & INTT_MASK];
1887
1888         /* read IntrMitigate and adjust according to scale */
1889         for (w = RTL_R16(tp, IntrMitigate); w; w >>= RTL_COALESCE_SHIFT, p++) {
1890                 *p->max_frames = (w & RTL_COALESCE_MASK) << 2;
1891                 w >>= RTL_COALESCE_SHIFT;
1892                 *p->usecs = w & RTL_COALESCE_MASK;
1893         }
1894
1895         for (i = 0; i < 2; i++) {
1896                 p = coal_settings + i;
1897                 *p->usecs = (*p->usecs * scale->nsecs[i]) / 1000;
1898
1899                 /*
1900                  * ethtool_coalesce says it is illegal to set both usecs and
1901                  * max_frames to 0.
1902                  */
1903                 if (!*p->usecs && !*p->max_frames)
1904                         *p->max_frames = 1;
1905         }
1906
1907         return 0;
1908 }
1909
1910 /* choose appropriate scale factor and CPlusCmd[0:1] for (speed, nsec) */
1911 static const struct rtl_coalesce_scale *rtl_coalesce_choose_scale(
1912                         struct net_device *dev, u32 nsec, u16 *cp01)
1913 {
1914         const struct rtl_coalesce_info *ci;
1915         u16 i;
1916
1917         ci = rtl_coalesce_info(dev);
1918         if (IS_ERR(ci))
1919                 return ERR_CAST(ci);
1920
1921         for (i = 0; i < 4; i++) {
1922                 u32 rxtx_maxscale = max(ci->scalev[i].nsecs[0],
1923                                         ci->scalev[i].nsecs[1]);
1924                 if (nsec <= rxtx_maxscale * RTL_COALESCE_T_MAX) {
1925                         *cp01 = i;
1926                         return &ci->scalev[i];
1927                 }
1928         }
1929
1930         return ERR_PTR(-EINVAL);
1931 }
1932
1933 static int rtl_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1934 {
1935         struct rtl8169_private *tp = netdev_priv(dev);
1936         const struct rtl_coalesce_scale *scale;
1937         struct {
1938                 u32 frames;
1939                 u32 usecs;
1940         } coal_settings [] = {
1941                 { ec->rx_max_coalesced_frames, ec->rx_coalesce_usecs },
1942                 { ec->tx_max_coalesced_frames, ec->tx_coalesce_usecs }
1943         }, *p = coal_settings;
1944         u16 w = 0, cp01;
1945         int i;
1946
1947         scale = rtl_coalesce_choose_scale(dev,
1948                         max(p[0].usecs, p[1].usecs) * 1000, &cp01);
1949         if (IS_ERR(scale))
1950                 return PTR_ERR(scale);
1951
1952         for (i = 0; i < 2; i++, p++) {
1953                 u32 units;
1954
1955                 /*
1956                  * accept max_frames=1 we returned in rtl_get_coalesce.
1957                  * accept it not only when usecs=0 because of e.g. the following scenario:
1958                  *
1959                  * - both rx_usecs=0 & rx_frames=0 in hardware (no delay on RX)
1960                  * - rtl_get_coalesce returns rx_usecs=0, rx_frames=1
1961                  * - then user does `ethtool -C eth0 rx-usecs 100`
1962                  *
1963                  * since ethtool sends to kernel whole ethtool_coalesce
1964                  * settings, if we do not handle rx_usecs=!0, rx_frames=1
1965                  * we'll reject it below in `frames % 4 != 0`.
1966                  */
1967                 if (p->frames == 1) {
1968                         p->frames = 0;
1969                 }
1970
1971                 units = p->usecs * 1000 / scale->nsecs[i];
1972                 if (p->frames > RTL_COALESCE_FRAME_MAX || p->frames % 4)
1973                         return -EINVAL;
1974
1975                 w <<= RTL_COALESCE_SHIFT;
1976                 w |= units;
1977                 w <<= RTL_COALESCE_SHIFT;
1978                 w |= p->frames >> 2;
1979         }
1980
1981         rtl_lock_work(tp);
1982
1983         RTL_W16(tp, IntrMitigate, swab16(w));
1984
1985         tp->cp_cmd = (tp->cp_cmd & ~INTT_MASK) | cp01;
1986         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1987         RTL_R16(tp, CPlusCmd);
1988
1989         rtl_unlock_work(tp);
1990
1991         return 0;
1992 }
1993
1994 static const struct ethtool_ops rtl8169_ethtool_ops = {
1995         .get_drvinfo            = rtl8169_get_drvinfo,
1996         .get_regs_len           = rtl8169_get_regs_len,
1997         .get_link               = ethtool_op_get_link,
1998         .get_coalesce           = rtl_get_coalesce,
1999         .set_coalesce           = rtl_set_coalesce,
2000         .get_msglevel           = rtl8169_get_msglevel,
2001         .set_msglevel           = rtl8169_set_msglevel,
2002         .get_regs               = rtl8169_get_regs,
2003         .get_wol                = rtl8169_get_wol,
2004         .set_wol                = rtl8169_set_wol,
2005         .get_strings            = rtl8169_get_strings,
2006         .get_sset_count         = rtl8169_get_sset_count,
2007         .get_ethtool_stats      = rtl8169_get_ethtool_stats,
2008         .get_ts_info            = ethtool_op_get_ts_info,
2009         .nway_reset             = phy_ethtool_nway_reset,
2010         .get_link_ksettings     = phy_ethtool_get_link_ksettings,
2011         .set_link_ksettings     = phy_ethtool_set_link_ksettings,
2012 };
2013
2014 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
2015                                     u8 default_version)
2016 {
2017         /*
2018          * The driver currently handles the 8168Bf and the 8168Be identically
2019          * but they can be identified more specifically through the test below
2020          * if needed:
2021          *
2022          * (RTL_R32(tp, TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
2023          *
2024          * Same thing for the 8101Eb and the 8101Ec:
2025          *
2026          * (RTL_R32(tp, TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
2027          */
2028         static const struct rtl_mac_info {
2029                 u16 mask;
2030                 u16 val;
2031                 u16 mac_version;
2032         } mac_info[] = {
2033                 /* 8168EP family. */
2034                 { 0x7cf, 0x502, RTL_GIGA_MAC_VER_51 },
2035                 { 0x7cf, 0x501, RTL_GIGA_MAC_VER_50 },
2036                 { 0x7cf, 0x500, RTL_GIGA_MAC_VER_49 },
2037
2038                 /* 8168H family. */
2039                 { 0x7cf, 0x541, RTL_GIGA_MAC_VER_46 },
2040                 { 0x7cf, 0x540, RTL_GIGA_MAC_VER_45 },
2041
2042                 /* 8168G family. */
2043                 { 0x7cf, 0x5c8, RTL_GIGA_MAC_VER_44 },
2044                 { 0x7cf, 0x509, RTL_GIGA_MAC_VER_42 },
2045                 { 0x7cf, 0x4c1, RTL_GIGA_MAC_VER_41 },
2046                 { 0x7cf, 0x4c0, RTL_GIGA_MAC_VER_40 },
2047
2048                 /* 8168F family. */
2049                 { 0x7c8, 0x488, RTL_GIGA_MAC_VER_38 },
2050                 { 0x7cf, 0x481, RTL_GIGA_MAC_VER_36 },
2051                 { 0x7cf, 0x480, RTL_GIGA_MAC_VER_35 },
2052
2053                 /* 8168E family. */
2054                 { 0x7c8, 0x2c8, RTL_GIGA_MAC_VER_34 },
2055                 { 0x7cf, 0x2c1, RTL_GIGA_MAC_VER_32 },
2056                 { 0x7c8, 0x2c0, RTL_GIGA_MAC_VER_33 },
2057
2058                 /* 8168D family. */
2059                 { 0x7cf, 0x281, RTL_GIGA_MAC_VER_25 },
2060                 { 0x7c8, 0x280, RTL_GIGA_MAC_VER_26 },
2061
2062                 /* 8168DP family. */
2063                 { 0x7cf, 0x288, RTL_GIGA_MAC_VER_27 },
2064                 { 0x7cf, 0x28a, RTL_GIGA_MAC_VER_28 },
2065                 { 0x7cf, 0x28b, RTL_GIGA_MAC_VER_31 },
2066
2067                 /* 8168C family. */
2068                 { 0x7cf, 0x3c9, RTL_GIGA_MAC_VER_23 },
2069                 { 0x7cf, 0x3c8, RTL_GIGA_MAC_VER_18 },
2070                 { 0x7c8, 0x3c8, RTL_GIGA_MAC_VER_24 },
2071                 { 0x7cf, 0x3c0, RTL_GIGA_MAC_VER_19 },
2072                 { 0x7cf, 0x3c2, RTL_GIGA_MAC_VER_20 },
2073                 { 0x7cf, 0x3c3, RTL_GIGA_MAC_VER_21 },
2074                 { 0x7c8, 0x3c0, RTL_GIGA_MAC_VER_22 },
2075
2076                 /* 8168B family. */
2077                 { 0x7cf, 0x380, RTL_GIGA_MAC_VER_12 },
2078                 { 0x7c8, 0x380, RTL_GIGA_MAC_VER_17 },
2079                 { 0x7c8, 0x300, RTL_GIGA_MAC_VER_11 },
2080
2081                 /* 8101 family. */
2082                 { 0x7c8, 0x448, RTL_GIGA_MAC_VER_39 },
2083                 { 0x7c8, 0x440, RTL_GIGA_MAC_VER_37 },
2084                 { 0x7cf, 0x409, RTL_GIGA_MAC_VER_29 },
2085                 { 0x7c8, 0x408, RTL_GIGA_MAC_VER_30 },
2086                 { 0x7cf, 0x349, RTL_GIGA_MAC_VER_08 },
2087                 { 0x7cf, 0x249, RTL_GIGA_MAC_VER_08 },
2088                 { 0x7cf, 0x348, RTL_GIGA_MAC_VER_07 },
2089                 { 0x7cf, 0x248, RTL_GIGA_MAC_VER_07 },
2090                 { 0x7cf, 0x340, RTL_GIGA_MAC_VER_13 },
2091                 { 0x7cf, 0x343, RTL_GIGA_MAC_VER_10 },
2092                 { 0x7cf, 0x342, RTL_GIGA_MAC_VER_16 },
2093                 { 0x7c8, 0x348, RTL_GIGA_MAC_VER_09 },
2094                 { 0x7c8, 0x248, RTL_GIGA_MAC_VER_09 },
2095                 { 0x7c8, 0x340, RTL_GIGA_MAC_VER_16 },
2096                 /* FIXME: where did these entries come from ? -- FR */
2097                 { 0xfc8, 0x388, RTL_GIGA_MAC_VER_15 },
2098                 { 0xfc8, 0x308, RTL_GIGA_MAC_VER_14 },
2099
2100                 /* 8110 family. */
2101                 { 0xfc8, 0x980, RTL_GIGA_MAC_VER_06 },
2102                 { 0xfc8, 0x180, RTL_GIGA_MAC_VER_05 },
2103                 { 0xfc8, 0x100, RTL_GIGA_MAC_VER_04 },
2104                 { 0xfc8, 0x040, RTL_GIGA_MAC_VER_03 },
2105                 { 0xfc8, 0x008, RTL_GIGA_MAC_VER_02 },
2106                 { 0xfc8, 0x000, RTL_GIGA_MAC_VER_01 },
2107
2108                 /* Catch-all */
2109                 { 0x000, 0x000, RTL_GIGA_MAC_NONE   }
2110         };
2111         const struct rtl_mac_info *p = mac_info;
2112         u16 reg = RTL_R32(tp, TxConfig) >> 20;
2113
2114         while ((reg & p->mask) != p->val)
2115                 p++;
2116         tp->mac_version = p->mac_version;
2117
2118         if (tp->mac_version == RTL_GIGA_MAC_NONE) {
2119                 dev_notice(tp_to_dev(tp),
2120                            "unknown MAC, using family default\n");
2121                 tp->mac_version = default_version;
2122         } else if (tp->mac_version == RTL_GIGA_MAC_VER_42) {
2123                 tp->mac_version = tp->supports_gmii ?
2124                                   RTL_GIGA_MAC_VER_42 :
2125                                   RTL_GIGA_MAC_VER_43;
2126         } else if (tp->mac_version == RTL_GIGA_MAC_VER_45) {
2127                 tp->mac_version = tp->supports_gmii ?
2128                                   RTL_GIGA_MAC_VER_45 :
2129                                   RTL_GIGA_MAC_VER_47;
2130         } else if (tp->mac_version == RTL_GIGA_MAC_VER_46) {
2131                 tp->mac_version = tp->supports_gmii ?
2132                                   RTL_GIGA_MAC_VER_46 :
2133                                   RTL_GIGA_MAC_VER_48;
2134         }
2135 }
2136
2137 struct phy_reg {
2138         u16 reg;
2139         u16 val;
2140 };
2141
2142 static void rtl_writephy_batch(struct rtl8169_private *tp,
2143                                const struct phy_reg *regs, int len)
2144 {
2145         while (len-- > 0) {
2146                 rtl_writephy(tp, regs->reg, regs->val);
2147                 regs++;
2148         }
2149 }
2150
2151 #define PHY_READ                0x00000000
2152 #define PHY_DATA_OR             0x10000000
2153 #define PHY_DATA_AND            0x20000000
2154 #define PHY_BJMPN               0x30000000
2155 #define PHY_MDIO_CHG            0x40000000
2156 #define PHY_CLEAR_READCOUNT     0x70000000
2157 #define PHY_WRITE               0x80000000
2158 #define PHY_READCOUNT_EQ_SKIP   0x90000000
2159 #define PHY_COMP_EQ_SKIPN       0xa0000000
2160 #define PHY_COMP_NEQ_SKIPN      0xb0000000
2161 #define PHY_WRITE_PREVIOUS      0xc0000000
2162 #define PHY_SKIPN               0xd0000000
2163 #define PHY_DELAY_MS            0xe0000000
2164
2165 struct fw_info {
2166         u32     magic;
2167         char    version[RTL_VER_SIZE];
2168         __le32  fw_start;
2169         __le32  fw_len;
2170         u8      chksum;
2171 } __packed;
2172
2173 #define FW_OPCODE_SIZE  sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
2174
2175 static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2176 {
2177         const struct firmware *fw = rtl_fw->fw;
2178         struct fw_info *fw_info = (struct fw_info *)fw->data;
2179         struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2180         char *version = rtl_fw->version;
2181         bool rc = false;
2182
2183         if (fw->size < FW_OPCODE_SIZE)
2184                 goto out;
2185
2186         if (!fw_info->magic) {
2187                 size_t i, size, start;
2188                 u8 checksum = 0;
2189
2190                 if (fw->size < sizeof(*fw_info))
2191                         goto out;
2192
2193                 for (i = 0; i < fw->size; i++)
2194                         checksum += fw->data[i];
2195                 if (checksum != 0)
2196                         goto out;
2197
2198                 start = le32_to_cpu(fw_info->fw_start);
2199                 if (start > fw->size)
2200                         goto out;
2201
2202                 size = le32_to_cpu(fw_info->fw_len);
2203                 if (size > (fw->size - start) / FW_OPCODE_SIZE)
2204                         goto out;
2205
2206                 memcpy(version, fw_info->version, RTL_VER_SIZE);
2207
2208                 pa->code = (__le32 *)(fw->data + start);
2209                 pa->size = size;
2210         } else {
2211                 if (fw->size % FW_OPCODE_SIZE)
2212                         goto out;
2213
2214                 strlcpy(version, rtl_lookup_firmware_name(tp), RTL_VER_SIZE);
2215
2216                 pa->code = (__le32 *)fw->data;
2217                 pa->size = fw->size / FW_OPCODE_SIZE;
2218         }
2219         version[RTL_VER_SIZE - 1] = 0;
2220
2221         rc = true;
2222 out:
2223         return rc;
2224 }
2225
2226 static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev,
2227                            struct rtl_fw_phy_action *pa)
2228 {
2229         bool rc = false;
2230         size_t index;
2231
2232         for (index = 0; index < pa->size; index++) {
2233                 u32 action = le32_to_cpu(pa->code[index]);
2234                 u32 regno = (action & 0x0fff0000) >> 16;
2235
2236                 switch(action & 0xf0000000) {
2237                 case PHY_READ:
2238                 case PHY_DATA_OR:
2239                 case PHY_DATA_AND:
2240                 case PHY_MDIO_CHG:
2241                 case PHY_CLEAR_READCOUNT:
2242                 case PHY_WRITE:
2243                 case PHY_WRITE_PREVIOUS:
2244                 case PHY_DELAY_MS:
2245                         break;
2246
2247                 case PHY_BJMPN:
2248                         if (regno > index) {
2249                                 netif_err(tp, ifup, tp->dev,
2250                                           "Out of range of firmware\n");
2251                                 goto out;
2252                         }
2253                         break;
2254                 case PHY_READCOUNT_EQ_SKIP:
2255                         if (index + 2 >= pa->size) {
2256                                 netif_err(tp, ifup, tp->dev,
2257                                           "Out of range of firmware\n");
2258                                 goto out;
2259                         }
2260                         break;
2261                 case PHY_COMP_EQ_SKIPN:
2262                 case PHY_COMP_NEQ_SKIPN:
2263                 case PHY_SKIPN:
2264                         if (index + 1 + regno >= pa->size) {
2265                                 netif_err(tp, ifup, tp->dev,
2266                                           "Out of range of firmware\n");
2267                                 goto out;
2268                         }
2269                         break;
2270
2271                 default:
2272                         netif_err(tp, ifup, tp->dev,
2273                                   "Invalid action 0x%08x\n", action);
2274                         goto out;
2275                 }
2276         }
2277         rc = true;
2278 out:
2279         return rc;
2280 }
2281
2282 static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2283 {
2284         struct net_device *dev = tp->dev;
2285         int rc = -EINVAL;
2286
2287         if (!rtl_fw_format_ok(tp, rtl_fw)) {
2288                 netif_err(tp, ifup, dev, "invalid firmware\n");
2289                 goto out;
2290         }
2291
2292         if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action))
2293                 rc = 0;
2294 out:
2295         return rc;
2296 }
2297
2298 static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2299 {
2300         struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2301         struct mdio_ops org, *ops = &tp->mdio_ops;
2302         u32 predata, count;
2303         size_t index;
2304
2305         predata = count = 0;
2306         org.write = ops->write;
2307         org.read = ops->read;
2308
2309         for (index = 0; index < pa->size; ) {
2310                 u32 action = le32_to_cpu(pa->code[index]);
2311                 u32 data = action & 0x0000ffff;
2312                 u32 regno = (action & 0x0fff0000) >> 16;
2313
2314                 if (!action)
2315                         break;
2316
2317                 switch(action & 0xf0000000) {
2318                 case PHY_READ:
2319                         predata = rtl_readphy(tp, regno);
2320                         count++;
2321                         index++;
2322                         break;
2323                 case PHY_DATA_OR:
2324                         predata |= data;
2325                         index++;
2326                         break;
2327                 case PHY_DATA_AND:
2328                         predata &= data;
2329                         index++;
2330                         break;
2331                 case PHY_BJMPN:
2332                         index -= regno;
2333                         break;
2334                 case PHY_MDIO_CHG:
2335                         if (data == 0) {
2336                                 ops->write = org.write;
2337                                 ops->read = org.read;
2338                         } else if (data == 1) {
2339                                 ops->write = mac_mcu_write;
2340                                 ops->read = mac_mcu_read;
2341                         }
2342
2343                         index++;
2344                         break;
2345                 case PHY_CLEAR_READCOUNT:
2346                         count = 0;
2347                         index++;
2348                         break;
2349                 case PHY_WRITE:
2350                         rtl_writephy(tp, regno, data);
2351                         index++;
2352                         break;
2353                 case PHY_READCOUNT_EQ_SKIP:
2354                         index += (count == data) ? 2 : 1;
2355                         break;
2356                 case PHY_COMP_EQ_SKIPN:
2357                         if (predata == data)
2358                                 index += regno;
2359                         index++;
2360                         break;
2361                 case PHY_COMP_NEQ_SKIPN:
2362                         if (predata != data)
2363                                 index += regno;
2364                         index++;
2365                         break;
2366                 case PHY_WRITE_PREVIOUS:
2367                         rtl_writephy(tp, regno, predata);
2368                         index++;
2369                         break;
2370                 case PHY_SKIPN:
2371                         index += regno + 1;
2372                         break;
2373                 case PHY_DELAY_MS:
2374                         mdelay(data);
2375                         index++;
2376                         break;
2377
2378                 default:
2379                         BUG();
2380                 }
2381         }
2382
2383         ops->write = org.write;
2384         ops->read = org.read;
2385 }
2386
2387 static void rtl_release_firmware(struct rtl8169_private *tp)
2388 {
2389         if (!IS_ERR_OR_NULL(tp->rtl_fw)) {
2390                 release_firmware(tp->rtl_fw->fw);
2391                 kfree(tp->rtl_fw);
2392         }
2393         tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
2394 }
2395
2396 static void rtl_apply_firmware(struct rtl8169_private *tp)
2397 {
2398         struct rtl_fw *rtl_fw = tp->rtl_fw;
2399
2400         /* TODO: release firmware once rtl_phy_write_fw signals failures. */
2401         if (!IS_ERR_OR_NULL(rtl_fw))
2402                 rtl_phy_write_fw(tp, rtl_fw);
2403 }
2404
2405 static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
2406 {
2407         if (rtl_readphy(tp, reg) != val)
2408                 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
2409         else
2410                 rtl_apply_firmware(tp);
2411 }
2412
2413 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
2414 {
2415         static const struct phy_reg phy_reg_init[] = {
2416                 { 0x1f, 0x0001 },
2417                 { 0x06, 0x006e },
2418                 { 0x08, 0x0708 },
2419                 { 0x15, 0x4000 },
2420                 { 0x18, 0x65c7 },
2421
2422                 { 0x1f, 0x0001 },
2423                 { 0x03, 0x00a1 },
2424                 { 0x02, 0x0008 },
2425                 { 0x01, 0x0120 },
2426                 { 0x00, 0x1000 },
2427                 { 0x04, 0x0800 },
2428                 { 0x04, 0x0000 },
2429
2430                 { 0x03, 0xff41 },
2431                 { 0x02, 0xdf60 },
2432                 { 0x01, 0x0140 },
2433                 { 0x00, 0x0077 },
2434                 { 0x04, 0x7800 },
2435                 { 0x04, 0x7000 },
2436
2437                 { 0x03, 0x802f },
2438                 { 0x02, 0x4f02 },
2439                 { 0x01, 0x0409 },
2440                 { 0x00, 0xf0f9 },
2441                 { 0x04, 0x9800 },
2442                 { 0x04, 0x9000 },
2443
2444                 { 0x03, 0xdf01 },
2445                 { 0x02, 0xdf20 },
2446                 { 0x01, 0xff95 },
2447                 { 0x00, 0xba00 },
2448                 { 0x04, 0xa800 },
2449                 { 0x04, 0xa000 },
2450
2451                 { 0x03, 0xff41 },
2452                 { 0x02, 0xdf20 },
2453                 { 0x01, 0x0140 },
2454                 { 0x00, 0x00bb },
2455                 { 0x04, 0xb800 },
2456                 { 0x04, 0xb000 },
2457
2458                 { 0x03, 0xdf41 },
2459                 { 0x02, 0xdc60 },
2460                 { 0x01, 0x6340 },
2461                 { 0x00, 0x007d },
2462                 { 0x04, 0xd800 },
2463                 { 0x04, 0xd000 },
2464
2465                 { 0x03, 0xdf01 },
2466                 { 0x02, 0xdf20 },
2467                 { 0x01, 0x100a },
2468                 { 0x00, 0xa0ff },
2469                 { 0x04, 0xf800 },
2470                 { 0x04, 0xf000 },
2471
2472                 { 0x1f, 0x0000 },
2473                 { 0x0b, 0x0000 },
2474                 { 0x00, 0x9200 }
2475         };
2476
2477         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2478 }
2479
2480 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
2481 {
2482         static const struct phy_reg phy_reg_init[] = {
2483                 { 0x1f, 0x0002 },
2484                 { 0x01, 0x90d0 },
2485                 { 0x1f, 0x0000 }
2486         };
2487
2488         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2489 }
2490
2491 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2492 {
2493         struct pci_dev *pdev = tp->pci_dev;
2494
2495         if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
2496             (pdev->subsystem_device != 0xe000))
2497                 return;
2498
2499         rtl_writephy(tp, 0x1f, 0x0001);
2500         rtl_writephy(tp, 0x10, 0xf01b);
2501         rtl_writephy(tp, 0x1f, 0x0000);
2502 }
2503
2504 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2505 {
2506         static const struct phy_reg phy_reg_init[] = {
2507                 { 0x1f, 0x0001 },
2508                 { 0x04, 0x0000 },
2509                 { 0x03, 0x00a1 },
2510                 { 0x02, 0x0008 },
2511                 { 0x01, 0x0120 },
2512                 { 0x00, 0x1000 },
2513                 { 0x04, 0x0800 },
2514                 { 0x04, 0x9000 },
2515                 { 0x03, 0x802f },
2516                 { 0x02, 0x4f02 },
2517                 { 0x01, 0x0409 },
2518                 { 0x00, 0xf099 },
2519                 { 0x04, 0x9800 },
2520                 { 0x04, 0xa000 },
2521                 { 0x03, 0xdf01 },
2522                 { 0x02, 0xdf20 },
2523                 { 0x01, 0xff95 },
2524                 { 0x00, 0xba00 },
2525                 { 0x04, 0xa800 },
2526                 { 0x04, 0xf000 },
2527                 { 0x03, 0xdf01 },
2528                 { 0x02, 0xdf20 },
2529                 { 0x01, 0x101a },
2530                 { 0x00, 0xa0ff },
2531                 { 0x04, 0xf800 },
2532                 { 0x04, 0x0000 },
2533                 { 0x1f, 0x0000 },
2534
2535                 { 0x1f, 0x0001 },
2536                 { 0x10, 0xf41b },
2537                 { 0x14, 0xfb54 },
2538                 { 0x18, 0xf5c7 },
2539                 { 0x1f, 0x0000 },
2540
2541                 { 0x1f, 0x0001 },
2542                 { 0x17, 0x0cc0 },
2543                 { 0x1f, 0x0000 }
2544         };
2545
2546         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2547
2548         rtl8169scd_hw_phy_config_quirk(tp);
2549 }
2550
2551 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
2552 {
2553         static const struct phy_reg phy_reg_init[] = {
2554                 { 0x1f, 0x0001 },
2555                 { 0x04, 0x0000 },
2556                 { 0x03, 0x00a1 },
2557                 { 0x02, 0x0008 },
2558                 { 0x01, 0x0120 },
2559                 { 0x00, 0x1000 },
2560                 { 0x04, 0x0800 },
2561                 { 0x04, 0x9000 },
2562                 { 0x03, 0x802f },
2563                 { 0x02, 0x4f02 },
2564                 { 0x01, 0x0409 },
2565                 { 0x00, 0xf099 },
2566                 { 0x04, 0x9800 },
2567                 { 0x04, 0xa000 },
2568                 { 0x03, 0xdf01 },
2569                 { 0x02, 0xdf20 },
2570                 { 0x01, 0xff95 },
2571                 { 0x00, 0xba00 },
2572                 { 0x04, 0xa800 },
2573                 { 0x04, 0xf000 },
2574                 { 0x03, 0xdf01 },
2575                 { 0x02, 0xdf20 },
2576                 { 0x01, 0x101a },
2577                 { 0x00, 0xa0ff },
2578                 { 0x04, 0xf800 },
2579                 { 0x04, 0x0000 },
2580                 { 0x1f, 0x0000 },
2581
2582                 { 0x1f, 0x0001 },
2583                 { 0x0b, 0x8480 },
2584                 { 0x1f, 0x0000 },
2585
2586                 { 0x1f, 0x0001 },
2587                 { 0x18, 0x67c7 },
2588                 { 0x04, 0x2000 },
2589                 { 0x03, 0x002f },
2590                 { 0x02, 0x4360 },
2591                 { 0x01, 0x0109 },
2592                 { 0x00, 0x3022 },
2593                 { 0x04, 0x2800 },
2594                 { 0x1f, 0x0000 },
2595
2596                 { 0x1f, 0x0001 },
2597                 { 0x17, 0x0cc0 },
2598                 { 0x1f, 0x0000 }
2599         };
2600
2601         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2602 }
2603
2604 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
2605 {
2606         static const struct phy_reg phy_reg_init[] = {
2607                 { 0x10, 0xf41b },
2608                 { 0x1f, 0x0000 }
2609         };
2610
2611         rtl_writephy(tp, 0x1f, 0x0001);
2612         rtl_patchphy(tp, 0x16, 1 << 0);
2613
2614         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2615 }
2616
2617 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
2618 {
2619         static const struct phy_reg phy_reg_init[] = {
2620                 { 0x1f, 0x0001 },
2621                 { 0x10, 0xf41b },
2622                 { 0x1f, 0x0000 }
2623         };
2624
2625         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2626 }
2627
2628 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
2629 {
2630         static const struct phy_reg phy_reg_init[] = {
2631                 { 0x1f, 0x0000 },
2632                 { 0x1d, 0x0f00 },
2633                 { 0x1f, 0x0002 },
2634                 { 0x0c, 0x1ec8 },
2635                 { 0x1f, 0x0000 }
2636         };
2637
2638         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2639 }
2640
2641 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
2642 {
2643         static const struct phy_reg phy_reg_init[] = {
2644                 { 0x1f, 0x0001 },
2645                 { 0x1d, 0x3d98 },
2646                 { 0x1f, 0x0000 }
2647         };
2648
2649         rtl_writephy(tp, 0x1f, 0x0000);
2650         rtl_patchphy(tp, 0x14, 1 << 5);
2651         rtl_patchphy(tp, 0x0d, 1 << 5);
2652
2653         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2654 }
2655
2656 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
2657 {
2658         static const struct phy_reg phy_reg_init[] = {
2659                 { 0x1f, 0x0001 },
2660                 { 0x12, 0x2300 },
2661                 { 0x1f, 0x0002 },
2662                 { 0x00, 0x88d4 },
2663                 { 0x01, 0x82b1 },
2664                 { 0x03, 0x7002 },
2665                 { 0x08, 0x9e30 },
2666                 { 0x09, 0x01f0 },
2667                 { 0x0a, 0x5500 },
2668                 { 0x0c, 0x00c8 },
2669                 { 0x1f, 0x0003 },
2670                 { 0x12, 0xc096 },
2671                 { 0x16, 0x000a },
2672                 { 0x1f, 0x0000 },
2673                 { 0x1f, 0x0000 },
2674                 { 0x09, 0x2000 },
2675                 { 0x09, 0x0000 }
2676         };
2677
2678         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2679
2680         rtl_patchphy(tp, 0x14, 1 << 5);
2681         rtl_patchphy(tp, 0x0d, 1 << 5);
2682         rtl_writephy(tp, 0x1f, 0x0000);
2683 }
2684
2685 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
2686 {
2687         static const struct phy_reg phy_reg_init[] = {
2688                 { 0x1f, 0x0001 },
2689                 { 0x12, 0x2300 },
2690                 { 0x03, 0x802f },
2691                 { 0x02, 0x4f02 },
2692                 { 0x01, 0x0409 },
2693                 { 0x00, 0xf099 },
2694                 { 0x04, 0x9800 },
2695                 { 0x04, 0x9000 },
2696                 { 0x1d, 0x3d98 },
2697                 { 0x1f, 0x0002 },
2698                 { 0x0c, 0x7eb8 },
2699                 { 0x06, 0x0761 },
2700                 { 0x1f, 0x0003 },
2701                 { 0x16, 0x0f0a },
2702                 { 0x1f, 0x0000 }
2703         };
2704
2705         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2706
2707         rtl_patchphy(tp, 0x16, 1 << 0);
2708         rtl_patchphy(tp, 0x14, 1 << 5);
2709         rtl_patchphy(tp, 0x0d, 1 << 5);
2710         rtl_writephy(tp, 0x1f, 0x0000);
2711 }
2712
2713 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
2714 {
2715         static const struct phy_reg phy_reg_init[] = {
2716                 { 0x1f, 0x0001 },
2717                 { 0x12, 0x2300 },
2718                 { 0x1d, 0x3d98 },
2719                 { 0x1f, 0x0002 },
2720                 { 0x0c, 0x7eb8 },
2721                 { 0x06, 0x5461 },
2722                 { 0x1f, 0x0003 },
2723                 { 0x16, 0x0f0a },
2724                 { 0x1f, 0x0000 }
2725         };
2726
2727         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2728
2729         rtl_patchphy(tp, 0x16, 1 << 0);
2730         rtl_patchphy(tp, 0x14, 1 << 5);
2731         rtl_patchphy(tp, 0x0d, 1 << 5);
2732         rtl_writephy(tp, 0x1f, 0x0000);
2733 }
2734
2735 static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
2736 {
2737         rtl8168c_3_hw_phy_config(tp);
2738 }
2739
2740 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
2741 {
2742         static const struct phy_reg phy_reg_init_0[] = {
2743                 /* Channel Estimation */
2744                 { 0x1f, 0x0001 },
2745                 { 0x06, 0x4064 },
2746                 { 0x07, 0x2863 },
2747                 { 0x08, 0x059c },
2748                 { 0x09, 0x26b4 },
2749                 { 0x0a, 0x6a19 },
2750                 { 0x0b, 0xdcc8 },
2751                 { 0x10, 0xf06d },
2752                 { 0x14, 0x7f68 },
2753                 { 0x18, 0x7fd9 },
2754                 { 0x1c, 0xf0ff },
2755                 { 0x1d, 0x3d9c },
2756                 { 0x1f, 0x0003 },
2757                 { 0x12, 0xf49f },
2758                 { 0x13, 0x070b },
2759                 { 0x1a, 0x05ad },
2760                 { 0x14, 0x94c0 },
2761
2762                 /*
2763                  * Tx Error Issue
2764                  * Enhance line driver power
2765                  */
2766                 { 0x1f, 0x0002 },
2767                 { 0x06, 0x5561 },
2768                 { 0x1f, 0x0005 },
2769                 { 0x05, 0x8332 },
2770                 { 0x06, 0x5561 },
2771
2772                 /*
2773                  * Can not link to 1Gbps with bad cable
2774                  * Decrease SNR threshold form 21.07dB to 19.04dB
2775                  */
2776                 { 0x1f, 0x0001 },
2777                 { 0x17, 0x0cc0 },
2778
2779                 { 0x1f, 0x0000 },
2780                 { 0x0d, 0xf880 }
2781         };
2782
2783         rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2784
2785         /*
2786          * Rx Error Issue
2787          * Fine Tune Switching regulator parameter
2788          */
2789         rtl_writephy(tp, 0x1f, 0x0002);
2790         rtl_w0w1_phy(tp, 0x0b, 0x0010, 0x00ef);
2791         rtl_w0w1_phy(tp, 0x0c, 0xa200, 0x5d00);
2792
2793         if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
2794                 static const struct phy_reg phy_reg_init[] = {
2795                         { 0x1f, 0x0002 },
2796                         { 0x05, 0x669a },
2797                         { 0x1f, 0x0005 },
2798                         { 0x05, 0x8330 },
2799                         { 0x06, 0x669a },
2800                         { 0x1f, 0x0002 }
2801                 };
2802                 int val;
2803
2804                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2805
2806                 val = rtl_readphy(tp, 0x0d);
2807
2808                 if ((val & 0x00ff) != 0x006c) {
2809                         static const u32 set[] = {
2810                                 0x0065, 0x0066, 0x0067, 0x0068,
2811                                 0x0069, 0x006a, 0x006b, 0x006c
2812                         };
2813                         int i;
2814
2815                         rtl_writephy(tp, 0x1f, 0x0002);
2816
2817                         val &= 0xff00;
2818                         for (i = 0; i < ARRAY_SIZE(set); i++)
2819                                 rtl_writephy(tp, 0x0d, val | set[i]);
2820                 }
2821         } else {
2822                 static const struct phy_reg phy_reg_init[] = {
2823                         { 0x1f, 0x0002 },
2824                         { 0x05, 0x6662 },
2825                         { 0x1f, 0x0005 },
2826                         { 0x05, 0x8330 },
2827                         { 0x06, 0x6662 }
2828                 };
2829
2830                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2831         }
2832
2833         /* RSET couple improve */
2834         rtl_writephy(tp, 0x1f, 0x0002);
2835         rtl_patchphy(tp, 0x0d, 0x0300);
2836         rtl_patchphy(tp, 0x0f, 0x0010);
2837
2838         /* Fine tune PLL performance */
2839         rtl_writephy(tp, 0x1f, 0x0002);
2840         rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
2841         rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
2842
2843         rtl_writephy(tp, 0x1f, 0x0005);
2844         rtl_writephy(tp, 0x05, 0x001b);
2845
2846         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
2847
2848         rtl_writephy(tp, 0x1f, 0x0000);
2849 }
2850
2851 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
2852 {
2853         static const struct phy_reg phy_reg_init_0[] = {
2854                 /* Channel Estimation */
2855                 { 0x1f, 0x0001 },
2856                 { 0x06, 0x4064 },
2857                 { 0x07, 0x2863 },
2858                 { 0x08, 0x059c },
2859                 { 0x09, 0x26b4 },
2860                 { 0x0a, 0x6a19 },
2861                 { 0x0b, 0xdcc8 },
2862                 { 0x10, 0xf06d },
2863                 { 0x14, 0x7f68 },
2864                 { 0x18, 0x7fd9 },
2865                 { 0x1c, 0xf0ff },
2866                 { 0x1d, 0x3d9c },
2867                 { 0x1f, 0x0003 },
2868                 { 0x12, 0xf49f },
2869                 { 0x13, 0x070b },
2870                 { 0x1a, 0x05ad },
2871                 { 0x14, 0x94c0 },
2872
2873                 /*
2874                  * Tx Error Issue
2875                  * Enhance line driver power
2876                  */
2877                 { 0x1f, 0x0002 },
2878                 { 0x06, 0x5561 },
2879                 { 0x1f, 0x0005 },
2880                 { 0x05, 0x8332 },
2881                 { 0x06, 0x5561 },
2882
2883                 /*
2884                  * Can not link to 1Gbps with bad cable
2885                  * Decrease SNR threshold form 21.07dB to 19.04dB
2886                  */
2887                 { 0x1f, 0x0001 },
2888                 { 0x17, 0x0cc0 },
2889
2890                 { 0x1f, 0x0000 },
2891                 { 0x0d, 0xf880 }
2892         };
2893
2894         rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2895
2896         if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
2897                 static const struct phy_reg phy_reg_init[] = {
2898                         { 0x1f, 0x0002 },
2899                         { 0x05, 0x669a },
2900                         { 0x1f, 0x0005 },
2901                         { 0x05, 0x8330 },
2902                         { 0x06, 0x669a },
2903
2904                         { 0x1f, 0x0002 }
2905                 };
2906                 int val;
2907
2908                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2909
2910                 val = rtl_readphy(tp, 0x0d);
2911                 if ((val & 0x00ff) != 0x006c) {
2912                         static const u32 set[] = {
2913                                 0x0065, 0x0066, 0x0067, 0x0068,
2914                                 0x0069, 0x006a, 0x006b, 0x006c
2915                         };
2916                         int i;
2917
2918                         rtl_writephy(tp, 0x1f, 0x0002);
2919
2920                         val &= 0xff00;
2921                         for (i = 0; i < ARRAY_SIZE(set); i++)
2922                                 rtl_writephy(tp, 0x0d, val | set[i]);
2923                 }
2924         } else {
2925                 static const struct phy_reg phy_reg_init[] = {
2926                         { 0x1f, 0x0002 },
2927                         { 0x05, 0x2642 },
2928                         { 0x1f, 0x0005 },
2929                         { 0x05, 0x8330 },
2930                         { 0x06, 0x2642 }
2931                 };
2932
2933                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2934         }
2935
2936         /* Fine tune PLL performance */
2937         rtl_writephy(tp, 0x1f, 0x0002);
2938         rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
2939         rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
2940
2941         /* Switching regulator Slew rate */
2942         rtl_writephy(tp, 0x1f, 0x0002);
2943         rtl_patchphy(tp, 0x0f, 0x0017);
2944
2945         rtl_writephy(tp, 0x1f, 0x0005);
2946         rtl_writephy(tp, 0x05, 0x001b);
2947
2948         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
2949
2950         rtl_writephy(tp, 0x1f, 0x0000);
2951 }
2952
2953 static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
2954 {
2955         static const struct phy_reg phy_reg_init[] = {
2956                 { 0x1f, 0x0002 },
2957                 { 0x10, 0x0008 },
2958                 { 0x0d, 0x006c },
2959
2960                 { 0x1f, 0x0000 },
2961                 { 0x0d, 0xf880 },
2962
2963                 { 0x1f, 0x0001 },
2964                 { 0x17, 0x0cc0 },
2965
2966                 { 0x1f, 0x0001 },
2967                 { 0x0b, 0xa4d8 },
2968                 { 0x09, 0x281c },
2969                 { 0x07, 0x2883 },
2970                 { 0x0a, 0x6b35 },
2971                 { 0x1d, 0x3da4 },
2972                 { 0x1c, 0xeffd },
2973                 { 0x14, 0x7f52 },
2974                 { 0x18, 0x7fc6 },
2975                 { 0x08, 0x0601 },
2976                 { 0x06, 0x4063 },
2977                 { 0x10, 0xf074 },
2978                 { 0x1f, 0x0003 },
2979                 { 0x13, 0x0789 },
2980                 { 0x12, 0xf4bd },
2981                 { 0x1a, 0x04fd },
2982                 { 0x14, 0x84b0 },
2983                 { 0x1f, 0x0000 },
2984                 { 0x00, 0x9200 },
2985
2986                 { 0x1f, 0x0005 },
2987                 { 0x01, 0x0340 },
2988                 { 0x1f, 0x0001 },
2989                 { 0x04, 0x4000 },
2990                 { 0x03, 0x1d21 },
2991                 { 0x02, 0x0c32 },
2992                 { 0x01, 0x0200 },
2993                 { 0x00, 0x5554 },
2994                 { 0x04, 0x4800 },
2995                 { 0x04, 0x4000 },
2996                 { 0x04, 0xf000 },
2997                 { 0x03, 0xdf01 },
2998                 { 0x02, 0xdf20 },
2999                 { 0x01, 0x101a },
3000                 { 0x00, 0xa0ff },
3001                 { 0x04, 0xf800 },
3002                 { 0x04, 0xf000 },
3003                 { 0x1f, 0x0000 },
3004
3005                 { 0x1f, 0x0007 },
3006                 { 0x1e, 0x0023 },
3007                 { 0x16, 0x0000 },
3008                 { 0x1f, 0x0000 }
3009         };
3010
3011         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3012 }
3013
3014 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
3015 {
3016         static const struct phy_reg phy_reg_init[] = {
3017                 { 0x1f, 0x0001 },
3018                 { 0x17, 0x0cc0 },
3019
3020                 { 0x1f, 0x0007 },
3021                 { 0x1e, 0x002d },
3022                 { 0x18, 0x0040 },
3023                 { 0x1f, 0x0000 }
3024         };
3025
3026         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3027         rtl_patchphy(tp, 0x0d, 1 << 5);
3028 }
3029
3030 static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
3031 {
3032         static const struct phy_reg phy_reg_init[] = {
3033                 /* Enable Delay cap */
3034                 { 0x1f, 0x0005 },
3035                 { 0x05, 0x8b80 },
3036                 { 0x06, 0xc896 },
3037                 { 0x1f, 0x0000 },
3038
3039                 /* Channel estimation fine tune */
3040                 { 0x1f, 0x0001 },
3041                 { 0x0b, 0x6c20 },
3042                 { 0x07, 0x2872 },
3043                 { 0x1c, 0xefff },
3044                 { 0x1f, 0x0003 },
3045                 { 0x14, 0x6420 },
3046                 { 0x1f, 0x0000 },
3047
3048                 /* Update PFM & 10M TX idle timer */
3049                 { 0x1f, 0x0007 },
3050                 { 0x1e, 0x002f },
3051                 { 0x15, 0x1919 },
3052                 { 0x1f, 0x0000 },
3053
3054                 { 0x1f, 0x0007 },
3055                 { 0x1e, 0x00ac },
3056                 { 0x18, 0x0006 },
3057                 { 0x1f, 0x0000 }
3058         };
3059
3060         rtl_apply_firmware(tp);
3061
3062         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3063
3064         /* DCO enable for 10M IDLE Power */
3065         rtl_writephy(tp, 0x1f, 0x0007);
3066         rtl_writephy(tp, 0x1e, 0x0023);
3067         rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
3068         rtl_writephy(tp, 0x1f, 0x0000);
3069
3070         /* For impedance matching */
3071         rtl_writephy(tp, 0x1f, 0x0002);
3072         rtl_w0w1_phy(tp, 0x08, 0x8000, 0x7f00);
3073         rtl_writephy(tp, 0x1f, 0x0000);
3074
3075         /* PHY auto speed down */
3076         rtl_writephy(tp, 0x1f, 0x0007);
3077         rtl_writephy(tp, 0x1e, 0x002d);
3078         rtl_w0w1_phy(tp, 0x18, 0x0050, 0x0000);
3079         rtl_writephy(tp, 0x1f, 0x0000);
3080         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3081
3082         rtl_writephy(tp, 0x1f, 0x0005);
3083         rtl_writephy(tp, 0x05, 0x8b86);
3084         rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3085         rtl_writephy(tp, 0x1f, 0x0000);
3086
3087         rtl_writephy(tp, 0x1f, 0x0005);
3088         rtl_writephy(tp, 0x05, 0x8b85);
3089         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
3090         rtl_writephy(tp, 0x1f, 0x0007);
3091         rtl_writephy(tp, 0x1e, 0x0020);
3092         rtl_w0w1_phy(tp, 0x15, 0x0000, 0x1100);
3093         rtl_writephy(tp, 0x1f, 0x0006);
3094         rtl_writephy(tp, 0x00, 0x5a00);
3095         rtl_writephy(tp, 0x1f, 0x0000);
3096         rtl_writephy(tp, 0x0d, 0x0007);
3097         rtl_writephy(tp, 0x0e, 0x003c);
3098         rtl_writephy(tp, 0x0d, 0x4007);
3099         rtl_writephy(tp, 0x0e, 0x0000);
3100         rtl_writephy(tp, 0x0d, 0x0000);
3101 }
3102
3103 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, u8 *addr)
3104 {
3105         const u16 w[] = {
3106                 addr[0] | (addr[1] << 8),
3107                 addr[2] | (addr[3] << 8),
3108                 addr[4] | (addr[5] << 8)
3109         };
3110         const struct exgmac_reg e[] = {
3111                 { .addr = 0xe0, ERIAR_MASK_1111, .val = w[0] | (w[1] << 16) },
3112                 { .addr = 0xe4, ERIAR_MASK_1111, .val = w[2] },
3113                 { .addr = 0xf0, ERIAR_MASK_1111, .val = w[0] << 16 },
3114                 { .addr = 0xf4, ERIAR_MASK_1111, .val = w[1] | (w[2] << 16) }
3115         };
3116
3117         rtl_write_exgmac_batch(tp, e, ARRAY_SIZE(e));
3118 }
3119
3120 static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
3121 {
3122         static const struct phy_reg phy_reg_init[] = {
3123                 /* Enable Delay cap */
3124                 { 0x1f, 0x0004 },
3125                 { 0x1f, 0x0007 },
3126                 { 0x1e, 0x00ac },
3127                 { 0x18, 0x0006 },
3128                 { 0x1f, 0x0002 },
3129                 { 0x1f, 0x0000 },
3130                 { 0x1f, 0x0000 },
3131
3132                 /* Channel estimation fine tune */
3133                 { 0x1f, 0x0003 },
3134                 { 0x09, 0xa20f },
3135                 { 0x1f, 0x0000 },
3136                 { 0x1f, 0x0000 },
3137
3138                 /* Green Setting */
3139                 { 0x1f, 0x0005 },
3140                 { 0x05, 0x8b5b },
3141                 { 0x06, 0x9222 },
3142                 { 0x05, 0x8b6d },
3143                 { 0x06, 0x8000 },
3144                 { 0x05, 0x8b76 },
3145                 { 0x06, 0x8000 },
3146                 { 0x1f, 0x0000 }
3147         };
3148
3149         rtl_apply_firmware(tp);
3150
3151         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3152
3153         /* For 4-corner performance improve */
3154         rtl_writephy(tp, 0x1f, 0x0005);
3155         rtl_writephy(tp, 0x05, 0x8b80);
3156         rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
3157         rtl_writephy(tp, 0x1f, 0x0000);
3158
3159         /* PHY auto speed down */
3160         rtl_writephy(tp, 0x1f, 0x0004);
3161         rtl_writephy(tp, 0x1f, 0x0007);
3162         rtl_writephy(tp, 0x1e, 0x002d);
3163         rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
3164         rtl_writephy(tp, 0x1f, 0x0002);
3165         rtl_writephy(tp, 0x1f, 0x0000);
3166         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3167
3168         /* improve 10M EEE waveform */
3169         rtl_writephy(tp, 0x1f, 0x0005);
3170         rtl_writephy(tp, 0x05, 0x8b86);
3171         rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3172         rtl_writephy(tp, 0x1f, 0x0000);
3173
3174         /* Improve 2-pair detection performance */
3175         rtl_writephy(tp, 0x1f, 0x0005);
3176         rtl_writephy(tp, 0x05, 0x8b85);
3177         rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3178         rtl_writephy(tp, 0x1f, 0x0000);
3179
3180         /* EEE setting */
3181         rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_1111, 0x0003, 0x0000, ERIAR_EXGMAC);
3182         rtl_writephy(tp, 0x1f, 0x0005);
3183         rtl_writephy(tp, 0x05, 0x8b85);
3184         rtl_w0w1_phy(tp, 0x06, 0x2000, 0x0000);
3185         rtl_writephy(tp, 0x1f, 0x0004);
3186         rtl_writephy(tp, 0x1f, 0x0007);
3187         rtl_writephy(tp, 0x1e, 0x0020);
3188         rtl_w0w1_phy(tp, 0x15, 0x0100, 0x0000);
3189         rtl_writephy(tp, 0x1f, 0x0002);
3190         rtl_writephy(tp, 0x1f, 0x0000);
3191         rtl_writephy(tp, 0x0d, 0x0007);
3192         rtl_writephy(tp, 0x0e, 0x003c);
3193         rtl_writephy(tp, 0x0d, 0x4007);
3194         rtl_writephy(tp, 0x0e, 0x0006);
3195         rtl_writephy(tp, 0x0d, 0x0000);
3196
3197         /* Green feature */
3198         rtl_writephy(tp, 0x1f, 0x0003);
3199         rtl_w0w1_phy(tp, 0x19, 0x0001, 0x0000);
3200         rtl_w0w1_phy(tp, 0x10, 0x0400, 0x0000);
3201         rtl_writephy(tp, 0x1f, 0x0000);
3202         rtl_writephy(tp, 0x1f, 0x0005);
3203         rtl_w0w1_phy(tp, 0x01, 0x0100, 0x0000);
3204         rtl_writephy(tp, 0x1f, 0x0000);
3205
3206         /* Broken BIOS workaround: feed GigaMAC registers with MAC address. */
3207         rtl_rar_exgmac_set(tp, tp->dev->dev_addr);
3208 }
3209
3210 static void rtl8168f_hw_phy_config(struct rtl8169_private *tp)
3211 {
3212         /* For 4-corner performance improve */
3213         rtl_writephy(tp, 0x1f, 0x0005);
3214         rtl_writephy(tp, 0x05, 0x8b80);
3215         rtl_w0w1_phy(tp, 0x06, 0x0006, 0x0000);
3216         rtl_writephy(tp, 0x1f, 0x0000);
3217
3218         /* PHY auto speed down */
3219         rtl_writephy(tp, 0x1f, 0x0007);
3220         rtl_writephy(tp, 0x1e, 0x002d);
3221         rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
3222         rtl_writephy(tp, 0x1f, 0x0000);
3223         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3224
3225         /* Improve 10M EEE waveform */
3226         rtl_writephy(tp, 0x1f, 0x0005);
3227         rtl_writephy(tp, 0x05, 0x8b86);
3228         rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3229         rtl_writephy(tp, 0x1f, 0x0000);
3230 }
3231
3232 static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp)
3233 {
3234         static const struct phy_reg phy_reg_init[] = {
3235                 /* Channel estimation fine tune */
3236                 { 0x1f, 0x0003 },
3237                 { 0x09, 0xa20f },
3238                 { 0x1f, 0x0000 },
3239
3240                 /* Modify green table for giga & fnet */
3241                 { 0x1f, 0x0005 },
3242                 { 0x05, 0x8b55 },
3243                 { 0x06, 0x0000 },
3244                 { 0x05, 0x8b5e },
3245                 { 0x06, 0x0000 },
3246                 { 0x05, 0x8b67 },
3247                 { 0x06, 0x0000 },
3248                 { 0x05, 0x8b70 },
3249                 { 0x06, 0x0000 },
3250                 { 0x1f, 0x0000 },
3251                 { 0x1f, 0x0007 },
3252                 { 0x1e, 0x0078 },
3253                 { 0x17, 0x0000 },
3254                 { 0x19, 0x00fb },
3255                 { 0x1f, 0x0000 },
3256
3257                 /* Modify green table for 10M */
3258                 { 0x1f, 0x0005 },
3259                 { 0x05, 0x8b79 },
3260                 { 0x06, 0xaa00 },
3261                 { 0x1f, 0x0000 },
3262
3263                 /* Disable hiimpedance detection (RTCT) */
3264                 { 0x1f, 0x0003 },
3265                 { 0x01, 0x328a },
3266                 { 0x1f, 0x0000 }
3267         };
3268
3269         rtl_apply_firmware(tp);
3270
3271         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3272
3273         rtl8168f_hw_phy_config(tp);
3274
3275         /* Improve 2-pair detection performance */
3276         rtl_writephy(tp, 0x1f, 0x0005);
3277         rtl_writephy(tp, 0x05, 0x8b85);
3278         rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3279         rtl_writephy(tp, 0x1f, 0x0000);
3280 }
3281
3282 static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp)
3283 {
3284         rtl_apply_firmware(tp);
3285
3286         rtl8168f_hw_phy_config(tp);
3287 }
3288
3289 static void rtl8411_hw_phy_config(struct rtl8169_private *tp)
3290 {
3291         static const struct phy_reg phy_reg_init[] = {
3292                 /* Channel estimation fine tune */
3293                 { 0x1f, 0x0003 },
3294                 { 0x09, 0xa20f },
3295                 { 0x1f, 0x0000 },
3296
3297                 /* Modify green table for giga & fnet */
3298                 { 0x1f, 0x0005 },
3299                 { 0x05, 0x8b55 },
3300                 { 0x06, 0x0000 },
3301                 { 0x05, 0x8b5e },
3302                 { 0x06, 0x0000 },
3303                 { 0x05, 0x8b67 },
3304                 { 0x06, 0x0000 },
3305                 { 0x05, 0x8b70 },
3306                 { 0x06, 0x0000 },
3307                 { 0x1f, 0x0000 },
3308                 { 0x1f, 0x0007 },
3309                 { 0x1e, 0x0078 },
3310                 { 0x17, 0x0000 },
3311                 { 0x19, 0x00aa },
3312                 { 0x1f, 0x0000 },
3313
3314                 /* Modify green table for 10M */
3315                 { 0x1f, 0x0005 },
3316                 { 0x05, 0x8b79 },
3317                 { 0x06, 0xaa00 },
3318                 { 0x1f, 0x0000 },
3319
3320                 /* Disable hiimpedance detection (RTCT) */
3321                 { 0x1f, 0x0003 },
3322                 { 0x01, 0x328a },
3323                 { 0x1f, 0x0000 }
3324         };
3325
3326
3327         rtl_apply_firmware(tp);
3328
3329         rtl8168f_hw_phy_config(tp);
3330
3331         /* Improve 2-pair detection performance */
3332         rtl_writephy(tp, 0x1f, 0x0005);
3333         rtl_writephy(tp, 0x05, 0x8b85);
3334         rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3335         rtl_writephy(tp, 0x1f, 0x0000);
3336
3337         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3338
3339         /* Modify green table for giga */
3340         rtl_writephy(tp, 0x1f, 0x0005);
3341         rtl_writephy(tp, 0x05, 0x8b54);
3342         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
3343         rtl_writephy(tp, 0x05, 0x8b5d);
3344         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
3345         rtl_writephy(tp, 0x05, 0x8a7c);
3346         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3347         rtl_writephy(tp, 0x05, 0x8a7f);
3348         rtl_w0w1_phy(tp, 0x06, 0x0100, 0x0000);
3349         rtl_writephy(tp, 0x05, 0x8a82);
3350         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3351         rtl_writephy(tp, 0x05, 0x8a85);
3352         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3353         rtl_writephy(tp, 0x05, 0x8a88);
3354         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3355         rtl_writephy(tp, 0x1f, 0x0000);
3356
3357         /* uc same-seed solution */
3358         rtl_writephy(tp, 0x1f, 0x0005);
3359         rtl_writephy(tp, 0x05, 0x8b85);
3360         rtl_w0w1_phy(tp, 0x06, 0x8000, 0x0000);
3361         rtl_writephy(tp, 0x1f, 0x0000);
3362
3363         /* eee setting */
3364         rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x00, 0x03, ERIAR_EXGMAC);
3365         rtl_writephy(tp, 0x1f, 0x0005);
3366         rtl_writephy(tp, 0x05, 0x8b85);
3367         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
3368         rtl_writephy(tp, 0x1f, 0x0004);
3369         rtl_writephy(tp, 0x1f, 0x0007);
3370         rtl_writephy(tp, 0x1e, 0x0020);
3371         rtl_w0w1_phy(tp, 0x15, 0x0000, 0x0100);
3372         rtl_writephy(tp, 0x1f, 0x0000);
3373         rtl_writephy(tp, 0x0d, 0x0007);
3374         rtl_writephy(tp, 0x0e, 0x003c);
3375         rtl_writephy(tp, 0x0d, 0x4007);
3376         rtl_writephy(tp, 0x0e, 0x0000);
3377         rtl_writephy(tp, 0x0d, 0x0000);
3378
3379         /* Green feature */
3380         rtl_writephy(tp, 0x1f, 0x0003);
3381         rtl_w0w1_phy(tp, 0x19, 0x0000, 0x0001);
3382         rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0400);
3383         rtl_writephy(tp, 0x1f, 0x0000);
3384 }
3385
3386 static void rtl8168g_1_hw_phy_config(struct rtl8169_private *tp)
3387 {
3388         rtl_apply_firmware(tp);
3389
3390         rtl_writephy(tp, 0x1f, 0x0a46);
3391         if (rtl_readphy(tp, 0x10) & 0x0100) {
3392                 rtl_writephy(tp, 0x1f, 0x0bcc);
3393                 rtl_w0w1_phy(tp, 0x12, 0x0000, 0x8000);
3394         } else {
3395                 rtl_writephy(tp, 0x1f, 0x0bcc);
3396                 rtl_w0w1_phy(tp, 0x12, 0x8000, 0x0000);
3397         }
3398
3399         rtl_writephy(tp, 0x1f, 0x0a46);
3400         if (rtl_readphy(tp, 0x13) & 0x0100) {
3401                 rtl_writephy(tp, 0x1f, 0x0c41);
3402                 rtl_w0w1_phy(tp, 0x15, 0x0002, 0x0000);
3403         } else {
3404                 rtl_writephy(tp, 0x1f, 0x0c41);
3405                 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x0002);
3406         }
3407
3408         /* Enable PHY auto speed down */
3409         rtl_writephy(tp, 0x1f, 0x0a44);
3410         rtl_w0w1_phy(tp, 0x11, 0x000c, 0x0000);
3411
3412         rtl_writephy(tp, 0x1f, 0x0bcc);
3413         rtl_w0w1_phy(tp, 0x14, 0x0100, 0x0000);
3414         rtl_writephy(tp, 0x1f, 0x0a44);
3415         rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
3416         rtl_writephy(tp, 0x1f, 0x0a43);
3417         rtl_writephy(tp, 0x13, 0x8084);
3418         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
3419         rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
3420
3421         /* EEE auto-fallback function */
3422         rtl_writephy(tp, 0x1f, 0x0a4b);
3423         rtl_w0w1_phy(tp, 0x11, 0x0004, 0x0000);
3424
3425         /* Enable UC LPF tune function */
3426         rtl_writephy(tp, 0x1f, 0x0a43);
3427         rtl_writephy(tp, 0x13, 0x8012);
3428         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3429
3430         rtl_writephy(tp, 0x1f, 0x0c42);
3431         rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
3432
3433         /* Improve SWR Efficiency */
3434         rtl_writephy(tp, 0x1f, 0x0bcd);
3435         rtl_writephy(tp, 0x14, 0x5065);
3436         rtl_writephy(tp, 0x14, 0xd065);
3437         rtl_writephy(tp, 0x1f, 0x0bc8);
3438         rtl_writephy(tp, 0x11, 0x5655);
3439         rtl_writephy(tp, 0x1f, 0x0bcd);
3440         rtl_writephy(tp, 0x14, 0x1065);
3441         rtl_writephy(tp, 0x14, 0x9065);
3442         rtl_writephy(tp, 0x14, 0x1065);
3443
3444         /* Check ALDPS bit, disable it if enabled */
3445         rtl_writephy(tp, 0x1f, 0x0a43);
3446         if (rtl_readphy(tp, 0x10) & 0x0004)
3447                 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
3448
3449         rtl_writephy(tp, 0x1f, 0x0000);
3450 }
3451
3452 static void rtl8168g_2_hw_phy_config(struct rtl8169_private *tp)
3453 {
3454         rtl_apply_firmware(tp);
3455 }
3456
3457 static void rtl8168h_1_hw_phy_config(struct rtl8169_private *tp)
3458 {
3459         u16 dout_tapbin;
3460         u32 data;
3461
3462         rtl_apply_firmware(tp);
3463
3464         /* CHN EST parameters adjust - giga master */
3465         rtl_writephy(tp, 0x1f, 0x0a43);
3466         rtl_writephy(tp, 0x13, 0x809b);
3467         rtl_w0w1_phy(tp, 0x14, 0x8000, 0xf800);
3468         rtl_writephy(tp, 0x13, 0x80a2);
3469         rtl_w0w1_phy(tp, 0x14, 0x8000, 0xff00);
3470         rtl_writephy(tp, 0x13, 0x80a4);
3471         rtl_w0w1_phy(tp, 0x14, 0x8500, 0xff00);
3472         rtl_writephy(tp, 0x13, 0x809c);
3473         rtl_w0w1_phy(tp, 0x14, 0xbd00, 0xff00);
3474         rtl_writephy(tp, 0x1f, 0x0000);
3475
3476         /* CHN EST parameters adjust - giga slave */
3477         rtl_writephy(tp, 0x1f, 0x0a43);
3478         rtl_writephy(tp, 0x13, 0x80ad);
3479         rtl_w0w1_phy(tp, 0x14, 0x7000, 0xf800);
3480         rtl_writephy(tp, 0x13, 0x80b4);
3481         rtl_w0w1_phy(tp, 0x14, 0x5000, 0xff00);
3482         rtl_writephy(tp, 0x13, 0x80ac);
3483         rtl_w0w1_phy(tp, 0x14, 0x4000, 0xff00);
3484         rtl_writephy(tp, 0x1f, 0x0000);
3485
3486         /* CHN EST parameters adjust - fnet */
3487         rtl_writephy(tp, 0x1f, 0x0a43);
3488         rtl_writephy(tp, 0x13, 0x808e);
3489         rtl_w0w1_phy(tp, 0x14, 0x1200, 0xff00);
3490         rtl_writephy(tp, 0x13, 0x8090);
3491         rtl_w0w1_phy(tp, 0x14, 0xe500, 0xff00);
3492         rtl_writephy(tp, 0x13, 0x8092);
3493         rtl_w0w1_phy(tp, 0x14, 0x9f00, 0xff00);
3494         rtl_writephy(tp, 0x1f, 0x0000);
3495
3496         /* enable R-tune & PGA-retune function */
3497         dout_tapbin = 0;
3498         rtl_writephy(tp, 0x1f, 0x0a46);
3499         data = rtl_readphy(tp, 0x13);
3500         data &= 3;
3501         data <<= 2;
3502         dout_tapbin |= data;
3503         data = rtl_readphy(tp, 0x12);
3504         data &= 0xc000;
3505         data >>= 14;
3506         dout_tapbin |= data;
3507         dout_tapbin = ~(dout_tapbin^0x08);
3508         dout_tapbin <<= 12;
3509         dout_tapbin &= 0xf000;
3510         rtl_writephy(tp, 0x1f, 0x0a43);
3511         rtl_writephy(tp, 0x13, 0x827a);
3512         rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3513         rtl_writephy(tp, 0x13, 0x827b);
3514         rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3515         rtl_writephy(tp, 0x13, 0x827c);
3516         rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3517         rtl_writephy(tp, 0x13, 0x827d);
3518         rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3519
3520         rtl_writephy(tp, 0x1f, 0x0a43);
3521         rtl_writephy(tp, 0x13, 0x0811);
3522         rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
3523         rtl_writephy(tp, 0x1f, 0x0a42);
3524         rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
3525         rtl_writephy(tp, 0x1f, 0x0000);
3526
3527         /* enable GPHY 10M */
3528         rtl_writephy(tp, 0x1f, 0x0a44);
3529         rtl_w0w1_phy(tp, 0x11, 0x0800, 0x0000);
3530         rtl_writephy(tp, 0x1f, 0x0000);
3531
3532         /* SAR ADC performance */
3533         rtl_writephy(tp, 0x1f, 0x0bca);
3534         rtl_w0w1_phy(tp, 0x17, 0x4000, 0x3000);
3535         rtl_writephy(tp, 0x1f, 0x0000);
3536
3537         rtl_writephy(tp, 0x1f, 0x0a43);
3538         rtl_writephy(tp, 0x13, 0x803f);
3539         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3540         rtl_writephy(tp, 0x13, 0x8047);
3541         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3542         rtl_writephy(tp, 0x13, 0x804f);
3543         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3544         rtl_writephy(tp, 0x13, 0x8057);
3545         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3546         rtl_writephy(tp, 0x13, 0x805f);
3547         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3548         rtl_writephy(tp, 0x13, 0x8067);
3549         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3550         rtl_writephy(tp, 0x13, 0x806f);
3551         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3552         rtl_writephy(tp, 0x1f, 0x0000);
3553
3554         /* disable phy pfm mode */
3555         rtl_writephy(tp, 0x1f, 0x0a44);
3556         rtl_w0w1_phy(tp, 0x11, 0x0000, 0x0080);
3557         rtl_writephy(tp, 0x1f, 0x0000);
3558
3559         /* Check ALDPS bit, disable it if enabled */
3560         rtl_writephy(tp, 0x1f, 0x0a43);
3561         if (rtl_readphy(tp, 0x10) & 0x0004)
3562                 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
3563
3564         rtl_writephy(tp, 0x1f, 0x0000);
3565 }
3566
3567 static void rtl8168h_2_hw_phy_config(struct rtl8169_private *tp)
3568 {
3569         u16 ioffset_p3, ioffset_p2, ioffset_p1, ioffset_p0;
3570         u16 rlen;
3571         u32 data;
3572
3573         rtl_apply_firmware(tp);
3574
3575         /* CHIN EST parameter update */
3576         rtl_writephy(tp, 0x1f, 0x0a43);
3577         rtl_writephy(tp, 0x13, 0x808a);
3578         rtl_w0w1_phy(tp, 0x14, 0x000a, 0x003f);
3579         rtl_writephy(tp, 0x1f, 0x0000);
3580
3581         /* enable R-tune & PGA-retune function */
3582         rtl_writephy(tp, 0x1f, 0x0a43);
3583         rtl_writephy(tp, 0x13, 0x0811);
3584         rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
3585         rtl_writephy(tp, 0x1f, 0x0a42);
3586         rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
3587         rtl_writephy(tp, 0x1f, 0x0000);
3588
3589         /* enable GPHY 10M */
3590         rtl_writephy(tp, 0x1f, 0x0a44);
3591         rtl_w0w1_phy(tp, 0x11, 0x0800, 0x0000);
3592         rtl_writephy(tp, 0x1f, 0x0000);
3593
3594         r8168_mac_ocp_write(tp, 0xdd02, 0x807d);
3595         data = r8168_mac_ocp_read(tp, 0xdd02);
3596         ioffset_p3 = ((data & 0x80)>>7);
3597         ioffset_p3 <<= 3;
3598
3599         data = r8168_mac_ocp_read(tp, 0xdd00);
3600         ioffset_p3 |= ((data & (0xe000))>>13);
3601         ioffset_p2 = ((data & (0x1e00))>>9);
3602         ioffset_p1 = ((data & (0x01e0))>>5);
3603         ioffset_p0 = ((data & 0x0010)>>4);
3604         ioffset_p0 <<= 3;
3605         ioffset_p0 |= (data & (0x07));
3606         data = (ioffset_p3<<12)|(ioffset_p2<<8)|(ioffset_p1<<4)|(ioffset_p0);
3607
3608         if ((ioffset_p3 != 0x0f) || (ioffset_p2 != 0x0f) ||
3609             (ioffset_p1 != 0x0f) || (ioffset_p0 != 0x0f)) {
3610                 rtl_writephy(tp, 0x1f, 0x0bcf);
3611                 rtl_writephy(tp, 0x16, data);
3612                 rtl_writephy(tp, 0x1f, 0x0000);
3613         }
3614
3615         /* Modify rlen (TX LPF corner frequency) level */
3616         rtl_writephy(tp, 0x1f, 0x0bcd);
3617         data = rtl_readphy(tp, 0x16);
3618         data &= 0x000f;
3619         rlen = 0;
3620         if (data > 3)
3621                 rlen = data - 3;
3622         data = rlen | (rlen<<4) | (rlen<<8) | (rlen<<12);
3623         rtl_writephy(tp, 0x17, data);
3624         rtl_writephy(tp, 0x1f, 0x0bcd);
3625         rtl_writephy(tp, 0x1f, 0x0000);
3626
3627         /* disable phy pfm mode */
3628         rtl_writephy(tp, 0x1f, 0x0a44);
3629         rtl_w0w1_phy(tp, 0x11, 0x0000, 0x0080);
3630         rtl_writephy(tp, 0x1f, 0x0000);
3631
3632         /* Check ALDPS bit, disable it if enabled */
3633         rtl_writephy(tp, 0x1f, 0x0a43);
3634         if (rtl_readphy(tp, 0x10) & 0x0004)
3635                 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
3636
3637         rtl_writephy(tp, 0x1f, 0x0000);
3638 }
3639
3640 static void rtl8168ep_1_hw_phy_config(struct rtl8169_private *tp)
3641 {
3642         /* Enable PHY auto speed down */
3643         rtl_writephy(tp, 0x1f, 0x0a44);
3644         rtl_w0w1_phy(tp, 0x11, 0x000c, 0x0000);
3645         rtl_writephy(tp, 0x1f, 0x0000);
3646
3647         /* patch 10M & ALDPS */
3648         rtl_writephy(tp, 0x1f, 0x0bcc);
3649         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x0100);
3650         rtl_writephy(tp, 0x1f, 0x0a44);
3651         rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
3652         rtl_writephy(tp, 0x1f, 0x0a43);
3653         rtl_writephy(tp, 0x13, 0x8084);
3654         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
3655         rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
3656         rtl_writephy(tp, 0x1f, 0x0000);
3657
3658         /* Enable EEE auto-fallback function */
3659         rtl_writephy(tp, 0x1f, 0x0a4b);
3660         rtl_w0w1_phy(tp, 0x11, 0x0004, 0x0000);
3661         rtl_writephy(tp, 0x1f, 0x0000);
3662
3663         /* Enable UC LPF tune function */
3664         rtl_writephy(tp, 0x1f, 0x0a43);
3665         rtl_writephy(tp, 0x13, 0x8012);
3666         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3667         rtl_writephy(tp, 0x1f, 0x0000);
3668
3669         /* set rg_sel_sdm_rate */
3670         rtl_writephy(tp, 0x1f, 0x0c42);
3671         rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
3672         rtl_writephy(tp, 0x1f, 0x0000);
3673
3674         /* Check ALDPS bit, disable it if enabled */
3675         rtl_writephy(tp, 0x1f, 0x0a43);
3676         if (rtl_readphy(tp, 0x10) & 0x0004)
3677                 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
3678
3679         rtl_writephy(tp, 0x1f, 0x0000);
3680 }
3681
3682 static void rtl8168ep_2_hw_phy_config(struct rtl8169_private *tp)
3683 {
3684         /* patch 10M & ALDPS */
3685         rtl_writephy(tp, 0x1f, 0x0bcc);
3686         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x0100);
3687         rtl_writephy(tp, 0x1f, 0x0a44);
3688         rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
3689         rtl_writephy(tp, 0x1f, 0x0a43);
3690         rtl_writephy(tp, 0x13, 0x8084);
3691         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
3692         rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
3693         rtl_writephy(tp, 0x1f, 0x0000);
3694
3695         /* Enable UC LPF tune function */
3696         rtl_writephy(tp, 0x1f, 0x0a43);
3697         rtl_writephy(tp, 0x13, 0x8012);
3698         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3699         rtl_writephy(tp, 0x1f, 0x0000);
3700
3701         /* Set rg_sel_sdm_rate */
3702         rtl_writephy(tp, 0x1f, 0x0c42);
3703         rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
3704         rtl_writephy(tp, 0x1f, 0x0000);
3705
3706         /* Channel estimation parameters */
3707         rtl_writephy(tp, 0x1f, 0x0a43);
3708         rtl_writephy(tp, 0x13, 0x80f3);
3709         rtl_w0w1_phy(tp, 0x14, 0x8b00, ~0x8bff);
3710         rtl_writephy(tp, 0x13, 0x80f0);
3711         rtl_w0w1_phy(tp, 0x14, 0x3a00, ~0x3aff);
3712         rtl_writephy(tp, 0x13, 0x80ef);
3713         rtl_w0w1_phy(tp, 0x14, 0x0500, ~0x05ff);
3714         rtl_writephy(tp, 0x13, 0x80f6);
3715         rtl_w0w1_phy(tp, 0x14, 0x6e00, ~0x6eff);
3716         rtl_writephy(tp, 0x13, 0x80ec);
3717         rtl_w0w1_phy(tp, 0x14, 0x6800, ~0x68ff);
3718         rtl_writephy(tp, 0x13, 0x80ed);
3719         rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
3720         rtl_writephy(tp, 0x13, 0x80f2);
3721         rtl_w0w1_phy(tp, 0x14, 0xf400, ~0xf4ff);
3722         rtl_writephy(tp, 0x13, 0x80f4);
3723         rtl_w0w1_phy(tp, 0x14, 0x8500, ~0x85ff);
3724         rtl_writephy(tp, 0x1f, 0x0a43);
3725         rtl_writephy(tp, 0x13, 0x8110);
3726         rtl_w0w1_phy(tp, 0x14, 0xa800, ~0xa8ff);
3727         rtl_writephy(tp, 0x13, 0x810f);
3728         rtl_w0w1_phy(tp, 0x14, 0x1d00, ~0x1dff);
3729         rtl_writephy(tp, 0x13, 0x8111);
3730         rtl_w0w1_phy(tp, 0x14, 0xf500, ~0xf5ff);
3731         rtl_writephy(tp, 0x13, 0x8113);
3732         rtl_w0w1_phy(tp, 0x14, 0x6100, ~0x61ff);
3733         rtl_writephy(tp, 0x13, 0x8115);
3734         rtl_w0w1_phy(tp, 0x14, 0x9200, ~0x92ff);
3735         rtl_writephy(tp, 0x13, 0x810e);
3736         rtl_w0w1_phy(tp, 0x14, 0x0400, ~0x04ff);
3737         rtl_writephy(tp, 0x13, 0x810c);
3738         rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
3739         rtl_writephy(tp, 0x13, 0x810b);
3740         rtl_w0w1_phy(tp, 0x14, 0x5a00, ~0x5aff);
3741         rtl_writephy(tp, 0x1f, 0x0a43);
3742         rtl_writephy(tp, 0x13, 0x80d1);
3743         rtl_w0w1_phy(tp, 0x14, 0xff00, ~0xffff);
3744         rtl_writephy(tp, 0x13, 0x80cd);
3745         rtl_w0w1_phy(tp, 0x14, 0x9e00, ~0x9eff);
3746         rtl_writephy(tp, 0x13, 0x80d3);
3747         rtl_w0w1_phy(tp, 0x14, 0x0e00, ~0x0eff);
3748         rtl_writephy(tp, 0x13, 0x80d5);
3749         rtl_w0w1_phy(tp, 0x14, 0xca00, ~0xcaff);
3750         rtl_writephy(tp, 0x13, 0x80d7);
3751         rtl_w0w1_phy(tp, 0x14, 0x8400, ~0x84ff);
3752
3753         /* Force PWM-mode */
3754         rtl_writephy(tp, 0x1f, 0x0bcd);
3755         rtl_writephy(tp, 0x14, 0x5065);
3756         rtl_writephy(tp, 0x14, 0xd065);
3757         rtl_writephy(tp, 0x1f, 0x0bc8);
3758         rtl_writephy(tp, 0x12, 0x00ed);
3759         rtl_writephy(tp, 0x1f, 0x0bcd);
3760         rtl_writephy(tp, 0x14, 0x1065);
3761         rtl_writephy(tp, 0x14, 0x9065);
3762         rtl_writephy(tp, 0x14, 0x1065);
3763         rtl_writephy(tp, 0x1f, 0x0000);
3764
3765         /* Check ALDPS bit, disable it if enabled */
3766         rtl_writephy(tp, 0x1f, 0x0a43);
3767         if (rtl_readphy(tp, 0x10) & 0x0004)
3768                 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
3769
3770         rtl_writephy(tp, 0x1f, 0x0000);
3771 }
3772
3773 static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
3774 {
3775         static const struct phy_reg phy_reg_init[] = {
3776                 { 0x1f, 0x0003 },
3777                 { 0x08, 0x441d },
3778                 { 0x01, 0x9100 },
3779                 { 0x1f, 0x0000 }
3780         };
3781
3782         rtl_writephy(tp, 0x1f, 0x0000);
3783         rtl_patchphy(tp, 0x11, 1 << 12);
3784         rtl_patchphy(tp, 0x19, 1 << 13);
3785         rtl_patchphy(tp, 0x10, 1 << 15);
3786
3787         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3788 }
3789
3790 static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
3791 {
3792         static const struct phy_reg phy_reg_init[] = {
3793                 { 0x1f, 0x0005 },
3794                 { 0x1a, 0x0000 },
3795                 { 0x1f, 0x0000 },
3796
3797                 { 0x1f, 0x0004 },
3798                 { 0x1c, 0x0000 },
3799                 { 0x1f, 0x0000 },
3800
3801                 { 0x1f, 0x0001 },
3802                 { 0x15, 0x7701 },
3803                 { 0x1f, 0x0000 }
3804         };
3805
3806         /* Disable ALDPS before ram code */
3807         rtl_writephy(tp, 0x1f, 0x0000);
3808         rtl_writephy(tp, 0x18, 0x0310);
3809         msleep(100);
3810
3811         rtl_apply_firmware(tp);
3812
3813         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3814 }
3815
3816 static void rtl8402_hw_phy_config(struct rtl8169_private *tp)
3817 {
3818         /* Disable ALDPS before setting firmware */
3819         rtl_writephy(tp, 0x1f, 0x0000);
3820         rtl_writephy(tp, 0x18, 0x0310);
3821         msleep(20);
3822
3823         rtl_apply_firmware(tp);
3824
3825         /* EEE setting */
3826         rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
3827         rtl_writephy(tp, 0x1f, 0x0004);
3828         rtl_writephy(tp, 0x10, 0x401f);
3829         rtl_writephy(tp, 0x19, 0x7030);
3830         rtl_writephy(tp, 0x1f, 0x0000);
3831 }
3832
3833 static void rtl8106e_hw_phy_config(struct rtl8169_private *tp)
3834 {
3835         static const struct phy_reg phy_reg_init[] = {
3836                 { 0x1f, 0x0004 },
3837                 { 0x10, 0xc07f },
3838                 { 0x19, 0x7030 },
3839                 { 0x1f, 0x0000 }
3840         };
3841
3842         /* Disable ALDPS before ram code */
3843         rtl_writephy(tp, 0x1f, 0x0000);
3844         rtl_writephy(tp, 0x18, 0x0310);
3845         msleep(100);
3846
3847         rtl_apply_firmware(tp);
3848
3849         rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
3850         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3851
3852         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
3853 }
3854
3855 static void rtl_hw_phy_config(struct net_device *dev)
3856 {
3857         struct rtl8169_private *tp = netdev_priv(dev);
3858
3859         switch (tp->mac_version) {
3860         case RTL_GIGA_MAC_VER_01:
3861                 break;
3862         case RTL_GIGA_MAC_VER_02:
3863         case RTL_GIGA_MAC_VER_03:
3864                 rtl8169s_hw_phy_config(tp);
3865                 break;
3866         case RTL_GIGA_MAC_VER_04:
3867                 rtl8169sb_hw_phy_config(tp);
3868                 break;
3869         case RTL_GIGA_MAC_VER_05:
3870                 rtl8169scd_hw_phy_config(tp);
3871                 break;
3872         case RTL_GIGA_MAC_VER_06:
3873                 rtl8169sce_hw_phy_config(tp);
3874                 break;
3875         case RTL_GIGA_MAC_VER_07:
3876         case RTL_GIGA_MAC_VER_08:
3877         case RTL_GIGA_MAC_VER_09:
3878                 rtl8102e_hw_phy_config(tp);
3879                 break;
3880         case RTL_GIGA_MAC_VER_11:
3881                 rtl8168bb_hw_phy_config(tp);
3882                 break;
3883         case RTL_GIGA_MAC_VER_12:
3884                 rtl8168bef_hw_phy_config(tp);
3885                 break;
3886         case RTL_GIGA_MAC_VER_17:
3887                 rtl8168bef_hw_phy_config(tp);
3888                 break;
3889         case RTL_GIGA_MAC_VER_18:
3890                 rtl8168cp_1_hw_phy_config(tp);
3891                 break;
3892         case RTL_GIGA_MAC_VER_19:
3893                 rtl8168c_1_hw_phy_config(tp);
3894                 break;
3895         case RTL_GIGA_MAC_VER_20:
3896                 rtl8168c_2_hw_phy_config(tp);
3897                 break;
3898         case RTL_GIGA_MAC_VER_21:
3899                 rtl8168c_3_hw_phy_config(tp);
3900                 break;
3901         case RTL_GIGA_MAC_VER_22:
3902                 rtl8168c_4_hw_phy_config(tp);
3903                 break;
3904         case RTL_GIGA_MAC_VER_23:
3905         case RTL_GIGA_MAC_VER_24:
3906                 rtl8168cp_2_hw_phy_config(tp);
3907                 break;
3908         case RTL_GIGA_MAC_VER_25:
3909                 rtl8168d_1_hw_phy_config(tp);
3910                 break;
3911         case RTL_GIGA_MAC_VER_26:
3912                 rtl8168d_2_hw_phy_config(tp);
3913                 break;
3914         case RTL_GIGA_MAC_VER_27:
3915                 rtl8168d_3_hw_phy_config(tp);
3916                 break;
3917         case RTL_GIGA_MAC_VER_28:
3918                 rtl8168d_4_hw_phy_config(tp);
3919                 break;
3920         case RTL_GIGA_MAC_VER_29:
3921         case RTL_GIGA_MAC_VER_30:
3922                 rtl8105e_hw_phy_config(tp);
3923                 break;
3924         case RTL_GIGA_MAC_VER_31:
3925                 /* None. */
3926                 break;
3927         case RTL_GIGA_MAC_VER_32:
3928         case RTL_GIGA_MAC_VER_33:
3929                 rtl8168e_1_hw_phy_config(tp);
3930                 break;
3931         case RTL_GIGA_MAC_VER_34:
3932                 rtl8168e_2_hw_phy_config(tp);
3933                 break;
3934         case RTL_GIGA_MAC_VER_35:
3935                 rtl8168f_1_hw_phy_config(tp);
3936                 break;
3937         case RTL_GIGA_MAC_VER_36:
3938                 rtl8168f_2_hw_phy_config(tp);
3939                 break;
3940
3941         case RTL_GIGA_MAC_VER_37:
3942                 rtl8402_hw_phy_config(tp);
3943                 break;
3944
3945         case RTL_GIGA_MAC_VER_38:
3946                 rtl8411_hw_phy_config(tp);
3947                 break;
3948
3949         case RTL_GIGA_MAC_VER_39:
3950                 rtl8106e_hw_phy_config(tp);
3951                 break;
3952
3953         case RTL_GIGA_MAC_VER_40:
3954                 rtl8168g_1_hw_phy_config(tp);
3955                 break;
3956         case RTL_GIGA_MAC_VER_42:
3957         case RTL_GIGA_MAC_VER_43:
3958         case RTL_GIGA_MAC_VER_44:
3959                 rtl8168g_2_hw_phy_config(tp);
3960                 break;
3961         case RTL_GIGA_MAC_VER_45:
3962         case RTL_GIGA_MAC_VER_47:
3963                 rtl8168h_1_hw_phy_config(tp);
3964                 break;
3965         case RTL_GIGA_MAC_VER_46:
3966         case RTL_GIGA_MAC_VER_48:
3967                 rtl8168h_2_hw_phy_config(tp);
3968                 break;
3969
3970         case RTL_GIGA_MAC_VER_49:
3971                 rtl8168ep_1_hw_phy_config(tp);
3972                 break;
3973         case RTL_GIGA_MAC_VER_50:
3974         case RTL_GIGA_MAC_VER_51:
3975                 rtl8168ep_2_hw_phy_config(tp);
3976                 break;
3977
3978         case RTL_GIGA_MAC_VER_41:
3979         default:
3980                 break;
3981         }
3982 }
3983
3984 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
3985 {
3986         if (!test_and_set_bit(flag, tp->wk.flags))
3987                 schedule_work(&tp->wk.work);
3988 }
3989
3990 static bool rtl_tbi_enabled(struct rtl8169_private *tp)
3991 {
3992         return (tp->mac_version == RTL_GIGA_MAC_VER_01) &&
3993                (RTL_R8(tp, PHYstatus) & TBI_Enable);
3994 }
3995
3996 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
3997 {
3998         rtl_hw_phy_config(dev);
3999
4000         if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
4001                 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
4002                 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4003                 netif_dbg(tp, drv, dev,
4004                           "Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
4005                 RTL_W8(tp, 0x82, 0x01);
4006         }
4007
4008         /* We may have called phy_speed_down before */
4009         phy_speed_up(dev->phydev);
4010
4011         genphy_soft_reset(dev->phydev);
4012
4013         /* It was reported that several chips end up with 10MBit/Half on a
4014          * 1GBit link after resuming from S3. For whatever reason the PHY on
4015          * these chips doesn't properly start a renegotiation when soft-reset.
4016          * Explicitly requesting a renegotiation fixes this.
4017          */
4018         if (dev->phydev->autoneg == AUTONEG_ENABLE)
4019                 phy_restart_aneg(dev->phydev);
4020 }
4021
4022 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
4023 {
4024         rtl_lock_work(tp);
4025
4026         RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
4027
4028         RTL_W32(tp, MAC4, addr[4] | addr[5] << 8);
4029         RTL_R32(tp, MAC4);
4030
4031         RTL_W32(tp, MAC0, addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24);
4032         RTL_R32(tp, MAC0);
4033
4034         if (tp->mac_version == RTL_GIGA_MAC_VER_34)
4035                 rtl_rar_exgmac_set(tp, addr);
4036
4037         RTL_W8(tp, Cfg9346, Cfg9346_Lock);
4038
4039         rtl_unlock_work(tp);
4040 }
4041
4042 static int rtl_set_mac_address(struct net_device *dev, void *p)
4043 {
4044         struct rtl8169_private *tp = netdev_priv(dev);
4045         struct device *d = tp_to_dev(tp);
4046         int ret;
4047
4048         ret = eth_mac_addr(dev, p);
4049         if (ret)
4050                 return ret;
4051
4052         pm_runtime_get_noresume(d);
4053
4054         if (pm_runtime_active(d))
4055                 rtl_rar_set(tp, dev->dev_addr);
4056
4057         pm_runtime_put_noidle(d);
4058
4059         return 0;
4060 }
4061
4062 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
4063 {
4064         if (!netif_running(dev))
4065                 return -ENODEV;
4066
4067         return phy_mii_ioctl(dev->phydev, ifr, cmd);
4068 }
4069
4070 static void rtl_init_mdio_ops(struct rtl8169_private *tp)
4071 {
4072         struct mdio_ops *ops = &tp->mdio_ops;
4073
4074         switch (tp->mac_version) {
4075         case RTL_GIGA_MAC_VER_27:
4076                 ops->write      = r8168dp_1_mdio_write;
4077                 ops->read       = r8168dp_1_mdio_read;
4078                 break;
4079         case RTL_GIGA_MAC_VER_28:
4080         case RTL_GIGA_MAC_VER_31:
4081                 ops->write      = r8168dp_2_mdio_write;
4082                 ops->read       = r8168dp_2_mdio_read;
4083                 break;
4084         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
4085                 ops->write      = r8168g_mdio_write;
4086                 ops->read       = r8168g_mdio_read;
4087                 break;
4088         default:
4089                 ops->write      = r8169_mdio_write;
4090                 ops->read       = r8169_mdio_read;
4091                 break;
4092         }
4093 }
4094
4095 static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
4096 {
4097         switch (tp->mac_version) {
4098         case RTL_GIGA_MAC_VER_25:
4099         case RTL_GIGA_MAC_VER_26:
4100         case RTL_GIGA_MAC_VER_29:
4101         case RTL_GIGA_MAC_VER_30:
4102         case RTL_GIGA_MAC_VER_32:
4103         case RTL_GIGA_MAC_VER_33:
4104         case RTL_GIGA_MAC_VER_34:
4105         case RTL_GIGA_MAC_VER_37 ... RTL_GIGA_MAC_VER_51:
4106                 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) |
4107                         AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
4108                 break;
4109         default:
4110                 break;
4111         }
4112 }
4113
4114 static bool rtl_wol_pll_power_down(struct rtl8169_private *tp)
4115 {
4116         struct phy_device *phydev;
4117
4118         if (!__rtl8169_get_wol(tp))
4119                 return false;
4120
4121         /* phydev may not be attached to netdevice */
4122         phydev = mdiobus_get_phy(tp->mii_bus, 0);
4123
4124         phy_speed_down(phydev, false);
4125         rtl_wol_suspend_quirk(tp);
4126
4127         return true;
4128 }
4129
4130 static void r8168_pll_power_down(struct rtl8169_private *tp)
4131 {
4132         if (r8168_check_dash(tp))
4133                 return;
4134
4135         if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
4136             tp->mac_version == RTL_GIGA_MAC_VER_33)
4137                 rtl_ephy_write(tp, 0x19, 0xff64);
4138
4139         if (rtl_wol_pll_power_down(tp))
4140                 return;
4141
4142         switch (tp->mac_version) {
4143         case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_33:
4144         case RTL_GIGA_MAC_VER_37:
4145         case RTL_GIGA_MAC_VER_39:
4146         case RTL_GIGA_MAC_VER_43:
4147         case RTL_GIGA_MAC_VER_44:
4148         case RTL_GIGA_MAC_VER_45:
4149         case RTL_GIGA_MAC_VER_46:
4150         case RTL_GIGA_MAC_VER_47:
4151         case RTL_GIGA_MAC_VER_48:
4152         case RTL_GIGA_MAC_VER_50:
4153         case RTL_GIGA_MAC_VER_51:
4154                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80);
4155                 break;
4156         case RTL_GIGA_MAC_VER_40:
4157         case RTL_GIGA_MAC_VER_41:
4158         case RTL_GIGA_MAC_VER_49:
4159                 rtl_w0w1_eri(tp, 0x1a8, ERIAR_MASK_1111, 0x00000000,
4160                              0xfc000000, ERIAR_EXGMAC);
4161                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80);
4162                 break;
4163         }
4164 }
4165
4166 static void r8168_pll_power_up(struct rtl8169_private *tp)
4167 {
4168         switch (tp->mac_version) {
4169         case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_33:
4170         case RTL_GIGA_MAC_VER_37:
4171         case RTL_GIGA_MAC_VER_39:
4172         case RTL_GIGA_MAC_VER_43:
4173                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0x80);
4174                 break;
4175         case RTL_GIGA_MAC_VER_44:
4176         case RTL_GIGA_MAC_VER_45:
4177         case RTL_GIGA_MAC_VER_46:
4178         case RTL_GIGA_MAC_VER_47:
4179         case RTL_GIGA_MAC_VER_48:
4180         case RTL_GIGA_MAC_VER_50:
4181         case RTL_GIGA_MAC_VER_51:
4182                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0);
4183                 break;
4184         case RTL_GIGA_MAC_VER_40:
4185         case RTL_GIGA_MAC_VER_41:
4186         case RTL_GIGA_MAC_VER_49:
4187                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0);
4188                 rtl_w0w1_eri(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000,
4189                              0x00000000, ERIAR_EXGMAC);
4190                 break;
4191         }
4192
4193         phy_resume(tp->dev->phydev);
4194         /* give MAC/PHY some time to resume */
4195         msleep(20);
4196 }
4197
4198 static void rtl_pll_power_down(struct rtl8169_private *tp)
4199 {
4200         switch (tp->mac_version) {
4201         case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_06:
4202         case RTL_GIGA_MAC_VER_13 ... RTL_GIGA_MAC_VER_15:
4203                 break;
4204         default:
4205                 r8168_pll_power_down(tp);
4206         }
4207 }
4208
4209 static void rtl_pll_power_up(struct rtl8169_private *tp)
4210 {
4211         switch (tp->mac_version) {
4212         case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_06:
4213         case RTL_GIGA_MAC_VER_13 ... RTL_GIGA_MAC_VER_15:
4214                 break;
4215         default:
4216                 r8168_pll_power_up(tp);
4217         }
4218 }
4219
4220 static void rtl_init_rxcfg(struct rtl8169_private *tp)
4221 {
4222         switch (tp->mac_version) {
4223         case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_06:
4224         case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
4225                 RTL_W32(tp, RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
4226                 break;
4227         case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
4228         case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36:
4229         case RTL_GIGA_MAC_VER_38:
4230                 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
4231                 break;
4232         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
4233                 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF);
4234                 break;
4235         default:
4236                 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_DMA_BURST);
4237                 break;
4238         }
4239 }
4240
4241 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
4242 {
4243         tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0;
4244 }
4245
4246 static void rtl_hw_jumbo_enable(struct rtl8169_private *tp)
4247 {
4248         if (tp->jumbo_ops.enable) {
4249                 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
4250                 tp->jumbo_ops.enable(tp);
4251                 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
4252         }
4253 }
4254
4255 static void rtl_hw_jumbo_disable(struct rtl8169_private *tp)
4256 {
4257         if (tp->jumbo_ops.disable) {
4258                 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
4259                 tp->jumbo_ops.disable(tp);
4260                 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
4261         }
4262 }
4263
4264 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
4265 {
4266         RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
4267         RTL_W8(tp, Config4, RTL_R8(tp, Config4) | Jumbo_En1);
4268         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_512B);
4269 }
4270
4271 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
4272 {
4273         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
4274         RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~Jumbo_En1);
4275         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4276 }
4277
4278 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
4279 {
4280         RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
4281 }
4282
4283 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
4284 {
4285         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
4286 }
4287
4288 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
4289 {
4290         RTL_W8(tp, MaxTxPacketSize, 0x3f);
4291         RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
4292         RTL_W8(tp, Config4, RTL_R8(tp, Config4) | 0x01);
4293         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_512B);
4294 }
4295
4296 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
4297 {
4298         RTL_W8(tp, MaxTxPacketSize, 0x0c);
4299         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
4300         RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~0x01);
4301         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4302 }
4303
4304 static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp)
4305 {
4306         rtl_tx_performance_tweak(tp,
4307                 PCI_EXP_DEVCTL_READRQ_512B | PCI_EXP_DEVCTL_NOSNOOP_EN);
4308 }
4309
4310 static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp)
4311 {
4312         rtl_tx_performance_tweak(tp,
4313                 PCI_EXP_DEVCTL_READRQ_4096B | PCI_EXP_DEVCTL_NOSNOOP_EN);
4314 }
4315
4316 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
4317 {
4318         r8168b_0_hw_jumbo_enable(tp);
4319
4320         RTL_W8(tp, Config4, RTL_R8(tp, Config4) | (1 << 0));
4321 }
4322
4323 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
4324 {
4325         r8168b_0_hw_jumbo_disable(tp);
4326
4327         RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0));
4328 }
4329
4330 static void rtl_init_jumbo_ops(struct rtl8169_private *tp)
4331 {
4332         struct jumbo_ops *ops = &tp->jumbo_ops;
4333
4334         switch (tp->mac_version) {
4335         case RTL_GIGA_MAC_VER_11:
4336                 ops->disable    = r8168b_0_hw_jumbo_disable;
4337                 ops->enable     = r8168b_0_hw_jumbo_enable;
4338                 break;
4339         case RTL_GIGA_MAC_VER_12:
4340         case RTL_GIGA_MAC_VER_17:
4341                 ops->disable    = r8168b_1_hw_jumbo_disable;
4342                 ops->enable     = r8168b_1_hw_jumbo_enable;
4343                 break;
4344         case RTL_GIGA_MAC_VER_18: /* Wild guess. Needs info from Realtek. */
4345         case RTL_GIGA_MAC_VER_19:
4346         case RTL_GIGA_MAC_VER_20:
4347         case RTL_GIGA_MAC_VER_21: /* Wild guess. Needs info from Realtek. */
4348         case RTL_GIGA_MAC_VER_22:
4349         case RTL_GIGA_MAC_VER_23:
4350         case RTL_GIGA_MAC_VER_24:
4351         case RTL_GIGA_MAC_VER_25:
4352         case RTL_GIGA_MAC_VER_26:
4353                 ops->disable    = r8168c_hw_jumbo_disable;
4354                 ops->enable     = r8168c_hw_jumbo_enable;
4355                 break;
4356         case RTL_GIGA_MAC_VER_27:
4357         case RTL_GIGA_MAC_VER_28:
4358                 ops->disable    = r8168dp_hw_jumbo_disable;
4359                 ops->enable     = r8168dp_hw_jumbo_enable;
4360                 break;
4361         case RTL_GIGA_MAC_VER_31: /* Wild guess. Needs info from Realtek. */
4362         case RTL_GIGA_MAC_VER_32:
4363         case RTL_GIGA_MAC_VER_33:
4364         case RTL_GIGA_MAC_VER_34:
4365                 ops->disable    = r8168e_hw_jumbo_disable;
4366                 ops->enable     = r8168e_hw_jumbo_enable;
4367                 break;
4368
4369         /*
4370          * No action needed for jumbo frames with 8169.
4371          * No jumbo for 810x at all.
4372          */
4373         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
4374         default:
4375                 ops->disable    = NULL;
4376                 ops->enable     = NULL;
4377                 break;
4378         }
4379 }
4380
4381 DECLARE_RTL_COND(rtl_chipcmd_cond)
4382 {
4383         return RTL_R8(tp, ChipCmd) & CmdReset;
4384 }
4385
4386 static void rtl_hw_reset(struct rtl8169_private *tp)
4387 {
4388         RTL_W8(tp, ChipCmd, CmdReset);
4389
4390         rtl_udelay_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100);
4391 }
4392
4393 static void rtl_request_uncached_firmware(struct rtl8169_private *tp)
4394 {
4395         struct rtl_fw *rtl_fw;
4396         const char *name;
4397         int rc = -ENOMEM;
4398
4399         name = rtl_lookup_firmware_name(tp);
4400         if (!name)
4401                 goto out_no_firmware;
4402
4403         rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
4404         if (!rtl_fw)
4405                 goto err_warn;
4406
4407         rc = request_firmware(&rtl_fw->fw, name, tp_to_dev(tp));
4408         if (rc < 0)
4409                 goto err_free;
4410
4411         rc = rtl_check_firmware(tp, rtl_fw);
4412         if (rc < 0)
4413                 goto err_release_firmware;
4414
4415         tp->rtl_fw = rtl_fw;
4416 out:
4417         return;
4418
4419 err_release_firmware:
4420         release_firmware(rtl_fw->fw);
4421 err_free:
4422         kfree(rtl_fw);
4423 err_warn:
4424         netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n",
4425                    name, rc);
4426 out_no_firmware:
4427         tp->rtl_fw = NULL;
4428         goto out;
4429 }
4430
4431 static void rtl_request_firmware(struct rtl8169_private *tp)
4432 {
4433         if (IS_ERR(tp->rtl_fw))
4434                 rtl_request_uncached_firmware(tp);
4435 }
4436
4437 static void rtl_rx_close(struct rtl8169_private *tp)
4438 {
4439         RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
4440 }
4441
4442 DECLARE_RTL_COND(rtl_npq_cond)
4443 {
4444         return RTL_R8(tp, TxPoll) & NPQ;
4445 }
4446
4447 DECLARE_RTL_COND(rtl_txcfg_empty_cond)
4448 {
4449         return RTL_R32(tp, TxConfig) & TXCFG_EMPTY;
4450 }
4451
4452 static void rtl8169_hw_reset(struct rtl8169_private *tp)
4453 {
4454         /* Disable interrupts */
4455         rtl8169_irq_mask_and_ack(tp);
4456
4457         rtl_rx_close(tp);
4458
4459         switch (tp->mac_version) {
4460         case RTL_GIGA_MAC_VER_27:
4461         case RTL_GIGA_MAC_VER_28:
4462         case RTL_GIGA_MAC_VER_31:
4463                 rtl_udelay_loop_wait_low(tp, &rtl_npq_cond, 20, 42*42);
4464                 break;
4465         case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
4466         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
4467                 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
4468                 rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);
4469                 break;
4470         default:
4471                 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
4472                 udelay(100);
4473                 break;
4474         }
4475
4476         rtl_hw_reset(tp);
4477 }
4478
4479 static void rtl_set_tx_config_registers(struct rtl8169_private *tp)
4480 {
4481         u32 val = TX_DMA_BURST << TxDMAShift |
4482                   InterFrameGap << TxInterFrameGapShift;
4483
4484         if (tp->mac_version >= RTL_GIGA_MAC_VER_34 &&
4485             tp->mac_version != RTL_GIGA_MAC_VER_39)
4486                 val |= TXCFG_AUTO_FIFO;
4487
4488         RTL_W32(tp, TxConfig, val);
4489 }
4490
4491 static void rtl_set_rx_max_size(struct rtl8169_private *tp)
4492 {
4493         /* Low hurts. Let's disable the filtering. */
4494         RTL_W16(tp, RxMaxSize, R8169_RX_BUF_SIZE + 1);
4495 }
4496
4497 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp)
4498 {
4499         /*
4500          * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
4501          * register to be written before TxDescAddrLow to work.
4502          * Switching from MMIO to I/O access fixes the issue as well.
4503          */
4504         RTL_W32(tp, TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
4505         RTL_W32(tp, TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
4506         RTL_W32(tp, RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
4507         RTL_W32(tp, RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
4508 }
4509
4510 static void rtl8169_set_magic_reg(struct rtl8169_private *tp, unsigned mac_version)
4511 {
4512         u32 val;
4513
4514         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
4515                 val = 0x000fff00;
4516         else if (tp->mac_version == RTL_GIGA_MAC_VER_06)
4517                 val = 0x00ffff00;
4518         else
4519                 return;
4520
4521         if (RTL_R8(tp, Config2) & PCI_Clock_66MHz)
4522                 val |= 0xff;
4523
4524         RTL_W32(tp, 0x7c, val);
4525 }
4526
4527 static void rtl_set_rx_mode(struct net_device *dev)
4528 {
4529         struct rtl8169_private *tp = netdev_priv(dev);
4530         u32 mc_filter[2];       /* Multicast hash filter */
4531         int rx_mode;
4532         u32 tmp = 0;
4533
4534         if (dev->flags & IFF_PROMISC) {
4535                 /* Unconditionally log net taps. */
4536                 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
4537                 rx_mode =
4538                     AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
4539                     AcceptAllPhys;
4540                 mc_filter[1] = mc_filter[0] = 0xffffffff;
4541         } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
4542                    (dev->flags & IFF_ALLMULTI)) {
4543                 /* Too many to filter perfectly -- accept all multicasts. */
4544                 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
4545                 mc_filter[1] = mc_filter[0] = 0xffffffff;
4546         } else {
4547                 struct netdev_hw_addr *ha;
4548
4549                 rx_mode = AcceptBroadcast | AcceptMyPhys;
4550                 mc_filter[1] = mc_filter[0] = 0;
4551                 netdev_for_each_mc_addr(ha, dev) {
4552                         int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
4553                         mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
4554                         rx_mode |= AcceptMulticast;
4555                 }
4556         }
4557
4558         if (dev->features & NETIF_F_RXALL)
4559                 rx_mode |= (AcceptErr | AcceptRunt);
4560
4561         tmp = (RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK) | rx_mode;
4562
4563         if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
4564                 u32 data = mc_filter[0];
4565
4566                 mc_filter[0] = swab32(mc_filter[1]);
4567                 mc_filter[1] = swab32(data);
4568         }
4569
4570         if (tp->mac_version == RTL_GIGA_MAC_VER_35)
4571                 mc_filter[1] = mc_filter[0] = 0xffffffff;
4572
4573         RTL_W32(tp, MAR0 + 4, mc_filter[1]);
4574         RTL_W32(tp, MAR0 + 0, mc_filter[0]);
4575
4576         RTL_W32(tp, RxConfig, tmp);
4577 }
4578
4579 static void rtl_hw_start(struct  rtl8169_private *tp)
4580 {
4581         RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
4582
4583         tp->hw_start(tp);
4584
4585         rtl_set_rx_max_size(tp);
4586         rtl_set_rx_tx_desc_registers(tp);
4587         RTL_W8(tp, Cfg9346, Cfg9346_Lock);
4588
4589         /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
4590         RTL_R8(tp, IntrMask);
4591         RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb);
4592         rtl_init_rxcfg(tp);
4593         rtl_set_tx_config_registers(tp);
4594
4595         rtl_set_rx_mode(tp->dev);
4596         /* no early-rx interrupts */
4597         RTL_W16(tp, MultiIntr, RTL_R16(tp, MultiIntr) & 0xf000);
4598         rtl_irq_enable(tp);
4599 }
4600
4601 static void rtl_hw_start_8169(struct rtl8169_private *tp)
4602 {
4603         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
4604                 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4605
4606         RTL_W8(tp, EarlyTxThres, NoEarlyTx);
4607
4608         tp->cp_cmd |= PCIMulRW;
4609
4610         if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4611             tp->mac_version == RTL_GIGA_MAC_VER_03) {
4612                 netif_dbg(tp, drv, tp->dev,
4613                           "Set MAC Reg C+CR Offset 0xe0. Bit 3 and Bit 14 MUST be 1\n");
4614                 tp->cp_cmd |= (1 << 14);
4615         }
4616
4617         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4618
4619         rtl8169_set_magic_reg(tp, tp->mac_version);
4620
4621         /*
4622          * Undocumented corner. Supposedly:
4623          * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
4624          */
4625         RTL_W16(tp, IntrMitigate, 0x0000);
4626
4627         RTL_W32(tp, RxMissed, 0);
4628 }
4629
4630 DECLARE_RTL_COND(rtl_csiar_cond)
4631 {
4632         return RTL_R32(tp, CSIAR) & CSIAR_FLAG;
4633 }
4634
4635 static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)
4636 {
4637         u32 func = PCI_FUNC(tp->pci_dev->devfn);
4638
4639         RTL_W32(tp, CSIDR, value);
4640         RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
4641                 CSIAR_BYTE_ENABLE | func << 16);
4642
4643         rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
4644 }
4645
4646 static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)
4647 {
4648         u32 func = PCI_FUNC(tp->pci_dev->devfn);
4649
4650         RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) | func << 16 |
4651                 CSIAR_BYTE_ENABLE);
4652
4653         return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
4654                 RTL_R32(tp, CSIDR) : ~0;
4655 }
4656
4657 static void rtl_csi_access_enable(struct rtl8169_private *tp, u8 val)
4658 {
4659         struct pci_dev *pdev = tp->pci_dev;
4660         u32 csi;
4661
4662         /* According to Realtek the value at config space address 0x070f
4663          * controls the L0s/L1 entrance latency. We try standard ECAM access
4664          * first and if it fails fall back to CSI.
4665          */
4666         if (pdev->cfg_size > 0x070f &&
4667             pci_write_config_byte(pdev, 0x070f, val) == PCIBIOS_SUCCESSFUL)
4668                 return;
4669
4670         netdev_notice_once(tp->dev,
4671                 "No native access to PCI extended config space, falling back to CSI\n");
4672         csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff;
4673         rtl_csi_write(tp, 0x070c, csi | val << 24);
4674 }
4675
4676 static void rtl_set_def_aspm_entry_latency(struct rtl8169_private *tp)
4677 {
4678         rtl_csi_access_enable(tp, 0x27);
4679 }
4680
4681 struct ephy_info {
4682         unsigned int offset;
4683         u16 mask;
4684         u16 bits;
4685 };
4686
4687 static void rtl_ephy_init(struct rtl8169_private *tp, const struct ephy_info *e,
4688                           int len)
4689 {
4690         u16 w;
4691
4692         while (len-- > 0) {
4693                 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits;
4694                 rtl_ephy_write(tp, e->offset, w);
4695                 e++;
4696         }
4697 }
4698
4699 static void rtl_disable_clock_request(struct rtl8169_private *tp)
4700 {
4701         pcie_capability_clear_word(tp->pci_dev, PCI_EXP_LNKCTL,
4702                                    PCI_EXP_LNKCTL_CLKREQ_EN);
4703 }
4704
4705 static void rtl_enable_clock_request(struct rtl8169_private *tp)
4706 {
4707         pcie_capability_set_word(tp->pci_dev, PCI_EXP_LNKCTL,
4708                                  PCI_EXP_LNKCTL_CLKREQ_EN);
4709 }
4710
4711 static void rtl_pcie_state_l2l3_enable(struct rtl8169_private *tp, bool enable)
4712 {
4713         u8 data;
4714
4715         data = RTL_R8(tp, Config3);
4716
4717         if (enable)
4718                 data |= Rdy_to_L23;
4719         else
4720                 data &= ~Rdy_to_L23;
4721
4722         RTL_W8(tp, Config3, data);
4723 }
4724
4725 static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable)
4726 {
4727         if (enable) {
4728                 RTL_W8(tp, Config5, RTL_R8(tp, Config5) | ASPM_en);
4729                 RTL_W8(tp, Config2, RTL_R8(tp, Config2) | ClkReqEn);
4730         } else {
4731                 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
4732                 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
4733         }
4734
4735         udelay(10);
4736 }
4737
4738 static void rtl_hw_start_8168bb(struct rtl8169_private *tp)
4739 {
4740         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4741
4742         tp->cp_cmd &= CPCMD_QUIRK_MASK;
4743         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4744
4745         if (tp->dev->mtu <= ETH_DATA_LEN) {
4746                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B |
4747                                          PCI_EXP_DEVCTL_NOSNOOP_EN);
4748         }
4749 }
4750
4751 static void rtl_hw_start_8168bef(struct rtl8169_private *tp)
4752 {
4753         rtl_hw_start_8168bb(tp);
4754
4755         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4756
4757         RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0));
4758 }
4759
4760 static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)
4761 {
4762         RTL_W8(tp, Config1, RTL_R8(tp, Config1) | Speed_down);
4763
4764         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4765
4766         if (tp->dev->mtu <= ETH_DATA_LEN)
4767                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4768
4769         rtl_disable_clock_request(tp);
4770
4771         tp->cp_cmd &= CPCMD_QUIRK_MASK;
4772         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4773 }
4774
4775 static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp)
4776 {
4777         static const struct ephy_info e_info_8168cp[] = {
4778                 { 0x01, 0,      0x0001 },
4779                 { 0x02, 0x0800, 0x1000 },
4780                 { 0x03, 0,      0x0042 },
4781                 { 0x06, 0x0080, 0x0000 },
4782                 { 0x07, 0,      0x2000 }
4783         };
4784
4785         rtl_set_def_aspm_entry_latency(tp);
4786
4787         rtl_ephy_init(tp, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
4788
4789         __rtl_hw_start_8168cp(tp);
4790 }
4791
4792 static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)
4793 {
4794         rtl_set_def_aspm_entry_latency(tp);
4795
4796         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4797
4798         if (tp->dev->mtu <= ETH_DATA_LEN)
4799                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4800
4801         tp->cp_cmd &= CPCMD_QUIRK_MASK;
4802         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4803 }
4804
4805 static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)
4806 {
4807         rtl_set_def_aspm_entry_latency(tp);
4808
4809         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4810
4811         /* Magic. */
4812         RTL_W8(tp, DBG_REG, 0x20);
4813
4814         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4815
4816         if (tp->dev->mtu <= ETH_DATA_LEN)
4817                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4818
4819         tp->cp_cmd &= CPCMD_QUIRK_MASK;
4820         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4821 }
4822
4823 static void rtl_hw_start_8168c_1(struct rtl8169_private *tp)
4824 {
4825         static const struct ephy_info e_info_8168c_1[] = {
4826                 { 0x02, 0x0800, 0x1000 },
4827                 { 0x03, 0,      0x0002 },
4828                 { 0x06, 0x0080, 0x0000 }
4829         };
4830
4831         rtl_set_def_aspm_entry_latency(tp);
4832
4833         RTL_W8(tp, DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
4834
4835         rtl_ephy_init(tp, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
4836
4837         __rtl_hw_start_8168cp(tp);
4838 }
4839
4840 static void rtl_hw_start_8168c_2(struct rtl8169_private *tp)
4841 {
4842         static const struct ephy_info e_info_8168c_2[] = {
4843                 { 0x01, 0,      0x0001 },
4844                 { 0x03, 0x0400, 0x0220 }
4845         };
4846
4847         rtl_set_def_aspm_entry_latency(tp);
4848
4849         rtl_ephy_init(tp, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
4850
4851         __rtl_hw_start_8168cp(tp);
4852 }
4853
4854 static void rtl_hw_start_8168c_3(struct rtl8169_private *tp)
4855 {
4856         rtl_hw_start_8168c_2(tp);
4857 }
4858
4859 static void rtl_hw_start_8168c_4(struct rtl8169_private *tp)
4860 {
4861         rtl_set_def_aspm_entry_latency(tp);
4862
4863         __rtl_hw_start_8168cp(tp);
4864 }
4865
4866 static void rtl_hw_start_8168d(struct rtl8169_private *tp)
4867 {
4868         rtl_set_def_aspm_entry_latency(tp);
4869
4870         rtl_disable_clock_request(tp);
4871
4872         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4873
4874         if (tp->dev->mtu <= ETH_DATA_LEN)
4875                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4876
4877         tp->cp_cmd &= CPCMD_QUIRK_MASK;
4878         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4879 }
4880
4881 static void rtl_hw_start_8168dp(struct rtl8169_private *tp)
4882 {
4883         rtl_set_def_aspm_entry_latency(tp);
4884
4885         if (tp->dev->mtu <= ETH_DATA_LEN)
4886                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4887
4888         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4889
4890         rtl_disable_clock_request(tp);
4891 }
4892
4893 static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
4894 {
4895         static const struct ephy_info e_info_8168d_4[] = {
4896                 { 0x0b, 0x0000, 0x0048 },
4897                 { 0x19, 0x0020, 0x0050 },
4898                 { 0x0c, 0x0100, 0x0020 }
4899         };
4900
4901         rtl_set_def_aspm_entry_latency(tp);
4902
4903         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4904
4905         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4906
4907         rtl_ephy_init(tp, e_info_8168d_4, ARRAY_SIZE(e_info_8168d_4));
4908
4909         rtl_enable_clock_request(tp);
4910 }
4911
4912 static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)
4913 {
4914         static const struct ephy_info e_info_8168e_1[] = {
4915                 { 0x00, 0x0200, 0x0100 },
4916                 { 0x00, 0x0000, 0x0004 },
4917                 { 0x06, 0x0002, 0x0001 },
4918                 { 0x06, 0x0000, 0x0030 },
4919                 { 0x07, 0x0000, 0x2000 },
4920                 { 0x00, 0x0000, 0x0020 },
4921                 { 0x03, 0x5800, 0x2000 },
4922                 { 0x03, 0x0000, 0x0001 },
4923                 { 0x01, 0x0800, 0x1000 },
4924                 { 0x07, 0x0000, 0x4000 },
4925                 { 0x1e, 0x0000, 0x2000 },
4926                 { 0x19, 0xffff, 0xfe6c },
4927                 { 0x0a, 0x0000, 0x0040 }
4928         };
4929
4930         rtl_set_def_aspm_entry_latency(tp);
4931
4932         rtl_ephy_init(tp, e_info_8168e_1, ARRAY_SIZE(e_info_8168e_1));
4933
4934         if (tp->dev->mtu <= ETH_DATA_LEN)
4935                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4936
4937         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4938
4939         rtl_disable_clock_request(tp);
4940
4941         /* Reset tx FIFO pointer */
4942         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | TXPLA_RST);
4943         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~TXPLA_RST);
4944
4945         RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
4946 }
4947
4948 static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
4949 {
4950         static const struct ephy_info e_info_8168e_2[] = {
4951                 { 0x09, 0x0000, 0x0080 },
4952                 { 0x19, 0x0000, 0x0224 }
4953         };
4954
4955         rtl_set_def_aspm_entry_latency(tp);
4956
4957         rtl_ephy_init(tp, e_info_8168e_2, ARRAY_SIZE(e_info_8168e_2));
4958
4959         if (tp->dev->mtu <= ETH_DATA_LEN)
4960                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4961
4962         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4963         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4964         rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
4965         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
4966         rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
4967         rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060, ERIAR_EXGMAC);
4968         rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
4969         rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
4970
4971         RTL_W8(tp, MaxTxPacketSize, EarlySize);
4972
4973         rtl_disable_clock_request(tp);
4974
4975         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
4976
4977         /* Adjust EEE LED frequency */
4978         RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
4979
4980         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
4981         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
4982         RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
4983
4984         rtl_hw_aspm_clkreq_enable(tp, true);
4985 }
4986
4987 static void rtl_hw_start_8168f(struct rtl8169_private *tp)
4988 {
4989         rtl_set_def_aspm_entry_latency(tp);
4990
4991         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4992
4993         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4994         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4995         rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
4996         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
4997         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
4998         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
4999         rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5000         rtl_w0w1_eri(tp, 0x1d0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5001         rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
5002         rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060, ERIAR_EXGMAC);
5003
5004         RTL_W8(tp, MaxTxPacketSize, EarlySize);
5005
5006         rtl_disable_clock_request(tp);
5007
5008         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
5009         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
5010         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
5011         RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
5012 }
5013
5014 static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
5015 {
5016         static const struct ephy_info e_info_8168f_1[] = {
5017                 { 0x06, 0x00c0, 0x0020 },
5018                 { 0x08, 0x0001, 0x0002 },
5019                 { 0x09, 0x0000, 0x0080 },
5020                 { 0x19, 0x0000, 0x0224 }
5021         };
5022
5023         rtl_hw_start_8168f(tp);
5024
5025         rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
5026
5027         rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
5028
5029         /* Adjust EEE LED frequency */
5030         RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
5031 }
5032
5033 static void rtl_hw_start_8411(struct rtl8169_private *tp)
5034 {
5035         static const struct ephy_info e_info_8168f_1[] = {
5036                 { 0x06, 0x00c0, 0x0020 },
5037                 { 0x0f, 0xffff, 0x5200 },
5038                 { 0x1e, 0x0000, 0x4000 },
5039                 { 0x19, 0x0000, 0x0224 }
5040         };
5041
5042         rtl_hw_start_8168f(tp);
5043         rtl_pcie_state_l2l3_enable(tp, false);
5044
5045         rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
5046
5047         rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0x0000, ERIAR_EXGMAC);
5048 }
5049
5050 static void rtl_hw_start_8168g(struct rtl8169_private *tp)
5051 {
5052         rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x080002, ERIAR_EXGMAC);
5053         rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
5054         rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
5055         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5056
5057         rtl_set_def_aspm_entry_latency(tp);
5058
5059         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5060
5061         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5062         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5063         rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f, ERIAR_EXGMAC);
5064
5065         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
5066         RTL_W8(tp, MaxTxPacketSize, EarlySize);
5067
5068         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5069         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5070
5071         /* Adjust EEE LED frequency */
5072         RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
5073
5074         rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06, ERIAR_EXGMAC);
5075         rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC);
5076
5077         rtl_pcie_state_l2l3_enable(tp, false);
5078 }
5079
5080 static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
5081 {
5082         static const struct ephy_info e_info_8168g_1[] = {
5083                 { 0x00, 0x0000, 0x0008 },
5084                 { 0x0c, 0x37d0, 0x0820 },
5085                 { 0x1e, 0x0000, 0x0001 },
5086                 { 0x19, 0x8000, 0x0000 }
5087         };
5088
5089         rtl_hw_start_8168g(tp);
5090
5091         /* disable aspm and clock request before access ephy */
5092         rtl_hw_aspm_clkreq_enable(tp, false);
5093         rtl_ephy_init(tp, e_info_8168g_1, ARRAY_SIZE(e_info_8168g_1));
5094         rtl_hw_aspm_clkreq_enable(tp, true);
5095 }
5096
5097 static void rtl_hw_start_8168g_2(struct rtl8169_private *tp)
5098 {
5099         static const struct ephy_info e_info_8168g_2[] = {
5100                 { 0x00, 0x0000, 0x0008 },
5101                 { 0x0c, 0x3df0, 0x0200 },
5102                 { 0x19, 0xffff, 0xfc00 },
5103                 { 0x1e, 0xffff, 0x20eb }
5104         };
5105
5106         rtl_hw_start_8168g(tp);
5107
5108         /* disable aspm and clock request before access ephy */
5109         RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
5110         RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
5111         rtl_ephy_init(tp, e_info_8168g_2, ARRAY_SIZE(e_info_8168g_2));
5112 }
5113
5114 static void rtl_hw_start_8411_2(struct rtl8169_private *tp)
5115 {
5116         static const struct ephy_info e_info_8411_2[] = {
5117                 { 0x00, 0x0000, 0x0008 },
5118                 { 0x0c, 0x3df0, 0x0200 },
5119                 { 0x0f, 0xffff, 0x5200 },
5120                 { 0x19, 0x0020, 0x0000 },
5121                 { 0x1e, 0x0000, 0x2000 }
5122         };
5123
5124         rtl_hw_start_8168g(tp);
5125
5126         /* disable aspm and clock request before access ephy */
5127         rtl_hw_aspm_clkreq_enable(tp, false);
5128         rtl_ephy_init(tp, e_info_8411_2, ARRAY_SIZE(e_info_8411_2));
5129         rtl_hw_aspm_clkreq_enable(tp, true);
5130 }
5131
5132 static void rtl_hw_start_8168h_1(struct rtl8169_private *tp)
5133 {
5134         int rg_saw_cnt;
5135         u32 data;
5136         static const struct ephy_info e_info_8168h_1[] = {
5137                 { 0x1e, 0x0800, 0x0001 },
5138                 { 0x1d, 0x0000, 0x0800 },
5139                 { 0x05, 0xffff, 0x2089 },
5140                 { 0x06, 0xffff, 0x5881 },
5141                 { 0x04, 0xffff, 0x154a },
5142                 { 0x01, 0xffff, 0x068b }
5143         };
5144
5145         /* disable aspm and clock request before access ephy */
5146         rtl_hw_aspm_clkreq_enable(tp, false);
5147         rtl_ephy_init(tp, e_info_8168h_1, ARRAY_SIZE(e_info_8168h_1));
5148
5149         rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x00080002, ERIAR_EXGMAC);
5150         rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
5151         rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
5152         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5153
5154         rtl_set_def_aspm_entry_latency(tp);
5155
5156         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5157
5158         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5159         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5160
5161         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_1111, 0x0010, 0x00, ERIAR_EXGMAC);
5162
5163         rtl_w0w1_eri(tp, 0xd4, ERIAR_MASK_1111, 0x1f00, 0x00, ERIAR_EXGMAC);
5164
5165         rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87, ERIAR_EXGMAC);
5166
5167         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
5168         RTL_W8(tp, MaxTxPacketSize, EarlySize);
5169
5170         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5171         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5172
5173         /* Adjust EEE LED frequency */
5174         RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
5175
5176         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5177         RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
5178
5179         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
5180
5181         rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC);
5182
5183         rtl_pcie_state_l2l3_enable(tp, false);
5184
5185         rtl_writephy(tp, 0x1f, 0x0c42);
5186         rg_saw_cnt = (rtl_readphy(tp, 0x13) & 0x3fff);
5187         rtl_writephy(tp, 0x1f, 0x0000);
5188         if (rg_saw_cnt > 0) {
5189                 u16 sw_cnt_1ms_ini;
5190
5191                 sw_cnt_1ms_ini = 16000000/rg_saw_cnt;
5192                 sw_cnt_1ms_ini &= 0x0fff;
5193                 data = r8168_mac_ocp_read(tp, 0xd412);
5194                 data &= ~0x0fff;
5195                 data |= sw_cnt_1ms_ini;
5196                 r8168_mac_ocp_write(tp, 0xd412, data);
5197         }
5198
5199         data = r8168_mac_ocp_read(tp, 0xe056);
5200         data &= ~0xf0;
5201         data |= 0x70;
5202         r8168_mac_ocp_write(tp, 0xe056, data);
5203
5204         data = r8168_mac_ocp_read(tp, 0xe052);
5205         data &= ~0x6000;
5206         data |= 0x8008;
5207         r8168_mac_ocp_write(tp, 0xe052, data);
5208
5209         data = r8168_mac_ocp_read(tp, 0xe0d6);
5210         data &= ~0x01ff;
5211         data |= 0x017f;
5212         r8168_mac_ocp_write(tp, 0xe0d6, data);
5213
5214         data = r8168_mac_ocp_read(tp, 0xd420);
5215         data &= ~0x0fff;
5216         data |= 0x047f;
5217         r8168_mac_ocp_write(tp, 0xd420, data);
5218
5219         r8168_mac_ocp_write(tp, 0xe63e, 0x0001);
5220         r8168_mac_ocp_write(tp, 0xe63e, 0x0000);
5221         r8168_mac_ocp_write(tp, 0xc094, 0x0000);
5222         r8168_mac_ocp_write(tp, 0xc09e, 0x0000);
5223
5224         rtl_hw_aspm_clkreq_enable(tp, true);
5225 }
5226
5227 static void rtl_hw_start_8168ep(struct rtl8169_private *tp)
5228 {
5229         rtl8168ep_stop_cmac(tp);
5230
5231         rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x00080002, ERIAR_EXGMAC);
5232         rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x2f, ERIAR_EXGMAC);
5233         rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x5f, ERIAR_EXGMAC);
5234         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5235
5236         rtl_set_def_aspm_entry_latency(tp);
5237
5238         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5239
5240         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5241         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5242
5243         rtl_w0w1_eri(tp, 0xd4, ERIAR_MASK_1111, 0x1f80, 0x00, ERIAR_EXGMAC);
5244
5245         rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87, ERIAR_EXGMAC);
5246
5247         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
5248         RTL_W8(tp, MaxTxPacketSize, EarlySize);
5249
5250         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5251         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5252
5253         /* Adjust EEE LED frequency */
5254         RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
5255
5256         rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06, ERIAR_EXGMAC);
5257
5258         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
5259
5260         rtl_pcie_state_l2l3_enable(tp, false);
5261 }
5262
5263 static void rtl_hw_start_8168ep_1(struct rtl8169_private *tp)
5264 {
5265         static const struct ephy_info e_info_8168ep_1[] = {
5266                 { 0x00, 0xffff, 0x10ab },
5267                 { 0x06, 0xffff, 0xf030 },
5268                 { 0x08, 0xffff, 0x2006 },
5269                 { 0x0d, 0xffff, 0x1666 },
5270                 { 0x0c, 0x3ff0, 0x0000 }
5271         };
5272
5273         /* disable aspm and clock request before access ephy */
5274         rtl_hw_aspm_clkreq_enable(tp, false);
5275         rtl_ephy_init(tp, e_info_8168ep_1, ARRAY_SIZE(e_info_8168ep_1));
5276
5277         rtl_hw_start_8168ep(tp);
5278
5279         rtl_hw_aspm_clkreq_enable(tp, true);
5280 }
5281
5282 static void rtl_hw_start_8168ep_2(struct rtl8169_private *tp)
5283 {
5284         static const struct ephy_info e_info_8168ep_2[] = {
5285                 { 0x00, 0xffff, 0x10a3 },
5286                 { 0x19, 0xffff, 0xfc00 },
5287                 { 0x1e, 0xffff, 0x20ea }
5288         };
5289
5290         /* disable aspm and clock request before access ephy */
5291         rtl_hw_aspm_clkreq_enable(tp, false);
5292         rtl_ephy_init(tp, e_info_8168ep_2, ARRAY_SIZE(e_info_8168ep_2));
5293
5294         rtl_hw_start_8168ep(tp);
5295
5296         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5297         RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
5298
5299         rtl_hw_aspm_clkreq_enable(tp, true);
5300 }
5301
5302 static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp)
5303 {
5304         u32 data;
5305         static const struct ephy_info e_info_8168ep_3[] = {
5306                 { 0x00, 0xffff, 0x10a3 },
5307                 { 0x19, 0xffff, 0x7c00 },
5308                 { 0x1e, 0xffff, 0x20eb },
5309                 { 0x0d, 0xffff, 0x1666 }
5310         };
5311
5312         /* disable aspm and clock request before access ephy */
5313         rtl_hw_aspm_clkreq_enable(tp, false);
5314         rtl_ephy_init(tp, e_info_8168ep_3, ARRAY_SIZE(e_info_8168ep_3));
5315
5316         rtl_hw_start_8168ep(tp);
5317
5318         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5319         RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
5320
5321         data = r8168_mac_ocp_read(tp, 0xd3e2);
5322         data &= 0xf000;
5323         data |= 0x0271;
5324         r8168_mac_ocp_write(tp, 0xd3e2, data);
5325
5326         data = r8168_mac_ocp_read(tp, 0xd3e4);
5327         data &= 0xff00;
5328         r8168_mac_ocp_write(tp, 0xd3e4, data);
5329
5330         data = r8168_mac_ocp_read(tp, 0xe860);
5331         data |= 0x0080;
5332         r8168_mac_ocp_write(tp, 0xe860, data);
5333
5334         rtl_hw_aspm_clkreq_enable(tp, true);
5335 }
5336
5337 static void rtl_hw_start_8168(struct rtl8169_private *tp)
5338 {
5339         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
5340
5341         tp->cp_cmd &= ~INTT_MASK;
5342         tp->cp_cmd |= PktCntrDisable | INTT_1;
5343         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
5344
5345         RTL_W16(tp, IntrMitigate, 0x5151);
5346
5347         /* Work around for RxFIFO overflow. */
5348         if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
5349                 tp->irq_mask |= RxFIFOOver;
5350                 tp->irq_mask &= ~RxOverflow;
5351         }
5352
5353         switch (tp->mac_version) {
5354         case RTL_GIGA_MAC_VER_11:
5355                 rtl_hw_start_8168bb(tp);
5356                 break;
5357
5358         case RTL_GIGA_MAC_VER_12:
5359         case RTL_GIGA_MAC_VER_17:
5360                 rtl_hw_start_8168bef(tp);
5361                 break;
5362
5363         case RTL_GIGA_MAC_VER_18:
5364                 rtl_hw_start_8168cp_1(tp);
5365                 break;
5366
5367         case RTL_GIGA_MAC_VER_19:
5368                 rtl_hw_start_8168c_1(tp);
5369                 break;
5370
5371         case RTL_GIGA_MAC_VER_20:
5372                 rtl_hw_start_8168c_2(tp);
5373                 break;
5374
5375         case RTL_GIGA_MAC_VER_21:
5376                 rtl_hw_start_8168c_3(tp);
5377                 break;
5378
5379         case RTL_GIGA_MAC_VER_22:
5380                 rtl_hw_start_8168c_4(tp);
5381                 break;
5382
5383         case RTL_GIGA_MAC_VER_23:
5384                 rtl_hw_start_8168cp_2(tp);
5385                 break;
5386
5387         case RTL_GIGA_MAC_VER_24:
5388                 rtl_hw_start_8168cp_3(tp);
5389                 break;
5390
5391         case RTL_GIGA_MAC_VER_25:
5392         case RTL_GIGA_MAC_VER_26:
5393         case RTL_GIGA_MAC_VER_27:
5394                 rtl_hw_start_8168d(tp);
5395                 break;
5396
5397         case RTL_GIGA_MAC_VER_28:
5398                 rtl_hw_start_8168d_4(tp);
5399                 break;
5400
5401         case RTL_GIGA_MAC_VER_31:
5402                 rtl_hw_start_8168dp(tp);
5403                 break;
5404
5405         case RTL_GIGA_MAC_VER_32:
5406         case RTL_GIGA_MAC_VER_33:
5407                 rtl_hw_start_8168e_1(tp);
5408                 break;
5409         case RTL_GIGA_MAC_VER_34:
5410                 rtl_hw_start_8168e_2(tp);
5411                 break;
5412
5413         case RTL_GIGA_MAC_VER_35:
5414         case RTL_GIGA_MAC_VER_36:
5415                 rtl_hw_start_8168f_1(tp);
5416                 break;
5417
5418         case RTL_GIGA_MAC_VER_38:
5419                 rtl_hw_start_8411(tp);
5420                 break;
5421
5422         case RTL_GIGA_MAC_VER_40:
5423         case RTL_GIGA_MAC_VER_41:
5424                 rtl_hw_start_8168g_1(tp);
5425                 break;
5426         case RTL_GIGA_MAC_VER_42:
5427                 rtl_hw_start_8168g_2(tp);
5428                 break;
5429
5430         case RTL_GIGA_MAC_VER_44:
5431                 rtl_hw_start_8411_2(tp);
5432                 break;
5433
5434         case RTL_GIGA_MAC_VER_45:
5435         case RTL_GIGA_MAC_VER_46:
5436                 rtl_hw_start_8168h_1(tp);
5437                 break;
5438
5439         case RTL_GIGA_MAC_VER_49:
5440                 rtl_hw_start_8168ep_1(tp);
5441                 break;
5442
5443         case RTL_GIGA_MAC_VER_50:
5444                 rtl_hw_start_8168ep_2(tp);
5445                 break;
5446
5447         case RTL_GIGA_MAC_VER_51:
5448                 rtl_hw_start_8168ep_3(tp);
5449                 break;
5450
5451         default:
5452                 netif_err(tp, drv, tp->dev,
5453                           "unknown chipset (mac_version = %d)\n",
5454                           tp->mac_version);
5455                 break;
5456         }
5457 }
5458
5459 static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)
5460 {
5461         static const struct ephy_info e_info_8102e_1[] = {
5462                 { 0x01, 0, 0x6e65 },
5463                 { 0x02, 0, 0x091f },
5464                 { 0x03, 0, 0xc2f9 },
5465                 { 0x06, 0, 0xafb5 },
5466                 { 0x07, 0, 0x0e00 },
5467                 { 0x19, 0, 0xec80 },
5468                 { 0x01, 0, 0x2e65 },
5469                 { 0x01, 0, 0x6e65 }
5470         };
5471         u8 cfg1;
5472
5473         rtl_set_def_aspm_entry_latency(tp);
5474
5475         RTL_W8(tp, DBG_REG, FIX_NAK_1);
5476
5477         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5478
5479         RTL_W8(tp, Config1,
5480                LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
5481         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
5482
5483         cfg1 = RTL_R8(tp, Config1);
5484         if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
5485                 RTL_W8(tp, Config1, cfg1 & ~LEDS0);
5486
5487         rtl_ephy_init(tp, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
5488 }
5489
5490 static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)
5491 {
5492         rtl_set_def_aspm_entry_latency(tp);
5493
5494         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5495
5496         RTL_W8(tp, Config1, MEMMAP | IOMAP | VPD | PMEnable);
5497         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
5498 }
5499
5500 static void rtl_hw_start_8102e_3(struct rtl8169_private *tp)
5501 {
5502         rtl_hw_start_8102e_2(tp);
5503
5504         rtl_ephy_write(tp, 0x03, 0xc2f9);
5505 }
5506
5507 static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)
5508 {
5509         static const struct ephy_info e_info_8105e_1[] = {
5510                 { 0x07, 0, 0x4000 },
5511                 { 0x19, 0, 0x0200 },
5512                 { 0x19, 0, 0x0020 },
5513                 { 0x1e, 0, 0x2000 },
5514                 { 0x03, 0, 0x0001 },
5515                 { 0x19, 0, 0x0100 },
5516                 { 0x19, 0, 0x0004 },
5517                 { 0x0a, 0, 0x0020 }
5518         };
5519
5520         /* Force LAN exit from ASPM if Rx/Tx are not idle */
5521         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
5522
5523         /* Disable Early Tally Counter */
5524         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) & ~0x010000);
5525
5526         RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
5527         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
5528
5529         rtl_ephy_init(tp, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
5530
5531         rtl_pcie_state_l2l3_enable(tp, false);
5532 }
5533
5534 static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)
5535 {
5536         rtl_hw_start_8105e_1(tp);
5537         rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000);
5538 }
5539
5540 static void rtl_hw_start_8402(struct rtl8169_private *tp)
5541 {
5542         static const struct ephy_info e_info_8402[] = {
5543                 { 0x19, 0xffff, 0xff64 },
5544                 { 0x1e, 0, 0x4000 }
5545         };
5546
5547         rtl_set_def_aspm_entry_latency(tp);
5548
5549         /* Force LAN exit from ASPM if Rx/Tx are not idle */
5550         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
5551
5552         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
5553
5554         rtl_ephy_init(tp, e_info_8402, ARRAY_SIZE(e_info_8402));
5555
5556         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5557
5558         rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00000002, ERIAR_EXGMAC);
5559         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00000006, ERIAR_EXGMAC);
5560         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5561         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5562         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5563         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5564         rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0e00, 0xff00, ERIAR_EXGMAC);
5565
5566         rtl_pcie_state_l2l3_enable(tp, false);
5567 }
5568
5569 static void rtl_hw_start_8106(struct rtl8169_private *tp)
5570 {
5571         rtl_hw_aspm_clkreq_enable(tp, false);
5572
5573         /* Force LAN exit from ASPM if Rx/Tx are not idle */
5574         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
5575
5576         RTL_W32(tp, MISC, (RTL_R32(tp, MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);
5577         RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
5578         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5579
5580         rtl_pcie_state_l2l3_enable(tp, false);
5581         rtl_hw_aspm_clkreq_enable(tp, true);
5582 }
5583
5584 static void rtl_hw_start_8101(struct rtl8169_private *tp)
5585 {
5586         if (tp->mac_version >= RTL_GIGA_MAC_VER_30)
5587                 tp->irq_mask &= ~RxFIFOOver;
5588
5589         if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
5590             tp->mac_version == RTL_GIGA_MAC_VER_16)
5591                 pcie_capability_set_word(tp->pci_dev, PCI_EXP_DEVCTL,
5592                                          PCI_EXP_DEVCTL_NOSNOOP_EN);
5593
5594         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
5595
5596         tp->cp_cmd &= CPCMD_QUIRK_MASK;
5597         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
5598
5599         switch (tp->mac_version) {
5600         case RTL_GIGA_MAC_VER_07:
5601                 rtl_hw_start_8102e_1(tp);
5602                 break;
5603
5604         case RTL_GIGA_MAC_VER_08:
5605                 rtl_hw_start_8102e_3(tp);
5606                 break;
5607
5608         case RTL_GIGA_MAC_VER_09:
5609                 rtl_hw_start_8102e_2(tp);
5610                 break;
5611
5612         case RTL_GIGA_MAC_VER_29:
5613                 rtl_hw_start_8105e_1(tp);
5614                 break;
5615         case RTL_GIGA_MAC_VER_30:
5616                 rtl_hw_start_8105e_2(tp);
5617                 break;
5618
5619         case RTL_GIGA_MAC_VER_37:
5620                 rtl_hw_start_8402(tp);
5621                 break;
5622
5623         case RTL_GIGA_MAC_VER_39:
5624                 rtl_hw_start_8106(tp);
5625                 break;
5626         case RTL_GIGA_MAC_VER_43:
5627                 rtl_hw_start_8168g_2(tp);
5628                 break;
5629         case RTL_GIGA_MAC_VER_47:
5630         case RTL_GIGA_MAC_VER_48:
5631                 rtl_hw_start_8168h_1(tp);
5632                 break;
5633         }
5634
5635         RTL_W16(tp, IntrMitigate, 0x0000);
5636 }
5637
5638 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
5639 {
5640         struct rtl8169_private *tp = netdev_priv(dev);
5641
5642         if (new_mtu > ETH_DATA_LEN)
5643                 rtl_hw_jumbo_enable(tp);
5644         else
5645                 rtl_hw_jumbo_disable(tp);
5646
5647         dev->mtu = new_mtu;
5648         netdev_update_features(dev);
5649
5650         return 0;
5651 }
5652
5653 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
5654 {
5655         desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
5656         desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
5657 }
5658
5659 static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
5660                                      void **data_buff, struct RxDesc *desc)
5661 {
5662         dma_unmap_single(tp_to_dev(tp), le64_to_cpu(desc->addr),
5663                          R8169_RX_BUF_SIZE, DMA_FROM_DEVICE);
5664
5665         kfree(*data_buff);
5666         *data_buff = NULL;
5667         rtl8169_make_unusable_by_asic(desc);
5668 }
5669
5670 static inline void rtl8169_mark_to_asic(struct RxDesc *desc)
5671 {
5672         u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
5673
5674         /* Force memory writes to complete before releasing descriptor */
5675         dma_wmb();
5676
5677         desc->opts1 = cpu_to_le32(DescOwn | eor | R8169_RX_BUF_SIZE);
5678 }
5679
5680 static inline void *rtl8169_align(void *data)
5681 {
5682         return (void *)ALIGN((long)data, 16);
5683 }
5684
5685 static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
5686                                              struct RxDesc *desc)
5687 {
5688         void *data;
5689         dma_addr_t mapping;
5690         struct device *d = tp_to_dev(tp);
5691         int node = dev_to_node(d);
5692
5693         data = kmalloc_node(R8169_RX_BUF_SIZE, GFP_KERNEL, node);
5694         if (!data)
5695                 return NULL;
5696
5697         if (rtl8169_align(data) != data) {
5698                 kfree(data);
5699                 data = kmalloc_node(R8169_RX_BUF_SIZE + 15, GFP_KERNEL, node);
5700                 if (!data)
5701                         return NULL;
5702         }
5703
5704         mapping = dma_map_single(d, rtl8169_align(data), R8169_RX_BUF_SIZE,
5705                                  DMA_FROM_DEVICE);
5706         if (unlikely(dma_mapping_error(d, mapping))) {
5707                 if (net_ratelimit())
5708                         netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
5709                 goto err_out;
5710         }
5711
5712         desc->addr = cpu_to_le64(mapping);
5713         rtl8169_mark_to_asic(desc);
5714         return data;
5715
5716 err_out:
5717         kfree(data);
5718         return NULL;
5719 }
5720
5721 static void rtl8169_rx_clear(struct rtl8169_private *tp)
5722 {
5723         unsigned int i;
5724
5725         for (i = 0; i < NUM_RX_DESC; i++) {
5726                 if (tp->Rx_databuff[i]) {
5727                         rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
5728                                             tp->RxDescArray + i);
5729                 }
5730         }
5731 }
5732
5733 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
5734 {
5735         desc->opts1 |= cpu_to_le32(RingEnd);
5736 }
5737
5738 static int rtl8169_rx_fill(struct rtl8169_private *tp)
5739 {
5740         unsigned int i;
5741
5742         for (i = 0; i < NUM_RX_DESC; i++) {
5743                 void *data;
5744
5745                 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
5746                 if (!data) {
5747                         rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
5748                         goto err_out;
5749                 }
5750                 tp->Rx_databuff[i] = data;
5751         }
5752
5753         rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
5754         return 0;
5755
5756 err_out:
5757         rtl8169_rx_clear(tp);
5758         return -ENOMEM;
5759 }
5760
5761 static int rtl8169_init_ring(struct rtl8169_private *tp)
5762 {
5763         rtl8169_init_ring_indexes(tp);
5764
5765         memset(tp->tx_skb, 0, sizeof(tp->tx_skb));
5766         memset(tp->Rx_databuff, 0, sizeof(tp->Rx_databuff));
5767
5768         return rtl8169_rx_fill(tp);
5769 }
5770
5771 static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
5772                                  struct TxDesc *desc)
5773 {
5774         unsigned int len = tx_skb->len;
5775
5776         dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
5777
5778         desc->opts1 = 0x00;
5779         desc->opts2 = 0x00;
5780         desc->addr = 0x00;
5781         tx_skb->len = 0;
5782 }
5783
5784 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
5785                                    unsigned int n)
5786 {
5787         unsigned int i;
5788
5789         for (i = 0; i < n; i++) {
5790                 unsigned int entry = (start + i) % NUM_TX_DESC;
5791                 struct ring_info *tx_skb = tp->tx_skb + entry;
5792                 unsigned int len = tx_skb->len;
5793
5794                 if (len) {
5795                         struct sk_buff *skb = tx_skb->skb;
5796
5797                         rtl8169_unmap_tx_skb(tp_to_dev(tp), tx_skb,
5798                                              tp->TxDescArray + entry);
5799                         if (skb) {
5800                                 dev_consume_skb_any(skb);
5801                                 tx_skb->skb = NULL;
5802                         }
5803                 }
5804         }
5805 }
5806
5807 static void rtl8169_tx_clear(struct rtl8169_private *tp)
5808 {
5809         rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
5810         tp->cur_tx = tp->dirty_tx = 0;
5811         netdev_reset_queue(tp->dev);
5812 }
5813
5814 static void rtl_reset_work(struct rtl8169_private *tp)
5815 {
5816         struct net_device *dev = tp->dev;
5817         int i;
5818
5819         napi_disable(&tp->napi);
5820         netif_stop_queue(dev);
5821         synchronize_sched();
5822
5823         rtl8169_hw_reset(tp);
5824
5825         for (i = 0; i < NUM_RX_DESC; i++)
5826                 rtl8169_mark_to_asic(tp->RxDescArray + i);
5827
5828         rtl8169_tx_clear(tp);
5829         rtl8169_init_ring_indexes(tp);
5830
5831         napi_enable(&tp->napi);
5832         rtl_hw_start(tp);
5833         netif_wake_queue(dev);
5834 }
5835
5836 static void rtl8169_tx_timeout(struct net_device *dev)
5837 {
5838         struct rtl8169_private *tp = netdev_priv(dev);
5839
5840         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
5841 }
5842
5843 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
5844                               u32 *opts)
5845 {
5846         struct skb_shared_info *info = skb_shinfo(skb);
5847         unsigned int cur_frag, entry;
5848         struct TxDesc *uninitialized_var(txd);
5849         struct device *d = tp_to_dev(tp);
5850
5851         entry = tp->cur_tx;
5852         for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
5853                 const skb_frag_t *frag = info->frags + cur_frag;
5854                 dma_addr_t mapping;
5855                 u32 status, len;
5856                 void *addr;
5857
5858                 entry = (entry + 1) % NUM_TX_DESC;
5859
5860                 txd = tp->TxDescArray + entry;
5861                 len = skb_frag_size(frag);
5862                 addr = skb_frag_address(frag);
5863                 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
5864                 if (unlikely(dma_mapping_error(d, mapping))) {
5865                         if (net_ratelimit())
5866                                 netif_err(tp, drv, tp->dev,
5867                                           "Failed to map TX fragments DMA!\n");
5868                         goto err_out;
5869                 }
5870
5871                 status = opts[0] | len;
5872                 if (entry == NUM_TX_DESC - 1)
5873                         status |= RingEnd;
5874
5875                 txd->opts1 = cpu_to_le32(status);
5876                 txd->opts2 = cpu_to_le32(opts[1]);
5877                 txd->addr = cpu_to_le64(mapping);
5878
5879                 tp->tx_skb[entry].len = len;
5880         }
5881
5882         if (cur_frag) {
5883                 tp->tx_skb[entry].skb = skb;
5884                 txd->opts1 |= cpu_to_le32(LastFrag);
5885         }
5886
5887         return cur_frag;
5888
5889 err_out:
5890         rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
5891         return -EIO;
5892 }
5893
5894 static bool rtl_test_hw_pad_bug(struct rtl8169_private *tp, struct sk_buff *skb)
5895 {
5896         return skb->len < ETH_ZLEN && tp->mac_version == RTL_GIGA_MAC_VER_34;
5897 }
5898
5899 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
5900                                       struct net_device *dev);
5901 /* r8169_csum_workaround()
5902  * The hw limites the value the transport offset. When the offset is out of the
5903  * range, calculate the checksum by sw.
5904  */
5905 static void r8169_csum_workaround(struct rtl8169_private *tp,
5906                                   struct sk_buff *skb)
5907 {
5908         if (skb_shinfo(skb)->gso_size) {
5909                 netdev_features_t features = tp->dev->features;
5910                 struct sk_buff *segs, *nskb;
5911
5912                 features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
5913                 segs = skb_gso_segment(skb, features);
5914                 if (IS_ERR(segs) || !segs)
5915                         goto drop;
5916
5917                 do {
5918                         nskb = segs;
5919                         segs = segs->next;
5920                         nskb->next = NULL;
5921                         rtl8169_start_xmit(nskb, tp->dev);
5922                 } while (segs);
5923
5924                 dev_consume_skb_any(skb);
5925         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5926                 if (skb_checksum_help(skb) < 0)
5927                         goto drop;
5928
5929                 rtl8169_start_xmit(skb, tp->dev);
5930         } else {
5931                 struct net_device_stats *stats;
5932
5933 drop:
5934                 stats = &tp->dev->stats;
5935                 stats->tx_dropped++;
5936                 dev_kfree_skb_any(skb);
5937         }
5938 }
5939
5940 /* msdn_giant_send_check()
5941  * According to the document of microsoft, the TCP Pseudo Header excludes the
5942  * packet length for IPv6 TCP large packets.
5943  */
5944 static int msdn_giant_send_check(struct sk_buff *skb)
5945 {
5946         const struct ipv6hdr *ipv6h;
5947         struct tcphdr *th;
5948         int ret;
5949
5950         ret = skb_cow_head(skb, 0);
5951         if (ret)
5952                 return ret;
5953
5954         ipv6h = ipv6_hdr(skb);
5955         th = tcp_hdr(skb);
5956
5957         th->check = 0;
5958         th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0);
5959
5960         return ret;
5961 }
5962
5963 static bool rtl8169_tso_csum_v1(struct rtl8169_private *tp,
5964                                 struct sk_buff *skb, u32 *opts)
5965 {
5966         u32 mss = skb_shinfo(skb)->gso_size;
5967
5968         if (mss) {
5969                 opts[0] |= TD_LSO;
5970                 opts[0] |= min(mss, TD_MSS_MAX) << TD0_MSS_SHIFT;
5971         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5972                 const struct iphdr *ip = ip_hdr(skb);
5973
5974                 if (ip->protocol == IPPROTO_TCP)
5975                         opts[0] |= TD0_IP_CS | TD0_TCP_CS;
5976                 else if (ip->protocol == IPPROTO_UDP)
5977                         opts[0] |= TD0_IP_CS | TD0_UDP_CS;
5978                 else
5979                         WARN_ON_ONCE(1);
5980         }
5981
5982         return true;
5983 }
5984
5985 static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp,
5986                                 struct sk_buff *skb, u32 *opts)
5987 {
5988         u32 transport_offset = (u32)skb_transport_offset(skb);
5989         u32 mss = skb_shinfo(skb)->gso_size;
5990
5991         if (mss) {
5992                 if (transport_offset > GTTCPHO_MAX) {
5993                         netif_warn(tp, tx_err, tp->dev,
5994                                    "Invalid transport offset 0x%x for TSO\n",
5995                                    transport_offset);
5996                         return false;
5997                 }
5998
5999                 switch (vlan_get_protocol(skb)) {
6000                 case htons(ETH_P_IP):
6001                         opts[0] |= TD1_GTSENV4;
6002                         break;
6003
6004                 case htons(ETH_P_IPV6):
6005                         if (msdn_giant_send_check(skb))
6006                                 return false;
6007
6008                         opts[0] |= TD1_GTSENV6;
6009                         break;
6010
6011                 default:
6012                         WARN_ON_ONCE(1);
6013                         break;
6014                 }
6015
6016                 opts[0] |= transport_offset << GTTCPHO_SHIFT;
6017                 opts[1] |= min(mss, TD_MSS_MAX) << TD1_MSS_SHIFT;
6018         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
6019                 u8 ip_protocol;
6020
6021                 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
6022                         return !(skb_checksum_help(skb) || eth_skb_pad(skb));
6023
6024                 if (transport_offset > TCPHO_MAX) {
6025                         netif_warn(tp, tx_err, tp->dev,
6026                                    "Invalid transport offset 0x%x\n",
6027                                    transport_offset);
6028                         return false;
6029                 }
6030
6031                 switch (vlan_get_protocol(skb)) {
6032                 case htons(ETH_P_IP):
6033                         opts[1] |= TD1_IPv4_CS;
6034                         ip_protocol = ip_hdr(skb)->protocol;
6035                         break;
6036
6037                 case htons(ETH_P_IPV6):
6038                         opts[1] |= TD1_IPv6_CS;
6039                         ip_protocol = ipv6_hdr(skb)->nexthdr;
6040                         break;
6041
6042                 default:
6043                         ip_protocol = IPPROTO_RAW;
6044                         break;
6045                 }
6046
6047                 if (ip_protocol == IPPROTO_TCP)
6048                         opts[1] |= TD1_TCP_CS;
6049                 else if (ip_protocol == IPPROTO_UDP)
6050                         opts[1] |= TD1_UDP_CS;
6051                 else
6052                         WARN_ON_ONCE(1);
6053
6054                 opts[1] |= transport_offset << TCPHO_SHIFT;
6055         } else {
6056                 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
6057                         return !eth_skb_pad(skb);
6058         }
6059
6060         return true;
6061 }
6062
6063 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
6064                                       struct net_device *dev)
6065 {
6066         struct rtl8169_private *tp = netdev_priv(dev);
6067         unsigned int entry = tp->cur_tx % NUM_TX_DESC;
6068         struct TxDesc *txd = tp->TxDescArray + entry;
6069         struct device *d = tp_to_dev(tp);
6070         dma_addr_t mapping;
6071         u32 status, len;
6072         u32 opts[2];
6073         int frags;
6074
6075         if (unlikely(!TX_FRAGS_READY_FOR(tp, skb_shinfo(skb)->nr_frags))) {
6076                 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
6077                 goto err_stop_0;
6078         }
6079
6080         if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
6081                 goto err_stop_0;
6082
6083         opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(skb));
6084         opts[0] = DescOwn;
6085
6086         if (!tp->tso_csum(tp, skb, opts)) {
6087                 r8169_csum_workaround(tp, skb);
6088                 return NETDEV_TX_OK;
6089         }
6090
6091         len = skb_headlen(skb);
6092         mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
6093         if (unlikely(dma_mapping_error(d, mapping))) {
6094                 if (net_ratelimit())
6095                         netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
6096                 goto err_dma_0;
6097         }
6098
6099         tp->tx_skb[entry].len = len;
6100         txd->addr = cpu_to_le64(mapping);
6101
6102         frags = rtl8169_xmit_frags(tp, skb, opts);
6103         if (frags < 0)
6104                 goto err_dma_1;
6105         else if (frags)
6106                 opts[0] |= FirstFrag;
6107         else {
6108                 opts[0] |= FirstFrag | LastFrag;
6109                 tp->tx_skb[entry].skb = skb;
6110         }
6111
6112         txd->opts2 = cpu_to_le32(opts[1]);
6113
6114         netdev_sent_queue(dev, skb->len);
6115
6116         skb_tx_timestamp(skb);
6117
6118         /* Force memory writes to complete before releasing descriptor */
6119         dma_wmb();
6120
6121         /* Anti gcc 2.95.3 bugware (sic) */
6122         status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
6123         txd->opts1 = cpu_to_le32(status);
6124
6125         /* Force all memory writes to complete before notifying device */
6126         wmb();
6127
6128         tp->cur_tx += frags + 1;
6129
6130         RTL_W8(tp, TxPoll, NPQ);
6131
6132         mmiowb();
6133
6134         if (!TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
6135                 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
6136                  * not miss a ring update when it notices a stopped queue.
6137                  */
6138                 smp_wmb();
6139                 netif_stop_queue(dev);
6140                 /* Sync with rtl_tx:
6141                  * - publish queue status and cur_tx ring index (write barrier)
6142                  * - refresh dirty_tx ring index (read barrier).
6143                  * May the current thread have a pessimistic view of the ring
6144                  * status and forget to wake up queue, a racing rtl_tx thread
6145                  * can't.
6146                  */
6147                 smp_mb();
6148                 if (TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS))
6149                         netif_wake_queue(dev);
6150         }
6151
6152         return NETDEV_TX_OK;
6153
6154 err_dma_1:
6155         rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
6156 err_dma_0:
6157         dev_kfree_skb_any(skb);
6158         dev->stats.tx_dropped++;
6159         return NETDEV_TX_OK;
6160
6161 err_stop_0:
6162         netif_stop_queue(dev);
6163         dev->stats.tx_dropped++;
6164         return NETDEV_TX_BUSY;
6165 }
6166
6167 static void rtl8169_pcierr_interrupt(struct net_device *dev)
6168 {
6169         struct rtl8169_private *tp = netdev_priv(dev);
6170         struct pci_dev *pdev = tp->pci_dev;
6171         u16 pci_status, pci_cmd;
6172
6173         pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
6174         pci_read_config_word(pdev, PCI_STATUS, &pci_status);
6175
6176         netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
6177                   pci_cmd, pci_status);
6178
6179         /*
6180          * The recovery sequence below admits a very elaborated explanation:
6181          * - it seems to work;
6182          * - I did not see what else could be done;
6183          * - it makes iop3xx happy.
6184          *
6185          * Feel free to adjust to your needs.
6186          */
6187         if (pdev->broken_parity_status)
6188                 pci_cmd &= ~PCI_COMMAND_PARITY;
6189         else
6190                 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
6191
6192         pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
6193
6194         pci_write_config_word(pdev, PCI_STATUS,
6195                 pci_status & (PCI_STATUS_DETECTED_PARITY |
6196                 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
6197                 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
6198
6199         /* The infamous DAC f*ckup only happens at boot time */
6200         if ((tp->cp_cmd & PCIDAC) && !tp->cur_rx) {
6201                 netif_info(tp, intr, dev, "disabling PCI DAC\n");
6202                 tp->cp_cmd &= ~PCIDAC;
6203                 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
6204                 dev->features &= ~NETIF_F_HIGHDMA;
6205         }
6206
6207         rtl8169_hw_reset(tp);
6208
6209         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
6210 }
6211
6212 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp)
6213 {
6214         unsigned int dirty_tx, tx_left, bytes_compl = 0, pkts_compl = 0;
6215
6216         dirty_tx = tp->dirty_tx;
6217         smp_rmb();
6218         tx_left = tp->cur_tx - dirty_tx;
6219
6220         while (tx_left > 0) {
6221                 unsigned int entry = dirty_tx % NUM_TX_DESC;
6222                 struct ring_info *tx_skb = tp->tx_skb + entry;
6223                 u32 status;
6224
6225                 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
6226                 if (status & DescOwn)
6227                         break;
6228
6229                 /* This barrier is needed to keep us from reading
6230                  * any other fields out of the Tx descriptor until
6231                  * we know the status of DescOwn
6232                  */
6233                 dma_rmb();
6234
6235                 rtl8169_unmap_tx_skb(tp_to_dev(tp), tx_skb,
6236                                      tp->TxDescArray + entry);
6237                 if (status & LastFrag) {
6238                         pkts_compl++;
6239                         bytes_compl += tx_skb->skb->len;
6240                         dev_consume_skb_any(tx_skb->skb);
6241                         tx_skb->skb = NULL;
6242                 }
6243                 dirty_tx++;
6244                 tx_left--;
6245         }
6246
6247         if (tp->dirty_tx != dirty_tx) {
6248                 netdev_completed_queue(dev, pkts_compl, bytes_compl);
6249
6250                 u64_stats_update_begin(&tp->tx_stats.syncp);
6251                 tp->tx_stats.packets += pkts_compl;
6252                 tp->tx_stats.bytes += bytes_compl;
6253                 u64_stats_update_end(&tp->tx_stats.syncp);
6254
6255                 tp->dirty_tx = dirty_tx;
6256                 /* Sync with rtl8169_start_xmit:
6257                  * - publish dirty_tx ring index (write barrier)
6258                  * - refresh cur_tx ring index and queue status (read barrier)
6259                  * May the current thread miss the stopped queue condition,
6260                  * a racing xmit thread can only have a right view of the
6261                  * ring status.
6262                  */
6263                 smp_mb();
6264                 if (netif_queue_stopped(dev) &&
6265                     TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
6266                         netif_wake_queue(dev);
6267                 }
6268                 /*
6269                  * 8168 hack: TxPoll requests are lost when the Tx packets are
6270                  * too close. Let's kick an extra TxPoll request when a burst
6271                  * of start_xmit activity is detected (if it is not detected,
6272                  * it is slow enough). -- FR
6273                  */
6274                 if (tp->cur_tx != dirty_tx)
6275                         RTL_W8(tp, TxPoll, NPQ);
6276         }
6277 }
6278
6279 static inline int rtl8169_fragmented_frame(u32 status)
6280 {
6281         return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
6282 }
6283
6284 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
6285 {
6286         u32 status = opts1 & RxProtoMask;
6287
6288         if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
6289             ((status == RxProtoUDP) && !(opts1 & UDPFail)))
6290                 skb->ip_summed = CHECKSUM_UNNECESSARY;
6291         else
6292                 skb_checksum_none_assert(skb);
6293 }
6294
6295 static struct sk_buff *rtl8169_try_rx_copy(void *data,
6296                                            struct rtl8169_private *tp,
6297                                            int pkt_size,
6298                                            dma_addr_t addr)
6299 {
6300         struct sk_buff *skb;
6301         struct device *d = tp_to_dev(tp);
6302
6303         data = rtl8169_align(data);
6304         dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
6305         prefetch(data);
6306         skb = napi_alloc_skb(&tp->napi, pkt_size);
6307         if (skb)
6308                 skb_copy_to_linear_data(skb, data, pkt_size);
6309         dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
6310
6311         return skb;
6312 }
6313
6314 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget)
6315 {
6316         unsigned int cur_rx, rx_left;
6317         unsigned int count;
6318
6319         cur_rx = tp->cur_rx;
6320
6321         for (rx_left = min(budget, NUM_RX_DESC); rx_left > 0; rx_left--, cur_rx++) {
6322                 unsigned int entry = cur_rx % NUM_RX_DESC;
6323                 struct RxDesc *desc = tp->RxDescArray + entry;
6324                 u32 status;
6325
6326                 status = le32_to_cpu(desc->opts1);
6327                 if (status & DescOwn)
6328                         break;
6329
6330                 /* This barrier is needed to keep us from reading
6331                  * any other fields out of the Rx descriptor until
6332                  * we know the status of DescOwn
6333                  */
6334                 dma_rmb();
6335
6336                 if (unlikely(status & RxRES)) {
6337                         netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
6338                                    status);
6339                         dev->stats.rx_errors++;
6340                         if (status & (RxRWT | RxRUNT))
6341                                 dev->stats.rx_length_errors++;
6342                         if (status & RxCRC)
6343                                 dev->stats.rx_crc_errors++;
6344                         /* RxFOVF is a reserved bit on later chip versions */
6345                         if (tp->mac_version == RTL_GIGA_MAC_VER_01 &&
6346                             status & RxFOVF) {
6347                                 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
6348                                 dev->stats.rx_fifo_errors++;
6349                         } else if (status & (RxRUNT | RxCRC) &&
6350                                    !(status & RxRWT) &&
6351                                    dev->features & NETIF_F_RXALL) {
6352                                 goto process_pkt;
6353                         }
6354                 } else {
6355                         struct sk_buff *skb;
6356                         dma_addr_t addr;
6357                         int pkt_size;
6358
6359 process_pkt:
6360                         addr = le64_to_cpu(desc->addr);
6361                         if (likely(!(dev->features & NETIF_F_RXFCS)))
6362                                 pkt_size = (status & 0x00003fff) - 4;
6363                         else
6364                                 pkt_size = status & 0x00003fff;
6365
6366                         /*
6367                          * The driver does not support incoming fragmented
6368                          * frames. They are seen as a symptom of over-mtu
6369                          * sized frames.
6370                          */
6371                         if (unlikely(rtl8169_fragmented_frame(status))) {
6372                                 dev->stats.rx_dropped++;
6373                                 dev->stats.rx_length_errors++;
6374                                 goto release_descriptor;
6375                         }
6376
6377                         skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
6378                                                   tp, pkt_size, addr);
6379                         if (!skb) {
6380                                 dev->stats.rx_dropped++;
6381                                 goto release_descriptor;
6382                         }
6383
6384                         rtl8169_rx_csum(skb, status);
6385                         skb_put(skb, pkt_size);
6386                         skb->protocol = eth_type_trans(skb, dev);
6387
6388                         rtl8169_rx_vlan_tag(desc, skb);
6389
6390                         if (skb->pkt_type == PACKET_MULTICAST)
6391                                 dev->stats.multicast++;
6392
6393                         napi_gro_receive(&tp->napi, skb);
6394
6395                         u64_stats_update_begin(&tp->rx_stats.syncp);
6396                         tp->rx_stats.packets++;
6397                         tp->rx_stats.bytes += pkt_size;
6398                         u64_stats_update_end(&tp->rx_stats.syncp);
6399                 }
6400 release_descriptor:
6401                 desc->opts2 = 0;
6402                 rtl8169_mark_to_asic(desc);
6403         }
6404
6405         count = cur_rx - tp->cur_rx;
6406         tp->cur_rx = cur_rx;
6407
6408         return count;
6409 }
6410
6411 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
6412 {
6413         struct rtl8169_private *tp = dev_instance;
6414         u16 status = rtl_get_events(tp);
6415
6416         if (status == 0xffff || !(status & tp->irq_mask))
6417                 return IRQ_NONE;
6418
6419         if (unlikely(status & SYSErr)) {
6420                 rtl8169_pcierr_interrupt(tp->dev);
6421                 goto out;
6422         }
6423
6424         if (status & LinkChg)
6425                 phy_mac_interrupt(tp->dev->phydev);
6426
6427         if (unlikely(status & RxFIFOOver &&
6428             tp->mac_version == RTL_GIGA_MAC_VER_11)) {
6429                 netif_stop_queue(tp->dev);
6430                 /* XXX - Hack alert. See rtl_task(). */
6431                 set_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags);
6432         }
6433
6434         if (status & RTL_EVENT_NAPI) {
6435                 rtl_irq_disable(tp);
6436                 napi_schedule_irqoff(&tp->napi);
6437         }
6438 out:
6439         rtl_ack_events(tp, status);
6440
6441         return IRQ_HANDLED;
6442 }
6443
6444 static void rtl_task(struct work_struct *work)
6445 {
6446         static const struct {
6447                 int bitnr;
6448                 void (*action)(struct rtl8169_private *);
6449         } rtl_work[] = {
6450                 { RTL_FLAG_TASK_RESET_PENDING,  rtl_reset_work },
6451         };
6452         struct rtl8169_private *tp =
6453                 container_of(work, struct rtl8169_private, wk.work);
6454         struct net_device *dev = tp->dev;
6455         int i;
6456
6457         rtl_lock_work(tp);
6458
6459         if (!netif_running(dev) ||
6460             !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
6461                 goto out_unlock;
6462
6463         for (i = 0; i < ARRAY_SIZE(rtl_work); i++) {
6464                 bool pending;
6465
6466                 pending = test_and_clear_bit(rtl_work[i].bitnr, tp->wk.flags);
6467                 if (pending)
6468                         rtl_work[i].action(tp);
6469         }
6470
6471 out_unlock:
6472         rtl_unlock_work(tp);
6473 }
6474
6475 static int rtl8169_poll(struct napi_struct *napi, int budget)
6476 {
6477         struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
6478         struct net_device *dev = tp->dev;
6479         int work_done;
6480
6481         work_done = rtl_rx(dev, tp, (u32) budget);
6482
6483         rtl_tx(dev, tp);
6484
6485         if (work_done < budget) {
6486                 napi_complete_done(napi, work_done);
6487
6488                 rtl_irq_enable(tp);
6489                 mmiowb();
6490         }
6491
6492         return work_done;
6493 }
6494
6495 static void rtl8169_rx_missed(struct net_device *dev)
6496 {
6497         struct rtl8169_private *tp = netdev_priv(dev);
6498
6499         if (tp->mac_version > RTL_GIGA_MAC_VER_06)
6500                 return;
6501
6502         dev->stats.rx_missed_errors += RTL_R32(tp, RxMissed) & 0xffffff;
6503         RTL_W32(tp, RxMissed, 0);
6504 }
6505
6506 static void r8169_phylink_handler(struct net_device *ndev)
6507 {
6508         struct rtl8169_private *tp = netdev_priv(ndev);
6509
6510         if (netif_carrier_ok(ndev)) {
6511                 rtl_link_chg_patch(tp);
6512                 pm_request_resume(&tp->pci_dev->dev);
6513         } else {
6514                 pm_runtime_idle(&tp->pci_dev->dev);
6515         }
6516
6517         if (net_ratelimit())
6518                 phy_print_status(ndev->phydev);
6519 }
6520
6521 static int r8169_phy_connect(struct rtl8169_private *tp)
6522 {
6523         struct phy_device *phydev = mdiobus_get_phy(tp->mii_bus, 0);
6524         phy_interface_t phy_mode;
6525         int ret;
6526
6527         phy_mode = tp->supports_gmii ? PHY_INTERFACE_MODE_GMII :
6528                    PHY_INTERFACE_MODE_MII;
6529
6530         ret = phy_connect_direct(tp->dev, phydev, r8169_phylink_handler,
6531                                  phy_mode);
6532         if (ret)
6533                 return ret;
6534
6535         if (!tp->supports_gmii)
6536                 phy_set_max_speed(phydev, SPEED_100);
6537
6538         /* Ensure to advertise everything, incl. pause */
6539         linkmode_copy(phydev->advertising, phydev->supported);
6540
6541         phy_attached_info(phydev);
6542
6543         return 0;
6544 }
6545
6546 static void rtl8169_down(struct net_device *dev)
6547 {
6548         struct rtl8169_private *tp = netdev_priv(dev);
6549
6550         phy_stop(dev->phydev);
6551
6552         napi_disable(&tp->napi);
6553         netif_stop_queue(dev);
6554
6555         rtl8169_hw_reset(tp);
6556         /*
6557          * At this point device interrupts can not be enabled in any function,
6558          * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task)
6559          * and napi is disabled (rtl8169_poll).
6560          */
6561         rtl8169_rx_missed(dev);
6562
6563         /* Give a racing hard_start_xmit a few cycles to complete. */
6564         synchronize_sched();
6565
6566         rtl8169_tx_clear(tp);
6567
6568         rtl8169_rx_clear(tp);
6569
6570         rtl_pll_power_down(tp);
6571 }
6572
6573 static int rtl8169_close(struct net_device *dev)
6574 {
6575         struct rtl8169_private *tp = netdev_priv(dev);
6576         struct pci_dev *pdev = tp->pci_dev;
6577
6578         pm_runtime_get_sync(&pdev->dev);
6579
6580         /* Update counters before going down */
6581         rtl8169_update_counters(tp);
6582
6583         rtl_lock_work(tp);
6584         /* Clear all task flags */
6585         bitmap_zero(tp->wk.flags, RTL_FLAG_MAX);
6586
6587         rtl8169_down(dev);
6588         rtl_unlock_work(tp);
6589
6590         cancel_work_sync(&tp->wk.work);
6591
6592         phy_disconnect(dev->phydev);
6593
6594         pci_free_irq(pdev, 0, tp);
6595
6596         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6597                           tp->RxPhyAddr);
6598         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6599                           tp->TxPhyAddr);
6600         tp->TxDescArray = NULL;
6601         tp->RxDescArray = NULL;
6602
6603         pm_runtime_put_sync(&pdev->dev);
6604
6605         return 0;
6606 }
6607
6608 #ifdef CONFIG_NET_POLL_CONTROLLER
6609 static void rtl8169_netpoll(struct net_device *dev)
6610 {
6611         struct rtl8169_private *tp = netdev_priv(dev);
6612
6613         rtl8169_interrupt(pci_irq_vector(tp->pci_dev, 0), tp);
6614 }
6615 #endif
6616
6617 static int rtl_open(struct net_device *dev)
6618 {
6619         struct rtl8169_private *tp = netdev_priv(dev);
6620         struct pci_dev *pdev = tp->pci_dev;
6621         int retval = -ENOMEM;
6622
6623         pm_runtime_get_sync(&pdev->dev);
6624
6625         /*
6626          * Rx and Tx descriptors needs 256 bytes alignment.
6627          * dma_alloc_coherent provides more.
6628          */
6629         tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
6630                                              &tp->TxPhyAddr, GFP_KERNEL);
6631         if (!tp->TxDescArray)
6632                 goto err_pm_runtime_put;
6633
6634         tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
6635                                              &tp->RxPhyAddr, GFP_KERNEL);
6636         if (!tp->RxDescArray)
6637                 goto err_free_tx_0;
6638
6639         retval = rtl8169_init_ring(tp);
6640         if (retval < 0)
6641                 goto err_free_rx_1;
6642
6643         INIT_WORK(&tp->wk.work, rtl_task);
6644
6645         smp_mb();
6646
6647         rtl_request_firmware(tp);
6648
6649         retval = pci_request_irq(pdev, 0, rtl8169_interrupt, NULL, tp,
6650                                  dev->name);
6651         if (retval < 0)
6652                 goto err_release_fw_2;
6653
6654         retval = r8169_phy_connect(tp);
6655         if (retval)
6656                 goto err_free_irq;
6657
6658         rtl_lock_work(tp);
6659
6660         set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6661
6662         napi_enable(&tp->napi);
6663
6664         rtl8169_init_phy(dev, tp);
6665
6666         rtl_pll_power_up(tp);
6667
6668         rtl_hw_start(tp);
6669
6670         if (!rtl8169_init_counter_offsets(tp))
6671                 netif_warn(tp, hw, dev, "counter reset/update failed\n");
6672
6673         phy_start(dev->phydev);
6674         netif_start_queue(dev);
6675
6676         rtl_unlock_work(tp);
6677
6678         pm_runtime_put_sync(&pdev->dev);
6679 out:
6680         return retval;
6681
6682 err_free_irq:
6683         pci_free_irq(pdev, 0, tp);
6684 err_release_fw_2:
6685         rtl_release_firmware(tp);
6686         rtl8169_rx_clear(tp);
6687 err_free_rx_1:
6688         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6689                           tp->RxPhyAddr);
6690         tp->RxDescArray = NULL;
6691 err_free_tx_0:
6692         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6693                           tp->TxPhyAddr);
6694         tp->TxDescArray = NULL;
6695 err_pm_runtime_put:
6696         pm_runtime_put_noidle(&pdev->dev);
6697         goto out;
6698 }
6699
6700 static void
6701 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
6702 {
6703         struct rtl8169_private *tp = netdev_priv(dev);
6704         struct pci_dev *pdev = tp->pci_dev;
6705         struct rtl8169_counters *counters = tp->counters;
6706         unsigned int start;
6707
6708         pm_runtime_get_noresume(&pdev->dev);
6709
6710         if (netif_running(dev) && pm_runtime_active(&pdev->dev))
6711                 rtl8169_rx_missed(dev);
6712
6713         do {
6714                 start = u64_stats_fetch_begin_irq(&tp->rx_stats.syncp);
6715                 stats->rx_packets = tp->rx_stats.packets;
6716                 stats->rx_bytes = tp->rx_stats.bytes;
6717         } while (u64_stats_fetch_retry_irq(&tp->rx_stats.syncp, start));
6718
6719         do {
6720                 start = u64_stats_fetch_begin_irq(&tp->tx_stats.syncp);
6721                 stats->tx_packets = tp->tx_stats.packets;
6722                 stats->tx_bytes = tp->tx_stats.bytes;
6723         } while (u64_stats_fetch_retry_irq(&tp->tx_stats.syncp, start));
6724
6725         stats->rx_dropped       = dev->stats.rx_dropped;
6726         stats->tx_dropped       = dev->stats.tx_dropped;
6727         stats->rx_length_errors = dev->stats.rx_length_errors;
6728         stats->rx_errors        = dev->stats.rx_errors;
6729         stats->rx_crc_errors    = dev->stats.rx_crc_errors;
6730         stats->rx_fifo_errors   = dev->stats.rx_fifo_errors;
6731         stats->rx_missed_errors = dev->stats.rx_missed_errors;
6732         stats->multicast        = dev->stats.multicast;
6733
6734         /*
6735          * Fetch additonal counter values missing in stats collected by driver
6736          * from tally counters.
6737          */
6738         if (pm_runtime_active(&pdev->dev))
6739                 rtl8169_update_counters(tp);
6740
6741         /*
6742          * Subtract values fetched during initalization.
6743          * See rtl8169_init_counter_offsets for a description why we do that.
6744          */
6745         stats->tx_errors = le64_to_cpu(counters->tx_errors) -
6746                 le64_to_cpu(tp->tc_offset.tx_errors);
6747         stats->collisions = le32_to_cpu(counters->tx_multi_collision) -
6748                 le32_to_cpu(tp->tc_offset.tx_multi_collision);
6749         stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) -
6750                 le16_to_cpu(tp->tc_offset.tx_aborted);
6751
6752         pm_runtime_put_noidle(&pdev->dev);
6753 }
6754
6755 static void rtl8169_net_suspend(struct net_device *dev)
6756 {
6757         struct rtl8169_private *tp = netdev_priv(dev);
6758
6759         if (!netif_running(dev))
6760                 return;
6761
6762         phy_stop(dev->phydev);
6763         netif_device_detach(dev);
6764
6765         rtl_lock_work(tp);
6766         napi_disable(&tp->napi);
6767         /* Clear all task flags */
6768         bitmap_zero(tp->wk.flags, RTL_FLAG_MAX);
6769
6770         rtl_unlock_work(tp);
6771
6772         rtl_pll_power_down(tp);
6773 }
6774
6775 #ifdef CONFIG_PM
6776
6777 static int rtl8169_suspend(struct device *device)
6778 {
6779         struct net_device *dev = dev_get_drvdata(device);
6780         struct rtl8169_private *tp = netdev_priv(dev);
6781
6782         rtl8169_net_suspend(dev);
6783         clk_disable_unprepare(tp->clk);
6784
6785         return 0;
6786 }
6787
6788 static void __rtl8169_resume(struct net_device *dev)
6789 {
6790         struct rtl8169_private *tp = netdev_priv(dev);
6791
6792         netif_device_attach(dev);
6793
6794         rtl_pll_power_up(tp);
6795         rtl8169_init_phy(dev, tp);
6796
6797         phy_start(tp->dev->phydev);
6798
6799         rtl_lock_work(tp);
6800         napi_enable(&tp->napi);
6801         set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6802         rtl_unlock_work(tp);
6803
6804         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
6805 }
6806
6807 static int rtl8169_resume(struct device *device)
6808 {
6809         struct net_device *dev = dev_get_drvdata(device);
6810         struct rtl8169_private *tp = netdev_priv(dev);
6811
6812         clk_prepare_enable(tp->clk);
6813
6814         if (netif_running(dev))
6815                 __rtl8169_resume(dev);
6816
6817         return 0;
6818 }
6819
6820 static int rtl8169_runtime_suspend(struct device *device)
6821 {
6822         struct net_device *dev = dev_get_drvdata(device);
6823         struct rtl8169_private *tp = netdev_priv(dev);
6824
6825         if (!tp->TxDescArray)
6826                 return 0;
6827
6828         rtl_lock_work(tp);
6829         __rtl8169_set_wol(tp, WAKE_ANY);
6830         rtl_unlock_work(tp);
6831
6832         rtl8169_net_suspend(dev);
6833
6834         /* Update counters before going runtime suspend */
6835         rtl8169_rx_missed(dev);
6836         rtl8169_update_counters(tp);
6837
6838         return 0;
6839 }
6840
6841 static int rtl8169_runtime_resume(struct device *device)
6842 {
6843         struct net_device *dev = dev_get_drvdata(device);
6844         struct rtl8169_private *tp = netdev_priv(dev);
6845         rtl_rar_set(tp, dev->dev_addr);
6846
6847         if (!tp->TxDescArray)
6848                 return 0;
6849
6850         rtl_lock_work(tp);
6851         __rtl8169_set_wol(tp, tp->saved_wolopts);
6852         rtl_unlock_work(tp);
6853
6854         __rtl8169_resume(dev);
6855
6856         return 0;
6857 }
6858
6859 static int rtl8169_runtime_idle(struct device *device)
6860 {
6861         struct net_device *dev = dev_get_drvdata(device);
6862
6863         if (!netif_running(dev) || !netif_carrier_ok(dev))
6864                 pm_schedule_suspend(device, 10000);
6865
6866         return -EBUSY;
6867 }
6868
6869 static const struct dev_pm_ops rtl8169_pm_ops = {
6870         .suspend                = rtl8169_suspend,
6871         .resume                 = rtl8169_resume,
6872         .freeze                 = rtl8169_suspend,
6873         .thaw                   = rtl8169_resume,
6874         .poweroff               = rtl8169_suspend,
6875         .restore                = rtl8169_resume,
6876         .runtime_suspend        = rtl8169_runtime_suspend,
6877         .runtime_resume         = rtl8169_runtime_resume,
6878         .runtime_idle           = rtl8169_runtime_idle,
6879 };
6880
6881 #define RTL8169_PM_OPS  (&rtl8169_pm_ops)
6882
6883 #else /* !CONFIG_PM */
6884
6885 #define RTL8169_PM_OPS  NULL
6886
6887 #endif /* !CONFIG_PM */
6888
6889 static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
6890 {
6891         /* WoL fails with 8168b when the receiver is disabled. */
6892         switch (tp->mac_version) {
6893         case RTL_GIGA_MAC_VER_11:
6894         case RTL_GIGA_MAC_VER_12:
6895         case RTL_GIGA_MAC_VER_17:
6896                 pci_clear_master(tp->pci_dev);
6897
6898                 RTL_W8(tp, ChipCmd, CmdRxEnb);
6899                 /* PCI commit */
6900                 RTL_R8(tp, ChipCmd);
6901                 break;
6902         default:
6903                 break;
6904         }
6905 }
6906
6907 static void rtl_shutdown(struct pci_dev *pdev)
6908 {
6909         struct net_device *dev = pci_get_drvdata(pdev);
6910         struct rtl8169_private *tp = netdev_priv(dev);
6911
6912         rtl8169_net_suspend(dev);
6913
6914         /* Restore original MAC address */
6915         rtl_rar_set(tp, dev->perm_addr);
6916
6917         rtl8169_hw_reset(tp);
6918
6919         if (system_state == SYSTEM_POWER_OFF) {
6920                 if (tp->saved_wolopts) {
6921                         rtl_wol_suspend_quirk(tp);
6922                         rtl_wol_shutdown_quirk(tp);
6923                 }
6924
6925                 pci_wake_from_d3(pdev, true);
6926                 pci_set_power_state(pdev, PCI_D3hot);
6927         }
6928 }
6929
6930 static void rtl_remove_one(struct pci_dev *pdev)
6931 {
6932         struct net_device *dev = pci_get_drvdata(pdev);
6933         struct rtl8169_private *tp = netdev_priv(dev);
6934
6935         if (r8168_check_dash(tp))
6936                 rtl8168_driver_stop(tp);
6937
6938         netif_napi_del(&tp->napi);
6939
6940         unregister_netdev(dev);
6941         mdiobus_unregister(tp->mii_bus);
6942
6943         rtl_release_firmware(tp);
6944
6945         if (pci_dev_run_wake(pdev))
6946                 pm_runtime_get_noresume(&pdev->dev);
6947
6948         /* restore original MAC address */
6949         rtl_rar_set(tp, dev->perm_addr);
6950 }
6951
6952 static const struct net_device_ops rtl_netdev_ops = {
6953         .ndo_open               = rtl_open,
6954         .ndo_stop               = rtl8169_close,
6955         .ndo_get_stats64        = rtl8169_get_stats64,
6956         .ndo_start_xmit         = rtl8169_start_xmit,
6957         .ndo_tx_timeout         = rtl8169_tx_timeout,
6958         .ndo_validate_addr      = eth_validate_addr,
6959         .ndo_change_mtu         = rtl8169_change_mtu,
6960         .ndo_fix_features       = rtl8169_fix_features,
6961         .ndo_set_features       = rtl8169_set_features,
6962         .ndo_set_mac_address    = rtl_set_mac_address,
6963         .ndo_do_ioctl           = rtl8169_ioctl,
6964         .ndo_set_rx_mode        = rtl_set_rx_mode,
6965 #ifdef CONFIG_NET_POLL_CONTROLLER
6966         .ndo_poll_controller    = rtl8169_netpoll,
6967 #endif
6968
6969 };
6970
6971 static const struct rtl_cfg_info {
6972         void (*hw_start)(struct rtl8169_private *tp);
6973         u16 irq_mask;
6974         unsigned int has_gmii:1;
6975         const struct rtl_coalesce_info *coalesce_info;
6976         u8 default_ver;
6977 } rtl_cfg_infos [] = {
6978         [RTL_CFG_0] = {
6979                 .hw_start       = rtl_hw_start_8169,
6980                 .irq_mask       = SYSErr | LinkChg | RxOverflow | RxFIFOOver,
6981                 .has_gmii       = 1,
6982                 .coalesce_info  = rtl_coalesce_info_8169,
6983                 .default_ver    = RTL_GIGA_MAC_VER_01,
6984         },
6985         [RTL_CFG_1] = {
6986                 .hw_start       = rtl_hw_start_8168,
6987                 .irq_mask       = LinkChg | RxOverflow,
6988                 .has_gmii       = 1,
6989                 .coalesce_info  = rtl_coalesce_info_8168_8136,
6990                 .default_ver    = RTL_GIGA_MAC_VER_11,
6991         },
6992         [RTL_CFG_2] = {
6993                 .hw_start       = rtl_hw_start_8101,
6994                 .irq_mask       = LinkChg | RxOverflow | RxFIFOOver,
6995                 .coalesce_info  = rtl_coalesce_info_8168_8136,
6996                 .default_ver    = RTL_GIGA_MAC_VER_13,
6997         }
6998 };
6999
7000 static int rtl_alloc_irq(struct rtl8169_private *tp)
7001 {
7002         unsigned int flags;
7003
7004         if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
7005                 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
7006                 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~MSIEnable);
7007                 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
7008                 flags = PCI_IRQ_LEGACY;
7009         } else {
7010                 flags = PCI_IRQ_ALL_TYPES;
7011         }
7012
7013         return pci_alloc_irq_vectors(tp->pci_dev, 1, 1, flags);
7014 }
7015
7016 DECLARE_RTL_COND(rtl_link_list_ready_cond)
7017 {
7018         return RTL_R8(tp, MCU) & LINK_LIST_RDY;
7019 }
7020
7021 DECLARE_RTL_COND(rtl_rxtx_empty_cond)
7022 {
7023         return (RTL_R8(tp, MCU) & RXTX_EMPTY) == RXTX_EMPTY;
7024 }
7025
7026 static int r8169_mdio_read_reg(struct mii_bus *mii_bus, int phyaddr, int phyreg)
7027 {
7028         struct rtl8169_private *tp = mii_bus->priv;
7029
7030         if (phyaddr > 0)
7031                 return -ENODEV;
7032
7033         return rtl_readphy(tp, phyreg);
7034 }
7035
7036 static int r8169_mdio_write_reg(struct mii_bus *mii_bus, int phyaddr,
7037                                 int phyreg, u16 val)
7038 {
7039         struct rtl8169_private *tp = mii_bus->priv;
7040
7041         if (phyaddr > 0)
7042                 return -ENODEV;
7043
7044         rtl_writephy(tp, phyreg, val);
7045
7046         return 0;
7047 }
7048
7049 static int r8169_mdio_register(struct rtl8169_private *tp)
7050 {
7051         struct pci_dev *pdev = tp->pci_dev;
7052         struct phy_device *phydev;
7053         struct mii_bus *new_bus;
7054         int ret;
7055
7056         new_bus = devm_mdiobus_alloc(&pdev->dev);
7057         if (!new_bus)
7058                 return -ENOMEM;
7059
7060         new_bus->name = "r8169";
7061         new_bus->priv = tp;
7062         new_bus->parent = &pdev->dev;
7063         new_bus->irq[0] = PHY_IGNORE_INTERRUPT;
7064         snprintf(new_bus->id, MII_BUS_ID_SIZE, "r8169-%x",
7065                  PCI_DEVID(pdev->bus->number, pdev->devfn));
7066
7067         new_bus->read = r8169_mdio_read_reg;
7068         new_bus->write = r8169_mdio_write_reg;
7069
7070         ret = mdiobus_register(new_bus);
7071         if (ret)
7072                 return ret;
7073
7074         phydev = mdiobus_get_phy(new_bus, 0);
7075         if (!phydev) {
7076                 mdiobus_unregister(new_bus);
7077                 return -ENODEV;
7078         }
7079
7080         /* PHY will be woken up in rtl_open() */
7081         phy_suspend(phydev);
7082
7083         tp->mii_bus = new_bus;
7084
7085         return 0;
7086 }
7087
7088 static void rtl_hw_init_8168g(struct rtl8169_private *tp)
7089 {
7090         u32 data;
7091
7092         tp->ocp_base = OCP_STD_PHY_BASE;
7093
7094         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN);
7095
7096         if (!rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42))
7097                 return;
7098
7099         if (!rtl_udelay_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42))
7100                 return;
7101
7102         RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
7103         msleep(1);
7104         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
7105
7106         data = r8168_mac_ocp_read(tp, 0xe8de);
7107         data &= ~(1 << 14);
7108         r8168_mac_ocp_write(tp, 0xe8de, data);
7109
7110         if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
7111                 return;
7112
7113         data = r8168_mac_ocp_read(tp, 0xe8de);
7114         data |= (1 << 15);
7115         r8168_mac_ocp_write(tp, 0xe8de, data);
7116
7117         if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
7118                 return;
7119 }
7120
7121 static void rtl_hw_init_8168ep(struct rtl8169_private *tp)
7122 {
7123         rtl8168ep_stop_cmac(tp);
7124         rtl_hw_init_8168g(tp);
7125 }
7126
7127 static void rtl_hw_initialize(struct rtl8169_private *tp)
7128 {
7129         switch (tp->mac_version) {
7130         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_48:
7131                 rtl_hw_init_8168g(tp);
7132                 break;
7133         case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_51:
7134                 rtl_hw_init_8168ep(tp);
7135                 break;
7136         default:
7137                 break;
7138         }
7139 }
7140
7141 /* Versions RTL8102e and from RTL8168c onwards support csum_v2 */
7142 static bool rtl_chip_supports_csum_v2(struct rtl8169_private *tp)
7143 {
7144         switch (tp->mac_version) {
7145         case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_06:
7146         case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
7147                 return false;
7148         default:
7149                 return true;
7150         }
7151 }
7152
7153 static int rtl_jumbo_max(struct rtl8169_private *tp)
7154 {
7155         /* Non-GBit versions don't support jumbo frames */
7156         if (!tp->supports_gmii)
7157                 return JUMBO_1K;
7158
7159         switch (tp->mac_version) {
7160         /* RTL8169 */
7161         case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_06:
7162                 return JUMBO_7K;
7163         /* RTL8168b */
7164         case RTL_GIGA_MAC_VER_11:
7165         case RTL_GIGA_MAC_VER_12:
7166         case RTL_GIGA_MAC_VER_17:
7167                 return JUMBO_4K;
7168         /* RTL8168c */
7169         case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
7170                 return JUMBO_6K;
7171         default:
7172                 return JUMBO_9K;
7173         }
7174 }
7175
7176 static void rtl_disable_clk(void *data)
7177 {
7178         clk_disable_unprepare(data);
7179 }
7180
7181 static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
7182 {
7183         const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
7184         struct rtl8169_private *tp;
7185         struct net_device *dev;
7186         int chipset, region, i;
7187         int jumbo_max, rc;
7188
7189         dev = devm_alloc_etherdev(&pdev->dev, sizeof (*tp));
7190         if (!dev)
7191                 return -ENOMEM;
7192
7193         SET_NETDEV_DEV(dev, &pdev->dev);
7194         dev->netdev_ops = &rtl_netdev_ops;
7195         tp = netdev_priv(dev);
7196         tp->dev = dev;
7197         tp->pci_dev = pdev;
7198         tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
7199         tp->supports_gmii = cfg->has_gmii;
7200
7201         /* Get the *optional* external "ether_clk" used on some boards */
7202         tp->clk = devm_clk_get(&pdev->dev, "ether_clk");
7203         if (IS_ERR(tp->clk)) {
7204                 rc = PTR_ERR(tp->clk);
7205                 if (rc == -ENOENT) {
7206                         /* clk-core allows NULL (for suspend / resume) */
7207                         tp->clk = NULL;
7208                 } else if (rc == -EPROBE_DEFER) {
7209                         return rc;
7210                 } else {
7211                         dev_err(&pdev->dev, "failed to get clk: %d\n", rc);
7212                         return rc;
7213                 }
7214         } else {
7215                 rc = clk_prepare_enable(tp->clk);
7216                 if (rc) {
7217                         dev_err(&pdev->dev, "failed to enable clk: %d\n", rc);
7218                         return rc;
7219                 }
7220
7221                 rc = devm_add_action_or_reset(&pdev->dev, rtl_disable_clk,
7222                                               tp->clk);
7223                 if (rc)
7224                         return rc;
7225         }
7226
7227         /* enable device (incl. PCI PM wakeup and hotplug setup) */
7228         rc = pcim_enable_device(pdev);
7229         if (rc < 0) {
7230                 dev_err(&pdev->dev, "enable failure\n");
7231                 return rc;
7232         }
7233
7234         if (pcim_set_mwi(pdev) < 0)
7235                 dev_info(&pdev->dev, "Mem-Wr-Inval unavailable\n");
7236
7237         /* use first MMIO region */
7238         region = ffs(pci_select_bars(pdev, IORESOURCE_MEM)) - 1;
7239         if (region < 0) {
7240                 dev_err(&pdev->dev, "no MMIO resource found\n");
7241                 return -ENODEV;
7242         }
7243
7244         /* check for weird/broken PCI region reporting */
7245         if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
7246                 dev_err(&pdev->dev, "Invalid PCI region size(s), aborting\n");
7247                 return -ENODEV;
7248         }
7249
7250         rc = pcim_iomap_regions(pdev, BIT(region), MODULENAME);
7251         if (rc < 0) {
7252                 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
7253                 return rc;
7254         }
7255
7256         tp->mmio_addr = pcim_iomap_table(pdev)[region];
7257
7258         /* Identify chip attached to board */
7259         rtl8169_get_mac_version(tp, cfg->default_ver);
7260
7261         if (rtl_tbi_enabled(tp)) {
7262                 dev_err(&pdev->dev, "TBI fiber mode not supported\n");
7263                 return -ENODEV;
7264         }
7265
7266         tp->cp_cmd = RTL_R16(tp, CPlusCmd);
7267
7268         if (sizeof(dma_addr_t) > 4 && (use_dac == 1 || (use_dac == -1 &&
7269             tp->mac_version >= RTL_GIGA_MAC_VER_18)) &&
7270             !dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) {
7271
7272                 /* CPlusCmd Dual Access Cycle is only needed for non-PCIe */
7273                 if (!pci_is_pcie(pdev))
7274                         tp->cp_cmd |= PCIDAC;
7275                 dev->features |= NETIF_F_HIGHDMA;
7276         } else {
7277                 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
7278                 if (rc < 0) {
7279                         dev_err(&pdev->dev, "DMA configuration failed\n");
7280                         return rc;
7281                 }
7282         }
7283
7284         rtl_init_rxcfg(tp);
7285
7286         rtl8169_irq_mask_and_ack(tp);
7287
7288         rtl_hw_initialize(tp);
7289
7290         rtl_hw_reset(tp);
7291
7292         pci_set_master(pdev);
7293
7294         rtl_init_mdio_ops(tp);
7295         rtl_init_jumbo_ops(tp);
7296
7297         chipset = tp->mac_version;
7298
7299         rc = rtl_alloc_irq(tp);
7300         if (rc < 0) {
7301                 dev_err(&pdev->dev, "Can't allocate interrupt\n");
7302                 return rc;
7303         }
7304
7305         tp->saved_wolopts = __rtl8169_get_wol(tp);
7306
7307         mutex_init(&tp->wk.mutex);
7308         u64_stats_init(&tp->rx_stats.syncp);
7309         u64_stats_init(&tp->tx_stats.syncp);
7310
7311         /* Get MAC address */
7312         switch (tp->mac_version) {
7313                 u8 mac_addr[ETH_ALEN] __aligned(4);
7314         case RTL_GIGA_MAC_VER_35 ... RTL_GIGA_MAC_VER_38:
7315         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
7316                 *(u32 *)&mac_addr[0] = rtl_eri_read(tp, 0xe0, ERIAR_EXGMAC);
7317                 *(u16 *)&mac_addr[4] = rtl_eri_read(tp, 0xe4, ERIAR_EXGMAC);
7318
7319                 if (is_valid_ether_addr(mac_addr))
7320                         rtl_rar_set(tp, mac_addr);
7321                 break;
7322         default:
7323                 break;
7324         }
7325         for (i = 0; i < ETH_ALEN; i++)
7326                 dev->dev_addr[i] = RTL_R8(tp, MAC0 + i);
7327
7328         dev->ethtool_ops = &rtl8169_ethtool_ops;
7329
7330         netif_napi_add(dev, &tp->napi, rtl8169_poll, NAPI_POLL_WEIGHT);
7331
7332         /* don't enable SG, IP_CSUM and TSO by default - it might not work
7333          * properly for all devices */
7334         dev->features |= NETIF_F_RXCSUM |
7335                 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
7336
7337         dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
7338                 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_TX |
7339                 NETIF_F_HW_VLAN_CTAG_RX;
7340         dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
7341                 NETIF_F_HIGHDMA;
7342         dev->priv_flags |= IFF_LIVE_ADDR_CHANGE;
7343
7344         tp->cp_cmd |= RxChkSum | RxVlan;
7345
7346         /*
7347          * Pretend we are using VLANs; This bypasses a nasty bug where
7348          * Interrupts stop flowing on high load on 8110SCd controllers.
7349          */
7350         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
7351                 /* Disallow toggling */
7352                 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX;
7353
7354         if (rtl_chip_supports_csum_v2(tp)) {
7355                 tp->tso_csum = rtl8169_tso_csum_v2;
7356                 dev->hw_features |= NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
7357         } else {
7358                 tp->tso_csum = rtl8169_tso_csum_v1;
7359         }
7360
7361         dev->hw_features |= NETIF_F_RXALL;
7362         dev->hw_features |= NETIF_F_RXFCS;
7363
7364         /* MTU range: 60 - hw-specific max */
7365         dev->min_mtu = ETH_ZLEN;
7366         jumbo_max = rtl_jumbo_max(tp);
7367         dev->max_mtu = jumbo_max;
7368
7369         tp->hw_start = cfg->hw_start;
7370         tp->irq_mask = RTL_EVENT_NAPI | cfg->irq_mask;
7371         tp->coalesce_info = cfg->coalesce_info;
7372
7373         tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
7374
7375         tp->counters = dmam_alloc_coherent (&pdev->dev, sizeof(*tp->counters),
7376                                             &tp->counters_phys_addr,
7377                                             GFP_KERNEL);
7378         if (!tp->counters)
7379                 return -ENOMEM;
7380
7381         pci_set_drvdata(pdev, dev);
7382
7383         rc = r8169_mdio_register(tp);
7384         if (rc)
7385                 return rc;
7386
7387         /* chip gets powered up in rtl_open() */
7388         rtl_pll_power_down(tp);
7389
7390         rc = register_netdev(dev);
7391         if (rc)
7392                 goto err_mdio_unregister;
7393
7394         netif_info(tp, probe, dev, "%s, %pM, XID %03x, IRQ %d\n",
7395                    rtl_chip_infos[chipset].name, dev->dev_addr,
7396                    (RTL_R32(tp, TxConfig) >> 20) & 0xfcf,
7397                    pci_irq_vector(pdev, 0));
7398
7399         if (jumbo_max > JUMBO_1K)
7400                 netif_info(tp, probe, dev,
7401                            "jumbo features [frames: %d bytes, tx checksumming: %s]\n",
7402                            jumbo_max, tp->mac_version <= RTL_GIGA_MAC_VER_06 ?
7403                            "ok" : "ko");
7404
7405         if (r8168_check_dash(tp))
7406                 rtl8168_driver_start(tp);
7407
7408         if (pci_dev_run_wake(pdev))
7409                 pm_runtime_put_sync(&pdev->dev);
7410
7411         return 0;
7412
7413 err_mdio_unregister:
7414         mdiobus_unregister(tp->mii_bus);
7415         return rc;
7416 }
7417
7418 static struct pci_driver rtl8169_pci_driver = {
7419         .name           = MODULENAME,
7420         .id_table       = rtl8169_pci_tbl,
7421         .probe          = rtl_init_one,
7422         .remove         = rtl_remove_one,
7423         .shutdown       = rtl_shutdown,
7424         .driver.pm      = RTL8169_PM_OPS,
7425 };
7426
7427 module_pci_driver(rtl8169_pci_driver);