drivers/net/ethernet/realtek/r8169.c

   1 /*
   2  * r8169.c: RealTek 8169/8168/8101 ethernet driver.
   3  *
   4  * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
   5  * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
   6  * Copyright (c) a lot of people too. Please respect their work.
   7  *
   8  * See MAINTAINERS file for support contact information.
   9  */
  10
  11 #include <linux/module.h>
  12 #include <linux/moduleparam.h>
  13 #include <linux/pci.h>
  14 #include <linux/netdevice.h>
  15 #include <linux/etherdevice.h>
  16 #include <linux/delay.h>
  17 #include <linux/ethtool.h>
  18 #include <linux/mii.h>
  19 #include <linux/if_vlan.h>
  20 #include <linux/crc32.h>
  21 #include <linux/in.h>
  22 #include <linux/ip.h>
  23 #include <linux/tcp.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/dma-mapping.h>
  26 #include <linux/pm_runtime.h>
  27 #include <linux/firmware.h>
  28 #include <linux/pci-aspm.h>
  29 #include <linux/prefetch.h>
  30 #include <linux/ipv6.h>
  31 #include <net/ip6_checksum.h>
  32
  33 #include <asm/io.h>
  34 #include <asm/irq.h>
  35
  36 #define RTL8169_VERSION "2.3LK-NAPI"
  37 #define MODULENAME "r8169"
  38 #define PFX MODULENAME ": "
  39
  40 #define FIRMWARE_8168D_1        "rtl_nic/rtl8168d-1.fw"
  41 #define FIRMWARE_8168D_2        "rtl_nic/rtl8168d-2.fw"
  42 #define FIRMWARE_8168E_1        "rtl_nic/rtl8168e-1.fw"
  43 #define FIRMWARE_8168E_2        "rtl_nic/rtl8168e-2.fw"
  44 #define FIRMWARE_8168E_3        "rtl_nic/rtl8168e-3.fw"
  45 #define FIRMWARE_8168F_1        "rtl_nic/rtl8168f-1.fw"
  46 #define FIRMWARE_8168F_2        "rtl_nic/rtl8168f-2.fw"
  47 #define FIRMWARE_8105E_1        "rtl_nic/rtl8105e-1.fw"
  48 #define FIRMWARE_8402_1         "rtl_nic/rtl8402-1.fw"
  49 #define FIRMWARE_8411_1         "rtl_nic/rtl8411-1.fw"
  50 #define FIRMWARE_8411_2         "rtl_nic/rtl8411-2.fw"
  51 #define FIRMWARE_8106E_1        "rtl_nic/rtl8106e-1.fw"
  52 #define FIRMWARE_8106E_2        "rtl_nic/rtl8106e-2.fw"
  53 #define FIRMWARE_8168G_2        "rtl_nic/rtl8168g-2.fw"
  54 #define FIRMWARE_8168G_3        "rtl_nic/rtl8168g-3.fw"
  55 #define FIRMWARE_8168H_1        "rtl_nic/rtl8168h-1.fw"
  56 #define FIRMWARE_8168H_2        "rtl_nic/rtl8168h-2.fw"
  57 #define FIRMWARE_8107E_1        "rtl_nic/rtl8107e-1.fw"
  58 #define FIRMWARE_8107E_2        "rtl_nic/rtl8107e-2.fw"
  59
  60 #ifdef RTL8169_DEBUG
  61 #define assert(expr) \
  62         if (!(expr)) {                                  \
  63                 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
  64                 #expr,__FILE__,__func__,__LINE__);              \
  65         }
  66 #define dprintk(fmt, args...) \
  67         do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
  68 #else
  69 #define assert(expr) do {} while (0)
  70 #define dprintk(fmt, args...)   do {} while (0)
  71 #endif /* RTL8169_DEBUG */
  72
  73 #define R8169_MSG_DEFAULT \
  74         (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
  75
  76 #define TX_SLOTS_AVAIL(tp) \
  77         (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx)
  78
  79 /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
  80 #define TX_FRAGS_READY_FOR(tp,nr_frags) \
  81         (TX_SLOTS_AVAIL(tp) >= (nr_frags + 1))
  82
  83 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
  84    The RTL chips use a 64 element hash table based on the Ethernet CRC. */
  85 static const int multicast_filter_limit = 32;
  86
  87 #define TX_DMA_BURST    7       /* Maximum PCI burst, '7' is unlimited */
  88 #define InterFrameGap   0x03    /* 3 means InterFrameGap = the shortest one */
  89
  90 #define R8169_REGS_SIZE         256
  91 #define R8169_RX_BUF_SIZE       (SZ_16K - 1)
  92 #define NUM_TX_DESC     64      /* Number of Tx descriptor registers */
  93 #define NUM_RX_DESC     256U    /* Number of Rx descriptor registers */
  94 #define R8169_TX_RING_BYTES     (NUM_TX_DESC * sizeof(struct TxDesc))
  95 #define R8169_RX_RING_BYTES     (NUM_RX_DESC * sizeof(struct RxDesc))
  96
  97 #define RTL8169_TX_TIMEOUT      (6*HZ)
  98 #define RTL8169_PHY_TIMEOUT     (10*HZ)
  99
 100 /* write/read MMIO register */
 101 #define RTL_W8(tp, reg, val8)   writeb((val8), tp->mmio_addr + (reg))
 102 #define RTL_W16(tp, reg, val16) writew((val16), tp->mmio_addr + (reg))
 103 #define RTL_W32(tp, reg, val32) writel((val32), tp->mmio_addr + (reg))
 104 #define RTL_R8(tp, reg)         readb(tp->mmio_addr + (reg))
 105 #define RTL_R16(tp, reg)                readw(tp->mmio_addr + (reg))
 106 #define RTL_R32(tp, reg)                readl(tp->mmio_addr + (reg))
 107
 108 enum mac_version {
 109         RTL_GIGA_MAC_VER_01 = 0,
 110         RTL_GIGA_MAC_VER_02,
 111         RTL_GIGA_MAC_VER_03,
 112         RTL_GIGA_MAC_VER_04,
 113         RTL_GIGA_MAC_VER_05,
 114         RTL_GIGA_MAC_VER_06,
 115         RTL_GIGA_MAC_VER_07,
 116         RTL_GIGA_MAC_VER_08,
 117         RTL_GIGA_MAC_VER_09,
 118         RTL_GIGA_MAC_VER_10,
 119         RTL_GIGA_MAC_VER_11,
 120         RTL_GIGA_MAC_VER_12,
 121         RTL_GIGA_MAC_VER_13,
 122         RTL_GIGA_MAC_VER_14,
 123         RTL_GIGA_MAC_VER_15,
 124         RTL_GIGA_MAC_VER_16,
 125         RTL_GIGA_MAC_VER_17,
 126         RTL_GIGA_MAC_VER_18,
 127         RTL_GIGA_MAC_VER_19,
 128         RTL_GIGA_MAC_VER_20,
 129         RTL_GIGA_MAC_VER_21,
 130         RTL_GIGA_MAC_VER_22,
 131         RTL_GIGA_MAC_VER_23,
 132         RTL_GIGA_MAC_VER_24,
 133         RTL_GIGA_MAC_VER_25,
 134         RTL_GIGA_MAC_VER_26,
 135         RTL_GIGA_MAC_VER_27,
 136         RTL_GIGA_MAC_VER_28,
 137         RTL_GIGA_MAC_VER_29,
 138         RTL_GIGA_MAC_VER_30,
 139         RTL_GIGA_MAC_VER_31,
 140         RTL_GIGA_MAC_VER_32,
 141         RTL_GIGA_MAC_VER_33,
 142         RTL_GIGA_MAC_VER_34,
 143         RTL_GIGA_MAC_VER_35,
 144         RTL_GIGA_MAC_VER_36,
 145         RTL_GIGA_MAC_VER_37,
 146         RTL_GIGA_MAC_VER_38,
 147         RTL_GIGA_MAC_VER_39,
 148         RTL_GIGA_MAC_VER_40,
 149         RTL_GIGA_MAC_VER_41,
 150         RTL_GIGA_MAC_VER_42,
 151         RTL_GIGA_MAC_VER_43,
 152         RTL_GIGA_MAC_VER_44,
 153         RTL_GIGA_MAC_VER_45,
 154         RTL_GIGA_MAC_VER_46,
 155         RTL_GIGA_MAC_VER_47,
 156         RTL_GIGA_MAC_VER_48,
 157         RTL_GIGA_MAC_VER_49,
 158         RTL_GIGA_MAC_VER_50,
 159         RTL_GIGA_MAC_VER_51,
 160         RTL_GIGA_MAC_NONE   = 0xff,
 161 };
 162
 163 enum rtl_tx_desc_version {
 164         RTL_TD_0        = 0,
 165         RTL_TD_1        = 1,
 166 };
 167
 168 #define JUMBO_1K        ETH_DATA_LEN
 169 #define JUMBO_4K        (4*1024 - ETH_HLEN - 2)
 170 #define JUMBO_6K        (6*1024 - ETH_HLEN - 2)
 171 #define JUMBO_7K        (7*1024 - ETH_HLEN - 2)
 172 #define JUMBO_9K        (9*1024 - ETH_HLEN - 2)
 173
 174 #define _R(NAME,TD,FW,SZ,B) {   \
 175         .name = NAME,           \
 176         .txd_version = TD,      \
 177         .fw_name = FW,          \
 178         .jumbo_max = SZ,        \
 179         .jumbo_tx_csum = B      \
 180 }
 181
 182 static const struct {
 183         const char *name;
 184         enum rtl_tx_desc_version txd_version;
 185         const char *fw_name;
 186         u16 jumbo_max;
 187         bool jumbo_tx_csum;
 188 } rtl_chip_infos[] = {
 189         /* PCI devices. */
 190         [RTL_GIGA_MAC_VER_01] =
 191                 _R("RTL8169",           RTL_TD_0, NULL, JUMBO_7K, true),
 192         [RTL_GIGA_MAC_VER_02] =
 193                 _R("RTL8169s",          RTL_TD_0, NULL, JUMBO_7K, true),
 194         [RTL_GIGA_MAC_VER_03] =
 195                 _R("RTL8110s",          RTL_TD_0, NULL, JUMBO_7K, true),
 196         [RTL_GIGA_MAC_VER_04] =
 197                 _R("RTL8169sb/8110sb",  RTL_TD_0, NULL, JUMBO_7K, true),
 198         [RTL_GIGA_MAC_VER_05] =
 199                 _R("RTL8169sc/8110sc",  RTL_TD_0, NULL, JUMBO_7K, true),
 200         [RTL_GIGA_MAC_VER_06] =
 201                 _R("RTL8169sc/8110sc",  RTL_TD_0, NULL, JUMBO_7K, true),
 202         /* PCI-E devices. */
 203         [RTL_GIGA_MAC_VER_07] =
 204                 _R("RTL8102e",          RTL_TD_1, NULL, JUMBO_1K, true),
 205         [RTL_GIGA_MAC_VER_08] =
 206                 _R("RTL8102e",          RTL_TD_1, NULL, JUMBO_1K, true),
 207         [RTL_GIGA_MAC_VER_09] =
 208                 _R("RTL8102e",          RTL_TD_1, NULL, JUMBO_1K, true),
 209         [RTL_GIGA_MAC_VER_10] =
 210                 _R("RTL8101e",          RTL_TD_0, NULL, JUMBO_1K, true),
 211         [RTL_GIGA_MAC_VER_11] =
 212                 _R("RTL8168b/8111b",    RTL_TD_0, NULL, JUMBO_4K, false),
 213         [RTL_GIGA_MAC_VER_12] =
 214                 _R("RTL8168b/8111b",    RTL_TD_0, NULL, JUMBO_4K, false),
 215         [RTL_GIGA_MAC_VER_13] =
 216                 _R("RTL8101e",          RTL_TD_0, NULL, JUMBO_1K, true),
 217         [RTL_GIGA_MAC_VER_14] =
 218                 _R("RTL8100e",          RTL_TD_0, NULL, JUMBO_1K, true),
 219         [RTL_GIGA_MAC_VER_15] =
 220                 _R("RTL8100e",          RTL_TD_0, NULL, JUMBO_1K, true),
 221         [RTL_GIGA_MAC_VER_16] =
 222                 _R("RTL8101e",          RTL_TD_0, NULL, JUMBO_1K, true),
 223         [RTL_GIGA_MAC_VER_17] =
 224                 _R("RTL8168b/8111b",    RTL_TD_0, NULL, JUMBO_4K, false),
 225         [RTL_GIGA_MAC_VER_18] =
 226                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL, JUMBO_6K, false),
 227         [RTL_GIGA_MAC_VER_19] =
 228                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K, false),
 229         [RTL_GIGA_MAC_VER_20] =
 230                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K, false),
 231         [RTL_GIGA_MAC_VER_21] =
 232                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K, false),
 233         [RTL_GIGA_MAC_VER_22] =
 234                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K, false),
 235         [RTL_GIGA_MAC_VER_23] =
 236                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL, JUMBO_6K, false),
 237         [RTL_GIGA_MAC_VER_24] =
 238                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL, JUMBO_6K, false),
 239         [RTL_GIGA_MAC_VER_25] =
 240                 _R("RTL8168d/8111d",    RTL_TD_1, FIRMWARE_8168D_1,
 241                                                         JUMBO_9K, false),
 242         [RTL_GIGA_MAC_VER_26] =
 243                 _R("RTL8168d/8111d",    RTL_TD_1, FIRMWARE_8168D_2,
 244                                                         JUMBO_9K, false),
 245         [RTL_GIGA_MAC_VER_27] =
 246                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL, JUMBO_9K, false),
 247         [RTL_GIGA_MAC_VER_28] =
 248                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL, JUMBO_9K, false),
 249         [RTL_GIGA_MAC_VER_29] =
 250                 _R("RTL8105e",          RTL_TD_1, FIRMWARE_8105E_1,
 251                                                         JUMBO_1K, true),
 252         [RTL_GIGA_MAC_VER_30] =
 253                 _R("RTL8105e",          RTL_TD_1, FIRMWARE_8105E_1,
 254                                                         JUMBO_1K, true),
 255         [RTL_GIGA_MAC_VER_31] =
 256                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL, JUMBO_9K, false),
 257         [RTL_GIGA_MAC_VER_32] =
 258                 _R("RTL8168e/8111e",    RTL_TD_1, FIRMWARE_8168E_1,
 259                                                         JUMBO_9K, false),
 260         [RTL_GIGA_MAC_VER_33] =
 261                 _R("RTL8168e/8111e",    RTL_TD_1, FIRMWARE_8168E_2,
 262                                                         JUMBO_9K, false),
 263         [RTL_GIGA_MAC_VER_34] =
 264                 _R("RTL8168evl/8111evl",RTL_TD_1, FIRMWARE_8168E_3,
 265                                                         JUMBO_9K, false),
 266         [RTL_GIGA_MAC_VER_35] =
 267                 _R("RTL8168f/8111f",    RTL_TD_1, FIRMWARE_8168F_1,
 268                                                         JUMBO_9K, false),
 269         [RTL_GIGA_MAC_VER_36] =
 270                 _R("RTL8168f/8111f",    RTL_TD_1, FIRMWARE_8168F_2,
 271                                                         JUMBO_9K, false),
 272         [RTL_GIGA_MAC_VER_37] =
 273                 _R("RTL8402",           RTL_TD_1, FIRMWARE_8402_1,
 274                                                         JUMBO_1K, true),
 275         [RTL_GIGA_MAC_VER_38] =
 276                 _R("RTL8411",           RTL_TD_1, FIRMWARE_8411_1,
 277                                                         JUMBO_9K, false),
 278         [RTL_GIGA_MAC_VER_39] =
 279                 _R("RTL8106e",          RTL_TD_1, FIRMWARE_8106E_1,
 280                                                         JUMBO_1K, true),
 281         [RTL_GIGA_MAC_VER_40] =
 282                 _R("RTL8168g/8111g",    RTL_TD_1, FIRMWARE_8168G_2,
 283                                                         JUMBO_9K, false),
 284         [RTL_GIGA_MAC_VER_41] =
 285                 _R("RTL8168g/8111g",    RTL_TD_1, NULL, JUMBO_9K, false),
 286         [RTL_GIGA_MAC_VER_42] =
 287                 _R("RTL8168g/8111g",    RTL_TD_1, FIRMWARE_8168G_3,
 288                                                         JUMBO_9K, false),
 289         [RTL_GIGA_MAC_VER_43] =
 290                 _R("RTL8106e",          RTL_TD_1, FIRMWARE_8106E_2,
 291                                                         JUMBO_1K, true),
 292         [RTL_GIGA_MAC_VER_44] =
 293                 _R("RTL8411",           RTL_TD_1, FIRMWARE_8411_2,
 294                                                         JUMBO_9K, false),
 295         [RTL_GIGA_MAC_VER_45] =
 296                 _R("RTL8168h/8111h",    RTL_TD_1, FIRMWARE_8168H_1,
 297                                                         JUMBO_9K, false),
 298         [RTL_GIGA_MAC_VER_46] =
 299                 _R("RTL8168h/8111h",    RTL_TD_1, FIRMWARE_8168H_2,
 300                                                         JUMBO_9K, false),
 301         [RTL_GIGA_MAC_VER_47] =
 302                 _R("RTL8107e",          RTL_TD_1, FIRMWARE_8107E_1,
 303                                                         JUMBO_1K, false),
 304         [RTL_GIGA_MAC_VER_48] =
 305                 _R("RTL8107e",          RTL_TD_1, FIRMWARE_8107E_2,
 306                                                         JUMBO_1K, false),
 307         [RTL_GIGA_MAC_VER_49] =
 308                 _R("RTL8168ep/8111ep",  RTL_TD_1, NULL,
 309                                                         JUMBO_9K, false),
 310         [RTL_GIGA_MAC_VER_50] =
 311                 _R("RTL8168ep/8111ep",  RTL_TD_1, NULL,
 312                                                         JUMBO_9K, false),
 313         [RTL_GIGA_MAC_VER_51] =
 314                 _R("RTL8168ep/8111ep",  RTL_TD_1, NULL,
 315                                                         JUMBO_9K, false),
 316 };
 317 #undef _R
 318
 319 enum cfg_version {
 320         RTL_CFG_0 = 0x00,
 321         RTL_CFG_1,
 322         RTL_CFG_2
 323 };
 324
 325 static const struct pci_device_id rtl8169_pci_tbl[] = {
 326         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8129), 0, 0, RTL_CFG_0 },
 327         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8136), 0, 0, RTL_CFG_2 },
 328         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8161), 0, 0, RTL_CFG_1 },
 329         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8167), 0, 0, RTL_CFG_0 },
 330         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8168), 0, 0, RTL_CFG_1 },
 331         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8169), 0, 0, RTL_CFG_0 },
 332         { PCI_VENDOR_ID_DLINK,                  0x4300,
 333                 PCI_VENDOR_ID_DLINK, 0x4b10,             0, 0, RTL_CFG_1 },
 334         { PCI_DEVICE(PCI_VENDOR_ID_DLINK,       0x4300), 0, 0, RTL_CFG_0 },
 335         { PCI_DEVICE(PCI_VENDOR_ID_DLINK,       0x4302), 0, 0, RTL_CFG_0 },
 336         { PCI_DEVICE(PCI_VENDOR_ID_AT,          0xc107), 0, 0, RTL_CFG_0 },
 337         { PCI_DEVICE(0x16ec,                    0x0116), 0, 0, RTL_CFG_0 },
 338         { PCI_VENDOR_ID_LINKSYS,                0x1032,
 339                 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
 340         { 0x0001,                               0x8168,
 341                 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
 342         {0,},
 343 };
 344
 345 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
 346
 347 static int use_dac = -1;
 348 static struct {
 349         u32 msg_enable;
 350 } debug = { -1 };
 351
 352 enum rtl_registers {
 353         MAC0            = 0,    /* Ethernet hardware address. */
 354         MAC4            = 4,
 355         MAR0            = 8,    /* Multicast filter. */
 356         CounterAddrLow          = 0x10,
 357         CounterAddrHigh         = 0x14,
 358         TxDescStartAddrLow      = 0x20,
 359         TxDescStartAddrHigh     = 0x24,
 360         TxHDescStartAddrLow     = 0x28,
 361         TxHDescStartAddrHigh    = 0x2c,
 362         FLASH           = 0x30,
 363         ERSR            = 0x36,
 364         ChipCmd         = 0x37,
 365         TxPoll          = 0x38,
 366         IntrMask        = 0x3c,
 367         IntrStatus      = 0x3e,
 368
 369         TxConfig        = 0x40,
 370 #define TXCFG_AUTO_FIFO                 (1 << 7)        /* 8111e-vl */
 371 #define TXCFG_EMPTY                     (1 << 11)       /* 8111e-vl */
 372
 373         RxConfig        = 0x44,
 374 #define RX128_INT_EN                    (1 << 15)       /* 8111c and later */
 375 #define RX_MULTI_EN                     (1 << 14)       /* 8111c only */
 376 #define RXCFG_FIFO_SHIFT                13
 377                                         /* No threshold before first PCI xfer */
 378 #define RX_FIFO_THRESH                  (7 << RXCFG_FIFO_SHIFT)
 379 #define RX_EARLY_OFF                    (1 << 11)
 380 #define RXCFG_DMA_SHIFT                 8
 381                                         /* Unlimited maximum PCI burst. */
 382 #define RX_DMA_BURST                    (7 << RXCFG_DMA_SHIFT)
 383
 384         RxMissed        = 0x4c,
 385         Cfg9346         = 0x50,
 386         Config0         = 0x51,
 387         Config1         = 0x52,
 388         Config2         = 0x53,
 389 #define PME_SIGNAL                      (1 << 5)        /* 8168c and later */
 390
 391         Config3         = 0x54,
 392         Config4         = 0x55,
 393         Config5         = 0x56,
 394         MultiIntr       = 0x5c,
 395         PHYAR           = 0x60,
 396         PHYstatus       = 0x6c,
 397         RxMaxSize       = 0xda,
 398         CPlusCmd        = 0xe0,
 399         IntrMitigate    = 0xe2,
 400
 401 #define RTL_COALESCE_MASK       0x0f
 402 #define RTL_COALESCE_SHIFT      4
 403 #define RTL_COALESCE_T_MAX      (RTL_COALESCE_MASK)
 404 #define RTL_COALESCE_FRAME_MAX  (RTL_COALESCE_MASK << 2)
 405
 406         RxDescAddrLow   = 0xe4,
 407         RxDescAddrHigh  = 0xe8,
 408         EarlyTxThres    = 0xec, /* 8169. Unit of 32 bytes. */
 409
 410 #define NoEarlyTx       0x3f    /* Max value : no early transmit. */
 411
 412         MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
 413
 414 #define TxPacketMax     (8064 >> 7)
 415 #define EarlySize       0x27
 416
 417         FuncEvent       = 0xf0,
 418         FuncEventMask   = 0xf4,
 419         FuncPresetState = 0xf8,
 420         IBCR0           = 0xf8,
 421         IBCR2           = 0xf9,
 422         IBIMR0          = 0xfa,
 423         IBISR0          = 0xfb,
 424         FuncForceEvent  = 0xfc,
 425 };
 426
 427 enum rtl8110_registers {
 428         TBICSR                  = 0x64,
 429         TBI_ANAR                = 0x68,
 430         TBI_LPAR                = 0x6a,
 431 };
 432
 433 enum rtl8168_8101_registers {
 434         CSIDR                   = 0x64,
 435         CSIAR                   = 0x68,
 436 #define CSIAR_FLAG                      0x80000000
 437 #define CSIAR_WRITE_CMD                 0x80000000
 438 #define CSIAR_BYTE_ENABLE               0x0f
 439 #define CSIAR_BYTE_ENABLE_SHIFT         12
 440 #define CSIAR_ADDR_MASK                 0x0fff
 441 #define CSIAR_FUNC_CARD                 0x00000000
 442 #define CSIAR_FUNC_SDIO                 0x00010000
 443 #define CSIAR_FUNC_NIC                  0x00020000
 444 #define CSIAR_FUNC_NIC2                 0x00010000
 445         PMCH                    = 0x6f,
 446         EPHYAR                  = 0x80,
 447 #define EPHYAR_FLAG                     0x80000000
 448 #define EPHYAR_WRITE_CMD                0x80000000
 449 #define EPHYAR_REG_MASK                 0x1f
 450 #define EPHYAR_REG_SHIFT                16
 451 #define EPHYAR_DATA_MASK                0xffff
 452         DLLPR                   = 0xd0,
 453 #define PFM_EN                          (1 << 6)
 454 #define TX_10M_PS_EN                    (1 << 7)
 455         DBG_REG                 = 0xd1,
 456 #define FIX_NAK_1                       (1 << 4)
 457 #define FIX_NAK_2                       (1 << 3)
 458         TWSI                    = 0xd2,
 459         MCU                     = 0xd3,
 460 #define NOW_IS_OOB                      (1 << 7)
 461 #define TX_EMPTY                        (1 << 5)
 462 #define RX_EMPTY                        (1 << 4)
 463 #define RXTX_EMPTY                      (TX_EMPTY | RX_EMPTY)
 464 #define EN_NDP                          (1 << 3)
 465 #define EN_OOB_RESET                    (1 << 2)
 466 #define LINK_LIST_RDY                   (1 << 1)
 467         EFUSEAR                 = 0xdc,
 468 #define EFUSEAR_FLAG                    0x80000000
 469 #define EFUSEAR_WRITE_CMD               0x80000000
 470 #define EFUSEAR_READ_CMD                0x00000000
 471 #define EFUSEAR_REG_MASK                0x03ff
 472 #define EFUSEAR_REG_SHIFT               8
 473 #define EFUSEAR_DATA_MASK               0xff
 474         MISC_1                  = 0xf2,
 475 #define PFM_D3COLD_EN                   (1 << 6)
 476 };
 477
 478 enum rtl8168_registers {
 479         LED_FREQ                = 0x1a,
 480         EEE_LED                 = 0x1b,
 481         ERIDR                   = 0x70,
 482         ERIAR                   = 0x74,
 483 #define ERIAR_FLAG                      0x80000000
 484 #define ERIAR_WRITE_CMD                 0x80000000
 485 #define ERIAR_READ_CMD                  0x00000000
 486 #define ERIAR_ADDR_BYTE_ALIGN           4
 487 #define ERIAR_TYPE_SHIFT                16
 488 #define ERIAR_EXGMAC                    (0x00 << ERIAR_TYPE_SHIFT)
 489 #define ERIAR_MSIX                      (0x01 << ERIAR_TYPE_SHIFT)
 490 #define ERIAR_ASF                       (0x02 << ERIAR_TYPE_SHIFT)
 491 #define ERIAR_OOB                       (0x02 << ERIAR_TYPE_SHIFT)
 492 #define ERIAR_MASK_SHIFT                12
 493 #define ERIAR_MASK_0001                 (0x1 << ERIAR_MASK_SHIFT)
 494 #define ERIAR_MASK_0011                 (0x3 << ERIAR_MASK_SHIFT)
 495 #define ERIAR_MASK_0100                 (0x4 << ERIAR_MASK_SHIFT)
 496 #define ERIAR_MASK_0101                 (0x5 << ERIAR_MASK_SHIFT)
 497 #define ERIAR_MASK_1111                 (0xf << ERIAR_MASK_SHIFT)
 498         EPHY_RXER_NUM           = 0x7c,
 499         OCPDR                   = 0xb0, /* OCP GPHY access */
 500 #define OCPDR_WRITE_CMD                 0x80000000
 501 #define OCPDR_READ_CMD                  0x00000000
 502 #define OCPDR_REG_MASK                  0x7f
 503 #define OCPDR_GPHY_REG_SHIFT            16
 504 #define OCPDR_DATA_MASK                 0xffff
 505         OCPAR                   = 0xb4,
 506 #define OCPAR_FLAG                      0x80000000
 507 #define OCPAR_GPHY_WRITE_CMD            0x8000f060
 508 #define OCPAR_GPHY_READ_CMD             0x0000f060
 509         GPHY_OCP                = 0xb8,
 510         RDSAR1                  = 0xd0, /* 8168c only. Undocumented on 8168dp */
 511         MISC                    = 0xf0, /* 8168e only. */
 512 #define TXPLA_RST                       (1 << 29)
 513 #define DISABLE_LAN_EN                  (1 << 23) /* Enable GPIO pin */
 514 #define PWM_EN                          (1 << 22)
 515 #define RXDV_GATED_EN                   (1 << 19)
 516 #define EARLY_TALLY_EN                  (1 << 16)
 517 };
 518
 519 enum rtl_register_content {
 520         /* InterruptStatusBits */
 521         SYSErr          = 0x8000,
 522         PCSTimeout      = 0x4000,
 523         SWInt           = 0x0100,
 524         TxDescUnavail   = 0x0080,
 525         RxFIFOOver      = 0x0040,
 526         LinkChg         = 0x0020,
 527         RxOverflow      = 0x0010,
 528         TxErr           = 0x0008,
 529         TxOK            = 0x0004,
 530         RxErr           = 0x0002,
 531         RxOK            = 0x0001,
 532
 533         /* RxStatusDesc */
 534         RxBOVF  = (1 << 24),
 535         RxFOVF  = (1 << 23),
 536         RxRWT   = (1 << 22),
 537         RxRES   = (1 << 21),
 538         RxRUNT  = (1 << 20),
 539         RxCRC   = (1 << 19),
 540
 541         /* ChipCmdBits */
 542         StopReq         = 0x80,
 543         CmdReset        = 0x10,
 544         CmdRxEnb        = 0x08,
 545         CmdTxEnb        = 0x04,
 546         RxBufEmpty      = 0x01,
 547
 548         /* TXPoll register p.5 */
 549         HPQ             = 0x80,         /* Poll cmd on the high prio queue */
 550         NPQ             = 0x40,         /* Poll cmd on the low prio queue */
 551         FSWInt          = 0x01,         /* Forced software interrupt */
 552
 553         /* Cfg9346Bits */
 554         Cfg9346_Lock    = 0x00,
 555         Cfg9346_Unlock  = 0xc0,
 556
 557         /* rx_mode_bits */
 558         AcceptErr       = 0x20,
 559         AcceptRunt      = 0x10,
 560         AcceptBroadcast = 0x08,
 561         AcceptMulticast = 0x04,
 562         AcceptMyPhys    = 0x02,
 563         AcceptAllPhys   = 0x01,
 564 #define RX_CONFIG_ACCEPT_MASK           0x3f
 565
 566         /* TxConfigBits */
 567         TxInterFrameGapShift = 24,
 568         TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
 569
 570         /* Config1 register p.24 */
 571         LEDS1           = (1 << 7),
 572         LEDS0           = (1 << 6),
 573         Speed_down      = (1 << 4),
 574         MEMMAP          = (1 << 3),
 575         IOMAP           = (1 << 2),
 576         VPD             = (1 << 1),
 577         PMEnable        = (1 << 0),     /* Power Management Enable */
 578
 579         /* Config2 register p. 25 */
 580         ClkReqEn        = (1 << 7),     /* Clock Request Enable */
 581         MSIEnable       = (1 << 5),     /* 8169 only. Reserved in the 8168. */
 582         PCI_Clock_66MHz = 0x01,
 583         PCI_Clock_33MHz = 0x00,
 584
 585         /* Config3 register p.25 */
 586         MagicPacket     = (1 << 5),     /* Wake up when receives a Magic Packet */
 587         LinkUp          = (1 << 4),     /* Wake up when the cable connection is re-established */
 588         Jumbo_En0       = (1 << 2),     /* 8168 only. Reserved in the 8168b */
 589         Rdy_to_L23      = (1 << 1),     /* L23 Enable */
 590         Beacon_en       = (1 << 0),     /* 8168 only. Reserved in the 8168b */
 591
 592         /* Config4 register */
 593         Jumbo_En1       = (1 << 1),     /* 8168 only. Reserved in the 8168b */
 594
 595         /* Config5 register p.27 */
 596         BWF             = (1 << 6),     /* Accept Broadcast wakeup frame */
 597         MWF             = (1 << 5),     /* Accept Multicast wakeup frame */
 598         UWF             = (1 << 4),     /* Accept Unicast wakeup frame */
 599         Spi_en          = (1 << 3),
 600         LanWake         = (1 << 1),     /* LanWake enable/disable */
 601         PMEStatus       = (1 << 0),     /* PME status can be reset by PCI RST# */
 602         ASPM_en         = (1 << 0),     /* ASPM enable */
 603
 604         /* TBICSR p.28 */
 605         TBIReset        = 0x80000000,
 606         TBILoopback     = 0x40000000,
 607         TBINwEnable     = 0x20000000,
 608         TBINwRestart    = 0x10000000,
 609         TBILinkOk       = 0x02000000,
 610         TBINwComplete   = 0x01000000,
 611
 612         /* CPlusCmd p.31 */
 613         EnableBist      = (1 << 15),    // 8168 8101
 614         Mac_dbgo_oe     = (1 << 14),    // 8168 8101
 615         Normal_mode     = (1 << 13),    // unused
 616         Force_half_dup  = (1 << 12),    // 8168 8101
 617         Force_rxflow_en = (1 << 11),    // 8168 8101
 618         Force_txflow_en = (1 << 10),    // 8168 8101
 619         Cxpl_dbg_sel    = (1 << 9),     // 8168 8101
 620         ASF             = (1 << 8),     // 8168 8101
 621         PktCntrDisable  = (1 << 7),     // 8168 8101
 622         Mac_dbgo_sel    = 0x001c,       // 8168
 623         RxVlan          = (1 << 6),
 624         RxChkSum        = (1 << 5),
 625         PCIDAC          = (1 << 4),
 626         PCIMulRW        = (1 << 3),
 627         INTT_0          = 0x0000,       // 8168
 628         INTT_1          = 0x0001,       // 8168
 629         INTT_2          = 0x0002,       // 8168
 630         INTT_3          = 0x0003,       // 8168
 631
 632         /* rtl8169_PHYstatus */
 633         TBI_Enable      = 0x80,
 634         TxFlowCtrl      = 0x40,
 635         RxFlowCtrl      = 0x20,
 636         _1000bpsF       = 0x10,
 637         _100bps         = 0x08,
 638         _10bps          = 0x04,
 639         LinkStatus      = 0x02,
 640         FullDup         = 0x01,
 641
 642         /* _TBICSRBit */
 643         TBILinkOK       = 0x02000000,
 644
 645         /* ResetCounterCommand */
 646         CounterReset    = 0x1,
 647
 648         /* DumpCounterCommand */
 649         CounterDump     = 0x8,
 650
 651         /* magic enable v2 */
 652         MagicPacket_v2  = (1 << 16),    /* Wake up when receives a Magic Packet */
 653 };
 654
 655 enum rtl_desc_bit {
 656         /* First doubleword. */
 657         DescOwn         = (1 << 31), /* Descriptor is owned by NIC */
 658         RingEnd         = (1 << 30), /* End of descriptor ring */
 659         FirstFrag       = (1 << 29), /* First segment of a packet */
 660         LastFrag        = (1 << 28), /* Final segment of a packet */
 661 };
 662
 663 /* Generic case. */
 664 enum rtl_tx_desc_bit {
 665         /* First doubleword. */
 666         TD_LSO          = (1 << 27),            /* Large Send Offload */
 667 #define TD_MSS_MAX                      0x07ffu /* MSS value */
 668
 669         /* Second doubleword. */
 670         TxVlanTag       = (1 << 17),            /* Add VLAN tag */
 671 };
 672
 673 /* 8169, 8168b and 810x except 8102e. */
 674 enum rtl_tx_desc_bit_0 {
 675         /* First doubleword. */
 676 #define TD0_MSS_SHIFT                   16      /* MSS position (11 bits) */
 677         TD0_TCP_CS      = (1 << 16),            /* Calculate TCP/IP checksum */
 678         TD0_UDP_CS      = (1 << 17),            /* Calculate UDP/IP checksum */
 679         TD0_IP_CS       = (1 << 18),            /* Calculate IP checksum */
 680 };
 681
 682 /* 8102e, 8168c and beyond. */
 683 enum rtl_tx_desc_bit_1 {
 684         /* First doubleword. */
 685         TD1_GTSENV4     = (1 << 26),            /* Giant Send for IPv4 */
 686         TD1_GTSENV6     = (1 << 25),            /* Giant Send for IPv6 */
 687 #define GTTCPHO_SHIFT                   18
 688 #define GTTCPHO_MAX                     0x7fU
 689
 690         /* Second doubleword. */
 691 #define TCPHO_SHIFT                     18
 692 #define TCPHO_MAX                       0x3ffU
 693 #define TD1_MSS_SHIFT                   18      /* MSS position (11 bits) */
 694         TD1_IPv6_CS     = (1 << 28),            /* Calculate IPv6 checksum */
 695         TD1_IPv4_CS     = (1 << 29),            /* Calculate IPv4 checksum */
 696         TD1_TCP_CS      = (1 << 30),            /* Calculate TCP/IP checksum */
 697         TD1_UDP_CS      = (1 << 31),            /* Calculate UDP/IP checksum */
 698 };
 699
 700 enum rtl_rx_desc_bit {
 701         /* Rx private */
 702         PID1            = (1 << 18), /* Protocol ID bit 1/2 */
 703         PID0            = (1 << 17), /* Protocol ID bit 0/2 */
 704
 705 #define RxProtoUDP      (PID1)
 706 #define RxProtoTCP      (PID0)
 707 #define RxProtoIP       (PID1 | PID0)
 708 #define RxProtoMask     RxProtoIP
 709
 710         IPFail          = (1 << 16), /* IP checksum failed */
 711         UDPFail         = (1 << 15), /* UDP/IP checksum failed */
 712         TCPFail         = (1 << 14), /* TCP/IP checksum failed */
 713         RxVlanTag       = (1 << 16), /* VLAN tag available */
 714 };
 715
 716 #define RsvdMask        0x3fffc000
 717
 718 struct TxDesc {
 719         __le32 opts1;
 720         __le32 opts2;
 721         __le64 addr;
 722 };
 723
 724 struct RxDesc {
 725         __le32 opts1;
 726         __le32 opts2;
 727         __le64 addr;
 728 };
 729
 730 struct ring_info {
 731         struct sk_buff  *skb;
 732         u32             len;
 733         u8              __pad[sizeof(void *) - sizeof(u32)];
 734 };
 735
 736 struct rtl8169_counters {
 737         __le64  tx_packets;
 738         __le64  rx_packets;
 739         __le64  tx_errors;
 740         __le32  rx_errors;
 741         __le16  rx_missed;
 742         __le16  align_errors;
 743         __le32  tx_one_collision;
 744         __le32  tx_multi_collision;
 745         __le64  rx_unicast;
 746         __le64  rx_broadcast;
 747         __le32  rx_multicast;
 748         __le16  tx_aborted;
 749         __le16  tx_underun;
 750 };
 751
 752 struct rtl8169_tc_offsets {
 753         bool    inited;
 754         __le64  tx_errors;
 755         __le32  tx_multi_collision;
 756         __le16  tx_aborted;
 757 };
 758
 759 enum rtl_flag {
 760         RTL_FLAG_TASK_ENABLED,
 761         RTL_FLAG_TASK_SLOW_PENDING,
 762         RTL_FLAG_TASK_RESET_PENDING,
 763         RTL_FLAG_TASK_PHY_PENDING,
 764         RTL_FLAG_MAX
 765 };
 766
 767 struct rtl8169_stats {
 768         u64                     packets;
 769         u64                     bytes;
 770         struct u64_stats_sync   syncp;
 771 };
 772
 773 struct rtl8169_private {
 774         void __iomem *mmio_addr;        /* memory map physical address */
 775         struct pci_dev *pci_dev;
 776         struct net_device *dev;
 777         struct napi_struct napi;
 778         u32 msg_enable;
 779         u16 txd_version;
 780         u16 mac_version;
 781         u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
 782         u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
 783         u32 dirty_tx;
 784         struct rtl8169_stats rx_stats;
 785         struct rtl8169_stats tx_stats;
 786         struct TxDesc *TxDescArray;     /* 256-aligned Tx descriptor ring */
 787         struct RxDesc *RxDescArray;     /* 256-aligned Rx descriptor ring */
 788         dma_addr_t TxPhyAddr;
 789         dma_addr_t RxPhyAddr;
 790         void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
 791         struct ring_info tx_skb[NUM_TX_DESC];   /* Tx data buffers */
 792         struct timer_list timer;
 793         u16 cp_cmd;
 794
 795         u16 event_slow;
 796         const struct rtl_coalesce_info *coalesce_info;
 797
 798         struct mdio_ops {
 799                 void (*write)(struct rtl8169_private *, int, int);
 800                 int (*read)(struct rtl8169_private *, int);
 801         } mdio_ops;
 802
 803         struct pll_power_ops {
 804                 void (*down)(struct rtl8169_private *);
 805                 void (*up)(struct rtl8169_private *);
 806         } pll_power_ops;
 807
 808         struct jumbo_ops {
 809                 void (*enable)(struct rtl8169_private *);
 810                 void (*disable)(struct rtl8169_private *);
 811         } jumbo_ops;
 812
 813         struct csi_ops {
 814                 void (*write)(struct rtl8169_private *, int, int);
 815                 u32 (*read)(struct rtl8169_private *, int);
 816         } csi_ops;
 817
 818         int (*set_speed)(struct net_device *, u8 aneg, u16 sp, u8 dpx, u32 adv);
 819         int (*get_link_ksettings)(struct net_device *,
 820                                   struct ethtool_link_ksettings *);
 821         void (*phy_reset_enable)(struct rtl8169_private *tp);
 822         void (*hw_start)(struct rtl8169_private *tp);
 823         unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
 824         unsigned int (*link_ok)(struct rtl8169_private *tp);
 825         int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
 826         bool (*tso_csum)(struct rtl8169_private *, struct sk_buff *, u32 *);
 827
 828         struct {
 829                 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
 830                 struct mutex mutex;
 831                 struct work_struct work;
 832         } wk;
 833
 834         struct mii_if_info mii;
 835         dma_addr_t counters_phys_addr;
 836         struct rtl8169_counters *counters;
 837         struct rtl8169_tc_offsets tc_offset;
 838         u32 saved_wolopts;
 839         u32 opts1_mask;
 840
 841         struct rtl_fw {
 842                 const struct firmware *fw;
 843
 844 #define RTL_VER_SIZE            32
 845
 846                 char version[RTL_VER_SIZE];
 847
 848                 struct rtl_fw_phy_action {
 849                         __le32 *code;
 850                         size_t size;
 851                 } phy_action;
 852         } *rtl_fw;
 853 #define RTL_FIRMWARE_UNKNOWN    ERR_PTR(-EAGAIN)
 854
 855         u32 ocp_base;
 856 };
 857
 858 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
 859 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
 860 module_param(use_dac, int, 0);
 861 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
 862 module_param_named(debug, debug.msg_enable, int, 0);
 863 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
 864 MODULE_LICENSE("GPL");
 865 MODULE_VERSION(RTL8169_VERSION);
 866 MODULE_FIRMWARE(FIRMWARE_8168D_1);
 867 MODULE_FIRMWARE(FIRMWARE_8168D_2);
 868 MODULE_FIRMWARE(FIRMWARE_8168E_1);
 869 MODULE_FIRMWARE(FIRMWARE_8168E_2);
 870 MODULE_FIRMWARE(FIRMWARE_8168E_3);
 871 MODULE_FIRMWARE(FIRMWARE_8105E_1);
 872 MODULE_FIRMWARE(FIRMWARE_8168F_1);
 873 MODULE_FIRMWARE(FIRMWARE_8168F_2);
 874 MODULE_FIRMWARE(FIRMWARE_8402_1);
 875 MODULE_FIRMWARE(FIRMWARE_8411_1);
 876 MODULE_FIRMWARE(FIRMWARE_8411_2);
 877 MODULE_FIRMWARE(FIRMWARE_8106E_1);
 878 MODULE_FIRMWARE(FIRMWARE_8106E_2);
 879 MODULE_FIRMWARE(FIRMWARE_8168G_2);
 880 MODULE_FIRMWARE(FIRMWARE_8168G_3);
 881 MODULE_FIRMWARE(FIRMWARE_8168H_1);
 882 MODULE_FIRMWARE(FIRMWARE_8168H_2);
 883 MODULE_FIRMWARE(FIRMWARE_8107E_1);
 884 MODULE_FIRMWARE(FIRMWARE_8107E_2);
 885
 886 static inline struct device *tp_to_dev(struct rtl8169_private *tp)
 887 {
 888         return &tp->pci_dev->dev;
 889 }
 890
 891 static void rtl_lock_work(struct rtl8169_private *tp)
 892 {
 893         mutex_lock(&tp->wk.mutex);
 894 }
 895
 896 static void rtl_unlock_work(struct rtl8169_private *tp)
 897 {
 898         mutex_unlock(&tp->wk.mutex);
 899 }
 900
 901 static void rtl_tx_performance_tweak(struct rtl8169_private *tp, u16 force)
 902 {
 903         pcie_capability_clear_and_set_word(tp->pci_dev, PCI_EXP_DEVCTL,
 904                                            PCI_EXP_DEVCTL_READRQ, force);
 905 }
 906
 907 struct rtl_cond {
 908         bool (*check)(struct rtl8169_private *);
 909         const char *msg;
 910 };
 911
 912 static void rtl_udelay(unsigned int d)
 913 {
 914         udelay(d);
 915 }
 916
 917 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,
 918                           void (*delay)(unsigned int), unsigned int d, int n,
 919                           bool high)
 920 {
 921         int i;
 922
 923         for (i = 0; i < n; i++) {
 924                 delay(d);
 925                 if (c->check(tp) == high)
 926                         return true;
 927         }
 928         netif_err(tp, drv, tp->dev, "%s == %d (loop: %d, delay: %d).\n",
 929                   c->msg, !high, n, d);
 930         return false;
 931 }
 932
 933 static bool rtl_udelay_loop_wait_high(struct rtl8169_private *tp,
 934                                       const struct rtl_cond *c,
 935                                       unsigned int d, int n)
 936 {
 937         return rtl_loop_wait(tp, c, rtl_udelay, d, n, true);
 938 }
 939
 940 static bool rtl_udelay_loop_wait_low(struct rtl8169_private *tp,
 941                                      const struct rtl_cond *c,
 942                                      unsigned int d, int n)
 943 {
 944         return rtl_loop_wait(tp, c, rtl_udelay, d, n, false);
 945 }
 946
 947 static bool rtl_msleep_loop_wait_high(struct rtl8169_private *tp,
 948                                       const struct rtl_cond *c,
 949                                       unsigned int d, int n)
 950 {
 951         return rtl_loop_wait(tp, c, msleep, d, n, true);
 952 }
 953
 954 static bool rtl_msleep_loop_wait_low(struct rtl8169_private *tp,
 955                                      const struct rtl_cond *c,
 956                                      unsigned int d, int n)
 957 {
 958         return rtl_loop_wait(tp, c, msleep, d, n, false);
 959 }
 960
 961 #define DECLARE_RTL_COND(name)                          \
 962 static bool name ## _check(struct rtl8169_private *);   \
 963                                                         \
 964 static const struct rtl_cond name = {                   \
 965         .check  = name ## _check,                       \
 966         .msg    = #name                                 \
 967 };                                                      \
 968                                                         \
 969 static bool name ## _check(struct rtl8169_private *tp)
 970
 971 static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg)
 972 {
 973         if (reg & 0xffff0001) {
 974                 netif_err(tp, drv, tp->dev, "Invalid ocp reg %x!\n", reg);
 975                 return true;
 976         }
 977         return false;
 978 }
 979
 980 DECLARE_RTL_COND(rtl_ocp_gphy_cond)
 981 {
 982         return RTL_R32(tp, GPHY_OCP) & OCPAR_FLAG;
 983 }
 984
 985 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
 986 {
 987         if (rtl_ocp_reg_failure(tp, reg))
 988                 return;
 989
 990         RTL_W32(tp, GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);
 991
 992         rtl_udelay_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);
 993 }
 994
 995 static u16 r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
 996 {
 997         if (rtl_ocp_reg_failure(tp, reg))
 998                 return 0;
 999
1000         RTL_W32(tp, GPHY_OCP, reg << 15);
1001
1002         return rtl_udelay_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?
1003                 (RTL_R32(tp, GPHY_OCP) & 0xffff) : ~0;
1004 }
1005
1006 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
1007 {
1008         if (rtl_ocp_reg_failure(tp, reg))
1009                 return;
1010
1011         RTL_W32(tp, OCPDR, OCPAR_FLAG | (reg << 15) | data);
1012 }
1013
1014 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
1015 {
1016         if (rtl_ocp_reg_failure(tp, reg))
1017                 return 0;
1018
1019         RTL_W32(tp, OCPDR, reg << 15);
1020
1021         return RTL_R32(tp, OCPDR);
1022 }
1023
1024 #define OCP_STD_PHY_BASE        0xa400
1025
1026 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)
1027 {
1028         if (reg == 0x1f) {
1029                 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;
1030                 return;
1031         }
1032
1033         if (tp->ocp_base != OCP_STD_PHY_BASE)
1034                 reg -= 0x10;
1035
1036         r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);
1037 }
1038
1039 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)
1040 {
1041         if (tp->ocp_base != OCP_STD_PHY_BASE)
1042                 reg -= 0x10;
1043
1044         return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);
1045 }
1046
1047 static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value)
1048 {
1049         if (reg == 0x1f) {
1050                 tp->ocp_base = value << 4;
1051                 return;
1052         }
1053
1054         r8168_mac_ocp_write(tp, tp->ocp_base + reg, value);
1055 }
1056
1057 static int mac_mcu_read(struct rtl8169_private *tp, int reg)
1058 {
1059         return r8168_mac_ocp_read(tp, tp->ocp_base + reg);
1060 }
1061
1062 DECLARE_RTL_COND(rtl_phyar_cond)
1063 {
1064         return RTL_R32(tp, PHYAR) & 0x80000000;
1065 }
1066
1067 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)
1068 {
1069         RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
1070
1071         rtl_udelay_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);
1072         /*
1073          * According to hardware specs a 20us delay is required after write
1074          * complete indication, but before sending next command.
1075          */
1076         udelay(20);
1077 }
1078
1079 static int r8169_mdio_read(struct rtl8169_private *tp, int reg)
1080 {
1081         int value;
1082
1083         RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16);
1084
1085         value = rtl_udelay_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?
1086                 RTL_R32(tp, PHYAR) & 0xffff : ~0;
1087
1088         /*
1089          * According to hardware specs a 20us delay is required after read
1090          * complete indication, but before sending next command.
1091          */
1092         udelay(20);
1093
1094         return value;
1095 }
1096
1097 DECLARE_RTL_COND(rtl_ocpar_cond)
1098 {
1099         return RTL_R32(tp, OCPAR) & OCPAR_FLAG;
1100 }
1101
1102 static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data)
1103 {
1104         RTL_W32(tp, OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
1105         RTL_W32(tp, OCPAR, OCPAR_GPHY_WRITE_CMD);
1106         RTL_W32(tp, EPHY_RXER_NUM, 0);
1107
1108         rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100);
1109 }
1110
1111 static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value)
1112 {
1113         r8168dp_1_mdio_access(tp, reg,
1114                               OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK));
1115 }
1116
1117 static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg)
1118 {
1119         r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD);
1120
1121         mdelay(1);
1122         RTL_W32(tp, OCPAR, OCPAR_GPHY_READ_CMD);
1123         RTL_W32(tp, EPHY_RXER_NUM, 0);
1124
1125         return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ?
1126                 RTL_R32(tp, OCPDR) & OCPDR_DATA_MASK : ~0;
1127 }
1128
1129 #define R8168DP_1_MDIO_ACCESS_BIT       0x00020000
1130
1131 static void r8168dp_2_mdio_start(struct rtl8169_private *tp)
1132 {
1133         RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
1134 }
1135
1136 static void r8168dp_2_mdio_stop(struct rtl8169_private *tp)
1137 {
1138         RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
1139 }
1140
1141 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)
1142 {
1143         r8168dp_2_mdio_start(tp);
1144
1145         r8169_mdio_write(tp, reg, value);
1146
1147         r8168dp_2_mdio_stop(tp);
1148 }
1149
1150 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)
1151 {
1152         int value;
1153
1154         r8168dp_2_mdio_start(tp);
1155
1156         value = r8169_mdio_read(tp, reg);
1157
1158         r8168dp_2_mdio_stop(tp);
1159
1160         return value;
1161 }
1162
1163 static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
1164 {
1165         tp->mdio_ops.write(tp, location, val);
1166 }
1167
1168 static int rtl_readphy(struct rtl8169_private *tp, int location)
1169 {
1170         return tp->mdio_ops.read(tp, location);
1171 }
1172
1173 static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
1174 {
1175         rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
1176 }
1177
1178 static void rtl_w0w1_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
1179 {
1180         int val;
1181
1182         val = rtl_readphy(tp, reg_addr);
1183         rtl_writephy(tp, reg_addr, (val & ~m) | p);
1184 }
1185
1186 static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
1187                            int val)
1188 {
1189         struct rtl8169_private *tp = netdev_priv(dev);
1190
1191         rtl_writephy(tp, location, val);
1192 }
1193
1194 static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
1195 {
1196         struct rtl8169_private *tp = netdev_priv(dev);
1197
1198         return rtl_readphy(tp, location);
1199 }
1200
1201 DECLARE_RTL_COND(rtl_ephyar_cond)
1202 {
1203         return RTL_R32(tp, EPHYAR) & EPHYAR_FLAG;
1204 }
1205
1206 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)
1207 {
1208         RTL_W32(tp, EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1209                 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1210
1211         rtl_udelay_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);
1212
1213         udelay(10);
1214 }
1215
1216 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)
1217 {
1218         RTL_W32(tp, EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1219
1220         return rtl_udelay_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?
1221                 RTL_R32(tp, EPHYAR) & EPHYAR_DATA_MASK : ~0;
1222 }
1223
1224 DECLARE_RTL_COND(rtl_eriar_cond)
1225 {
1226         return RTL_R32(tp, ERIAR) & ERIAR_FLAG;
1227 }
1228
1229 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1230                           u32 val, int type)
1231 {
1232         BUG_ON((addr & 3) || (mask == 0));
1233         RTL_W32(tp, ERIDR, val);
1234         RTL_W32(tp, ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
1235
1236         rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);
1237 }
1238
1239 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
1240 {
1241         RTL_W32(tp, ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
1242
1243         return rtl_udelay_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?
1244                 RTL_R32(tp, ERIDR) : ~0;
1245 }
1246
1247 static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 mask, u32 p,
1248                          u32 m, int type)
1249 {
1250         u32 val;
1251
1252         val = rtl_eri_read(tp, addr, type);
1253         rtl_eri_write(tp, addr, mask, (val & ~m) | p, type);
1254 }
1255
1256 static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1257 {
1258         RTL_W32(tp, OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1259         return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?
1260                 RTL_R32(tp, OCPDR) : ~0;
1261 }
1262
1263 static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1264 {
1265         return rtl_eri_read(tp, reg, ERIAR_OOB);
1266 }
1267
1268 static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1269 {
1270         switch (tp->mac_version) {
1271         case RTL_GIGA_MAC_VER_27:
1272         case RTL_GIGA_MAC_VER_28:
1273         case RTL_GIGA_MAC_VER_31:
1274                 return r8168dp_ocp_read(tp, mask, reg);
1275         case RTL_GIGA_MAC_VER_49:
1276         case RTL_GIGA_MAC_VER_50:
1277         case RTL_GIGA_MAC_VER_51:
1278                 return r8168ep_ocp_read(tp, mask, reg);
1279         default:
1280                 BUG();
1281                 return ~0;
1282         }
1283 }
1284
1285 static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1286                               u32 data)
1287 {
1288         RTL_W32(tp, OCPDR, data);
1289         RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1290         rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);
1291 }
1292
1293 static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1294                               u32 data)
1295 {
1296         rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT,
1297                       data, ERIAR_OOB);
1298 }
1299
1300 static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
1301 {
1302         switch (tp->mac_version) {
1303         case RTL_GIGA_MAC_VER_27:
1304         case RTL_GIGA_MAC_VER_28:
1305         case RTL_GIGA_MAC_VER_31:
1306                 r8168dp_ocp_write(tp, mask, reg, data);
1307                 break;
1308         case RTL_GIGA_MAC_VER_49:
1309         case RTL_GIGA_MAC_VER_50:
1310         case RTL_GIGA_MAC_VER_51:
1311                 r8168ep_ocp_write(tp, mask, reg, data);
1312                 break;
1313         default:
1314                 BUG();
1315                 break;
1316         }
1317 }
1318
1319 static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
1320 {
1321         rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd, ERIAR_EXGMAC);
1322
1323         ocp_write(tp, 0x1, 0x30, 0x00000001);
1324 }
1325
1326 #define OOB_CMD_RESET           0x00
1327 #define OOB_CMD_DRIVER_START    0x05
1328 #define OOB_CMD_DRIVER_STOP     0x06
1329
1330 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
1331 {
1332         return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
1333 }
1334
1335 DECLARE_RTL_COND(rtl_ocp_read_cond)
1336 {
1337         u16 reg;
1338
1339         reg = rtl8168_get_ocp_reg(tp);
1340
1341         return ocp_read(tp, 0x0f, reg) & 0x00000800;
1342 }
1343
1344 DECLARE_RTL_COND(rtl_ep_ocp_read_cond)
1345 {
1346         return ocp_read(tp, 0x0f, 0x124) & 0x00000001;
1347 }
1348
1349 DECLARE_RTL_COND(rtl_ocp_tx_cond)
1350 {
1351         return RTL_R8(tp, IBISR0) & 0x20;
1352 }
1353
1354 static void rtl8168ep_stop_cmac(struct rtl8169_private *tp)
1355 {
1356         RTL_W8(tp, IBCR2, RTL_R8(tp, IBCR2) & ~0x01);
1357         rtl_msleep_loop_wait_high(tp, &rtl_ocp_tx_cond, 50, 2000);
1358         RTL_W8(tp, IBISR0, RTL_R8(tp, IBISR0) | 0x20);
1359         RTL_W8(tp, IBCR0, RTL_R8(tp, IBCR0) & ~0x01);
1360 }
1361
1362 static void rtl8168dp_driver_start(struct rtl8169_private *tp)
1363 {
1364         rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
1365         rtl_msleep_loop_wait_high(tp, &rtl_ocp_read_cond, 10, 10);
1366 }
1367
1368 static void rtl8168ep_driver_start(struct rtl8169_private *tp)
1369 {
1370         ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START);
1371         ocp_write(tp, 0x01, 0x30, ocp_read(tp, 0x01, 0x30) | 0x01);
1372         rtl_msleep_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10, 10);
1373 }
1374
1375 static void rtl8168_driver_start(struct rtl8169_private *tp)
1376 {
1377         switch (tp->mac_version) {
1378         case RTL_GIGA_MAC_VER_27:
1379         case RTL_GIGA_MAC_VER_28:
1380         case RTL_GIGA_MAC_VER_31:
1381                 rtl8168dp_driver_start(tp);
1382                 break;
1383         case RTL_GIGA_MAC_VER_49:
1384         case RTL_GIGA_MAC_VER_50:
1385         case RTL_GIGA_MAC_VER_51:
1386                 rtl8168ep_driver_start(tp);
1387                 break;
1388         default:
1389                 BUG();
1390                 break;
1391         }
1392 }
1393
1394 static void rtl8168dp_driver_stop(struct rtl8169_private *tp)
1395 {
1396         rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
1397         rtl_msleep_loop_wait_low(tp, &rtl_ocp_read_cond, 10, 10);
1398 }
1399
1400 static void rtl8168ep_driver_stop(struct rtl8169_private *tp)
1401 {
1402         rtl8168ep_stop_cmac(tp);
1403         ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP);
1404         ocp_write(tp, 0x01, 0x30, ocp_read(tp, 0x01, 0x30) | 0x01);
1405         rtl_msleep_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10, 10);
1406 }
1407
1408 static void rtl8168_driver_stop(struct rtl8169_private *tp)
1409 {
1410         switch (tp->mac_version) {
1411         case RTL_GIGA_MAC_VER_27:
1412         case RTL_GIGA_MAC_VER_28:
1413         case RTL_GIGA_MAC_VER_31:
1414                 rtl8168dp_driver_stop(tp);
1415                 break;
1416         case RTL_GIGA_MAC_VER_49:
1417         case RTL_GIGA_MAC_VER_50:
1418         case RTL_GIGA_MAC_VER_51:
1419                 rtl8168ep_driver_stop(tp);
1420                 break;
1421         default:
1422                 BUG();
1423                 break;
1424         }
1425 }
1426
1427 static bool r8168dp_check_dash(struct rtl8169_private *tp)
1428 {
1429         u16 reg = rtl8168_get_ocp_reg(tp);
1430
1431         return !!(ocp_read(tp, 0x0f, reg) & 0x00008000);
1432 }
1433
1434 static bool r8168ep_check_dash(struct rtl8169_private *tp)
1435 {
1436         return !!(ocp_read(tp, 0x0f, 0x128) & 0x00000001);
1437 }
1438
1439 static bool r8168_check_dash(struct rtl8169_private *tp)
1440 {
1441         switch (tp->mac_version) {
1442         case RTL_GIGA_MAC_VER_27:
1443         case RTL_GIGA_MAC_VER_28:
1444         case RTL_GIGA_MAC_VER_31:
1445                 return r8168dp_check_dash(tp);
1446         case RTL_GIGA_MAC_VER_49:
1447         case RTL_GIGA_MAC_VER_50:
1448         case RTL_GIGA_MAC_VER_51:
1449                 return r8168ep_check_dash(tp);
1450         default:
1451                 return false;
1452         }
1453 }
1454
1455 struct exgmac_reg {
1456         u16 addr;
1457         u16 mask;
1458         u32 val;
1459 };
1460
1461 static void rtl_write_exgmac_batch(struct rtl8169_private *tp,
1462                                    const struct exgmac_reg *r, int len)
1463 {
1464         while (len-- > 0) {
1465                 rtl_eri_write(tp, r->addr, r->mask, r->val, ERIAR_EXGMAC);
1466                 r++;
1467         }
1468 }
1469
1470 DECLARE_RTL_COND(rtl_efusear_cond)
1471 {
1472         return RTL_R32(tp, EFUSEAR) & EFUSEAR_FLAG;
1473 }
1474
1475 static u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)
1476 {
1477         RTL_W32(tp, EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1478
1479         return rtl_udelay_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?
1480                 RTL_R32(tp, EFUSEAR) & EFUSEAR_DATA_MASK : ~0;
1481 }
1482
1483 static u16 rtl_get_events(struct rtl8169_private *tp)
1484 {
1485         return RTL_R16(tp, IntrStatus);
1486 }
1487
1488 static void rtl_ack_events(struct rtl8169_private *tp, u16 bits)
1489 {
1490         RTL_W16(tp, IntrStatus, bits);
1491         mmiowb();
1492 }
1493
1494 static void rtl_irq_disable(struct rtl8169_private *tp)
1495 {
1496         RTL_W16(tp, IntrMask, 0);
1497         mmiowb();
1498 }
1499
1500 static void rtl_irq_enable(struct rtl8169_private *tp, u16 bits)
1501 {
1502         RTL_W16(tp, IntrMask, bits);
1503 }
1504
1505 #define RTL_EVENT_NAPI_RX       (RxOK | RxErr)
1506 #define RTL_EVENT_NAPI_TX       (TxOK | TxErr)
1507 #define RTL_EVENT_NAPI          (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX)
1508
1509 static void rtl_irq_enable_all(struct rtl8169_private *tp)
1510 {
1511         rtl_irq_enable(tp, RTL_EVENT_NAPI | tp->event_slow);
1512 }
1513
1514 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1515 {
1516         rtl_irq_disable(tp);
1517         rtl_ack_events(tp, RTL_EVENT_NAPI | tp->event_slow);
1518         RTL_R8(tp, ChipCmd);
1519 }
1520
1521 static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
1522 {
1523         return RTL_R32(tp, TBICSR) & TBIReset;
1524 }
1525
1526 static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
1527 {
1528         return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
1529 }
1530
1531 static unsigned int rtl8169_tbi_link_ok(struct rtl8169_private *tp)
1532 {
1533         return RTL_R32(tp, TBICSR) & TBILinkOk;
1534 }
1535
1536 static unsigned int rtl8169_xmii_link_ok(struct rtl8169_private *tp)
1537 {
1538         return RTL_R8(tp, PHYstatus) & LinkStatus;
1539 }
1540
1541 static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
1542 {
1543         RTL_W32(tp, TBICSR, RTL_R32(tp, TBICSR) | TBIReset);
1544 }
1545
1546 static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
1547 {
1548         unsigned int val;
1549
1550         val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
1551         rtl_writephy(tp, MII_BMCR, val & 0xffff);
1552 }
1553
1554 static void rtl_link_chg_patch(struct rtl8169_private *tp)
1555 {
1556         struct net_device *dev = tp->dev;
1557
1558         if (!netif_running(dev))
1559                 return;
1560
1561         if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
1562             tp->mac_version == RTL_GIGA_MAC_VER_38) {
1563                 if (RTL_R8(tp, PHYstatus) & _1000bpsF) {
1564                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1565                                       ERIAR_EXGMAC);
1566                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1567                                       ERIAR_EXGMAC);
1568                 } else if (RTL_R8(tp, PHYstatus) & _100bps) {
1569                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1570                                       ERIAR_EXGMAC);
1571                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1572                                       ERIAR_EXGMAC);
1573                 } else {
1574                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1575                                       ERIAR_EXGMAC);
1576                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1577                                       ERIAR_EXGMAC);
1578                 }
1579                 /* Reset packet filter */
1580                 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01,
1581                              ERIAR_EXGMAC);
1582                 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00,
1583                              ERIAR_EXGMAC);
1584         } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1585                    tp->mac_version == RTL_GIGA_MAC_VER_36) {
1586                 if (RTL_R8(tp, PHYstatus) & _1000bpsF) {
1587                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1588                                       ERIAR_EXGMAC);
1589                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1590                                       ERIAR_EXGMAC);
1591                 } else {
1592                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1593                                       ERIAR_EXGMAC);
1594                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1595                                       ERIAR_EXGMAC);
1596                 }
1597         } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
1598                 if (RTL_R8(tp, PHYstatus) & _10bps) {
1599                         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02,
1600                                       ERIAR_EXGMAC);
1601                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060,
1602                                       ERIAR_EXGMAC);
1603                 } else {
1604                         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000,
1605                                       ERIAR_EXGMAC);
1606                 }
1607         }
1608 }
1609
1610 static void rtl8169_check_link_status(struct net_device *dev,
1611                                       struct rtl8169_private *tp)
1612 {
1613         struct device *d = tp_to_dev(tp);
1614
1615         if (tp->link_ok(tp)) {
1616                 rtl_link_chg_patch(tp);
1617                 /* This is to cancel a scheduled suspend if there's one. */
1618                 pm_request_resume(d);
1619                 netif_carrier_on(dev);
1620                 if (net_ratelimit())
1621                         netif_info(tp, ifup, dev, "link up\n");
1622         } else {
1623                 netif_carrier_off(dev);
1624                 netif_info(tp, ifdown, dev, "link down\n");
1625                 pm_runtime_idle(d);
1626         }
1627 }
1628
1629 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1630
1631 static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
1632 {
1633         u8 options;
1634         u32 wolopts = 0;
1635
1636         options = RTL_R8(tp, Config1);
1637         if (!(options & PMEnable))
1638                 return 0;
1639
1640         options = RTL_R8(tp, Config3);
1641         if (options & LinkUp)
1642                 wolopts |= WAKE_PHY;
1643         switch (tp->mac_version) {
1644         case RTL_GIGA_MAC_VER_34:
1645         case RTL_GIGA_MAC_VER_35:
1646         case RTL_GIGA_MAC_VER_36:
1647         case RTL_GIGA_MAC_VER_37:
1648         case RTL_GIGA_MAC_VER_38:
1649         case RTL_GIGA_MAC_VER_40:
1650         case RTL_GIGA_MAC_VER_41:
1651         case RTL_GIGA_MAC_VER_42:
1652         case RTL_GIGA_MAC_VER_43:
1653         case RTL_GIGA_MAC_VER_44:
1654         case RTL_GIGA_MAC_VER_45:
1655         case RTL_GIGA_MAC_VER_46:
1656         case RTL_GIGA_MAC_VER_47:
1657         case RTL_GIGA_MAC_VER_48:
1658         case RTL_GIGA_MAC_VER_49:
1659         case RTL_GIGA_MAC_VER_50:
1660         case RTL_GIGA_MAC_VER_51:
1661                 if (rtl_eri_read(tp, 0xdc, ERIAR_EXGMAC) & MagicPacket_v2)
1662                         wolopts |= WAKE_MAGIC;
1663                 break;
1664         default:
1665                 if (options & MagicPacket)
1666                         wolopts |= WAKE_MAGIC;
1667                 break;
1668         }
1669
1670         options = RTL_R8(tp, Config5);
1671         if (options & UWF)
1672                 wolopts |= WAKE_UCAST;
1673         if (options & BWF)
1674                 wolopts |= WAKE_BCAST;
1675         if (options & MWF)
1676                 wolopts |= WAKE_MCAST;
1677
1678         return wolopts;
1679 }
1680
1681 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1682 {
1683         struct rtl8169_private *tp = netdev_priv(dev);
1684         struct device *d = tp_to_dev(tp);
1685
1686         pm_runtime_get_noresume(d);
1687
1688         rtl_lock_work(tp);
1689
1690         wol->supported = WAKE_ANY;
1691         if (pm_runtime_active(d))
1692                 wol->wolopts = __rtl8169_get_wol(tp);
1693         else
1694                 wol->wolopts = tp->saved_wolopts;
1695
1696         rtl_unlock_work(tp);
1697
1698         pm_runtime_put_noidle(d);
1699 }
1700
1701 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1702 {
1703         unsigned int i, tmp;
1704         static const struct {
1705                 u32 opt;
1706                 u16 reg;
1707                 u8  mask;
1708         } cfg[] = {
1709                 { WAKE_PHY,   Config3, LinkUp },
1710                 { WAKE_UCAST, Config5, UWF },
1711                 { WAKE_BCAST, Config5, BWF },
1712                 { WAKE_MCAST, Config5, MWF },
1713                 { WAKE_ANY,   Config5, LanWake },
1714                 { WAKE_MAGIC, Config3, MagicPacket }
1715         };
1716         u8 options;
1717
1718         RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
1719
1720         switch (tp->mac_version) {
1721         case RTL_GIGA_MAC_VER_34:
1722         case RTL_GIGA_MAC_VER_35:
1723         case RTL_GIGA_MAC_VER_36:
1724         case RTL_GIGA_MAC_VER_37:
1725         case RTL_GIGA_MAC_VER_38:
1726         case RTL_GIGA_MAC_VER_40:
1727         case RTL_GIGA_MAC_VER_41:
1728         case RTL_GIGA_MAC_VER_42:
1729         case RTL_GIGA_MAC_VER_43:
1730         case RTL_GIGA_MAC_VER_44:
1731         case RTL_GIGA_MAC_VER_45:
1732         case RTL_GIGA_MAC_VER_46:
1733         case RTL_GIGA_MAC_VER_47:
1734         case RTL_GIGA_MAC_VER_48:
1735         case RTL_GIGA_MAC_VER_49:
1736         case RTL_GIGA_MAC_VER_50:
1737         case RTL_GIGA_MAC_VER_51:
1738                 tmp = ARRAY_SIZE(cfg) - 1;
1739                 if (wolopts & WAKE_MAGIC)
1740                         rtl_w0w1_eri(tp,
1741                                      0x0dc,
1742                                      ERIAR_MASK_0100,
1743                                      MagicPacket_v2,
1744                                      0x0000,
1745                                      ERIAR_EXGMAC);
1746                 else
1747                         rtl_w0w1_eri(tp,
1748                                      0x0dc,
1749                                      ERIAR_MASK_0100,
1750                                      0x0000,
1751                                      MagicPacket_v2,
1752                                      ERIAR_EXGMAC);
1753                 break;
1754         default:
1755                 tmp = ARRAY_SIZE(cfg);
1756                 break;
1757         }
1758
1759         for (i = 0; i < tmp; i++) {
1760                 options = RTL_R8(tp, cfg[i].reg) & ~cfg[i].mask;
1761                 if (wolopts & cfg[i].opt)
1762                         options |= cfg[i].mask;
1763                 RTL_W8(tp, cfg[i].reg, options);
1764         }
1765
1766         switch (tp->mac_version) {
1767         case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_17:
1768                 options = RTL_R8(tp, Config1) & ~PMEnable;
1769                 if (wolopts)
1770                         options |= PMEnable;
1771                 RTL_W8(tp, Config1, options);
1772                 break;
1773         default:
1774                 options = RTL_R8(tp, Config2) & ~PME_SIGNAL;
1775                 if (wolopts)
1776                         options |= PME_SIGNAL;
1777                 RTL_W8(tp, Config2, options);
1778                 break;
1779         }
1780
1781         RTL_W8(tp, Cfg9346, Cfg9346_Lock);
1782 }
1783
1784 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1785 {
1786         struct rtl8169_private *tp = netdev_priv(dev);
1787         struct device *d = tp_to_dev(tp);
1788
1789         pm_runtime_get_noresume(d);
1790
1791         rtl_lock_work(tp);
1792
1793         if (pm_runtime_active(d))
1794                 __rtl8169_set_wol(tp, wol->wolopts);
1795         else
1796                 tp->saved_wolopts = wol->wolopts;
1797
1798         rtl_unlock_work(tp);
1799
1800         device_set_wakeup_enable(d, wol->wolopts);
1801
1802         pm_runtime_put_noidle(d);
1803
1804         return 0;
1805 }
1806
1807 static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp)
1808 {
1809         return rtl_chip_infos[tp->mac_version].fw_name;
1810 }
1811
1812 static void rtl8169_get_drvinfo(struct net_device *dev,
1813                                 struct ethtool_drvinfo *info)
1814 {
1815         struct rtl8169_private *tp = netdev_priv(dev);
1816         struct rtl_fw *rtl_fw = tp->rtl_fw;
1817
1818         strlcpy(info->driver, MODULENAME, sizeof(info->driver));
1819         strlcpy(info->version, RTL8169_VERSION, sizeof(info->version));
1820         strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1821         BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
1822         if (!IS_ERR_OR_NULL(rtl_fw))
1823                 strlcpy(info->fw_version, rtl_fw->version,
1824                         sizeof(info->fw_version));
1825 }
1826
1827 static int rtl8169_get_regs_len(struct net_device *dev)
1828 {
1829         return R8169_REGS_SIZE;
1830 }
1831
1832 static int rtl8169_set_speed_tbi(struct net_device *dev,
1833                                  u8 autoneg, u16 speed, u8 duplex, u32 ignored)
1834 {
1835         struct rtl8169_private *tp = netdev_priv(dev);
1836         int ret = 0;
1837         u32 reg;
1838
1839         reg = RTL_R32(tp, TBICSR);
1840         if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
1841             (duplex == DUPLEX_FULL)) {
1842                 RTL_W32(tp, TBICSR, reg & ~(TBINwEnable | TBINwRestart));
1843         } else if (autoneg == AUTONEG_ENABLE)
1844                 RTL_W32(tp, TBICSR, reg | TBINwEnable | TBINwRestart);
1845         else {
1846                 netif_warn(tp, link, dev,
1847                            "incorrect speed setting refused in TBI mode\n");
1848                 ret = -EOPNOTSUPP;
1849         }
1850
1851         return ret;
1852 }
1853
1854 static int rtl8169_set_speed_xmii(struct net_device *dev,
1855                                   u8 autoneg, u16 speed, u8 duplex, u32 adv)
1856 {
1857         struct rtl8169_private *tp = netdev_priv(dev);
1858         int giga_ctrl, bmcr;
1859         int rc = -EINVAL;
1860
1861         rtl_writephy(tp, 0x1f, 0x0000);
1862
1863         if (autoneg == AUTONEG_ENABLE) {
1864                 int auto_nego;
1865
1866                 auto_nego = rtl_readphy(tp, MII_ADVERTISE);
1867                 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
1868                                 ADVERTISE_100HALF | ADVERTISE_100FULL);
1869
1870                 if (adv & ADVERTISED_10baseT_Half)
1871                         auto_nego |= ADVERTISE_10HALF;
1872                 if (adv & ADVERTISED_10baseT_Full)
1873                         auto_nego |= ADVERTISE_10FULL;
1874                 if (adv & ADVERTISED_100baseT_Half)
1875                         auto_nego |= ADVERTISE_100HALF;
1876                 if (adv & ADVERTISED_100baseT_Full)
1877                         auto_nego |= ADVERTISE_100FULL;
1878
1879                 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1880
1881                 giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
1882                 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
1883
1884                 /* The 8100e/8101e/8102e do Fast Ethernet only. */
1885                 if (tp->mii.supports_gmii) {
1886                         if (adv & ADVERTISED_1000baseT_Half)
1887                                 giga_ctrl |= ADVERTISE_1000HALF;
1888                         if (adv & ADVERTISED_1000baseT_Full)
1889                                 giga_ctrl |= ADVERTISE_1000FULL;
1890                 } else if (adv & (ADVERTISED_1000baseT_Half |
1891                                   ADVERTISED_1000baseT_Full)) {
1892                         netif_info(tp, link, dev,
1893                                    "PHY does not support 1000Mbps\n");
1894                         goto out;
1895                 }
1896
1897                 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
1898
1899                 rtl_writephy(tp, MII_ADVERTISE, auto_nego);
1900                 rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
1901         } else {
1902                 if (speed == SPEED_10)
1903                         bmcr = 0;
1904                 else if (speed == SPEED_100)
1905                         bmcr = BMCR_SPEED100;
1906                 else
1907                         goto out;
1908
1909                 if (duplex == DUPLEX_FULL)
1910                         bmcr |= BMCR_FULLDPLX;
1911         }
1912
1913         rtl_writephy(tp, MII_BMCR, bmcr);
1914
1915         if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
1916             tp->mac_version == RTL_GIGA_MAC_VER_03) {
1917                 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
1918                         rtl_writephy(tp, 0x17, 0x2138);
1919                         rtl_writephy(tp, 0x0e, 0x0260);
1920                 } else {
1921                         rtl_writephy(tp, 0x17, 0x2108);
1922                         rtl_writephy(tp, 0x0e, 0x0000);
1923                 }
1924         }
1925
1926         rc = 0;
1927 out:
1928         return rc;
1929 }
1930
1931 static int rtl8169_set_speed(struct net_device *dev,
1932                              u8 autoneg, u16 speed, u8 duplex, u32 advertising)
1933 {
1934         struct rtl8169_private *tp = netdev_priv(dev);
1935         int ret;
1936
1937         ret = tp->set_speed(dev, autoneg, speed, duplex, advertising);
1938         if (ret < 0)
1939                 goto out;
1940
1941         if (netif_running(dev) && (autoneg == AUTONEG_ENABLE) &&
1942             (advertising & ADVERTISED_1000baseT_Full) &&
1943             !pci_is_pcie(tp->pci_dev)) {
1944                 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
1945         }
1946 out:
1947         return ret;
1948 }
1949
1950 static netdev_features_t rtl8169_fix_features(struct net_device *dev,
1951         netdev_features_t features)
1952 {
1953         struct rtl8169_private *tp = netdev_priv(dev);
1954
1955         if (dev->mtu > TD_MSS_MAX)
1956                 features &= ~NETIF_F_ALL_TSO;
1957
1958         if (dev->mtu > JUMBO_1K &&
1959             !rtl_chip_infos[tp->mac_version].jumbo_tx_csum)
1960                 features &= ~NETIF_F_IP_CSUM;
1961
1962         return features;
1963 }
1964
1965 static void __rtl8169_set_features(struct net_device *dev,
1966                                    netdev_features_t features)
1967 {
1968         struct rtl8169_private *tp = netdev_priv(dev);
1969         u32 rx_config;
1970
1971         rx_config = RTL_R32(tp, RxConfig);
1972         if (features & NETIF_F_RXALL)
1973                 rx_config |= (AcceptErr | AcceptRunt);
1974         else
1975                 rx_config &= ~(AcceptErr | AcceptRunt);
1976
1977         RTL_W32(tp, RxConfig, rx_config);
1978
1979         if (features & NETIF_F_RXCSUM)
1980                 tp->cp_cmd |= RxChkSum;
1981         else
1982                 tp->cp_cmd &= ~RxChkSum;
1983
1984         if (features & NETIF_F_HW_VLAN_CTAG_RX)
1985                 tp->cp_cmd |= RxVlan;
1986         else
1987                 tp->cp_cmd &= ~RxVlan;
1988
1989         tp->cp_cmd |= RTL_R16(tp, CPlusCmd) & ~(RxVlan | RxChkSum);
1990
1991         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1992         RTL_R16(tp, CPlusCmd);
1993 }
1994
1995 static int rtl8169_set_features(struct net_device *dev,
1996                                 netdev_features_t features)
1997 {
1998         struct rtl8169_private *tp = netdev_priv(dev);
1999
2000         features &= NETIF_F_RXALL | NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_RX;
2001
2002         rtl_lock_work(tp);
2003         if (features ^ dev->features)
2004                 __rtl8169_set_features(dev, features);
2005         rtl_unlock_work(tp);
2006
2007         return 0;
2008 }
2009
2010
2011 static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb)
2012 {
2013         return (skb_vlan_tag_present(skb)) ?
2014                 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00;
2015 }
2016
2017 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
2018 {
2019         u32 opts2 = le32_to_cpu(desc->opts2);
2020
2021         if (opts2 & RxVlanTag)
2022                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff));
2023 }
2024
2025 static int rtl8169_get_link_ksettings_tbi(struct net_device *dev,
2026                                           struct ethtool_link_ksettings *cmd)
2027 {
2028         struct rtl8169_private *tp = netdev_priv(dev);
2029         u32 status;
2030         u32 supported, advertising;
2031
2032         supported =
2033                 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
2034         cmd->base.port = PORT_FIBRE;
2035
2036         status = RTL_R32(tp, TBICSR);
2037         advertising = (status & TBINwEnable) ?  ADVERTISED_Autoneg : 0;
2038         cmd->base.autoneg = !!(status & TBINwEnable);
2039
2040         cmd->base.speed = SPEED_1000;
2041         cmd->base.duplex = DUPLEX_FULL; /* Always set */
2042
2043         ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported,
2044                                                 supported);
2045         ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising,
2046                                                 advertising);
2047
2048         return 0;
2049 }
2050
2051 static int rtl8169_get_link_ksettings_xmii(struct net_device *dev,
2052                                            struct ethtool_link_ksettings *cmd)
2053 {
2054         struct rtl8169_private *tp = netdev_priv(dev);
2055
2056         mii_ethtool_get_link_ksettings(&tp->mii, cmd);
2057
2058         return 0;
2059 }
2060
2061 static int rtl8169_get_link_ksettings(struct net_device *dev,
2062                                       struct ethtool_link_ksettings *cmd)
2063 {
2064         struct rtl8169_private *tp = netdev_priv(dev);
2065         int rc;
2066
2067         rtl_lock_work(tp);
2068         rc = tp->get_link_ksettings(dev, cmd);
2069         rtl_unlock_work(tp);
2070
2071         return rc;
2072 }
2073
2074 static int rtl8169_set_link_ksettings(struct net_device *dev,
2075                                       const struct ethtool_link_ksettings *cmd)
2076 {
2077         struct rtl8169_private *tp = netdev_priv(dev);
2078         int rc;
2079         u32 advertising;
2080
2081         if (!ethtool_convert_link_mode_to_legacy_u32(&advertising,
2082             cmd->link_modes.advertising))
2083                 return -EINVAL;
2084
2085         del_timer_sync(&tp->timer);
2086
2087         rtl_lock_work(tp);
2088         rc = rtl8169_set_speed(dev, cmd->base.autoneg, cmd->base.speed,
2089                                cmd->base.duplex, advertising);
2090         rtl_unlock_work(tp);
2091
2092         return rc;
2093 }
2094
2095 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
2096                              void *p)
2097 {
2098         struct rtl8169_private *tp = netdev_priv(dev);
2099         u32 __iomem *data = tp->mmio_addr;
2100         u32 *dw = p;
2101         int i;
2102
2103         rtl_lock_work(tp);
2104         for (i = 0; i < R8169_REGS_SIZE; i += 4)
2105                 memcpy_fromio(dw++, data++, 4);
2106         rtl_unlock_work(tp);
2107 }
2108
2109 static u32 rtl8169_get_msglevel(struct net_device *dev)
2110 {
2111         struct rtl8169_private *tp = netdev_priv(dev);
2112
2113         return tp->msg_enable;
2114 }
2115
2116 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
2117 {
2118         struct rtl8169_private *tp = netdev_priv(dev);
2119
2120         tp->msg_enable = value;
2121 }
2122
2123 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
2124         "tx_packets",
2125         "rx_packets",
2126         "tx_errors",
2127         "rx_errors",
2128         "rx_missed",
2129         "align_errors",
2130         "tx_single_collisions",
2131         "tx_multi_collisions",
2132         "unicast",
2133         "broadcast",
2134         "multicast",
2135         "tx_aborted",
2136         "tx_underrun",
2137 };
2138
2139 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
2140 {
2141         switch (sset) {
2142         case ETH_SS_STATS:
2143                 return ARRAY_SIZE(rtl8169_gstrings);
2144         default:
2145                 return -EOPNOTSUPP;
2146         }
2147 }
2148
2149 DECLARE_RTL_COND(rtl_counters_cond)
2150 {
2151         return RTL_R32(tp, CounterAddrLow) & (CounterReset | CounterDump);
2152 }
2153
2154 static bool rtl8169_do_counters(struct rtl8169_private *tp, u32 counter_cmd)
2155 {
2156         dma_addr_t paddr = tp->counters_phys_addr;
2157         u32 cmd;
2158
2159         RTL_W32(tp, CounterAddrHigh, (u64)paddr >> 32);
2160         RTL_R32(tp, CounterAddrHigh);
2161         cmd = (u64)paddr & DMA_BIT_MASK(32);
2162         RTL_W32(tp, CounterAddrLow, cmd);
2163         RTL_W32(tp, CounterAddrLow, cmd | counter_cmd);
2164
2165         return rtl_udelay_loop_wait_low(tp, &rtl_counters_cond, 10, 1000);
2166 }
2167
2168 static bool rtl8169_reset_counters(struct rtl8169_private *tp)
2169 {
2170         /*
2171          * Versions prior to RTL_GIGA_MAC_VER_19 don't support resetting the
2172          * tally counters.
2173          */
2174         if (tp->mac_version < RTL_GIGA_MAC_VER_19)
2175                 return true;
2176
2177         return rtl8169_do_counters(tp, CounterReset);
2178 }
2179
2180 static bool rtl8169_update_counters(struct rtl8169_private *tp)
2181 {
2182         /*
2183          * Some chips are unable to dump tally counters when the receiver
2184          * is disabled.
2185          */
2186         if ((RTL_R8(tp, ChipCmd) & CmdRxEnb) == 0)
2187                 return true;
2188
2189         return rtl8169_do_counters(tp, CounterDump);
2190 }
2191
2192 static bool rtl8169_init_counter_offsets(struct rtl8169_private *tp)
2193 {
2194         struct rtl8169_counters *counters = tp->counters;
2195         bool ret = false;
2196
2197         /*
2198          * rtl8169_init_counter_offsets is called from rtl_open.  On chip
2199          * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only
2200          * reset by a power cycle, while the counter values collected by the
2201          * driver are reset at every driver unload/load cycle.
2202          *
2203          * To make sure the HW values returned by @get_stats64 match the SW
2204          * values, we collect the initial values at first open(*) and use them
2205          * as offsets to normalize the values returned by @get_stats64.
2206          *
2207          * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one
2208          * for the reason stated in rtl8169_update_counters; CmdRxEnb is only
2209          * set at open time by rtl_hw_start.
2210          */
2211
2212         if (tp->tc_offset.inited)
2213                 return true;
2214
2215         /* If both, reset and update fail, propagate to caller. */
2216         if (rtl8169_reset_counters(tp))
2217                 ret = true;
2218
2219         if (rtl8169_update_counters(tp))
2220                 ret = true;
2221
2222         tp->tc_offset.tx_errors = counters->tx_errors;
2223         tp->tc_offset.tx_multi_collision = counters->tx_multi_collision;
2224         tp->tc_offset.tx_aborted = counters->tx_aborted;
2225         tp->tc_offset.inited = true;
2226
2227         return ret;
2228 }
2229
2230 static void rtl8169_get_ethtool_stats(struct net_device *dev,
2231                                       struct ethtool_stats *stats, u64 *data)
2232 {
2233         struct rtl8169_private *tp = netdev_priv(dev);
2234         struct device *d = tp_to_dev(tp);
2235         struct rtl8169_counters *counters = tp->counters;
2236
2237         ASSERT_RTNL();
2238
2239         pm_runtime_get_noresume(d);
2240
2241         if (pm_runtime_active(d))
2242                 rtl8169_update_counters(tp);
2243
2244         pm_runtime_put_noidle(d);
2245
2246         data[0] = le64_to_cpu(counters->tx_packets);
2247         data[1] = le64_to_cpu(counters->rx_packets);
2248         data[2] = le64_to_cpu(counters->tx_errors);
2249         data[3] = le32_to_cpu(counters->rx_errors);
2250         data[4] = le16_to_cpu(counters->rx_missed);
2251         data[5] = le16_to_cpu(counters->align_errors);
2252         data[6] = le32_to_cpu(counters->tx_one_collision);
2253         data[7] = le32_to_cpu(counters->tx_multi_collision);
2254         data[8] = le64_to_cpu(counters->rx_unicast);
2255         data[9] = le64_to_cpu(counters->rx_broadcast);
2256         data[10] = le32_to_cpu(counters->rx_multicast);
2257         data[11] = le16_to_cpu(counters->tx_aborted);
2258         data[12] = le16_to_cpu(counters->tx_underun);
2259 }
2260
2261 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
2262 {
2263         switch(stringset) {
2264         case ETH_SS_STATS:
2265                 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
2266                 break;
2267         }
2268 }
2269
2270 static int rtl8169_nway_reset(struct net_device *dev)
2271 {
2272         struct rtl8169_private *tp = netdev_priv(dev);
2273
2274         return mii_nway_restart(&tp->mii);
2275 }
2276
2277 /*
2278  * Interrupt coalescing
2279  *
2280  * > 1 - the availability of the IntrMitigate (0xe2) register through the
2281  * >     8169, 8168 and 810x line of chipsets
2282  *
2283  * 8169, 8168, and 8136(810x) serial chipsets support it.
2284  *
2285  * > 2 - the Tx timer unit at gigabit speed
2286  *
2287  * The unit of the timer depends on both the speed and the setting of CPlusCmd
2288  * (0xe0) bit 1 and bit 0.
2289  *
2290  * For 8169
2291  * bit[1:0] \ speed        1000M           100M            10M
2292  * 0 0                     320ns           2.56us          40.96us
2293  * 0 1                     2.56us          20.48us         327.7us
2294  * 1 0                     5.12us          40.96us         655.4us
2295  * 1 1                     10.24us         81.92us         1.31ms
2296  *
2297  * For the other
2298  * bit[1:0] \ speed        1000M           100M            10M
2299  * 0 0                     5us             2.56us          40.96us
2300  * 0 1                     40us            20.48us         327.7us
2301  * 1 0                     80us            40.96us         655.4us
2302  * 1 1                     160us           81.92us         1.31ms
2303  */
2304
2305 /* rx/tx scale factors for one particular CPlusCmd[0:1] value */
2306 struct rtl_coalesce_scale {
2307         /* Rx / Tx */
2308         u32 nsecs[2];
2309 };
2310
2311 /* rx/tx scale factors for all CPlusCmd[0:1] cases */
2312 struct rtl_coalesce_info {
2313         u32 speed;
2314         struct rtl_coalesce_scale scalev[4];    /* each CPlusCmd[0:1] case */
2315 };
2316
2317 /* produce (r,t) pairs with each being in series of *1, *8, *8*2, *8*2*2 */
2318 #define rxtx_x1822(r, t) {              \
2319         {{(r),          (t)}},          \
2320         {{(r)*8,        (t)*8}},        \
2321         {{(r)*8*2,      (t)*8*2}},      \
2322         {{(r)*8*2*2,    (t)*8*2*2}},    \
2323 }
2324 static const struct rtl_coalesce_info rtl_coalesce_info_8169[] = {
2325         /* speed        delays:     rx00   tx00 */
2326         { SPEED_10,     rxtx_x1822(40960, 40960)        },
2327         { SPEED_100,    rxtx_x1822( 2560,  2560)        },
2328         { SPEED_1000,   rxtx_x1822(  320,   320)        },
2329         { 0 },
2330 };
2331
2332 static const struct rtl_coalesce_info rtl_coalesce_info_8168_8136[] = {
2333         /* speed        delays:     rx00   tx00 */
2334         { SPEED_10,     rxtx_x1822(40960, 40960)        },
2335         { SPEED_100,    rxtx_x1822( 2560,  2560)        },
2336         { SPEED_1000,   rxtx_x1822( 5000,  5000)        },
2337         { 0 },
2338 };
2339 #undef rxtx_x1822
2340
2341 /* get rx/tx scale vector corresponding to current speed */
2342 static const struct rtl_coalesce_info *rtl_coalesce_info(struct net_device *dev)
2343 {
2344         struct rtl8169_private *tp = netdev_priv(dev);
2345         struct ethtool_link_ksettings ecmd;
2346         const struct rtl_coalesce_info *ci;
2347         int rc;
2348
2349         rc = rtl8169_get_link_ksettings(dev, &ecmd);
2350         if (rc < 0)
2351                 return ERR_PTR(rc);
2352
2353         for (ci = tp->coalesce_info; ci->speed != 0; ci++) {
2354                 if (ecmd.base.speed == ci->speed) {
2355                         return ci;
2356                 }
2357         }
2358
2359         return ERR_PTR(-ELNRNG);
2360 }
2361
2362 static int rtl_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
2363 {
2364         struct rtl8169_private *tp = netdev_priv(dev);
2365         const struct rtl_coalesce_info *ci;
2366         const struct rtl_coalesce_scale *scale;
2367         struct {
2368                 u32 *max_frames;
2369                 u32 *usecs;
2370         } coal_settings [] = {
2371                 { &ec->rx_max_coalesced_frames, &ec->rx_coalesce_usecs },
2372                 { &ec->tx_max_coalesced_frames, &ec->tx_coalesce_usecs }
2373         }, *p = coal_settings;
2374         int i;
2375         u16 w;
2376
2377         memset(ec, 0, sizeof(*ec));
2378
2379         /* get rx/tx scale corresponding to current speed and CPlusCmd[0:1] */
2380         ci = rtl_coalesce_info(dev);
2381         if (IS_ERR(ci))
2382                 return PTR_ERR(ci);
2383
2384         scale = &ci->scalev[RTL_R16(tp, CPlusCmd) & 3];
2385
2386         /* read IntrMitigate and adjust according to scale */
2387         for (w = RTL_R16(tp, IntrMitigate); w; w >>= RTL_COALESCE_SHIFT, p++) {
2388                 *p->max_frames = (w & RTL_COALESCE_MASK) << 2;
2389                 w >>= RTL_COALESCE_SHIFT;
2390                 *p->usecs = w & RTL_COALESCE_MASK;
2391         }
2392
2393         for (i = 0; i < 2; i++) {
2394                 p = coal_settings + i;
2395                 *p->usecs = (*p->usecs * scale->nsecs[i]) / 1000;
2396
2397                 /*
2398                  * ethtool_coalesce says it is illegal to set both usecs and
2399                  * max_frames to 0.
2400                  */
2401                 if (!*p->usecs && !*p->max_frames)
2402                         *p->max_frames = 1;
2403         }
2404
2405         return 0;
2406 }
2407
2408 /* choose appropriate scale factor and CPlusCmd[0:1] for (speed, nsec) */
2409 static const struct rtl_coalesce_scale *rtl_coalesce_choose_scale(
2410                         struct net_device *dev, u32 nsec, u16 *cp01)
2411 {
2412         const struct rtl_coalesce_info *ci;
2413         u16 i;
2414
2415         ci = rtl_coalesce_info(dev);
2416         if (IS_ERR(ci))
2417                 return ERR_CAST(ci);
2418
2419         for (i = 0; i < 4; i++) {
2420                 u32 rxtx_maxscale = max(ci->scalev[i].nsecs[0],
2421                                         ci->scalev[i].nsecs[1]);
2422                 if (nsec <= rxtx_maxscale * RTL_COALESCE_T_MAX) {
2423                         *cp01 = i;
2424                         return &ci->scalev[i];
2425                 }
2426         }
2427
2428         return ERR_PTR(-EINVAL);
2429 }
2430
2431 static int rtl_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
2432 {
2433         struct rtl8169_private *tp = netdev_priv(dev);
2434         const struct rtl_coalesce_scale *scale;
2435         struct {
2436                 u32 frames;
2437                 u32 usecs;
2438         } coal_settings [] = {
2439                 { ec->rx_max_coalesced_frames, ec->rx_coalesce_usecs },
2440                 { ec->tx_max_coalesced_frames, ec->tx_coalesce_usecs }
2441         }, *p = coal_settings;
2442         u16 w = 0, cp01;
2443         int i;
2444
2445         scale = rtl_coalesce_choose_scale(dev,
2446                         max(p[0].usecs, p[1].usecs) * 1000, &cp01);
2447         if (IS_ERR(scale))
2448                 return PTR_ERR(scale);
2449
2450         for (i = 0; i < 2; i++, p++) {
2451                 u32 units;
2452
2453                 /*
2454                  * accept max_frames=1 we returned in rtl_get_coalesce.
2455                  * accept it not only when usecs=0 because of e.g. the following scenario:
2456                  *
2457                  * - both rx_usecs=0 & rx_frames=0 in hardware (no delay on RX)
2458                  * - rtl_get_coalesce returns rx_usecs=0, rx_frames=1
2459                  * - then user does `ethtool -C eth0 rx-usecs 100`
2460                  *
2461                  * since ethtool sends to kernel whole ethtool_coalesce
2462                  * settings, if we do not handle rx_usecs=!0, rx_frames=1
2463                  * we'll reject it below in `frames % 4 != 0`.
2464                  */
2465                 if (p->frames == 1) {
2466                         p->frames = 0;
2467                 }
2468
2469                 units = p->usecs * 1000 / scale->nsecs[i];
2470                 if (p->frames > RTL_COALESCE_FRAME_MAX || p->frames % 4)
2471                         return -EINVAL;
2472
2473                 w <<= RTL_COALESCE_SHIFT;
2474                 w |= units;
2475                 w <<= RTL_COALESCE_SHIFT;
2476                 w |= p->frames >> 2;
2477         }
2478
2479         rtl_lock_work(tp);
2480
2481         RTL_W16(tp, IntrMitigate, swab16(w));
2482
2483         tp->cp_cmd = (tp->cp_cmd & ~3) | cp01;
2484         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
2485         RTL_R16(tp, CPlusCmd);
2486
2487         rtl_unlock_work(tp);
2488
2489         return 0;
2490 }
2491
2492 static const struct ethtool_ops rtl8169_ethtool_ops = {
2493         .get_drvinfo            = rtl8169_get_drvinfo,
2494         .get_regs_len           = rtl8169_get_regs_len,
2495         .get_link               = ethtool_op_get_link,
2496         .get_coalesce           = rtl_get_coalesce,
2497         .set_coalesce           = rtl_set_coalesce,
2498         .get_msglevel           = rtl8169_get_msglevel,
2499         .set_msglevel           = rtl8169_set_msglevel,
2500         .get_regs               = rtl8169_get_regs,
2501         .get_wol                = rtl8169_get_wol,
2502         .set_wol                = rtl8169_set_wol,
2503         .get_strings            = rtl8169_get_strings,
2504         .get_sset_count         = rtl8169_get_sset_count,
2505         .get_ethtool_stats      = rtl8169_get_ethtool_stats,
2506         .get_ts_info            = ethtool_op_get_ts_info,
2507         .nway_reset             = rtl8169_nway_reset,
2508         .get_link_ksettings     = rtl8169_get_link_ksettings,
2509         .set_link_ksettings     = rtl8169_set_link_ksettings,
2510 };
2511
2512 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
2513                                     struct net_device *dev, u8 default_version)
2514 {
2515         /*
2516          * The driver currently handles the 8168Bf and the 8168Be identically
2517          * but they can be identified more specifically through the test below
2518          * if needed:
2519          *
2520          * (RTL_R32(tp, TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
2521          *
2522          * Same thing for the 8101Eb and the 8101Ec:
2523          *
2524          * (RTL_R32(tp, TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
2525          */
2526         static const struct rtl_mac_info {
2527                 u32 mask;
2528                 u32 val;
2529                 int mac_version;
2530         } mac_info[] = {
2531                 /* 8168EP family. */
2532                 { 0x7cf00000, 0x50200000,       RTL_GIGA_MAC_VER_51 },
2533                 { 0x7cf00000, 0x50100000,       RTL_GIGA_MAC_VER_50 },
2534                 { 0x7cf00000, 0x50000000,       RTL_GIGA_MAC_VER_49 },
2535
2536                 /* 8168H family. */
2537                 { 0x7cf00000, 0x54100000,       RTL_GIGA_MAC_VER_46 },
2538                 { 0x7cf00000, 0x54000000,       RTL_GIGA_MAC_VER_45 },
2539
2540                 /* 8168G family. */
2541                 { 0x7cf00000, 0x5c800000,       RTL_GIGA_MAC_VER_44 },
2542                 { 0x7cf00000, 0x50900000,       RTL_GIGA_MAC_VER_42 },
2543                 { 0x7cf00000, 0x4c100000,       RTL_GIGA_MAC_VER_41 },
2544                 { 0x7cf00000, 0x4c000000,       RTL_GIGA_MAC_VER_40 },
2545
2546                 /* 8168F family. */
2547                 { 0x7c800000, 0x48800000,       RTL_GIGA_MAC_VER_38 },
2548                 { 0x7cf00000, 0x48100000,       RTL_GIGA_MAC_VER_36 },
2549                 { 0x7cf00000, 0x48000000,       RTL_GIGA_MAC_VER_35 },
2550
2551                 /* 8168E family. */
2552                 { 0x7c800000, 0x2c800000,       RTL_GIGA_MAC_VER_34 },
2553                 { 0x7cf00000, 0x2c200000,       RTL_GIGA_MAC_VER_33 },
2554                 { 0x7cf00000, 0x2c100000,       RTL_GIGA_MAC_VER_32 },
2555                 { 0x7c800000, 0x2c000000,       RTL_GIGA_MAC_VER_33 },
2556
2557                 /* 8168D family. */
2558                 { 0x7cf00000, 0x28300000,       RTL_GIGA_MAC_VER_26 },
2559                 { 0x7cf00000, 0x28100000,       RTL_GIGA_MAC_VER_25 },
2560                 { 0x7c800000, 0x28000000,       RTL_GIGA_MAC_VER_26 },
2561
2562                 /* 8168DP family. */
2563                 { 0x7cf00000, 0x28800000,       RTL_GIGA_MAC_VER_27 },
2564                 { 0x7cf00000, 0x28a00000,       RTL_GIGA_MAC_VER_28 },
2565                 { 0x7cf00000, 0x28b00000,       RTL_GIGA_MAC_VER_31 },
2566
2567                 /* 8168C family. */
2568                 { 0x7cf00000, 0x3cb00000,       RTL_GIGA_MAC_VER_24 },
2569                 { 0x7cf00000, 0x3c900000,       RTL_GIGA_MAC_VER_23 },
2570                 { 0x7cf00000, 0x3c800000,       RTL_GIGA_MAC_VER_18 },
2571                 { 0x7c800000, 0x3c800000,       RTL_GIGA_MAC_VER_24 },
2572                 { 0x7cf00000, 0x3c000000,       RTL_GIGA_MAC_VER_19 },
2573                 { 0x7cf00000, 0x3c200000,       RTL_GIGA_MAC_VER_20 },
2574                 { 0x7cf00000, 0x3c300000,       RTL_GIGA_MAC_VER_21 },
2575                 { 0x7cf00000, 0x3c400000,       RTL_GIGA_MAC_VER_22 },
2576                 { 0x7c800000, 0x3c000000,       RTL_GIGA_MAC_VER_22 },
2577
2578                 /* 8168B family. */
2579                 { 0x7cf00000, 0x38000000,       RTL_GIGA_MAC_VER_12 },
2580                 { 0x7cf00000, 0x38500000,       RTL_GIGA_MAC_VER_17 },
2581                 { 0x7c800000, 0x38000000,       RTL_GIGA_MAC_VER_17 },
2582                 { 0x7c800000, 0x30000000,       RTL_GIGA_MAC_VER_11 },
2583
2584                 /* 8101 family. */
2585                 { 0x7cf00000, 0x44900000,       RTL_GIGA_MAC_VER_39 },
2586                 { 0x7c800000, 0x44800000,       RTL_GIGA_MAC_VER_39 },
2587                 { 0x7c800000, 0x44000000,       RTL_GIGA_MAC_VER_37 },
2588                 { 0x7cf00000, 0x40b00000,       RTL_GIGA_MAC_VER_30 },
2589                 { 0x7cf00000, 0x40a00000,       RTL_GIGA_MAC_VER_30 },
2590                 { 0x7cf00000, 0x40900000,       RTL_GIGA_MAC_VER_29 },
2591                 { 0x7c800000, 0x40800000,       RTL_GIGA_MAC_VER_30 },
2592                 { 0x7cf00000, 0x34a00000,       RTL_GIGA_MAC_VER_09 },
2593                 { 0x7cf00000, 0x24a00000,       RTL_GIGA_MAC_VER_09 },
2594                 { 0x7cf00000, 0x34900000,       RTL_GIGA_MAC_VER_08 },
2595                 { 0x7cf00000, 0x24900000,       RTL_GIGA_MAC_VER_08 },
2596                 { 0x7cf00000, 0x34800000,       RTL_GIGA_MAC_VER_07 },
2597                 { 0x7cf00000, 0x24800000,       RTL_GIGA_MAC_VER_07 },
2598                 { 0x7cf00000, 0x34000000,       RTL_GIGA_MAC_VER_13 },
2599                 { 0x7cf00000, 0x34300000,       RTL_GIGA_MAC_VER_10 },
2600                 { 0x7cf00000, 0x34200000,       RTL_GIGA_MAC_VER_16 },
2601                 { 0x7c800000, 0x34800000,       RTL_GIGA_MAC_VER_09 },
2602                 { 0x7c800000, 0x24800000,       RTL_GIGA_MAC_VER_09 },
2603                 { 0x7c800000, 0x34000000,       RTL_GIGA_MAC_VER_16 },
2604                 /* FIXME: where did these entries come from ? -- FR */
2605                 { 0xfc800000, 0x38800000,       RTL_GIGA_MAC_VER_15 },
2606                 { 0xfc800000, 0x30800000,       RTL_GIGA_MAC_VER_14 },
2607
2608                 /* 8110 family. */
2609                 { 0xfc800000, 0x98000000,       RTL_GIGA_MAC_VER_06 },
2610                 { 0xfc800000, 0x18000000,       RTL_GIGA_MAC_VER_05 },
2611                 { 0xfc800000, 0x10000000,       RTL_GIGA_MAC_VER_04 },
2612                 { 0xfc800000, 0x04000000,       RTL_GIGA_MAC_VER_03 },
2613                 { 0xfc800000, 0x00800000,       RTL_GIGA_MAC_VER_02 },
2614                 { 0xfc800000, 0x00000000,       RTL_GIGA_MAC_VER_01 },
2615
2616                 /* Catch-all */
2617                 { 0x00000000, 0x00000000,       RTL_GIGA_MAC_NONE   }
2618         };
2619         const struct rtl_mac_info *p = mac_info;
2620         u32 reg;
2621
2622         reg = RTL_R32(tp, TxConfig);
2623         while ((reg & p->mask) != p->val)
2624                 p++;
2625         tp->mac_version = p->mac_version;
2626
2627         if (tp->mac_version == RTL_GIGA_MAC_NONE) {
2628                 netif_notice(tp, probe, dev,
2629                              "unknown MAC, using family default\n");
2630                 tp->mac_version = default_version;
2631         } else if (tp->mac_version == RTL_GIGA_MAC_VER_42) {
2632                 tp->mac_version = tp->mii.supports_gmii ?
2633                                   RTL_GIGA_MAC_VER_42 :
2634                                   RTL_GIGA_MAC_VER_43;
2635         } else if (tp->mac_version == RTL_GIGA_MAC_VER_45) {
2636                 tp->mac_version = tp->mii.supports_gmii ?
2637                                   RTL_GIGA_MAC_VER_45 :
2638                                   RTL_GIGA_MAC_VER_47;
2639         } else if (tp->mac_version == RTL_GIGA_MAC_VER_46) {
2640                 tp->mac_version = tp->mii.supports_gmii ?
2641                                   RTL_GIGA_MAC_VER_46 :
2642                                   RTL_GIGA_MAC_VER_48;
2643         }
2644 }
2645
2646 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
2647 {
2648         dprintk("mac_version = 0x%02x\n", tp->mac_version);
2649 }
2650
2651 struct phy_reg {
2652         u16 reg;
2653         u16 val;
2654 };
2655
2656 static void rtl_writephy_batch(struct rtl8169_private *tp,
2657                                const struct phy_reg *regs, int len)
2658 {
2659         while (len-- > 0) {
2660                 rtl_writephy(tp, regs->reg, regs->val);
2661                 regs++;
2662         }
2663 }
2664
2665 #define PHY_READ                0x00000000
2666 #define PHY_DATA_OR             0x10000000
2667 #define PHY_DATA_AND            0x20000000
2668 #define PHY_BJMPN               0x30000000
2669 #define PHY_MDIO_CHG            0x40000000
2670 #define PHY_CLEAR_READCOUNT     0x70000000
2671 #define PHY_WRITE               0x80000000
2672 #define PHY_READCOUNT_EQ_SKIP   0x90000000
2673 #define PHY_COMP_EQ_SKIPN       0xa0000000
2674 #define PHY_COMP_NEQ_SKIPN      0xb0000000
2675 #define PHY_WRITE_PREVIOUS      0xc0000000
2676 #define PHY_SKIPN               0xd0000000
2677 #define PHY_DELAY_MS            0xe0000000
2678
2679 struct fw_info {
2680         u32     magic;
2681         char    version[RTL_VER_SIZE];
2682         __le32  fw_start;
2683         __le32  fw_len;
2684         u8      chksum;
2685 } __packed;
2686
2687 #define FW_OPCODE_SIZE  sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
2688
2689 static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2690 {
2691         const struct firmware *fw = rtl_fw->fw;
2692         struct fw_info *fw_info = (struct fw_info *)fw->data;
2693         struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2694         char *version = rtl_fw->version;
2695         bool rc = false;
2696
2697         if (fw->size < FW_OPCODE_SIZE)
2698                 goto out;
2699
2700         if (!fw_info->magic) {
2701                 size_t i, size, start;
2702                 u8 checksum = 0;
2703
2704                 if (fw->size < sizeof(*fw_info))
2705                         goto out;
2706
2707                 for (i = 0; i < fw->size; i++)
2708                         checksum += fw->data[i];
2709                 if (checksum != 0)
2710                         goto out;
2711
2712                 start = le32_to_cpu(fw_info->fw_start);
2713                 if (start > fw->size)
2714                         goto out;
2715
2716                 size = le32_to_cpu(fw_info->fw_len);
2717                 if (size > (fw->size - start) / FW_OPCODE_SIZE)
2718                         goto out;
2719
2720                 memcpy(version, fw_info->version, RTL_VER_SIZE);
2721
2722                 pa->code = (__le32 *)(fw->data + start);
2723                 pa->size = size;
2724         } else {
2725                 if (fw->size % FW_OPCODE_SIZE)
2726                         goto out;
2727
2728                 strlcpy(version, rtl_lookup_firmware_name(tp), RTL_VER_SIZE);
2729
2730                 pa->code = (__le32 *)fw->data;
2731                 pa->size = fw->size / FW_OPCODE_SIZE;
2732         }
2733         version[RTL_VER_SIZE - 1] = 0;
2734
2735         rc = true;
2736 out:
2737         return rc;
2738 }
2739
2740 static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev,
2741                            struct rtl_fw_phy_action *pa)
2742 {
2743         bool rc = false;
2744         size_t index;
2745
2746         for (index = 0; index < pa->size; index++) {
2747                 u32 action = le32_to_cpu(pa->code[index]);
2748                 u32 regno = (action & 0x0fff0000) >> 16;
2749
2750                 switch(action & 0xf0000000) {
2751                 case PHY_READ:
2752                 case PHY_DATA_OR:
2753                 case PHY_DATA_AND:
2754                 case PHY_MDIO_CHG:
2755                 case PHY_CLEAR_READCOUNT:
2756                 case PHY_WRITE:
2757                 case PHY_WRITE_PREVIOUS:
2758                 case PHY_DELAY_MS:
2759                         break;
2760
2761                 case PHY_BJMPN:
2762                         if (regno > index) {
2763                                 netif_err(tp, ifup, tp->dev,
2764                                           "Out of range of firmware\n");
2765                                 goto out;
2766                         }
2767                         break;
2768                 case PHY_READCOUNT_EQ_SKIP:
2769                         if (index + 2 >= pa->size) {
2770                                 netif_err(tp, ifup, tp->dev,
2771                                           "Out of range of firmware\n");
2772                                 goto out;
2773                         }
2774                         break;
2775                 case PHY_COMP_EQ_SKIPN:
2776                 case PHY_COMP_NEQ_SKIPN:
2777                 case PHY_SKIPN:
2778                         if (index + 1 + regno >= pa->size) {
2779                                 netif_err(tp, ifup, tp->dev,
2780                                           "Out of range of firmware\n");
2781                                 goto out;
2782                         }
2783                         break;
2784
2785                 default:
2786                         netif_err(tp, ifup, tp->dev,
2787                                   "Invalid action 0x%08x\n", action);
2788                         goto out;
2789                 }
2790         }
2791         rc = true;
2792 out:
2793         return rc;
2794 }
2795
2796 static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2797 {
2798         struct net_device *dev = tp->dev;
2799         int rc = -EINVAL;
2800
2801         if (!rtl_fw_format_ok(tp, rtl_fw)) {
2802                 netif_err(tp, ifup, dev, "invalid firmware\n");
2803                 goto out;
2804         }
2805
2806         if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action))
2807                 rc = 0;
2808 out:
2809         return rc;
2810 }
2811
2812 static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2813 {
2814         struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2815         struct mdio_ops org, *ops = &tp->mdio_ops;
2816         u32 predata, count;
2817         size_t index;
2818
2819         predata = count = 0;
2820         org.write = ops->write;
2821         org.read = ops->read;
2822
2823         for (index = 0; index < pa->size; ) {
2824                 u32 action = le32_to_cpu(pa->code[index]);
2825                 u32 data = action & 0x0000ffff;
2826                 u32 regno = (action & 0x0fff0000) >> 16;
2827
2828                 if (!action)
2829                         break;
2830
2831                 switch(action & 0xf0000000) {
2832                 case PHY_READ:
2833                         predata = rtl_readphy(tp, regno);
2834                         count++;
2835                         index++;
2836                         break;
2837                 case PHY_DATA_OR:
2838                         predata |= data;
2839                         index++;
2840                         break;
2841                 case PHY_DATA_AND:
2842                         predata &= data;
2843                         index++;
2844                         break;
2845                 case PHY_BJMPN:
2846                         index -= regno;
2847                         break;
2848                 case PHY_MDIO_CHG:
2849                         if (data == 0) {
2850                                 ops->write = org.write;
2851                                 ops->read = org.read;
2852                         } else if (data == 1) {
2853                                 ops->write = mac_mcu_write;
2854                                 ops->read = mac_mcu_read;
2855                         }
2856
2857                         index++;
2858                         break;
2859                 case PHY_CLEAR_READCOUNT:
2860                         count = 0;
2861                         index++;
2862                         break;
2863                 case PHY_WRITE:
2864                         rtl_writephy(tp, regno, data);
2865                         index++;
2866                         break;
2867                 case PHY_READCOUNT_EQ_SKIP:
2868                         index += (count == data) ? 2 : 1;
2869                         break;
2870                 case PHY_COMP_EQ_SKIPN:
2871                         if (predata == data)
2872                                 index += regno;
2873                         index++;
2874                         break;
2875                 case PHY_COMP_NEQ_SKIPN:
2876                         if (predata != data)
2877                                 index += regno;
2878                         index++;
2879                         break;
2880                 case PHY_WRITE_PREVIOUS:
2881                         rtl_writephy(tp, regno, predata);
2882                         index++;
2883                         break;
2884                 case PHY_SKIPN:
2885                         index += regno + 1;
2886                         break;
2887                 case PHY_DELAY_MS:
2888                         mdelay(data);
2889                         index++;
2890                         break;
2891
2892                 default:
2893                         BUG();
2894                 }
2895         }
2896
2897         ops->write = org.write;
2898         ops->read = org.read;
2899 }
2900
2901 static void rtl_release_firmware(struct rtl8169_private *tp)
2902 {
2903         if (!IS_ERR_OR_NULL(tp->rtl_fw)) {
2904                 release_firmware(tp->rtl_fw->fw);
2905                 kfree(tp->rtl_fw);
2906         }
2907         tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
2908 }
2909
2910 static void rtl_apply_firmware(struct rtl8169_private *tp)
2911 {
2912         struct rtl_fw *rtl_fw = tp->rtl_fw;
2913
2914         /* TODO: release firmware once rtl_phy_write_fw signals failures. */
2915         if (!IS_ERR_OR_NULL(rtl_fw))
2916                 rtl_phy_write_fw(tp, rtl_fw);
2917 }
2918
2919 static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
2920 {
2921         if (rtl_readphy(tp, reg) != val)
2922                 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
2923         else
2924                 rtl_apply_firmware(tp);
2925 }
2926
2927 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
2928 {
2929         static const struct phy_reg phy_reg_init[] = {
2930                 { 0x1f, 0x0001 },
2931                 { 0x06, 0x006e },
2932                 { 0x08, 0x0708 },
2933                 { 0x15, 0x4000 },
2934                 { 0x18, 0x65c7 },
2935
2936                 { 0x1f, 0x0001 },
2937                 { 0x03, 0x00a1 },
2938                 { 0x02, 0x0008 },
2939                 { 0x01, 0x0120 },
2940                 { 0x00, 0x1000 },
2941                 { 0x04, 0x0800 },
2942                 { 0x04, 0x0000 },
2943
2944                 { 0x03, 0xff41 },
2945                 { 0x02, 0xdf60 },
2946                 { 0x01, 0x0140 },
2947                 { 0x00, 0x0077 },
2948                 { 0x04, 0x7800 },
2949                 { 0x04, 0x7000 },
2950
2951                 { 0x03, 0x802f },
2952                 { 0x02, 0x4f02 },
2953                 { 0x01, 0x0409 },
2954                 { 0x00, 0xf0f9 },
2955                 { 0x04, 0x9800 },
2956                 { 0x04, 0x9000 },
2957
2958                 { 0x03, 0xdf01 },
2959                 { 0x02, 0xdf20 },
2960                 { 0x01, 0xff95 },
2961                 { 0x00, 0xba00 },
2962                 { 0x04, 0xa800 },
2963                 { 0x04, 0xa000 },
2964
2965                 { 0x03, 0xff41 },
2966                 { 0x02, 0xdf20 },
2967                 { 0x01, 0x0140 },
2968                 { 0x00, 0x00bb },
2969                 { 0x04, 0xb800 },
2970                 { 0x04, 0xb000 },
2971
2972                 { 0x03, 0xdf41 },
2973                 { 0x02, 0xdc60 },
2974                 { 0x01, 0x6340 },
2975                 { 0x00, 0x007d },
2976                 { 0x04, 0xd800 },
2977                 { 0x04, 0xd000 },
2978
2979                 { 0x03, 0xdf01 },
2980                 { 0x02, 0xdf20 },
2981                 { 0x01, 0x100a },
2982                 { 0x00, 0xa0ff },
2983                 { 0x04, 0xf800 },
2984                 { 0x04, 0xf000 },
2985
2986                 { 0x1f, 0x0000 },
2987                 { 0x0b, 0x0000 },
2988                 { 0x00, 0x9200 }
2989         };
2990
2991         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2992 }
2993
2994 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
2995 {
2996         static const struct phy_reg phy_reg_init[] = {
2997                 { 0x1f, 0x0002 },
2998                 { 0x01, 0x90d0 },
2999                 { 0x1f, 0x0000 }
3000         };
3001
3002         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3003 }
3004
3005 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
3006 {
3007         struct pci_dev *pdev = tp->pci_dev;
3008
3009         if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
3010             (pdev->subsystem_device != 0xe000))
3011                 return;
3012
3013         rtl_writephy(tp, 0x1f, 0x0001);
3014         rtl_writephy(tp, 0x10, 0xf01b);
3015         rtl_writephy(tp, 0x1f, 0x0000);
3016 }
3017
3018 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
3019 {
3020         static const struct phy_reg phy_reg_init[] = {
3021                 { 0x1f, 0x0001 },
3022                 { 0x04, 0x0000 },
3023                 { 0x03, 0x00a1 },
3024                 { 0x02, 0x0008 },
3025                 { 0x01, 0x0120 },
3026                 { 0x00, 0x1000 },
3027                 { 0x04, 0x0800 },
3028                 { 0x04, 0x9000 },
3029                 { 0x03, 0x802f },
3030                 { 0x02, 0x4f02 },
3031                 { 0x01, 0x0409 },
3032                 { 0x00, 0xf099 },
3033                 { 0x04, 0x9800 },
3034                 { 0x04, 0xa000 },
3035                 { 0x03, 0xdf01 },
3036                 { 0x02, 0xdf20 },
3037                 { 0x01, 0xff95 },
3038                 { 0x00, 0xba00 },
3039                 { 0x04, 0xa800 },
3040                 { 0x04, 0xf000 },
3041                 { 0x03, 0xdf01 },
3042                 { 0x02, 0xdf20 },
3043                 { 0x01, 0x101a },
3044                 { 0x00, 0xa0ff },
3045                 { 0x04, 0xf800 },
3046                 { 0x04, 0x0000 },
3047                 { 0x1f, 0x0000 },
3048
3049                 { 0x1f, 0x0001 },
3050                 { 0x10, 0xf41b },
3051                 { 0x14, 0xfb54 },
3052                 { 0x18, 0xf5c7 },
3053                 { 0x1f, 0x0000 },
3054
3055                 { 0x1f, 0x0001 },
3056                 { 0x17, 0x0cc0 },
3057                 { 0x1f, 0x0000 }
3058         };
3059
3060         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3061
3062         rtl8169scd_hw_phy_config_quirk(tp);
3063 }
3064
3065 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
3066 {
3067         static const struct phy_reg phy_reg_init[] = {
3068                 { 0x1f, 0x0001 },
3069                 { 0x04, 0x0000 },
3070                 { 0x03, 0x00a1 },
3071                 { 0x02, 0x0008 },
3072                 { 0x01, 0x0120 },
3073                 { 0x00, 0x1000 },
3074                 { 0x04, 0x0800 },
3075                 { 0x04, 0x9000 },
3076                 { 0x03, 0x802f },
3077                 { 0x02, 0x4f02 },
3078                 { 0x01, 0x0409 },
3079                 { 0x00, 0xf099 },
3080                 { 0x04, 0x9800 },
3081                 { 0x04, 0xa000 },
3082                 { 0x03, 0xdf01 },
3083                 { 0x02, 0xdf20 },
3084                 { 0x01, 0xff95 },
3085                 { 0x00, 0xba00 },
3086                 { 0x04, 0xa800 },
3087                 { 0x04, 0xf000 },
3088                 { 0x03, 0xdf01 },
3089                 { 0x02, 0xdf20 },
3090                 { 0x01, 0x101a },
3091                 { 0x00, 0xa0ff },
3092                 { 0x04, 0xf800 },
3093                 { 0x04, 0x0000 },
3094                 { 0x1f, 0x0000 },
3095
3096                 { 0x1f, 0x0001 },
3097                 { 0x0b, 0x8480 },
3098                 { 0x1f, 0x0000 },
3099
3100                 { 0x1f, 0x0001 },
3101                 { 0x18, 0x67c7 },
3102                 { 0x04, 0x2000 },
3103                 { 0x03, 0x002f },
3104                 { 0x02, 0x4360 },
3105                 { 0x01, 0x0109 },
3106                 { 0x00, 0x3022 },
3107                 { 0x04, 0x2800 },
3108                 { 0x1f, 0x0000 },
3109
3110                 { 0x1f, 0x0001 },
3111                 { 0x17, 0x0cc0 },
3112                 { 0x1f, 0x0000 }
3113         };
3114
3115         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3116 }
3117
3118 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
3119 {
3120         static const struct phy_reg phy_reg_init[] = {
3121                 { 0x10, 0xf41b },
3122                 { 0x1f, 0x0000 }
3123         };
3124
3125         rtl_writephy(tp, 0x1f, 0x0001);
3126         rtl_patchphy(tp, 0x16, 1 << 0);
3127
3128         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3129 }
3130
3131 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
3132 {
3133         static const struct phy_reg phy_reg_init[] = {
3134                 { 0x1f, 0x0001 },
3135                 { 0x10, 0xf41b },
3136                 { 0x1f, 0x0000 }
3137         };
3138
3139         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3140 }
3141
3142 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
3143 {
3144         static const struct phy_reg phy_reg_init[] = {
3145                 { 0x1f, 0x0000 },
3146                 { 0x1d, 0x0f00 },
3147                 { 0x1f, 0x0002 },
3148                 { 0x0c, 0x1ec8 },
3149                 { 0x1f, 0x0000 }
3150         };
3151
3152         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3153 }
3154
3155 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
3156 {
3157         static const struct phy_reg phy_reg_init[] = {
3158                 { 0x1f, 0x0001 },
3159                 { 0x1d, 0x3d98 },
3160                 { 0x1f, 0x0000 }
3161         };
3162
3163         rtl_writephy(tp, 0x1f, 0x0000);
3164         rtl_patchphy(tp, 0x14, 1 << 5);
3165         rtl_patchphy(tp, 0x0d, 1 << 5);
3166
3167         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3168 }
3169
3170 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
3171 {
3172         static const struct phy_reg phy_reg_init[] = {
3173                 { 0x1f, 0x0001 },
3174                 { 0x12, 0x2300 },
3175                 { 0x1f, 0x0002 },
3176                 { 0x00, 0x88d4 },
3177                 { 0x01, 0x82b1 },
3178                 { 0x03, 0x7002 },
3179                 { 0x08, 0x9e30 },
3180                 { 0x09, 0x01f0 },
3181                 { 0x0a, 0x5500 },
3182                 { 0x0c, 0x00c8 },
3183                 { 0x1f, 0x0003 },
3184                 { 0x12, 0xc096 },
3185                 { 0x16, 0x000a },
3186                 { 0x1f, 0x0000 },
3187                 { 0x1f, 0x0000 },
3188                 { 0x09, 0x2000 },
3189                 { 0x09, 0x0000 }
3190         };
3191
3192         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3193
3194         rtl_patchphy(tp, 0x14, 1 << 5);
3195         rtl_patchphy(tp, 0x0d, 1 << 5);
3196         rtl_writephy(tp, 0x1f, 0x0000);
3197 }
3198
3199 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
3200 {
3201         static const struct phy_reg phy_reg_init[] = {
3202                 { 0x1f, 0x0001 },
3203                 { 0x12, 0x2300 },
3204                 { 0x03, 0x802f },
3205                 { 0x02, 0x4f02 },
3206                 { 0x01, 0x0409 },
3207                 { 0x00, 0xf099 },
3208                 { 0x04, 0x9800 },
3209                 { 0x04, 0x9000 },
3210                 { 0x1d, 0x3d98 },
3211                 { 0x1f, 0x0002 },
3212                 { 0x0c, 0x7eb8 },
3213                 { 0x06, 0x0761 },
3214                 { 0x1f, 0x0003 },
3215                 { 0x16, 0x0f0a },
3216                 { 0x1f, 0x0000 }
3217         };
3218
3219         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3220
3221         rtl_patchphy(tp, 0x16, 1 << 0);
3222         rtl_patchphy(tp, 0x14, 1 << 5);
3223         rtl_patchphy(tp, 0x0d, 1 << 5);
3224         rtl_writephy(tp, 0x1f, 0x0000);
3225 }
3226
3227 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
3228 {
3229         static const struct phy_reg phy_reg_init[] = {
3230                 { 0x1f, 0x0001 },
3231                 { 0x12, 0x2300 },
3232                 { 0x1d, 0x3d98 },
3233                 { 0x1f, 0x0002 },
3234                 { 0x0c, 0x7eb8 },
3235                 { 0x06, 0x5461 },
3236                 { 0x1f, 0x0003 },
3237                 { 0x16, 0x0f0a },
3238                 { 0x1f, 0x0000 }
3239         };
3240
3241         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3242
3243         rtl_patchphy(tp, 0x16, 1 << 0);
3244         rtl_patchphy(tp, 0x14, 1 << 5);
3245         rtl_patchphy(tp, 0x0d, 1 << 5);
3246         rtl_writephy(tp, 0x1f, 0x0000);
3247 }
3248
3249 static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
3250 {
3251         rtl8168c_3_hw_phy_config(tp);
3252 }
3253
3254 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
3255 {
3256         static const struct phy_reg phy_reg_init_0[] = {
3257                 /* Channel Estimation */
3258                 { 0x1f, 0x0001 },
3259                 { 0x06, 0x4064 },
3260                 { 0x07, 0x2863 },
3261                 { 0x08, 0x059c },
3262                 { 0x09, 0x26b4 },
3263                 { 0x0a, 0x6a19 },
3264                 { 0x0b, 0xdcc8 },
3265                 { 0x10, 0xf06d },
3266                 { 0x14, 0x7f68 },
3267                 { 0x18, 0x7fd9 },
3268                 { 0x1c, 0xf0ff },
3269                 { 0x1d, 0x3d9c },
3270                 { 0x1f, 0x0003 },
3271                 { 0x12, 0xf49f },
3272                 { 0x13, 0x070b },
3273                 { 0x1a, 0x05ad },
3274                 { 0x14, 0x94c0 },
3275
3276                 /*
3277                  * Tx Error Issue
3278                  * Enhance line driver power
3279                  */
3280                 { 0x1f, 0x0002 },
3281                 { 0x06, 0x5561 },
3282                 { 0x1f, 0x0005 },
3283                 { 0x05, 0x8332 },
3284                 { 0x06, 0x5561 },
3285
3286                 /*
3287                  * Can not link to 1Gbps with bad cable
3288                  * Decrease SNR threshold form 21.07dB to 19.04dB
3289                  */
3290                 { 0x1f, 0x0001 },
3291                 { 0x17, 0x0cc0 },
3292
3293                 { 0x1f, 0x0000 },
3294                 { 0x0d, 0xf880 }
3295         };
3296
3297         rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
3298
3299         /*
3300          * Rx Error Issue
3301          * Fine Tune Switching regulator parameter
3302          */
3303         rtl_writephy(tp, 0x1f, 0x0002);
3304         rtl_w0w1_phy(tp, 0x0b, 0x0010, 0x00ef);
3305         rtl_w0w1_phy(tp, 0x0c, 0xa200, 0x5d00);
3306
3307         if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
3308                 static const struct phy_reg phy_reg_init[] = {
3309                         { 0x1f, 0x0002 },
3310                         { 0x05, 0x669a },
3311                         { 0x1f, 0x0005 },
3312                         { 0x05, 0x8330 },
3313                         { 0x06, 0x669a },
3314                         { 0x1f, 0x0002 }
3315                 };
3316                 int val;
3317
3318                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3319
3320                 val = rtl_readphy(tp, 0x0d);
3321
3322                 if ((val & 0x00ff) != 0x006c) {
3323                         static const u32 set[] = {
3324                                 0x0065, 0x0066, 0x0067, 0x0068,
3325                                 0x0069, 0x006a, 0x006b, 0x006c
3326                         };
3327                         int i;
3328
3329                         rtl_writephy(tp, 0x1f, 0x0002);
3330
3331                         val &= 0xff00;
3332                         for (i = 0; i < ARRAY_SIZE(set); i++)
3333                                 rtl_writephy(tp, 0x0d, val | set[i]);
3334                 }
3335         } else {
3336                 static const struct phy_reg phy_reg_init[] = {
3337                         { 0x1f, 0x0002 },
3338                         { 0x05, 0x6662 },
3339                         { 0x1f, 0x0005 },
3340                         { 0x05, 0x8330 },
3341                         { 0x06, 0x6662 }
3342                 };
3343
3344                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3345         }
3346
3347         /* RSET couple improve */
3348         rtl_writephy(tp, 0x1f, 0x0002);
3349         rtl_patchphy(tp, 0x0d, 0x0300);
3350         rtl_patchphy(tp, 0x0f, 0x0010);
3351
3352         /* Fine tune PLL performance */
3353         rtl_writephy(tp, 0x1f, 0x0002);
3354         rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
3355         rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
3356
3357         rtl_writephy(tp, 0x1f, 0x0005);
3358         rtl_writephy(tp, 0x05, 0x001b);
3359
3360         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
3361
3362         rtl_writephy(tp, 0x1f, 0x0000);
3363 }
3364
3365 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
3366 {
3367         static const struct phy_reg phy_reg_init_0[] = {
3368                 /* Channel Estimation */
3369                 { 0x1f, 0x0001 },
3370                 { 0x06, 0x4064 },
3371                 { 0x07, 0x2863 },
3372                 { 0x08, 0x059c },
3373                 { 0x09, 0x26b4 },
3374                 { 0x0a, 0x6a19 },
3375                 { 0x0b, 0xdcc8 },
3376                 { 0x10, 0xf06d },
3377                 { 0x14, 0x7f68 },
3378                 { 0x18, 0x7fd9 },
3379                 { 0x1c, 0xf0ff },
3380                 { 0x1d, 0x3d9c },
3381                 { 0x1f, 0x0003 },
3382                 { 0x12, 0xf49f },
3383                 { 0x13, 0x070b },
3384                 { 0x1a, 0x05ad },
3385                 { 0x14, 0x94c0 },
3386
3387                 /*
3388                  * Tx Error Issue
3389                  * Enhance line driver power
3390                  */
3391                 { 0x1f, 0x0002 },
3392                 { 0x06, 0x5561 },
3393                 { 0x1f, 0x0005 },
3394                 { 0x05, 0x8332 },
3395                 { 0x06, 0x5561 },
3396
3397                 /*
3398                  * Can not link to 1Gbps with bad cable
3399                  * Decrease SNR threshold form 21.07dB to 19.04dB
3400                  */
3401                 { 0x1f, 0x0001 },
3402                 { 0x17, 0x0cc0 },
3403
3404                 { 0x1f, 0x0000 },
3405                 { 0x0d, 0xf880 }
3406         };
3407
3408         rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
3409
3410         if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
3411                 static const struct phy_reg phy_reg_init[] = {
3412                         { 0x1f, 0x0002 },
3413                         { 0x05, 0x669a },
3414                         { 0x1f, 0x0005 },
3415                         { 0x05, 0x8330 },
3416                         { 0x06, 0x669a },
3417
3418                         { 0x1f, 0x0002 }
3419                 };
3420                 int val;
3421
3422                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3423
3424                 val = rtl_readphy(tp, 0x0d);
3425                 if ((val & 0x00ff) != 0x006c) {
3426                         static const u32 set[] = {
3427                                 0x0065, 0x0066, 0x0067, 0x0068,
3428                                 0x0069, 0x006a, 0x006b, 0x006c
3429                         };
3430                         int i;
3431
3432                         rtl_writephy(tp, 0x1f, 0x0002);
3433
3434                         val &= 0xff00;
3435                         for (i = 0; i < ARRAY_SIZE(set); i++)
3436                                 rtl_writephy(tp, 0x0d, val | set[i]);
3437                 }
3438         } else {
3439                 static const struct phy_reg phy_reg_init[] = {
3440                         { 0x1f, 0x0002 },
3441                         { 0x05, 0x2642 },
3442                         { 0x1f, 0x0005 },
3443                         { 0x05, 0x8330 },
3444                         { 0x06, 0x2642 }
3445                 };
3446
3447                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3448         }
3449
3450         /* Fine tune PLL performance */
3451         rtl_writephy(tp, 0x1f, 0x0002);
3452         rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
3453         rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
3454
3455         /* Switching regulator Slew rate */
3456         rtl_writephy(tp, 0x1f, 0x0002);
3457         rtl_patchphy(tp, 0x0f, 0x0017);
3458
3459         rtl_writephy(tp, 0x1f, 0x0005);
3460         rtl_writephy(tp, 0x05, 0x001b);
3461
3462         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
3463
3464         rtl_writephy(tp, 0x1f, 0x0000);
3465 }
3466
3467 static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
3468 {
3469         static const struct phy_reg phy_reg_init[] = {
3470                 { 0x1f, 0x0002 },
3471                 { 0x10, 0x0008 },
3472                 { 0x0d, 0x006c },
3473
3474                 { 0x1f, 0x0000 },
3475                 { 0x0d, 0xf880 },
3476
3477                 { 0x1f, 0x0001 },
3478                 { 0x17, 0x0cc0 },
3479
3480                 { 0x1f, 0x0001 },
3481                 { 0x0b, 0xa4d8 },
3482                 { 0x09, 0x281c },
3483                 { 0x07, 0x2883 },
3484                 { 0x0a, 0x6b35 },
3485                 { 0x1d, 0x3da4 },
3486                 { 0x1c, 0xeffd },
3487                 { 0x14, 0x7f52 },
3488                 { 0x18, 0x7fc6 },
3489                 { 0x08, 0x0601 },
3490                 { 0x06, 0x4063 },
3491                 { 0x10, 0xf074 },
3492                 { 0x1f, 0x0003 },
3493                 { 0x13, 0x0789 },
3494                 { 0x12, 0xf4bd },
3495                 { 0x1a, 0x04fd },
3496                 { 0x14, 0x84b0 },
3497                 { 0x1f, 0x0000 },
3498                 { 0x00, 0x9200 },
3499
3500                 { 0x1f, 0x0005 },
3501                 { 0x01, 0x0340 },
3502                 { 0x1f, 0x0001 },
3503                 { 0x04, 0x4000 },
3504                 { 0x03, 0x1d21 },
3505                 { 0x02, 0x0c32 },
3506                 { 0x01, 0x0200 },
3507                 { 0x00, 0x5554 },
3508                 { 0x04, 0x4800 },
3509                 { 0x04, 0x4000 },
3510                 { 0x04, 0xf000 },
3511                 { 0x03, 0xdf01 },
3512                 { 0x02, 0xdf20 },
3513                 { 0x01, 0x101a },
3514                 { 0x00, 0xa0ff },
3515                 { 0x04, 0xf800 },
3516                 { 0x04, 0xf000 },
3517                 { 0x1f, 0x0000 },
3518
3519                 { 0x1f, 0x0007 },
3520                 { 0x1e, 0x0023 },
3521                 { 0x16, 0x0000 },
3522                 { 0x1f, 0x0000 }
3523         };
3524
3525         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3526 }
3527
3528 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
3529 {
3530         static const struct phy_reg phy_reg_init[] = {
3531                 { 0x1f, 0x0001 },
3532                 { 0x17, 0x0cc0 },
3533
3534                 { 0x1f, 0x0007 },
3535                 { 0x1e, 0x002d },
3536                 { 0x18, 0x0040 },
3537                 { 0x1f, 0x0000 }
3538         };
3539
3540         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3541         rtl_patchphy(tp, 0x0d, 1 << 5);
3542 }
3543
3544 static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
3545 {
3546         static const struct phy_reg phy_reg_init[] = {
3547                 /* Enable Delay cap */
3548                 { 0x1f, 0x0005 },
3549                 { 0x05, 0x8b80 },
3550                 { 0x06, 0xc896 },
3551                 { 0x1f, 0x0000 },
3552
3553                 /* Channel estimation fine tune */
3554                 { 0x1f, 0x0001 },
3555                 { 0x0b, 0x6c20 },
3556                 { 0x07, 0x2872 },
3557                 { 0x1c, 0xefff },
3558                 { 0x1f, 0x0003 },
3559                 { 0x14, 0x6420 },
3560                 { 0x1f, 0x0000 },
3561
3562                 /* Update PFM & 10M TX idle timer */
3563                 { 0x1f, 0x0007 },
3564                 { 0x1e, 0x002f },
3565                 { 0x15, 0x1919 },
3566                 { 0x1f, 0x0000 },
3567
3568                 { 0x1f, 0x0007 },
3569                 { 0x1e, 0x00ac },
3570                 { 0x18, 0x0006 },
3571                 { 0x1f, 0x0000 }
3572         };
3573
3574         rtl_apply_firmware(tp);
3575
3576         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3577
3578         /* DCO enable for 10M IDLE Power */
3579         rtl_writephy(tp, 0x1f, 0x0007);
3580         rtl_writephy(tp, 0x1e, 0x0023);
3581         rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
3582         rtl_writephy(tp, 0x1f, 0x0000);
3583
3584         /* For impedance matching */
3585         rtl_writephy(tp, 0x1f, 0x0002);
3586         rtl_w0w1_phy(tp, 0x08, 0x8000, 0x7f00);
3587         rtl_writephy(tp, 0x1f, 0x0000);
3588
3589         /* PHY auto speed down */
3590         rtl_writephy(tp, 0x1f, 0x0007);
3591         rtl_writephy(tp, 0x1e, 0x002d);
3592         rtl_w0w1_phy(tp, 0x18, 0x0050, 0x0000);
3593         rtl_writephy(tp, 0x1f, 0x0000);
3594         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3595
3596         rtl_writephy(tp, 0x1f, 0x0005);
3597         rtl_writephy(tp, 0x05, 0x8b86);
3598         rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3599         rtl_writephy(tp, 0x1f, 0x0000);
3600
3601         rtl_writephy(tp, 0x1f, 0x0005);
3602         rtl_writephy(tp, 0x05, 0x8b85);
3603         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
3604         rtl_writephy(tp, 0x1f, 0x0007);
3605         rtl_writephy(tp, 0x1e, 0x0020);
3606         rtl_w0w1_phy(tp, 0x15, 0x0000, 0x1100);
3607         rtl_writephy(tp, 0x1f, 0x0006);
3608         rtl_writephy(tp, 0x00, 0x5a00);
3609         rtl_writephy(tp, 0x1f, 0x0000);
3610         rtl_writephy(tp, 0x0d, 0x0007);
3611         rtl_writephy(tp, 0x0e, 0x003c);
3612         rtl_writephy(tp, 0x0d, 0x4007);
3613         rtl_writephy(tp, 0x0e, 0x0000);
3614         rtl_writephy(tp, 0x0d, 0x0000);
3615 }
3616
3617 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, u8 *addr)
3618 {
3619         const u16 w[] = {
3620                 addr[0] | (addr[1] << 8),
3621                 addr[2] | (addr[3] << 8),
3622                 addr[4] | (addr[5] << 8)
3623         };
3624         const struct exgmac_reg e[] = {
3625                 { .addr = 0xe0, ERIAR_MASK_1111, .val = w[0] | (w[1] << 16) },
3626                 { .addr = 0xe4, ERIAR_MASK_1111, .val = w[2] },
3627                 { .addr = 0xf0, ERIAR_MASK_1111, .val = w[0] << 16 },
3628                 { .addr = 0xf4, ERIAR_MASK_1111, .val = w[1] | (w[2] << 16) }
3629         };
3630
3631         rtl_write_exgmac_batch(tp, e, ARRAY_SIZE(e));
3632 }
3633
3634 static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
3635 {
3636         static const struct phy_reg phy_reg_init[] = {
3637                 /* Enable Delay cap */
3638                 { 0x1f, 0x0004 },
3639                 { 0x1f, 0x0007 },
3640                 { 0x1e, 0x00ac },
3641                 { 0x18, 0x0006 },
3642                 { 0x1f, 0x0002 },
3643                 { 0x1f, 0x0000 },
3644                 { 0x1f, 0x0000 },
3645
3646                 /* Channel estimation fine tune */
3647                 { 0x1f, 0x0003 },
3648                 { 0x09, 0xa20f },
3649                 { 0x1f, 0x0000 },
3650                 { 0x1f, 0x0000 },
3651
3652                 /* Green Setting */
3653                 { 0x1f, 0x0005 },
3654                 { 0x05, 0x8b5b },
3655                 { 0x06, 0x9222 },
3656                 { 0x05, 0x8b6d },
3657                 { 0x06, 0x8000 },
3658                 { 0x05, 0x8b76 },
3659                 { 0x06, 0x8000 },
3660                 { 0x1f, 0x0000 }
3661         };
3662
3663         rtl_apply_firmware(tp);
3664
3665         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3666
3667         /* For 4-corner performance improve */
3668         rtl_writephy(tp, 0x1f, 0x0005);
3669         rtl_writephy(tp, 0x05, 0x8b80);
3670         rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
3671         rtl_writephy(tp, 0x1f, 0x0000);
3672
3673         /* PHY auto speed down */
3674         rtl_writephy(tp, 0x1f, 0x0004);
3675         rtl_writephy(tp, 0x1f, 0x0007);
3676         rtl_writephy(tp, 0x1e, 0x002d);
3677         rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
3678         rtl_writephy(tp, 0x1f, 0x0002);
3679         rtl_writephy(tp, 0x1f, 0x0000);
3680         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3681
3682         /* improve 10M EEE waveform */
3683         rtl_writephy(tp, 0x1f, 0x0005);
3684         rtl_writephy(tp, 0x05, 0x8b86);
3685         rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3686         rtl_writephy(tp, 0x1f, 0x0000);
3687
3688         /* Improve 2-pair detection performance */
3689         rtl_writephy(tp, 0x1f, 0x0005);
3690         rtl_writephy(tp, 0x05, 0x8b85);
3691         rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3692         rtl_writephy(tp, 0x1f, 0x0000);
3693
3694         /* EEE setting */
3695         rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_1111, 0x0003, 0x0000, ERIAR_EXGMAC);
3696         rtl_writephy(tp, 0x1f, 0x0005);
3697         rtl_writephy(tp, 0x05, 0x8b85);
3698         rtl_w0w1_phy(tp, 0x06, 0x2000, 0x0000);
3699         rtl_writephy(tp, 0x1f, 0x0004);
3700         rtl_writephy(tp, 0x1f, 0x0007);
3701         rtl_writephy(tp, 0x1e, 0x0020);
3702         rtl_w0w1_phy(tp, 0x15, 0x0100, 0x0000);
3703         rtl_writephy(tp, 0x1f, 0x0002);
3704         rtl_writephy(tp, 0x1f, 0x0000);
3705         rtl_writephy(tp, 0x0d, 0x0007);
3706         rtl_writephy(tp, 0x0e, 0x003c);
3707         rtl_writephy(tp, 0x0d, 0x4007);
3708         rtl_writephy(tp, 0x0e, 0x0006);
3709         rtl_writephy(tp, 0x0d, 0x0000);
3710
3711         /* Green feature */
3712         rtl_writephy(tp, 0x1f, 0x0003);
3713         rtl_w0w1_phy(tp, 0x19, 0x0001, 0x0000);
3714         rtl_w0w1_phy(tp, 0x10, 0x0400, 0x0000);
3715         rtl_writephy(tp, 0x1f, 0x0000);
3716         rtl_writephy(tp, 0x1f, 0x0005);
3717         rtl_w0w1_phy(tp, 0x01, 0x0100, 0x0000);
3718         rtl_writephy(tp, 0x1f, 0x0000);
3719
3720         /* Broken BIOS workaround: feed GigaMAC registers with MAC address. */
3721         rtl_rar_exgmac_set(tp, tp->dev->dev_addr);
3722 }
3723
3724 static void rtl8168f_hw_phy_config(struct rtl8169_private *tp)
3725 {
3726         /* For 4-corner performance improve */
3727         rtl_writephy(tp, 0x1f, 0x0005);
3728         rtl_writephy(tp, 0x05, 0x8b80);
3729         rtl_w0w1_phy(tp, 0x06, 0x0006, 0x0000);
3730         rtl_writephy(tp, 0x1f, 0x0000);
3731
3732         /* PHY auto speed down */
3733         rtl_writephy(tp, 0x1f, 0x0007);
3734         rtl_writephy(tp, 0x1e, 0x002d);
3735         rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
3736         rtl_writephy(tp, 0x1f, 0x0000);
3737         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3738
3739         /* Improve 10M EEE waveform */
3740         rtl_writephy(tp, 0x1f, 0x0005);
3741         rtl_writephy(tp, 0x05, 0x8b86);
3742         rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3743         rtl_writephy(tp, 0x1f, 0x0000);
3744 }
3745
3746 static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp)
3747 {
3748         static const struct phy_reg phy_reg_init[] = {
3749                 /* Channel estimation fine tune */
3750                 { 0x1f, 0x0003 },
3751                 { 0x09, 0xa20f },
3752                 { 0x1f, 0x0000 },
3753
3754                 /* Modify green table for giga & fnet */
3755                 { 0x1f, 0x0005 },
3756                 { 0x05, 0x8b55 },
3757                 { 0x06, 0x0000 },
3758                 { 0x05, 0x8b5e },
3759                 { 0x06, 0x0000 },
3760                 { 0x05, 0x8b67 },
3761                 { 0x06, 0x0000 },
3762                 { 0x05, 0x8b70 },
3763                 { 0x06, 0x0000 },
3764                 { 0x1f, 0x0000 },
3765                 { 0x1f, 0x0007 },
3766                 { 0x1e, 0x0078 },
3767                 { 0x17, 0x0000 },
3768                 { 0x19, 0x00fb },
3769                 { 0x1f, 0x0000 },
3770
3771                 /* Modify green table for 10M */
3772                 { 0x1f, 0x0005 },
3773                 { 0x05, 0x8b79 },
3774                 { 0x06, 0xaa00 },
3775                 { 0x1f, 0x0000 },
3776
3777                 /* Disable hiimpedance detection (RTCT) */
3778                 { 0x1f, 0x0003 },
3779                 { 0x01, 0x328a },
3780                 { 0x1f, 0x0000 }
3781         };
3782
3783         rtl_apply_firmware(tp);
3784
3785         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3786
3787         rtl8168f_hw_phy_config(tp);
3788
3789         /* Improve 2-pair detection performance */
3790         rtl_writephy(tp, 0x1f, 0x0005);
3791         rtl_writephy(tp, 0x05, 0x8b85);
3792         rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3793         rtl_writephy(tp, 0x1f, 0x0000);
3794 }
3795
3796 static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp)
3797 {
3798         rtl_apply_firmware(tp);
3799
3800         rtl8168f_hw_phy_config(tp);
3801 }
3802
3803 static void rtl8411_hw_phy_config(struct rtl8169_private *tp)
3804 {
3805         static const struct phy_reg phy_reg_init[] = {
3806                 /* Channel estimation fine tune */
3807                 { 0x1f, 0x0003 },
3808                 { 0x09, 0xa20f },
3809                 { 0x1f, 0x0000 },
3810
3811                 /* Modify green table for giga & fnet */
3812                 { 0x1f, 0x0005 },
3813                 { 0x05, 0x8b55 },
3814                 { 0x06, 0x0000 },
3815                 { 0x05, 0x8b5e },
3816                 { 0x06, 0x0000 },
3817                 { 0x05, 0x8b67 },
3818                 { 0x06, 0x0000 },
3819                 { 0x05, 0x8b70 },
3820                 { 0x06, 0x0000 },
3821                 { 0x1f, 0x0000 },
3822                 { 0x1f, 0x0007 },
3823                 { 0x1e, 0x0078 },
3824                 { 0x17, 0x0000 },
3825                 { 0x19, 0x00aa },
3826                 { 0x1f, 0x0000 },
3827
3828                 /* Modify green table for 10M */
3829                 { 0x1f, 0x0005 },
3830                 { 0x05, 0x8b79 },
3831                 { 0x06, 0xaa00 },
3832                 { 0x1f, 0x0000 },
3833
3834                 /* Disable hiimpedance detection (RTCT) */
3835                 { 0x1f, 0x0003 },
3836                 { 0x01, 0x328a },
3837                 { 0x1f, 0x0000 }
3838         };
3839
3840
3841         rtl_apply_firmware(tp);
3842
3843         rtl8168f_hw_phy_config(tp);
3844
3845         /* Improve 2-pair detection performance */
3846         rtl_writephy(tp, 0x1f, 0x0005);
3847         rtl_writephy(tp, 0x05, 0x8b85);
3848         rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3849         rtl_writephy(tp, 0x1f, 0x0000);
3850
3851         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3852
3853         /* Modify green table for giga */
3854         rtl_writephy(tp, 0x1f, 0x0005);
3855         rtl_writephy(tp, 0x05, 0x8b54);
3856         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
3857         rtl_writephy(tp, 0x05, 0x8b5d);
3858         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
3859         rtl_writephy(tp, 0x05, 0x8a7c);
3860         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3861         rtl_writephy(tp, 0x05, 0x8a7f);
3862         rtl_w0w1_phy(tp, 0x06, 0x0100, 0x0000);
3863         rtl_writephy(tp, 0x05, 0x8a82);
3864         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3865         rtl_writephy(tp, 0x05, 0x8a85);
3866         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3867         rtl_writephy(tp, 0x05, 0x8a88);
3868         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3869         rtl_writephy(tp, 0x1f, 0x0000);
3870
3871         /* uc same-seed solution */
3872         rtl_writephy(tp, 0x1f, 0x0005);
3873         rtl_writephy(tp, 0x05, 0x8b85);
3874         rtl_w0w1_phy(tp, 0x06, 0x8000, 0x0000);
3875         rtl_writephy(tp, 0x1f, 0x0000);
3876
3877         /* eee setting */
3878         rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x00, 0x03, ERIAR_EXGMAC);
3879         rtl_writephy(tp, 0x1f, 0x0005);
3880         rtl_writephy(tp, 0x05, 0x8b85);
3881         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
3882         rtl_writephy(tp, 0x1f, 0x0004);
3883         rtl_writephy(tp, 0x1f, 0x0007);
3884         rtl_writephy(tp, 0x1e, 0x0020);
3885         rtl_w0w1_phy(tp, 0x15, 0x0000, 0x0100);
3886         rtl_writephy(tp, 0x1f, 0x0000);
3887         rtl_writephy(tp, 0x0d, 0x0007);
3888         rtl_writephy(tp, 0x0e, 0x003c);
3889         rtl_writephy(tp, 0x0d, 0x4007);
3890         rtl_writephy(tp, 0x0e, 0x0000);
3891         rtl_writephy(tp, 0x0d, 0x0000);
3892
3893         /* Green feature */
3894         rtl_writephy(tp, 0x1f, 0x0003);
3895         rtl_w0w1_phy(tp, 0x19, 0x0000, 0x0001);
3896         rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0400);
3897         rtl_writephy(tp, 0x1f, 0x0000);
3898 }
3899
3900 static void rtl8168g_1_hw_phy_config(struct rtl8169_private *tp)
3901 {
3902         rtl_apply_firmware(tp);
3903
3904         rtl_writephy(tp, 0x1f, 0x0a46);
3905         if (rtl_readphy(tp, 0x10) & 0x0100) {
3906                 rtl_writephy(tp, 0x1f, 0x0bcc);
3907                 rtl_w0w1_phy(tp, 0x12, 0x0000, 0x8000);
3908         } else {
3909                 rtl_writephy(tp, 0x1f, 0x0bcc);
3910                 rtl_w0w1_phy(tp, 0x12, 0x8000, 0x0000);
3911         }
3912
3913         rtl_writephy(tp, 0x1f, 0x0a46);
3914         if (rtl_readphy(tp, 0x13) & 0x0100) {
3915                 rtl_writephy(tp, 0x1f, 0x0c41);
3916                 rtl_w0w1_phy(tp, 0x15, 0x0002, 0x0000);
3917         } else {
3918                 rtl_writephy(tp, 0x1f, 0x0c41);
3919                 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x0002);
3920         }
3921
3922         /* Enable PHY auto speed down */
3923         rtl_writephy(tp, 0x1f, 0x0a44);
3924         rtl_w0w1_phy(tp, 0x11, 0x000c, 0x0000);
3925
3926         rtl_writephy(tp, 0x1f, 0x0bcc);
3927         rtl_w0w1_phy(tp, 0x14, 0x0100, 0x0000);
3928         rtl_writephy(tp, 0x1f, 0x0a44);
3929         rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
3930         rtl_writephy(tp, 0x1f, 0x0a43);
3931         rtl_writephy(tp, 0x13, 0x8084);
3932         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
3933         rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
3934
3935         /* EEE auto-fallback function */
3936         rtl_writephy(tp, 0x1f, 0x0a4b);
3937         rtl_w0w1_phy(tp, 0x11, 0x0004, 0x0000);
3938
3939         /* Enable UC LPF tune function */
3940         rtl_writephy(tp, 0x1f, 0x0a43);
3941         rtl_writephy(tp, 0x13, 0x8012);
3942         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3943
3944         rtl_writephy(tp, 0x1f, 0x0c42);
3945         rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
3946
3947         /* Improve SWR Efficiency */
3948         rtl_writephy(tp, 0x1f, 0x0bcd);
3949         rtl_writephy(tp, 0x14, 0x5065);
3950         rtl_writephy(tp, 0x14, 0xd065);
3951         rtl_writephy(tp, 0x1f, 0x0bc8);
3952         rtl_writephy(tp, 0x11, 0x5655);
3953         rtl_writephy(tp, 0x1f, 0x0bcd);
3954         rtl_writephy(tp, 0x14, 0x1065);
3955         rtl_writephy(tp, 0x14, 0x9065);
3956         rtl_writephy(tp, 0x14, 0x1065);
3957
3958         /* Check ALDPS bit, disable it if enabled */
3959         rtl_writephy(tp, 0x1f, 0x0a43);
3960         if (rtl_readphy(tp, 0x10) & 0x0004)
3961                 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
3962
3963         rtl_writephy(tp, 0x1f, 0x0000);
3964 }
3965
3966 static void rtl8168g_2_hw_phy_config(struct rtl8169_private *tp)
3967 {
3968         rtl_apply_firmware(tp);
3969 }
3970
3971 static void rtl8168h_1_hw_phy_config(struct rtl8169_private *tp)
3972 {
3973         u16 dout_tapbin;
3974         u32 data;
3975
3976         rtl_apply_firmware(tp);
3977
3978         /* CHN EST parameters adjust - giga master */
3979         rtl_writephy(tp, 0x1f, 0x0a43);
3980         rtl_writephy(tp, 0x13, 0x809b);
3981         rtl_w0w1_phy(tp, 0x14, 0x8000, 0xf800);
3982         rtl_writephy(tp, 0x13, 0x80a2);
3983         rtl_w0w1_phy(tp, 0x14, 0x8000, 0xff00);
3984         rtl_writephy(tp, 0x13, 0x80a4);
3985         rtl_w0w1_phy(tp, 0x14, 0x8500, 0xff00);
3986         rtl_writephy(tp, 0x13, 0x809c);
3987         rtl_w0w1_phy(tp, 0x14, 0xbd00, 0xff00);
3988         rtl_writephy(tp, 0x1f, 0x0000);
3989
3990         /* CHN EST parameters adjust - giga slave */
3991         rtl_writephy(tp, 0x1f, 0x0a43);
3992         rtl_writephy(tp, 0x13, 0x80ad);
3993         rtl_w0w1_phy(tp, 0x14, 0x7000, 0xf800);
3994         rtl_writephy(tp, 0x13, 0x80b4);
3995         rtl_w0w1_phy(tp, 0x14, 0x5000, 0xff00);
3996         rtl_writephy(tp, 0x13, 0x80ac);
3997         rtl_w0w1_phy(tp, 0x14, 0x4000, 0xff00);
3998         rtl_writephy(tp, 0x1f, 0x0000);
3999
4000         /* CHN EST parameters adjust - fnet */
4001         rtl_writephy(tp, 0x1f, 0x0a43);
4002         rtl_writephy(tp, 0x13, 0x808e);
4003         rtl_w0w1_phy(tp, 0x14, 0x1200, 0xff00);
4004         rtl_writephy(tp, 0x13, 0x8090);
4005         rtl_w0w1_phy(tp, 0x14, 0xe500, 0xff00);
4006         rtl_writephy(tp, 0x13, 0x8092);
4007         rtl_w0w1_phy(tp, 0x14, 0x9f00, 0xff00);
4008         rtl_writephy(tp, 0x1f, 0x0000);
4009
4010         /* enable R-tune & PGA-retune function */
4011         dout_tapbin = 0;
4012         rtl_writephy(tp, 0x1f, 0x0a46);
4013         data = rtl_readphy(tp, 0x13);
4014         data &= 3;
4015         data <<= 2;
4016         dout_tapbin |= data;
4017         data = rtl_readphy(tp, 0x12);
4018         data &= 0xc000;
4019         data >>= 14;
4020         dout_tapbin |= data;
4021         dout_tapbin = ~(dout_tapbin^0x08);
4022         dout_tapbin <<= 12;
4023         dout_tapbin &= 0xf000;
4024         rtl_writephy(tp, 0x1f, 0x0a43);
4025         rtl_writephy(tp, 0x13, 0x827a);
4026         rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
4027         rtl_writephy(tp, 0x13, 0x827b);
4028         rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
4029         rtl_writephy(tp, 0x13, 0x827c);
4030         rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
4031         rtl_writephy(tp, 0x13, 0x827d);
4032         rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
4033
4034         rtl_writephy(tp, 0x1f, 0x0a43);
4035         rtl_writephy(tp, 0x13, 0x0811);
4036         rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
4037         rtl_writephy(tp, 0x1f, 0x0a42);
4038         rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
4039         rtl_writephy(tp, 0x1f, 0x0000);
4040
4041         /* enable GPHY 10M */
4042         rtl_writephy(tp, 0x1f, 0x0a44);
4043         rtl_w0w1_phy(tp, 0x11, 0x0800, 0x0000);
4044         rtl_writephy(tp, 0x1f, 0x0000);
4045
4046         /* SAR ADC performance */
4047         rtl_writephy(tp, 0x1f, 0x0bca);
4048         rtl_w0w1_phy(tp, 0x17, 0x4000, 0x3000);
4049         rtl_writephy(tp, 0x1f, 0x0000);
4050
4051         rtl_writephy(tp, 0x1f, 0x0a43);
4052         rtl_writephy(tp, 0x13, 0x803f);
4053         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
4054         rtl_writephy(tp, 0x13, 0x8047);
4055         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
4056         rtl_writephy(tp, 0x13, 0x804f);
4057         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
4058         rtl_writephy(tp, 0x13, 0x8057);
4059         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
4060         rtl_writephy(tp, 0x13, 0x805f);
4061         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
4062         rtl_writephy(tp, 0x13, 0x8067);
4063         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
4064         rtl_writephy(tp, 0x13, 0x806f);
4065         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
4066         rtl_writephy(tp, 0x1f, 0x0000);
4067
4068         /* disable phy pfm mode */
4069         rtl_writephy(tp, 0x1f, 0x0a44);
4070         rtl_w0w1_phy(tp, 0x11, 0x0000, 0x0080);
4071         rtl_writephy(tp, 0x1f, 0x0000);
4072
4073         /* Check ALDPS bit, disable it if enabled */
4074         rtl_writephy(tp, 0x1f, 0x0a43);
4075         if (rtl_readphy(tp, 0x10) & 0x0004)
4076                 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
4077
4078         rtl_writephy(tp, 0x1f, 0x0000);
4079 }
4080
4081 static void rtl8168h_2_hw_phy_config(struct rtl8169_private *tp)
4082 {
4083         u16 ioffset_p3, ioffset_p2, ioffset_p1, ioffset_p0;
4084         u16 rlen;
4085         u32 data;
4086
4087         rtl_apply_firmware(tp);
4088
4089         /* CHIN EST parameter update */
4090         rtl_writephy(tp, 0x1f, 0x0a43);
4091         rtl_writephy(tp, 0x13, 0x808a);
4092         rtl_w0w1_phy(tp, 0x14, 0x000a, 0x003f);
4093         rtl_writephy(tp, 0x1f, 0x0000);
4094
4095         /* enable R-tune & PGA-retune function */
4096         rtl_writephy(tp, 0x1f, 0x0a43);
4097         rtl_writephy(tp, 0x13, 0x0811);
4098         rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
4099         rtl_writephy(tp, 0x1f, 0x0a42);
4100         rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
4101         rtl_writephy(tp, 0x1f, 0x0000);
4102
4103         /* enable GPHY 10M */
4104         rtl_writephy(tp, 0x1f, 0x0a44);
4105         rtl_w0w1_phy(tp, 0x11, 0x0800, 0x0000);
4106         rtl_writephy(tp, 0x1f, 0x0000);
4107
4108         r8168_mac_ocp_write(tp, 0xdd02, 0x807d);
4109         data = r8168_mac_ocp_read(tp, 0xdd02);
4110         ioffset_p3 = ((data & 0x80)>>7);
4111         ioffset_p3 <<= 3;
4112
4113         data = r8168_mac_ocp_read(tp, 0xdd00);
4114         ioffset_p3 |= ((data & (0xe000))>>13);
4115         ioffset_p2 = ((data & (0x1e00))>>9);
4116         ioffset_p1 = ((data & (0x01e0))>>5);
4117         ioffset_p0 = ((data & 0x0010)>>4);
4118         ioffset_p0 <<= 3;
4119         ioffset_p0 |= (data & (0x07));
4120         data = (ioffset_p3<<12)|(ioffset_p2<<8)|(ioffset_p1<<4)|(ioffset_p0);
4121
4122         if ((ioffset_p3 != 0x0f) || (ioffset_p2 != 0x0f) ||
4123             (ioffset_p1 != 0x0f) || (ioffset_p0 != 0x0f)) {
4124                 rtl_writephy(tp, 0x1f, 0x0bcf);
4125                 rtl_writephy(tp, 0x16, data);
4126                 rtl_writephy(tp, 0x1f, 0x0000);
4127         }
4128
4129         /* Modify rlen (TX LPF corner frequency) level */
4130         rtl_writephy(tp, 0x1f, 0x0bcd);
4131         data = rtl_readphy(tp, 0x16);
4132         data &= 0x000f;
4133         rlen = 0;
4134         if (data > 3)
4135                 rlen = data - 3;
4136         data = rlen | (rlen<<4) | (rlen<<8) | (rlen<<12);
4137         rtl_writephy(tp, 0x17, data);
4138         rtl_writephy(tp, 0x1f, 0x0bcd);
4139         rtl_writephy(tp, 0x1f, 0x0000);
4140
4141         /* disable phy pfm mode */
4142         rtl_writephy(tp, 0x1f, 0x0a44);
4143         rtl_w0w1_phy(tp, 0x11, 0x0000, 0x0080);
4144         rtl_writephy(tp, 0x1f, 0x0000);
4145
4146         /* Check ALDPS bit, disable it if enabled */
4147         rtl_writephy(tp, 0x1f, 0x0a43);
4148         if (rtl_readphy(tp, 0x10) & 0x0004)
4149                 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
4150
4151         rtl_writephy(tp, 0x1f, 0x0000);
4152 }
4153
4154 static void rtl8168ep_1_hw_phy_config(struct rtl8169_private *tp)
4155 {
4156         /* Enable PHY auto speed down */
4157         rtl_writephy(tp, 0x1f, 0x0a44);
4158         rtl_w0w1_phy(tp, 0x11, 0x000c, 0x0000);
4159         rtl_writephy(tp, 0x1f, 0x0000);
4160
4161         /* patch 10M & ALDPS */
4162         rtl_writephy(tp, 0x1f, 0x0bcc);
4163         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x0100);
4164         rtl_writephy(tp, 0x1f, 0x0a44);
4165         rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
4166         rtl_writephy(tp, 0x1f, 0x0a43);
4167         rtl_writephy(tp, 0x13, 0x8084);
4168         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
4169         rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
4170         rtl_writephy(tp, 0x1f, 0x0000);
4171
4172         /* Enable EEE auto-fallback function */
4173         rtl_writephy(tp, 0x1f, 0x0a4b);
4174         rtl_w0w1_phy(tp, 0x11, 0x0004, 0x0000);
4175         rtl_writephy(tp, 0x1f, 0x0000);
4176
4177         /* Enable UC LPF tune function */
4178         rtl_writephy(tp, 0x1f, 0x0a43);
4179         rtl_writephy(tp, 0x13, 0x8012);
4180         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
4181         rtl_writephy(tp, 0x1f, 0x0000);
4182
4183         /* set rg_sel_sdm_rate */
4184         rtl_writephy(tp, 0x1f, 0x0c42);
4185         rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
4186         rtl_writephy(tp, 0x1f, 0x0000);
4187
4188         /* Check ALDPS bit, disable it if enabled */
4189         rtl_writephy(tp, 0x1f, 0x0a43);
4190         if (rtl_readphy(tp, 0x10) & 0x0004)
4191                 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
4192
4193         rtl_writephy(tp, 0x1f, 0x0000);
4194 }
4195
4196 static void rtl8168ep_2_hw_phy_config(struct rtl8169_private *tp)
4197 {
4198         /* patch 10M & ALDPS */
4199         rtl_writephy(tp, 0x1f, 0x0bcc);
4200         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x0100);
4201         rtl_writephy(tp, 0x1f, 0x0a44);
4202         rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
4203         rtl_writephy(tp, 0x1f, 0x0a43);
4204         rtl_writephy(tp, 0x13, 0x8084);
4205         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
4206         rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
4207         rtl_writephy(tp, 0x1f, 0x0000);
4208
4209         /* Enable UC LPF tune function */
4210         rtl_writephy(tp, 0x1f, 0x0a43);
4211         rtl_writephy(tp, 0x13, 0x8012);
4212         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
4213         rtl_writephy(tp, 0x1f, 0x0000);
4214
4215         /* Set rg_sel_sdm_rate */
4216         rtl_writephy(tp, 0x1f, 0x0c42);
4217         rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
4218         rtl_writephy(tp, 0x1f, 0x0000);
4219
4220         /* Channel estimation parameters */
4221         rtl_writephy(tp, 0x1f, 0x0a43);
4222         rtl_writephy(tp, 0x13, 0x80f3);
4223         rtl_w0w1_phy(tp, 0x14, 0x8b00, ~0x8bff);
4224         rtl_writephy(tp, 0x13, 0x80f0);
4225         rtl_w0w1_phy(tp, 0x14, 0x3a00, ~0x3aff);
4226         rtl_writephy(tp, 0x13, 0x80ef);
4227         rtl_w0w1_phy(tp, 0x14, 0x0500, ~0x05ff);
4228         rtl_writephy(tp, 0x13, 0x80f6);
4229         rtl_w0w1_phy(tp, 0x14, 0x6e00, ~0x6eff);
4230         rtl_writephy(tp, 0x13, 0x80ec);
4231         rtl_w0w1_phy(tp, 0x14, 0x6800, ~0x68ff);
4232         rtl_writephy(tp, 0x13, 0x80ed);
4233         rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
4234         rtl_writephy(tp, 0x13, 0x80f2);
4235         rtl_w0w1_phy(tp, 0x14, 0xf400, ~0xf4ff);
4236         rtl_writephy(tp, 0x13, 0x80f4);
4237         rtl_w0w1_phy(tp, 0x14, 0x8500, ~0x85ff);
4238         rtl_writephy(tp, 0x1f, 0x0a43);
4239         rtl_writephy(tp, 0x13, 0x8110);
4240         rtl_w0w1_phy(tp, 0x14, 0xa800, ~0xa8ff);
4241         rtl_writephy(tp, 0x13, 0x810f);
4242         rtl_w0w1_phy(tp, 0x14, 0x1d00, ~0x1dff);
4243         rtl_writephy(tp, 0x13, 0x8111);
4244         rtl_w0w1_phy(tp, 0x14, 0xf500, ~0xf5ff);
4245         rtl_writephy(tp, 0x13, 0x8113);
4246         rtl_w0w1_phy(tp, 0x14, 0x6100, ~0x61ff);
4247         rtl_writephy(tp, 0x13, 0x8115);
4248         rtl_w0w1_phy(tp, 0x14, 0x9200, ~0x92ff);
4249         rtl_writephy(tp, 0x13, 0x810e);
4250         rtl_w0w1_phy(tp, 0x14, 0x0400, ~0x04ff);
4251         rtl_writephy(tp, 0x13, 0x810c);
4252         rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
4253         rtl_writephy(tp, 0x13, 0x810b);
4254         rtl_w0w1_phy(tp, 0x14, 0x5a00, ~0x5aff);
4255         rtl_writephy(tp, 0x1f, 0x0a43);
4256         rtl_writephy(tp, 0x13, 0x80d1);
4257         rtl_w0w1_phy(tp, 0x14, 0xff00, ~0xffff);
4258         rtl_writephy(tp, 0x13, 0x80cd);
4259         rtl_w0w1_phy(tp, 0x14, 0x9e00, ~0x9eff);
4260         rtl_writephy(tp, 0x13, 0x80d3);
4261         rtl_w0w1_phy(tp, 0x14, 0x0e00, ~0x0eff);
4262         rtl_writephy(tp, 0x13, 0x80d5);
4263         rtl_w0w1_phy(tp, 0x14, 0xca00, ~0xcaff);
4264         rtl_writephy(tp, 0x13, 0x80d7);
4265         rtl_w0w1_phy(tp, 0x14, 0x8400, ~0x84ff);
4266
4267         /* Force PWM-mode */
4268         rtl_writephy(tp, 0x1f, 0x0bcd);
4269         rtl_writephy(tp, 0x14, 0x5065);
4270         rtl_writephy(tp, 0x14, 0xd065);
4271         rtl_writephy(tp, 0x1f, 0x0bc8);
4272         rtl_writephy(tp, 0x12, 0x00ed);
4273         rtl_writephy(tp, 0x1f, 0x0bcd);
4274         rtl_writephy(tp, 0x14, 0x1065);
4275         rtl_writephy(tp, 0x14, 0x9065);
4276         rtl_writephy(tp, 0x14, 0x1065);
4277         rtl_writephy(tp, 0x1f, 0x0000);
4278
4279         /* Check ALDPS bit, disable it if enabled */
4280         rtl_writephy(tp, 0x1f, 0x0a43);
4281         if (rtl_readphy(tp, 0x10) & 0x0004)
4282                 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
4283
4284         rtl_writephy(tp, 0x1f, 0x0000);
4285 }
4286
4287 static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
4288 {
4289         static const struct phy_reg phy_reg_init[] = {
4290                 { 0x1f, 0x0003 },
4291                 { 0x08, 0x441d },
4292                 { 0x01, 0x9100 },
4293                 { 0x1f, 0x0000 }
4294         };
4295
4296         rtl_writephy(tp, 0x1f, 0x0000);
4297         rtl_patchphy(tp, 0x11, 1 << 12);
4298         rtl_patchphy(tp, 0x19, 1 << 13);
4299         rtl_patchphy(tp, 0x10, 1 << 15);
4300
4301         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
4302 }
4303
4304 static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
4305 {
4306         static const struct phy_reg phy_reg_init[] = {
4307                 { 0x1f, 0x0005 },
4308                 { 0x1a, 0x0000 },
4309                 { 0x1f, 0x0000 },
4310
4311                 { 0x1f, 0x0004 },
4312                 { 0x1c, 0x0000 },
4313                 { 0x1f, 0x0000 },
4314
4315                 { 0x1f, 0x0001 },
4316                 { 0x15, 0x7701 },
4317                 { 0x1f, 0x0000 }
4318         };
4319
4320         /* Disable ALDPS before ram code */
4321         rtl_writephy(tp, 0x1f, 0x0000);
4322         rtl_writephy(tp, 0x18, 0x0310);
4323         msleep(100);
4324
4325         rtl_apply_firmware(tp);
4326
4327         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
4328 }
4329
4330 static void rtl8402_hw_phy_config(struct rtl8169_private *tp)
4331 {
4332         /* Disable ALDPS before setting firmware */
4333         rtl_writephy(tp, 0x1f, 0x0000);
4334         rtl_writephy(tp, 0x18, 0x0310);
4335         msleep(20);
4336
4337         rtl_apply_firmware(tp);
4338
4339         /* EEE setting */
4340         rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4341         rtl_writephy(tp, 0x1f, 0x0004);
4342         rtl_writephy(tp, 0x10, 0x401f);
4343         rtl_writephy(tp, 0x19, 0x7030);
4344         rtl_writephy(tp, 0x1f, 0x0000);
4345 }
4346
4347 static void rtl8106e_hw_phy_config(struct rtl8169_private *tp)
4348 {
4349         static const struct phy_reg phy_reg_init[] = {
4350                 { 0x1f, 0x0004 },
4351                 { 0x10, 0xc07f },
4352                 { 0x19, 0x7030 },
4353                 { 0x1f, 0x0000 }
4354         };
4355
4356         /* Disable ALDPS before ram code */
4357         rtl_writephy(tp, 0x1f, 0x0000);
4358         rtl_writephy(tp, 0x18, 0x0310);
4359         msleep(100);
4360
4361         rtl_apply_firmware(tp);
4362
4363         rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4364         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
4365
4366         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4367 }
4368
4369 static void rtl_hw_phy_config(struct net_device *dev)
4370 {
4371         struct rtl8169_private *tp = netdev_priv(dev);
4372
4373         rtl8169_print_mac_version(tp);
4374
4375         switch (tp->mac_version) {
4376         case RTL_GIGA_MAC_VER_01:
4377                 break;
4378         case RTL_GIGA_MAC_VER_02:
4379         case RTL_GIGA_MAC_VER_03:
4380                 rtl8169s_hw_phy_config(tp);
4381                 break;
4382         case RTL_GIGA_MAC_VER_04:
4383                 rtl8169sb_hw_phy_config(tp);
4384                 break;
4385         case RTL_GIGA_MAC_VER_05:
4386                 rtl8169scd_hw_phy_config(tp);
4387                 break;
4388         case RTL_GIGA_MAC_VER_06:
4389                 rtl8169sce_hw_phy_config(tp);
4390                 break;
4391         case RTL_GIGA_MAC_VER_07:
4392         case RTL_GIGA_MAC_VER_08:
4393         case RTL_GIGA_MAC_VER_09:
4394                 rtl8102e_hw_phy_config(tp);
4395                 break;
4396         case RTL_GIGA_MAC_VER_11:
4397                 rtl8168bb_hw_phy_config(tp);
4398                 break;
4399         case RTL_GIGA_MAC_VER_12:
4400                 rtl8168bef_hw_phy_config(tp);
4401                 break;
4402         case RTL_GIGA_MAC_VER_17:
4403                 rtl8168bef_hw_phy_config(tp);
4404                 break;
4405         case RTL_GIGA_MAC_VER_18:
4406                 rtl8168cp_1_hw_phy_config(tp);
4407                 break;
4408         case RTL_GIGA_MAC_VER_19:
4409                 rtl8168c_1_hw_phy_config(tp);
4410                 break;
4411         case RTL_GIGA_MAC_VER_20:
4412                 rtl8168c_2_hw_phy_config(tp);
4413                 break;
4414         case RTL_GIGA_MAC_VER_21:
4415                 rtl8168c_3_hw_phy_config(tp);
4416                 break;
4417         case RTL_GIGA_MAC_VER_22:
4418                 rtl8168c_4_hw_phy_config(tp);
4419                 break;
4420         case RTL_GIGA_MAC_VER_23:
4421         case RTL_GIGA_MAC_VER_24:
4422                 rtl8168cp_2_hw_phy_config(tp);
4423                 break;
4424         case RTL_GIGA_MAC_VER_25:
4425                 rtl8168d_1_hw_phy_config(tp);
4426                 break;
4427         case RTL_GIGA_MAC_VER_26:
4428                 rtl8168d_2_hw_phy_config(tp);
4429                 break;
4430         case RTL_GIGA_MAC_VER_27:
4431                 rtl8168d_3_hw_phy_config(tp);
4432                 break;
4433         case RTL_GIGA_MAC_VER_28:
4434                 rtl8168d_4_hw_phy_config(tp);
4435                 break;
4436         case RTL_GIGA_MAC_VER_29:
4437         case RTL_GIGA_MAC_VER_30:
4438                 rtl8105e_hw_phy_config(tp);
4439                 break;
4440         case RTL_GIGA_MAC_VER_31:
4441                 /* None. */
4442                 break;
4443         case RTL_GIGA_MAC_VER_32:
4444         case RTL_GIGA_MAC_VER_33:
4445                 rtl8168e_1_hw_phy_config(tp);
4446                 break;
4447         case RTL_GIGA_MAC_VER_34:
4448                 rtl8168e_2_hw_phy_config(tp);
4449                 break;
4450         case RTL_GIGA_MAC_VER_35:
4451                 rtl8168f_1_hw_phy_config(tp);
4452                 break;
4453         case RTL_GIGA_MAC_VER_36:
4454                 rtl8168f_2_hw_phy_config(tp);
4455                 break;
4456
4457         case RTL_GIGA_MAC_VER_37:
4458                 rtl8402_hw_phy_config(tp);
4459                 break;
4460
4461         case RTL_GIGA_MAC_VER_38:
4462                 rtl8411_hw_phy_config(tp);
4463                 break;
4464
4465         case RTL_GIGA_MAC_VER_39:
4466                 rtl8106e_hw_phy_config(tp);
4467                 break;
4468
4469         case RTL_GIGA_MAC_VER_40:
4470                 rtl8168g_1_hw_phy_config(tp);
4471                 break;
4472         case RTL_GIGA_MAC_VER_42:
4473         case RTL_GIGA_MAC_VER_43:
4474         case RTL_GIGA_MAC_VER_44:
4475                 rtl8168g_2_hw_phy_config(tp);
4476                 break;
4477         case RTL_GIGA_MAC_VER_45:
4478         case RTL_GIGA_MAC_VER_47:
4479                 rtl8168h_1_hw_phy_config(tp);
4480                 break;
4481         case RTL_GIGA_MAC_VER_46:
4482         case RTL_GIGA_MAC_VER_48:
4483                 rtl8168h_2_hw_phy_config(tp);
4484                 break;
4485
4486         case RTL_GIGA_MAC_VER_49:
4487                 rtl8168ep_1_hw_phy_config(tp);
4488                 break;
4489         case RTL_GIGA_MAC_VER_50:
4490         case RTL_GIGA_MAC_VER_51:
4491                 rtl8168ep_2_hw_phy_config(tp);
4492                 break;
4493
4494         case RTL_GIGA_MAC_VER_41:
4495         default:
4496                 break;
4497         }
4498 }
4499
4500 static void rtl_phy_work(struct rtl8169_private *tp)
4501 {
4502         struct timer_list *timer = &tp->timer;
4503         unsigned long timeout = RTL8169_PHY_TIMEOUT;
4504
4505         assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
4506
4507         if (tp->phy_reset_pending(tp)) {
4508                 /*
4509                  * A busy loop could burn quite a few cycles on nowadays CPU.
4510                  * Let's delay the execution of the timer for a few ticks.
4511                  */
4512                 timeout = HZ/10;
4513                 goto out_mod_timer;
4514         }
4515
4516         if (tp->link_ok(tp))
4517                 return;
4518
4519         netif_dbg(tp, link, tp->dev, "PHY reset until link up\n");
4520
4521         tp->phy_reset_enable(tp);
4522
4523 out_mod_timer:
4524         mod_timer(timer, jiffies + timeout);
4525 }
4526
4527 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
4528 {
4529         if (!test_and_set_bit(flag, tp->wk.flags))
4530                 schedule_work(&tp->wk.work);
4531 }
4532
4533 static void rtl8169_phy_timer(struct timer_list *t)
4534 {
4535         struct rtl8169_private *tp = from_timer(tp, t, timer);
4536
4537         rtl_schedule_task(tp, RTL_FLAG_TASK_PHY_PENDING);
4538 }
4539
4540 DECLARE_RTL_COND(rtl_phy_reset_cond)
4541 {
4542         return tp->phy_reset_pending(tp);
4543 }
4544
4545 static void rtl8169_phy_reset(struct net_device *dev,
4546                               struct rtl8169_private *tp)
4547 {
4548         tp->phy_reset_enable(tp);
4549         rtl_msleep_loop_wait_low(tp, &rtl_phy_reset_cond, 1, 100);
4550 }
4551
4552 static bool rtl_tbi_enabled(struct rtl8169_private *tp)
4553 {
4554         return (tp->mac_version == RTL_GIGA_MAC_VER_01) &&
4555             (RTL_R8(tp, PHYstatus) & TBI_Enable);
4556 }
4557
4558 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
4559 {
4560         rtl_hw_phy_config(dev);
4561
4562         if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
4563                 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
4564                 RTL_W8(tp, 0x82, 0x01);
4565         }
4566
4567         pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
4568
4569         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
4570                 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4571
4572         if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
4573                 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
4574                 RTL_W8(tp, 0x82, 0x01);
4575                 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
4576                 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
4577         }
4578
4579         rtl8169_phy_reset(dev, tp);
4580
4581         rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
4582                           ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
4583                           ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
4584                           (tp->mii.supports_gmii ?
4585                            ADVERTISED_1000baseT_Half |
4586                            ADVERTISED_1000baseT_Full : 0));
4587
4588         if (rtl_tbi_enabled(tp))
4589                 netif_info(tp, link, dev, "TBI auto-negotiating\n");
4590 }
4591
4592 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
4593 {
4594         rtl_lock_work(tp);
4595
4596         RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
4597
4598         RTL_W32(tp, MAC4, addr[4] | addr[5] << 8);
4599         RTL_R32(tp, MAC4);
4600
4601         RTL_W32(tp, MAC0, addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24);
4602         RTL_R32(tp, MAC0);
4603
4604         if (tp->mac_version == RTL_GIGA_MAC_VER_34)
4605                 rtl_rar_exgmac_set(tp, addr);
4606
4607         RTL_W8(tp, Cfg9346, Cfg9346_Lock);
4608
4609         rtl_unlock_work(tp);
4610 }
4611
4612 static int rtl_set_mac_address(struct net_device *dev, void *p)
4613 {
4614         struct rtl8169_private *tp = netdev_priv(dev);
4615         struct device *d = tp_to_dev(tp);
4616         int ret;
4617
4618         ret = eth_mac_addr(dev, p);
4619         if (ret)
4620                 return ret;
4621
4622         pm_runtime_get_noresume(d);
4623
4624         if (pm_runtime_active(d))
4625                 rtl_rar_set(tp, dev->dev_addr);
4626
4627         pm_runtime_put_noidle(d);
4628
4629         return 0;
4630 }
4631
4632 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
4633 {
4634         struct rtl8169_private *tp = netdev_priv(dev);
4635         struct mii_ioctl_data *data = if_mii(ifr);
4636
4637         return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
4638 }
4639
4640 static int rtl_xmii_ioctl(struct rtl8169_private *tp,
4641                           struct mii_ioctl_data *data, int cmd)
4642 {
4643         switch (cmd) {
4644         case SIOCGMIIPHY:
4645                 data->phy_id = 32; /* Internal PHY */
4646                 return 0;
4647
4648         case SIOCGMIIREG:
4649                 data->val_out = rtl_readphy(tp, data->reg_num & 0x1f);
4650                 return 0;
4651
4652         case SIOCSMIIREG:
4653                 rtl_writephy(tp, data->reg_num & 0x1f, data->val_in);
4654                 return 0;
4655         }
4656         return -EOPNOTSUPP;
4657 }
4658
4659 static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
4660 {
4661         return -EOPNOTSUPP;
4662 }
4663
4664 static void rtl_init_mdio_ops(struct rtl8169_private *tp)
4665 {
4666         struct mdio_ops *ops = &tp->mdio_ops;
4667
4668         switch (tp->mac_version) {
4669         case RTL_GIGA_MAC_VER_27:
4670                 ops->write      = r8168dp_1_mdio_write;
4671                 ops->read       = r8168dp_1_mdio_read;
4672                 break;
4673         case RTL_GIGA_MAC_VER_28:
4674         case RTL_GIGA_MAC_VER_31:
4675                 ops->write      = r8168dp_2_mdio_write;
4676                 ops->read       = r8168dp_2_mdio_read;
4677                 break;
4678         case RTL_GIGA_MAC_VER_40:
4679         case RTL_GIGA_MAC_VER_41:
4680         case RTL_GIGA_MAC_VER_42:
4681         case RTL_GIGA_MAC_VER_43:
4682         case RTL_GIGA_MAC_VER_44:
4683         case RTL_GIGA_MAC_VER_45:
4684         case RTL_GIGA_MAC_VER_46:
4685         case RTL_GIGA_MAC_VER_47:
4686         case RTL_GIGA_MAC_VER_48:
4687         case RTL_GIGA_MAC_VER_49:
4688         case RTL_GIGA_MAC_VER_50:
4689         case RTL_GIGA_MAC_VER_51:
4690                 ops->write      = r8168g_mdio_write;
4691                 ops->read       = r8168g_mdio_read;
4692                 break;
4693         default:
4694                 ops->write      = r8169_mdio_write;
4695                 ops->read       = r8169_mdio_read;
4696                 break;
4697         }
4698 }
4699
4700 static void rtl_speed_down(struct rtl8169_private *tp)
4701 {
4702         u32 adv;
4703         int lpa;
4704
4705         rtl_writephy(tp, 0x1f, 0x0000);
4706         lpa = rtl_readphy(tp, MII_LPA);
4707
4708         if (lpa & (LPA_10HALF | LPA_10FULL))
4709                 adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full;
4710         else if (lpa & (LPA_100HALF | LPA_100FULL))
4711                 adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
4712                       ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full;
4713         else
4714                 adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
4715                       ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
4716                       (tp->mii.supports_gmii ?
4717                        ADVERTISED_1000baseT_Half |
4718                        ADVERTISED_1000baseT_Full : 0);
4719
4720         rtl8169_set_speed(tp->dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
4721                           adv);
4722 }
4723
4724 static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
4725 {
4726         switch (tp->mac_version) {
4727         case RTL_GIGA_MAC_VER_25:
4728         case RTL_GIGA_MAC_VER_26:
4729         case RTL_GIGA_MAC_VER_29:
4730         case RTL_GIGA_MAC_VER_30:
4731         case RTL_GIGA_MAC_VER_32:
4732         case RTL_GIGA_MAC_VER_33:
4733         case RTL_GIGA_MAC_VER_34:
4734         case RTL_GIGA_MAC_VER_37:
4735         case RTL_GIGA_MAC_VER_38:
4736         case RTL_GIGA_MAC_VER_39:
4737         case RTL_GIGA_MAC_VER_40:
4738         case RTL_GIGA_MAC_VER_41:
4739         case RTL_GIGA_MAC_VER_42:
4740         case RTL_GIGA_MAC_VER_43:
4741         case RTL_GIGA_MAC_VER_44:
4742         case RTL_GIGA_MAC_VER_45:
4743         case RTL_GIGA_MAC_VER_46:
4744         case RTL_GIGA_MAC_VER_47:
4745         case RTL_GIGA_MAC_VER_48:
4746         case RTL_GIGA_MAC_VER_49:
4747         case RTL_GIGA_MAC_VER_50:
4748         case RTL_GIGA_MAC_VER_51:
4749                 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) |
4750                         AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
4751                 break;
4752         default:
4753                 break;
4754         }
4755 }
4756
4757 static bool rtl_wol_pll_power_down(struct rtl8169_private *tp)
4758 {
4759         if (!(__rtl8169_get_wol(tp) & WAKE_ANY))
4760                 return false;
4761
4762         rtl_speed_down(tp);
4763         rtl_wol_suspend_quirk(tp);
4764
4765         return true;
4766 }
4767
4768 static void r810x_phy_power_down(struct rtl8169_private *tp)
4769 {
4770         rtl_writephy(tp, 0x1f, 0x0000);
4771         rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
4772 }
4773
4774 static void r810x_phy_power_up(struct rtl8169_private *tp)
4775 {
4776         rtl_writephy(tp, 0x1f, 0x0000);
4777         rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
4778 }
4779
4780 static void r810x_pll_power_down(struct rtl8169_private *tp)
4781 {
4782         if (rtl_wol_pll_power_down(tp))
4783                 return;
4784
4785         r810x_phy_power_down(tp);
4786
4787         switch (tp->mac_version) {
4788         case RTL_GIGA_MAC_VER_07:
4789         case RTL_GIGA_MAC_VER_08:
4790         case RTL_GIGA_MAC_VER_09:
4791         case RTL_GIGA_MAC_VER_10:
4792         case RTL_GIGA_MAC_VER_13:
4793         case RTL_GIGA_MAC_VER_16:
4794                 break;
4795         default:
4796                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80);
4797                 break;
4798         }
4799 }
4800
4801 static void r810x_pll_power_up(struct rtl8169_private *tp)
4802 {
4803         r810x_phy_power_up(tp);
4804
4805         switch (tp->mac_version) {
4806         case RTL_GIGA_MAC_VER_07:
4807         case RTL_GIGA_MAC_VER_08:
4808         case RTL_GIGA_MAC_VER_09:
4809         case RTL_GIGA_MAC_VER_10:
4810         case RTL_GIGA_MAC_VER_13:
4811         case RTL_GIGA_MAC_VER_16:
4812                 break;
4813         case RTL_GIGA_MAC_VER_47:
4814         case RTL_GIGA_MAC_VER_48:
4815                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0);
4816                 break;
4817         default:
4818                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0x80);
4819                 break;
4820         }
4821 }
4822
4823 static void r8168_phy_power_up(struct rtl8169_private *tp)
4824 {
4825         rtl_writephy(tp, 0x1f, 0x0000);
4826         switch (tp->mac_version) {
4827         case RTL_GIGA_MAC_VER_11:
4828         case RTL_GIGA_MAC_VER_12:
4829         case RTL_GIGA_MAC_VER_17:
4830         case RTL_GIGA_MAC_VER_18:
4831         case RTL_GIGA_MAC_VER_19:
4832         case RTL_GIGA_MAC_VER_20:
4833         case RTL_GIGA_MAC_VER_21:
4834         case RTL_GIGA_MAC_VER_22:
4835         case RTL_GIGA_MAC_VER_23:
4836         case RTL_GIGA_MAC_VER_24:
4837         case RTL_GIGA_MAC_VER_25:
4838         case RTL_GIGA_MAC_VER_26:
4839         case RTL_GIGA_MAC_VER_27:
4840         case RTL_GIGA_MAC_VER_28:
4841         case RTL_GIGA_MAC_VER_31:
4842                 rtl_writephy(tp, 0x0e, 0x0000);
4843                 break;
4844         default:
4845                 break;
4846         }
4847         rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
4848 }
4849
4850 static void r8168_phy_power_down(struct rtl8169_private *tp)
4851 {
4852         rtl_writephy(tp, 0x1f, 0x0000);
4853         switch (tp->mac_version) {
4854         case RTL_GIGA_MAC_VER_32:
4855         case RTL_GIGA_MAC_VER_33:
4856         case RTL_GIGA_MAC_VER_40:
4857         case RTL_GIGA_MAC_VER_41:
4858                 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_PDOWN);
4859                 break;
4860
4861         case RTL_GIGA_MAC_VER_11:
4862         case RTL_GIGA_MAC_VER_12:
4863         case RTL_GIGA_MAC_VER_17:
4864         case RTL_GIGA_MAC_VER_18:
4865         case RTL_GIGA_MAC_VER_19:
4866         case RTL_GIGA_MAC_VER_20:
4867         case RTL_GIGA_MAC_VER_21:
4868         case RTL_GIGA_MAC_VER_22:
4869         case RTL_GIGA_MAC_VER_23:
4870         case RTL_GIGA_MAC_VER_24:
4871         case RTL_GIGA_MAC_VER_25:
4872         case RTL_GIGA_MAC_VER_26:
4873         case RTL_GIGA_MAC_VER_27:
4874         case RTL_GIGA_MAC_VER_28:
4875         case RTL_GIGA_MAC_VER_31:
4876                 rtl_writephy(tp, 0x0e, 0x0200);
4877         default:
4878                 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
4879                 break;
4880         }
4881 }
4882
4883 static void r8168_pll_power_down(struct rtl8169_private *tp)
4884 {
4885         if (r8168_check_dash(tp))
4886                 return;
4887
4888         if ((tp->mac_version == RTL_GIGA_MAC_VER_23 ||
4889              tp->mac_version == RTL_GIGA_MAC_VER_24) &&
4890             (RTL_R16(tp, CPlusCmd) & ASF)) {
4891                 return;
4892         }
4893
4894         if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
4895             tp->mac_version == RTL_GIGA_MAC_VER_33)
4896                 rtl_ephy_write(tp, 0x19, 0xff64);
4897
4898         if (rtl_wol_pll_power_down(tp))
4899                 return;
4900
4901         r8168_phy_power_down(tp);
4902
4903         switch (tp->mac_version) {
4904         case RTL_GIGA_MAC_VER_25:
4905         case RTL_GIGA_MAC_VER_26:
4906         case RTL_GIGA_MAC_VER_27:
4907         case RTL_GIGA_MAC_VER_28:
4908         case RTL_GIGA_MAC_VER_31:
4909         case RTL_GIGA_MAC_VER_32:
4910         case RTL_GIGA_MAC_VER_33:
4911         case RTL_GIGA_MAC_VER_44:
4912         case RTL_GIGA_MAC_VER_45:
4913         case RTL_GIGA_MAC_VER_46:
4914         case RTL_GIGA_MAC_VER_50:
4915         case RTL_GIGA_MAC_VER_51:
4916                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80);
4917                 break;
4918         case RTL_GIGA_MAC_VER_40:
4919         case RTL_GIGA_MAC_VER_41:
4920         case RTL_GIGA_MAC_VER_49:
4921                 rtl_w0w1_eri(tp, 0x1a8, ERIAR_MASK_1111, 0x00000000,
4922                              0xfc000000, ERIAR_EXGMAC);
4923                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80);
4924                 break;
4925         }
4926 }
4927
4928 static void r8168_pll_power_up(struct rtl8169_private *tp)
4929 {
4930         switch (tp->mac_version) {
4931         case RTL_GIGA_MAC_VER_25:
4932         case RTL_GIGA_MAC_VER_26:
4933         case RTL_GIGA_MAC_VER_27:
4934         case RTL_GIGA_MAC_VER_28:
4935         case RTL_GIGA_MAC_VER_31:
4936         case RTL_GIGA_MAC_VER_32:
4937         case RTL_GIGA_MAC_VER_33:
4938                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0x80);
4939                 break;
4940         case RTL_GIGA_MAC_VER_44:
4941         case RTL_GIGA_MAC_VER_45:
4942         case RTL_GIGA_MAC_VER_46:
4943         case RTL_GIGA_MAC_VER_50:
4944         case RTL_GIGA_MAC_VER_51:
4945                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0);
4946                 break;
4947         case RTL_GIGA_MAC_VER_40:
4948         case RTL_GIGA_MAC_VER_41:
4949         case RTL_GIGA_MAC_VER_49:
4950                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0);
4951                 rtl_w0w1_eri(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000,
4952                              0x00000000, ERIAR_EXGMAC);
4953                 break;
4954         }
4955
4956         r8168_phy_power_up(tp);
4957 }
4958
4959 static void rtl_generic_op(struct rtl8169_private *tp,
4960                            void (*op)(struct rtl8169_private *))
4961 {
4962         if (op)
4963                 op(tp);
4964 }
4965
4966 static void rtl_pll_power_down(struct rtl8169_private *tp)
4967 {
4968         rtl_generic_op(tp, tp->pll_power_ops.down);
4969 }
4970
4971 static void rtl_pll_power_up(struct rtl8169_private *tp)
4972 {
4973         rtl_generic_op(tp, tp->pll_power_ops.up);
4974 }
4975
4976 static void rtl_init_pll_power_ops(struct rtl8169_private *tp)
4977 {
4978         struct pll_power_ops *ops = &tp->pll_power_ops;
4979
4980         switch (tp->mac_version) {
4981         case RTL_GIGA_MAC_VER_07:
4982         case RTL_GIGA_MAC_VER_08:
4983         case RTL_GIGA_MAC_VER_09:
4984         case RTL_GIGA_MAC_VER_10:
4985         case RTL_GIGA_MAC_VER_16:
4986         case RTL_GIGA_MAC_VER_29:
4987         case RTL_GIGA_MAC_VER_30:
4988         case RTL_GIGA_MAC_VER_37:
4989         case RTL_GIGA_MAC_VER_39:
4990         case RTL_GIGA_MAC_VER_43:
4991         case RTL_GIGA_MAC_VER_47:
4992         case RTL_GIGA_MAC_VER_48:
4993                 ops->down       = r810x_pll_power_down;
4994                 ops->up         = r810x_pll_power_up;
4995                 break;
4996
4997         case RTL_GIGA_MAC_VER_11:
4998         case RTL_GIGA_MAC_VER_12:
4999         case RTL_GIGA_MAC_VER_17:
5000         case RTL_GIGA_MAC_VER_18:
5001         case RTL_GIGA_MAC_VER_19:
5002         case RTL_GIGA_MAC_VER_20:
5003         case RTL_GIGA_MAC_VER_21:
5004         case RTL_GIGA_MAC_VER_22:
5005         case RTL_GIGA_MAC_VER_23:
5006         case RTL_GIGA_MAC_VER_24:
5007         case RTL_GIGA_MAC_VER_25:
5008         case RTL_GIGA_MAC_VER_26:
5009         case RTL_GIGA_MAC_VER_27:
5010         case RTL_GIGA_MAC_VER_28:
5011         case RTL_GIGA_MAC_VER_31:
5012         case RTL_GIGA_MAC_VER_32:
5013         case RTL_GIGA_MAC_VER_33:
5014         case RTL_GIGA_MAC_VER_34:
5015         case RTL_GIGA_MAC_VER_35:
5016         case RTL_GIGA_MAC_VER_36:
5017         case RTL_GIGA_MAC_VER_38:
5018         case RTL_GIGA_MAC_VER_40:
5019         case RTL_GIGA_MAC_VER_41:
5020         case RTL_GIGA_MAC_VER_42:
5021         case RTL_GIGA_MAC_VER_44:
5022         case RTL_GIGA_MAC_VER_45:
5023         case RTL_GIGA_MAC_VER_46:
5024         case RTL_GIGA_MAC_VER_49:
5025         case RTL_GIGA_MAC_VER_50:
5026         case RTL_GIGA_MAC_VER_51:
5027                 ops->down       = r8168_pll_power_down;
5028                 ops->up         = r8168_pll_power_up;
5029                 break;
5030
5031         default:
5032                 ops->down       = NULL;
5033                 ops->up         = NULL;
5034                 break;
5035         }
5036 }
5037
5038 static void rtl_init_rxcfg(struct rtl8169_private *tp)
5039 {
5040         switch (tp->mac_version) {
5041         case RTL_GIGA_MAC_VER_01:
5042         case RTL_GIGA_MAC_VER_02:
5043         case RTL_GIGA_MAC_VER_03:
5044         case RTL_GIGA_MAC_VER_04:
5045         case RTL_GIGA_MAC_VER_05:
5046         case RTL_GIGA_MAC_VER_06:
5047         case RTL_GIGA_MAC_VER_10:
5048         case RTL_GIGA_MAC_VER_11:
5049         case RTL_GIGA_MAC_VER_12:
5050         case RTL_GIGA_MAC_VER_13:
5051         case RTL_GIGA_MAC_VER_14:
5052         case RTL_GIGA_MAC_VER_15:
5053         case RTL_GIGA_MAC_VER_16:
5054         case RTL_GIGA_MAC_VER_17:
5055                 RTL_W32(tp, RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
5056                 break;
5057         case RTL_GIGA_MAC_VER_18:
5058         case RTL_GIGA_MAC_VER_19:
5059         case RTL_GIGA_MAC_VER_20:
5060         case RTL_GIGA_MAC_VER_21:
5061         case RTL_GIGA_MAC_VER_22:
5062         case RTL_GIGA_MAC_VER_23:
5063         case RTL_GIGA_MAC_VER_24:
5064         case RTL_GIGA_MAC_VER_34:
5065         case RTL_GIGA_MAC_VER_35:
5066                 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
5067                 break;
5068         case RTL_GIGA_MAC_VER_40:
5069         case RTL_GIGA_MAC_VER_41:
5070         case RTL_GIGA_MAC_VER_42:
5071         case RTL_GIGA_MAC_VER_43:
5072         case RTL_GIGA_MAC_VER_44:
5073         case RTL_GIGA_MAC_VER_45:
5074         case RTL_GIGA_MAC_VER_46:
5075         case RTL_GIGA_MAC_VER_47:
5076         case RTL_GIGA_MAC_VER_48:
5077         case RTL_GIGA_MAC_VER_49:
5078         case RTL_GIGA_MAC_VER_50:
5079         case RTL_GIGA_MAC_VER_51:
5080                 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF);
5081                 break;
5082         default:
5083                 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_DMA_BURST);
5084                 break;
5085         }
5086 }
5087
5088 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
5089 {
5090         tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0;
5091 }
5092
5093 static void rtl_hw_jumbo_enable(struct rtl8169_private *tp)
5094 {
5095         RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
5096         rtl_generic_op(tp, tp->jumbo_ops.enable);
5097         RTL_W8(tp, Cfg9346, Cfg9346_Lock);
5098 }
5099
5100 static void rtl_hw_jumbo_disable(struct rtl8169_private *tp)
5101 {
5102         RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
5103         rtl_generic_op(tp, tp->jumbo_ops.disable);
5104         RTL_W8(tp, Cfg9346, Cfg9346_Lock);
5105 }
5106
5107 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
5108 {
5109         RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
5110         RTL_W8(tp, Config4, RTL_R8(tp, Config4) | Jumbo_En1);
5111         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_512B);
5112 }
5113
5114 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
5115 {
5116         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
5117         RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~Jumbo_En1);
5118         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5119 }
5120
5121 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
5122 {
5123         RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
5124 }
5125
5126 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
5127 {
5128         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
5129 }
5130
5131 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
5132 {
5133         RTL_W8(tp, MaxTxPacketSize, 0x3f);
5134         RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
5135         RTL_W8(tp, Config4, RTL_R8(tp, Config4) | 0x01);
5136         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_512B);
5137 }
5138
5139 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
5140 {
5141         RTL_W8(tp, MaxTxPacketSize, 0x0c);
5142         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
5143         RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~0x01);
5144         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5145 }
5146
5147 static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp)
5148 {
5149         rtl_tx_performance_tweak(tp,
5150                 PCI_EXP_DEVCTL_READRQ_512B | PCI_EXP_DEVCTL_NOSNOOP_EN);
5151 }
5152
5153 static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp)
5154 {
5155         rtl_tx_performance_tweak(tp,
5156                 PCI_EXP_DEVCTL_READRQ_4096B | PCI_EXP_DEVCTL_NOSNOOP_EN);
5157 }
5158
5159 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
5160 {
5161         r8168b_0_hw_jumbo_enable(tp);
5162
5163         RTL_W8(tp, Config4, RTL_R8(tp, Config4) | (1 << 0));
5164 }
5165
5166 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
5167 {
5168         r8168b_0_hw_jumbo_disable(tp);
5169
5170         RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0));
5171 }
5172
5173 static void rtl_init_jumbo_ops(struct rtl8169_private *tp)
5174 {
5175         struct jumbo_ops *ops = &tp->jumbo_ops;
5176
5177         switch (tp->mac_version) {
5178         case RTL_GIGA_MAC_VER_11:
5179                 ops->disable    = r8168b_0_hw_jumbo_disable;
5180                 ops->enable     = r8168b_0_hw_jumbo_enable;
5181                 break;
5182         case RTL_GIGA_MAC_VER_12:
5183         case RTL_GIGA_MAC_VER_17:
5184                 ops->disable    = r8168b_1_hw_jumbo_disable;
5185                 ops->enable     = r8168b_1_hw_jumbo_enable;
5186                 break;
5187         case RTL_GIGA_MAC_VER_18: /* Wild guess. Needs info from Realtek. */
5188         case RTL_GIGA_MAC_VER_19:
5189         case RTL_GIGA_MAC_VER_20:
5190         case RTL_GIGA_MAC_VER_21: /* Wild guess. Needs info from Realtek. */
5191         case RTL_GIGA_MAC_VER_22:
5192         case RTL_GIGA_MAC_VER_23:
5193         case RTL_GIGA_MAC_VER_24:
5194         case RTL_GIGA_MAC_VER_25:
5195         case RTL_GIGA_MAC_VER_26:
5196                 ops->disable    = r8168c_hw_jumbo_disable;
5197                 ops->enable     = r8168c_hw_jumbo_enable;
5198                 break;
5199         case RTL_GIGA_MAC_VER_27:
5200         case RTL_GIGA_MAC_VER_28:
5201                 ops->disable    = r8168dp_hw_jumbo_disable;
5202                 ops->enable     = r8168dp_hw_jumbo_enable;
5203                 break;
5204         case RTL_GIGA_MAC_VER_31: /* Wild guess. Needs info from Realtek. */
5205         case RTL_GIGA_MAC_VER_32:
5206         case RTL_GIGA_MAC_VER_33:
5207         case RTL_GIGA_MAC_VER_34:
5208                 ops->disable    = r8168e_hw_jumbo_disable;
5209                 ops->enable     = r8168e_hw_jumbo_enable;
5210                 break;
5211
5212         /*
5213          * No action needed for jumbo frames with 8169.
5214          * No jumbo for 810x at all.
5215          */
5216         case RTL_GIGA_MAC_VER_40:
5217         case RTL_GIGA_MAC_VER_41:
5218         case RTL_GIGA_MAC_VER_42:
5219         case RTL_GIGA_MAC_VER_43:
5220         case RTL_GIGA_MAC_VER_44:
5221         case RTL_GIGA_MAC_VER_45:
5222         case RTL_GIGA_MAC_VER_46:
5223         case RTL_GIGA_MAC_VER_47:
5224         case RTL_GIGA_MAC_VER_48:
5225         case RTL_GIGA_MAC_VER_49:
5226         case RTL_GIGA_MAC_VER_50:
5227         case RTL_GIGA_MAC_VER_51:
5228         default:
5229                 ops->disable    = NULL;
5230                 ops->enable     = NULL;
5231                 break;
5232         }
5233 }
5234
5235 DECLARE_RTL_COND(rtl_chipcmd_cond)
5236 {
5237         return RTL_R8(tp, ChipCmd) & CmdReset;
5238 }
5239
5240 static void rtl_hw_reset(struct rtl8169_private *tp)
5241 {
5242         RTL_W8(tp, ChipCmd, CmdReset);
5243
5244         rtl_udelay_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100);
5245 }
5246
5247 static void rtl_request_uncached_firmware(struct rtl8169_private *tp)
5248 {
5249         struct rtl_fw *rtl_fw;
5250         const char *name;
5251         int rc = -ENOMEM;
5252
5253         name = rtl_lookup_firmware_name(tp);
5254         if (!name)
5255                 goto out_no_firmware;
5256
5257         rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
5258         if (!rtl_fw)
5259                 goto err_warn;
5260
5261         rc = request_firmware(&rtl_fw->fw, name, tp_to_dev(tp));
5262         if (rc < 0)
5263                 goto err_free;
5264
5265         rc = rtl_check_firmware(tp, rtl_fw);
5266         if (rc < 0)
5267                 goto err_release_firmware;
5268
5269         tp->rtl_fw = rtl_fw;
5270 out:
5271         return;
5272
5273 err_release_firmware:
5274         release_firmware(rtl_fw->fw);
5275 err_free:
5276         kfree(rtl_fw);
5277 err_warn:
5278         netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n",
5279                    name, rc);
5280 out_no_firmware:
5281         tp->rtl_fw = NULL;
5282         goto out;
5283 }
5284
5285 static void rtl_request_firmware(struct rtl8169_private *tp)
5286 {
5287         if (IS_ERR(tp->rtl_fw))
5288                 rtl_request_uncached_firmware(tp);
5289 }
5290
5291 static void rtl_rx_close(struct rtl8169_private *tp)
5292 {
5293         RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
5294 }
5295
5296 DECLARE_RTL_COND(rtl_npq_cond)
5297 {
5298         return RTL_R8(tp, TxPoll) & NPQ;
5299 }
5300
5301 DECLARE_RTL_COND(rtl_txcfg_empty_cond)
5302 {
5303         return RTL_R32(tp, TxConfig) & TXCFG_EMPTY;
5304 }
5305
5306 static void rtl8169_hw_reset(struct rtl8169_private *tp)
5307 {
5308         /* Disable interrupts */
5309         rtl8169_irq_mask_and_ack(tp);
5310
5311         rtl_rx_close(tp);
5312
5313         if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
5314             tp->mac_version == RTL_GIGA_MAC_VER_28 ||
5315             tp->mac_version == RTL_GIGA_MAC_VER_31) {
5316                 rtl_udelay_loop_wait_low(tp, &rtl_npq_cond, 20, 42*42);
5317         } else if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
5318                    tp->mac_version == RTL_GIGA_MAC_VER_35 ||
5319                    tp->mac_version == RTL_GIGA_MAC_VER_36 ||
5320                    tp->mac_version == RTL_GIGA_MAC_VER_37 ||
5321                    tp->mac_version == RTL_GIGA_MAC_VER_38 ||
5322                    tp->mac_version == RTL_GIGA_MAC_VER_40 ||
5323                    tp->mac_version == RTL_GIGA_MAC_VER_41 ||
5324                    tp->mac_version == RTL_GIGA_MAC_VER_42 ||
5325                    tp->mac_version == RTL_GIGA_MAC_VER_43 ||
5326                    tp->mac_version == RTL_GIGA_MAC_VER_44 ||
5327                    tp->mac_version == RTL_GIGA_MAC_VER_45 ||
5328                    tp->mac_version == RTL_GIGA_MAC_VER_46 ||
5329                    tp->mac_version == RTL_GIGA_MAC_VER_47 ||
5330                    tp->mac_version == RTL_GIGA_MAC_VER_48 ||
5331                    tp->mac_version == RTL_GIGA_MAC_VER_49 ||
5332                    tp->mac_version == RTL_GIGA_MAC_VER_50 ||
5333                    tp->mac_version == RTL_GIGA_MAC_VER_51) {
5334                 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
5335                 rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);
5336         } else {
5337                 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
5338                 udelay(100);
5339         }
5340
5341         rtl_hw_reset(tp);
5342 }
5343
5344 static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
5345 {
5346         /* Set DMA burst size and Interframe Gap Time */
5347         RTL_W32(tp, TxConfig, (TX_DMA_BURST << TxDMAShift) |
5348                 (InterFrameGap << TxInterFrameGapShift));
5349 }
5350
5351 static void rtl_hw_start(struct  rtl8169_private *tp)
5352 {
5353         tp->hw_start(tp);
5354         rtl_irq_enable_all(tp);
5355 }
5356
5357 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp)
5358 {
5359         /*
5360          * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
5361          * register to be written before TxDescAddrLow to work.
5362          * Switching from MMIO to I/O access fixes the issue as well.
5363          */
5364         RTL_W32(tp, TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
5365         RTL_W32(tp, TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
5366         RTL_W32(tp, RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
5367         RTL_W32(tp, RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
5368 }
5369
5370 static u16 rtl_rw_cpluscmd(struct rtl8169_private *tp)
5371 {
5372         u16 cmd;
5373
5374         cmd = RTL_R16(tp, CPlusCmd);
5375         RTL_W16(tp, CPlusCmd, cmd);
5376         return cmd;
5377 }
5378
5379 static void rtl_set_rx_max_size(struct rtl8169_private *tp)
5380 {
5381         /* Low hurts. Let's disable the filtering. */
5382         RTL_W16(tp, RxMaxSize, R8169_RX_BUF_SIZE + 1);
5383 }
5384
5385 static void rtl8169_set_magic_reg(struct rtl8169_private *tp, unsigned mac_version)
5386 {
5387         static const struct rtl_cfg2_info {
5388                 u32 mac_version;
5389                 u32 clk;
5390                 u32 val;
5391         } cfg2_info [] = {
5392                 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
5393                 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
5394                 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
5395                 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
5396         };
5397         const struct rtl_cfg2_info *p = cfg2_info;
5398         unsigned int i;
5399         u32 clk;
5400
5401         clk = RTL_R8(tp, Config2) & PCI_Clock_66MHz;
5402         for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
5403                 if ((p->mac_version == mac_version) && (p->clk == clk)) {
5404                         RTL_W32(tp, 0x7c, p->val);
5405                         break;
5406                 }
5407         }
5408 }
5409
5410 static void rtl_set_rx_mode(struct net_device *dev)
5411 {
5412         struct rtl8169_private *tp = netdev_priv(dev);
5413         u32 mc_filter[2];       /* Multicast hash filter */
5414         int rx_mode;
5415         u32 tmp = 0;
5416
5417         if (dev->flags & IFF_PROMISC) {
5418                 /* Unconditionally log net taps. */
5419                 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
5420                 rx_mode =
5421                     AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
5422                     AcceptAllPhys;
5423                 mc_filter[1] = mc_filter[0] = 0xffffffff;
5424         } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
5425                    (dev->flags & IFF_ALLMULTI)) {
5426                 /* Too many to filter perfectly -- accept all multicasts. */
5427                 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
5428                 mc_filter[1] = mc_filter[0] = 0xffffffff;
5429         } else {
5430                 struct netdev_hw_addr *ha;
5431
5432                 rx_mode = AcceptBroadcast | AcceptMyPhys;
5433                 mc_filter[1] = mc_filter[0] = 0;
5434                 netdev_for_each_mc_addr(ha, dev) {
5435                         int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
5436                         mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
5437                         rx_mode |= AcceptMulticast;
5438                 }
5439         }
5440
5441         if (dev->features & NETIF_F_RXALL)
5442                 rx_mode |= (AcceptErr | AcceptRunt);
5443
5444         tmp = (RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK) | rx_mode;
5445
5446         if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
5447                 u32 data = mc_filter[0];
5448
5449                 mc_filter[0] = swab32(mc_filter[1]);
5450                 mc_filter[1] = swab32(data);
5451         }
5452
5453         if (tp->mac_version == RTL_GIGA_MAC_VER_35)
5454                 mc_filter[1] = mc_filter[0] = 0xffffffff;
5455
5456         RTL_W32(tp, MAR0 + 4, mc_filter[1]);
5457         RTL_W32(tp, MAR0 + 0, mc_filter[0]);
5458
5459         RTL_W32(tp, RxConfig, tmp);
5460 }
5461
5462 static void rtl_hw_start_8169(struct rtl8169_private *tp)
5463 {
5464         if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
5465                 RTL_W16(tp, CPlusCmd, RTL_R16(tp, CPlusCmd) | PCIMulRW);
5466                 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
5467         }
5468
5469         RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
5470         if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
5471             tp->mac_version == RTL_GIGA_MAC_VER_02 ||
5472             tp->mac_version == RTL_GIGA_MAC_VER_03 ||
5473             tp->mac_version == RTL_GIGA_MAC_VER_04)
5474                 RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb);
5475
5476         rtl_init_rxcfg(tp);
5477
5478         RTL_W8(tp, EarlyTxThres, NoEarlyTx);
5479
5480         rtl_set_rx_max_size(tp);
5481
5482         if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
5483             tp->mac_version == RTL_GIGA_MAC_VER_02 ||
5484             tp->mac_version == RTL_GIGA_MAC_VER_03 ||
5485             tp->mac_version == RTL_GIGA_MAC_VER_04)
5486                 rtl_set_rx_tx_config_registers(tp);
5487
5488         tp->cp_cmd |= rtl_rw_cpluscmd(tp) | PCIMulRW;
5489
5490         if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
5491             tp->mac_version == RTL_GIGA_MAC_VER_03) {
5492                 dprintk("Set MAC Reg C+CR Offset 0xe0. "
5493                         "Bit-3 and bit-14 MUST be 1\n");
5494                 tp->cp_cmd |= (1 << 14);
5495         }
5496
5497         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
5498
5499         rtl8169_set_magic_reg(tp, tp->mac_version);
5500
5501         /*
5502          * Undocumented corner. Supposedly:
5503          * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
5504          */
5505         RTL_W16(tp, IntrMitigate, 0x0000);
5506
5507         rtl_set_rx_tx_desc_registers(tp);
5508
5509         if (tp->mac_version != RTL_GIGA_MAC_VER_01 &&
5510             tp->mac_version != RTL_GIGA_MAC_VER_02 &&
5511             tp->mac_version != RTL_GIGA_MAC_VER_03 &&
5512             tp->mac_version != RTL_GIGA_MAC_VER_04) {
5513                 RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb);
5514                 rtl_set_rx_tx_config_registers(tp);
5515         }
5516
5517         RTL_W8(tp, Cfg9346, Cfg9346_Lock);
5518
5519         /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
5520         RTL_R8(tp, IntrMask);
5521
5522         RTL_W32(tp, RxMissed, 0);
5523
5524         rtl_set_rx_mode(tp->dev);
5525
5526         /* no early-rx interrupts */
5527         RTL_W16(tp, MultiIntr, RTL_R16(tp, MultiIntr) & 0xf000);
5528 }
5529
5530 static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)
5531 {
5532         if (tp->csi_ops.write)
5533                 tp->csi_ops.write(tp, addr, value);
5534 }
5535
5536 static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)
5537 {
5538         return tp->csi_ops.read ? tp->csi_ops.read(tp, addr) : ~0;
5539 }
5540
5541 static void rtl_csi_access_enable(struct rtl8169_private *tp, u32 bits)
5542 {
5543         u32 csi;
5544
5545         csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff;
5546         rtl_csi_write(tp, 0x070c, csi | bits);
5547 }
5548
5549 static void rtl_csi_access_enable_1(struct rtl8169_private *tp)
5550 {
5551         rtl_csi_access_enable(tp, 0x17000000);
5552 }
5553
5554 static void rtl_csi_access_enable_2(struct rtl8169_private *tp)
5555 {
5556         rtl_csi_access_enable(tp, 0x27000000);
5557 }
5558
5559 DECLARE_RTL_COND(rtl_csiar_cond)
5560 {
5561         return RTL_R32(tp, CSIAR) & CSIAR_FLAG;
5562 }
5563
5564 static void r8169_csi_write(struct rtl8169_private *tp, int addr, int value)
5565 {
5566         RTL_W32(tp, CSIDR, value);
5567         RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
5568                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
5569
5570         rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
5571 }
5572
5573 static u32 r8169_csi_read(struct rtl8169_private *tp, int addr)
5574 {
5575         RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) |
5576                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
5577
5578         return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
5579                 RTL_R32(tp, CSIDR) : ~0;
5580 }
5581
5582 static void r8402_csi_write(struct rtl8169_private *tp, int addr, int value)
5583 {
5584         RTL_W32(tp, CSIDR, value);
5585         RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
5586                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT |
5587                 CSIAR_FUNC_NIC);
5588
5589         rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
5590 }
5591
5592 static u32 r8402_csi_read(struct rtl8169_private *tp, int addr)
5593 {
5594         RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) | CSIAR_FUNC_NIC |
5595                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
5596
5597         return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
5598                 RTL_R32(tp, CSIDR) : ~0;
5599 }
5600
5601 static void r8411_csi_write(struct rtl8169_private *tp, int addr, int value)
5602 {
5603         RTL_W32(tp, CSIDR, value);
5604         RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
5605                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT |
5606                 CSIAR_FUNC_NIC2);
5607
5608         rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
5609 }
5610
5611 static u32 r8411_csi_read(struct rtl8169_private *tp, int addr)
5612 {
5613         RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) | CSIAR_FUNC_NIC2 |
5614                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
5615
5616         return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
5617                 RTL_R32(tp, CSIDR) : ~0;
5618 }
5619
5620 static void rtl_init_csi_ops(struct rtl8169_private *tp)
5621 {
5622         struct csi_ops *ops = &tp->csi_ops;
5623
5624         switch (tp->mac_version) {
5625         case RTL_GIGA_MAC_VER_01:
5626         case RTL_GIGA_MAC_VER_02:
5627         case RTL_GIGA_MAC_VER_03:
5628         case RTL_GIGA_MAC_VER_04:
5629         case RTL_GIGA_MAC_VER_05:
5630         case RTL_GIGA_MAC_VER_06:
5631         case RTL_GIGA_MAC_VER_10:
5632         case RTL_GIGA_MAC_VER_11:
5633         case RTL_GIGA_MAC_VER_12:
5634         case RTL_GIGA_MAC_VER_13:
5635         case RTL_GIGA_MAC_VER_14:
5636         case RTL_GIGA_MAC_VER_15:
5637         case RTL_GIGA_MAC_VER_16:
5638         case RTL_GIGA_MAC_VER_17:
5639                 ops->write      = NULL;
5640                 ops->read       = NULL;
5641                 break;
5642
5643         case RTL_GIGA_MAC_VER_37:
5644         case RTL_GIGA_MAC_VER_38:
5645                 ops->write      = r8402_csi_write;
5646                 ops->read       = r8402_csi_read;
5647                 break;
5648
5649         case RTL_GIGA_MAC_VER_44:
5650                 ops->write      = r8411_csi_write;
5651                 ops->read       = r8411_csi_read;
5652                 break;
5653
5654         default:
5655                 ops->write      = r8169_csi_write;
5656                 ops->read       = r8169_csi_read;
5657                 break;
5658         }
5659 }
5660
5661 struct ephy_info {
5662         unsigned int offset;
5663         u16 mask;
5664         u16 bits;
5665 };
5666
5667 static void rtl_ephy_init(struct rtl8169_private *tp, const struct ephy_info *e,
5668                           int len)
5669 {
5670         u16 w;
5671
5672         while (len-- > 0) {
5673                 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits;
5674                 rtl_ephy_write(tp, e->offset, w);
5675                 e++;
5676         }
5677 }
5678
5679 static void rtl_disable_clock_request(struct rtl8169_private *tp)
5680 {
5681         pcie_capability_clear_word(tp->pci_dev, PCI_EXP_LNKCTL,
5682                                    PCI_EXP_LNKCTL_CLKREQ_EN);
5683 }
5684
5685 static void rtl_enable_clock_request(struct rtl8169_private *tp)
5686 {
5687         pcie_capability_set_word(tp->pci_dev, PCI_EXP_LNKCTL,
5688                                  PCI_EXP_LNKCTL_CLKREQ_EN);
5689 }
5690
5691 static void rtl_pcie_state_l2l3_enable(struct rtl8169_private *tp, bool enable)
5692 {
5693         u8 data;
5694
5695         data = RTL_R8(tp, Config3);
5696
5697         if (enable)
5698                 data |= Rdy_to_L23;
5699         else
5700                 data &= ~Rdy_to_L23;
5701
5702         RTL_W8(tp, Config3, data);
5703 }
5704
5705 #define R8168_CPCMD_QUIRK_MASK (\
5706         EnableBist | \
5707         Mac_dbgo_oe | \
5708         Force_half_dup | \
5709         Force_rxflow_en | \
5710         Force_txflow_en | \
5711         Cxpl_dbg_sel | \
5712         ASF | \
5713         PktCntrDisable | \
5714         Mac_dbgo_sel)
5715
5716 static void rtl_hw_start_8168bb(struct rtl8169_private *tp)
5717 {
5718         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
5719
5720         RTL_W16(tp, CPlusCmd, RTL_R16(tp, CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5721
5722         if (tp->dev->mtu <= ETH_DATA_LEN) {
5723                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B |
5724                                          PCI_EXP_DEVCTL_NOSNOOP_EN);
5725         }
5726 }
5727
5728 static void rtl_hw_start_8168bef(struct rtl8169_private *tp)
5729 {
5730         rtl_hw_start_8168bb(tp);
5731
5732         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
5733
5734         RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0));
5735 }
5736
5737 static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)
5738 {
5739         RTL_W8(tp, Config1, RTL_R8(tp, Config1) | Speed_down);
5740
5741         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
5742
5743         if (tp->dev->mtu <= ETH_DATA_LEN)
5744                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5745
5746         rtl_disable_clock_request(tp);
5747
5748         RTL_W16(tp, CPlusCmd, RTL_R16(tp, CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5749 }
5750
5751 static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp)
5752 {
5753         static const struct ephy_info e_info_8168cp[] = {
5754                 { 0x01, 0,      0x0001 },
5755                 { 0x02, 0x0800, 0x1000 },
5756                 { 0x03, 0,      0x0042 },
5757                 { 0x06, 0x0080, 0x0000 },
5758                 { 0x07, 0,      0x2000 }
5759         };
5760
5761         rtl_csi_access_enable_2(tp);
5762
5763         rtl_ephy_init(tp, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
5764
5765         __rtl_hw_start_8168cp(tp);
5766 }
5767
5768 static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)
5769 {
5770         rtl_csi_access_enable_2(tp);
5771
5772         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
5773
5774         if (tp->dev->mtu <= ETH_DATA_LEN)
5775                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5776
5777         RTL_W16(tp, CPlusCmd, RTL_R16(tp, CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5778 }
5779
5780 static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)
5781 {
5782         rtl_csi_access_enable_2(tp);
5783
5784         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
5785
5786         /* Magic. */
5787         RTL_W8(tp, DBG_REG, 0x20);
5788
5789         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
5790
5791         if (tp->dev->mtu <= ETH_DATA_LEN)
5792                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5793
5794         RTL_W16(tp, CPlusCmd, RTL_R16(tp, CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5795 }
5796
5797 static void rtl_hw_start_8168c_1(struct rtl8169_private *tp)
5798 {
5799         static const struct ephy_info e_info_8168c_1[] = {
5800                 { 0x02, 0x0800, 0x1000 },
5801                 { 0x03, 0,      0x0002 },
5802                 { 0x06, 0x0080, 0x0000 }
5803         };
5804
5805         rtl_csi_access_enable_2(tp);
5806
5807         RTL_W8(tp, DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
5808
5809         rtl_ephy_init(tp, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
5810
5811         __rtl_hw_start_8168cp(tp);
5812 }
5813
5814 static void rtl_hw_start_8168c_2(struct rtl8169_private *tp)
5815 {
5816         static const struct ephy_info e_info_8168c_2[] = {
5817                 { 0x01, 0,      0x0001 },
5818                 { 0x03, 0x0400, 0x0220 }
5819         };
5820
5821         rtl_csi_access_enable_2(tp);
5822
5823         rtl_ephy_init(tp, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
5824
5825         __rtl_hw_start_8168cp(tp);
5826 }
5827
5828 static void rtl_hw_start_8168c_3(struct rtl8169_private *tp)
5829 {
5830         rtl_hw_start_8168c_2(tp);
5831 }
5832
5833 static void rtl_hw_start_8168c_4(struct rtl8169_private *tp)
5834 {
5835         rtl_csi_access_enable_2(tp);
5836
5837         __rtl_hw_start_8168cp(tp);
5838 }
5839
5840 static void rtl_hw_start_8168d(struct rtl8169_private *tp)
5841 {
5842         rtl_csi_access_enable_2(tp);
5843
5844         rtl_disable_clock_request(tp);
5845
5846         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
5847
5848         if (tp->dev->mtu <= ETH_DATA_LEN)
5849                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5850
5851         RTL_W16(tp, CPlusCmd, RTL_R16(tp, CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5852 }
5853
5854 static void rtl_hw_start_8168dp(struct rtl8169_private *tp)
5855 {
5856         rtl_csi_access_enable_1(tp);
5857
5858         if (tp->dev->mtu <= ETH_DATA_LEN)
5859                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5860
5861         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
5862
5863         rtl_disable_clock_request(tp);
5864 }
5865
5866 static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
5867 {
5868         static const struct ephy_info e_info_8168d_4[] = {
5869                 { 0x0b, 0x0000, 0x0048 },
5870                 { 0x19, 0x0020, 0x0050 },
5871                 { 0x0c, 0x0100, 0x0020 }
5872         };
5873
5874         rtl_csi_access_enable_1(tp);
5875
5876         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5877
5878         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
5879
5880         rtl_ephy_init(tp, e_info_8168d_4, ARRAY_SIZE(e_info_8168d_4));
5881
5882         rtl_enable_clock_request(tp);
5883 }
5884
5885 static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)
5886 {
5887         static const struct ephy_info e_info_8168e_1[] = {
5888                 { 0x00, 0x0200, 0x0100 },
5889                 { 0x00, 0x0000, 0x0004 },
5890                 { 0x06, 0x0002, 0x0001 },
5891                 { 0x06, 0x0000, 0x0030 },
5892                 { 0x07, 0x0000, 0x2000 },
5893                 { 0x00, 0x0000, 0x0020 },
5894                 { 0x03, 0x5800, 0x2000 },
5895                 { 0x03, 0x0000, 0x0001 },
5896                 { 0x01, 0x0800, 0x1000 },
5897                 { 0x07, 0x0000, 0x4000 },
5898                 { 0x1e, 0x0000, 0x2000 },
5899                 { 0x19, 0xffff, 0xfe6c },
5900                 { 0x0a, 0x0000, 0x0040 }
5901         };
5902
5903         rtl_csi_access_enable_2(tp);
5904
5905         rtl_ephy_init(tp, e_info_8168e_1, ARRAY_SIZE(e_info_8168e_1));
5906
5907         if (tp->dev->mtu <= ETH_DATA_LEN)
5908                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5909
5910         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
5911
5912         rtl_disable_clock_request(tp);
5913
5914         /* Reset tx FIFO pointer */
5915         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | TXPLA_RST);
5916         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~TXPLA_RST);
5917
5918         RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
5919 }
5920
5921 static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
5922 {
5923         static const struct ephy_info e_info_8168e_2[] = {
5924                 { 0x09, 0x0000, 0x0080 },
5925                 { 0x19, 0x0000, 0x0224 }
5926         };
5927
5928         rtl_csi_access_enable_1(tp);
5929
5930         rtl_ephy_init(tp, e_info_8168e_2, ARRAY_SIZE(e_info_8168e_2));
5931
5932         if (tp->dev->mtu <= ETH_DATA_LEN)
5933                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5934
5935         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5936         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5937         rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
5938         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5939         rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
5940         rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060, ERIAR_EXGMAC);
5941         rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5942         rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
5943
5944         RTL_W8(tp, MaxTxPacketSize, EarlySize);
5945
5946         rtl_disable_clock_request(tp);
5947
5948         RTL_W32(tp, TxConfig, RTL_R32(tp, TxConfig) | TXCFG_AUTO_FIFO);
5949         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
5950
5951         /* Adjust EEE LED frequency */
5952         RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
5953
5954         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
5955         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
5956         RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
5957 }
5958
5959 static void rtl_hw_start_8168f(struct rtl8169_private *tp)
5960 {
5961         rtl_csi_access_enable_2(tp);
5962
5963         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5964
5965         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5966         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5967         rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
5968         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5969         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5970         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5971         rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5972         rtl_w0w1_eri(tp, 0x1d0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5973         rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
5974         rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060, ERIAR_EXGMAC);
5975
5976         RTL_W8(tp, MaxTxPacketSize, EarlySize);
5977
5978         rtl_disable_clock_request(tp);
5979
5980         RTL_W32(tp, TxConfig, RTL_R32(tp, TxConfig) | TXCFG_AUTO_FIFO);
5981         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
5982         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
5983         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
5984         RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
5985 }
5986
5987 static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
5988 {
5989         static const struct ephy_info e_info_8168f_1[] = {
5990                 { 0x06, 0x00c0, 0x0020 },
5991                 { 0x08, 0x0001, 0x0002 },
5992                 { 0x09, 0x0000, 0x0080 },
5993                 { 0x19, 0x0000, 0x0224 }
5994         };
5995
5996         rtl_hw_start_8168f(tp);
5997
5998         rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
5999
6000         rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
6001
6002         /* Adjust EEE LED frequency */
6003         RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
6004 }
6005
6006 static void rtl_hw_start_8411(struct rtl8169_private *tp)
6007 {
6008         static const struct ephy_info e_info_8168f_1[] = {
6009                 { 0x06, 0x00c0, 0x0020 },
6010                 { 0x0f, 0xffff, 0x5200 },
6011                 { 0x1e, 0x0000, 0x4000 },
6012                 { 0x19, 0x0000, 0x0224 }
6013         };
6014
6015         rtl_hw_start_8168f(tp);
6016         rtl_pcie_state_l2l3_enable(tp, false);
6017
6018         rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
6019
6020         rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0x0000, ERIAR_EXGMAC);
6021 }
6022
6023 static void rtl_hw_start_8168g(struct rtl8169_private *tp)
6024 {
6025         RTL_W32(tp, TxConfig, RTL_R32(tp, TxConfig) | TXCFG_AUTO_FIFO);
6026
6027         rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x080002, ERIAR_EXGMAC);
6028         rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
6029         rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
6030         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
6031
6032         rtl_csi_access_enable_1(tp);
6033
6034         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
6035
6036         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
6037         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
6038         rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f, ERIAR_EXGMAC);
6039
6040         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
6041         RTL_W8(tp, MaxTxPacketSize, EarlySize);
6042
6043         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6044         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6045
6046         /* Adjust EEE LED frequency */
6047         RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
6048
6049         rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06, ERIAR_EXGMAC);
6050         rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC);
6051
6052         rtl_pcie_state_l2l3_enable(tp, false);
6053 }
6054
6055 static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
6056 {
6057         static const struct ephy_info e_info_8168g_1[] = {
6058                 { 0x00, 0x0000, 0x0008 },
6059                 { 0x0c, 0x37d0, 0x0820 },
6060                 { 0x1e, 0x0000, 0x0001 },
6061                 { 0x19, 0x8000, 0x0000 }
6062         };
6063
6064         rtl_hw_start_8168g(tp);
6065
6066         /* disable aspm and clock request before access ephy */
6067         RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
6068         RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
6069         rtl_ephy_init(tp, e_info_8168g_1, ARRAY_SIZE(e_info_8168g_1));
6070 }
6071
6072 static void rtl_hw_start_8168g_2(struct rtl8169_private *tp)
6073 {
6074         static const struct ephy_info e_info_8168g_2[] = {
6075                 { 0x00, 0x0000, 0x0008 },
6076                 { 0x0c, 0x3df0, 0x0200 },
6077                 { 0x19, 0xffff, 0xfc00 },
6078                 { 0x1e, 0xffff, 0x20eb }
6079         };
6080
6081         rtl_hw_start_8168g(tp);
6082
6083         /* disable aspm and clock request before access ephy */
6084         RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
6085         RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
6086         rtl_ephy_init(tp, e_info_8168g_2, ARRAY_SIZE(e_info_8168g_2));
6087 }
6088
6089 static void rtl_hw_start_8411_2(struct rtl8169_private *tp)
6090 {
6091         static const struct ephy_info e_info_8411_2[] = {
6092                 { 0x00, 0x0000, 0x0008 },
6093                 { 0x0c, 0x3df0, 0x0200 },
6094                 { 0x0f, 0xffff, 0x5200 },
6095                 { 0x19, 0x0020, 0x0000 },
6096                 { 0x1e, 0x0000, 0x2000 }
6097         };
6098
6099         rtl_hw_start_8168g(tp);
6100
6101         /* disable aspm and clock request before access ephy */
6102         RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
6103         RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
6104         rtl_ephy_init(tp, e_info_8411_2, ARRAY_SIZE(e_info_8411_2));
6105 }
6106
6107 static void rtl_hw_start_8168h_1(struct rtl8169_private *tp)
6108 {
6109         int rg_saw_cnt;
6110         u32 data;
6111         static const struct ephy_info e_info_8168h_1[] = {
6112                 { 0x1e, 0x0800, 0x0001 },
6113                 { 0x1d, 0x0000, 0x0800 },
6114                 { 0x05, 0xffff, 0x2089 },
6115                 { 0x06, 0xffff, 0x5881 },
6116                 { 0x04, 0xffff, 0x154a },
6117                 { 0x01, 0xffff, 0x068b }
6118         };
6119
6120         /* disable aspm and clock request before access ephy */
6121         RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
6122         RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
6123         rtl_ephy_init(tp, e_info_8168h_1, ARRAY_SIZE(e_info_8168h_1));
6124
6125         RTL_W32(tp, TxConfig, RTL_R32(tp, TxConfig) | TXCFG_AUTO_FIFO);
6126
6127         rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x00080002, ERIAR_EXGMAC);
6128         rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
6129         rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
6130         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
6131
6132         rtl_csi_access_enable_1(tp);
6133
6134         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
6135
6136         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
6137         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
6138
6139         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_1111, 0x0010, 0x00, ERIAR_EXGMAC);
6140
6141         rtl_w0w1_eri(tp, 0xd4, ERIAR_MASK_1111, 0x1f00, 0x00, ERIAR_EXGMAC);
6142
6143         rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87, ERIAR_EXGMAC);
6144
6145         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
6146         RTL_W8(tp, MaxTxPacketSize, EarlySize);
6147
6148         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6149         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6150
6151         /* Adjust EEE LED frequency */
6152         RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
6153
6154         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
6155         RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
6156
6157         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
6158
6159         rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC);
6160
6161         rtl_pcie_state_l2l3_enable(tp, false);
6162
6163         rtl_writephy(tp, 0x1f, 0x0c42);
6164         rg_saw_cnt = (rtl_readphy(tp, 0x13) & 0x3fff);
6165         rtl_writephy(tp, 0x1f, 0x0000);
6166         if (rg_saw_cnt > 0) {
6167                 u16 sw_cnt_1ms_ini;
6168
6169                 sw_cnt_1ms_ini = 16000000/rg_saw_cnt;
6170                 sw_cnt_1ms_ini &= 0x0fff;
6171                 data = r8168_mac_ocp_read(tp, 0xd412);
6172                 data &= ~0x0fff;
6173                 data |= sw_cnt_1ms_ini;
6174                 r8168_mac_ocp_write(tp, 0xd412, data);
6175         }
6176
6177         data = r8168_mac_ocp_read(tp, 0xe056);
6178         data &= ~0xf0;
6179         data |= 0x70;
6180         r8168_mac_ocp_write(tp, 0xe056, data);
6181
6182         data = r8168_mac_ocp_read(tp, 0xe052);
6183         data &= ~0x6000;
6184         data |= 0x8008;
6185         r8168_mac_ocp_write(tp, 0xe052, data);
6186
6187         data = r8168_mac_ocp_read(tp, 0xe0d6);
6188         data &= ~0x01ff;
6189         data |= 0x017f;
6190         r8168_mac_ocp_write(tp, 0xe0d6, data);
6191
6192         data = r8168_mac_ocp_read(tp, 0xd420);
6193         data &= ~0x0fff;
6194         data |= 0x047f;
6195         r8168_mac_ocp_write(tp, 0xd420, data);
6196
6197         r8168_mac_ocp_write(tp, 0xe63e, 0x0001);
6198         r8168_mac_ocp_write(tp, 0xe63e, 0x0000);
6199         r8168_mac_ocp_write(tp, 0xc094, 0x0000);
6200         r8168_mac_ocp_write(tp, 0xc09e, 0x0000);
6201 }
6202
6203 static void rtl_hw_start_8168ep(struct rtl8169_private *tp)
6204 {
6205         rtl8168ep_stop_cmac(tp);
6206
6207         RTL_W32(tp, TxConfig, RTL_R32(tp, TxConfig) | TXCFG_AUTO_FIFO);
6208
6209         rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x00080002, ERIAR_EXGMAC);
6210         rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x2f, ERIAR_EXGMAC);
6211         rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x5f, ERIAR_EXGMAC);
6212         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
6213
6214         rtl_csi_access_enable_1(tp);
6215
6216         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
6217
6218         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
6219         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
6220
6221         rtl_w0w1_eri(tp, 0xd4, ERIAR_MASK_1111, 0x1f80, 0x00, ERIAR_EXGMAC);
6222
6223         rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87, ERIAR_EXGMAC);
6224
6225         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
6226         RTL_W8(tp, MaxTxPacketSize, EarlySize);
6227
6228         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6229         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6230
6231         /* Adjust EEE LED frequency */
6232         RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
6233
6234         rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06, ERIAR_EXGMAC);
6235
6236         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
6237
6238         rtl_pcie_state_l2l3_enable(tp, false);
6239 }
6240
6241 static void rtl_hw_start_8168ep_1(struct rtl8169_private *tp)
6242 {
6243         static const struct ephy_info e_info_8168ep_1[] = {
6244                 { 0x00, 0xffff, 0x10ab },
6245                 { 0x06, 0xffff, 0xf030 },
6246                 { 0x08, 0xffff, 0x2006 },
6247                 { 0x0d, 0xffff, 0x1666 },
6248                 { 0x0c, 0x3ff0, 0x0000 }
6249         };
6250
6251         /* disable aspm and clock request before access ephy */
6252         RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
6253         RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
6254         rtl_ephy_init(tp, e_info_8168ep_1, ARRAY_SIZE(e_info_8168ep_1));
6255
6256         rtl_hw_start_8168ep(tp);
6257 }
6258
6259 static void rtl_hw_start_8168ep_2(struct rtl8169_private *tp)
6260 {
6261         static const struct ephy_info e_info_8168ep_2[] = {
6262                 { 0x00, 0xffff, 0x10a3 },
6263                 { 0x19, 0xffff, 0xfc00 },
6264                 { 0x1e, 0xffff, 0x20ea }
6265         };
6266
6267         /* disable aspm and clock request before access ephy */
6268         RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
6269         RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
6270         rtl_ephy_init(tp, e_info_8168ep_2, ARRAY_SIZE(e_info_8168ep_2));
6271
6272         rtl_hw_start_8168ep(tp);
6273
6274         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
6275         RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
6276 }
6277
6278 static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp)
6279 {
6280         u32 data;
6281         static const struct ephy_info e_info_8168ep_3[] = {
6282                 { 0x00, 0xffff, 0x10a3 },
6283                 { 0x19, 0xffff, 0x7c00 },
6284                 { 0x1e, 0xffff, 0x20eb },
6285                 { 0x0d, 0xffff, 0x1666 }
6286         };
6287
6288         /* disable aspm and clock request before access ephy */
6289         RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
6290         RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
6291         rtl_ephy_init(tp, e_info_8168ep_3, ARRAY_SIZE(e_info_8168ep_3));
6292
6293         rtl_hw_start_8168ep(tp);
6294
6295         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
6296         RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
6297
6298         data = r8168_mac_ocp_read(tp, 0xd3e2);
6299         data &= 0xf000;
6300         data |= 0x0271;
6301         r8168_mac_ocp_write(tp, 0xd3e2, data);
6302
6303         data = r8168_mac_ocp_read(tp, 0xd3e4);
6304         data &= 0xff00;
6305         r8168_mac_ocp_write(tp, 0xd3e4, data);
6306
6307         data = r8168_mac_ocp_read(tp, 0xe860);
6308         data |= 0x0080;
6309         r8168_mac_ocp_write(tp, 0xe860, data);
6310 }
6311
6312 static void rtl_hw_start_8168(struct rtl8169_private *tp)
6313 {
6314         RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
6315
6316         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
6317
6318         rtl_set_rx_max_size(tp);
6319
6320         tp->cp_cmd |= RTL_R16(tp, CPlusCmd) | PktCntrDisable | INTT_1;
6321
6322         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
6323
6324         RTL_W16(tp, IntrMitigate, 0x5151);
6325
6326         /* Work around for RxFIFO overflow. */
6327         if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
6328                 tp->event_slow |= RxFIFOOver | PCSTimeout;
6329                 tp->event_slow &= ~RxOverflow;
6330         }
6331
6332         rtl_set_rx_tx_desc_registers(tp);
6333
6334         rtl_set_rx_tx_config_registers(tp);
6335
6336         RTL_R8(tp, IntrMask);
6337
6338         switch (tp->mac_version) {
6339         case RTL_GIGA_MAC_VER_11:
6340                 rtl_hw_start_8168bb(tp);
6341                 break;
6342
6343         case RTL_GIGA_MAC_VER_12:
6344         case RTL_GIGA_MAC_VER_17:
6345                 rtl_hw_start_8168bef(tp);
6346                 break;
6347
6348         case RTL_GIGA_MAC_VER_18:
6349                 rtl_hw_start_8168cp_1(tp);
6350                 break;
6351
6352         case RTL_GIGA_MAC_VER_19:
6353                 rtl_hw_start_8168c_1(tp);
6354                 break;
6355
6356         case RTL_GIGA_MAC_VER_20:
6357                 rtl_hw_start_8168c_2(tp);
6358                 break;
6359
6360         case RTL_GIGA_MAC_VER_21:
6361                 rtl_hw_start_8168c_3(tp);
6362                 break;
6363
6364         case RTL_GIGA_MAC_VER_22:
6365                 rtl_hw_start_8168c_4(tp);
6366                 break;
6367
6368         case RTL_GIGA_MAC_VER_23:
6369                 rtl_hw_start_8168cp_2(tp);
6370                 break;
6371
6372         case RTL_GIGA_MAC_VER_24:
6373                 rtl_hw_start_8168cp_3(tp);
6374                 break;
6375
6376         case RTL_GIGA_MAC_VER_25:
6377         case RTL_GIGA_MAC_VER_26:
6378         case RTL_GIGA_MAC_VER_27:
6379                 rtl_hw_start_8168d(tp);
6380                 break;
6381
6382         case RTL_GIGA_MAC_VER_28:
6383                 rtl_hw_start_8168d_4(tp);
6384                 break;
6385
6386         case RTL_GIGA_MAC_VER_31:
6387                 rtl_hw_start_8168dp(tp);
6388                 break;
6389
6390         case RTL_GIGA_MAC_VER_32:
6391         case RTL_GIGA_MAC_VER_33:
6392                 rtl_hw_start_8168e_1(tp);
6393                 break;
6394         case RTL_GIGA_MAC_VER_34:
6395                 rtl_hw_start_8168e_2(tp);
6396                 break;
6397
6398         case RTL_GIGA_MAC_VER_35:
6399         case RTL_GIGA_MAC_VER_36:
6400                 rtl_hw_start_8168f_1(tp);
6401                 break;
6402
6403         case RTL_GIGA_MAC_VER_38:
6404                 rtl_hw_start_8411(tp);
6405                 break;
6406
6407         case RTL_GIGA_MAC_VER_40:
6408         case RTL_GIGA_MAC_VER_41:
6409                 rtl_hw_start_8168g_1(tp);
6410                 break;
6411         case RTL_GIGA_MAC_VER_42:
6412                 rtl_hw_start_8168g_2(tp);
6413                 break;
6414
6415         case RTL_GIGA_MAC_VER_44:
6416                 rtl_hw_start_8411_2(tp);
6417                 break;
6418
6419         case RTL_GIGA_MAC_VER_45:
6420         case RTL_GIGA_MAC_VER_46:
6421                 rtl_hw_start_8168h_1(tp);
6422                 break;
6423
6424         case RTL_GIGA_MAC_VER_49:
6425                 rtl_hw_start_8168ep_1(tp);
6426                 break;
6427
6428         case RTL_GIGA_MAC_VER_50:
6429                 rtl_hw_start_8168ep_2(tp);
6430                 break;
6431
6432         case RTL_GIGA_MAC_VER_51:
6433                 rtl_hw_start_8168ep_3(tp);
6434                 break;
6435
6436         default:
6437                 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
6438                        tp->dev->name, tp->mac_version);
6439                 break;
6440         }
6441
6442         RTL_W8(tp, Cfg9346, Cfg9346_Lock);
6443
6444         RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb);
6445
6446         rtl_set_rx_mode(tp->dev);
6447
6448         RTL_W16(tp, MultiIntr, RTL_R16(tp, MultiIntr) & 0xf000);
6449 }
6450
6451 #define R810X_CPCMD_QUIRK_MASK (\
6452         EnableBist | \
6453         Mac_dbgo_oe | \
6454         Force_half_dup | \
6455         Force_rxflow_en | \
6456         Force_txflow_en | \
6457         Cxpl_dbg_sel | \
6458         ASF | \
6459         PktCntrDisable | \
6460         Mac_dbgo_sel)
6461
6462 static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)
6463 {
6464         static const struct ephy_info e_info_8102e_1[] = {
6465                 { 0x01, 0, 0x6e65 },
6466                 { 0x02, 0, 0x091f },
6467                 { 0x03, 0, 0xc2f9 },
6468                 { 0x06, 0, 0xafb5 },
6469                 { 0x07, 0, 0x0e00 },
6470                 { 0x19, 0, 0xec80 },
6471                 { 0x01, 0, 0x2e65 },
6472                 { 0x01, 0, 0x6e65 }
6473         };
6474         u8 cfg1;
6475
6476         rtl_csi_access_enable_2(tp);
6477
6478         RTL_W8(tp, DBG_REG, FIX_NAK_1);
6479
6480         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
6481
6482         RTL_W8(tp, Config1,
6483                LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
6484         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
6485
6486         cfg1 = RTL_R8(tp, Config1);
6487         if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
6488                 RTL_W8(tp, Config1, cfg1 & ~LEDS0);
6489
6490         rtl_ephy_init(tp, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
6491 }
6492
6493 static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)
6494 {
6495         rtl_csi_access_enable_2(tp);
6496
6497         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
6498
6499         RTL_W8(tp, Config1, MEMMAP | IOMAP | VPD | PMEnable);
6500         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
6501 }
6502
6503 static void rtl_hw_start_8102e_3(struct rtl8169_private *tp)
6504 {
6505         rtl_hw_start_8102e_2(tp);
6506
6507         rtl_ephy_write(tp, 0x03, 0xc2f9);
6508 }
6509
6510 static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)
6511 {
6512         static const struct ephy_info e_info_8105e_1[] = {
6513                 { 0x07, 0, 0x4000 },
6514                 { 0x19, 0, 0x0200 },
6515                 { 0x19, 0, 0x0020 },
6516                 { 0x1e, 0, 0x2000 },
6517                 { 0x03, 0, 0x0001 },
6518                 { 0x19, 0, 0x0100 },
6519                 { 0x19, 0, 0x0004 },
6520                 { 0x0a, 0, 0x0020 }
6521         };
6522
6523         /* Force LAN exit from ASPM if Rx/Tx are not idle */
6524         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
6525
6526         /* Disable Early Tally Counter */
6527         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) & ~0x010000);
6528
6529         RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
6530         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
6531
6532         rtl_ephy_init(tp, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
6533
6534         rtl_pcie_state_l2l3_enable(tp, false);
6535 }
6536
6537 static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)
6538 {
6539         rtl_hw_start_8105e_1(tp);
6540         rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000);
6541 }
6542
6543 static void rtl_hw_start_8402(struct rtl8169_private *tp)
6544 {
6545         static const struct ephy_info e_info_8402[] = {
6546                 { 0x19, 0xffff, 0xff64 },
6547                 { 0x1e, 0, 0x4000 }
6548         };
6549
6550         rtl_csi_access_enable_2(tp);
6551
6552         /* Force LAN exit from ASPM if Rx/Tx are not idle */
6553         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
6554
6555         RTL_W32(tp, TxConfig, RTL_R32(tp, TxConfig) | TXCFG_AUTO_FIFO);
6556         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
6557
6558         rtl_ephy_init(tp, e_info_8402, ARRAY_SIZE(e_info_8402));
6559
6560         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
6561
6562         rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00000002, ERIAR_EXGMAC);
6563         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00000006, ERIAR_EXGMAC);
6564         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
6565         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
6566         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6567         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6568         rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0e00, 0xff00, ERIAR_EXGMAC);
6569
6570         rtl_pcie_state_l2l3_enable(tp, false);
6571 }
6572
6573 static void rtl_hw_start_8106(struct rtl8169_private *tp)
6574 {
6575         /* Force LAN exit from ASPM if Rx/Tx are not idle */
6576         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
6577
6578         RTL_W32(tp, MISC, (RTL_R32(tp, MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);
6579         RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
6580         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
6581
6582         rtl_pcie_state_l2l3_enable(tp, false);
6583 }
6584
6585 static void rtl_hw_start_8101(struct rtl8169_private *tp)
6586 {
6587         if (tp->mac_version >= RTL_GIGA_MAC_VER_30)
6588                 tp->event_slow &= ~RxFIFOOver;
6589
6590         if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
6591             tp->mac_version == RTL_GIGA_MAC_VER_16)
6592                 pcie_capability_set_word(tp->pci_dev, PCI_EXP_DEVCTL,
6593                                          PCI_EXP_DEVCTL_NOSNOOP_EN);
6594
6595         RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
6596
6597         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
6598
6599         rtl_set_rx_max_size(tp);
6600
6601         tp->cp_cmd &= ~R810X_CPCMD_QUIRK_MASK;
6602         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
6603
6604         rtl_set_rx_tx_desc_registers(tp);
6605
6606         rtl_set_rx_tx_config_registers(tp);
6607
6608         switch (tp->mac_version) {
6609         case RTL_GIGA_MAC_VER_07:
6610                 rtl_hw_start_8102e_1(tp);
6611                 break;
6612
6613         case RTL_GIGA_MAC_VER_08:
6614                 rtl_hw_start_8102e_3(tp);
6615                 break;
6616
6617         case RTL_GIGA_MAC_VER_09:
6618                 rtl_hw_start_8102e_2(tp);
6619                 break;
6620
6621         case RTL_GIGA_MAC_VER_29:
6622                 rtl_hw_start_8105e_1(tp);
6623                 break;
6624         case RTL_GIGA_MAC_VER_30:
6625                 rtl_hw_start_8105e_2(tp);
6626                 break;
6627
6628         case RTL_GIGA_MAC_VER_37:
6629                 rtl_hw_start_8402(tp);
6630                 break;
6631
6632         case RTL_GIGA_MAC_VER_39:
6633                 rtl_hw_start_8106(tp);
6634                 break;
6635         case RTL_GIGA_MAC_VER_43:
6636                 rtl_hw_start_8168g_2(tp);
6637                 break;
6638         case RTL_GIGA_MAC_VER_47:
6639         case RTL_GIGA_MAC_VER_48:
6640                 rtl_hw_start_8168h_1(tp);
6641                 break;
6642         }
6643
6644         RTL_W8(tp, Cfg9346, Cfg9346_Lock);
6645
6646         RTL_W16(tp, IntrMitigate, 0x0000);
6647
6648         RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb);
6649
6650         rtl_set_rx_mode(tp->dev);
6651
6652         RTL_R8(tp, IntrMask);
6653
6654         RTL_W16(tp, MultiIntr, RTL_R16(tp, MultiIntr) & 0xf000);
6655 }
6656
6657 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
6658 {
6659         struct rtl8169_private *tp = netdev_priv(dev);
6660
6661         if (new_mtu > ETH_DATA_LEN)
6662                 rtl_hw_jumbo_enable(tp);
6663         else
6664                 rtl_hw_jumbo_disable(tp);
6665
6666         dev->mtu = new_mtu;
6667         netdev_update_features(dev);
6668
6669         return 0;
6670 }
6671
6672 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
6673 {
6674         desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
6675         desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
6676 }
6677
6678 static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
6679                                      void **data_buff, struct RxDesc *desc)
6680 {
6681         dma_unmap_single(tp_to_dev(tp), le64_to_cpu(desc->addr),
6682                          R8169_RX_BUF_SIZE, DMA_FROM_DEVICE);
6683
6684         kfree(*data_buff);
6685         *data_buff = NULL;
6686         rtl8169_make_unusable_by_asic(desc);
6687 }
6688
6689 static inline void rtl8169_mark_to_asic(struct RxDesc *desc)
6690 {
6691         u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
6692
6693         /* Force memory writes to complete before releasing descriptor */
6694         dma_wmb();
6695
6696         desc->opts1 = cpu_to_le32(DescOwn | eor | R8169_RX_BUF_SIZE);
6697 }
6698
6699 static inline void *rtl8169_align(void *data)
6700 {
6701         return (void *)ALIGN((long)data, 16);
6702 }
6703
6704 static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
6705                                              struct RxDesc *desc)
6706 {
6707         void *data;
6708         dma_addr_t mapping;
6709         struct device *d = tp_to_dev(tp);
6710         int node = dev_to_node(d);
6711
6712         data = kmalloc_node(R8169_RX_BUF_SIZE, GFP_KERNEL, node);
6713         if (!data)
6714                 return NULL;
6715
6716         if (rtl8169_align(data) != data) {
6717                 kfree(data);
6718                 data = kmalloc_node(R8169_RX_BUF_SIZE + 15, GFP_KERNEL, node);
6719                 if (!data)
6720                         return NULL;
6721         }
6722
6723         mapping = dma_map_single(d, rtl8169_align(data), R8169_RX_BUF_SIZE,
6724                                  DMA_FROM_DEVICE);
6725         if (unlikely(dma_mapping_error(d, mapping))) {
6726                 if (net_ratelimit())
6727                         netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
6728                 goto err_out;
6729         }
6730
6731         desc->addr = cpu_to_le64(mapping);
6732         rtl8169_mark_to_asic(desc);
6733         return data;
6734
6735 err_out:
6736         kfree(data);
6737         return NULL;
6738 }
6739
6740 static void rtl8169_rx_clear(struct rtl8169_private *tp)
6741 {
6742         unsigned int i;
6743
6744         for (i = 0; i < NUM_RX_DESC; i++) {
6745                 if (tp->Rx_databuff[i]) {
6746                         rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
6747                                             tp->RxDescArray + i);
6748                 }
6749         }
6750 }
6751
6752 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
6753 {
6754         desc->opts1 |= cpu_to_le32(RingEnd);
6755 }
6756
6757 static int rtl8169_rx_fill(struct rtl8169_private *tp)
6758 {
6759         unsigned int i;
6760
6761         for (i = 0; i < NUM_RX_DESC; i++) {
6762                 void *data;
6763
6764                 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
6765                 if (!data) {
6766                         rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
6767                         goto err_out;
6768                 }
6769                 tp->Rx_databuff[i] = data;
6770         }
6771
6772         rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
6773         return 0;
6774
6775 err_out:
6776         rtl8169_rx_clear(tp);
6777         return -ENOMEM;
6778 }
6779
6780 static int rtl8169_init_ring(struct rtl8169_private *tp)
6781 {
6782         rtl8169_init_ring_indexes(tp);
6783
6784         memset(tp->tx_skb, 0, sizeof(tp->tx_skb));
6785         memset(tp->Rx_databuff, 0, sizeof(tp->Rx_databuff));
6786
6787         return rtl8169_rx_fill(tp);
6788 }
6789
6790 static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
6791                                  struct TxDesc *desc)
6792 {
6793         unsigned int len = tx_skb->len;
6794
6795         dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
6796
6797         desc->opts1 = 0x00;
6798         desc->opts2 = 0x00;
6799         desc->addr = 0x00;
6800         tx_skb->len = 0;
6801 }
6802
6803 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
6804                                    unsigned int n)
6805 {
6806         unsigned int i;
6807
6808         for (i = 0; i < n; i++) {
6809                 unsigned int entry = (start + i) % NUM_TX_DESC;
6810                 struct ring_info *tx_skb = tp->tx_skb + entry;
6811                 unsigned int len = tx_skb->len;
6812
6813                 if (len) {
6814                         struct sk_buff *skb = tx_skb->skb;
6815
6816                         rtl8169_unmap_tx_skb(tp_to_dev(tp), tx_skb,
6817                                              tp->TxDescArray + entry);
6818                         if (skb) {
6819                                 dev_consume_skb_any(skb);
6820                                 tx_skb->skb = NULL;
6821                         }
6822                 }
6823         }
6824 }
6825
6826 static void rtl8169_tx_clear(struct rtl8169_private *tp)
6827 {
6828         rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
6829         tp->cur_tx = tp->dirty_tx = 0;
6830 }
6831
6832 static void rtl_reset_work(struct rtl8169_private *tp)
6833 {
6834         struct net_device *dev = tp->dev;
6835         int i;
6836
6837         napi_disable(&tp->napi);
6838         netif_stop_queue(dev);
6839         synchronize_sched();
6840
6841         rtl8169_hw_reset(tp);
6842
6843         for (i = 0; i < NUM_RX_DESC; i++)
6844                 rtl8169_mark_to_asic(tp->RxDescArray + i);
6845
6846         rtl8169_tx_clear(tp);
6847         rtl8169_init_ring_indexes(tp);
6848
6849         napi_enable(&tp->napi);
6850         rtl_hw_start(tp);
6851         netif_wake_queue(dev);
6852         rtl8169_check_link_status(dev, tp);
6853 }
6854
6855 static void rtl8169_tx_timeout(struct net_device *dev)
6856 {
6857         struct rtl8169_private *tp = netdev_priv(dev);
6858
6859         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
6860 }
6861
6862 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
6863                               u32 *opts)
6864 {
6865         struct skb_shared_info *info = skb_shinfo(skb);
6866         unsigned int cur_frag, entry;
6867         struct TxDesc *uninitialized_var(txd);
6868         struct device *d = tp_to_dev(tp);
6869
6870         entry = tp->cur_tx;
6871         for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
6872                 const skb_frag_t *frag = info->frags + cur_frag;
6873                 dma_addr_t mapping;
6874                 u32 status, len;
6875                 void *addr;
6876
6877                 entry = (entry + 1) % NUM_TX_DESC;
6878
6879                 txd = tp->TxDescArray + entry;
6880                 len = skb_frag_size(frag);
6881                 addr = skb_frag_address(frag);
6882                 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
6883                 if (unlikely(dma_mapping_error(d, mapping))) {
6884                         if (net_ratelimit())
6885                                 netif_err(tp, drv, tp->dev,
6886                                           "Failed to map TX fragments DMA!\n");
6887                         goto err_out;
6888                 }
6889
6890                 /* Anti gcc 2.95.3 bugware (sic) */
6891                 status = opts[0] | len |
6892                         (RingEnd * !((entry + 1) % NUM_TX_DESC));
6893
6894                 txd->opts1 = cpu_to_le32(status);
6895                 txd->opts2 = cpu_to_le32(opts[1]);
6896                 txd->addr = cpu_to_le64(mapping);
6897
6898                 tp->tx_skb[entry].len = len;
6899         }
6900
6901         if (cur_frag) {
6902                 tp->tx_skb[entry].skb = skb;
6903                 txd->opts1 |= cpu_to_le32(LastFrag);
6904         }
6905
6906         return cur_frag;
6907
6908 err_out:
6909         rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
6910         return -EIO;
6911 }
6912
6913 static bool rtl_test_hw_pad_bug(struct rtl8169_private *tp, struct sk_buff *skb)
6914 {
6915         return skb->len < ETH_ZLEN && tp->mac_version == RTL_GIGA_MAC_VER_34;
6916 }
6917
6918 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
6919                                       struct net_device *dev);
6920 /* r8169_csum_workaround()
6921  * The hw limites the value the transport offset. When the offset is out of the
6922  * range, calculate the checksum by sw.
6923  */
6924 static void r8169_csum_workaround(struct rtl8169_private *tp,
6925                                   struct sk_buff *skb)
6926 {
6927         if (skb_shinfo(skb)->gso_size) {
6928                 netdev_features_t features = tp->dev->features;
6929                 struct sk_buff *segs, *nskb;
6930
6931                 features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
6932                 segs = skb_gso_segment(skb, features);
6933                 if (IS_ERR(segs) || !segs)
6934                         goto drop;
6935
6936                 do {
6937                         nskb = segs;
6938                         segs = segs->next;
6939                         nskb->next = NULL;
6940                         rtl8169_start_xmit(nskb, tp->dev);
6941                 } while (segs);
6942
6943                 dev_consume_skb_any(skb);
6944         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
6945                 if (skb_checksum_help(skb) < 0)
6946                         goto drop;
6947
6948                 rtl8169_start_xmit(skb, tp->dev);
6949         } else {
6950                 struct net_device_stats *stats;
6951
6952 drop:
6953                 stats = &tp->dev->stats;
6954                 stats->tx_dropped++;
6955                 dev_kfree_skb_any(skb);
6956         }
6957 }
6958
6959 /* msdn_giant_send_check()
6960  * According to the document of microsoft, the TCP Pseudo Header excludes the
6961  * packet length for IPv6 TCP large packets.
6962  */
6963 static int msdn_giant_send_check(struct sk_buff *skb)
6964 {
6965         const struct ipv6hdr *ipv6h;
6966         struct tcphdr *th;
6967         int ret;
6968
6969         ret = skb_cow_head(skb, 0);
6970         if (ret)
6971                 return ret;
6972
6973         ipv6h = ipv6_hdr(skb);
6974         th = tcp_hdr(skb);
6975
6976         th->check = 0;
6977         th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0);
6978
6979         return ret;
6980 }
6981
6982 static inline __be16 get_protocol(struct sk_buff *skb)
6983 {
6984         __be16 protocol;
6985
6986         if (skb->protocol == htons(ETH_P_8021Q))
6987                 protocol = vlan_eth_hdr(skb)->h_vlan_encapsulated_proto;
6988         else
6989                 protocol = skb->protocol;
6990
6991         return protocol;
6992 }
6993
6994 static bool rtl8169_tso_csum_v1(struct rtl8169_private *tp,
6995                                 struct sk_buff *skb, u32 *opts)
6996 {
6997         u32 mss = skb_shinfo(skb)->gso_size;
6998
6999         if (mss) {
7000                 opts[0] |= TD_LSO;
7001                 opts[0] |= min(mss, TD_MSS_MAX) << TD0_MSS_SHIFT;
7002         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
7003                 const struct iphdr *ip = ip_hdr(skb);
7004
7005                 if (ip->protocol == IPPROTO_TCP)
7006                         opts[0] |= TD0_IP_CS | TD0_TCP_CS;
7007                 else if (ip->protocol == IPPROTO_UDP)
7008                         opts[0] |= TD0_IP_CS | TD0_UDP_CS;
7009                 else
7010                         WARN_ON_ONCE(1);
7011         }
7012
7013         return true;
7014 }
7015
7016 static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp,
7017                                 struct sk_buff *skb, u32 *opts)
7018 {
7019         u32 transport_offset = (u32)skb_transport_offset(skb);
7020         u32 mss = skb_shinfo(skb)->gso_size;
7021
7022         if (mss) {
7023                 if (transport_offset > GTTCPHO_MAX) {
7024                         netif_warn(tp, tx_err, tp->dev,
7025                                    "Invalid transport offset 0x%x for TSO\n",
7026                                    transport_offset);
7027                         return false;
7028                 }
7029
7030                 switch (get_protocol(skb)) {
7031                 case htons(ETH_P_IP):
7032                         opts[0] |= TD1_GTSENV4;
7033                         break;
7034
7035                 case htons(ETH_P_IPV6):
7036                         if (msdn_giant_send_check(skb))
7037                                 return false;
7038
7039                         opts[0] |= TD1_GTSENV6;
7040                         break;
7041
7042                 default:
7043                         WARN_ON_ONCE(1);
7044                         break;
7045                 }
7046
7047                 opts[0] |= transport_offset << GTTCPHO_SHIFT;
7048                 opts[1] |= min(mss, TD_MSS_MAX) << TD1_MSS_SHIFT;
7049         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
7050                 u8 ip_protocol;
7051
7052                 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
7053                         return !(skb_checksum_help(skb) || eth_skb_pad(skb));
7054
7055                 if (transport_offset > TCPHO_MAX) {
7056                         netif_warn(tp, tx_err, tp->dev,
7057                                    "Invalid transport offset 0x%x\n",
7058                                    transport_offset);
7059                         return false;
7060                 }
7061
7062                 switch (get_protocol(skb)) {
7063                 case htons(ETH_P_IP):
7064                         opts[1] |= TD1_IPv4_CS;
7065                         ip_protocol = ip_hdr(skb)->protocol;
7066                         break;
7067
7068                 case htons(ETH_P_IPV6):
7069                         opts[1] |= TD1_IPv6_CS;
7070                         ip_protocol = ipv6_hdr(skb)->nexthdr;
7071                         break;
7072
7073                 default:
7074                         ip_protocol = IPPROTO_RAW;
7075                         break;
7076                 }
7077
7078                 if (ip_protocol == IPPROTO_TCP)
7079                         opts[1] |= TD1_TCP_CS;
7080                 else if (ip_protocol == IPPROTO_UDP)
7081                         opts[1] |= TD1_UDP_CS;
7082                 else
7083                         WARN_ON_ONCE(1);
7084
7085                 opts[1] |= transport_offset << TCPHO_SHIFT;
7086         } else {
7087                 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
7088                         return !eth_skb_pad(skb);
7089         }
7090
7091         return true;
7092 }
7093
7094 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
7095                                       struct net_device *dev)
7096 {
7097         struct rtl8169_private *tp = netdev_priv(dev);
7098         unsigned int entry = tp->cur_tx % NUM_TX_DESC;
7099         struct TxDesc *txd = tp->TxDescArray + entry;
7100         struct device *d = tp_to_dev(tp);
7101         dma_addr_t mapping;
7102         u32 status, len;
7103         u32 opts[2];
7104         int frags;
7105
7106         if (unlikely(!TX_FRAGS_READY_FOR(tp, skb_shinfo(skb)->nr_frags))) {
7107                 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
7108                 goto err_stop_0;
7109         }
7110
7111         if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
7112                 goto err_stop_0;
7113
7114         opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(skb));
7115         opts[0] = DescOwn;
7116
7117         if (!tp->tso_csum(tp, skb, opts)) {
7118                 r8169_csum_workaround(tp, skb);
7119                 return NETDEV_TX_OK;
7120         }
7121
7122         len = skb_headlen(skb);
7123         mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
7124         if (unlikely(dma_mapping_error(d, mapping))) {
7125                 if (net_ratelimit())
7126                         netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
7127                 goto err_dma_0;
7128         }
7129
7130         tp->tx_skb[entry].len = len;
7131         txd->addr = cpu_to_le64(mapping);
7132
7133         frags = rtl8169_xmit_frags(tp, skb, opts);
7134         if (frags < 0)
7135                 goto err_dma_1;
7136         else if (frags)
7137                 opts[0] |= FirstFrag;
7138         else {
7139                 opts[0] |= FirstFrag | LastFrag;
7140                 tp->tx_skb[entry].skb = skb;
7141         }
7142
7143         txd->opts2 = cpu_to_le32(opts[1]);
7144
7145         skb_tx_timestamp(skb);
7146
7147         /* Force memory writes to complete before releasing descriptor */
7148         dma_wmb();
7149
7150         /* Anti gcc 2.95.3 bugware (sic) */
7151         status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
7152         txd->opts1 = cpu_to_le32(status);
7153
7154         /* Force all memory writes to complete before notifying device */
7155         wmb();
7156
7157         tp->cur_tx += frags + 1;
7158
7159         RTL_W8(tp, TxPoll, NPQ);
7160
7161         mmiowb();
7162
7163         if (!TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
7164                 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
7165                  * not miss a ring update when it notices a stopped queue.
7166                  */
7167                 smp_wmb();
7168                 netif_stop_queue(dev);
7169                 /* Sync with rtl_tx:
7170                  * - publish queue status and cur_tx ring index (write barrier)
7171                  * - refresh dirty_tx ring index (read barrier).
7172                  * May the current thread have a pessimistic view of the ring
7173                  * status and forget to wake up queue, a racing rtl_tx thread
7174                  * can't.
7175                  */
7176                 smp_mb();
7177                 if (TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS))
7178                         netif_wake_queue(dev);
7179         }
7180
7181         return NETDEV_TX_OK;
7182
7183 err_dma_1:
7184         rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
7185 err_dma_0:
7186         dev_kfree_skb_any(skb);
7187         dev->stats.tx_dropped++;
7188         return NETDEV_TX_OK;
7189
7190 err_stop_0:
7191         netif_stop_queue(dev);
7192         dev->stats.tx_dropped++;
7193         return NETDEV_TX_BUSY;
7194 }
7195
7196 static void rtl8169_pcierr_interrupt(struct net_device *dev)
7197 {
7198         struct rtl8169_private *tp = netdev_priv(dev);
7199         struct pci_dev *pdev = tp->pci_dev;
7200         u16 pci_status, pci_cmd;
7201
7202         pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
7203         pci_read_config_word(pdev, PCI_STATUS, &pci_status);
7204
7205         netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
7206                   pci_cmd, pci_status);
7207
7208         /*
7209          * The recovery sequence below admits a very elaborated explanation:
7210          * - it seems to work;
7211          * - I did not see what else could be done;
7212          * - it makes iop3xx happy.
7213          *
7214          * Feel free to adjust to your needs.
7215          */
7216         if (pdev->broken_parity_status)
7217                 pci_cmd &= ~PCI_COMMAND_PARITY;
7218         else
7219                 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
7220
7221         pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
7222
7223         pci_write_config_word(pdev, PCI_STATUS,
7224                 pci_status & (PCI_STATUS_DETECTED_PARITY |
7225                 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
7226                 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
7227
7228         /* The infamous DAC f*ckup only happens at boot time */
7229         if ((tp->cp_cmd & PCIDAC) && !tp->cur_rx) {
7230                 netif_info(tp, intr, dev, "disabling PCI DAC\n");
7231                 tp->cp_cmd &= ~PCIDAC;
7232                 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
7233                 dev->features &= ~NETIF_F_HIGHDMA;
7234         }
7235
7236         rtl8169_hw_reset(tp);
7237
7238         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
7239 }
7240
7241 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp)
7242 {
7243         unsigned int dirty_tx, tx_left;
7244
7245         dirty_tx = tp->dirty_tx;
7246         smp_rmb();
7247         tx_left = tp->cur_tx - dirty_tx;
7248
7249         while (tx_left > 0) {
7250                 unsigned int entry = dirty_tx % NUM_TX_DESC;
7251                 struct ring_info *tx_skb = tp->tx_skb + entry;
7252                 u32 status;
7253
7254                 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
7255                 if (status & DescOwn)
7256                         break;
7257
7258                 /* This barrier is needed to keep us from reading
7259                  * any other fields out of the Tx descriptor until
7260                  * we know the status of DescOwn
7261                  */
7262                 dma_rmb();
7263
7264                 rtl8169_unmap_tx_skb(tp_to_dev(tp), tx_skb,
7265                                      tp->TxDescArray + entry);
7266                 if (status & LastFrag) {
7267                         u64_stats_update_begin(&tp->tx_stats.syncp);
7268                         tp->tx_stats.packets++;
7269                         tp->tx_stats.bytes += tx_skb->skb->len;
7270                         u64_stats_update_end(&tp->tx_stats.syncp);
7271                         dev_consume_skb_any(tx_skb->skb);
7272                         tx_skb->skb = NULL;
7273                 }
7274                 dirty_tx++;
7275                 tx_left--;
7276         }
7277
7278         if (tp->dirty_tx != dirty_tx) {
7279                 tp->dirty_tx = dirty_tx;
7280                 /* Sync with rtl8169_start_xmit:
7281                  * - publish dirty_tx ring index (write barrier)
7282                  * - refresh cur_tx ring index and queue status (read barrier)
7283                  * May the current thread miss the stopped queue condition,
7284                  * a racing xmit thread can only have a right view of the
7285                  * ring status.
7286                  */
7287                 smp_mb();
7288                 if (netif_queue_stopped(dev) &&
7289                     TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
7290                         netif_wake_queue(dev);
7291                 }
7292                 /*
7293                  * 8168 hack: TxPoll requests are lost when the Tx packets are
7294                  * too close. Let's kick an extra TxPoll request when a burst
7295                  * of start_xmit activity is detected (if it is not detected,
7296                  * it is slow enough). -- FR
7297                  */
7298                 if (tp->cur_tx != dirty_tx)
7299                         RTL_W8(tp, TxPoll, NPQ);
7300         }
7301 }
7302
7303 static inline int rtl8169_fragmented_frame(u32 status)
7304 {
7305         return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
7306 }
7307
7308 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
7309 {
7310         u32 status = opts1 & RxProtoMask;
7311
7312         if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
7313             ((status == RxProtoUDP) && !(opts1 & UDPFail)))
7314                 skb->ip_summed = CHECKSUM_UNNECESSARY;
7315         else
7316                 skb_checksum_none_assert(skb);
7317 }
7318
7319 static struct sk_buff *rtl8169_try_rx_copy(void *data,
7320                                            struct rtl8169_private *tp,
7321                                            int pkt_size,
7322                                            dma_addr_t addr)
7323 {
7324         struct sk_buff *skb;
7325         struct device *d = tp_to_dev(tp);
7326
7327         data = rtl8169_align(data);
7328         dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
7329         prefetch(data);
7330         skb = napi_alloc_skb(&tp->napi, pkt_size);
7331         if (skb)
7332                 skb_copy_to_linear_data(skb, data, pkt_size);
7333         dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
7334
7335         return skb;
7336 }
7337
7338 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget)
7339 {
7340         unsigned int cur_rx, rx_left;
7341         unsigned int count;
7342
7343         cur_rx = tp->cur_rx;
7344
7345         for (rx_left = min(budget, NUM_RX_DESC); rx_left > 0; rx_left--, cur_rx++) {
7346                 unsigned int entry = cur_rx % NUM_RX_DESC;
7347                 struct RxDesc *desc = tp->RxDescArray + entry;
7348                 u32 status;
7349
7350                 status = le32_to_cpu(desc->opts1) & tp->opts1_mask;
7351                 if (status & DescOwn)
7352                         break;
7353
7354                 /* This barrier is needed to keep us from reading
7355                  * any other fields out of the Rx descriptor until
7356                  * we know the status of DescOwn
7357                  */
7358                 dma_rmb();
7359
7360                 if (unlikely(status & RxRES)) {
7361                         netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
7362                                    status);
7363                         dev->stats.rx_errors++;
7364                         if (status & (RxRWT | RxRUNT))
7365                                 dev->stats.rx_length_errors++;
7366                         if (status & RxCRC)
7367                                 dev->stats.rx_crc_errors++;
7368                         if (status & RxFOVF) {
7369                                 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
7370                                 dev->stats.rx_fifo_errors++;
7371                         }
7372                         if ((status & (RxRUNT | RxCRC)) &&
7373                             !(status & (RxRWT | RxFOVF)) &&
7374                             (dev->features & NETIF_F_RXALL))
7375                                 goto process_pkt;
7376                 } else {
7377                         struct sk_buff *skb;
7378                         dma_addr_t addr;
7379                         int pkt_size;
7380
7381 process_pkt:
7382                         addr = le64_to_cpu(desc->addr);
7383                         if (likely(!(dev->features & NETIF_F_RXFCS)))
7384                                 pkt_size = (status & 0x00003fff) - 4;
7385                         else
7386                                 pkt_size = status & 0x00003fff;
7387
7388                         /*
7389                          * The driver does not support incoming fragmented
7390                          * frames. They are seen as a symptom of over-mtu
7391                          * sized frames.
7392                          */
7393                         if (unlikely(rtl8169_fragmented_frame(status))) {
7394                                 dev->stats.rx_dropped++;
7395                                 dev->stats.rx_length_errors++;
7396                                 goto release_descriptor;
7397                         }
7398
7399                         skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
7400                                                   tp, pkt_size, addr);
7401                         if (!skb) {
7402                                 dev->stats.rx_dropped++;
7403                                 goto release_descriptor;
7404                         }
7405
7406                         rtl8169_rx_csum(skb, status);
7407                         skb_put(skb, pkt_size);
7408                         skb->protocol = eth_type_trans(skb, dev);
7409
7410                         rtl8169_rx_vlan_tag(desc, skb);
7411
7412                         if (skb->pkt_type == PACKET_MULTICAST)
7413                                 dev->stats.multicast++;
7414
7415                         napi_gro_receive(&tp->napi, skb);
7416
7417                         u64_stats_update_begin(&tp->rx_stats.syncp);
7418                         tp->rx_stats.packets++;
7419                         tp->rx_stats.bytes += pkt_size;
7420                         u64_stats_update_end(&tp->rx_stats.syncp);
7421                 }
7422 release_descriptor:
7423                 desc->opts2 = 0;
7424                 rtl8169_mark_to_asic(desc);
7425         }
7426
7427         count = cur_rx - tp->cur_rx;
7428         tp->cur_rx = cur_rx;
7429
7430         return count;
7431 }
7432
7433 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
7434 {
7435         struct rtl8169_private *tp = dev_instance;
7436         int handled = 0;
7437         u16 status;
7438
7439         status = rtl_get_events(tp);
7440         if (status && status != 0xffff) {
7441                 status &= RTL_EVENT_NAPI | tp->event_slow;
7442                 if (status) {
7443                         handled = 1;
7444
7445                         rtl_irq_disable(tp);
7446                         napi_schedule_irqoff(&tp->napi);
7447                 }
7448         }
7449         return IRQ_RETVAL(handled);
7450 }
7451
7452 /*
7453  * Workqueue context.
7454  */
7455 static void rtl_slow_event_work(struct rtl8169_private *tp)
7456 {
7457         struct net_device *dev = tp->dev;
7458         u16 status;
7459
7460         status = rtl_get_events(tp) & tp->event_slow;
7461         rtl_ack_events(tp, status);
7462
7463         if (unlikely(status & RxFIFOOver)) {
7464                 switch (tp->mac_version) {
7465                 /* Work around for rx fifo overflow */
7466                 case RTL_GIGA_MAC_VER_11:
7467                         netif_stop_queue(dev);
7468                         /* XXX - Hack alert. See rtl_task(). */
7469                         set_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags);
7470                 default:
7471                         break;
7472                 }
7473         }
7474
7475         if (unlikely(status & SYSErr))
7476                 rtl8169_pcierr_interrupt(dev);
7477
7478         if (status & LinkChg)
7479                 rtl8169_check_link_status(dev, tp);
7480
7481         rtl_irq_enable_all(tp);
7482 }
7483
7484 static void rtl_task(struct work_struct *work)
7485 {
7486         static const struct {
7487                 int bitnr;
7488                 void (*action)(struct rtl8169_private *);
7489         } rtl_work[] = {
7490                 /* XXX - keep rtl_slow_event_work() as first element. */
7491                 { RTL_FLAG_TASK_SLOW_PENDING,   rtl_slow_event_work },
7492                 { RTL_FLAG_TASK_RESET_PENDING,  rtl_reset_work },
7493                 { RTL_FLAG_TASK_PHY_PENDING,    rtl_phy_work }
7494         };
7495         struct rtl8169_private *tp =
7496                 container_of(work, struct rtl8169_private, wk.work);
7497         struct net_device *dev = tp->dev;
7498         int i;
7499
7500         rtl_lock_work(tp);
7501
7502         if (!netif_running(dev) ||
7503             !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
7504                 goto out_unlock;
7505
7506         for (i = 0; i < ARRAY_SIZE(rtl_work); i++) {
7507                 bool pending;
7508
7509                 pending = test_and_clear_bit(rtl_work[i].bitnr, tp->wk.flags);
7510                 if (pending)
7511                         rtl_work[i].action(tp);
7512         }
7513
7514 out_unlock:
7515         rtl_unlock_work(tp);
7516 }
7517
7518 static int rtl8169_poll(struct napi_struct *napi, int budget)
7519 {
7520         struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
7521         struct net_device *dev = tp->dev;
7522         u16 enable_mask = RTL_EVENT_NAPI | tp->event_slow;
7523         int work_done= 0;
7524         u16 status;
7525
7526         status = rtl_get_events(tp);
7527         rtl_ack_events(tp, status & ~tp->event_slow);
7528
7529         if (status & RTL_EVENT_NAPI_RX)
7530                 work_done = rtl_rx(dev, tp, (u32) budget);
7531
7532         if (status & RTL_EVENT_NAPI_TX)
7533                 rtl_tx(dev, tp);
7534
7535         if (status & tp->event_slow) {
7536                 enable_mask &= ~tp->event_slow;
7537
7538                 rtl_schedule_task(tp, RTL_FLAG_TASK_SLOW_PENDING);
7539         }
7540
7541         if (work_done < budget) {
7542                 napi_complete_done(napi, work_done);
7543
7544                 rtl_irq_enable(tp, enable_mask);
7545                 mmiowb();
7546         }
7547
7548         return work_done;
7549 }
7550
7551 static void rtl8169_rx_missed(struct net_device *dev)
7552 {
7553         struct rtl8169_private *tp = netdev_priv(dev);
7554
7555         if (tp->mac_version > RTL_GIGA_MAC_VER_06)
7556                 return;
7557
7558         dev->stats.rx_missed_errors += RTL_R32(tp, RxMissed) & 0xffffff;
7559         RTL_W32(tp, RxMissed, 0);
7560 }
7561
7562 static void rtl8169_down(struct net_device *dev)
7563 {
7564         struct rtl8169_private *tp = netdev_priv(dev);
7565
7566         del_timer_sync(&tp->timer);
7567
7568         napi_disable(&tp->napi);
7569         netif_stop_queue(dev);
7570
7571         rtl8169_hw_reset(tp);
7572         /*
7573          * At this point device interrupts can not be enabled in any function,
7574          * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task)
7575          * and napi is disabled (rtl8169_poll).
7576          */
7577         rtl8169_rx_missed(dev);
7578
7579         /* Give a racing hard_start_xmit a few cycles to complete. */
7580         synchronize_sched();
7581
7582         rtl8169_tx_clear(tp);
7583
7584         rtl8169_rx_clear(tp);
7585
7586         rtl_pll_power_down(tp);
7587 }
7588
7589 static int rtl8169_close(struct net_device *dev)
7590 {
7591         struct rtl8169_private *tp = netdev_priv(dev);
7592         struct pci_dev *pdev = tp->pci_dev;
7593
7594         pm_runtime_get_sync(&pdev->dev);
7595
7596         /* Update counters before going down */
7597         rtl8169_update_counters(tp);
7598
7599         rtl_lock_work(tp);
7600         clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
7601
7602         rtl8169_down(dev);
7603         rtl_unlock_work(tp);
7604
7605         cancel_work_sync(&tp->wk.work);
7606
7607         pci_free_irq(pdev, 0, tp);
7608
7609         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
7610                           tp->RxPhyAddr);
7611         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
7612                           tp->TxPhyAddr);
7613         tp->TxDescArray = NULL;
7614         tp->RxDescArray = NULL;
7615
7616         pm_runtime_put_sync(&pdev->dev);
7617
7618         return 0;
7619 }
7620
7621 #ifdef CONFIG_NET_POLL_CONTROLLER
7622 static void rtl8169_netpoll(struct net_device *dev)
7623 {
7624         struct rtl8169_private *tp = netdev_priv(dev);
7625
7626         rtl8169_interrupt(pci_irq_vector(tp->pci_dev, 0), dev);
7627 }
7628 #endif
7629
7630 static int rtl_open(struct net_device *dev)
7631 {
7632         struct rtl8169_private *tp = netdev_priv(dev);
7633         struct pci_dev *pdev = tp->pci_dev;
7634         int retval = -ENOMEM;
7635
7636         pm_runtime_get_sync(&pdev->dev);
7637
7638         /*
7639          * Rx and Tx descriptors needs 256 bytes alignment.
7640          * dma_alloc_coherent provides more.
7641          */
7642         tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
7643                                              &tp->TxPhyAddr, GFP_KERNEL);
7644         if (!tp->TxDescArray)
7645                 goto err_pm_runtime_put;
7646
7647         tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
7648                                              &tp->RxPhyAddr, GFP_KERNEL);
7649         if (!tp->RxDescArray)
7650                 goto err_free_tx_0;
7651
7652         retval = rtl8169_init_ring(tp);
7653         if (retval < 0)
7654                 goto err_free_rx_1;
7655
7656         INIT_WORK(&tp->wk.work, rtl_task);
7657
7658         smp_mb();
7659
7660         rtl_request_firmware(tp);
7661
7662         retval = pci_request_irq(pdev, 0, rtl8169_interrupt, NULL, tp,
7663                                  dev->name);
7664         if (retval < 0)
7665                 goto err_release_fw_2;
7666
7667         rtl_lock_work(tp);
7668
7669         set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
7670
7671         napi_enable(&tp->napi);
7672
7673         rtl8169_init_phy(dev, tp);
7674
7675         __rtl8169_set_features(dev, dev->features);
7676
7677         rtl_pll_power_up(tp);
7678
7679         rtl_hw_start(tp);
7680
7681         if (!rtl8169_init_counter_offsets(tp))
7682                 netif_warn(tp, hw, dev, "counter reset/update failed\n");
7683
7684         netif_start_queue(dev);
7685
7686         rtl_unlock_work(tp);
7687
7688         tp->saved_wolopts = 0;
7689         pm_runtime_put_sync(&pdev->dev);
7690
7691         rtl8169_check_link_status(dev, tp);
7692 out:
7693         return retval;
7694
7695 err_release_fw_2:
7696         rtl_release_firmware(tp);
7697         rtl8169_rx_clear(tp);
7698 err_free_rx_1:
7699         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
7700                           tp->RxPhyAddr);
7701         tp->RxDescArray = NULL;
7702 err_free_tx_0:
7703         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
7704                           tp->TxPhyAddr);
7705         tp->TxDescArray = NULL;
7706 err_pm_runtime_put:
7707         pm_runtime_put_noidle(&pdev->dev);
7708         goto out;
7709 }
7710
7711 static void
7712 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
7713 {
7714         struct rtl8169_private *tp = netdev_priv(dev);
7715         struct pci_dev *pdev = tp->pci_dev;
7716         struct rtl8169_counters *counters = tp->counters;
7717         unsigned int start;
7718
7719         pm_runtime_get_noresume(&pdev->dev);
7720
7721         if (netif_running(dev) && pm_runtime_active(&pdev->dev))
7722                 rtl8169_rx_missed(dev);
7723
7724         do {
7725                 start = u64_stats_fetch_begin_irq(&tp->rx_stats.syncp);
7726                 stats->rx_packets = tp->rx_stats.packets;
7727                 stats->rx_bytes = tp->rx_stats.bytes;
7728         } while (u64_stats_fetch_retry_irq(&tp->rx_stats.syncp, start));
7729
7730         do {
7731                 start = u64_stats_fetch_begin_irq(&tp->tx_stats.syncp);
7732                 stats->tx_packets = tp->tx_stats.packets;
7733                 stats->tx_bytes = tp->tx_stats.bytes;
7734         } while (u64_stats_fetch_retry_irq(&tp->tx_stats.syncp, start));
7735
7736         stats->rx_dropped       = dev->stats.rx_dropped;
7737         stats->tx_dropped       = dev->stats.tx_dropped;
7738         stats->rx_length_errors = dev->stats.rx_length_errors;
7739         stats->rx_errors        = dev->stats.rx_errors;
7740         stats->rx_crc_errors    = dev->stats.rx_crc_errors;
7741         stats->rx_fifo_errors   = dev->stats.rx_fifo_errors;
7742         stats->rx_missed_errors = dev->stats.rx_missed_errors;
7743         stats->multicast        = dev->stats.multicast;
7744
7745         /*
7746          * Fetch additonal counter values missing in stats collected by driver
7747          * from tally counters.
7748          */
7749         if (pm_runtime_active(&pdev->dev))
7750                 rtl8169_update_counters(tp);
7751
7752         /*
7753          * Subtract values fetched during initalization.
7754          * See rtl8169_init_counter_offsets for a description why we do that.
7755          */
7756         stats->tx_errors = le64_to_cpu(counters->tx_errors) -
7757                 le64_to_cpu(tp->tc_offset.tx_errors);
7758         stats->collisions = le32_to_cpu(counters->tx_multi_collision) -
7759                 le32_to_cpu(tp->tc_offset.tx_multi_collision);
7760         stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) -
7761                 le16_to_cpu(tp->tc_offset.tx_aborted);
7762
7763         pm_runtime_put_noidle(&pdev->dev);
7764 }
7765
7766 static void rtl8169_net_suspend(struct net_device *dev)
7767 {
7768         struct rtl8169_private *tp = netdev_priv(dev);
7769
7770         if (!netif_running(dev))
7771                 return;
7772
7773         netif_device_detach(dev);
7774         netif_stop_queue(dev);
7775
7776         rtl_lock_work(tp);
7777         napi_disable(&tp->napi);
7778         clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
7779         rtl_unlock_work(tp);
7780
7781         rtl_pll_power_down(tp);
7782 }
7783
7784 #ifdef CONFIG_PM
7785
7786 static int rtl8169_suspend(struct device *device)
7787 {
7788         struct pci_dev *pdev = to_pci_dev(device);
7789         struct net_device *dev = pci_get_drvdata(pdev);
7790
7791         rtl8169_net_suspend(dev);
7792
7793         return 0;
7794 }
7795
7796 static void __rtl8169_resume(struct net_device *dev)
7797 {
7798         struct rtl8169_private *tp = netdev_priv(dev);
7799
7800         netif_device_attach(dev);
7801
7802         rtl_pll_power_up(tp);
7803
7804         rtl_lock_work(tp);
7805         napi_enable(&tp->napi);
7806         set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
7807         rtl_unlock_work(tp);
7808
7809         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
7810 }
7811
7812 static int rtl8169_resume(struct device *device)
7813 {
7814         struct pci_dev *pdev = to_pci_dev(device);
7815         struct net_device *dev = pci_get_drvdata(pdev);
7816         struct rtl8169_private *tp = netdev_priv(dev);
7817
7818         rtl8169_init_phy(dev, tp);
7819
7820         if (netif_running(dev))
7821                 __rtl8169_resume(dev);
7822
7823         return 0;
7824 }
7825
7826 static int rtl8169_runtime_suspend(struct device *device)
7827 {
7828         struct pci_dev *pdev = to_pci_dev(device);
7829         struct net_device *dev = pci_get_drvdata(pdev);
7830         struct rtl8169_private *tp = netdev_priv(dev);
7831
7832         if (!tp->TxDescArray) {
7833                 rtl_pll_power_down(tp);
7834                 return 0;
7835         }
7836
7837         rtl_lock_work(tp);
7838         tp->saved_wolopts = __rtl8169_get_wol(tp);
7839         __rtl8169_set_wol(tp, WAKE_ANY);
7840         rtl_unlock_work(tp);
7841
7842         rtl8169_net_suspend(dev);
7843
7844         /* Update counters before going runtime suspend */
7845         rtl8169_rx_missed(dev);
7846         rtl8169_update_counters(tp);
7847
7848         return 0;
7849 }
7850
7851 static int rtl8169_runtime_resume(struct device *device)
7852 {
7853         struct pci_dev *pdev = to_pci_dev(device);
7854         struct net_device *dev = pci_get_drvdata(pdev);
7855         struct rtl8169_private *tp = netdev_priv(dev);
7856         rtl_rar_set(tp, dev->dev_addr);
7857
7858         if (!tp->TxDescArray)
7859                 return 0;
7860
7861         rtl_lock_work(tp);
7862         __rtl8169_set_wol(tp, tp->saved_wolopts);
7863         tp->saved_wolopts = 0;
7864         rtl_unlock_work(tp);
7865
7866         rtl8169_init_phy(dev, tp);
7867
7868         __rtl8169_resume(dev);
7869
7870         return 0;
7871 }
7872
7873 static int rtl8169_runtime_idle(struct device *device)
7874 {
7875         struct pci_dev *pdev = to_pci_dev(device);
7876         struct net_device *dev = pci_get_drvdata(pdev);
7877
7878         if (!netif_running(dev) || !netif_carrier_ok(dev))
7879                 pm_schedule_suspend(device, 10000);
7880
7881         return -EBUSY;
7882 }
7883
7884 static const struct dev_pm_ops rtl8169_pm_ops = {
7885         .suspend                = rtl8169_suspend,
7886         .resume                 = rtl8169_resume,
7887         .freeze                 = rtl8169_suspend,
7888         .thaw                   = rtl8169_resume,
7889         .poweroff               = rtl8169_suspend,
7890         .restore                = rtl8169_resume,
7891         .runtime_suspend        = rtl8169_runtime_suspend,
7892         .runtime_resume         = rtl8169_runtime_resume,
7893         .runtime_idle           = rtl8169_runtime_idle,
7894 };
7895
7896 #define RTL8169_PM_OPS  (&rtl8169_pm_ops)
7897
7898 #else /* !CONFIG_PM */
7899
7900 #define RTL8169_PM_OPS  NULL
7901
7902 #endif /* !CONFIG_PM */
7903
7904 static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
7905 {
7906         /* WoL fails with 8168b when the receiver is disabled. */
7907         switch (tp->mac_version) {
7908         case RTL_GIGA_MAC_VER_11:
7909         case RTL_GIGA_MAC_VER_12:
7910         case RTL_GIGA_MAC_VER_17:
7911                 pci_clear_master(tp->pci_dev);
7912
7913                 RTL_W8(tp, ChipCmd, CmdRxEnb);
7914                 /* PCI commit */
7915                 RTL_R8(tp, ChipCmd);
7916                 break;
7917         default:
7918                 break;
7919         }
7920 }
7921
7922 static void rtl_shutdown(struct pci_dev *pdev)
7923 {
7924         struct net_device *dev = pci_get_drvdata(pdev);
7925         struct rtl8169_private *tp = netdev_priv(dev);
7926
7927         rtl8169_net_suspend(dev);
7928
7929         /* Restore original MAC address */
7930         rtl_rar_set(tp, dev->perm_addr);
7931
7932         rtl8169_hw_reset(tp);
7933
7934         if (system_state == SYSTEM_POWER_OFF) {
7935                 if (__rtl8169_get_wol(tp) & WAKE_ANY) {
7936                         rtl_wol_suspend_quirk(tp);
7937                         rtl_wol_shutdown_quirk(tp);
7938                 }
7939
7940                 pci_wake_from_d3(pdev, true);
7941                 pci_set_power_state(pdev, PCI_D3hot);
7942         }
7943 }
7944
7945 static void rtl_remove_one(struct pci_dev *pdev)
7946 {
7947         struct net_device *dev = pci_get_drvdata(pdev);
7948         struct rtl8169_private *tp = netdev_priv(dev);
7949
7950         if (r8168_check_dash(tp))
7951                 rtl8168_driver_stop(tp);
7952
7953         netif_napi_del(&tp->napi);
7954
7955         unregister_netdev(dev);
7956
7957         rtl_release_firmware(tp);
7958
7959         if (pci_dev_run_wake(pdev))
7960                 pm_runtime_get_noresume(&pdev->dev);
7961
7962         /* restore original MAC address */
7963         rtl_rar_set(tp, dev->perm_addr);
7964 }
7965
7966 static const struct net_device_ops rtl_netdev_ops = {
7967         .ndo_open               = rtl_open,
7968         .ndo_stop               = rtl8169_close,
7969         .ndo_get_stats64        = rtl8169_get_stats64,
7970         .ndo_start_xmit         = rtl8169_start_xmit,
7971         .ndo_tx_timeout         = rtl8169_tx_timeout,
7972         .ndo_validate_addr      = eth_validate_addr,
7973         .ndo_change_mtu         = rtl8169_change_mtu,
7974         .ndo_fix_features       = rtl8169_fix_features,
7975         .ndo_set_features       = rtl8169_set_features,
7976         .ndo_set_mac_address    = rtl_set_mac_address,
7977         .ndo_do_ioctl           = rtl8169_ioctl,
7978         .ndo_set_rx_mode        = rtl_set_rx_mode,
7979 #ifdef CONFIG_NET_POLL_CONTROLLER
7980         .ndo_poll_controller    = rtl8169_netpoll,
7981 #endif
7982
7983 };
7984
7985 static const struct rtl_cfg_info {
7986         void (*hw_start)(struct rtl8169_private *tp);
7987         unsigned int region;
7988         u16 event_slow;
7989         unsigned int has_gmii:1;
7990         const struct rtl_coalesce_info *coalesce_info;
7991         u8 default_ver;
7992 } rtl_cfg_infos [] = {
7993         [RTL_CFG_0] = {
7994                 .hw_start       = rtl_hw_start_8169,
7995                 .region         = 1,
7996                 .event_slow     = SYSErr | LinkChg | RxOverflow | RxFIFOOver,
7997                 .has_gmii       = 1,
7998                 .coalesce_info  = rtl_coalesce_info_8169,
7999                 .default_ver    = RTL_GIGA_MAC_VER_01,
8000         },
8001         [RTL_CFG_1] = {
8002                 .hw_start       = rtl_hw_start_8168,
8003                 .region         = 2,
8004                 .event_slow     = SYSErr | LinkChg | RxOverflow,
8005                 .has_gmii       = 1,
8006                 .coalesce_info  = rtl_coalesce_info_8168_8136,
8007                 .default_ver    = RTL_GIGA_MAC_VER_11,
8008         },
8009         [RTL_CFG_2] = {
8010                 .hw_start       = rtl_hw_start_8101,
8011                 .region         = 2,
8012                 .event_slow     = SYSErr | LinkChg | RxOverflow | RxFIFOOver |
8013                                   PCSTimeout,
8014                 .coalesce_info  = rtl_coalesce_info_8168_8136,
8015                 .default_ver    = RTL_GIGA_MAC_VER_13,
8016         }
8017 };
8018
8019 static int rtl_alloc_irq(struct rtl8169_private *tp)
8020 {
8021         unsigned int flags;
8022
8023         if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
8024                 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
8025                 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~MSIEnable);
8026                 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
8027                 flags = PCI_IRQ_LEGACY;
8028         } else {
8029                 flags = PCI_IRQ_ALL_TYPES;
8030         }
8031
8032         return pci_alloc_irq_vectors(tp->pci_dev, 1, 1, flags);
8033 }
8034
8035 DECLARE_RTL_COND(rtl_link_list_ready_cond)
8036 {
8037         return RTL_R8(tp, MCU) & LINK_LIST_RDY;
8038 }
8039
8040 DECLARE_RTL_COND(rtl_rxtx_empty_cond)
8041 {
8042         return (RTL_R8(tp, MCU) & RXTX_EMPTY) == RXTX_EMPTY;
8043 }
8044
8045 static void rtl_hw_init_8168g(struct rtl8169_private *tp)
8046 {
8047         u32 data;
8048
8049         tp->ocp_base = OCP_STD_PHY_BASE;
8050
8051         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN);
8052
8053         if (!rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42))
8054                 return;
8055
8056         if (!rtl_udelay_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42))
8057                 return;
8058
8059         RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
8060         msleep(1);
8061         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
8062
8063         data = r8168_mac_ocp_read(tp, 0xe8de);
8064         data &= ~(1 << 14);
8065         r8168_mac_ocp_write(tp, 0xe8de, data);
8066
8067         if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
8068                 return;
8069
8070         data = r8168_mac_ocp_read(tp, 0xe8de);
8071         data |= (1 << 15);
8072         r8168_mac_ocp_write(tp, 0xe8de, data);
8073
8074         if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
8075                 return;
8076 }
8077
8078 static void rtl_hw_init_8168ep(struct rtl8169_private *tp)
8079 {
8080         rtl8168ep_stop_cmac(tp);
8081         rtl_hw_init_8168g(tp);
8082 }
8083
8084 static void rtl_hw_initialize(struct rtl8169_private *tp)
8085 {
8086         switch (tp->mac_version) {
8087         case RTL_GIGA_MAC_VER_40:
8088         case RTL_GIGA_MAC_VER_41:
8089         case RTL_GIGA_MAC_VER_42:
8090         case RTL_GIGA_MAC_VER_43:
8091         case RTL_GIGA_MAC_VER_44:
8092         case RTL_GIGA_MAC_VER_45:
8093         case RTL_GIGA_MAC_VER_46:
8094         case RTL_GIGA_MAC_VER_47:
8095         case RTL_GIGA_MAC_VER_48:
8096                 rtl_hw_init_8168g(tp);
8097                 break;
8098         case RTL_GIGA_MAC_VER_49:
8099         case RTL_GIGA_MAC_VER_50:
8100         case RTL_GIGA_MAC_VER_51:
8101                 rtl_hw_init_8168ep(tp);
8102                 break;
8103         default:
8104                 break;
8105         }
8106 }
8107
8108 static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
8109 {
8110         const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
8111         const unsigned int region = cfg->region;
8112         struct rtl8169_private *tp;
8113         struct mii_if_info *mii;
8114         struct net_device *dev;
8115         int chipset, i;
8116         int rc;
8117
8118         if (netif_msg_drv(&debug)) {
8119                 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
8120                        MODULENAME, RTL8169_VERSION);
8121         }
8122
8123         dev = devm_alloc_etherdev(&pdev->dev, sizeof (*tp));
8124         if (!dev)
8125                 return -ENOMEM;
8126
8127         SET_NETDEV_DEV(dev, &pdev->dev);
8128         dev->netdev_ops = &rtl_netdev_ops;
8129         tp = netdev_priv(dev);
8130         tp->dev = dev;
8131         tp->pci_dev = pdev;
8132         tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
8133
8134         mii = &tp->mii;
8135         mii->dev = dev;
8136         mii->mdio_read = rtl_mdio_read;
8137         mii->mdio_write = rtl_mdio_write;
8138         mii->phy_id_mask = 0x1f;
8139         mii->reg_num_mask = 0x1f;
8140         mii->supports_gmii = cfg->has_gmii;
8141
8142         /* disable ASPM completely as that cause random device stop working
8143          * problems as well as full system hangs for some PCIe devices users */
8144         pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
8145                                      PCIE_LINK_STATE_CLKPM);
8146
8147         /* enable device (incl. PCI PM wakeup and hotplug setup) */
8148         rc = pcim_enable_device(pdev);
8149         if (rc < 0) {
8150                 netif_err(tp, probe, dev, "enable failure\n");
8151                 return rc;
8152         }
8153
8154         if (pcim_set_mwi(pdev) < 0)
8155                 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
8156
8157         /* make sure PCI base addr 1 is MMIO */
8158         if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
8159                 netif_err(tp, probe, dev,
8160                           "region #%d not an MMIO resource, aborting\n",
8161                           region);
8162                 return -ENODEV;
8163         }
8164
8165         /* check for weird/broken PCI region reporting */
8166         if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
8167                 netif_err(tp, probe, dev,
8168                           "Invalid PCI region size(s), aborting\n");
8169                 return -ENODEV;
8170         }
8171
8172         rc = pcim_iomap_regions(pdev, BIT(region), MODULENAME);
8173         if (rc < 0) {
8174                 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
8175                 return rc;
8176         }
8177
8178         tp->mmio_addr = pcim_iomap_table(pdev)[region];
8179
8180         if (!pci_is_pcie(pdev))
8181                 netif_info(tp, probe, dev, "not PCI Express\n");
8182
8183         /* Identify chip attached to board */
8184         rtl8169_get_mac_version(tp, dev, cfg->default_ver);
8185
8186         tp->cp_cmd = 0;
8187
8188         if ((sizeof(dma_addr_t) > 4) &&
8189             (use_dac == 1 || (use_dac == -1 && pci_is_pcie(pdev) &&
8190                               tp->mac_version >= RTL_GIGA_MAC_VER_18)) &&
8191             !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) &&
8192             !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
8193
8194                 /* CPlusCmd Dual Access Cycle is only needed for non-PCIe */
8195                 if (!pci_is_pcie(pdev))
8196                         tp->cp_cmd |= PCIDAC;
8197                 dev->features |= NETIF_F_HIGHDMA;
8198         } else {
8199                 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
8200                 if (rc < 0) {
8201                         netif_err(tp, probe, dev, "DMA configuration failed\n");
8202                         return rc;
8203                 }
8204         }
8205
8206         rtl_init_rxcfg(tp);
8207
8208         rtl_irq_disable(tp);
8209
8210         rtl_hw_initialize(tp);
8211
8212         rtl_hw_reset(tp);
8213
8214         rtl_ack_events(tp, 0xffff);
8215
8216         pci_set_master(pdev);
8217
8218         rtl_init_mdio_ops(tp);
8219         rtl_init_pll_power_ops(tp);
8220         rtl_init_jumbo_ops(tp);
8221         rtl_init_csi_ops(tp);
8222
8223         rtl8169_print_mac_version(tp);
8224
8225         chipset = tp->mac_version;
8226         tp->txd_version = rtl_chip_infos[chipset].txd_version;
8227
8228         rc = rtl_alloc_irq(tp);
8229         if (rc < 0) {
8230                 netif_err(tp, probe, dev, "Can't allocate interrupt\n");
8231                 return rc;
8232         }
8233
8234         /* override BIOS settings, use userspace tools to enable WOL */
8235         __rtl8169_set_wol(tp, 0);
8236
8237         if (rtl_tbi_enabled(tp)) {
8238                 tp->set_speed = rtl8169_set_speed_tbi;
8239                 tp->get_link_ksettings = rtl8169_get_link_ksettings_tbi;
8240                 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
8241                 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
8242                 tp->link_ok = rtl8169_tbi_link_ok;
8243                 tp->do_ioctl = rtl_tbi_ioctl;
8244         } else {
8245                 tp->set_speed = rtl8169_set_speed_xmii;
8246                 tp->get_link_ksettings = rtl8169_get_link_ksettings_xmii;
8247                 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
8248                 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
8249                 tp->link_ok = rtl8169_xmii_link_ok;
8250                 tp->do_ioctl = rtl_xmii_ioctl;
8251         }
8252
8253         mutex_init(&tp->wk.mutex);
8254         u64_stats_init(&tp->rx_stats.syncp);
8255         u64_stats_init(&tp->tx_stats.syncp);
8256
8257         /* Get MAC address */
8258         if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
8259             tp->mac_version == RTL_GIGA_MAC_VER_36 ||
8260             tp->mac_version == RTL_GIGA_MAC_VER_37 ||
8261             tp->mac_version == RTL_GIGA_MAC_VER_38 ||
8262             tp->mac_version == RTL_GIGA_MAC_VER_40 ||
8263             tp->mac_version == RTL_GIGA_MAC_VER_41 ||
8264             tp->mac_version == RTL_GIGA_MAC_VER_42 ||
8265             tp->mac_version == RTL_GIGA_MAC_VER_43 ||
8266             tp->mac_version == RTL_GIGA_MAC_VER_44 ||
8267             tp->mac_version == RTL_GIGA_MAC_VER_45 ||
8268             tp->mac_version == RTL_GIGA_MAC_VER_46 ||
8269             tp->mac_version == RTL_GIGA_MAC_VER_47 ||
8270             tp->mac_version == RTL_GIGA_MAC_VER_48 ||
8271             tp->mac_version == RTL_GIGA_MAC_VER_49 ||
8272             tp->mac_version == RTL_GIGA_MAC_VER_50 ||
8273             tp->mac_version == RTL_GIGA_MAC_VER_51) {
8274                 u16 mac_addr[3];
8275
8276                 *(u32 *)&mac_addr[0] = rtl_eri_read(tp, 0xe0, ERIAR_EXGMAC);
8277                 *(u16 *)&mac_addr[2] = rtl_eri_read(tp, 0xe4, ERIAR_EXGMAC);
8278
8279                 if (is_valid_ether_addr((u8 *)mac_addr))
8280                         rtl_rar_set(tp, (u8 *)mac_addr);
8281         }
8282         for (i = 0; i < ETH_ALEN; i++)
8283                 dev->dev_addr[i] = RTL_R8(tp, MAC0 + i);
8284
8285         dev->ethtool_ops = &rtl8169_ethtool_ops;
8286         dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
8287
8288         netif_napi_add(dev, &tp->napi, rtl8169_poll, NAPI_POLL_WEIGHT);
8289
8290         /* don't enable SG, IP_CSUM and TSO by default - it might not work
8291          * properly for all devices */
8292         dev->features |= NETIF_F_RXCSUM |
8293                 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
8294
8295         dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
8296                 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_TX |
8297                 NETIF_F_HW_VLAN_CTAG_RX;
8298         dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
8299                 NETIF_F_HIGHDMA;
8300
8301         tp->cp_cmd |= RxChkSum | RxVlan;
8302
8303         /*
8304          * Pretend we are using VLANs; This bypasses a nasty bug where
8305          * Interrupts stop flowing on high load on 8110SCd controllers.
8306          */
8307         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
8308                 /* Disallow toggling */
8309                 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX;
8310
8311         if (tp->txd_version == RTL_TD_0)
8312                 tp->tso_csum = rtl8169_tso_csum_v1;
8313         else if (tp->txd_version == RTL_TD_1) {
8314                 tp->tso_csum = rtl8169_tso_csum_v2;
8315                 dev->hw_features |= NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
8316         } else
8317                 WARN_ON_ONCE(1);
8318
8319         dev->hw_features |= NETIF_F_RXALL;
8320         dev->hw_features |= NETIF_F_RXFCS;
8321
8322         /* MTU range: 60 - hw-specific max */
8323         dev->min_mtu = ETH_ZLEN;
8324         dev->max_mtu = rtl_chip_infos[chipset].jumbo_max;
8325
8326         tp->hw_start = cfg->hw_start;
8327         tp->event_slow = cfg->event_slow;
8328         tp->coalesce_info = cfg->coalesce_info;
8329
8330         tp->opts1_mask = (tp->mac_version != RTL_GIGA_MAC_VER_01) ?
8331                 ~(RxBOVF | RxFOVF) : ~0;
8332
8333         timer_setup(&tp->timer, rtl8169_phy_timer, 0);
8334
8335         tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
8336
8337         tp->counters = dmam_alloc_coherent (&pdev->dev, sizeof(*tp->counters),
8338                                             &tp->counters_phys_addr,
8339                                             GFP_KERNEL);
8340         if (!tp->counters)
8341                 return -ENOMEM;
8342
8343         pci_set_drvdata(pdev, dev);
8344
8345         rc = register_netdev(dev);
8346         if (rc < 0)
8347                 return rc;
8348
8349         netif_info(tp, probe, dev, "%s at 0x%p, %pM, XID %08x IRQ %d\n",
8350                    rtl_chip_infos[chipset].name, tp->mmio_addr, dev->dev_addr,
8351                    (u32)(RTL_R32(tp, TxConfig) & 0x9cf0f8ff),
8352                    pci_irq_vector(pdev, 0));
8353         if (rtl_chip_infos[chipset].jumbo_max != JUMBO_1K) {
8354                 netif_info(tp, probe, dev, "jumbo features [frames: %d bytes, "
8355                            "tx checksumming: %s]\n",
8356                            rtl_chip_infos[chipset].jumbo_max,
8357                            rtl_chip_infos[chipset].jumbo_tx_csum ? "ok" : "ko");
8358         }
8359
8360         if (r8168_check_dash(tp))
8361                 rtl8168_driver_start(tp);
8362
8363         netif_carrier_off(dev);
8364
8365         if (pci_dev_run_wake(pdev))
8366                 pm_runtime_put_sync(&pdev->dev);
8367
8368         return 0;
8369 }
8370
8371 static struct pci_driver rtl8169_pci_driver = {
8372         .name           = MODULENAME,
8373         .id_table       = rtl8169_pci_tbl,
8374         .probe          = rtl_init_one,
8375         .remove         = rtl_remove_one,
8376         .shutdown       = rtl_shutdown,
8377         .driver.pm      = RTL8169_PM_OPS,
8378 };
8379
8380 module_pci_driver(rtl8169_pci_driver);