drivers/net/ethernet/realtek/r8169.c

   1 /*
   2  * r8169.c: RealTek 8169/8168/8101 ethernet driver.
   3  *
   4  * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
   5  * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
   6  * Copyright (c) a lot of people too. Please respect their work.
   7  *
   8  * See MAINTAINERS file for support contact information.
   9  */
  10
  11 #include <linux/module.h>
  12 #include <linux/moduleparam.h>
  13 #include <linux/pci.h>
  14 #include <linux/netdevice.h>
  15 #include <linux/etherdevice.h>
  16 #include <linux/clk.h>
  17 #include <linux/delay.h>
  18 #include <linux/ethtool.h>
  19 #include <linux/phy.h>
  20 #include <linux/if_vlan.h>
  21 #include <linux/crc32.h>
  22 #include <linux/in.h>
  23 #include <linux/io.h>
  24 #include <linux/ip.h>
  25 #include <linux/tcp.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/dma-mapping.h>
  28 #include <linux/pm_runtime.h>
  29 #include <linux/firmware.h>
  30 #include <linux/prefetch.h>
  31 #include <linux/ipv6.h>
  32 #include <net/ip6_checksum.h>
  33
  34 #define MODULENAME "r8169"
  35
  36 #define FIRMWARE_8168D_1        "rtl_nic/rtl8168d-1.fw"
  37 #define FIRMWARE_8168D_2        "rtl_nic/rtl8168d-2.fw"
  38 #define FIRMWARE_8168E_1        "rtl_nic/rtl8168e-1.fw"
  39 #define FIRMWARE_8168E_2        "rtl_nic/rtl8168e-2.fw"
  40 #define FIRMWARE_8168E_3        "rtl_nic/rtl8168e-3.fw"
  41 #define FIRMWARE_8168F_1        "rtl_nic/rtl8168f-1.fw"
  42 #define FIRMWARE_8168F_2        "rtl_nic/rtl8168f-2.fw"
  43 #define FIRMWARE_8105E_1        "rtl_nic/rtl8105e-1.fw"
  44 #define FIRMWARE_8402_1         "rtl_nic/rtl8402-1.fw"
  45 #define FIRMWARE_8411_1         "rtl_nic/rtl8411-1.fw"
  46 #define FIRMWARE_8411_2         "rtl_nic/rtl8411-2.fw"
  47 #define FIRMWARE_8106E_1        "rtl_nic/rtl8106e-1.fw"
  48 #define FIRMWARE_8106E_2        "rtl_nic/rtl8106e-2.fw"
  49 #define FIRMWARE_8168G_2        "rtl_nic/rtl8168g-2.fw"
  50 #define FIRMWARE_8168G_3        "rtl_nic/rtl8168g-3.fw"
  51 #define FIRMWARE_8168H_1        "rtl_nic/rtl8168h-1.fw"
  52 #define FIRMWARE_8168H_2        "rtl_nic/rtl8168h-2.fw"
  53 #define FIRMWARE_8107E_1        "rtl_nic/rtl8107e-1.fw"
  54 #define FIRMWARE_8107E_2        "rtl_nic/rtl8107e-2.fw"
  55
  56 #define R8169_MSG_DEFAULT \
  57         (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
  58
  59 #define TX_SLOTS_AVAIL(tp) \
  60         (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx)
  61
  62 /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
  63 #define TX_FRAGS_READY_FOR(tp,nr_frags) \
  64         (TX_SLOTS_AVAIL(tp) >= (nr_frags + 1))
  65
  66 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
  67    The RTL chips use a 64 element hash table based on the Ethernet CRC. */
  68 static const int multicast_filter_limit = 32;
  69
  70 #define TX_DMA_BURST    7       /* Maximum PCI burst, '7' is unlimited */
  71 #define InterFrameGap   0x03    /* 3 means InterFrameGap = the shortest one */
  72
  73 #define R8169_REGS_SIZE         256
  74 #define R8169_RX_BUF_SIZE       (SZ_16K - 1)
  75 #define NUM_TX_DESC     64      /* Number of Tx descriptor registers */
  76 #define NUM_RX_DESC     256U    /* Number of Rx descriptor registers */
  77 #define R8169_TX_RING_BYTES     (NUM_TX_DESC * sizeof(struct TxDesc))
  78 #define R8169_RX_RING_BYTES     (NUM_RX_DESC * sizeof(struct RxDesc))
  79
  80 /* write/read MMIO register */
  81 #define RTL_W8(tp, reg, val8)   writeb((val8), tp->mmio_addr + (reg))
  82 #define RTL_W16(tp, reg, val16) writew((val16), tp->mmio_addr + (reg))
  83 #define RTL_W32(tp, reg, val32) writel((val32), tp->mmio_addr + (reg))
  84 #define RTL_R8(tp, reg)         readb(tp->mmio_addr + (reg))
  85 #define RTL_R16(tp, reg)                readw(tp->mmio_addr + (reg))
  86 #define RTL_R32(tp, reg)                readl(tp->mmio_addr + (reg))
  87
  88 enum mac_version {
  89         RTL_GIGA_MAC_VER_01 = 0,
  90         RTL_GIGA_MAC_VER_02,
  91         RTL_GIGA_MAC_VER_03,
  92         RTL_GIGA_MAC_VER_04,
  93         RTL_GIGA_MAC_VER_05,
  94         RTL_GIGA_MAC_VER_06,
  95         RTL_GIGA_MAC_VER_07,
  96         RTL_GIGA_MAC_VER_08,
  97         RTL_GIGA_MAC_VER_09,
  98         RTL_GIGA_MAC_VER_10,
  99         RTL_GIGA_MAC_VER_11,
 100         RTL_GIGA_MAC_VER_12,
 101         RTL_GIGA_MAC_VER_13,
 102         RTL_GIGA_MAC_VER_14,
 103         RTL_GIGA_MAC_VER_15,
 104         RTL_GIGA_MAC_VER_16,
 105         RTL_GIGA_MAC_VER_17,
 106         RTL_GIGA_MAC_VER_18,
 107         RTL_GIGA_MAC_VER_19,
 108         RTL_GIGA_MAC_VER_20,
 109         RTL_GIGA_MAC_VER_21,
 110         RTL_GIGA_MAC_VER_22,
 111         RTL_GIGA_MAC_VER_23,
 112         RTL_GIGA_MAC_VER_24,
 113         RTL_GIGA_MAC_VER_25,
 114         RTL_GIGA_MAC_VER_26,
 115         RTL_GIGA_MAC_VER_27,
 116         RTL_GIGA_MAC_VER_28,
 117         RTL_GIGA_MAC_VER_29,
 118         RTL_GIGA_MAC_VER_30,
 119         RTL_GIGA_MAC_VER_31,
 120         RTL_GIGA_MAC_VER_32,
 121         RTL_GIGA_MAC_VER_33,
 122         RTL_GIGA_MAC_VER_34,
 123         RTL_GIGA_MAC_VER_35,
 124         RTL_GIGA_MAC_VER_36,
 125         RTL_GIGA_MAC_VER_37,
 126         RTL_GIGA_MAC_VER_38,
 127         RTL_GIGA_MAC_VER_39,
 128         RTL_GIGA_MAC_VER_40,
 129         RTL_GIGA_MAC_VER_41,
 130         RTL_GIGA_MAC_VER_42,
 131         RTL_GIGA_MAC_VER_43,
 132         RTL_GIGA_MAC_VER_44,
 133         RTL_GIGA_MAC_VER_45,
 134         RTL_GIGA_MAC_VER_46,
 135         RTL_GIGA_MAC_VER_47,
 136         RTL_GIGA_MAC_VER_48,
 137         RTL_GIGA_MAC_VER_49,
 138         RTL_GIGA_MAC_VER_50,
 139         RTL_GIGA_MAC_VER_51,
 140         RTL_GIGA_MAC_NONE   = 0xff,
 141 };
 142
 143 #define JUMBO_1K        ETH_DATA_LEN
 144 #define JUMBO_4K        (4*1024 - ETH_HLEN - 2)
 145 #define JUMBO_6K        (6*1024 - ETH_HLEN - 2)
 146 #define JUMBO_7K        (7*1024 - ETH_HLEN - 2)
 147 #define JUMBO_9K        (9*1024 - ETH_HLEN - 2)
 148
 149 static const struct {
 150         const char *name;
 151         const char *fw_name;
 152 } rtl_chip_infos[] = {
 153         /* PCI devices. */
 154         [RTL_GIGA_MAC_VER_01] = {"RTL8169"                              },
 155         [RTL_GIGA_MAC_VER_02] = {"RTL8169s"                             },
 156         [RTL_GIGA_MAC_VER_03] = {"RTL8110s"                             },
 157         [RTL_GIGA_MAC_VER_04] = {"RTL8169sb/8110sb"                     },
 158         [RTL_GIGA_MAC_VER_05] = {"RTL8169sc/8110sc"                     },
 159         [RTL_GIGA_MAC_VER_06] = {"RTL8169sc/8110sc"                     },
 160         /* PCI-E devices. */
 161         [RTL_GIGA_MAC_VER_07] = {"RTL8102e"                             },
 162         [RTL_GIGA_MAC_VER_08] = {"RTL8102e"                             },
 163         [RTL_GIGA_MAC_VER_09] = {"RTL8102e"                             },
 164         [RTL_GIGA_MAC_VER_10] = {"RTL8101e"                             },
 165         [RTL_GIGA_MAC_VER_11] = {"RTL8168b/8111b"                       },
 166         [RTL_GIGA_MAC_VER_12] = {"RTL8168b/8111b"                       },
 167         [RTL_GIGA_MAC_VER_13] = {"RTL8101e"                             },
 168         [RTL_GIGA_MAC_VER_14] = {"RTL8100e"                             },
 169         [RTL_GIGA_MAC_VER_15] = {"RTL8100e"                             },
 170         [RTL_GIGA_MAC_VER_16] = {"RTL8101e"                             },
 171         [RTL_GIGA_MAC_VER_17] = {"RTL8168b/8111b"                       },
 172         [RTL_GIGA_MAC_VER_18] = {"RTL8168cp/8111cp"                     },
 173         [RTL_GIGA_MAC_VER_19] = {"RTL8168c/8111c"                       },
 174         [RTL_GIGA_MAC_VER_20] = {"RTL8168c/8111c"                       },
 175         [RTL_GIGA_MAC_VER_21] = {"RTL8168c/8111c"                       },
 176         [RTL_GIGA_MAC_VER_22] = {"RTL8168c/8111c"                       },
 177         [RTL_GIGA_MAC_VER_23] = {"RTL8168cp/8111cp"                     },
 178         [RTL_GIGA_MAC_VER_24] = {"RTL8168cp/8111cp"                     },
 179         [RTL_GIGA_MAC_VER_25] = {"RTL8168d/8111d",      FIRMWARE_8168D_1},
 180         [RTL_GIGA_MAC_VER_26] = {"RTL8168d/8111d",      FIRMWARE_8168D_2},
 181         [RTL_GIGA_MAC_VER_27] = {"RTL8168dp/8111dp"                     },
 182         [RTL_GIGA_MAC_VER_28] = {"RTL8168dp/8111dp"                     },
 183         [RTL_GIGA_MAC_VER_29] = {"RTL8105e",            FIRMWARE_8105E_1},
 184         [RTL_GIGA_MAC_VER_30] = {"RTL8105e",            FIRMWARE_8105E_1},
 185         [RTL_GIGA_MAC_VER_31] = {"RTL8168dp/8111dp"                     },
 186         [RTL_GIGA_MAC_VER_32] = {"RTL8168e/8111e",      FIRMWARE_8168E_1},
 187         [RTL_GIGA_MAC_VER_33] = {"RTL8168e/8111e",      FIRMWARE_8168E_2},
 188         [RTL_GIGA_MAC_VER_34] = {"RTL8168evl/8111evl",  FIRMWARE_8168E_3},
 189         [RTL_GIGA_MAC_VER_35] = {"RTL8168f/8111f",      FIRMWARE_8168F_1},
 190         [RTL_GIGA_MAC_VER_36] = {"RTL8168f/8111f",      FIRMWARE_8168F_2},
 191         [RTL_GIGA_MAC_VER_37] = {"RTL8402",             FIRMWARE_8402_1 },
 192         [RTL_GIGA_MAC_VER_38] = {"RTL8411",             FIRMWARE_8411_1 },
 193         [RTL_GIGA_MAC_VER_39] = {"RTL8106e",            FIRMWARE_8106E_1},
 194         [RTL_GIGA_MAC_VER_40] = {"RTL8168g/8111g",      FIRMWARE_8168G_2},
 195         [RTL_GIGA_MAC_VER_41] = {"RTL8168g/8111g"                       },
 196         [RTL_GIGA_MAC_VER_42] = {"RTL8168g/8111g",      FIRMWARE_8168G_3},
 197         [RTL_GIGA_MAC_VER_43] = {"RTL8106e",            FIRMWARE_8106E_2},
 198         [RTL_GIGA_MAC_VER_44] = {"RTL8411",             FIRMWARE_8411_2 },
 199         [RTL_GIGA_MAC_VER_45] = {"RTL8168h/8111h",      FIRMWARE_8168H_1},
 200         [RTL_GIGA_MAC_VER_46] = {"RTL8168h/8111h",      FIRMWARE_8168H_2},
 201         [RTL_GIGA_MAC_VER_47] = {"RTL8107e",            FIRMWARE_8107E_1},
 202         [RTL_GIGA_MAC_VER_48] = {"RTL8107e",            FIRMWARE_8107E_2},
 203         [RTL_GIGA_MAC_VER_49] = {"RTL8168ep/8111ep"                     },
 204         [RTL_GIGA_MAC_VER_50] = {"RTL8168ep/8111ep"                     },
 205         [RTL_GIGA_MAC_VER_51] = {"RTL8168ep/8111ep"                     },
 206 };
 207
 208 enum cfg_version {
 209         RTL_CFG_0 = 0x00,
 210         RTL_CFG_1,
 211         RTL_CFG_2
 212 };
 213
 214 static const struct pci_device_id rtl8169_pci_tbl[] = {
 215         { PCI_VDEVICE(REALTEK,  0x8129), RTL_CFG_0 },
 216         { PCI_VDEVICE(REALTEK,  0x8136), RTL_CFG_2 },
 217         { PCI_VDEVICE(REALTEK,  0x8161), RTL_CFG_1 },
 218         { PCI_VDEVICE(REALTEK,  0x8167), RTL_CFG_0 },
 219         { PCI_VDEVICE(REALTEK,  0x8168), RTL_CFG_1 },
 220         { PCI_VDEVICE(NCUBE,    0x8168), RTL_CFG_1 },
 221         { PCI_VDEVICE(REALTEK,  0x8169), RTL_CFG_0 },
 222         { PCI_VENDOR_ID_DLINK,  0x4300,
 223                 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0, RTL_CFG_1 },
 224         { PCI_VDEVICE(DLINK,    0x4300), RTL_CFG_0 },
 225         { PCI_VDEVICE(DLINK,    0x4302), RTL_CFG_0 },
 226         { PCI_VDEVICE(AT,       0xc107), RTL_CFG_0 },
 227         { PCI_VDEVICE(USR,      0x0116), RTL_CFG_0 },
 228         { PCI_VENDOR_ID_LINKSYS,                0x1032,
 229                 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
 230         { 0x0001,                               0x8168,
 231                 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
 232         {}
 233 };
 234
 235 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
 236
 237 static int use_dac = -1;
 238 static struct {
 239         u32 msg_enable;
 240 } debug = { -1 };
 241
 242 enum rtl_registers {
 243         MAC0            = 0,    /* Ethernet hardware address. */
 244         MAC4            = 4,
 245         MAR0            = 8,    /* Multicast filter. */
 246         CounterAddrLow          = 0x10,
 247         CounterAddrHigh         = 0x14,
 248         TxDescStartAddrLow      = 0x20,
 249         TxDescStartAddrHigh     = 0x24,
 250         TxHDescStartAddrLow     = 0x28,
 251         TxHDescStartAddrHigh    = 0x2c,
 252         FLASH           = 0x30,
 253         ERSR            = 0x36,
 254         ChipCmd         = 0x37,
 255         TxPoll          = 0x38,
 256         IntrMask        = 0x3c,
 257         IntrStatus      = 0x3e,
 258
 259         TxConfig        = 0x40,
 260 #define TXCFG_AUTO_FIFO                 (1 << 7)        /* 8111e-vl */
 261 #define TXCFG_EMPTY                     (1 << 11)       /* 8111e-vl */
 262
 263         RxConfig        = 0x44,
 264 #define RX128_INT_EN                    (1 << 15)       /* 8111c and later */
 265 #define RX_MULTI_EN                     (1 << 14)       /* 8111c only */
 266 #define RXCFG_FIFO_SHIFT                13
 267                                         /* No threshold before first PCI xfer */
 268 #define RX_FIFO_THRESH                  (7 << RXCFG_FIFO_SHIFT)
 269 #define RX_EARLY_OFF                    (1 << 11)
 270 #define RXCFG_DMA_SHIFT                 8
 271                                         /* Unlimited maximum PCI burst. */
 272 #define RX_DMA_BURST                    (7 << RXCFG_DMA_SHIFT)
 273
 274         RxMissed        = 0x4c,
 275         Cfg9346         = 0x50,
 276         Config0         = 0x51,
 277         Config1         = 0x52,
 278         Config2         = 0x53,
 279 #define PME_SIGNAL                      (1 << 5)        /* 8168c and later */
 280
 281         Config3         = 0x54,
 282         Config4         = 0x55,
 283         Config5         = 0x56,
 284         MultiIntr       = 0x5c,
 285         PHYAR           = 0x60,
 286         PHYstatus       = 0x6c,
 287         RxMaxSize       = 0xda,
 288         CPlusCmd        = 0xe0,
 289         IntrMitigate    = 0xe2,
 290
 291 #define RTL_COALESCE_MASK       0x0f
 292 #define RTL_COALESCE_SHIFT      4
 293 #define RTL_COALESCE_T_MAX      (RTL_COALESCE_MASK)
 294 #define RTL_COALESCE_FRAME_MAX  (RTL_COALESCE_MASK << 2)
 295
 296         RxDescAddrLow   = 0xe4,
 297         RxDescAddrHigh  = 0xe8,
 298         EarlyTxThres    = 0xec, /* 8169. Unit of 32 bytes. */
 299
 300 #define NoEarlyTx       0x3f    /* Max value : no early transmit. */
 301
 302         MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
 303
 304 #define TxPacketMax     (8064 >> 7)
 305 #define EarlySize       0x27
 306
 307         FuncEvent       = 0xf0,
 308         FuncEventMask   = 0xf4,
 309         FuncPresetState = 0xf8,
 310         IBCR0           = 0xf8,
 311         IBCR2           = 0xf9,
 312         IBIMR0          = 0xfa,
 313         IBISR0          = 0xfb,
 314         FuncForceEvent  = 0xfc,
 315 };
 316
 317 enum rtl8168_8101_registers {
 318         CSIDR                   = 0x64,
 319         CSIAR                   = 0x68,
 320 #define CSIAR_FLAG                      0x80000000
 321 #define CSIAR_WRITE_CMD                 0x80000000
 322 #define CSIAR_BYTE_ENABLE               0x0000f000
 323 #define CSIAR_ADDR_MASK                 0x00000fff
 324         PMCH                    = 0x6f,
 325         EPHYAR                  = 0x80,
 326 #define EPHYAR_FLAG                     0x80000000
 327 #define EPHYAR_WRITE_CMD                0x80000000
 328 #define EPHYAR_REG_MASK                 0x1f
 329 #define EPHYAR_REG_SHIFT                16
 330 #define EPHYAR_DATA_MASK                0xffff
 331         DLLPR                   = 0xd0,
 332 #define PFM_EN                          (1 << 6)
 333 #define TX_10M_PS_EN                    (1 << 7)
 334         DBG_REG                 = 0xd1,
 335 #define FIX_NAK_1                       (1 << 4)
 336 #define FIX_NAK_2                       (1 << 3)
 337         TWSI                    = 0xd2,
 338         MCU                     = 0xd3,
 339 #define NOW_IS_OOB                      (1 << 7)
 340 #define TX_EMPTY                        (1 << 5)
 341 #define RX_EMPTY                        (1 << 4)
 342 #define RXTX_EMPTY                      (TX_EMPTY | RX_EMPTY)
 343 #define EN_NDP                          (1 << 3)
 344 #define EN_OOB_RESET                    (1 << 2)
 345 #define LINK_LIST_RDY                   (1 << 1)
 346         EFUSEAR                 = 0xdc,
 347 #define EFUSEAR_FLAG                    0x80000000
 348 #define EFUSEAR_WRITE_CMD               0x80000000
 349 #define EFUSEAR_READ_CMD                0x00000000
 350 #define EFUSEAR_REG_MASK                0x03ff
 351 #define EFUSEAR_REG_SHIFT               8
 352 #define EFUSEAR_DATA_MASK               0xff
 353         MISC_1                  = 0xf2,
 354 #define PFM_D3COLD_EN                   (1 << 6)
 355 };
 356
 357 enum rtl8168_registers {
 358         LED_FREQ                = 0x1a,
 359         EEE_LED                 = 0x1b,
 360         ERIDR                   = 0x70,
 361         ERIAR                   = 0x74,
 362 #define ERIAR_FLAG                      0x80000000
 363 #define ERIAR_WRITE_CMD                 0x80000000
 364 #define ERIAR_READ_CMD                  0x00000000
 365 #define ERIAR_ADDR_BYTE_ALIGN           4
 366 #define ERIAR_TYPE_SHIFT                16
 367 #define ERIAR_EXGMAC                    (0x00 << ERIAR_TYPE_SHIFT)
 368 #define ERIAR_MSIX                      (0x01 << ERIAR_TYPE_SHIFT)
 369 #define ERIAR_ASF                       (0x02 << ERIAR_TYPE_SHIFT)
 370 #define ERIAR_OOB                       (0x02 << ERIAR_TYPE_SHIFT)
 371 #define ERIAR_MASK_SHIFT                12
 372 #define ERIAR_MASK_0001                 (0x1 << ERIAR_MASK_SHIFT)
 373 #define ERIAR_MASK_0011                 (0x3 << ERIAR_MASK_SHIFT)
 374 #define ERIAR_MASK_0100                 (0x4 << ERIAR_MASK_SHIFT)
 375 #define ERIAR_MASK_0101                 (0x5 << ERIAR_MASK_SHIFT)
 376 #define ERIAR_MASK_1111                 (0xf << ERIAR_MASK_SHIFT)
 377         EPHY_RXER_NUM           = 0x7c,
 378         OCPDR                   = 0xb0, /* OCP GPHY access */
 379 #define OCPDR_WRITE_CMD                 0x80000000
 380 #define OCPDR_READ_CMD                  0x00000000
 381 #define OCPDR_REG_MASK                  0x7f
 382 #define OCPDR_GPHY_REG_SHIFT            16
 383 #define OCPDR_DATA_MASK                 0xffff
 384         OCPAR                   = 0xb4,
 385 #define OCPAR_FLAG                      0x80000000
 386 #define OCPAR_GPHY_WRITE_CMD            0x8000f060
 387 #define OCPAR_GPHY_READ_CMD             0x0000f060
 388         GPHY_OCP                = 0xb8,
 389         RDSAR1                  = 0xd0, /* 8168c only. Undocumented on 8168dp */
 390         MISC                    = 0xf0, /* 8168e only. */
 391 #define TXPLA_RST                       (1 << 29)
 392 #define DISABLE_LAN_EN                  (1 << 23) /* Enable GPIO pin */
 393 #define PWM_EN                          (1 << 22)
 394 #define RXDV_GATED_EN                   (1 << 19)
 395 #define EARLY_TALLY_EN                  (1 << 16)
 396 };
 397
 398 enum rtl_register_content {
 399         /* InterruptStatusBits */
 400         SYSErr          = 0x8000,
 401         PCSTimeout      = 0x4000,
 402         SWInt           = 0x0100,
 403         TxDescUnavail   = 0x0080,
 404         RxFIFOOver      = 0x0040,
 405         LinkChg         = 0x0020,
 406         RxOverflow      = 0x0010,
 407         TxErr           = 0x0008,
 408         TxOK            = 0x0004,
 409         RxErr           = 0x0002,
 410         RxOK            = 0x0001,
 411
 412         /* RxStatusDesc */
 413         RxBOVF  = (1 << 24),
 414         RxFOVF  = (1 << 23),
 415         RxRWT   = (1 << 22),
 416         RxRES   = (1 << 21),
 417         RxRUNT  = (1 << 20),
 418         RxCRC   = (1 << 19),
 419
 420         /* ChipCmdBits */
 421         StopReq         = 0x80,
 422         CmdReset        = 0x10,
 423         CmdRxEnb        = 0x08,
 424         CmdTxEnb        = 0x04,
 425         RxBufEmpty      = 0x01,
 426
 427         /* TXPoll register p.5 */
 428         HPQ             = 0x80,         /* Poll cmd on the high prio queue */
 429         NPQ             = 0x40,         /* Poll cmd on the low prio queue */
 430         FSWInt          = 0x01,         /* Forced software interrupt */
 431
 432         /* Cfg9346Bits */
 433         Cfg9346_Lock    = 0x00,
 434         Cfg9346_Unlock  = 0xc0,
 435
 436         /* rx_mode_bits */
 437         AcceptErr       = 0x20,
 438         AcceptRunt      = 0x10,
 439         AcceptBroadcast = 0x08,
 440         AcceptMulticast = 0x04,
 441         AcceptMyPhys    = 0x02,
 442         AcceptAllPhys   = 0x01,
 443 #define RX_CONFIG_ACCEPT_MASK           0x3f
 444
 445         /* TxConfigBits */
 446         TxInterFrameGapShift = 24,
 447         TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
 448
 449         /* Config1 register p.24 */
 450         LEDS1           = (1 << 7),
 451         LEDS0           = (1 << 6),
 452         Speed_down      = (1 << 4),
 453         MEMMAP          = (1 << 3),
 454         IOMAP           = (1 << 2),
 455         VPD             = (1 << 1),
 456         PMEnable        = (1 << 0),     /* Power Management Enable */
 457
 458         /* Config2 register p. 25 */
 459         ClkReqEn        = (1 << 7),     /* Clock Request Enable */
 460         MSIEnable       = (1 << 5),     /* 8169 only. Reserved in the 8168. */
 461         PCI_Clock_66MHz = 0x01,
 462         PCI_Clock_33MHz = 0x00,
 463
 464         /* Config3 register p.25 */
 465         MagicPacket     = (1 << 5),     /* Wake up when receives a Magic Packet */
 466         LinkUp          = (1 << 4),     /* Wake up when the cable connection is re-established */
 467         Jumbo_En0       = (1 << 2),     /* 8168 only. Reserved in the 8168b */
 468         Rdy_to_L23      = (1 << 1),     /* L23 Enable */
 469         Beacon_en       = (1 << 0),     /* 8168 only. Reserved in the 8168b */
 470
 471         /* Config4 register */
 472         Jumbo_En1       = (1 << 1),     /* 8168 only. Reserved in the 8168b */
 473
 474         /* Config5 register p.27 */
 475         BWF             = (1 << 6),     /* Accept Broadcast wakeup frame */
 476         MWF             = (1 << 5),     /* Accept Multicast wakeup frame */
 477         UWF             = (1 << 4),     /* Accept Unicast wakeup frame */
 478         Spi_en          = (1 << 3),
 479         LanWake         = (1 << 1),     /* LanWake enable/disable */
 480         PMEStatus       = (1 << 0),     /* PME status can be reset by PCI RST# */
 481         ASPM_en         = (1 << 0),     /* ASPM enable */
 482
 483         /* CPlusCmd p.31 */
 484         EnableBist      = (1 << 15),    // 8168 8101
 485         Mac_dbgo_oe     = (1 << 14),    // 8168 8101
 486         Normal_mode     = (1 << 13),    // unused
 487         Force_half_dup  = (1 << 12),    // 8168 8101
 488         Force_rxflow_en = (1 << 11),    // 8168 8101
 489         Force_txflow_en = (1 << 10),    // 8168 8101
 490         Cxpl_dbg_sel    = (1 << 9),     // 8168 8101
 491         ASF             = (1 << 8),     // 8168 8101
 492         PktCntrDisable  = (1 << 7),     // 8168 8101
 493         Mac_dbgo_sel    = 0x001c,       // 8168
 494         RxVlan          = (1 << 6),
 495         RxChkSum        = (1 << 5),
 496         PCIDAC          = (1 << 4),
 497         PCIMulRW        = (1 << 3),
 498 #define INTT_MASK       GENMASK(1, 0)
 499         INTT_0          = 0x0000,       // 8168
 500         INTT_1          = 0x0001,       // 8168
 501         INTT_2          = 0x0002,       // 8168
 502         INTT_3          = 0x0003,       // 8168
 503
 504         /* rtl8169_PHYstatus */
 505         TBI_Enable      = 0x80,
 506         TxFlowCtrl      = 0x40,
 507         RxFlowCtrl      = 0x20,
 508         _1000bpsF       = 0x10,
 509         _100bps         = 0x08,
 510         _10bps          = 0x04,
 511         LinkStatus      = 0x02,
 512         FullDup         = 0x01,
 513
 514         /* _TBICSRBit */
 515         TBILinkOK       = 0x02000000,
 516
 517         /* ResetCounterCommand */
 518         CounterReset    = 0x1,
 519
 520         /* DumpCounterCommand */
 521         CounterDump     = 0x8,
 522
 523         /* magic enable v2 */
 524         MagicPacket_v2  = (1 << 16),    /* Wake up when receives a Magic Packet */
 525 };
 526
 527 enum rtl_desc_bit {
 528         /* First doubleword. */
 529         DescOwn         = (1 << 31), /* Descriptor is owned by NIC */
 530         RingEnd         = (1 << 30), /* End of descriptor ring */
 531         FirstFrag       = (1 << 29), /* First segment of a packet */
 532         LastFrag        = (1 << 28), /* Final segment of a packet */
 533 };
 534
 535 /* Generic case. */
 536 enum rtl_tx_desc_bit {
 537         /* First doubleword. */
 538         TD_LSO          = (1 << 27),            /* Large Send Offload */
 539 #define TD_MSS_MAX                      0x07ffu /* MSS value */
 540
 541         /* Second doubleword. */
 542         TxVlanTag       = (1 << 17),            /* Add VLAN tag */
 543 };
 544
 545 /* 8169, 8168b and 810x except 8102e. */
 546 enum rtl_tx_desc_bit_0 {
 547         /* First doubleword. */
 548 #define TD0_MSS_SHIFT                   16      /* MSS position (11 bits) */
 549         TD0_TCP_CS      = (1 << 16),            /* Calculate TCP/IP checksum */
 550         TD0_UDP_CS      = (1 << 17),            /* Calculate UDP/IP checksum */
 551         TD0_IP_CS       = (1 << 18),            /* Calculate IP checksum */
 552 };
 553
 554 /* 8102e, 8168c and beyond. */
 555 enum rtl_tx_desc_bit_1 {
 556         /* First doubleword. */
 557         TD1_GTSENV4     = (1 << 26),            /* Giant Send for IPv4 */
 558         TD1_GTSENV6     = (1 << 25),            /* Giant Send for IPv6 */
 559 #define GTTCPHO_SHIFT                   18
 560 #define GTTCPHO_MAX                     0x7fU
 561
 562         /* Second doubleword. */
 563 #define TCPHO_SHIFT                     18
 564 #define TCPHO_MAX                       0x3ffU
 565 #define TD1_MSS_SHIFT                   18      /* MSS position (11 bits) */
 566         TD1_IPv6_CS     = (1 << 28),            /* Calculate IPv6 checksum */
 567         TD1_IPv4_CS     = (1 << 29),            /* Calculate IPv4 checksum */
 568         TD1_TCP_CS      = (1 << 30),            /* Calculate TCP/IP checksum */
 569         TD1_UDP_CS      = (1 << 31),            /* Calculate UDP/IP checksum */
 570 };
 571
 572 enum rtl_rx_desc_bit {
 573         /* Rx private */
 574         PID1            = (1 << 18), /* Protocol ID bit 1/2 */
 575         PID0            = (1 << 17), /* Protocol ID bit 0/2 */
 576
 577 #define RxProtoUDP      (PID1)
 578 #define RxProtoTCP      (PID0)
 579 #define RxProtoIP       (PID1 | PID0)
 580 #define RxProtoMask     RxProtoIP
 581
 582         IPFail          = (1 << 16), /* IP checksum failed */
 583         UDPFail         = (1 << 15), /* UDP/IP checksum failed */
 584         TCPFail         = (1 << 14), /* TCP/IP checksum failed */
 585         RxVlanTag       = (1 << 16), /* VLAN tag available */
 586 };
 587
 588 #define RsvdMask        0x3fffc000
 589 #define CPCMD_QUIRK_MASK        (Normal_mode | RxVlan | RxChkSum | INTT_MASK)
 590
 591 struct TxDesc {
 592         __le32 opts1;
 593         __le32 opts2;
 594         __le64 addr;
 595 };
 596
 597 struct RxDesc {
 598         __le32 opts1;
 599         __le32 opts2;
 600         __le64 addr;
 601 };
 602
 603 struct ring_info {
 604         struct sk_buff  *skb;
 605         u32             len;
 606         u8              __pad[sizeof(void *) - sizeof(u32)];
 607 };
 608
 609 struct rtl8169_counters {
 610         __le64  tx_packets;
 611         __le64  rx_packets;
 612         __le64  tx_errors;
 613         __le32  rx_errors;
 614         __le16  rx_missed;
 615         __le16  align_errors;
 616         __le32  tx_one_collision;
 617         __le32  tx_multi_collision;
 618         __le64  rx_unicast;
 619         __le64  rx_broadcast;
 620         __le32  rx_multicast;
 621         __le16  tx_aborted;
 622         __le16  tx_underun;
 623 };
 624
 625 struct rtl8169_tc_offsets {
 626         bool    inited;
 627         __le64  tx_errors;
 628         __le32  tx_multi_collision;
 629         __le16  tx_aborted;
 630 };
 631
 632 enum rtl_flag {
 633         RTL_FLAG_TASK_ENABLED = 0,
 634         RTL_FLAG_TASK_RESET_PENDING,
 635         RTL_FLAG_MAX
 636 };
 637
 638 struct rtl8169_stats {
 639         u64                     packets;
 640         u64                     bytes;
 641         struct u64_stats_sync   syncp;
 642 };
 643
 644 struct rtl8169_private {
 645         void __iomem *mmio_addr;        /* memory map physical address */
 646         struct pci_dev *pci_dev;
 647         struct net_device *dev;
 648         struct napi_struct napi;
 649         u32 msg_enable;
 650         u16 mac_version;
 651         u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
 652         u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
 653         u32 dirty_tx;
 654         struct rtl8169_stats rx_stats;
 655         struct rtl8169_stats tx_stats;
 656         struct TxDesc *TxDescArray;     /* 256-aligned Tx descriptor ring */
 657         struct RxDesc *RxDescArray;     /* 256-aligned Rx descriptor ring */
 658         dma_addr_t TxPhyAddr;
 659         dma_addr_t RxPhyAddr;
 660         void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
 661         struct ring_info tx_skb[NUM_TX_DESC];   /* Tx data buffers */
 662         u16 cp_cmd;
 663
 664         u16 irq_mask;
 665         const struct rtl_coalesce_info *coalesce_info;
 666         struct clk *clk;
 667
 668         struct mdio_ops {
 669                 void (*write)(struct rtl8169_private *, int, int);
 670                 int (*read)(struct rtl8169_private *, int);
 671         } mdio_ops;
 672
 673         struct jumbo_ops {
 674                 void (*enable)(struct rtl8169_private *);
 675                 void (*disable)(struct rtl8169_private *);
 676         } jumbo_ops;
 677
 678         void (*hw_start)(struct rtl8169_private *tp);
 679         bool (*tso_csum)(struct rtl8169_private *, struct sk_buff *, u32 *);
 680
 681         struct {
 682                 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
 683                 struct mutex mutex;
 684                 struct work_struct work;
 685         } wk;
 686
 687         unsigned supports_gmii:1;
 688         struct mii_bus *mii_bus;
 689         dma_addr_t counters_phys_addr;
 690         struct rtl8169_counters *counters;
 691         struct rtl8169_tc_offsets tc_offset;
 692         u32 saved_wolopts;
 693
 694         struct rtl_fw {
 695                 const struct firmware *fw;
 696
 697 #define RTL_VER_SIZE            32
 698
 699                 char version[RTL_VER_SIZE];
 700
 701                 struct rtl_fw_phy_action {
 702                         __le32 *code;
 703                         size_t size;
 704                 } phy_action;
 705         } *rtl_fw;
 706 #define RTL_FIRMWARE_UNKNOWN    ERR_PTR(-EAGAIN)
 707
 708         u32 ocp_base;
 709 };
 710
 711 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
 712 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
 713 module_param(use_dac, int, 0);
 714 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
 715 module_param_named(debug, debug.msg_enable, int, 0);
 716 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
 717 MODULE_LICENSE("GPL");
 718 MODULE_FIRMWARE(FIRMWARE_8168D_1);
 719 MODULE_FIRMWARE(FIRMWARE_8168D_2);
 720 MODULE_FIRMWARE(FIRMWARE_8168E_1);
 721 MODULE_FIRMWARE(FIRMWARE_8168E_2);
 722 MODULE_FIRMWARE(FIRMWARE_8168E_3);
 723 MODULE_FIRMWARE(FIRMWARE_8105E_1);
 724 MODULE_FIRMWARE(FIRMWARE_8168F_1);
 725 MODULE_FIRMWARE(FIRMWARE_8168F_2);
 726 MODULE_FIRMWARE(FIRMWARE_8402_1);
 727 MODULE_FIRMWARE(FIRMWARE_8411_1);
 728 MODULE_FIRMWARE(FIRMWARE_8411_2);
 729 MODULE_FIRMWARE(FIRMWARE_8106E_1);
 730 MODULE_FIRMWARE(FIRMWARE_8106E_2);
 731 MODULE_FIRMWARE(FIRMWARE_8168G_2);
 732 MODULE_FIRMWARE(FIRMWARE_8168G_3);
 733 MODULE_FIRMWARE(FIRMWARE_8168H_1);
 734 MODULE_FIRMWARE(FIRMWARE_8168H_2);
 735 MODULE_FIRMWARE(FIRMWARE_8107E_1);
 736 MODULE_FIRMWARE(FIRMWARE_8107E_2);
 737
 738 static inline struct device *tp_to_dev(struct rtl8169_private *tp)
 739 {
 740         return &tp->pci_dev->dev;
 741 }
 742
 743 static void rtl_lock_work(struct rtl8169_private *tp)
 744 {
 745         mutex_lock(&tp->wk.mutex);
 746 }
 747
 748 static void rtl_unlock_work(struct rtl8169_private *tp)
 749 {
 750         mutex_unlock(&tp->wk.mutex);
 751 }
 752
 753 static void rtl_tx_performance_tweak(struct rtl8169_private *tp, u16 force)
 754 {
 755         pcie_capability_clear_and_set_word(tp->pci_dev, PCI_EXP_DEVCTL,
 756                                            PCI_EXP_DEVCTL_READRQ, force);
 757 }
 758
 759 struct rtl_cond {
 760         bool (*check)(struct rtl8169_private *);
 761         const char *msg;
 762 };
 763
 764 static void rtl_udelay(unsigned int d)
 765 {
 766         udelay(d);
 767 }
 768
 769 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,
 770                           void (*delay)(unsigned int), unsigned int d, int n,
 771                           bool high)
 772 {
 773         int i;
 774
 775         for (i = 0; i < n; i++) {
 776                 delay(d);
 777                 if (c->check(tp) == high)
 778                         return true;
 779         }
 780         netif_err(tp, drv, tp->dev, "%s == %d (loop: %d, delay: %d).\n",
 781                   c->msg, !high, n, d);
 782         return false;
 783 }
 784
 785 static bool rtl_udelay_loop_wait_high(struct rtl8169_private *tp,
 786                                       const struct rtl_cond *c,
 787                                       unsigned int d, int n)
 788 {
 789         return rtl_loop_wait(tp, c, rtl_udelay, d, n, true);
 790 }
 791
 792 static bool rtl_udelay_loop_wait_low(struct rtl8169_private *tp,
 793                                      const struct rtl_cond *c,
 794                                      unsigned int d, int n)
 795 {
 796         return rtl_loop_wait(tp, c, rtl_udelay, d, n, false);
 797 }
 798
 799 static bool rtl_msleep_loop_wait_high(struct rtl8169_private *tp,
 800                                       const struct rtl_cond *c,
 801                                       unsigned int d, int n)
 802 {
 803         return rtl_loop_wait(tp, c, msleep, d, n, true);
 804 }
 805
 806 static bool rtl_msleep_loop_wait_low(struct rtl8169_private *tp,
 807                                      const struct rtl_cond *c,
 808                                      unsigned int d, int n)
 809 {
 810         return rtl_loop_wait(tp, c, msleep, d, n, false);
 811 }
 812
 813 #define DECLARE_RTL_COND(name)                          \
 814 static bool name ## _check(struct rtl8169_private *);   \
 815                                                         \
 816 static const struct rtl_cond name = {                   \
 817         .check  = name ## _check,                       \
 818         .msg    = #name                                 \
 819 };                                                      \
 820                                                         \
 821 static bool name ## _check(struct rtl8169_private *tp)
 822
 823 static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg)
 824 {
 825         if (reg & 0xffff0001) {
 826                 netif_err(tp, drv, tp->dev, "Invalid ocp reg %x!\n", reg);
 827                 return true;
 828         }
 829         return false;
 830 }
 831
 832 DECLARE_RTL_COND(rtl_ocp_gphy_cond)
 833 {
 834         return RTL_R32(tp, GPHY_OCP) & OCPAR_FLAG;
 835 }
 836
 837 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
 838 {
 839         if (rtl_ocp_reg_failure(tp, reg))
 840                 return;
 841
 842         RTL_W32(tp, GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);
 843
 844         rtl_udelay_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);
 845 }
 846
 847 static u16 r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
 848 {
 849         if (rtl_ocp_reg_failure(tp, reg))
 850                 return 0;
 851
 852         RTL_W32(tp, GPHY_OCP, reg << 15);
 853
 854         return rtl_udelay_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?
 855                 (RTL_R32(tp, GPHY_OCP) & 0xffff) : ~0;
 856 }
 857
 858 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
 859 {
 860         if (rtl_ocp_reg_failure(tp, reg))
 861                 return;
 862
 863         RTL_W32(tp, OCPDR, OCPAR_FLAG | (reg << 15) | data);
 864 }
 865
 866 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
 867 {
 868         if (rtl_ocp_reg_failure(tp, reg))
 869                 return 0;
 870
 871         RTL_W32(tp, OCPDR, reg << 15);
 872
 873         return RTL_R32(tp, OCPDR);
 874 }
 875
 876 #define OCP_STD_PHY_BASE        0xa400
 877
 878 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)
 879 {
 880         if (reg == 0x1f) {
 881                 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;
 882                 return;
 883         }
 884
 885         if (tp->ocp_base != OCP_STD_PHY_BASE)
 886                 reg -= 0x10;
 887
 888         r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);
 889 }
 890
 891 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)
 892 {
 893         if (tp->ocp_base != OCP_STD_PHY_BASE)
 894                 reg -= 0x10;
 895
 896         return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);
 897 }
 898
 899 static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value)
 900 {
 901         if (reg == 0x1f) {
 902                 tp->ocp_base = value << 4;
 903                 return;
 904         }
 905
 906         r8168_mac_ocp_write(tp, tp->ocp_base + reg, value);
 907 }
 908
 909 static int mac_mcu_read(struct rtl8169_private *tp, int reg)
 910 {
 911         return r8168_mac_ocp_read(tp, tp->ocp_base + reg);
 912 }
 913
 914 DECLARE_RTL_COND(rtl_phyar_cond)
 915 {
 916         return RTL_R32(tp, PHYAR) & 0x80000000;
 917 }
 918
 919 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)
 920 {
 921         RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
 922
 923         rtl_udelay_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);
 924         /*
 925          * According to hardware specs a 20us delay is required after write
 926          * complete indication, but before sending next command.
 927          */
 928         udelay(20);
 929 }
 930
 931 static int r8169_mdio_read(struct rtl8169_private *tp, int reg)
 932 {
 933         int value;
 934
 935         RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16);
 936
 937         value = rtl_udelay_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?
 938                 RTL_R32(tp, PHYAR) & 0xffff : ~0;
 939
 940         /*
 941          * According to hardware specs a 20us delay is required after read
 942          * complete indication, but before sending next command.
 943          */
 944         udelay(20);
 945
 946         return value;
 947 }
 948
 949 DECLARE_RTL_COND(rtl_ocpar_cond)
 950 {
 951         return RTL_R32(tp, OCPAR) & OCPAR_FLAG;
 952 }
 953
 954 static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data)
 955 {
 956         RTL_W32(tp, OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
 957         RTL_W32(tp, OCPAR, OCPAR_GPHY_WRITE_CMD);
 958         RTL_W32(tp, EPHY_RXER_NUM, 0);
 959
 960         rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100);
 961 }
 962
 963 static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value)
 964 {
 965         r8168dp_1_mdio_access(tp, reg,
 966                               OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK));
 967 }
 968
 969 static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg)
 970 {
 971         r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD);
 972
 973         mdelay(1);
 974         RTL_W32(tp, OCPAR, OCPAR_GPHY_READ_CMD);
 975         RTL_W32(tp, EPHY_RXER_NUM, 0);
 976
 977         return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ?
 978                 RTL_R32(tp, OCPDR) & OCPDR_DATA_MASK : ~0;
 979 }
 980
 981 #define R8168DP_1_MDIO_ACCESS_BIT       0x00020000
 982
 983 static void r8168dp_2_mdio_start(struct rtl8169_private *tp)
 984 {
 985         RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
 986 }
 987
 988 static void r8168dp_2_mdio_stop(struct rtl8169_private *tp)
 989 {
 990         RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
 991 }
 992
 993 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)
 994 {
 995         r8168dp_2_mdio_start(tp);
 996
 997         r8169_mdio_write(tp, reg, value);
 998
 999         r8168dp_2_mdio_stop(tp);
1000 }
1001
1002 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)
1003 {
1004         int value;
1005
1006         r8168dp_2_mdio_start(tp);
1007
1008         value = r8169_mdio_read(tp, reg);
1009
1010         r8168dp_2_mdio_stop(tp);
1011
1012         return value;
1013 }
1014
1015 static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
1016 {
1017         tp->mdio_ops.write(tp, location, val);
1018 }
1019
1020 static int rtl_readphy(struct rtl8169_private *tp, int location)
1021 {
1022         return tp->mdio_ops.read(tp, location);
1023 }
1024
1025 static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
1026 {
1027         rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
1028 }
1029
1030 static void rtl_w0w1_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
1031 {
1032         int val;
1033
1034         val = rtl_readphy(tp, reg_addr);
1035         rtl_writephy(tp, reg_addr, (val & ~m) | p);
1036 }
1037
1038 DECLARE_RTL_COND(rtl_ephyar_cond)
1039 {
1040         return RTL_R32(tp, EPHYAR) & EPHYAR_FLAG;
1041 }
1042
1043 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)
1044 {
1045         RTL_W32(tp, EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1046                 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1047
1048         rtl_udelay_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);
1049
1050         udelay(10);
1051 }
1052
1053 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)
1054 {
1055         RTL_W32(tp, EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1056
1057         return rtl_udelay_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?
1058                 RTL_R32(tp, EPHYAR) & EPHYAR_DATA_MASK : ~0;
1059 }
1060
1061 DECLARE_RTL_COND(rtl_eriar_cond)
1062 {
1063         return RTL_R32(tp, ERIAR) & ERIAR_FLAG;
1064 }
1065
1066 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1067                           u32 val, int type)
1068 {
1069         BUG_ON((addr & 3) || (mask == 0));
1070         RTL_W32(tp, ERIDR, val);
1071         RTL_W32(tp, ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
1072
1073         rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);
1074 }
1075
1076 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
1077 {
1078         RTL_W32(tp, ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
1079
1080         return rtl_udelay_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?
1081                 RTL_R32(tp, ERIDR) : ~0;
1082 }
1083
1084 static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 mask, u32 p,
1085                          u32 m, int type)
1086 {
1087         u32 val;
1088
1089         val = rtl_eri_read(tp, addr, type);
1090         rtl_eri_write(tp, addr, mask, (val & ~m) | p, type);
1091 }
1092
1093 static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1094 {
1095         RTL_W32(tp, OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1096         return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?
1097                 RTL_R32(tp, OCPDR) : ~0;
1098 }
1099
1100 static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1101 {
1102         return rtl_eri_read(tp, reg, ERIAR_OOB);
1103 }
1104
1105 static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1106 {
1107         switch (tp->mac_version) {
1108         case RTL_GIGA_MAC_VER_27:
1109         case RTL_GIGA_MAC_VER_28:
1110         case RTL_GIGA_MAC_VER_31:
1111                 return r8168dp_ocp_read(tp, mask, reg);
1112         case RTL_GIGA_MAC_VER_49:
1113         case RTL_GIGA_MAC_VER_50:
1114         case RTL_GIGA_MAC_VER_51:
1115                 return r8168ep_ocp_read(tp, mask, reg);
1116         default:
1117                 BUG();
1118                 return ~0;
1119         }
1120 }
1121
1122 static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1123                               u32 data)
1124 {
1125         RTL_W32(tp, OCPDR, data);
1126         RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1127         rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);
1128 }
1129
1130 static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1131                               u32 data)
1132 {
1133         rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT,
1134                       data, ERIAR_OOB);
1135 }
1136
1137 static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
1138 {
1139         switch (tp->mac_version) {
1140         case RTL_GIGA_MAC_VER_27:
1141         case RTL_GIGA_MAC_VER_28:
1142         case RTL_GIGA_MAC_VER_31:
1143                 r8168dp_ocp_write(tp, mask, reg, data);
1144                 break;
1145         case RTL_GIGA_MAC_VER_49:
1146         case RTL_GIGA_MAC_VER_50:
1147         case RTL_GIGA_MAC_VER_51:
1148                 r8168ep_ocp_write(tp, mask, reg, data);
1149                 break;
1150         default:
1151                 BUG();
1152                 break;
1153         }
1154 }
1155
1156 static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
1157 {
1158         rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd, ERIAR_EXGMAC);
1159
1160         ocp_write(tp, 0x1, 0x30, 0x00000001);
1161 }
1162
1163 #define OOB_CMD_RESET           0x00
1164 #define OOB_CMD_DRIVER_START    0x05
1165 #define OOB_CMD_DRIVER_STOP     0x06
1166
1167 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
1168 {
1169         return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
1170 }
1171
1172 DECLARE_RTL_COND(rtl_ocp_read_cond)
1173 {
1174         u16 reg;
1175
1176         reg = rtl8168_get_ocp_reg(tp);
1177
1178         return ocp_read(tp, 0x0f, reg) & 0x00000800;
1179 }
1180
1181 DECLARE_RTL_COND(rtl_ep_ocp_read_cond)
1182 {
1183         return ocp_read(tp, 0x0f, 0x124) & 0x00000001;
1184 }
1185
1186 DECLARE_RTL_COND(rtl_ocp_tx_cond)
1187 {
1188         return RTL_R8(tp, IBISR0) & 0x20;
1189 }
1190
1191 static void rtl8168ep_stop_cmac(struct rtl8169_private *tp)
1192 {
1193         RTL_W8(tp, IBCR2, RTL_R8(tp, IBCR2) & ~0x01);
1194         rtl_msleep_loop_wait_high(tp, &rtl_ocp_tx_cond, 50, 2000);
1195         RTL_W8(tp, IBISR0, RTL_R8(tp, IBISR0) | 0x20);
1196         RTL_W8(tp, IBCR0, RTL_R8(tp, IBCR0) & ~0x01);
1197 }
1198
1199 static void rtl8168dp_driver_start(struct rtl8169_private *tp)
1200 {
1201         rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
1202         rtl_msleep_loop_wait_high(tp, &rtl_ocp_read_cond, 10, 10);
1203 }
1204
1205 static void rtl8168ep_driver_start(struct rtl8169_private *tp)
1206 {
1207         ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START);
1208         ocp_write(tp, 0x01, 0x30, ocp_read(tp, 0x01, 0x30) | 0x01);
1209         rtl_msleep_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10, 10);
1210 }
1211
1212 static void rtl8168_driver_start(struct rtl8169_private *tp)
1213 {
1214         switch (tp->mac_version) {
1215         case RTL_GIGA_MAC_VER_27:
1216         case RTL_GIGA_MAC_VER_28:
1217         case RTL_GIGA_MAC_VER_31:
1218                 rtl8168dp_driver_start(tp);
1219                 break;
1220         case RTL_GIGA_MAC_VER_49:
1221         case RTL_GIGA_MAC_VER_50:
1222         case RTL_GIGA_MAC_VER_51:
1223                 rtl8168ep_driver_start(tp);
1224                 break;
1225         default:
1226                 BUG();
1227                 break;
1228         }
1229 }
1230
1231 static void rtl8168dp_driver_stop(struct rtl8169_private *tp)
1232 {
1233         rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
1234         rtl_msleep_loop_wait_low(tp, &rtl_ocp_read_cond, 10, 10);
1235 }
1236
1237 static void rtl8168ep_driver_stop(struct rtl8169_private *tp)
1238 {
1239         rtl8168ep_stop_cmac(tp);
1240         ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP);
1241         ocp_write(tp, 0x01, 0x30, ocp_read(tp, 0x01, 0x30) | 0x01);
1242         rtl_msleep_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10, 10);
1243 }
1244
1245 static void rtl8168_driver_stop(struct rtl8169_private *tp)
1246 {
1247         switch (tp->mac_version) {
1248         case RTL_GIGA_MAC_VER_27:
1249         case RTL_GIGA_MAC_VER_28:
1250         case RTL_GIGA_MAC_VER_31:
1251                 rtl8168dp_driver_stop(tp);
1252                 break;
1253         case RTL_GIGA_MAC_VER_49:
1254         case RTL_GIGA_MAC_VER_50:
1255         case RTL_GIGA_MAC_VER_51:
1256                 rtl8168ep_driver_stop(tp);
1257                 break;
1258         default:
1259                 BUG();
1260                 break;
1261         }
1262 }
1263
1264 static bool r8168dp_check_dash(struct rtl8169_private *tp)
1265 {
1266         u16 reg = rtl8168_get_ocp_reg(tp);
1267
1268         return !!(ocp_read(tp, 0x0f, reg) & 0x00008000);
1269 }
1270
1271 static bool r8168ep_check_dash(struct rtl8169_private *tp)
1272 {
1273         return !!(ocp_read(tp, 0x0f, 0x128) & 0x00000001);
1274 }
1275
1276 static bool r8168_check_dash(struct rtl8169_private *tp)
1277 {
1278         switch (tp->mac_version) {
1279         case RTL_GIGA_MAC_VER_27:
1280         case RTL_GIGA_MAC_VER_28:
1281         case RTL_GIGA_MAC_VER_31:
1282                 return r8168dp_check_dash(tp);
1283         case RTL_GIGA_MAC_VER_49:
1284         case RTL_GIGA_MAC_VER_50:
1285         case RTL_GIGA_MAC_VER_51:
1286                 return r8168ep_check_dash(tp);
1287         default:
1288                 return false;
1289         }
1290 }
1291
1292 struct exgmac_reg {
1293         u16 addr;
1294         u16 mask;
1295         u32 val;
1296 };
1297
1298 static void rtl_write_exgmac_batch(struct rtl8169_private *tp,
1299                                    const struct exgmac_reg *r, int len)
1300 {
1301         while (len-- > 0) {
1302                 rtl_eri_write(tp, r->addr, r->mask, r->val, ERIAR_EXGMAC);
1303                 r++;
1304         }
1305 }
1306
1307 DECLARE_RTL_COND(rtl_efusear_cond)
1308 {
1309         return RTL_R32(tp, EFUSEAR) & EFUSEAR_FLAG;
1310 }
1311
1312 static u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)
1313 {
1314         RTL_W32(tp, EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1315
1316         return rtl_udelay_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?
1317                 RTL_R32(tp, EFUSEAR) & EFUSEAR_DATA_MASK : ~0;
1318 }
1319
1320 static u16 rtl_get_events(struct rtl8169_private *tp)
1321 {
1322         return RTL_R16(tp, IntrStatus);
1323 }
1324
1325 static void rtl_ack_events(struct rtl8169_private *tp, u16 bits)
1326 {
1327         RTL_W16(tp, IntrStatus, bits);
1328         mmiowb();
1329 }
1330
1331 static void rtl_irq_disable(struct rtl8169_private *tp)
1332 {
1333         RTL_W16(tp, IntrMask, 0);
1334         mmiowb();
1335 }
1336
1337 #define RTL_EVENT_NAPI_RX       (RxOK | RxErr)
1338 #define RTL_EVENT_NAPI_TX       (TxOK | TxErr)
1339 #define RTL_EVENT_NAPI          (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX)
1340
1341 static void rtl_irq_enable(struct rtl8169_private *tp)
1342 {
1343         RTL_W16(tp, IntrMask, tp->irq_mask);
1344 }
1345
1346 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1347 {
1348         rtl_irq_disable(tp);
1349         rtl_ack_events(tp, 0xffff);
1350         /* PCI commit */
1351         RTL_R8(tp, ChipCmd);
1352 }
1353
1354 static void rtl_link_chg_patch(struct rtl8169_private *tp)
1355 {
1356         struct net_device *dev = tp->dev;
1357         struct phy_device *phydev = dev->phydev;
1358
1359         if (!netif_running(dev))
1360                 return;
1361
1362         if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
1363             tp->mac_version == RTL_GIGA_MAC_VER_38) {
1364                 if (phydev->speed == SPEED_1000) {
1365                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1366                                       ERIAR_EXGMAC);
1367                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1368                                       ERIAR_EXGMAC);
1369                 } else if (phydev->speed == SPEED_100) {
1370                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1371                                       ERIAR_EXGMAC);
1372                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1373                                       ERIAR_EXGMAC);
1374                 } else {
1375                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1376                                       ERIAR_EXGMAC);
1377                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1378                                       ERIAR_EXGMAC);
1379                 }
1380                 /* Reset packet filter */
1381                 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01,
1382                              ERIAR_EXGMAC);
1383                 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00,
1384                              ERIAR_EXGMAC);
1385         } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1386                    tp->mac_version == RTL_GIGA_MAC_VER_36) {
1387                 if (phydev->speed == SPEED_1000) {
1388                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1389                                       ERIAR_EXGMAC);
1390                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1391                                       ERIAR_EXGMAC);
1392                 } else {
1393                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1394                                       ERIAR_EXGMAC);
1395                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1396                                       ERIAR_EXGMAC);
1397                 }
1398         } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
1399                 if (phydev->speed == SPEED_10) {
1400                         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02,
1401                                       ERIAR_EXGMAC);
1402                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060,
1403                                       ERIAR_EXGMAC);
1404                 } else {
1405                         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000,
1406                                       ERIAR_EXGMAC);
1407                 }
1408         }
1409 }
1410
1411 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1412
1413 static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
1414 {
1415         u8 options;
1416         u32 wolopts = 0;
1417
1418         options = RTL_R8(tp, Config1);
1419         if (!(options & PMEnable))
1420                 return 0;
1421
1422         options = RTL_R8(tp, Config3);
1423         if (options & LinkUp)
1424                 wolopts |= WAKE_PHY;
1425         switch (tp->mac_version) {
1426         case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
1427         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
1428                 if (rtl_eri_read(tp, 0xdc, ERIAR_EXGMAC) & MagicPacket_v2)
1429                         wolopts |= WAKE_MAGIC;
1430                 break;
1431         default:
1432                 if (options & MagicPacket)
1433                         wolopts |= WAKE_MAGIC;
1434                 break;
1435         }
1436
1437         options = RTL_R8(tp, Config5);
1438         if (options & UWF)
1439                 wolopts |= WAKE_UCAST;
1440         if (options & BWF)
1441                 wolopts |= WAKE_BCAST;
1442         if (options & MWF)
1443                 wolopts |= WAKE_MCAST;
1444
1445         return wolopts;
1446 }
1447
1448 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1449 {
1450         struct rtl8169_private *tp = netdev_priv(dev);
1451
1452         rtl_lock_work(tp);
1453         wol->supported = WAKE_ANY;
1454         wol->wolopts = tp->saved_wolopts;
1455         rtl_unlock_work(tp);
1456 }
1457
1458 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1459 {
1460         unsigned int i, tmp;
1461         static const struct {
1462                 u32 opt;
1463                 u16 reg;
1464                 u8  mask;
1465         } cfg[] = {
1466                 { WAKE_PHY,   Config3, LinkUp },
1467                 { WAKE_UCAST, Config5, UWF },
1468                 { WAKE_BCAST, Config5, BWF },
1469                 { WAKE_MCAST, Config5, MWF },
1470                 { WAKE_ANY,   Config5, LanWake },
1471                 { WAKE_MAGIC, Config3, MagicPacket }
1472         };
1473         u8 options;
1474
1475         RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
1476
1477         switch (tp->mac_version) {
1478         case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
1479         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
1480                 tmp = ARRAY_SIZE(cfg) - 1;
1481                 if (wolopts & WAKE_MAGIC)
1482                         rtl_w0w1_eri(tp,
1483                                      0x0dc,
1484                                      ERIAR_MASK_0100,
1485                                      MagicPacket_v2,
1486                                      0x0000,
1487                                      ERIAR_EXGMAC);
1488                 else
1489                         rtl_w0w1_eri(tp,
1490                                      0x0dc,
1491                                      ERIAR_MASK_0100,
1492                                      0x0000,
1493                                      MagicPacket_v2,
1494                                      ERIAR_EXGMAC);
1495                 break;
1496         default:
1497                 tmp = ARRAY_SIZE(cfg);
1498                 break;
1499         }
1500
1501         for (i = 0; i < tmp; i++) {
1502                 options = RTL_R8(tp, cfg[i].reg) & ~cfg[i].mask;
1503                 if (wolopts & cfg[i].opt)
1504                         options |= cfg[i].mask;
1505                 RTL_W8(tp, cfg[i].reg, options);
1506         }
1507
1508         switch (tp->mac_version) {
1509         case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_17:
1510                 options = RTL_R8(tp, Config1) & ~PMEnable;
1511                 if (wolopts)
1512                         options |= PMEnable;
1513                 RTL_W8(tp, Config1, options);
1514                 break;
1515         default:
1516                 options = RTL_R8(tp, Config2) & ~PME_SIGNAL;
1517                 if (wolopts)
1518                         options |= PME_SIGNAL;
1519                 RTL_W8(tp, Config2, options);
1520                 break;
1521         }
1522
1523         RTL_W8(tp, Cfg9346, Cfg9346_Lock);
1524 }
1525
1526 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1527 {
1528         struct rtl8169_private *tp = netdev_priv(dev);
1529         struct device *d = tp_to_dev(tp);
1530
1531         if (wol->wolopts & ~WAKE_ANY)
1532                 return -EINVAL;
1533
1534         pm_runtime_get_noresume(d);
1535
1536         rtl_lock_work(tp);
1537
1538         tp->saved_wolopts = wol->wolopts;
1539
1540         if (pm_runtime_active(d))
1541                 __rtl8169_set_wol(tp, tp->saved_wolopts);
1542
1543         rtl_unlock_work(tp);
1544
1545         device_set_wakeup_enable(d, tp->saved_wolopts);
1546
1547         pm_runtime_put_noidle(d);
1548
1549         return 0;
1550 }
1551
1552 static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp)
1553 {
1554         return rtl_chip_infos[tp->mac_version].fw_name;
1555 }
1556
1557 static void rtl8169_get_drvinfo(struct net_device *dev,
1558                                 struct ethtool_drvinfo *info)
1559 {
1560         struct rtl8169_private *tp = netdev_priv(dev);
1561         struct rtl_fw *rtl_fw = tp->rtl_fw;
1562
1563         strlcpy(info->driver, MODULENAME, sizeof(info->driver));
1564         strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1565         BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
1566         if (!IS_ERR_OR_NULL(rtl_fw))
1567                 strlcpy(info->fw_version, rtl_fw->version,
1568                         sizeof(info->fw_version));
1569 }
1570
1571 static int rtl8169_get_regs_len(struct net_device *dev)
1572 {
1573         return R8169_REGS_SIZE;
1574 }
1575
1576 static netdev_features_t rtl8169_fix_features(struct net_device *dev,
1577         netdev_features_t features)
1578 {
1579         struct rtl8169_private *tp = netdev_priv(dev);
1580
1581         if (dev->mtu > TD_MSS_MAX)
1582                 features &= ~NETIF_F_ALL_TSO;
1583
1584         if (dev->mtu > JUMBO_1K &&
1585             tp->mac_version > RTL_GIGA_MAC_VER_06)
1586                 features &= ~NETIF_F_IP_CSUM;
1587
1588         return features;
1589 }
1590
1591 static int rtl8169_set_features(struct net_device *dev,
1592                                 netdev_features_t features)
1593 {
1594         struct rtl8169_private *tp = netdev_priv(dev);
1595         u32 rx_config;
1596
1597         rtl_lock_work(tp);
1598
1599         rx_config = RTL_R32(tp, RxConfig);
1600         if (features & NETIF_F_RXALL)
1601                 rx_config |= (AcceptErr | AcceptRunt);
1602         else
1603                 rx_config &= ~(AcceptErr | AcceptRunt);
1604
1605         RTL_W32(tp, RxConfig, rx_config);
1606
1607         if (features & NETIF_F_RXCSUM)
1608                 tp->cp_cmd |= RxChkSum;
1609         else
1610                 tp->cp_cmd &= ~RxChkSum;
1611
1612         if (features & NETIF_F_HW_VLAN_CTAG_RX)
1613                 tp->cp_cmd |= RxVlan;
1614         else
1615                 tp->cp_cmd &= ~RxVlan;
1616
1617         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1618         RTL_R16(tp, CPlusCmd);
1619
1620         rtl_unlock_work(tp);
1621
1622         return 0;
1623 }
1624
1625 static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb)
1626 {
1627         return (skb_vlan_tag_present(skb)) ?
1628                 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00;
1629 }
1630
1631 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1632 {
1633         u32 opts2 = le32_to_cpu(desc->opts2);
1634
1635         if (opts2 & RxVlanTag)
1636                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff));
1637 }
1638
1639 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1640                              void *p)
1641 {
1642         struct rtl8169_private *tp = netdev_priv(dev);
1643         u32 __iomem *data = tp->mmio_addr;
1644         u32 *dw = p;
1645         int i;
1646
1647         rtl_lock_work(tp);
1648         for (i = 0; i < R8169_REGS_SIZE; i += 4)
1649                 memcpy_fromio(dw++, data++, 4);
1650         rtl_unlock_work(tp);
1651 }
1652
1653 static u32 rtl8169_get_msglevel(struct net_device *dev)
1654 {
1655         struct rtl8169_private *tp = netdev_priv(dev);
1656
1657         return tp->msg_enable;
1658 }
1659
1660 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1661 {
1662         struct rtl8169_private *tp = netdev_priv(dev);
1663
1664         tp->msg_enable = value;
1665 }
1666
1667 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1668         "tx_packets",
1669         "rx_packets",
1670         "tx_errors",
1671         "rx_errors",
1672         "rx_missed",
1673         "align_errors",
1674         "tx_single_collisions",
1675         "tx_multi_collisions",
1676         "unicast",
1677         "broadcast",
1678         "multicast",
1679         "tx_aborted",
1680         "tx_underrun",
1681 };
1682
1683 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1684 {
1685         switch (sset) {
1686         case ETH_SS_STATS:
1687                 return ARRAY_SIZE(rtl8169_gstrings);
1688         default:
1689                 return -EOPNOTSUPP;
1690         }
1691 }
1692
1693 DECLARE_RTL_COND(rtl_counters_cond)
1694 {
1695         return RTL_R32(tp, CounterAddrLow) & (CounterReset | CounterDump);
1696 }
1697
1698 static bool rtl8169_do_counters(struct rtl8169_private *tp, u32 counter_cmd)
1699 {
1700         dma_addr_t paddr = tp->counters_phys_addr;
1701         u32 cmd;
1702
1703         RTL_W32(tp, CounterAddrHigh, (u64)paddr >> 32);
1704         RTL_R32(tp, CounterAddrHigh);
1705         cmd = (u64)paddr & DMA_BIT_MASK(32);
1706         RTL_W32(tp, CounterAddrLow, cmd);
1707         RTL_W32(tp, CounterAddrLow, cmd | counter_cmd);
1708
1709         return rtl_udelay_loop_wait_low(tp, &rtl_counters_cond, 10, 1000);
1710 }
1711
1712 static bool rtl8169_reset_counters(struct rtl8169_private *tp)
1713 {
1714         /*
1715          * Versions prior to RTL_GIGA_MAC_VER_19 don't support resetting the
1716          * tally counters.
1717          */
1718         if (tp->mac_version < RTL_GIGA_MAC_VER_19)
1719                 return true;
1720
1721         return rtl8169_do_counters(tp, CounterReset);
1722 }
1723
1724 static bool rtl8169_update_counters(struct rtl8169_private *tp)
1725 {
1726         /*
1727          * Some chips are unable to dump tally counters when the receiver
1728          * is disabled.
1729          */
1730         if ((RTL_R8(tp, ChipCmd) & CmdRxEnb) == 0)
1731                 return true;
1732
1733         return rtl8169_do_counters(tp, CounterDump);
1734 }
1735
1736 static bool rtl8169_init_counter_offsets(struct rtl8169_private *tp)
1737 {
1738         struct rtl8169_counters *counters = tp->counters;
1739         bool ret = false;
1740
1741         /*
1742          * rtl8169_init_counter_offsets is called from rtl_open.  On chip
1743          * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only
1744          * reset by a power cycle, while the counter values collected by the
1745          * driver are reset at every driver unload/load cycle.
1746          *
1747          * To make sure the HW values returned by @get_stats64 match the SW
1748          * values, we collect the initial values at first open(*) and use them
1749          * as offsets to normalize the values returned by @get_stats64.
1750          *
1751          * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one
1752          * for the reason stated in rtl8169_update_counters; CmdRxEnb is only
1753          * set at open time by rtl_hw_start.
1754          */
1755
1756         if (tp->tc_offset.inited)
1757                 return true;
1758
1759         /* If both, reset and update fail, propagate to caller. */
1760         if (rtl8169_reset_counters(tp))
1761                 ret = true;
1762
1763         if (rtl8169_update_counters(tp))
1764                 ret = true;
1765
1766         tp->tc_offset.tx_errors = counters->tx_errors;
1767         tp->tc_offset.tx_multi_collision = counters->tx_multi_collision;
1768         tp->tc_offset.tx_aborted = counters->tx_aborted;
1769         tp->tc_offset.inited = true;
1770
1771         return ret;
1772 }
1773
1774 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1775                                       struct ethtool_stats *stats, u64 *data)
1776 {
1777         struct rtl8169_private *tp = netdev_priv(dev);
1778         struct device *d = tp_to_dev(tp);
1779         struct rtl8169_counters *counters = tp->counters;
1780
1781         ASSERT_RTNL();
1782
1783         pm_runtime_get_noresume(d);
1784
1785         if (pm_runtime_active(d))
1786                 rtl8169_update_counters(tp);
1787
1788         pm_runtime_put_noidle(d);
1789
1790         data[0] = le64_to_cpu(counters->tx_packets);
1791         data[1] = le64_to_cpu(counters->rx_packets);
1792         data[2] = le64_to_cpu(counters->tx_errors);
1793         data[3] = le32_to_cpu(counters->rx_errors);
1794         data[4] = le16_to_cpu(counters->rx_missed);
1795         data[5] = le16_to_cpu(counters->align_errors);
1796         data[6] = le32_to_cpu(counters->tx_one_collision);
1797         data[7] = le32_to_cpu(counters->tx_multi_collision);
1798         data[8] = le64_to_cpu(counters->rx_unicast);
1799         data[9] = le64_to_cpu(counters->rx_broadcast);
1800         data[10] = le32_to_cpu(counters->rx_multicast);
1801         data[11] = le16_to_cpu(counters->tx_aborted);
1802         data[12] = le16_to_cpu(counters->tx_underun);
1803 }
1804
1805 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1806 {
1807         switch(stringset) {
1808         case ETH_SS_STATS:
1809                 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1810                 break;
1811         }
1812 }
1813
1814 /*
1815  * Interrupt coalescing
1816  *
1817  * > 1 - the availability of the IntrMitigate (0xe2) register through the
1818  * >     8169, 8168 and 810x line of chipsets
1819  *
1820  * 8169, 8168, and 8136(810x) serial chipsets support it.
1821  *
1822  * > 2 - the Tx timer unit at gigabit speed
1823  *
1824  * The unit of the timer depends on both the speed and the setting of CPlusCmd
1825  * (0xe0) bit 1 and bit 0.
1826  *
1827  * For 8169
1828  * bit[1:0] \ speed        1000M           100M            10M
1829  * 0 0                     320ns           2.56us          40.96us
1830  * 0 1                     2.56us          20.48us         327.7us
1831  * 1 0                     5.12us          40.96us         655.4us
1832  * 1 1                     10.24us         81.92us         1.31ms
1833  *
1834  * For the other
1835  * bit[1:0] \ speed        1000M           100M            10M
1836  * 0 0                     5us             2.56us          40.96us
1837  * 0 1                     40us            20.48us         327.7us
1838  * 1 0                     80us            40.96us         655.4us
1839  * 1 1                     160us           81.92us         1.31ms
1840  */
1841
1842 /* rx/tx scale factors for one particular CPlusCmd[0:1] value */
1843 struct rtl_coalesce_scale {
1844         /* Rx / Tx */
1845         u32 nsecs[2];
1846 };
1847
1848 /* rx/tx scale factors for all CPlusCmd[0:1] cases */
1849 struct rtl_coalesce_info {
1850         u32 speed;
1851         struct rtl_coalesce_scale scalev[4];    /* each CPlusCmd[0:1] case */
1852 };
1853
1854 /* produce (r,t) pairs with each being in series of *1, *8, *8*2, *8*2*2 */
1855 #define rxtx_x1822(r, t) {              \
1856         {{(r),          (t)}},          \
1857         {{(r)*8,        (t)*8}},        \
1858         {{(r)*8*2,      (t)*8*2}},      \
1859         {{(r)*8*2*2,    (t)*8*2*2}},    \
1860 }
1861 static const struct rtl_coalesce_info rtl_coalesce_info_8169[] = {
1862         /* speed        delays:     rx00   tx00 */
1863         { SPEED_10,     rxtx_x1822(40960, 40960)        },
1864         { SPEED_100,    rxtx_x1822( 2560,  2560)        },
1865         { SPEED_1000,   rxtx_x1822(  320,   320)        },
1866         { 0 },
1867 };
1868
1869 static const struct rtl_coalesce_info rtl_coalesce_info_8168_8136[] = {
1870         /* speed        delays:     rx00   tx00 */
1871         { SPEED_10,     rxtx_x1822(40960, 40960)        },
1872         { SPEED_100,    rxtx_x1822( 2560,  2560)        },
1873         { SPEED_1000,   rxtx_x1822( 5000,  5000)        },
1874         { 0 },
1875 };
1876 #undef rxtx_x1822
1877
1878 /* get rx/tx scale vector corresponding to current speed */
1879 static const struct rtl_coalesce_info *rtl_coalesce_info(struct net_device *dev)
1880 {
1881         struct rtl8169_private *tp = netdev_priv(dev);
1882         struct ethtool_link_ksettings ecmd;
1883         const struct rtl_coalesce_info *ci;
1884         int rc;
1885
1886         rc = phy_ethtool_get_link_ksettings(dev, &ecmd);
1887         if (rc < 0)
1888                 return ERR_PTR(rc);
1889
1890         for (ci = tp->coalesce_info; ci->speed != 0; ci++) {
1891                 if (ecmd.base.speed == ci->speed) {
1892                         return ci;
1893                 }
1894         }
1895
1896         return ERR_PTR(-ELNRNG);
1897 }
1898
1899 static int rtl_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1900 {
1901         struct rtl8169_private *tp = netdev_priv(dev);
1902         const struct rtl_coalesce_info *ci;
1903         const struct rtl_coalesce_scale *scale;
1904         struct {
1905                 u32 *max_frames;
1906                 u32 *usecs;
1907         } coal_settings [] = {
1908                 { &ec->rx_max_coalesced_frames, &ec->rx_coalesce_usecs },
1909                 { &ec->tx_max_coalesced_frames, &ec->tx_coalesce_usecs }
1910         }, *p = coal_settings;
1911         int i;
1912         u16 w;
1913
1914         memset(ec, 0, sizeof(*ec));
1915
1916         /* get rx/tx scale corresponding to current speed and CPlusCmd[0:1] */
1917         ci = rtl_coalesce_info(dev);
1918         if (IS_ERR(ci))
1919                 return PTR_ERR(ci);
1920
1921         scale = &ci->scalev[tp->cp_cmd & INTT_MASK];
1922
1923         /* read IntrMitigate and adjust according to scale */
1924         for (w = RTL_R16(tp, IntrMitigate); w; w >>= RTL_COALESCE_SHIFT, p++) {
1925                 *p->max_frames = (w & RTL_COALESCE_MASK) << 2;
1926                 w >>= RTL_COALESCE_SHIFT;
1927                 *p->usecs = w & RTL_COALESCE_MASK;
1928         }
1929
1930         for (i = 0; i < 2; i++) {
1931                 p = coal_settings + i;
1932                 *p->usecs = (*p->usecs * scale->nsecs[i]) / 1000;
1933
1934                 /*
1935                  * ethtool_coalesce says it is illegal to set both usecs and
1936                  * max_frames to 0.
1937                  */
1938                 if (!*p->usecs && !*p->max_frames)
1939                         *p->max_frames = 1;
1940         }
1941
1942         return 0;
1943 }
1944
1945 /* choose appropriate scale factor and CPlusCmd[0:1] for (speed, nsec) */
1946 static const struct rtl_coalesce_scale *rtl_coalesce_choose_scale(
1947                         struct net_device *dev, u32 nsec, u16 *cp01)
1948 {
1949         const struct rtl_coalesce_info *ci;
1950         u16 i;
1951
1952         ci = rtl_coalesce_info(dev);
1953         if (IS_ERR(ci))
1954                 return ERR_CAST(ci);
1955
1956         for (i = 0; i < 4; i++) {
1957                 u32 rxtx_maxscale = max(ci->scalev[i].nsecs[0],
1958                                         ci->scalev[i].nsecs[1]);
1959                 if (nsec <= rxtx_maxscale * RTL_COALESCE_T_MAX) {
1960                         *cp01 = i;
1961                         return &ci->scalev[i];
1962                 }
1963         }
1964
1965         return ERR_PTR(-EINVAL);
1966 }
1967
1968 static int rtl_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1969 {
1970         struct rtl8169_private *tp = netdev_priv(dev);
1971         const struct rtl_coalesce_scale *scale;
1972         struct {
1973                 u32 frames;
1974                 u32 usecs;
1975         } coal_settings [] = {
1976                 { ec->rx_max_coalesced_frames, ec->rx_coalesce_usecs },
1977                 { ec->tx_max_coalesced_frames, ec->tx_coalesce_usecs }
1978         }, *p = coal_settings;
1979         u16 w = 0, cp01;
1980         int i;
1981
1982         scale = rtl_coalesce_choose_scale(dev,
1983                         max(p[0].usecs, p[1].usecs) * 1000, &cp01);
1984         if (IS_ERR(scale))
1985                 return PTR_ERR(scale);
1986
1987         for (i = 0; i < 2; i++, p++) {
1988                 u32 units;
1989
1990                 /*
1991                  * accept max_frames=1 we returned in rtl_get_coalesce.
1992                  * accept it not only when usecs=0 because of e.g. the following scenario:
1993                  *
1994                  * - both rx_usecs=0 & rx_frames=0 in hardware (no delay on RX)
1995                  * - rtl_get_coalesce returns rx_usecs=0, rx_frames=1
1996                  * - then user does `ethtool -C eth0 rx-usecs 100`
1997                  *
1998                  * since ethtool sends to kernel whole ethtool_coalesce
1999                  * settings, if we do not handle rx_usecs=!0, rx_frames=1
2000                  * we'll reject it below in `frames % 4 != 0`.
2001                  */
2002                 if (p->frames == 1) {
2003                         p->frames = 0;
2004                 }
2005
2006                 units = p->usecs * 1000 / scale->nsecs[i];
2007                 if (p->frames > RTL_COALESCE_FRAME_MAX || p->frames % 4)
2008                         return -EINVAL;
2009
2010                 w <<= RTL_COALESCE_SHIFT;
2011                 w |= units;
2012                 w <<= RTL_COALESCE_SHIFT;
2013                 w |= p->frames >> 2;
2014         }
2015
2016         rtl_lock_work(tp);
2017
2018         RTL_W16(tp, IntrMitigate, swab16(w));
2019
2020         tp->cp_cmd = (tp->cp_cmd & ~INTT_MASK) | cp01;
2021         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
2022         RTL_R16(tp, CPlusCmd);
2023
2024         rtl_unlock_work(tp);
2025
2026         return 0;
2027 }
2028
2029 static const struct ethtool_ops rtl8169_ethtool_ops = {
2030         .get_drvinfo            = rtl8169_get_drvinfo,
2031         .get_regs_len           = rtl8169_get_regs_len,
2032         .get_link               = ethtool_op_get_link,
2033         .get_coalesce           = rtl_get_coalesce,
2034         .set_coalesce           = rtl_set_coalesce,
2035         .get_msglevel           = rtl8169_get_msglevel,
2036         .set_msglevel           = rtl8169_set_msglevel,
2037         .get_regs               = rtl8169_get_regs,
2038         .get_wol                = rtl8169_get_wol,
2039         .set_wol                = rtl8169_set_wol,
2040         .get_strings            = rtl8169_get_strings,
2041         .get_sset_count         = rtl8169_get_sset_count,
2042         .get_ethtool_stats      = rtl8169_get_ethtool_stats,
2043         .get_ts_info            = ethtool_op_get_ts_info,
2044         .nway_reset             = phy_ethtool_nway_reset,
2045         .get_link_ksettings     = phy_ethtool_get_link_ksettings,
2046         .set_link_ksettings     = phy_ethtool_set_link_ksettings,
2047 };
2048
2049 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
2050                                     u8 default_version)
2051 {
2052         /*
2053          * The driver currently handles the 8168Bf and the 8168Be identically
2054          * but they can be identified more specifically through the test below
2055          * if needed:
2056          *
2057          * (RTL_R32(tp, TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
2058          *
2059          * Same thing for the 8101Eb and the 8101Ec:
2060          *
2061          * (RTL_R32(tp, TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
2062          */
2063         static const struct rtl_mac_info {
2064                 u32 mask;
2065                 u32 val;
2066                 int mac_version;
2067         } mac_info[] = {
2068                 /* 8168EP family. */
2069                 { 0x7cf00000, 0x50200000,       RTL_GIGA_MAC_VER_51 },
2070                 { 0x7cf00000, 0x50100000,       RTL_GIGA_MAC_VER_50 },
2071                 { 0x7cf00000, 0x50000000,       RTL_GIGA_MAC_VER_49 },
2072
2073                 /* 8168H family. */
2074                 { 0x7cf00000, 0x54100000,       RTL_GIGA_MAC_VER_46 },
2075                 { 0x7cf00000, 0x54000000,       RTL_GIGA_MAC_VER_45 },
2076
2077                 /* 8168G family. */
2078                 { 0x7cf00000, 0x5c800000,       RTL_GIGA_MAC_VER_44 },
2079                 { 0x7cf00000, 0x50900000,       RTL_GIGA_MAC_VER_42 },
2080                 { 0x7cf00000, 0x4c100000,       RTL_GIGA_MAC_VER_41 },
2081                 { 0x7cf00000, 0x4c000000,       RTL_GIGA_MAC_VER_40 },
2082
2083                 /* 8168F family. */
2084                 { 0x7c800000, 0x48800000,       RTL_GIGA_MAC_VER_38 },
2085                 { 0x7cf00000, 0x48100000,       RTL_GIGA_MAC_VER_36 },
2086                 { 0x7cf00000, 0x48000000,       RTL_GIGA_MAC_VER_35 },
2087
2088                 /* 8168E family. */
2089                 { 0x7c800000, 0x2c800000,       RTL_GIGA_MAC_VER_34 },
2090                 { 0x7cf00000, 0x2c100000,       RTL_GIGA_MAC_VER_32 },
2091                 { 0x7c800000, 0x2c000000,       RTL_GIGA_MAC_VER_33 },
2092
2093                 /* 8168D family. */
2094                 { 0x7cf00000, 0x28100000,       RTL_GIGA_MAC_VER_25 },
2095                 { 0x7c800000, 0x28000000,       RTL_GIGA_MAC_VER_26 },
2096
2097                 /* 8168DP family. */
2098                 { 0x7cf00000, 0x28800000,       RTL_GIGA_MAC_VER_27 },
2099                 { 0x7cf00000, 0x28a00000,       RTL_GIGA_MAC_VER_28 },
2100                 { 0x7cf00000, 0x28b00000,       RTL_GIGA_MAC_VER_31 },
2101
2102                 /* 8168C family. */
2103                 { 0x7cf00000, 0x3c900000,       RTL_GIGA_MAC_VER_23 },
2104                 { 0x7cf00000, 0x3c800000,       RTL_GIGA_MAC_VER_18 },
2105                 { 0x7c800000, 0x3c800000,       RTL_GIGA_MAC_VER_24 },
2106                 { 0x7cf00000, 0x3c000000,       RTL_GIGA_MAC_VER_19 },
2107                 { 0x7cf00000, 0x3c200000,       RTL_GIGA_MAC_VER_20 },
2108                 { 0x7cf00000, 0x3c300000,       RTL_GIGA_MAC_VER_21 },
2109                 { 0x7c800000, 0x3c000000,       RTL_GIGA_MAC_VER_22 },
2110
2111                 /* 8168B family. */
2112                 { 0x7cf00000, 0x38000000,       RTL_GIGA_MAC_VER_12 },
2113                 { 0x7c800000, 0x38000000,       RTL_GIGA_MAC_VER_17 },
2114                 { 0x7c800000, 0x30000000,       RTL_GIGA_MAC_VER_11 },
2115
2116                 /* 8101 family. */
2117                 { 0x7c800000, 0x44800000,       RTL_GIGA_MAC_VER_39 },
2118                 { 0x7c800000, 0x44000000,       RTL_GIGA_MAC_VER_37 },
2119                 { 0x7cf00000, 0x40900000,       RTL_GIGA_MAC_VER_29 },
2120                 { 0x7c800000, 0x40800000,       RTL_GIGA_MAC_VER_30 },
2121                 { 0x7cf00000, 0x34900000,       RTL_GIGA_MAC_VER_08 },
2122                 { 0x7cf00000, 0x24900000,       RTL_GIGA_MAC_VER_08 },
2123                 { 0x7cf00000, 0x34800000,       RTL_GIGA_MAC_VER_07 },
2124                 { 0x7cf00000, 0x24800000,       RTL_GIGA_MAC_VER_07 },
2125                 { 0x7cf00000, 0x34000000,       RTL_GIGA_MAC_VER_13 },
2126                 { 0x7cf00000, 0x34300000,       RTL_GIGA_MAC_VER_10 },
2127                 { 0x7cf00000, 0x34200000,       RTL_GIGA_MAC_VER_16 },
2128                 { 0x7c800000, 0x34800000,       RTL_GIGA_MAC_VER_09 },
2129                 { 0x7c800000, 0x24800000,       RTL_GIGA_MAC_VER_09 },
2130                 { 0x7c800000, 0x34000000,       RTL_GIGA_MAC_VER_16 },
2131                 /* FIXME: where did these entries come from ? -- FR */
2132                 { 0xfc800000, 0x38800000,       RTL_GIGA_MAC_VER_15 },
2133                 { 0xfc800000, 0x30800000,       RTL_GIGA_MAC_VER_14 },
2134
2135                 /* 8110 family. */
2136                 { 0xfc800000, 0x98000000,       RTL_GIGA_MAC_VER_06 },
2137                 { 0xfc800000, 0x18000000,       RTL_GIGA_MAC_VER_05 },
2138                 { 0xfc800000, 0x10000000,       RTL_GIGA_MAC_VER_04 },
2139                 { 0xfc800000, 0x04000000,       RTL_GIGA_MAC_VER_03 },
2140                 { 0xfc800000, 0x00800000,       RTL_GIGA_MAC_VER_02 },
2141                 { 0xfc800000, 0x00000000,       RTL_GIGA_MAC_VER_01 },
2142
2143                 /* Catch-all */
2144                 { 0x00000000, 0x00000000,       RTL_GIGA_MAC_NONE   }
2145         };
2146         const struct rtl_mac_info *p = mac_info;
2147         u32 reg;
2148
2149         reg = RTL_R32(tp, TxConfig);
2150         while ((reg & p->mask) != p->val)
2151                 p++;
2152         tp->mac_version = p->mac_version;
2153
2154         if (tp->mac_version == RTL_GIGA_MAC_NONE) {
2155                 dev_notice(tp_to_dev(tp),
2156                            "unknown MAC, using family default\n");
2157                 tp->mac_version = default_version;
2158         } else if (tp->mac_version == RTL_GIGA_MAC_VER_42) {
2159                 tp->mac_version = tp->supports_gmii ?
2160                                   RTL_GIGA_MAC_VER_42 :
2161                                   RTL_GIGA_MAC_VER_43;
2162         } else if (tp->mac_version == RTL_GIGA_MAC_VER_45) {
2163                 tp->mac_version = tp->supports_gmii ?
2164                                   RTL_GIGA_MAC_VER_45 :
2165                                   RTL_GIGA_MAC_VER_47;
2166         } else if (tp->mac_version == RTL_GIGA_MAC_VER_46) {
2167                 tp->mac_version = tp->supports_gmii ?
2168                                   RTL_GIGA_MAC_VER_46 :
2169                                   RTL_GIGA_MAC_VER_48;
2170         }
2171 }
2172
2173 struct phy_reg {
2174         u16 reg;
2175         u16 val;
2176 };
2177
2178 static void rtl_writephy_batch(struct rtl8169_private *tp,
2179                                const struct phy_reg *regs, int len)
2180 {
2181         while (len-- > 0) {
2182                 rtl_writephy(tp, regs->reg, regs->val);
2183                 regs++;
2184         }
2185 }
2186
2187 #define PHY_READ                0x00000000
2188 #define PHY_DATA_OR             0x10000000
2189 #define PHY_DATA_AND            0x20000000
2190 #define PHY_BJMPN               0x30000000
2191 #define PHY_MDIO_CHG            0x40000000
2192 #define PHY_CLEAR_READCOUNT     0x70000000
2193 #define PHY_WRITE               0x80000000
2194 #define PHY_READCOUNT_EQ_SKIP   0x90000000
2195 #define PHY_COMP_EQ_SKIPN       0xa0000000
2196 #define PHY_COMP_NEQ_SKIPN      0xb0000000
2197 #define PHY_WRITE_PREVIOUS      0xc0000000
2198 #define PHY_SKIPN               0xd0000000
2199 #define PHY_DELAY_MS            0xe0000000
2200
2201 struct fw_info {
2202         u32     magic;
2203         char    version[RTL_VER_SIZE];
2204         __le32  fw_start;
2205         __le32  fw_len;
2206         u8      chksum;
2207 } __packed;
2208
2209 #define FW_OPCODE_SIZE  sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
2210
2211 static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2212 {
2213         const struct firmware *fw = rtl_fw->fw;
2214         struct fw_info *fw_info = (struct fw_info *)fw->data;
2215         struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2216         char *version = rtl_fw->version;
2217         bool rc = false;
2218
2219         if (fw->size < FW_OPCODE_SIZE)
2220                 goto out;
2221
2222         if (!fw_info->magic) {
2223                 size_t i, size, start;
2224                 u8 checksum = 0;
2225
2226                 if (fw->size < sizeof(*fw_info))
2227                         goto out;
2228
2229                 for (i = 0; i < fw->size; i++)
2230                         checksum += fw->data[i];
2231                 if (checksum != 0)
2232                         goto out;
2233
2234                 start = le32_to_cpu(fw_info->fw_start);
2235                 if (start > fw->size)
2236                         goto out;
2237
2238                 size = le32_to_cpu(fw_info->fw_len);
2239                 if (size > (fw->size - start) / FW_OPCODE_SIZE)
2240                         goto out;
2241
2242                 memcpy(version, fw_info->version, RTL_VER_SIZE);
2243
2244                 pa->code = (__le32 *)(fw->data + start);
2245                 pa->size = size;
2246         } else {
2247                 if (fw->size % FW_OPCODE_SIZE)
2248                         goto out;
2249
2250                 strlcpy(version, rtl_lookup_firmware_name(tp), RTL_VER_SIZE);
2251
2252                 pa->code = (__le32 *)fw->data;
2253                 pa->size = fw->size / FW_OPCODE_SIZE;
2254         }
2255         version[RTL_VER_SIZE - 1] = 0;
2256
2257         rc = true;
2258 out:
2259         return rc;
2260 }
2261
2262 static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev,
2263                            struct rtl_fw_phy_action *pa)
2264 {
2265         bool rc = false;
2266         size_t index;
2267
2268         for (index = 0; index < pa->size; index++) {
2269                 u32 action = le32_to_cpu(pa->code[index]);
2270                 u32 regno = (action & 0x0fff0000) >> 16;
2271
2272                 switch(action & 0xf0000000) {
2273                 case PHY_READ:
2274                 case PHY_DATA_OR:
2275                 case PHY_DATA_AND:
2276                 case PHY_MDIO_CHG:
2277                 case PHY_CLEAR_READCOUNT:
2278                 case PHY_WRITE:
2279                 case PHY_WRITE_PREVIOUS:
2280                 case PHY_DELAY_MS:
2281                         break;
2282
2283                 case PHY_BJMPN:
2284                         if (regno > index) {
2285                                 netif_err(tp, ifup, tp->dev,
2286                                           "Out of range of firmware\n");
2287                                 goto out;
2288                         }
2289                         break;
2290                 case PHY_READCOUNT_EQ_SKIP:
2291                         if (index + 2 >= pa->size) {
2292                                 netif_err(tp, ifup, tp->dev,
2293                                           "Out of range of firmware\n");
2294                                 goto out;
2295                         }
2296                         break;
2297                 case PHY_COMP_EQ_SKIPN:
2298                 case PHY_COMP_NEQ_SKIPN:
2299                 case PHY_SKIPN:
2300                         if (index + 1 + regno >= pa->size) {
2301                                 netif_err(tp, ifup, tp->dev,
2302                                           "Out of range of firmware\n");
2303                                 goto out;
2304                         }
2305                         break;
2306
2307                 default:
2308                         netif_err(tp, ifup, tp->dev,
2309                                   "Invalid action 0x%08x\n", action);
2310                         goto out;
2311                 }
2312         }
2313         rc = true;
2314 out:
2315         return rc;
2316 }
2317
2318 static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2319 {
2320         struct net_device *dev = tp->dev;
2321         int rc = -EINVAL;
2322
2323         if (!rtl_fw_format_ok(tp, rtl_fw)) {
2324                 netif_err(tp, ifup, dev, "invalid firmware\n");
2325                 goto out;
2326         }
2327
2328         if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action))
2329                 rc = 0;
2330 out:
2331         return rc;
2332 }
2333
2334 static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2335 {
2336         struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2337         struct mdio_ops org, *ops = &tp->mdio_ops;
2338         u32 predata, count;
2339         size_t index;
2340
2341         predata = count = 0;
2342         org.write = ops->write;
2343         org.read = ops->read;
2344
2345         for (index = 0; index < pa->size; ) {
2346                 u32 action = le32_to_cpu(pa->code[index]);
2347                 u32 data = action & 0x0000ffff;
2348                 u32 regno = (action & 0x0fff0000) >> 16;
2349
2350                 if (!action)
2351                         break;
2352
2353                 switch(action & 0xf0000000) {
2354                 case PHY_READ:
2355                         predata = rtl_readphy(tp, regno);
2356                         count++;
2357                         index++;
2358                         break;
2359                 case PHY_DATA_OR:
2360                         predata |= data;
2361                         index++;
2362                         break;
2363                 case PHY_DATA_AND:
2364                         predata &= data;
2365                         index++;
2366                         break;
2367                 case PHY_BJMPN:
2368                         index -= regno;
2369                         break;
2370                 case PHY_MDIO_CHG:
2371                         if (data == 0) {
2372                                 ops->write = org.write;
2373                                 ops->read = org.read;
2374                         } else if (data == 1) {
2375                                 ops->write = mac_mcu_write;
2376                                 ops->read = mac_mcu_read;
2377                         }
2378
2379                         index++;
2380                         break;
2381                 case PHY_CLEAR_READCOUNT:
2382                         count = 0;
2383                         index++;
2384                         break;
2385                 case PHY_WRITE:
2386                         rtl_writephy(tp, regno, data);
2387                         index++;
2388                         break;
2389                 case PHY_READCOUNT_EQ_SKIP:
2390                         index += (count == data) ? 2 : 1;
2391                         break;
2392                 case PHY_COMP_EQ_SKIPN:
2393                         if (predata == data)
2394                                 index += regno;
2395                         index++;
2396                         break;
2397                 case PHY_COMP_NEQ_SKIPN:
2398                         if (predata != data)
2399                                 index += regno;
2400                         index++;
2401                         break;
2402                 case PHY_WRITE_PREVIOUS:
2403                         rtl_writephy(tp, regno, predata);
2404                         index++;
2405                         break;
2406                 case PHY_SKIPN:
2407                         index += regno + 1;
2408                         break;
2409                 case PHY_DELAY_MS:
2410                         mdelay(data);
2411                         index++;
2412                         break;
2413
2414                 default:
2415                         BUG();
2416                 }
2417         }
2418
2419         ops->write = org.write;
2420         ops->read = org.read;
2421 }
2422
2423 static void rtl_release_firmware(struct rtl8169_private *tp)
2424 {
2425         if (!IS_ERR_OR_NULL(tp->rtl_fw)) {
2426                 release_firmware(tp->rtl_fw->fw);
2427                 kfree(tp->rtl_fw);
2428         }
2429         tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
2430 }
2431
2432 static void rtl_apply_firmware(struct rtl8169_private *tp)
2433 {
2434         struct rtl_fw *rtl_fw = tp->rtl_fw;
2435
2436         /* TODO: release firmware once rtl_phy_write_fw signals failures. */
2437         if (!IS_ERR_OR_NULL(rtl_fw))
2438                 rtl_phy_write_fw(tp, rtl_fw);
2439 }
2440
2441 static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
2442 {
2443         if (rtl_readphy(tp, reg) != val)
2444                 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
2445         else
2446                 rtl_apply_firmware(tp);
2447 }
2448
2449 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
2450 {
2451         static const struct phy_reg phy_reg_init[] = {
2452                 { 0x1f, 0x0001 },
2453                 { 0x06, 0x006e },
2454                 { 0x08, 0x0708 },
2455                 { 0x15, 0x4000 },
2456                 { 0x18, 0x65c7 },
2457
2458                 { 0x1f, 0x0001 },
2459                 { 0x03, 0x00a1 },
2460                 { 0x02, 0x0008 },
2461                 { 0x01, 0x0120 },
2462                 { 0x00, 0x1000 },
2463                 { 0x04, 0x0800 },
2464                 { 0x04, 0x0000 },
2465
2466                 { 0x03, 0xff41 },
2467                 { 0x02, 0xdf60 },
2468                 { 0x01, 0x0140 },
2469                 { 0x00, 0x0077 },
2470                 { 0x04, 0x7800 },
2471                 { 0x04, 0x7000 },
2472
2473                 { 0x03, 0x802f },
2474                 { 0x02, 0x4f02 },
2475                 { 0x01, 0x0409 },
2476                 { 0x00, 0xf0f9 },
2477                 { 0x04, 0x9800 },
2478                 { 0x04, 0x9000 },
2479
2480                 { 0x03, 0xdf01 },
2481                 { 0x02, 0xdf20 },
2482                 { 0x01, 0xff95 },
2483                 { 0x00, 0xba00 },
2484                 { 0x04, 0xa800 },
2485                 { 0x04, 0xa000 },
2486
2487                 { 0x03, 0xff41 },
2488                 { 0x02, 0xdf20 },
2489                 { 0x01, 0x0140 },
2490                 { 0x00, 0x00bb },
2491                 { 0x04, 0xb800 },
2492                 { 0x04, 0xb000 },
2493
2494                 { 0x03, 0xdf41 },
2495                 { 0x02, 0xdc60 },
2496                 { 0x01, 0x6340 },
2497                 { 0x00, 0x007d },
2498                 { 0x04, 0xd800 },
2499                 { 0x04, 0xd000 },
2500
2501                 { 0x03, 0xdf01 },
2502                 { 0x02, 0xdf20 },
2503                 { 0x01, 0x100a },
2504                 { 0x00, 0xa0ff },
2505                 { 0x04, 0xf800 },
2506                 { 0x04, 0xf000 },
2507
2508                 { 0x1f, 0x0000 },
2509                 { 0x0b, 0x0000 },
2510                 { 0x00, 0x9200 }
2511         };
2512
2513         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2514 }
2515
2516 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
2517 {
2518         static const struct phy_reg phy_reg_init[] = {
2519                 { 0x1f, 0x0002 },
2520                 { 0x01, 0x90d0 },
2521                 { 0x1f, 0x0000 }
2522         };
2523
2524         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2525 }
2526
2527 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2528 {
2529         struct pci_dev *pdev = tp->pci_dev;
2530
2531         if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
2532             (pdev->subsystem_device != 0xe000))
2533                 return;
2534
2535         rtl_writephy(tp, 0x1f, 0x0001);
2536         rtl_writephy(tp, 0x10, 0xf01b);
2537         rtl_writephy(tp, 0x1f, 0x0000);
2538 }
2539
2540 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2541 {
2542         static const struct phy_reg phy_reg_init[] = {
2543                 { 0x1f, 0x0001 },
2544                 { 0x04, 0x0000 },
2545                 { 0x03, 0x00a1 },
2546                 { 0x02, 0x0008 },
2547                 { 0x01, 0x0120 },
2548                 { 0x00, 0x1000 },
2549                 { 0x04, 0x0800 },
2550                 { 0x04, 0x9000 },
2551                 { 0x03, 0x802f },
2552                 { 0x02, 0x4f02 },
2553                 { 0x01, 0x0409 },
2554                 { 0x00, 0xf099 },
2555                 { 0x04, 0x9800 },
2556                 { 0x04, 0xa000 },
2557                 { 0x03, 0xdf01 },
2558                 { 0x02, 0xdf20 },
2559                 { 0x01, 0xff95 },
2560                 { 0x00, 0xba00 },
2561                 { 0x04, 0xa800 },
2562                 { 0x04, 0xf000 },
2563                 { 0x03, 0xdf01 },
2564                 { 0x02, 0xdf20 },
2565                 { 0x01, 0x101a },
2566                 { 0x00, 0xa0ff },
2567                 { 0x04, 0xf800 },
2568                 { 0x04, 0x0000 },
2569                 { 0x1f, 0x0000 },
2570
2571                 { 0x1f, 0x0001 },
2572                 { 0x10, 0xf41b },
2573                 { 0x14, 0xfb54 },
2574                 { 0x18, 0xf5c7 },
2575                 { 0x1f, 0x0000 },
2576
2577                 { 0x1f, 0x0001 },
2578                 { 0x17, 0x0cc0 },
2579                 { 0x1f, 0x0000 }
2580         };
2581
2582         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2583
2584         rtl8169scd_hw_phy_config_quirk(tp);
2585 }
2586
2587 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
2588 {
2589         static const struct phy_reg phy_reg_init[] = {
2590                 { 0x1f, 0x0001 },
2591                 { 0x04, 0x0000 },
2592                 { 0x03, 0x00a1 },
2593                 { 0x02, 0x0008 },
2594                 { 0x01, 0x0120 },
2595                 { 0x00, 0x1000 },
2596                 { 0x04, 0x0800 },
2597                 { 0x04, 0x9000 },
2598                 { 0x03, 0x802f },
2599                 { 0x02, 0x4f02 },
2600                 { 0x01, 0x0409 },
2601                 { 0x00, 0xf099 },
2602                 { 0x04, 0x9800 },
2603                 { 0x04, 0xa000 },
2604                 { 0x03, 0xdf01 },
2605                 { 0x02, 0xdf20 },
2606                 { 0x01, 0xff95 },
2607                 { 0x00, 0xba00 },
2608                 { 0x04, 0xa800 },
2609                 { 0x04, 0xf000 },
2610                 { 0x03, 0xdf01 },
2611                 { 0x02, 0xdf20 },
2612                 { 0x01, 0x101a },
2613                 { 0x00, 0xa0ff },
2614                 { 0x04, 0xf800 },
2615                 { 0x04, 0x0000 },
2616                 { 0x1f, 0x0000 },
2617
2618                 { 0x1f, 0x0001 },
2619                 { 0x0b, 0x8480 },
2620                 { 0x1f, 0x0000 },
2621
2622                 { 0x1f, 0x0001 },
2623                 { 0x18, 0x67c7 },
2624                 { 0x04, 0x2000 },
2625                 { 0x03, 0x002f },
2626                 { 0x02, 0x4360 },
2627                 { 0x01, 0x0109 },
2628                 { 0x00, 0x3022 },
2629                 { 0x04, 0x2800 },
2630                 { 0x1f, 0x0000 },
2631
2632                 { 0x1f, 0x0001 },
2633                 { 0x17, 0x0cc0 },
2634                 { 0x1f, 0x0000 }
2635         };
2636
2637         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2638 }
2639
2640 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
2641 {
2642         static const struct phy_reg phy_reg_init[] = {
2643                 { 0x10, 0xf41b },
2644                 { 0x1f, 0x0000 }
2645         };
2646
2647         rtl_writephy(tp, 0x1f, 0x0001);
2648         rtl_patchphy(tp, 0x16, 1 << 0);
2649
2650         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2651 }
2652
2653 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
2654 {
2655         static const struct phy_reg phy_reg_init[] = {
2656                 { 0x1f, 0x0001 },
2657                 { 0x10, 0xf41b },
2658                 { 0x1f, 0x0000 }
2659         };
2660
2661         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2662 }
2663
2664 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
2665 {
2666         static const struct phy_reg phy_reg_init[] = {
2667                 { 0x1f, 0x0000 },
2668                 { 0x1d, 0x0f00 },
2669                 { 0x1f, 0x0002 },
2670                 { 0x0c, 0x1ec8 },
2671                 { 0x1f, 0x0000 }
2672         };
2673
2674         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2675 }
2676
2677 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
2678 {
2679         static const struct phy_reg phy_reg_init[] = {
2680                 { 0x1f, 0x0001 },
2681                 { 0x1d, 0x3d98 },
2682                 { 0x1f, 0x0000 }
2683         };
2684
2685         rtl_writephy(tp, 0x1f, 0x0000);
2686         rtl_patchphy(tp, 0x14, 1 << 5);
2687         rtl_patchphy(tp, 0x0d, 1 << 5);
2688
2689         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2690 }
2691
2692 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
2693 {
2694         static const struct phy_reg phy_reg_init[] = {
2695                 { 0x1f, 0x0001 },
2696                 { 0x12, 0x2300 },
2697                 { 0x1f, 0x0002 },
2698                 { 0x00, 0x88d4 },
2699                 { 0x01, 0x82b1 },
2700                 { 0x03, 0x7002 },
2701                 { 0x08, 0x9e30 },
2702                 { 0x09, 0x01f0 },
2703                 { 0x0a, 0x5500 },
2704                 { 0x0c, 0x00c8 },
2705                 { 0x1f, 0x0003 },
2706                 { 0x12, 0xc096 },
2707                 { 0x16, 0x000a },
2708                 { 0x1f, 0x0000 },
2709                 { 0x1f, 0x0000 },
2710                 { 0x09, 0x2000 },
2711                 { 0x09, 0x0000 }
2712         };
2713
2714         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2715
2716         rtl_patchphy(tp, 0x14, 1 << 5);
2717         rtl_patchphy(tp, 0x0d, 1 << 5);
2718         rtl_writephy(tp, 0x1f, 0x0000);
2719 }
2720
2721 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
2722 {
2723         static const struct phy_reg phy_reg_init[] = {
2724                 { 0x1f, 0x0001 },
2725                 { 0x12, 0x2300 },
2726                 { 0x03, 0x802f },
2727                 { 0x02, 0x4f02 },
2728                 { 0x01, 0x0409 },
2729                 { 0x00, 0xf099 },
2730                 { 0x04, 0x9800 },
2731                 { 0x04, 0x9000 },
2732                 { 0x1d, 0x3d98 },
2733                 { 0x1f, 0x0002 },
2734                 { 0x0c, 0x7eb8 },
2735                 { 0x06, 0x0761 },
2736                 { 0x1f, 0x0003 },
2737                 { 0x16, 0x0f0a },
2738                 { 0x1f, 0x0000 }
2739         };
2740
2741         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2742
2743         rtl_patchphy(tp, 0x16, 1 << 0);
2744         rtl_patchphy(tp, 0x14, 1 << 5);
2745         rtl_patchphy(tp, 0x0d, 1 << 5);
2746         rtl_writephy(tp, 0x1f, 0x0000);
2747 }
2748
2749 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
2750 {
2751         static const struct phy_reg phy_reg_init[] = {
2752                 { 0x1f, 0x0001 },
2753                 { 0x12, 0x2300 },
2754                 { 0x1d, 0x3d98 },
2755                 { 0x1f, 0x0002 },
2756                 { 0x0c, 0x7eb8 },
2757                 { 0x06, 0x5461 },
2758                 { 0x1f, 0x0003 },
2759                 { 0x16, 0x0f0a },
2760                 { 0x1f, 0x0000 }
2761         };
2762
2763         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2764
2765         rtl_patchphy(tp, 0x16, 1 << 0);
2766         rtl_patchphy(tp, 0x14, 1 << 5);
2767         rtl_patchphy(tp, 0x0d, 1 << 5);
2768         rtl_writephy(tp, 0x1f, 0x0000);
2769 }
2770
2771 static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
2772 {
2773         rtl8168c_3_hw_phy_config(tp);
2774 }
2775
2776 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
2777 {
2778         static const struct phy_reg phy_reg_init_0[] = {
2779                 /* Channel Estimation */
2780                 { 0x1f, 0x0001 },
2781                 { 0x06, 0x4064 },
2782                 { 0x07, 0x2863 },
2783                 { 0x08, 0x059c },
2784                 { 0x09, 0x26b4 },
2785                 { 0x0a, 0x6a19 },
2786                 { 0x0b, 0xdcc8 },
2787                 { 0x10, 0xf06d },
2788                 { 0x14, 0x7f68 },
2789                 { 0x18, 0x7fd9 },
2790                 { 0x1c, 0xf0ff },
2791                 { 0x1d, 0x3d9c },
2792                 { 0x1f, 0x0003 },
2793                 { 0x12, 0xf49f },
2794                 { 0x13, 0x070b },
2795                 { 0x1a, 0x05ad },
2796                 { 0x14, 0x94c0 },
2797
2798                 /*
2799                  * Tx Error Issue
2800                  * Enhance line driver power
2801                  */
2802                 { 0x1f, 0x0002 },
2803                 { 0x06, 0x5561 },
2804                 { 0x1f, 0x0005 },
2805                 { 0x05, 0x8332 },
2806                 { 0x06, 0x5561 },
2807
2808                 /*
2809                  * Can not link to 1Gbps with bad cable
2810                  * Decrease SNR threshold form 21.07dB to 19.04dB
2811                  */
2812                 { 0x1f, 0x0001 },
2813                 { 0x17, 0x0cc0 },
2814
2815                 { 0x1f, 0x0000 },
2816                 { 0x0d, 0xf880 }
2817         };
2818
2819         rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2820
2821         /*
2822          * Rx Error Issue
2823          * Fine Tune Switching regulator parameter
2824          */
2825         rtl_writephy(tp, 0x1f, 0x0002);
2826         rtl_w0w1_phy(tp, 0x0b, 0x0010, 0x00ef);
2827         rtl_w0w1_phy(tp, 0x0c, 0xa200, 0x5d00);
2828
2829         if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
2830                 static const struct phy_reg phy_reg_init[] = {
2831                         { 0x1f, 0x0002 },
2832                         { 0x05, 0x669a },
2833                         { 0x1f, 0x0005 },
2834                         { 0x05, 0x8330 },
2835                         { 0x06, 0x669a },
2836                         { 0x1f, 0x0002 }
2837                 };
2838                 int val;
2839
2840                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2841
2842                 val = rtl_readphy(tp, 0x0d);
2843
2844                 if ((val & 0x00ff) != 0x006c) {
2845                         static const u32 set[] = {
2846                                 0x0065, 0x0066, 0x0067, 0x0068,
2847                                 0x0069, 0x006a, 0x006b, 0x006c
2848                         };
2849                         int i;
2850
2851                         rtl_writephy(tp, 0x1f, 0x0002);
2852
2853                         val &= 0xff00;
2854                         for (i = 0; i < ARRAY_SIZE(set); i++)
2855                                 rtl_writephy(tp, 0x0d, val | set[i]);
2856                 }
2857         } else {
2858                 static const struct phy_reg phy_reg_init[] = {
2859                         { 0x1f, 0x0002 },
2860                         { 0x05, 0x6662 },
2861                         { 0x1f, 0x0005 },
2862                         { 0x05, 0x8330 },
2863                         { 0x06, 0x6662 }
2864                 };
2865
2866                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2867         }
2868
2869         /* RSET couple improve */
2870         rtl_writephy(tp, 0x1f, 0x0002);
2871         rtl_patchphy(tp, 0x0d, 0x0300);
2872         rtl_patchphy(tp, 0x0f, 0x0010);
2873
2874         /* Fine tune PLL performance */
2875         rtl_writephy(tp, 0x1f, 0x0002);
2876         rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
2877         rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
2878
2879         rtl_writephy(tp, 0x1f, 0x0005);
2880         rtl_writephy(tp, 0x05, 0x001b);
2881
2882         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
2883
2884         rtl_writephy(tp, 0x1f, 0x0000);
2885 }
2886
2887 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
2888 {
2889         static const struct phy_reg phy_reg_init_0[] = {
2890                 /* Channel Estimation */
2891                 { 0x1f, 0x0001 },
2892                 { 0x06, 0x4064 },
2893                 { 0x07, 0x2863 },
2894                 { 0x08, 0x059c },
2895                 { 0x09, 0x26b4 },
2896                 { 0x0a, 0x6a19 },
2897                 { 0x0b, 0xdcc8 },
2898                 { 0x10, 0xf06d },
2899                 { 0x14, 0x7f68 },
2900                 { 0x18, 0x7fd9 },
2901                 { 0x1c, 0xf0ff },
2902                 { 0x1d, 0x3d9c },
2903                 { 0x1f, 0x0003 },
2904                 { 0x12, 0xf49f },
2905                 { 0x13, 0x070b },
2906                 { 0x1a, 0x05ad },
2907                 { 0x14, 0x94c0 },
2908
2909                 /*
2910                  * Tx Error Issue
2911                  * Enhance line driver power
2912                  */
2913                 { 0x1f, 0x0002 },
2914                 { 0x06, 0x5561 },
2915                 { 0x1f, 0x0005 },
2916                 { 0x05, 0x8332 },
2917                 { 0x06, 0x5561 },
2918
2919                 /*
2920                  * Can not link to 1Gbps with bad cable
2921                  * Decrease SNR threshold form 21.07dB to 19.04dB
2922                  */
2923                 { 0x1f, 0x0001 },
2924                 { 0x17, 0x0cc0 },
2925
2926                 { 0x1f, 0x0000 },
2927                 { 0x0d, 0xf880 }
2928         };
2929
2930         rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2931
2932         if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
2933                 static const struct phy_reg phy_reg_init[] = {
2934                         { 0x1f, 0x0002 },
2935                         { 0x05, 0x669a },
2936                         { 0x1f, 0x0005 },
2937                         { 0x05, 0x8330 },
2938                         { 0x06, 0x669a },
2939
2940                         { 0x1f, 0x0002 }
2941                 };
2942                 int val;
2943
2944                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2945
2946                 val = rtl_readphy(tp, 0x0d);
2947                 if ((val & 0x00ff) != 0x006c) {
2948                         static const u32 set[] = {
2949                                 0x0065, 0x0066, 0x0067, 0x0068,
2950                                 0x0069, 0x006a, 0x006b, 0x006c
2951                         };
2952                         int i;
2953
2954                         rtl_writephy(tp, 0x1f, 0x0002);
2955
2956                         val &= 0xff00;
2957                         for (i = 0; i < ARRAY_SIZE(set); i++)
2958                                 rtl_writephy(tp, 0x0d, val | set[i]);
2959                 }
2960         } else {
2961                 static const struct phy_reg phy_reg_init[] = {
2962                         { 0x1f, 0x0002 },
2963                         { 0x05, 0x2642 },
2964                         { 0x1f, 0x0005 },
2965                         { 0x05, 0x8330 },
2966                         { 0x06, 0x2642 }
2967                 };
2968
2969                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2970         }
2971
2972         /* Fine tune PLL performance */
2973         rtl_writephy(tp, 0x1f, 0x0002);
2974         rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
2975         rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
2976
2977         /* Switching regulator Slew rate */
2978         rtl_writephy(tp, 0x1f, 0x0002);
2979         rtl_patchphy(tp, 0x0f, 0x0017);
2980
2981         rtl_writephy(tp, 0x1f, 0x0005);
2982         rtl_writephy(tp, 0x05, 0x001b);
2983
2984         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
2985
2986         rtl_writephy(tp, 0x1f, 0x0000);
2987 }
2988
2989 static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
2990 {
2991         static const struct phy_reg phy_reg_init[] = {
2992                 { 0x1f, 0x0002 },
2993                 { 0x10, 0x0008 },
2994                 { 0x0d, 0x006c },
2995
2996                 { 0x1f, 0x0000 },
2997                 { 0x0d, 0xf880 },
2998
2999                 { 0x1f, 0x0001 },
3000                 { 0x17, 0x0cc0 },
3001
3002                 { 0x1f, 0x0001 },
3003                 { 0x0b, 0xa4d8 },
3004                 { 0x09, 0x281c },
3005                 { 0x07, 0x2883 },
3006                 { 0x0a, 0x6b35 },
3007                 { 0x1d, 0x3da4 },
3008                 { 0x1c, 0xeffd },
3009                 { 0x14, 0x7f52 },
3010                 { 0x18, 0x7fc6 },
3011                 { 0x08, 0x0601 },
3012                 { 0x06, 0x4063 },
3013                 { 0x10, 0xf074 },
3014                 { 0x1f, 0x0003 },
3015                 { 0x13, 0x0789 },
3016                 { 0x12, 0xf4bd },
3017                 { 0x1a, 0x04fd },
3018                 { 0x14, 0x84b0 },
3019                 { 0x1f, 0x0000 },
3020                 { 0x00, 0x9200 },
3021
3022                 { 0x1f, 0x0005 },
3023                 { 0x01, 0x0340 },
3024                 { 0x1f, 0x0001 },
3025                 { 0x04, 0x4000 },
3026                 { 0x03, 0x1d21 },
3027                 { 0x02, 0x0c32 },
3028                 { 0x01, 0x0200 },
3029                 { 0x00, 0x5554 },
3030                 { 0x04, 0x4800 },
3031                 { 0x04, 0x4000 },
3032                 { 0x04, 0xf000 },
3033                 { 0x03, 0xdf01 },
3034                 { 0x02, 0xdf20 },
3035                 { 0x01, 0x101a },
3036                 { 0x00, 0xa0ff },
3037                 { 0x04, 0xf800 },
3038                 { 0x04, 0xf000 },
3039                 { 0x1f, 0x0000 },
3040
3041                 { 0x1f, 0x0007 },
3042                 { 0x1e, 0x0023 },
3043                 { 0x16, 0x0000 },
3044                 { 0x1f, 0x0000 }
3045         };
3046
3047         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3048 }
3049
3050 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
3051 {
3052         static const struct phy_reg phy_reg_init[] = {
3053                 { 0x1f, 0x0001 },
3054                 { 0x17, 0x0cc0 },
3055
3056                 { 0x1f, 0x0007 },
3057                 { 0x1e, 0x002d },
3058                 { 0x18, 0x0040 },
3059                 { 0x1f, 0x0000 }
3060         };
3061
3062         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3063         rtl_patchphy(tp, 0x0d, 1 << 5);
3064 }
3065
3066 static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
3067 {
3068         static const struct phy_reg phy_reg_init[] = {
3069                 /* Enable Delay cap */
3070                 { 0x1f, 0x0005 },
3071                 { 0x05, 0x8b80 },
3072                 { 0x06, 0xc896 },
3073                 { 0x1f, 0x0000 },
3074
3075                 /* Channel estimation fine tune */
3076                 { 0x1f, 0x0001 },
3077                 { 0x0b, 0x6c20 },
3078                 { 0x07, 0x2872 },
3079                 { 0x1c, 0xefff },
3080                 { 0x1f, 0x0003 },
3081                 { 0x14, 0x6420 },
3082                 { 0x1f, 0x0000 },
3083
3084                 /* Update PFM & 10M TX idle timer */
3085                 { 0x1f, 0x0007 },
3086                 { 0x1e, 0x002f },
3087                 { 0x15, 0x1919 },
3088                 { 0x1f, 0x0000 },
3089
3090                 { 0x1f, 0x0007 },
3091                 { 0x1e, 0x00ac },
3092                 { 0x18, 0x0006 },
3093                 { 0x1f, 0x0000 }
3094         };
3095
3096         rtl_apply_firmware(tp);
3097
3098         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3099
3100         /* DCO enable for 10M IDLE Power */
3101         rtl_writephy(tp, 0x1f, 0x0007);
3102         rtl_writephy(tp, 0x1e, 0x0023);
3103         rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
3104         rtl_writephy(tp, 0x1f, 0x0000);
3105
3106         /* For impedance matching */
3107         rtl_writephy(tp, 0x1f, 0x0002);
3108         rtl_w0w1_phy(tp, 0x08, 0x8000, 0x7f00);
3109         rtl_writephy(tp, 0x1f, 0x0000);
3110
3111         /* PHY auto speed down */
3112         rtl_writephy(tp, 0x1f, 0x0007);
3113         rtl_writephy(tp, 0x1e, 0x002d);
3114         rtl_w0w1_phy(tp, 0x18, 0x0050, 0x0000);
3115         rtl_writephy(tp, 0x1f, 0x0000);
3116         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3117
3118         rtl_writephy(tp, 0x1f, 0x0005);
3119         rtl_writephy(tp, 0x05, 0x8b86);
3120         rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3121         rtl_writephy(tp, 0x1f, 0x0000);
3122
3123         rtl_writephy(tp, 0x1f, 0x0005);
3124         rtl_writephy(tp, 0x05, 0x8b85);
3125         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
3126         rtl_writephy(tp, 0x1f, 0x0007);
3127         rtl_writephy(tp, 0x1e, 0x0020);
3128         rtl_w0w1_phy(tp, 0x15, 0x0000, 0x1100);
3129         rtl_writephy(tp, 0x1f, 0x0006);
3130         rtl_writephy(tp, 0x00, 0x5a00);
3131         rtl_writephy(tp, 0x1f, 0x0000);
3132         rtl_writephy(tp, 0x0d, 0x0007);
3133         rtl_writephy(tp, 0x0e, 0x003c);
3134         rtl_writephy(tp, 0x0d, 0x4007);
3135         rtl_writephy(tp, 0x0e, 0x0000);
3136         rtl_writephy(tp, 0x0d, 0x0000);
3137 }
3138
3139 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, u8 *addr)
3140 {
3141         const u16 w[] = {
3142                 addr[0] | (addr[1] << 8),
3143                 addr[2] | (addr[3] << 8),
3144                 addr[4] | (addr[5] << 8)
3145         };
3146         const struct exgmac_reg e[] = {
3147                 { .addr = 0xe0, ERIAR_MASK_1111, .val = w[0] | (w[1] << 16) },
3148                 { .addr = 0xe4, ERIAR_MASK_1111, .val = w[2] },
3149                 { .addr = 0xf0, ERIAR_MASK_1111, .val = w[0] << 16 },
3150                 { .addr = 0xf4, ERIAR_MASK_1111, .val = w[1] | (w[2] << 16) }
3151         };
3152
3153         rtl_write_exgmac_batch(tp, e, ARRAY_SIZE(e));
3154 }
3155
3156 static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
3157 {
3158         static const struct phy_reg phy_reg_init[] = {
3159                 /* Enable Delay cap */
3160                 { 0x1f, 0x0004 },
3161                 { 0x1f, 0x0007 },
3162                 { 0x1e, 0x00ac },
3163                 { 0x18, 0x0006 },
3164                 { 0x1f, 0x0002 },
3165                 { 0x1f, 0x0000 },
3166                 { 0x1f, 0x0000 },
3167
3168                 /* Channel estimation fine tune */
3169                 { 0x1f, 0x0003 },
3170                 { 0x09, 0xa20f },
3171                 { 0x1f, 0x0000 },
3172                 { 0x1f, 0x0000 },
3173
3174                 /* Green Setting */
3175                 { 0x1f, 0x0005 },
3176                 { 0x05, 0x8b5b },
3177                 { 0x06, 0x9222 },
3178                 { 0x05, 0x8b6d },
3179                 { 0x06, 0x8000 },
3180                 { 0x05, 0x8b76 },
3181                 { 0x06, 0x8000 },
3182                 { 0x1f, 0x0000 }
3183         };
3184
3185         rtl_apply_firmware(tp);
3186
3187         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3188
3189         /* For 4-corner performance improve */
3190         rtl_writephy(tp, 0x1f, 0x0005);
3191         rtl_writephy(tp, 0x05, 0x8b80);
3192         rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
3193         rtl_writephy(tp, 0x1f, 0x0000);
3194
3195         /* PHY auto speed down */
3196         rtl_writephy(tp, 0x1f, 0x0004);
3197         rtl_writephy(tp, 0x1f, 0x0007);
3198         rtl_writephy(tp, 0x1e, 0x002d);
3199         rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
3200         rtl_writephy(tp, 0x1f, 0x0002);
3201         rtl_writephy(tp, 0x1f, 0x0000);
3202         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3203
3204         /* improve 10M EEE waveform */
3205         rtl_writephy(tp, 0x1f, 0x0005);
3206         rtl_writephy(tp, 0x05, 0x8b86);
3207         rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3208         rtl_writephy(tp, 0x1f, 0x0000);
3209
3210         /* Improve 2-pair detection performance */
3211         rtl_writephy(tp, 0x1f, 0x0005);
3212         rtl_writephy(tp, 0x05, 0x8b85);
3213         rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3214         rtl_writephy(tp, 0x1f, 0x0000);
3215
3216         /* EEE setting */
3217         rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_1111, 0x0003, 0x0000, ERIAR_EXGMAC);
3218         rtl_writephy(tp, 0x1f, 0x0005);
3219         rtl_writephy(tp, 0x05, 0x8b85);
3220         rtl_w0w1_phy(tp, 0x06, 0x2000, 0x0000);
3221         rtl_writephy(tp, 0x1f, 0x0004);
3222         rtl_writephy(tp, 0x1f, 0x0007);
3223         rtl_writephy(tp, 0x1e, 0x0020);
3224         rtl_w0w1_phy(tp, 0x15, 0x0100, 0x0000);
3225         rtl_writephy(tp, 0x1f, 0x0002);
3226         rtl_writephy(tp, 0x1f, 0x0000);
3227         rtl_writephy(tp, 0x0d, 0x0007);
3228         rtl_writephy(tp, 0x0e, 0x003c);
3229         rtl_writephy(tp, 0x0d, 0x4007);
3230         rtl_writephy(tp, 0x0e, 0x0006);
3231         rtl_writephy(tp, 0x0d, 0x0000);
3232
3233         /* Green feature */
3234         rtl_writephy(tp, 0x1f, 0x0003);
3235         rtl_w0w1_phy(tp, 0x19, 0x0001, 0x0000);
3236         rtl_w0w1_phy(tp, 0x10, 0x0400, 0x0000);
3237         rtl_writephy(tp, 0x1f, 0x0000);
3238         rtl_writephy(tp, 0x1f, 0x0005);
3239         rtl_w0w1_phy(tp, 0x01, 0x0100, 0x0000);
3240         rtl_writephy(tp, 0x1f, 0x0000);
3241
3242         /* Broken BIOS workaround: feed GigaMAC registers with MAC address. */
3243         rtl_rar_exgmac_set(tp, tp->dev->dev_addr);
3244 }
3245
3246 static void rtl8168f_hw_phy_config(struct rtl8169_private *tp)
3247 {
3248         /* For 4-corner performance improve */
3249         rtl_writephy(tp, 0x1f, 0x0005);
3250         rtl_writephy(tp, 0x05, 0x8b80);
3251         rtl_w0w1_phy(tp, 0x06, 0x0006, 0x0000);
3252         rtl_writephy(tp, 0x1f, 0x0000);
3253
3254         /* PHY auto speed down */
3255         rtl_writephy(tp, 0x1f, 0x0007);
3256         rtl_writephy(tp, 0x1e, 0x002d);
3257         rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
3258         rtl_writephy(tp, 0x1f, 0x0000);
3259         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3260
3261         /* Improve 10M EEE waveform */
3262         rtl_writephy(tp, 0x1f, 0x0005);
3263         rtl_writephy(tp, 0x05, 0x8b86);
3264         rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3265         rtl_writephy(tp, 0x1f, 0x0000);
3266 }
3267
3268 static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp)
3269 {
3270         static const struct phy_reg phy_reg_init[] = {
3271                 /* Channel estimation fine tune */
3272                 { 0x1f, 0x0003 },
3273                 { 0x09, 0xa20f },
3274                 { 0x1f, 0x0000 },
3275
3276                 /* Modify green table for giga & fnet */
3277                 { 0x1f, 0x0005 },
3278                 { 0x05, 0x8b55 },
3279                 { 0x06, 0x0000 },
3280                 { 0x05, 0x8b5e },
3281                 { 0x06, 0x0000 },
3282                 { 0x05, 0x8b67 },
3283                 { 0x06, 0x0000 },
3284                 { 0x05, 0x8b70 },
3285                 { 0x06, 0x0000 },
3286                 { 0x1f, 0x0000 },
3287                 { 0x1f, 0x0007 },
3288                 { 0x1e, 0x0078 },
3289                 { 0x17, 0x0000 },
3290                 { 0x19, 0x00fb },
3291                 { 0x1f, 0x0000 },
3292
3293                 /* Modify green table for 10M */
3294                 { 0x1f, 0x0005 },
3295                 { 0x05, 0x8b79 },
3296                 { 0x06, 0xaa00 },
3297                 { 0x1f, 0x0000 },
3298
3299                 /* Disable hiimpedance detection (RTCT) */
3300                 { 0x1f, 0x0003 },
3301                 { 0x01, 0x328a },
3302                 { 0x1f, 0x0000 }
3303         };
3304
3305         rtl_apply_firmware(tp);
3306
3307         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3308
3309         rtl8168f_hw_phy_config(tp);
3310
3311         /* Improve 2-pair detection performance */
3312         rtl_writephy(tp, 0x1f, 0x0005);
3313         rtl_writephy(tp, 0x05, 0x8b85);
3314         rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3315         rtl_writephy(tp, 0x1f, 0x0000);
3316 }
3317
3318 static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp)
3319 {
3320         rtl_apply_firmware(tp);
3321
3322         rtl8168f_hw_phy_config(tp);
3323 }
3324
3325 static void rtl8411_hw_phy_config(struct rtl8169_private *tp)
3326 {
3327         static const struct phy_reg phy_reg_init[] = {
3328                 /* Channel estimation fine tune */
3329                 { 0x1f, 0x0003 },
3330                 { 0x09, 0xa20f },
3331                 { 0x1f, 0x0000 },
3332
3333                 /* Modify green table for giga & fnet */
3334                 { 0x1f, 0x0005 },
3335                 { 0x05, 0x8b55 },
3336                 { 0x06, 0x0000 },
3337                 { 0x05, 0x8b5e },
3338                 { 0x06, 0x0000 },
3339                 { 0x05, 0x8b67 },
3340                 { 0x06, 0x0000 },
3341                 { 0x05, 0x8b70 },
3342                 { 0x06, 0x0000 },
3343                 { 0x1f, 0x0000 },
3344                 { 0x1f, 0x0007 },
3345                 { 0x1e, 0x0078 },
3346                 { 0x17, 0x0000 },
3347                 { 0x19, 0x00aa },
3348                 { 0x1f, 0x0000 },
3349
3350                 /* Modify green table for 10M */
3351                 { 0x1f, 0x0005 },
3352                 { 0x05, 0x8b79 },
3353                 { 0x06, 0xaa00 },
3354                 { 0x1f, 0x0000 },
3355
3356                 /* Disable hiimpedance detection (RTCT) */
3357                 { 0x1f, 0x0003 },
3358                 { 0x01, 0x328a },
3359                 { 0x1f, 0x0000 }
3360         };
3361
3362
3363         rtl_apply_firmware(tp);
3364
3365         rtl8168f_hw_phy_config(tp);
3366
3367         /* Improve 2-pair detection performance */
3368         rtl_writephy(tp, 0x1f, 0x0005);
3369         rtl_writephy(tp, 0x05, 0x8b85);
3370         rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3371         rtl_writephy(tp, 0x1f, 0x0000);
3372
3373         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3374
3375         /* Modify green table for giga */
3376         rtl_writephy(tp, 0x1f, 0x0005);
3377         rtl_writephy(tp, 0x05, 0x8b54);
3378         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
3379         rtl_writephy(tp, 0x05, 0x8b5d);
3380         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
3381         rtl_writephy(tp, 0x05, 0x8a7c);
3382         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3383         rtl_writephy(tp, 0x05, 0x8a7f);
3384         rtl_w0w1_phy(tp, 0x06, 0x0100, 0x0000);
3385         rtl_writephy(tp, 0x05, 0x8a82);
3386         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3387         rtl_writephy(tp, 0x05, 0x8a85);
3388         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3389         rtl_writephy(tp, 0x05, 0x8a88);
3390         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3391         rtl_writephy(tp, 0x1f, 0x0000);
3392
3393         /* uc same-seed solution */
3394         rtl_writephy(tp, 0x1f, 0x0005);
3395         rtl_writephy(tp, 0x05, 0x8b85);
3396         rtl_w0w1_phy(tp, 0x06, 0x8000, 0x0000);
3397         rtl_writephy(tp, 0x1f, 0x0000);
3398
3399         /* eee setting */
3400         rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x00, 0x03, ERIAR_EXGMAC);
3401         rtl_writephy(tp, 0x1f, 0x0005);
3402         rtl_writephy(tp, 0x05, 0x8b85);
3403         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
3404         rtl_writephy(tp, 0x1f, 0x0004);
3405         rtl_writephy(tp, 0x1f, 0x0007);
3406         rtl_writephy(tp, 0x1e, 0x0020);
3407         rtl_w0w1_phy(tp, 0x15, 0x0000, 0x0100);
3408         rtl_writephy(tp, 0x1f, 0x0000);
3409         rtl_writephy(tp, 0x0d, 0x0007);
3410         rtl_writephy(tp, 0x0e, 0x003c);
3411         rtl_writephy(tp, 0x0d, 0x4007);
3412         rtl_writephy(tp, 0x0e, 0x0000);
3413         rtl_writephy(tp, 0x0d, 0x0000);
3414
3415         /* Green feature */
3416         rtl_writephy(tp, 0x1f, 0x0003);
3417         rtl_w0w1_phy(tp, 0x19, 0x0000, 0x0001);
3418         rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0400);
3419         rtl_writephy(tp, 0x1f, 0x0000);
3420 }
3421
3422 static void rtl8168g_1_hw_phy_config(struct rtl8169_private *tp)
3423 {
3424         rtl_apply_firmware(tp);
3425
3426         rtl_writephy(tp, 0x1f, 0x0a46);
3427         if (rtl_readphy(tp, 0x10) & 0x0100) {
3428                 rtl_writephy(tp, 0x1f, 0x0bcc);
3429                 rtl_w0w1_phy(tp, 0x12, 0x0000, 0x8000);
3430         } else {
3431                 rtl_writephy(tp, 0x1f, 0x0bcc);
3432                 rtl_w0w1_phy(tp, 0x12, 0x8000, 0x0000);
3433         }
3434
3435         rtl_writephy(tp, 0x1f, 0x0a46);
3436         if (rtl_readphy(tp, 0x13) & 0x0100) {
3437                 rtl_writephy(tp, 0x1f, 0x0c41);
3438                 rtl_w0w1_phy(tp, 0x15, 0x0002, 0x0000);
3439         } else {
3440                 rtl_writephy(tp, 0x1f, 0x0c41);
3441                 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x0002);
3442         }
3443
3444         /* Enable PHY auto speed down */
3445         rtl_writephy(tp, 0x1f, 0x0a44);
3446         rtl_w0w1_phy(tp, 0x11, 0x000c, 0x0000);
3447
3448         rtl_writephy(tp, 0x1f, 0x0bcc);
3449         rtl_w0w1_phy(tp, 0x14, 0x0100, 0x0000);
3450         rtl_writephy(tp, 0x1f, 0x0a44);
3451         rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
3452         rtl_writephy(tp, 0x1f, 0x0a43);
3453         rtl_writephy(tp, 0x13, 0x8084);
3454         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
3455         rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
3456
3457         /* EEE auto-fallback function */
3458         rtl_writephy(tp, 0x1f, 0x0a4b);
3459         rtl_w0w1_phy(tp, 0x11, 0x0004, 0x0000);
3460
3461         /* Enable UC LPF tune function */
3462         rtl_writephy(tp, 0x1f, 0x0a43);
3463         rtl_writephy(tp, 0x13, 0x8012);
3464         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3465
3466         rtl_writephy(tp, 0x1f, 0x0c42);
3467         rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
3468
3469         /* Improve SWR Efficiency */
3470         rtl_writephy(tp, 0x1f, 0x0bcd);
3471         rtl_writephy(tp, 0x14, 0x5065);
3472         rtl_writephy(tp, 0x14, 0xd065);
3473         rtl_writephy(tp, 0x1f, 0x0bc8);
3474         rtl_writephy(tp, 0x11, 0x5655);
3475         rtl_writephy(tp, 0x1f, 0x0bcd);
3476         rtl_writephy(tp, 0x14, 0x1065);
3477         rtl_writephy(tp, 0x14, 0x9065);
3478         rtl_writephy(tp, 0x14, 0x1065);
3479
3480         /* Check ALDPS bit, disable it if enabled */
3481         rtl_writephy(tp, 0x1f, 0x0a43);
3482         if (rtl_readphy(tp, 0x10) & 0x0004)
3483                 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
3484
3485         rtl_writephy(tp, 0x1f, 0x0000);
3486 }
3487
3488 static void rtl8168g_2_hw_phy_config(struct rtl8169_private *tp)
3489 {
3490         rtl_apply_firmware(tp);
3491 }
3492
3493 static void rtl8168h_1_hw_phy_config(struct rtl8169_private *tp)
3494 {
3495         u16 dout_tapbin;
3496         u32 data;
3497
3498         rtl_apply_firmware(tp);
3499
3500         /* CHN EST parameters adjust - giga master */
3501         rtl_writephy(tp, 0x1f, 0x0a43);
3502         rtl_writephy(tp, 0x13, 0x809b);
3503         rtl_w0w1_phy(tp, 0x14, 0x8000, 0xf800);
3504         rtl_writephy(tp, 0x13, 0x80a2);
3505         rtl_w0w1_phy(tp, 0x14, 0x8000, 0xff00);
3506         rtl_writephy(tp, 0x13, 0x80a4);
3507         rtl_w0w1_phy(tp, 0x14, 0x8500, 0xff00);
3508         rtl_writephy(tp, 0x13, 0x809c);
3509         rtl_w0w1_phy(tp, 0x14, 0xbd00, 0xff00);
3510         rtl_writephy(tp, 0x1f, 0x0000);
3511
3512         /* CHN EST parameters adjust - giga slave */
3513         rtl_writephy(tp, 0x1f, 0x0a43);
3514         rtl_writephy(tp, 0x13, 0x80ad);
3515         rtl_w0w1_phy(tp, 0x14, 0x7000, 0xf800);
3516         rtl_writephy(tp, 0x13, 0x80b4);
3517         rtl_w0w1_phy(tp, 0x14, 0x5000, 0xff00);
3518         rtl_writephy(tp, 0x13, 0x80ac);
3519         rtl_w0w1_phy(tp, 0x14, 0x4000, 0xff00);
3520         rtl_writephy(tp, 0x1f, 0x0000);
3521
3522         /* CHN EST parameters adjust - fnet */
3523         rtl_writephy(tp, 0x1f, 0x0a43);
3524         rtl_writephy(tp, 0x13, 0x808e);
3525         rtl_w0w1_phy(tp, 0x14, 0x1200, 0xff00);
3526         rtl_writephy(tp, 0x13, 0x8090);
3527         rtl_w0w1_phy(tp, 0x14, 0xe500, 0xff00);
3528         rtl_writephy(tp, 0x13, 0x8092);
3529         rtl_w0w1_phy(tp, 0x14, 0x9f00, 0xff00);
3530         rtl_writephy(tp, 0x1f, 0x0000);
3531
3532         /* enable R-tune & PGA-retune function */
3533         dout_tapbin = 0;
3534         rtl_writephy(tp, 0x1f, 0x0a46);
3535         data = rtl_readphy(tp, 0x13);
3536         data &= 3;
3537         data <<= 2;
3538         dout_tapbin |= data;
3539         data = rtl_readphy(tp, 0x12);
3540         data &= 0xc000;
3541         data >>= 14;
3542         dout_tapbin |= data;
3543         dout_tapbin = ~(dout_tapbin^0x08);
3544         dout_tapbin <<= 12;
3545         dout_tapbin &= 0xf000;
3546         rtl_writephy(tp, 0x1f, 0x0a43);
3547         rtl_writephy(tp, 0x13, 0x827a);
3548         rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3549         rtl_writephy(tp, 0x13, 0x827b);
3550         rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3551         rtl_writephy(tp, 0x13, 0x827c);
3552         rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3553         rtl_writephy(tp, 0x13, 0x827d);
3554         rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3555
3556         rtl_writephy(tp, 0x1f, 0x0a43);
3557         rtl_writephy(tp, 0x13, 0x0811);
3558         rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
3559         rtl_writephy(tp, 0x1f, 0x0a42);
3560         rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
3561         rtl_writephy(tp, 0x1f, 0x0000);
3562
3563         /* enable GPHY 10M */
3564         rtl_writephy(tp, 0x1f, 0x0a44);
3565         rtl_w0w1_phy(tp, 0x11, 0x0800, 0x0000);
3566         rtl_writephy(tp, 0x1f, 0x0000);
3567
3568         /* SAR ADC performance */
3569         rtl_writephy(tp, 0x1f, 0x0bca);
3570         rtl_w0w1_phy(tp, 0x17, 0x4000, 0x3000);
3571         rtl_writephy(tp, 0x1f, 0x0000);
3572
3573         rtl_writephy(tp, 0x1f, 0x0a43);
3574         rtl_writephy(tp, 0x13, 0x803f);
3575         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3576         rtl_writephy(tp, 0x13, 0x8047);
3577         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3578         rtl_writephy(tp, 0x13, 0x804f);
3579         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3580         rtl_writephy(tp, 0x13, 0x8057);
3581         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3582         rtl_writephy(tp, 0x13, 0x805f);
3583         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3584         rtl_writephy(tp, 0x13, 0x8067);
3585         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3586         rtl_writephy(tp, 0x13, 0x806f);
3587         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3588         rtl_writephy(tp, 0x1f, 0x0000);
3589
3590         /* disable phy pfm mode */
3591         rtl_writephy(tp, 0x1f, 0x0a44);
3592         rtl_w0w1_phy(tp, 0x11, 0x0000, 0x0080);
3593         rtl_writephy(tp, 0x1f, 0x0000);
3594
3595         /* Check ALDPS bit, disable it if enabled */
3596         rtl_writephy(tp, 0x1f, 0x0a43);
3597         if (rtl_readphy(tp, 0x10) & 0x0004)
3598                 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
3599
3600         rtl_writephy(tp, 0x1f, 0x0000);
3601 }
3602
3603 static void rtl8168h_2_hw_phy_config(struct rtl8169_private *tp)
3604 {
3605         u16 ioffset_p3, ioffset_p2, ioffset_p1, ioffset_p0;
3606         u16 rlen;
3607         u32 data;
3608
3609         rtl_apply_firmware(tp);
3610
3611         /* CHIN EST parameter update */
3612         rtl_writephy(tp, 0x1f, 0x0a43);
3613         rtl_writephy(tp, 0x13, 0x808a);
3614         rtl_w0w1_phy(tp, 0x14, 0x000a, 0x003f);
3615         rtl_writephy(tp, 0x1f, 0x0000);
3616
3617         /* enable R-tune & PGA-retune function */
3618         rtl_writephy(tp, 0x1f, 0x0a43);
3619         rtl_writephy(tp, 0x13, 0x0811);
3620         rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
3621         rtl_writephy(tp, 0x1f, 0x0a42);
3622         rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
3623         rtl_writephy(tp, 0x1f, 0x0000);
3624
3625         /* enable GPHY 10M */
3626         rtl_writephy(tp, 0x1f, 0x0a44);
3627         rtl_w0w1_phy(tp, 0x11, 0x0800, 0x0000);
3628         rtl_writephy(tp, 0x1f, 0x0000);
3629
3630         r8168_mac_ocp_write(tp, 0xdd02, 0x807d);
3631         data = r8168_mac_ocp_read(tp, 0xdd02);
3632         ioffset_p3 = ((data & 0x80)>>7);
3633         ioffset_p3 <<= 3;
3634
3635         data = r8168_mac_ocp_read(tp, 0xdd00);
3636         ioffset_p3 |= ((data & (0xe000))>>13);
3637         ioffset_p2 = ((data & (0x1e00))>>9);
3638         ioffset_p1 = ((data & (0x01e0))>>5);
3639         ioffset_p0 = ((data & 0x0010)>>4);
3640         ioffset_p0 <<= 3;
3641         ioffset_p0 |= (data & (0x07));
3642         data = (ioffset_p3<<12)|(ioffset_p2<<8)|(ioffset_p1<<4)|(ioffset_p0);
3643
3644         if ((ioffset_p3 != 0x0f) || (ioffset_p2 != 0x0f) ||
3645             (ioffset_p1 != 0x0f) || (ioffset_p0 != 0x0f)) {
3646                 rtl_writephy(tp, 0x1f, 0x0bcf);
3647                 rtl_writephy(tp, 0x16, data);
3648                 rtl_writephy(tp, 0x1f, 0x0000);
3649         }
3650
3651         /* Modify rlen (TX LPF corner frequency) level */
3652         rtl_writephy(tp, 0x1f, 0x0bcd);
3653         data = rtl_readphy(tp, 0x16);
3654         data &= 0x000f;
3655         rlen = 0;
3656         if (data > 3)
3657                 rlen = data - 3;
3658         data = rlen | (rlen<<4) | (rlen<<8) | (rlen<<12);
3659         rtl_writephy(tp, 0x17, data);
3660         rtl_writephy(tp, 0x1f, 0x0bcd);
3661         rtl_writephy(tp, 0x1f, 0x0000);
3662
3663         /* disable phy pfm mode */
3664         rtl_writephy(tp, 0x1f, 0x0a44);
3665         rtl_w0w1_phy(tp, 0x11, 0x0000, 0x0080);
3666         rtl_writephy(tp, 0x1f, 0x0000);
3667
3668         /* Check ALDPS bit, disable it if enabled */
3669         rtl_writephy(tp, 0x1f, 0x0a43);
3670         if (rtl_readphy(tp, 0x10) & 0x0004)
3671                 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
3672
3673         rtl_writephy(tp, 0x1f, 0x0000);
3674 }
3675
3676 static void rtl8168ep_1_hw_phy_config(struct rtl8169_private *tp)
3677 {
3678         /* Enable PHY auto speed down */
3679         rtl_writephy(tp, 0x1f, 0x0a44);
3680         rtl_w0w1_phy(tp, 0x11, 0x000c, 0x0000);
3681         rtl_writephy(tp, 0x1f, 0x0000);
3682
3683         /* patch 10M & ALDPS */
3684         rtl_writephy(tp, 0x1f, 0x0bcc);
3685         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x0100);
3686         rtl_writephy(tp, 0x1f, 0x0a44);
3687         rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
3688         rtl_writephy(tp, 0x1f, 0x0a43);
3689         rtl_writephy(tp, 0x13, 0x8084);
3690         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
3691         rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
3692         rtl_writephy(tp, 0x1f, 0x0000);
3693
3694         /* Enable EEE auto-fallback function */
3695         rtl_writephy(tp, 0x1f, 0x0a4b);
3696         rtl_w0w1_phy(tp, 0x11, 0x0004, 0x0000);
3697         rtl_writephy(tp, 0x1f, 0x0000);
3698
3699         /* Enable UC LPF tune function */
3700         rtl_writephy(tp, 0x1f, 0x0a43);
3701         rtl_writephy(tp, 0x13, 0x8012);
3702         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3703         rtl_writephy(tp, 0x1f, 0x0000);
3704
3705         /* set rg_sel_sdm_rate */
3706         rtl_writephy(tp, 0x1f, 0x0c42);
3707         rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
3708         rtl_writephy(tp, 0x1f, 0x0000);
3709
3710         /* Check ALDPS bit, disable it if enabled */
3711         rtl_writephy(tp, 0x1f, 0x0a43);
3712         if (rtl_readphy(tp, 0x10) & 0x0004)
3713                 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
3714
3715         rtl_writephy(tp, 0x1f, 0x0000);
3716 }
3717
3718 static void rtl8168ep_2_hw_phy_config(struct rtl8169_private *tp)
3719 {
3720         /* patch 10M & ALDPS */
3721         rtl_writephy(tp, 0x1f, 0x0bcc);
3722         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x0100);
3723         rtl_writephy(tp, 0x1f, 0x0a44);
3724         rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
3725         rtl_writephy(tp, 0x1f, 0x0a43);
3726         rtl_writephy(tp, 0x13, 0x8084);
3727         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
3728         rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
3729         rtl_writephy(tp, 0x1f, 0x0000);
3730
3731         /* Enable UC LPF tune function */
3732         rtl_writephy(tp, 0x1f, 0x0a43);
3733         rtl_writephy(tp, 0x13, 0x8012);
3734         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3735         rtl_writephy(tp, 0x1f, 0x0000);
3736
3737         /* Set rg_sel_sdm_rate */
3738         rtl_writephy(tp, 0x1f, 0x0c42);
3739         rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
3740         rtl_writephy(tp, 0x1f, 0x0000);
3741
3742         /* Channel estimation parameters */
3743         rtl_writephy(tp, 0x1f, 0x0a43);
3744         rtl_writephy(tp, 0x13, 0x80f3);
3745         rtl_w0w1_phy(tp, 0x14, 0x8b00, ~0x8bff);
3746         rtl_writephy(tp, 0x13, 0x80f0);
3747         rtl_w0w1_phy(tp, 0x14, 0x3a00, ~0x3aff);
3748         rtl_writephy(tp, 0x13, 0x80ef);
3749         rtl_w0w1_phy(tp, 0x14, 0x0500, ~0x05ff);
3750         rtl_writephy(tp, 0x13, 0x80f6);
3751         rtl_w0w1_phy(tp, 0x14, 0x6e00, ~0x6eff);
3752         rtl_writephy(tp, 0x13, 0x80ec);
3753         rtl_w0w1_phy(tp, 0x14, 0x6800, ~0x68ff);
3754         rtl_writephy(tp, 0x13, 0x80ed);
3755         rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
3756         rtl_writephy(tp, 0x13, 0x80f2);
3757         rtl_w0w1_phy(tp, 0x14, 0xf400, ~0xf4ff);
3758         rtl_writephy(tp, 0x13, 0x80f4);
3759         rtl_w0w1_phy(tp, 0x14, 0x8500, ~0x85ff);
3760         rtl_writephy(tp, 0x1f, 0x0a43);
3761         rtl_writephy(tp, 0x13, 0x8110);
3762         rtl_w0w1_phy(tp, 0x14, 0xa800, ~0xa8ff);
3763         rtl_writephy(tp, 0x13, 0x810f);
3764         rtl_w0w1_phy(tp, 0x14, 0x1d00, ~0x1dff);
3765         rtl_writephy(tp, 0x13, 0x8111);
3766         rtl_w0w1_phy(tp, 0x14, 0xf500, ~0xf5ff);
3767         rtl_writephy(tp, 0x13, 0x8113);
3768         rtl_w0w1_phy(tp, 0x14, 0x6100, ~0x61ff);
3769         rtl_writephy(tp, 0x13, 0x8115);
3770         rtl_w0w1_phy(tp, 0x14, 0x9200, ~0x92ff);
3771         rtl_writephy(tp, 0x13, 0x810e);
3772         rtl_w0w1_phy(tp, 0x14, 0x0400, ~0x04ff);
3773         rtl_writephy(tp, 0x13, 0x810c);
3774         rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
3775         rtl_writephy(tp, 0x13, 0x810b);
3776         rtl_w0w1_phy(tp, 0x14, 0x5a00, ~0x5aff);
3777         rtl_writephy(tp, 0x1f, 0x0a43);
3778         rtl_writephy(tp, 0x13, 0x80d1);
3779         rtl_w0w1_phy(tp, 0x14, 0xff00, ~0xffff);
3780         rtl_writephy(tp, 0x13, 0x80cd);
3781         rtl_w0w1_phy(tp, 0x14, 0x9e00, ~0x9eff);
3782         rtl_writephy(tp, 0x13, 0x80d3);
3783         rtl_w0w1_phy(tp, 0x14, 0x0e00, ~0x0eff);
3784         rtl_writephy(tp, 0x13, 0x80d5);
3785         rtl_w0w1_phy(tp, 0x14, 0xca00, ~0xcaff);
3786         rtl_writephy(tp, 0x13, 0x80d7);
3787         rtl_w0w1_phy(tp, 0x14, 0x8400, ~0x84ff);
3788
3789         /* Force PWM-mode */
3790         rtl_writephy(tp, 0x1f, 0x0bcd);
3791         rtl_writephy(tp, 0x14, 0x5065);
3792         rtl_writephy(tp, 0x14, 0xd065);
3793         rtl_writephy(tp, 0x1f, 0x0bc8);
3794         rtl_writephy(tp, 0x12, 0x00ed);
3795         rtl_writephy(tp, 0x1f, 0x0bcd);
3796         rtl_writephy(tp, 0x14, 0x1065);
3797         rtl_writephy(tp, 0x14, 0x9065);
3798         rtl_writephy(tp, 0x14, 0x1065);
3799         rtl_writephy(tp, 0x1f, 0x0000);
3800
3801         /* Check ALDPS bit, disable it if enabled */
3802         rtl_writephy(tp, 0x1f, 0x0a43);
3803         if (rtl_readphy(tp, 0x10) & 0x0004)
3804                 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
3805
3806         rtl_writephy(tp, 0x1f, 0x0000);
3807 }
3808
3809 static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
3810 {
3811         static const struct phy_reg phy_reg_init[] = {
3812                 { 0x1f, 0x0003 },
3813                 { 0x08, 0x441d },
3814                 { 0x01, 0x9100 },
3815                 { 0x1f, 0x0000 }
3816         };
3817
3818         rtl_writephy(tp, 0x1f, 0x0000);
3819         rtl_patchphy(tp, 0x11, 1 << 12);
3820         rtl_patchphy(tp, 0x19, 1 << 13);
3821         rtl_patchphy(tp, 0x10, 1 << 15);
3822
3823         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3824 }
3825
3826 static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
3827 {
3828         static const struct phy_reg phy_reg_init[] = {
3829                 { 0x1f, 0x0005 },
3830                 { 0x1a, 0x0000 },
3831                 { 0x1f, 0x0000 },
3832
3833                 { 0x1f, 0x0004 },
3834                 { 0x1c, 0x0000 },
3835                 { 0x1f, 0x0000 },
3836
3837                 { 0x1f, 0x0001 },
3838                 { 0x15, 0x7701 },
3839                 { 0x1f, 0x0000 }
3840         };
3841
3842         /* Disable ALDPS before ram code */
3843         rtl_writephy(tp, 0x1f, 0x0000);
3844         rtl_writephy(tp, 0x18, 0x0310);
3845         msleep(100);
3846
3847         rtl_apply_firmware(tp);
3848
3849         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3850 }
3851
3852 static void rtl8402_hw_phy_config(struct rtl8169_private *tp)
3853 {
3854         /* Disable ALDPS before setting firmware */
3855         rtl_writephy(tp, 0x1f, 0x0000);
3856         rtl_writephy(tp, 0x18, 0x0310);
3857         msleep(20);
3858
3859         rtl_apply_firmware(tp);
3860
3861         /* EEE setting */
3862         rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
3863         rtl_writephy(tp, 0x1f, 0x0004);
3864         rtl_writephy(tp, 0x10, 0x401f);
3865         rtl_writephy(tp, 0x19, 0x7030);
3866         rtl_writephy(tp, 0x1f, 0x0000);
3867 }
3868
3869 static void rtl8106e_hw_phy_config(struct rtl8169_private *tp)
3870 {
3871         static const struct phy_reg phy_reg_init[] = {
3872                 { 0x1f, 0x0004 },
3873                 { 0x10, 0xc07f },
3874                 { 0x19, 0x7030 },
3875                 { 0x1f, 0x0000 }
3876         };
3877
3878         /* Disable ALDPS before ram code */
3879         rtl_writephy(tp, 0x1f, 0x0000);
3880         rtl_writephy(tp, 0x18, 0x0310);
3881         msleep(100);
3882
3883         rtl_apply_firmware(tp);
3884
3885         rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
3886         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3887
3888         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
3889 }
3890
3891 static void rtl_hw_phy_config(struct net_device *dev)
3892 {
3893         struct rtl8169_private *tp = netdev_priv(dev);
3894
3895         switch (tp->mac_version) {
3896         case RTL_GIGA_MAC_VER_01:
3897                 break;
3898         case RTL_GIGA_MAC_VER_02:
3899         case RTL_GIGA_MAC_VER_03:
3900                 rtl8169s_hw_phy_config(tp);
3901                 break;
3902         case RTL_GIGA_MAC_VER_04:
3903                 rtl8169sb_hw_phy_config(tp);
3904                 break;
3905         case RTL_GIGA_MAC_VER_05:
3906                 rtl8169scd_hw_phy_config(tp);
3907                 break;
3908         case RTL_GIGA_MAC_VER_06:
3909                 rtl8169sce_hw_phy_config(tp);
3910                 break;
3911         case RTL_GIGA_MAC_VER_07:
3912         case RTL_GIGA_MAC_VER_08:
3913         case RTL_GIGA_MAC_VER_09:
3914                 rtl8102e_hw_phy_config(tp);
3915                 break;
3916         case RTL_GIGA_MAC_VER_11:
3917                 rtl8168bb_hw_phy_config(tp);
3918                 break;
3919         case RTL_GIGA_MAC_VER_12:
3920                 rtl8168bef_hw_phy_config(tp);
3921                 break;
3922         case RTL_GIGA_MAC_VER_17:
3923                 rtl8168bef_hw_phy_config(tp);
3924                 break;
3925         case RTL_GIGA_MAC_VER_18:
3926                 rtl8168cp_1_hw_phy_config(tp);
3927                 break;
3928         case RTL_GIGA_MAC_VER_19:
3929                 rtl8168c_1_hw_phy_config(tp);
3930                 break;
3931         case RTL_GIGA_MAC_VER_20:
3932                 rtl8168c_2_hw_phy_config(tp);
3933                 break;
3934         case RTL_GIGA_MAC_VER_21:
3935                 rtl8168c_3_hw_phy_config(tp);
3936                 break;
3937         case RTL_GIGA_MAC_VER_22:
3938                 rtl8168c_4_hw_phy_config(tp);
3939                 break;
3940         case RTL_GIGA_MAC_VER_23:
3941         case RTL_GIGA_MAC_VER_24:
3942                 rtl8168cp_2_hw_phy_config(tp);
3943                 break;
3944         case RTL_GIGA_MAC_VER_25:
3945                 rtl8168d_1_hw_phy_config(tp);
3946                 break;
3947         case RTL_GIGA_MAC_VER_26:
3948                 rtl8168d_2_hw_phy_config(tp);
3949                 break;
3950         case RTL_GIGA_MAC_VER_27:
3951                 rtl8168d_3_hw_phy_config(tp);
3952                 break;
3953         case RTL_GIGA_MAC_VER_28:
3954                 rtl8168d_4_hw_phy_config(tp);
3955                 break;
3956         case RTL_GIGA_MAC_VER_29:
3957         case RTL_GIGA_MAC_VER_30:
3958                 rtl8105e_hw_phy_config(tp);
3959                 break;
3960         case RTL_GIGA_MAC_VER_31:
3961                 /* None. */
3962                 break;
3963         case RTL_GIGA_MAC_VER_32:
3964         case RTL_GIGA_MAC_VER_33:
3965                 rtl8168e_1_hw_phy_config(tp);
3966                 break;
3967         case RTL_GIGA_MAC_VER_34:
3968                 rtl8168e_2_hw_phy_config(tp);
3969                 break;
3970         case RTL_GIGA_MAC_VER_35:
3971                 rtl8168f_1_hw_phy_config(tp);
3972                 break;
3973         case RTL_GIGA_MAC_VER_36:
3974                 rtl8168f_2_hw_phy_config(tp);
3975                 break;
3976
3977         case RTL_GIGA_MAC_VER_37:
3978                 rtl8402_hw_phy_config(tp);
3979                 break;
3980
3981         case RTL_GIGA_MAC_VER_38:
3982                 rtl8411_hw_phy_config(tp);
3983                 break;
3984
3985         case RTL_GIGA_MAC_VER_39:
3986                 rtl8106e_hw_phy_config(tp);
3987                 break;
3988
3989         case RTL_GIGA_MAC_VER_40:
3990                 rtl8168g_1_hw_phy_config(tp);
3991                 break;
3992         case RTL_GIGA_MAC_VER_42:
3993         case RTL_GIGA_MAC_VER_43:
3994         case RTL_GIGA_MAC_VER_44:
3995                 rtl8168g_2_hw_phy_config(tp);
3996                 break;
3997         case RTL_GIGA_MAC_VER_45:
3998         case RTL_GIGA_MAC_VER_47:
3999                 rtl8168h_1_hw_phy_config(tp);
4000                 break;
4001         case RTL_GIGA_MAC_VER_46:
4002         case RTL_GIGA_MAC_VER_48:
4003                 rtl8168h_2_hw_phy_config(tp);
4004                 break;
4005
4006         case RTL_GIGA_MAC_VER_49:
4007                 rtl8168ep_1_hw_phy_config(tp);
4008                 break;
4009         case RTL_GIGA_MAC_VER_50:
4010         case RTL_GIGA_MAC_VER_51:
4011                 rtl8168ep_2_hw_phy_config(tp);
4012                 break;
4013
4014         case RTL_GIGA_MAC_VER_41:
4015         default:
4016                 break;
4017         }
4018 }
4019
4020 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
4021 {
4022         if (!test_and_set_bit(flag, tp->wk.flags))
4023                 schedule_work(&tp->wk.work);
4024 }
4025
4026 static bool rtl_tbi_enabled(struct rtl8169_private *tp)
4027 {
4028         return (tp->mac_version == RTL_GIGA_MAC_VER_01) &&
4029                (RTL_R8(tp, PHYstatus) & TBI_Enable);
4030 }
4031
4032 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
4033 {
4034         rtl_hw_phy_config(dev);
4035
4036         if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
4037                 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
4038                 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4039                 netif_dbg(tp, drv, dev,
4040                           "Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
4041                 RTL_W8(tp, 0x82, 0x01);
4042         }
4043
4044         /* We may have called phy_speed_down before */
4045         phy_speed_up(dev->phydev);
4046
4047         genphy_soft_reset(dev->phydev);
4048
4049         /* It was reported that several chips end up with 10MBit/Half on a
4050          * 1GBit link after resuming from S3. For whatever reason the PHY on
4051          * these chips doesn't properly start a renegotiation when soft-reset.
4052          * Explicitly requesting a renegotiation fixes this.
4053          */
4054         if (dev->phydev->autoneg == AUTONEG_ENABLE)
4055                 phy_restart_aneg(dev->phydev);
4056 }
4057
4058 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
4059 {
4060         rtl_lock_work(tp);
4061
4062         RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
4063
4064         RTL_W32(tp, MAC4, addr[4] | addr[5] << 8);
4065         RTL_R32(tp, MAC4);
4066
4067         RTL_W32(tp, MAC0, addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24);
4068         RTL_R32(tp, MAC0);
4069
4070         if (tp->mac_version == RTL_GIGA_MAC_VER_34)
4071                 rtl_rar_exgmac_set(tp, addr);
4072
4073         RTL_W8(tp, Cfg9346, Cfg9346_Lock);
4074
4075         rtl_unlock_work(tp);
4076 }
4077
4078 static int rtl_set_mac_address(struct net_device *dev, void *p)
4079 {
4080         struct rtl8169_private *tp = netdev_priv(dev);
4081         struct device *d = tp_to_dev(tp);
4082         int ret;
4083
4084         ret = eth_mac_addr(dev, p);
4085         if (ret)
4086                 return ret;
4087
4088         pm_runtime_get_noresume(d);
4089
4090         if (pm_runtime_active(d))
4091                 rtl_rar_set(tp, dev->dev_addr);
4092
4093         pm_runtime_put_noidle(d);
4094
4095         return 0;
4096 }
4097
4098 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
4099 {
4100         if (!netif_running(dev))
4101                 return -ENODEV;
4102
4103         return phy_mii_ioctl(dev->phydev, ifr, cmd);
4104 }
4105
4106 static void rtl_init_mdio_ops(struct rtl8169_private *tp)
4107 {
4108         struct mdio_ops *ops = &tp->mdio_ops;
4109
4110         switch (tp->mac_version) {
4111         case RTL_GIGA_MAC_VER_27:
4112                 ops->write      = r8168dp_1_mdio_write;
4113                 ops->read       = r8168dp_1_mdio_read;
4114                 break;
4115         case RTL_GIGA_MAC_VER_28:
4116         case RTL_GIGA_MAC_VER_31:
4117                 ops->write      = r8168dp_2_mdio_write;
4118                 ops->read       = r8168dp_2_mdio_read;
4119                 break;
4120         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
4121                 ops->write      = r8168g_mdio_write;
4122                 ops->read       = r8168g_mdio_read;
4123                 break;
4124         default:
4125                 ops->write      = r8169_mdio_write;
4126                 ops->read       = r8169_mdio_read;
4127                 break;
4128         }
4129 }
4130
4131 static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
4132 {
4133         switch (tp->mac_version) {
4134         case RTL_GIGA_MAC_VER_25:
4135         case RTL_GIGA_MAC_VER_26:
4136         case RTL_GIGA_MAC_VER_29:
4137         case RTL_GIGA_MAC_VER_30:
4138         case RTL_GIGA_MAC_VER_32:
4139         case RTL_GIGA_MAC_VER_33:
4140         case RTL_GIGA_MAC_VER_34:
4141         case RTL_GIGA_MAC_VER_37 ... RTL_GIGA_MAC_VER_51:
4142                 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) |
4143                         AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
4144                 break;
4145         default:
4146                 break;
4147         }
4148 }
4149
4150 static bool rtl_wol_pll_power_down(struct rtl8169_private *tp)
4151 {
4152         struct phy_device *phydev;
4153
4154         if (!__rtl8169_get_wol(tp))
4155                 return false;
4156
4157         /* phydev may not be attached to netdevice */
4158         phydev = mdiobus_get_phy(tp->mii_bus, 0);
4159
4160         phy_speed_down(phydev, false);
4161         rtl_wol_suspend_quirk(tp);
4162
4163         return true;
4164 }
4165
4166 static void r8168_pll_power_down(struct rtl8169_private *tp)
4167 {
4168         if (r8168_check_dash(tp))
4169                 return;
4170
4171         if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
4172             tp->mac_version == RTL_GIGA_MAC_VER_33)
4173                 rtl_ephy_write(tp, 0x19, 0xff64);
4174
4175         if (rtl_wol_pll_power_down(tp))
4176                 return;
4177
4178         switch (tp->mac_version) {
4179         case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_33:
4180         case RTL_GIGA_MAC_VER_37:
4181         case RTL_GIGA_MAC_VER_39:
4182         case RTL_GIGA_MAC_VER_43:
4183         case RTL_GIGA_MAC_VER_44:
4184         case RTL_GIGA_MAC_VER_45:
4185         case RTL_GIGA_MAC_VER_46:
4186         case RTL_GIGA_MAC_VER_47:
4187         case RTL_GIGA_MAC_VER_48:
4188         case RTL_GIGA_MAC_VER_50:
4189         case RTL_GIGA_MAC_VER_51:
4190                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80);
4191                 break;
4192         case RTL_GIGA_MAC_VER_40:
4193         case RTL_GIGA_MAC_VER_41:
4194         case RTL_GIGA_MAC_VER_49:
4195                 rtl_w0w1_eri(tp, 0x1a8, ERIAR_MASK_1111, 0x00000000,
4196                              0xfc000000, ERIAR_EXGMAC);
4197                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80);
4198                 break;
4199         }
4200 }
4201
4202 static void r8168_pll_power_up(struct rtl8169_private *tp)
4203 {
4204         switch (tp->mac_version) {
4205         case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_33:
4206         case RTL_GIGA_MAC_VER_37:
4207         case RTL_GIGA_MAC_VER_39:
4208         case RTL_GIGA_MAC_VER_43:
4209                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0x80);
4210                 break;
4211         case RTL_GIGA_MAC_VER_44:
4212         case RTL_GIGA_MAC_VER_45:
4213         case RTL_GIGA_MAC_VER_46:
4214         case RTL_GIGA_MAC_VER_47:
4215         case RTL_GIGA_MAC_VER_48:
4216         case RTL_GIGA_MAC_VER_50:
4217         case RTL_GIGA_MAC_VER_51:
4218                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0);
4219                 break;
4220         case RTL_GIGA_MAC_VER_40:
4221         case RTL_GIGA_MAC_VER_41:
4222         case RTL_GIGA_MAC_VER_49:
4223                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0);
4224                 rtl_w0w1_eri(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000,
4225                              0x00000000, ERIAR_EXGMAC);
4226                 break;
4227         }
4228
4229         phy_resume(tp->dev->phydev);
4230         /* give MAC/PHY some time to resume */
4231         msleep(20);
4232 }
4233
4234 static void rtl_pll_power_down(struct rtl8169_private *tp)
4235 {
4236         switch (tp->mac_version) {
4237         case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_06:
4238         case RTL_GIGA_MAC_VER_13 ... RTL_GIGA_MAC_VER_15:
4239                 break;
4240         default:
4241                 r8168_pll_power_down(tp);
4242         }
4243 }
4244
4245 static void rtl_pll_power_up(struct rtl8169_private *tp)
4246 {
4247         switch (tp->mac_version) {
4248         case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_06:
4249         case RTL_GIGA_MAC_VER_13 ... RTL_GIGA_MAC_VER_15:
4250                 break;
4251         default:
4252                 r8168_pll_power_up(tp);
4253         }
4254 }
4255
4256 static void rtl_init_rxcfg(struct rtl8169_private *tp)
4257 {
4258         switch (tp->mac_version) {
4259         case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_06:
4260         case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
4261                 RTL_W32(tp, RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
4262                 break;
4263         case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
4264         case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36:
4265         case RTL_GIGA_MAC_VER_38:
4266                 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
4267                 break;
4268         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
4269                 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF);
4270                 break;
4271         default:
4272                 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_DMA_BURST);
4273                 break;
4274         }
4275 }
4276
4277 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
4278 {
4279         tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0;
4280 }
4281
4282 static void rtl_hw_jumbo_enable(struct rtl8169_private *tp)
4283 {
4284         if (tp->jumbo_ops.enable) {
4285                 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
4286                 tp->jumbo_ops.enable(tp);
4287                 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
4288         }
4289 }
4290
4291 static void rtl_hw_jumbo_disable(struct rtl8169_private *tp)
4292 {
4293         if (tp->jumbo_ops.disable) {
4294                 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
4295                 tp->jumbo_ops.disable(tp);
4296                 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
4297         }
4298 }
4299
4300 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
4301 {
4302         RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
4303         RTL_W8(tp, Config4, RTL_R8(tp, Config4) | Jumbo_En1);
4304         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_512B);
4305 }
4306
4307 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
4308 {
4309         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
4310         RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~Jumbo_En1);
4311         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4312 }
4313
4314 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
4315 {
4316         RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
4317 }
4318
4319 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
4320 {
4321         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
4322 }
4323
4324 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
4325 {
4326         RTL_W8(tp, MaxTxPacketSize, 0x3f);
4327         RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
4328         RTL_W8(tp, Config4, RTL_R8(tp, Config4) | 0x01);
4329         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_512B);
4330 }
4331
4332 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
4333 {
4334         RTL_W8(tp, MaxTxPacketSize, 0x0c);
4335         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
4336         RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~0x01);
4337         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4338 }
4339
4340 static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp)
4341 {
4342         rtl_tx_performance_tweak(tp,
4343                 PCI_EXP_DEVCTL_READRQ_512B | PCI_EXP_DEVCTL_NOSNOOP_EN);
4344 }
4345
4346 static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp)
4347 {
4348         rtl_tx_performance_tweak(tp,
4349                 PCI_EXP_DEVCTL_READRQ_4096B | PCI_EXP_DEVCTL_NOSNOOP_EN);
4350 }
4351
4352 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
4353 {
4354         r8168b_0_hw_jumbo_enable(tp);
4355
4356         RTL_W8(tp, Config4, RTL_R8(tp, Config4) | (1 << 0));
4357 }
4358
4359 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
4360 {
4361         r8168b_0_hw_jumbo_disable(tp);
4362
4363         RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0));
4364 }
4365
4366 static void rtl_init_jumbo_ops(struct rtl8169_private *tp)
4367 {
4368         struct jumbo_ops *ops = &tp->jumbo_ops;
4369
4370         switch (tp->mac_version) {
4371         case RTL_GIGA_MAC_VER_11:
4372                 ops->disable    = r8168b_0_hw_jumbo_disable;
4373                 ops->enable     = r8168b_0_hw_jumbo_enable;
4374                 break;
4375         case RTL_GIGA_MAC_VER_12:
4376         case RTL_GIGA_MAC_VER_17:
4377                 ops->disable    = r8168b_1_hw_jumbo_disable;
4378                 ops->enable     = r8168b_1_hw_jumbo_enable;
4379                 break;
4380         case RTL_GIGA_MAC_VER_18: /* Wild guess. Needs info from Realtek. */
4381         case RTL_GIGA_MAC_VER_19:
4382         case RTL_GIGA_MAC_VER_20:
4383         case RTL_GIGA_MAC_VER_21: /* Wild guess. Needs info from Realtek. */
4384         case RTL_GIGA_MAC_VER_22:
4385         case RTL_GIGA_MAC_VER_23:
4386         case RTL_GIGA_MAC_VER_24:
4387         case RTL_GIGA_MAC_VER_25:
4388         case RTL_GIGA_MAC_VER_26:
4389                 ops->disable    = r8168c_hw_jumbo_disable;
4390                 ops->enable     = r8168c_hw_jumbo_enable;
4391                 break;
4392         case RTL_GIGA_MAC_VER_27:
4393         case RTL_GIGA_MAC_VER_28:
4394                 ops->disable    = r8168dp_hw_jumbo_disable;
4395                 ops->enable     = r8168dp_hw_jumbo_enable;
4396                 break;
4397         case RTL_GIGA_MAC_VER_31: /* Wild guess. Needs info from Realtek. */
4398         case RTL_GIGA_MAC_VER_32:
4399         case RTL_GIGA_MAC_VER_33:
4400         case RTL_GIGA_MAC_VER_34:
4401                 ops->disable    = r8168e_hw_jumbo_disable;
4402                 ops->enable     = r8168e_hw_jumbo_enable;
4403                 break;
4404
4405         /*
4406          * No action needed for jumbo frames with 8169.
4407          * No jumbo for 810x at all.
4408          */
4409         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
4410         default:
4411                 ops->disable    = NULL;
4412                 ops->enable     = NULL;
4413                 break;
4414         }
4415 }
4416
4417 DECLARE_RTL_COND(rtl_chipcmd_cond)
4418 {
4419         return RTL_R8(tp, ChipCmd) & CmdReset;
4420 }
4421
4422 static void rtl_hw_reset(struct rtl8169_private *tp)
4423 {
4424         RTL_W8(tp, ChipCmd, CmdReset);
4425
4426         rtl_udelay_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100);
4427 }
4428
4429 static void rtl_request_uncached_firmware(struct rtl8169_private *tp)
4430 {
4431         struct rtl_fw *rtl_fw;
4432         const char *name;
4433         int rc = -ENOMEM;
4434
4435         name = rtl_lookup_firmware_name(tp);
4436         if (!name)
4437                 goto out_no_firmware;
4438
4439         rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
4440         if (!rtl_fw)
4441                 goto err_warn;
4442
4443         rc = request_firmware(&rtl_fw->fw, name, tp_to_dev(tp));
4444         if (rc < 0)
4445                 goto err_free;
4446
4447         rc = rtl_check_firmware(tp, rtl_fw);
4448         if (rc < 0)
4449                 goto err_release_firmware;
4450
4451         tp->rtl_fw = rtl_fw;
4452 out:
4453         return;
4454
4455 err_release_firmware:
4456         release_firmware(rtl_fw->fw);
4457 err_free:
4458         kfree(rtl_fw);
4459 err_warn:
4460         netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n",
4461                    name, rc);
4462 out_no_firmware:
4463         tp->rtl_fw = NULL;
4464         goto out;
4465 }
4466
4467 static void rtl_request_firmware(struct rtl8169_private *tp)
4468 {
4469         if (IS_ERR(tp->rtl_fw))
4470                 rtl_request_uncached_firmware(tp);
4471 }
4472
4473 static void rtl_rx_close(struct rtl8169_private *tp)
4474 {
4475         RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
4476 }
4477
4478 DECLARE_RTL_COND(rtl_npq_cond)
4479 {
4480         return RTL_R8(tp, TxPoll) & NPQ;
4481 }
4482
4483 DECLARE_RTL_COND(rtl_txcfg_empty_cond)
4484 {
4485         return RTL_R32(tp, TxConfig) & TXCFG_EMPTY;
4486 }
4487
4488 static void rtl8169_hw_reset(struct rtl8169_private *tp)
4489 {
4490         /* Disable interrupts */
4491         rtl8169_irq_mask_and_ack(tp);
4492
4493         rtl_rx_close(tp);
4494
4495         switch (tp->mac_version) {
4496         case RTL_GIGA_MAC_VER_27:
4497         case RTL_GIGA_MAC_VER_28:
4498         case RTL_GIGA_MAC_VER_31:
4499                 rtl_udelay_loop_wait_low(tp, &rtl_npq_cond, 20, 42*42);
4500                 break;
4501         case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
4502         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
4503                 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
4504                 rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);
4505                 break;
4506         default:
4507                 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
4508                 udelay(100);
4509                 break;
4510         }
4511
4512         rtl_hw_reset(tp);
4513 }
4514
4515 static void rtl_set_tx_config_registers(struct rtl8169_private *tp)
4516 {
4517         u32 val = TX_DMA_BURST << TxDMAShift |
4518                   InterFrameGap << TxInterFrameGapShift;
4519
4520         if (tp->mac_version >= RTL_GIGA_MAC_VER_34 &&
4521             tp->mac_version != RTL_GIGA_MAC_VER_39)
4522                 val |= TXCFG_AUTO_FIFO;
4523
4524         RTL_W32(tp, TxConfig, val);
4525 }
4526
4527 static void rtl_set_rx_max_size(struct rtl8169_private *tp)
4528 {
4529         /* Low hurts. Let's disable the filtering. */
4530         RTL_W16(tp, RxMaxSize, R8169_RX_BUF_SIZE + 1);
4531 }
4532
4533 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp)
4534 {
4535         /*
4536          * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
4537          * register to be written before TxDescAddrLow to work.
4538          * Switching from MMIO to I/O access fixes the issue as well.
4539          */
4540         RTL_W32(tp, TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
4541         RTL_W32(tp, TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
4542         RTL_W32(tp, RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
4543         RTL_W32(tp, RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
4544 }
4545
4546 static void rtl8169_set_magic_reg(struct rtl8169_private *tp, unsigned mac_version)
4547 {
4548         u32 val;
4549
4550         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
4551                 val = 0x000fff00;
4552         else if (tp->mac_version == RTL_GIGA_MAC_VER_06)
4553                 val = 0x00ffff00;
4554         else
4555                 return;
4556
4557         if (RTL_R8(tp, Config2) & PCI_Clock_66MHz)
4558                 val |= 0xff;
4559
4560         RTL_W32(tp, 0x7c, val);
4561 }
4562
4563 static void rtl_set_rx_mode(struct net_device *dev)
4564 {
4565         struct rtl8169_private *tp = netdev_priv(dev);
4566         u32 mc_filter[2];       /* Multicast hash filter */
4567         int rx_mode;
4568         u32 tmp = 0;
4569
4570         if (dev->flags & IFF_PROMISC) {
4571                 /* Unconditionally log net taps. */
4572                 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
4573                 rx_mode =
4574                     AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
4575                     AcceptAllPhys;
4576                 mc_filter[1] = mc_filter[0] = 0xffffffff;
4577         } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
4578                    (dev->flags & IFF_ALLMULTI)) {
4579                 /* Too many to filter perfectly -- accept all multicasts. */
4580                 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
4581                 mc_filter[1] = mc_filter[0] = 0xffffffff;
4582         } else {
4583                 struct netdev_hw_addr *ha;
4584
4585                 rx_mode = AcceptBroadcast | AcceptMyPhys;
4586                 mc_filter[1] = mc_filter[0] = 0;
4587                 netdev_for_each_mc_addr(ha, dev) {
4588                         int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
4589                         mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
4590                         rx_mode |= AcceptMulticast;
4591                 }
4592         }
4593
4594         if (dev->features & NETIF_F_RXALL)
4595                 rx_mode |= (AcceptErr | AcceptRunt);
4596
4597         tmp = (RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK) | rx_mode;
4598
4599         if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
4600                 u32 data = mc_filter[0];
4601
4602                 mc_filter[0] = swab32(mc_filter[1]);
4603                 mc_filter[1] = swab32(data);
4604         }
4605
4606         if (tp->mac_version == RTL_GIGA_MAC_VER_35)
4607                 mc_filter[1] = mc_filter[0] = 0xffffffff;
4608
4609         RTL_W32(tp, MAR0 + 4, mc_filter[1]);
4610         RTL_W32(tp, MAR0 + 0, mc_filter[0]);
4611
4612         RTL_W32(tp, RxConfig, tmp);
4613 }
4614
4615 static void rtl_hw_start(struct  rtl8169_private *tp)
4616 {
4617         RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
4618
4619         tp->hw_start(tp);
4620
4621         rtl_set_rx_max_size(tp);
4622         rtl_set_rx_tx_desc_registers(tp);
4623         RTL_W8(tp, Cfg9346, Cfg9346_Lock);
4624
4625         /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
4626         RTL_R8(tp, IntrMask);
4627         RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb);
4628         rtl_init_rxcfg(tp);
4629         rtl_set_tx_config_registers(tp);
4630
4631         rtl_set_rx_mode(tp->dev);
4632         /* no early-rx interrupts */
4633         RTL_W16(tp, MultiIntr, RTL_R16(tp, MultiIntr) & 0xf000);
4634         rtl_irq_enable(tp);
4635 }
4636
4637 static void rtl_hw_start_8169(struct rtl8169_private *tp)
4638 {
4639         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
4640                 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4641
4642         RTL_W8(tp, EarlyTxThres, NoEarlyTx);
4643
4644         tp->cp_cmd |= PCIMulRW;
4645
4646         if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4647             tp->mac_version == RTL_GIGA_MAC_VER_03) {
4648                 netif_dbg(tp, drv, tp->dev,
4649                           "Set MAC Reg C+CR Offset 0xe0. Bit 3 and Bit 14 MUST be 1\n");
4650                 tp->cp_cmd |= (1 << 14);
4651         }
4652
4653         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4654
4655         rtl8169_set_magic_reg(tp, tp->mac_version);
4656
4657         /*
4658          * Undocumented corner. Supposedly:
4659          * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
4660          */
4661         RTL_W16(tp, IntrMitigate, 0x0000);
4662
4663         RTL_W32(tp, RxMissed, 0);
4664 }
4665
4666 DECLARE_RTL_COND(rtl_csiar_cond)
4667 {
4668         return RTL_R32(tp, CSIAR) & CSIAR_FLAG;
4669 }
4670
4671 static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)
4672 {
4673         u32 func = PCI_FUNC(tp->pci_dev->devfn);
4674
4675         RTL_W32(tp, CSIDR, value);
4676         RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
4677                 CSIAR_BYTE_ENABLE | func << 16);
4678
4679         rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
4680 }
4681
4682 static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)
4683 {
4684         u32 func = PCI_FUNC(tp->pci_dev->devfn);
4685
4686         RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) | func << 16 |
4687                 CSIAR_BYTE_ENABLE);
4688
4689         return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
4690                 RTL_R32(tp, CSIDR) : ~0;
4691 }
4692
4693 static void rtl_csi_access_enable(struct rtl8169_private *tp, u8 val)
4694 {
4695         struct pci_dev *pdev = tp->pci_dev;
4696         u32 csi;
4697
4698         /* According to Realtek the value at config space address 0x070f
4699          * controls the L0s/L1 entrance latency. We try standard ECAM access
4700          * first and if it fails fall back to CSI.
4701          */
4702         if (pdev->cfg_size > 0x070f &&
4703             pci_write_config_byte(pdev, 0x070f, val) == PCIBIOS_SUCCESSFUL)
4704                 return;
4705
4706         netdev_notice_once(tp->dev,
4707                 "No native access to PCI extended config space, falling back to CSI\n");
4708         csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff;
4709         rtl_csi_write(tp, 0x070c, csi | val << 24);
4710 }
4711
4712 static void rtl_set_def_aspm_entry_latency(struct rtl8169_private *tp)
4713 {
4714         rtl_csi_access_enable(tp, 0x27);
4715 }
4716
4717 struct ephy_info {
4718         unsigned int offset;
4719         u16 mask;
4720         u16 bits;
4721 };
4722
4723 static void rtl_ephy_init(struct rtl8169_private *tp, const struct ephy_info *e,
4724                           int len)
4725 {
4726         u16 w;
4727
4728         while (len-- > 0) {
4729                 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits;
4730                 rtl_ephy_write(tp, e->offset, w);
4731                 e++;
4732         }
4733 }
4734
4735 static void rtl_disable_clock_request(struct rtl8169_private *tp)
4736 {
4737         pcie_capability_clear_word(tp->pci_dev, PCI_EXP_LNKCTL,
4738                                    PCI_EXP_LNKCTL_CLKREQ_EN);
4739 }
4740
4741 static void rtl_enable_clock_request(struct rtl8169_private *tp)
4742 {
4743         pcie_capability_set_word(tp->pci_dev, PCI_EXP_LNKCTL,
4744                                  PCI_EXP_LNKCTL_CLKREQ_EN);
4745 }
4746
4747 static void rtl_pcie_state_l2l3_enable(struct rtl8169_private *tp, bool enable)
4748 {
4749         u8 data;
4750
4751         data = RTL_R8(tp, Config3);
4752
4753         if (enable)
4754                 data |= Rdy_to_L23;
4755         else
4756                 data &= ~Rdy_to_L23;
4757
4758         RTL_W8(tp, Config3, data);
4759 }
4760
4761 static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable)
4762 {
4763         if (enable) {
4764                 RTL_W8(tp, Config5, RTL_R8(tp, Config5) | ASPM_en);
4765                 RTL_W8(tp, Config2, RTL_R8(tp, Config2) | ClkReqEn);
4766         } else {
4767                 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
4768                 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
4769         }
4770
4771         udelay(10);
4772 }
4773
4774 static void rtl_hw_start_8168bb(struct rtl8169_private *tp)
4775 {
4776         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4777
4778         tp->cp_cmd &= CPCMD_QUIRK_MASK;
4779         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4780
4781         if (tp->dev->mtu <= ETH_DATA_LEN) {
4782                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B |
4783                                          PCI_EXP_DEVCTL_NOSNOOP_EN);
4784         }
4785 }
4786
4787 static void rtl_hw_start_8168bef(struct rtl8169_private *tp)
4788 {
4789         rtl_hw_start_8168bb(tp);
4790
4791         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4792
4793         RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0));
4794 }
4795
4796 static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)
4797 {
4798         RTL_W8(tp, Config1, RTL_R8(tp, Config1) | Speed_down);
4799
4800         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4801
4802         if (tp->dev->mtu <= ETH_DATA_LEN)
4803                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4804
4805         rtl_disable_clock_request(tp);
4806
4807         tp->cp_cmd &= CPCMD_QUIRK_MASK;
4808         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4809 }
4810
4811 static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp)
4812 {
4813         static const struct ephy_info e_info_8168cp[] = {
4814                 { 0x01, 0,      0x0001 },
4815                 { 0x02, 0x0800, 0x1000 },
4816                 { 0x03, 0,      0x0042 },
4817                 { 0x06, 0x0080, 0x0000 },
4818                 { 0x07, 0,      0x2000 }
4819         };
4820
4821         rtl_set_def_aspm_entry_latency(tp);
4822
4823         rtl_ephy_init(tp, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
4824
4825         __rtl_hw_start_8168cp(tp);
4826 }
4827
4828 static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)
4829 {
4830         rtl_set_def_aspm_entry_latency(tp);
4831
4832         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4833
4834         if (tp->dev->mtu <= ETH_DATA_LEN)
4835                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4836
4837         tp->cp_cmd &= CPCMD_QUIRK_MASK;
4838         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4839 }
4840
4841 static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)
4842 {
4843         rtl_set_def_aspm_entry_latency(tp);
4844
4845         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4846
4847         /* Magic. */
4848         RTL_W8(tp, DBG_REG, 0x20);
4849
4850         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4851
4852         if (tp->dev->mtu <= ETH_DATA_LEN)
4853                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4854
4855         tp->cp_cmd &= CPCMD_QUIRK_MASK;
4856         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4857 }
4858
4859 static void rtl_hw_start_8168c_1(struct rtl8169_private *tp)
4860 {
4861         static const struct ephy_info e_info_8168c_1[] = {
4862                 { 0x02, 0x0800, 0x1000 },
4863                 { 0x03, 0,      0x0002 },
4864                 { 0x06, 0x0080, 0x0000 }
4865         };
4866
4867         rtl_set_def_aspm_entry_latency(tp);
4868
4869         RTL_W8(tp, DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
4870
4871         rtl_ephy_init(tp, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
4872
4873         __rtl_hw_start_8168cp(tp);
4874 }
4875
4876 static void rtl_hw_start_8168c_2(struct rtl8169_private *tp)
4877 {
4878         static const struct ephy_info e_info_8168c_2[] = {
4879                 { 0x01, 0,      0x0001 },
4880                 { 0x03, 0x0400, 0x0220 }
4881         };
4882
4883         rtl_set_def_aspm_entry_latency(tp);
4884
4885         rtl_ephy_init(tp, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
4886
4887         __rtl_hw_start_8168cp(tp);
4888 }
4889
4890 static void rtl_hw_start_8168c_3(struct rtl8169_private *tp)
4891 {
4892         rtl_hw_start_8168c_2(tp);
4893 }
4894
4895 static void rtl_hw_start_8168c_4(struct rtl8169_private *tp)
4896 {
4897         rtl_set_def_aspm_entry_latency(tp);
4898
4899         __rtl_hw_start_8168cp(tp);
4900 }
4901
4902 static void rtl_hw_start_8168d(struct rtl8169_private *tp)
4903 {
4904         rtl_set_def_aspm_entry_latency(tp);
4905
4906         rtl_disable_clock_request(tp);
4907
4908         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4909
4910         if (tp->dev->mtu <= ETH_DATA_LEN)
4911                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4912
4913         tp->cp_cmd &= CPCMD_QUIRK_MASK;
4914         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4915 }
4916
4917 static void rtl_hw_start_8168dp(struct rtl8169_private *tp)
4918 {
4919         rtl_set_def_aspm_entry_latency(tp);
4920
4921         if (tp->dev->mtu <= ETH_DATA_LEN)
4922                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4923
4924         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4925
4926         rtl_disable_clock_request(tp);
4927 }
4928
4929 static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
4930 {
4931         static const struct ephy_info e_info_8168d_4[] = {
4932                 { 0x0b, 0x0000, 0x0048 },
4933                 { 0x19, 0x0020, 0x0050 },
4934                 { 0x0c, 0x0100, 0x0020 }
4935         };
4936
4937         rtl_set_def_aspm_entry_latency(tp);
4938
4939         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4940
4941         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4942
4943         rtl_ephy_init(tp, e_info_8168d_4, ARRAY_SIZE(e_info_8168d_4));
4944
4945         rtl_enable_clock_request(tp);
4946 }
4947
4948 static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)
4949 {
4950         static const struct ephy_info e_info_8168e_1[] = {
4951                 { 0x00, 0x0200, 0x0100 },
4952                 { 0x00, 0x0000, 0x0004 },
4953                 { 0x06, 0x0002, 0x0001 },
4954                 { 0x06, 0x0000, 0x0030 },
4955                 { 0x07, 0x0000, 0x2000 },
4956                 { 0x00, 0x0000, 0x0020 },
4957                 { 0x03, 0x5800, 0x2000 },
4958                 { 0x03, 0x0000, 0x0001 },
4959                 { 0x01, 0x0800, 0x1000 },
4960                 { 0x07, 0x0000, 0x4000 },
4961                 { 0x1e, 0x0000, 0x2000 },
4962                 { 0x19, 0xffff, 0xfe6c },
4963                 { 0x0a, 0x0000, 0x0040 }
4964         };
4965
4966         rtl_set_def_aspm_entry_latency(tp);
4967
4968         rtl_ephy_init(tp, e_info_8168e_1, ARRAY_SIZE(e_info_8168e_1));
4969
4970         if (tp->dev->mtu <= ETH_DATA_LEN)
4971                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4972
4973         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4974
4975         rtl_disable_clock_request(tp);
4976
4977         /* Reset tx FIFO pointer */
4978         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | TXPLA_RST);
4979         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~TXPLA_RST);
4980
4981         RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
4982 }
4983
4984 static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
4985 {
4986         static const struct ephy_info e_info_8168e_2[] = {
4987                 { 0x09, 0x0000, 0x0080 },
4988                 { 0x19, 0x0000, 0x0224 }
4989         };
4990
4991         rtl_set_def_aspm_entry_latency(tp);
4992
4993         rtl_ephy_init(tp, e_info_8168e_2, ARRAY_SIZE(e_info_8168e_2));
4994
4995         if (tp->dev->mtu <= ETH_DATA_LEN)
4996                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4997
4998         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4999         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5000         rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
5001         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5002         rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
5003         rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060, ERIAR_EXGMAC);
5004         rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5005         rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
5006
5007         RTL_W8(tp, MaxTxPacketSize, EarlySize);
5008
5009         rtl_disable_clock_request(tp);
5010
5011         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
5012
5013         /* Adjust EEE LED frequency */
5014         RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
5015
5016         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
5017         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
5018         RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
5019
5020         rtl_hw_aspm_clkreq_enable(tp, true);
5021 }
5022
5023 static void rtl_hw_start_8168f(struct rtl8169_private *tp)
5024 {
5025         rtl_set_def_aspm_entry_latency(tp);
5026
5027         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5028
5029         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5030         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5031         rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
5032         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5033         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5034         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5035         rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5036         rtl_w0w1_eri(tp, 0x1d0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5037         rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
5038         rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060, ERIAR_EXGMAC);
5039
5040         RTL_W8(tp, MaxTxPacketSize, EarlySize);
5041
5042         rtl_disable_clock_request(tp);
5043
5044         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
5045         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
5046         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
5047         RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
5048 }
5049
5050 static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
5051 {
5052         static const struct ephy_info e_info_8168f_1[] = {
5053                 { 0x06, 0x00c0, 0x0020 },
5054                 { 0x08, 0x0001, 0x0002 },
5055                 { 0x09, 0x0000, 0x0080 },
5056                 { 0x19, 0x0000, 0x0224 }
5057         };
5058
5059         rtl_hw_start_8168f(tp);
5060
5061         rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
5062
5063         rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
5064
5065         /* Adjust EEE LED frequency */
5066         RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
5067 }
5068
5069 static void rtl_hw_start_8411(struct rtl8169_private *tp)
5070 {
5071         static const struct ephy_info e_info_8168f_1[] = {
5072                 { 0x06, 0x00c0, 0x0020 },
5073                 { 0x0f, 0xffff, 0x5200 },
5074                 { 0x1e, 0x0000, 0x4000 },
5075                 { 0x19, 0x0000, 0x0224 }
5076         };
5077
5078         rtl_hw_start_8168f(tp);
5079         rtl_pcie_state_l2l3_enable(tp, false);
5080
5081         rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
5082
5083         rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0x0000, ERIAR_EXGMAC);
5084 }
5085
5086 static void rtl_hw_start_8168g(struct rtl8169_private *tp)
5087 {
5088         rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x080002, ERIAR_EXGMAC);
5089         rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
5090         rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
5091         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5092
5093         rtl_set_def_aspm_entry_latency(tp);
5094
5095         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5096
5097         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5098         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5099         rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f, ERIAR_EXGMAC);
5100
5101         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
5102         RTL_W8(tp, MaxTxPacketSize, EarlySize);
5103
5104         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5105         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5106
5107         /* Adjust EEE LED frequency */
5108         RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
5109
5110         rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06, ERIAR_EXGMAC);
5111         rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC);
5112
5113         rtl_pcie_state_l2l3_enable(tp, false);
5114 }
5115
5116 static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
5117 {
5118         static const struct ephy_info e_info_8168g_1[] = {
5119                 { 0x00, 0x0000, 0x0008 },
5120                 { 0x0c, 0x37d0, 0x0820 },
5121                 { 0x1e, 0x0000, 0x0001 },
5122                 { 0x19, 0x8000, 0x0000 }
5123         };
5124
5125         rtl_hw_start_8168g(tp);
5126
5127         /* disable aspm and clock request before access ephy */
5128         rtl_hw_aspm_clkreq_enable(tp, false);
5129         rtl_ephy_init(tp, e_info_8168g_1, ARRAY_SIZE(e_info_8168g_1));
5130         rtl_hw_aspm_clkreq_enable(tp, true);
5131 }
5132
5133 static void rtl_hw_start_8168g_2(struct rtl8169_private *tp)
5134 {
5135         static const struct ephy_info e_info_8168g_2[] = {
5136                 { 0x00, 0x0000, 0x0008 },
5137                 { 0x0c, 0x3df0, 0x0200 },
5138                 { 0x19, 0xffff, 0xfc00 },
5139                 { 0x1e, 0xffff, 0x20eb }
5140         };
5141
5142         rtl_hw_start_8168g(tp);
5143
5144         /* disable aspm and clock request before access ephy */
5145         RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
5146         RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
5147         rtl_ephy_init(tp, e_info_8168g_2, ARRAY_SIZE(e_info_8168g_2));
5148 }
5149
5150 static void rtl_hw_start_8411_2(struct rtl8169_private *tp)
5151 {
5152         static const struct ephy_info e_info_8411_2[] = {
5153                 { 0x00, 0x0000, 0x0008 },
5154                 { 0x0c, 0x3df0, 0x0200 },
5155                 { 0x0f, 0xffff, 0x5200 },
5156                 { 0x19, 0x0020, 0x0000 },
5157                 { 0x1e, 0x0000, 0x2000 }
5158         };
5159
5160         rtl_hw_start_8168g(tp);
5161
5162         /* disable aspm and clock request before access ephy */
5163         rtl_hw_aspm_clkreq_enable(tp, false);
5164         rtl_ephy_init(tp, e_info_8411_2, ARRAY_SIZE(e_info_8411_2));
5165         rtl_hw_aspm_clkreq_enable(tp, true);
5166 }
5167
5168 static void rtl_hw_start_8168h_1(struct rtl8169_private *tp)
5169 {
5170         int rg_saw_cnt;
5171         u32 data;
5172         static const struct ephy_info e_info_8168h_1[] = {
5173                 { 0x1e, 0x0800, 0x0001 },
5174                 { 0x1d, 0x0000, 0x0800 },
5175                 { 0x05, 0xffff, 0x2089 },
5176                 { 0x06, 0xffff, 0x5881 },
5177                 { 0x04, 0xffff, 0x154a },
5178                 { 0x01, 0xffff, 0x068b }
5179         };
5180
5181         /* disable aspm and clock request before access ephy */
5182         rtl_hw_aspm_clkreq_enable(tp, false);
5183         rtl_ephy_init(tp, e_info_8168h_1, ARRAY_SIZE(e_info_8168h_1));
5184
5185         rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x00080002, ERIAR_EXGMAC);
5186         rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
5187         rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
5188         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5189
5190         rtl_set_def_aspm_entry_latency(tp);
5191
5192         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5193
5194         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5195         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5196
5197         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_1111, 0x0010, 0x00, ERIAR_EXGMAC);
5198
5199         rtl_w0w1_eri(tp, 0xd4, ERIAR_MASK_1111, 0x1f00, 0x00, ERIAR_EXGMAC);
5200
5201         rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87, ERIAR_EXGMAC);
5202
5203         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
5204         RTL_W8(tp, MaxTxPacketSize, EarlySize);
5205
5206         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5207         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5208
5209         /* Adjust EEE LED frequency */
5210         RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
5211
5212         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5213         RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
5214
5215         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
5216
5217         rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC);
5218
5219         rtl_pcie_state_l2l3_enable(tp, false);
5220
5221         rtl_writephy(tp, 0x1f, 0x0c42);
5222         rg_saw_cnt = (rtl_readphy(tp, 0x13) & 0x3fff);
5223         rtl_writephy(tp, 0x1f, 0x0000);
5224         if (rg_saw_cnt > 0) {
5225                 u16 sw_cnt_1ms_ini;
5226
5227                 sw_cnt_1ms_ini = 16000000/rg_saw_cnt;
5228                 sw_cnt_1ms_ini &= 0x0fff;
5229                 data = r8168_mac_ocp_read(tp, 0xd412);
5230                 data &= ~0x0fff;
5231                 data |= sw_cnt_1ms_ini;
5232                 r8168_mac_ocp_write(tp, 0xd412, data);
5233         }
5234
5235         data = r8168_mac_ocp_read(tp, 0xe056);
5236         data &= ~0xf0;
5237         data |= 0x70;
5238         r8168_mac_ocp_write(tp, 0xe056, data);
5239
5240         data = r8168_mac_ocp_read(tp, 0xe052);
5241         data &= ~0x6000;
5242         data |= 0x8008;
5243         r8168_mac_ocp_write(tp, 0xe052, data);
5244
5245         data = r8168_mac_ocp_read(tp, 0xe0d6);
5246         data &= ~0x01ff;
5247         data |= 0x017f;
5248         r8168_mac_ocp_write(tp, 0xe0d6, data);
5249
5250         data = r8168_mac_ocp_read(tp, 0xd420);
5251         data &= ~0x0fff;
5252         data |= 0x047f;
5253         r8168_mac_ocp_write(tp, 0xd420, data);
5254
5255         r8168_mac_ocp_write(tp, 0xe63e, 0x0001);
5256         r8168_mac_ocp_write(tp, 0xe63e, 0x0000);
5257         r8168_mac_ocp_write(tp, 0xc094, 0x0000);
5258         r8168_mac_ocp_write(tp, 0xc09e, 0x0000);
5259
5260         rtl_hw_aspm_clkreq_enable(tp, true);
5261 }
5262
5263 static void rtl_hw_start_8168ep(struct rtl8169_private *tp)
5264 {
5265         rtl8168ep_stop_cmac(tp);
5266
5267         rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x00080002, ERIAR_EXGMAC);
5268         rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x2f, ERIAR_EXGMAC);
5269         rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x5f, ERIAR_EXGMAC);
5270         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5271
5272         rtl_set_def_aspm_entry_latency(tp);
5273
5274         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5275
5276         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5277         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5278
5279         rtl_w0w1_eri(tp, 0xd4, ERIAR_MASK_1111, 0x1f80, 0x00, ERIAR_EXGMAC);
5280
5281         rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87, ERIAR_EXGMAC);
5282
5283         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
5284         RTL_W8(tp, MaxTxPacketSize, EarlySize);
5285
5286         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5287         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5288
5289         /* Adjust EEE LED frequency */
5290         RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
5291
5292         rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06, ERIAR_EXGMAC);
5293
5294         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
5295
5296         rtl_pcie_state_l2l3_enable(tp, false);
5297 }
5298
5299 static void rtl_hw_start_8168ep_1(struct rtl8169_private *tp)
5300 {
5301         static const struct ephy_info e_info_8168ep_1[] = {
5302                 { 0x00, 0xffff, 0x10ab },
5303                 { 0x06, 0xffff, 0xf030 },
5304                 { 0x08, 0xffff, 0x2006 },
5305                 { 0x0d, 0xffff, 0x1666 },
5306                 { 0x0c, 0x3ff0, 0x0000 }
5307         };
5308
5309         /* disable aspm and clock request before access ephy */
5310         rtl_hw_aspm_clkreq_enable(tp, false);
5311         rtl_ephy_init(tp, e_info_8168ep_1, ARRAY_SIZE(e_info_8168ep_1));
5312
5313         rtl_hw_start_8168ep(tp);
5314
5315         rtl_hw_aspm_clkreq_enable(tp, true);
5316 }
5317
5318 static void rtl_hw_start_8168ep_2(struct rtl8169_private *tp)
5319 {
5320         static const struct ephy_info e_info_8168ep_2[] = {
5321                 { 0x00, 0xffff, 0x10a3 },
5322                 { 0x19, 0xffff, 0xfc00 },
5323                 { 0x1e, 0xffff, 0x20ea }
5324         };
5325
5326         /* disable aspm and clock request before access ephy */
5327         rtl_hw_aspm_clkreq_enable(tp, false);
5328         rtl_ephy_init(tp, e_info_8168ep_2, ARRAY_SIZE(e_info_8168ep_2));
5329
5330         rtl_hw_start_8168ep(tp);
5331
5332         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5333         RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
5334
5335         rtl_hw_aspm_clkreq_enable(tp, true);
5336 }
5337
5338 static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp)
5339 {
5340         u32 data;
5341         static const struct ephy_info e_info_8168ep_3[] = {
5342                 { 0x00, 0xffff, 0x10a3 },
5343                 { 0x19, 0xffff, 0x7c00 },
5344                 { 0x1e, 0xffff, 0x20eb },
5345                 { 0x0d, 0xffff, 0x1666 }
5346         };
5347
5348         /* disable aspm and clock request before access ephy */
5349         rtl_hw_aspm_clkreq_enable(tp, false);
5350         rtl_ephy_init(tp, e_info_8168ep_3, ARRAY_SIZE(e_info_8168ep_3));
5351
5352         rtl_hw_start_8168ep(tp);
5353
5354         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5355         RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
5356
5357         data = r8168_mac_ocp_read(tp, 0xd3e2);
5358         data &= 0xf000;
5359         data |= 0x0271;
5360         r8168_mac_ocp_write(tp, 0xd3e2, data);
5361
5362         data = r8168_mac_ocp_read(tp, 0xd3e4);
5363         data &= 0xff00;
5364         r8168_mac_ocp_write(tp, 0xd3e4, data);
5365
5366         data = r8168_mac_ocp_read(tp, 0xe860);
5367         data |= 0x0080;
5368         r8168_mac_ocp_write(tp, 0xe860, data);
5369
5370         rtl_hw_aspm_clkreq_enable(tp, true);
5371 }
5372
5373 static void rtl_hw_start_8168(struct rtl8169_private *tp)
5374 {
5375         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
5376
5377         tp->cp_cmd &= ~INTT_MASK;
5378         tp->cp_cmd |= PktCntrDisable | INTT_1;
5379         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
5380
5381         RTL_W16(tp, IntrMitigate, 0x5151);
5382
5383         /* Work around for RxFIFO overflow. */
5384         if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
5385                 tp->irq_mask |= RxFIFOOver;
5386                 tp->irq_mask &= ~RxOverflow;
5387         }
5388
5389         switch (tp->mac_version) {
5390         case RTL_GIGA_MAC_VER_11:
5391                 rtl_hw_start_8168bb(tp);
5392                 break;
5393
5394         case RTL_GIGA_MAC_VER_12:
5395         case RTL_GIGA_MAC_VER_17:
5396                 rtl_hw_start_8168bef(tp);
5397                 break;
5398
5399         case RTL_GIGA_MAC_VER_18:
5400                 rtl_hw_start_8168cp_1(tp);
5401                 break;
5402
5403         case RTL_GIGA_MAC_VER_19:
5404                 rtl_hw_start_8168c_1(tp);
5405                 break;
5406
5407         case RTL_GIGA_MAC_VER_20:
5408                 rtl_hw_start_8168c_2(tp);
5409                 break;
5410
5411         case RTL_GIGA_MAC_VER_21:
5412                 rtl_hw_start_8168c_3(tp);
5413                 break;
5414
5415         case RTL_GIGA_MAC_VER_22:
5416                 rtl_hw_start_8168c_4(tp);
5417                 break;
5418
5419         case RTL_GIGA_MAC_VER_23:
5420                 rtl_hw_start_8168cp_2(tp);
5421                 break;
5422
5423         case RTL_GIGA_MAC_VER_24:
5424                 rtl_hw_start_8168cp_3(tp);
5425                 break;
5426
5427         case RTL_GIGA_MAC_VER_25:
5428         case RTL_GIGA_MAC_VER_26:
5429         case RTL_GIGA_MAC_VER_27:
5430                 rtl_hw_start_8168d(tp);
5431                 break;
5432
5433         case RTL_GIGA_MAC_VER_28:
5434                 rtl_hw_start_8168d_4(tp);
5435                 break;
5436
5437         case RTL_GIGA_MAC_VER_31:
5438                 rtl_hw_start_8168dp(tp);
5439                 break;
5440
5441         case RTL_GIGA_MAC_VER_32:
5442         case RTL_GIGA_MAC_VER_33:
5443                 rtl_hw_start_8168e_1(tp);
5444                 break;
5445         case RTL_GIGA_MAC_VER_34:
5446                 rtl_hw_start_8168e_2(tp);
5447                 break;
5448
5449         case RTL_GIGA_MAC_VER_35:
5450         case RTL_GIGA_MAC_VER_36:
5451                 rtl_hw_start_8168f_1(tp);
5452                 break;
5453
5454         case RTL_GIGA_MAC_VER_38:
5455                 rtl_hw_start_8411(tp);
5456                 break;
5457
5458         case RTL_GIGA_MAC_VER_40:
5459         case RTL_GIGA_MAC_VER_41:
5460                 rtl_hw_start_8168g_1(tp);
5461                 break;
5462         case RTL_GIGA_MAC_VER_42:
5463                 rtl_hw_start_8168g_2(tp);
5464                 break;
5465
5466         case RTL_GIGA_MAC_VER_44:
5467                 rtl_hw_start_8411_2(tp);
5468                 break;
5469
5470         case RTL_GIGA_MAC_VER_45:
5471         case RTL_GIGA_MAC_VER_46:
5472                 rtl_hw_start_8168h_1(tp);
5473                 break;
5474
5475         case RTL_GIGA_MAC_VER_49:
5476                 rtl_hw_start_8168ep_1(tp);
5477                 break;
5478
5479         case RTL_GIGA_MAC_VER_50:
5480                 rtl_hw_start_8168ep_2(tp);
5481                 break;
5482
5483         case RTL_GIGA_MAC_VER_51:
5484                 rtl_hw_start_8168ep_3(tp);
5485                 break;
5486
5487         default:
5488                 netif_err(tp, drv, tp->dev,
5489                           "unknown chipset (mac_version = %d)\n",
5490                           tp->mac_version);
5491                 break;
5492         }
5493 }
5494
5495 static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)
5496 {
5497         static const struct ephy_info e_info_8102e_1[] = {
5498                 { 0x01, 0, 0x6e65 },
5499                 { 0x02, 0, 0x091f },
5500                 { 0x03, 0, 0xc2f9 },
5501                 { 0x06, 0, 0xafb5 },
5502                 { 0x07, 0, 0x0e00 },
5503                 { 0x19, 0, 0xec80 },
5504                 { 0x01, 0, 0x2e65 },
5505                 { 0x01, 0, 0x6e65 }
5506         };
5507         u8 cfg1;
5508
5509         rtl_set_def_aspm_entry_latency(tp);
5510
5511         RTL_W8(tp, DBG_REG, FIX_NAK_1);
5512
5513         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5514
5515         RTL_W8(tp, Config1,
5516                LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
5517         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
5518
5519         cfg1 = RTL_R8(tp, Config1);
5520         if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
5521                 RTL_W8(tp, Config1, cfg1 & ~LEDS0);
5522
5523         rtl_ephy_init(tp, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
5524 }
5525
5526 static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)
5527 {
5528         rtl_set_def_aspm_entry_latency(tp);
5529
5530         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5531
5532         RTL_W8(tp, Config1, MEMMAP | IOMAP | VPD | PMEnable);
5533         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
5534 }
5535
5536 static void rtl_hw_start_8102e_3(struct rtl8169_private *tp)
5537 {
5538         rtl_hw_start_8102e_2(tp);
5539
5540         rtl_ephy_write(tp, 0x03, 0xc2f9);
5541 }
5542
5543 static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)
5544 {
5545         static const struct ephy_info e_info_8105e_1[] = {
5546                 { 0x07, 0, 0x4000 },
5547                 { 0x19, 0, 0x0200 },
5548                 { 0x19, 0, 0x0020 },
5549                 { 0x1e, 0, 0x2000 },
5550                 { 0x03, 0, 0x0001 },
5551                 { 0x19, 0, 0x0100 },
5552                 { 0x19, 0, 0x0004 },
5553                 { 0x0a, 0, 0x0020 }
5554         };
5555
5556         /* Force LAN exit from ASPM if Rx/Tx are not idle */
5557         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
5558
5559         /* Disable Early Tally Counter */
5560         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) & ~0x010000);
5561
5562         RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
5563         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
5564
5565         rtl_ephy_init(tp, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
5566
5567         rtl_pcie_state_l2l3_enable(tp, false);
5568 }
5569
5570 static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)
5571 {
5572         rtl_hw_start_8105e_1(tp);
5573         rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000);
5574 }
5575
5576 static void rtl_hw_start_8402(struct rtl8169_private *tp)
5577 {
5578         static const struct ephy_info e_info_8402[] = {
5579                 { 0x19, 0xffff, 0xff64 },
5580                 { 0x1e, 0, 0x4000 }
5581         };
5582
5583         rtl_set_def_aspm_entry_latency(tp);
5584
5585         /* Force LAN exit from ASPM if Rx/Tx are not idle */
5586         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
5587
5588         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
5589
5590         rtl_ephy_init(tp, e_info_8402, ARRAY_SIZE(e_info_8402));
5591
5592         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5593
5594         rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00000002, ERIAR_EXGMAC);
5595         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00000006, ERIAR_EXGMAC);
5596         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5597         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5598         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5599         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5600         rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0e00, 0xff00, ERIAR_EXGMAC);
5601
5602         rtl_pcie_state_l2l3_enable(tp, false);
5603 }
5604
5605 static void rtl_hw_start_8106(struct rtl8169_private *tp)
5606 {
5607         rtl_hw_aspm_clkreq_enable(tp, false);
5608
5609         /* Force LAN exit from ASPM if Rx/Tx are not idle */
5610         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
5611
5612         RTL_W32(tp, MISC, (RTL_R32(tp, MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);
5613         RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
5614         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5615
5616         rtl_pcie_state_l2l3_enable(tp, false);
5617         rtl_hw_aspm_clkreq_enable(tp, true);
5618 }
5619
5620 static void rtl_hw_start_8101(struct rtl8169_private *tp)
5621 {
5622         if (tp->mac_version >= RTL_GIGA_MAC_VER_30)
5623                 tp->irq_mask &= ~RxFIFOOver;
5624
5625         if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
5626             tp->mac_version == RTL_GIGA_MAC_VER_16)
5627                 pcie_capability_set_word(tp->pci_dev, PCI_EXP_DEVCTL,
5628                                          PCI_EXP_DEVCTL_NOSNOOP_EN);
5629
5630         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
5631
5632         tp->cp_cmd &= CPCMD_QUIRK_MASK;
5633         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
5634
5635         switch (tp->mac_version) {
5636         case RTL_GIGA_MAC_VER_07:
5637                 rtl_hw_start_8102e_1(tp);
5638                 break;
5639
5640         case RTL_GIGA_MAC_VER_08:
5641                 rtl_hw_start_8102e_3(tp);
5642                 break;
5643
5644         case RTL_GIGA_MAC_VER_09:
5645                 rtl_hw_start_8102e_2(tp);
5646                 break;
5647
5648         case RTL_GIGA_MAC_VER_29:
5649                 rtl_hw_start_8105e_1(tp);
5650                 break;
5651         case RTL_GIGA_MAC_VER_30:
5652                 rtl_hw_start_8105e_2(tp);
5653                 break;
5654
5655         case RTL_GIGA_MAC_VER_37:
5656                 rtl_hw_start_8402(tp);
5657                 break;
5658
5659         case RTL_GIGA_MAC_VER_39:
5660                 rtl_hw_start_8106(tp);
5661                 break;
5662         case RTL_GIGA_MAC_VER_43:
5663                 rtl_hw_start_8168g_2(tp);
5664                 break;
5665         case RTL_GIGA_MAC_VER_47:
5666         case RTL_GIGA_MAC_VER_48:
5667                 rtl_hw_start_8168h_1(tp);
5668                 break;
5669         }
5670
5671         RTL_W16(tp, IntrMitigate, 0x0000);
5672 }
5673
5674 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
5675 {
5676         struct rtl8169_private *tp = netdev_priv(dev);
5677
5678         if (new_mtu > ETH_DATA_LEN)
5679                 rtl_hw_jumbo_enable(tp);
5680         else
5681                 rtl_hw_jumbo_disable(tp);
5682
5683         dev->mtu = new_mtu;
5684         netdev_update_features(dev);
5685
5686         return 0;
5687 }
5688
5689 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
5690 {
5691         desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
5692         desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
5693 }
5694
5695 static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
5696                                      void **data_buff, struct RxDesc *desc)
5697 {
5698         dma_unmap_single(tp_to_dev(tp), le64_to_cpu(desc->addr),
5699                          R8169_RX_BUF_SIZE, DMA_FROM_DEVICE);
5700
5701         kfree(*data_buff);
5702         *data_buff = NULL;
5703         rtl8169_make_unusable_by_asic(desc);
5704 }
5705
5706 static inline void rtl8169_mark_to_asic(struct RxDesc *desc)
5707 {
5708         u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
5709
5710         /* Force memory writes to complete before releasing descriptor */
5711         dma_wmb();
5712
5713         desc->opts1 = cpu_to_le32(DescOwn | eor | R8169_RX_BUF_SIZE);
5714 }
5715
5716 static inline void *rtl8169_align(void *data)
5717 {
5718         return (void *)ALIGN((long)data, 16);
5719 }
5720
5721 static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
5722                                              struct RxDesc *desc)
5723 {
5724         void *data;
5725         dma_addr_t mapping;
5726         struct device *d = tp_to_dev(tp);
5727         int node = dev_to_node(d);
5728
5729         data = kmalloc_node(R8169_RX_BUF_SIZE, GFP_KERNEL, node);
5730         if (!data)
5731                 return NULL;
5732
5733         if (rtl8169_align(data) != data) {
5734                 kfree(data);
5735                 data = kmalloc_node(R8169_RX_BUF_SIZE + 15, GFP_KERNEL, node);
5736                 if (!data)
5737                         return NULL;
5738         }
5739
5740         mapping = dma_map_single(d, rtl8169_align(data), R8169_RX_BUF_SIZE,
5741                                  DMA_FROM_DEVICE);
5742         if (unlikely(dma_mapping_error(d, mapping))) {
5743                 if (net_ratelimit())
5744                         netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
5745                 goto err_out;
5746         }
5747
5748         desc->addr = cpu_to_le64(mapping);
5749         rtl8169_mark_to_asic(desc);
5750         return data;
5751
5752 err_out:
5753         kfree(data);
5754         return NULL;
5755 }
5756
5757 static void rtl8169_rx_clear(struct rtl8169_private *tp)
5758 {
5759         unsigned int i;
5760
5761         for (i = 0; i < NUM_RX_DESC; i++) {
5762                 if (tp->Rx_databuff[i]) {
5763                         rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
5764                                             tp->RxDescArray + i);
5765                 }
5766         }
5767 }
5768
5769 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
5770 {
5771         desc->opts1 |= cpu_to_le32(RingEnd);
5772 }
5773
5774 static int rtl8169_rx_fill(struct rtl8169_private *tp)
5775 {
5776         unsigned int i;
5777
5778         for (i = 0; i < NUM_RX_DESC; i++) {
5779                 void *data;
5780
5781                 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
5782                 if (!data) {
5783                         rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
5784                         goto err_out;
5785                 }
5786                 tp->Rx_databuff[i] = data;
5787         }
5788
5789         rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
5790         return 0;
5791
5792 err_out:
5793         rtl8169_rx_clear(tp);
5794         return -ENOMEM;
5795 }
5796
5797 static int rtl8169_init_ring(struct rtl8169_private *tp)
5798 {
5799         rtl8169_init_ring_indexes(tp);
5800
5801         memset(tp->tx_skb, 0, sizeof(tp->tx_skb));
5802         memset(tp->Rx_databuff, 0, sizeof(tp->Rx_databuff));
5803
5804         return rtl8169_rx_fill(tp);
5805 }
5806
5807 static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
5808                                  struct TxDesc *desc)
5809 {
5810         unsigned int len = tx_skb->len;
5811
5812         dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
5813
5814         desc->opts1 = 0x00;
5815         desc->opts2 = 0x00;
5816         desc->addr = 0x00;
5817         tx_skb->len = 0;
5818 }
5819
5820 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
5821                                    unsigned int n)
5822 {
5823         unsigned int i;
5824
5825         for (i = 0; i < n; i++) {
5826                 unsigned int entry = (start + i) % NUM_TX_DESC;
5827                 struct ring_info *tx_skb = tp->tx_skb + entry;
5828                 unsigned int len = tx_skb->len;
5829
5830                 if (len) {
5831                         struct sk_buff *skb = tx_skb->skb;
5832
5833                         rtl8169_unmap_tx_skb(tp_to_dev(tp), tx_skb,
5834                                              tp->TxDescArray + entry);
5835                         if (skb) {
5836                                 dev_consume_skb_any(skb);
5837                                 tx_skb->skb = NULL;
5838                         }
5839                 }
5840         }
5841 }
5842
5843 static void rtl8169_tx_clear(struct rtl8169_private *tp)
5844 {
5845         rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
5846         tp->cur_tx = tp->dirty_tx = 0;
5847         netdev_reset_queue(tp->dev);
5848 }
5849
5850 static void rtl_reset_work(struct rtl8169_private *tp)
5851 {
5852         struct net_device *dev = tp->dev;
5853         int i;
5854
5855         napi_disable(&tp->napi);
5856         netif_stop_queue(dev);
5857         synchronize_sched();
5858
5859         rtl8169_hw_reset(tp);
5860
5861         for (i = 0; i < NUM_RX_DESC; i++)
5862                 rtl8169_mark_to_asic(tp->RxDescArray + i);
5863
5864         rtl8169_tx_clear(tp);
5865         rtl8169_init_ring_indexes(tp);
5866
5867         napi_enable(&tp->napi);
5868         rtl_hw_start(tp);
5869         netif_wake_queue(dev);
5870 }
5871
5872 static void rtl8169_tx_timeout(struct net_device *dev)
5873 {
5874         struct rtl8169_private *tp = netdev_priv(dev);
5875
5876         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
5877 }
5878
5879 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
5880                               u32 *opts)
5881 {
5882         struct skb_shared_info *info = skb_shinfo(skb);
5883         unsigned int cur_frag, entry;
5884         struct TxDesc *uninitialized_var(txd);
5885         struct device *d = tp_to_dev(tp);
5886
5887         entry = tp->cur_tx;
5888         for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
5889                 const skb_frag_t *frag = info->frags + cur_frag;
5890                 dma_addr_t mapping;
5891                 u32 status, len;
5892                 void *addr;
5893
5894                 entry = (entry + 1) % NUM_TX_DESC;
5895
5896                 txd = tp->TxDescArray + entry;
5897                 len = skb_frag_size(frag);
5898                 addr = skb_frag_address(frag);
5899                 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
5900                 if (unlikely(dma_mapping_error(d, mapping))) {
5901                         if (net_ratelimit())
5902                                 netif_err(tp, drv, tp->dev,
5903                                           "Failed to map TX fragments DMA!\n");
5904                         goto err_out;
5905                 }
5906
5907                 /* Anti gcc 2.95.3 bugware (sic) */
5908                 status = opts[0] | len |
5909                         (RingEnd * !((entry + 1) % NUM_TX_DESC));
5910
5911                 txd->opts1 = cpu_to_le32(status);
5912                 txd->opts2 = cpu_to_le32(opts[1]);
5913                 txd->addr = cpu_to_le64(mapping);
5914
5915                 tp->tx_skb[entry].len = len;
5916         }
5917
5918         if (cur_frag) {
5919                 tp->tx_skb[entry].skb = skb;
5920                 txd->opts1 |= cpu_to_le32(LastFrag);
5921         }
5922
5923         return cur_frag;
5924
5925 err_out:
5926         rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
5927         return -EIO;
5928 }
5929
5930 static bool rtl_test_hw_pad_bug(struct rtl8169_private *tp, struct sk_buff *skb)
5931 {
5932         return skb->len < ETH_ZLEN && tp->mac_version == RTL_GIGA_MAC_VER_34;
5933 }
5934
5935 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
5936                                       struct net_device *dev);
5937 /* r8169_csum_workaround()
5938  * The hw limites the value the transport offset. When the offset is out of the
5939  * range, calculate the checksum by sw.
5940  */
5941 static void r8169_csum_workaround(struct rtl8169_private *tp,
5942                                   struct sk_buff *skb)
5943 {
5944         if (skb_shinfo(skb)->gso_size) {
5945                 netdev_features_t features = tp->dev->features;
5946                 struct sk_buff *segs, *nskb;
5947
5948                 features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
5949                 segs = skb_gso_segment(skb, features);
5950                 if (IS_ERR(segs) || !segs)
5951                         goto drop;
5952
5953                 do {
5954                         nskb = segs;
5955                         segs = segs->next;
5956                         nskb->next = NULL;
5957                         rtl8169_start_xmit(nskb, tp->dev);
5958                 } while (segs);
5959
5960                 dev_consume_skb_any(skb);
5961         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5962                 if (skb_checksum_help(skb) < 0)
5963                         goto drop;
5964
5965                 rtl8169_start_xmit(skb, tp->dev);
5966         } else {
5967                 struct net_device_stats *stats;
5968
5969 drop:
5970                 stats = &tp->dev->stats;
5971                 stats->tx_dropped++;
5972                 dev_kfree_skb_any(skb);
5973         }
5974 }
5975
5976 /* msdn_giant_send_check()
5977  * According to the document of microsoft, the TCP Pseudo Header excludes the
5978  * packet length for IPv6 TCP large packets.
5979  */
5980 static int msdn_giant_send_check(struct sk_buff *skb)
5981 {
5982         const struct ipv6hdr *ipv6h;
5983         struct tcphdr *th;
5984         int ret;
5985
5986         ret = skb_cow_head(skb, 0);
5987         if (ret)
5988                 return ret;
5989
5990         ipv6h = ipv6_hdr(skb);
5991         th = tcp_hdr(skb);
5992
5993         th->check = 0;
5994         th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0);
5995
5996         return ret;
5997 }
5998
5999 static bool rtl8169_tso_csum_v1(struct rtl8169_private *tp,
6000                                 struct sk_buff *skb, u32 *opts)
6001 {
6002         u32 mss = skb_shinfo(skb)->gso_size;
6003
6004         if (mss) {
6005                 opts[0] |= TD_LSO;
6006                 opts[0] |= min(mss, TD_MSS_MAX) << TD0_MSS_SHIFT;
6007         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
6008                 const struct iphdr *ip = ip_hdr(skb);
6009
6010                 if (ip->protocol == IPPROTO_TCP)
6011                         opts[0] |= TD0_IP_CS | TD0_TCP_CS;
6012                 else if (ip->protocol == IPPROTO_UDP)
6013                         opts[0] |= TD0_IP_CS | TD0_UDP_CS;
6014                 else
6015                         WARN_ON_ONCE(1);
6016         }
6017
6018         return true;
6019 }
6020
6021 static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp,
6022                                 struct sk_buff *skb, u32 *opts)
6023 {
6024         u32 transport_offset = (u32)skb_transport_offset(skb);
6025         u32 mss = skb_shinfo(skb)->gso_size;
6026
6027         if (mss) {
6028                 if (transport_offset > GTTCPHO_MAX) {
6029                         netif_warn(tp, tx_err, tp->dev,
6030                                    "Invalid transport offset 0x%x for TSO\n",
6031                                    transport_offset);
6032                         return false;
6033                 }
6034
6035                 switch (vlan_get_protocol(skb)) {
6036                 case htons(ETH_P_IP):
6037                         opts[0] |= TD1_GTSENV4;
6038                         break;
6039
6040                 case htons(ETH_P_IPV6):
6041                         if (msdn_giant_send_check(skb))
6042                                 return false;
6043
6044                         opts[0] |= TD1_GTSENV6;
6045                         break;
6046
6047                 default:
6048                         WARN_ON_ONCE(1);
6049                         break;
6050                 }
6051
6052                 opts[0] |= transport_offset << GTTCPHO_SHIFT;
6053                 opts[1] |= min(mss, TD_MSS_MAX) << TD1_MSS_SHIFT;
6054         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
6055                 u8 ip_protocol;
6056
6057                 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
6058                         return !(skb_checksum_help(skb) || eth_skb_pad(skb));
6059
6060                 if (transport_offset > TCPHO_MAX) {
6061                         netif_warn(tp, tx_err, tp->dev,
6062                                    "Invalid transport offset 0x%x\n",
6063                                    transport_offset);
6064                         return false;
6065                 }
6066
6067                 switch (vlan_get_protocol(skb)) {
6068                 case htons(ETH_P_IP):
6069                         opts[1] |= TD1_IPv4_CS;
6070                         ip_protocol = ip_hdr(skb)->protocol;
6071                         break;
6072
6073                 case htons(ETH_P_IPV6):
6074                         opts[1] |= TD1_IPv6_CS;
6075                         ip_protocol = ipv6_hdr(skb)->nexthdr;
6076                         break;
6077
6078                 default:
6079                         ip_protocol = IPPROTO_RAW;
6080                         break;
6081                 }
6082
6083                 if (ip_protocol == IPPROTO_TCP)
6084                         opts[1] |= TD1_TCP_CS;
6085                 else if (ip_protocol == IPPROTO_UDP)
6086                         opts[1] |= TD1_UDP_CS;
6087                 else
6088                         WARN_ON_ONCE(1);
6089
6090                 opts[1] |= transport_offset << TCPHO_SHIFT;
6091         } else {
6092                 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
6093                         return !eth_skb_pad(skb);
6094         }
6095
6096         return true;
6097 }
6098
6099 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
6100                                       struct net_device *dev)
6101 {
6102         struct rtl8169_private *tp = netdev_priv(dev);
6103         unsigned int entry = tp->cur_tx % NUM_TX_DESC;
6104         struct TxDesc *txd = tp->TxDescArray + entry;
6105         struct device *d = tp_to_dev(tp);
6106         dma_addr_t mapping;
6107         u32 status, len;
6108         u32 opts[2];
6109         int frags;
6110
6111         if (unlikely(!TX_FRAGS_READY_FOR(tp, skb_shinfo(skb)->nr_frags))) {
6112                 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
6113                 goto err_stop_0;
6114         }
6115
6116         if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
6117                 goto err_stop_0;
6118
6119         opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(skb));
6120         opts[0] = DescOwn;
6121
6122         if (!tp->tso_csum(tp, skb, opts)) {
6123                 r8169_csum_workaround(tp, skb);
6124                 return NETDEV_TX_OK;
6125         }
6126
6127         len = skb_headlen(skb);
6128         mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
6129         if (unlikely(dma_mapping_error(d, mapping))) {
6130                 if (net_ratelimit())
6131                         netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
6132                 goto err_dma_0;
6133         }
6134
6135         tp->tx_skb[entry].len = len;
6136         txd->addr = cpu_to_le64(mapping);
6137
6138         frags = rtl8169_xmit_frags(tp, skb, opts);
6139         if (frags < 0)
6140                 goto err_dma_1;
6141         else if (frags)
6142                 opts[0] |= FirstFrag;
6143         else {
6144                 opts[0] |= FirstFrag | LastFrag;
6145                 tp->tx_skb[entry].skb = skb;
6146         }
6147
6148         txd->opts2 = cpu_to_le32(opts[1]);
6149
6150         netdev_sent_queue(dev, skb->len);
6151
6152         skb_tx_timestamp(skb);
6153
6154         /* Force memory writes to complete before releasing descriptor */
6155         dma_wmb();
6156
6157         /* Anti gcc 2.95.3 bugware (sic) */
6158         status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
6159         txd->opts1 = cpu_to_le32(status);
6160
6161         /* Force all memory writes to complete before notifying device */
6162         wmb();
6163
6164         tp->cur_tx += frags + 1;
6165
6166         RTL_W8(tp, TxPoll, NPQ);
6167
6168         mmiowb();
6169
6170         if (!TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
6171                 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
6172                  * not miss a ring update when it notices a stopped queue.
6173                  */
6174                 smp_wmb();
6175                 netif_stop_queue(dev);
6176                 /* Sync with rtl_tx:
6177                  * - publish queue status and cur_tx ring index (write barrier)
6178                  * - refresh dirty_tx ring index (read barrier).
6179                  * May the current thread have a pessimistic view of the ring
6180                  * status and forget to wake up queue, a racing rtl_tx thread
6181                  * can't.
6182                  */
6183                 smp_mb();
6184                 if (TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS))
6185                         netif_wake_queue(dev);
6186         }
6187
6188         return NETDEV_TX_OK;
6189
6190 err_dma_1:
6191         rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
6192 err_dma_0:
6193         dev_kfree_skb_any(skb);
6194         dev->stats.tx_dropped++;
6195         return NETDEV_TX_OK;
6196
6197 err_stop_0:
6198         netif_stop_queue(dev);
6199         dev->stats.tx_dropped++;
6200         return NETDEV_TX_BUSY;
6201 }
6202
6203 static void rtl8169_pcierr_interrupt(struct net_device *dev)
6204 {
6205         struct rtl8169_private *tp = netdev_priv(dev);
6206         struct pci_dev *pdev = tp->pci_dev;
6207         u16 pci_status, pci_cmd;
6208
6209         pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
6210         pci_read_config_word(pdev, PCI_STATUS, &pci_status);
6211
6212         netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
6213                   pci_cmd, pci_status);
6214
6215         /*
6216          * The recovery sequence below admits a very elaborated explanation:
6217          * - it seems to work;
6218          * - I did not see what else could be done;
6219          * - it makes iop3xx happy.
6220          *
6221          * Feel free to adjust to your needs.
6222          */
6223         if (pdev->broken_parity_status)
6224                 pci_cmd &= ~PCI_COMMAND_PARITY;
6225         else
6226                 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
6227
6228         pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
6229
6230         pci_write_config_word(pdev, PCI_STATUS,
6231                 pci_status & (PCI_STATUS_DETECTED_PARITY |
6232                 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
6233                 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
6234
6235         /* The infamous DAC f*ckup only happens at boot time */
6236         if ((tp->cp_cmd & PCIDAC) && !tp->cur_rx) {
6237                 netif_info(tp, intr, dev, "disabling PCI DAC\n");
6238                 tp->cp_cmd &= ~PCIDAC;
6239                 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
6240                 dev->features &= ~NETIF_F_HIGHDMA;
6241         }
6242
6243         rtl8169_hw_reset(tp);
6244
6245         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
6246 }
6247
6248 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp)
6249 {
6250         unsigned int dirty_tx, tx_left, bytes_compl = 0, pkts_compl = 0;
6251
6252         dirty_tx = tp->dirty_tx;
6253         smp_rmb();
6254         tx_left = tp->cur_tx - dirty_tx;
6255
6256         while (tx_left > 0) {
6257                 unsigned int entry = dirty_tx % NUM_TX_DESC;
6258                 struct ring_info *tx_skb = tp->tx_skb + entry;
6259                 u32 status;
6260
6261                 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
6262                 if (status & DescOwn)
6263                         break;
6264
6265                 /* This barrier is needed to keep us from reading
6266                  * any other fields out of the Tx descriptor until
6267                  * we know the status of DescOwn
6268                  */
6269                 dma_rmb();
6270
6271                 rtl8169_unmap_tx_skb(tp_to_dev(tp), tx_skb,
6272                                      tp->TxDescArray + entry);
6273                 if (status & LastFrag) {
6274                         pkts_compl++;
6275                         bytes_compl += tx_skb->skb->len;
6276                         dev_consume_skb_any(tx_skb->skb);
6277                         tx_skb->skb = NULL;
6278                 }
6279                 dirty_tx++;
6280                 tx_left--;
6281         }
6282
6283         if (tp->dirty_tx != dirty_tx) {
6284                 netdev_completed_queue(dev, pkts_compl, bytes_compl);
6285
6286                 u64_stats_update_begin(&tp->tx_stats.syncp);
6287                 tp->tx_stats.packets += pkts_compl;
6288                 tp->tx_stats.bytes += bytes_compl;
6289                 u64_stats_update_end(&tp->tx_stats.syncp);
6290
6291                 tp->dirty_tx = dirty_tx;
6292                 /* Sync with rtl8169_start_xmit:
6293                  * - publish dirty_tx ring index (write barrier)
6294                  * - refresh cur_tx ring index and queue status (read barrier)
6295                  * May the current thread miss the stopped queue condition,
6296                  * a racing xmit thread can only have a right view of the
6297                  * ring status.
6298                  */
6299                 smp_mb();
6300                 if (netif_queue_stopped(dev) &&
6301                     TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
6302                         netif_wake_queue(dev);
6303                 }
6304                 /*
6305                  * 8168 hack: TxPoll requests are lost when the Tx packets are
6306                  * too close. Let's kick an extra TxPoll request when a burst
6307                  * of start_xmit activity is detected (if it is not detected,
6308                  * it is slow enough). -- FR
6309                  */
6310                 if (tp->cur_tx != dirty_tx)
6311                         RTL_W8(tp, TxPoll, NPQ);
6312         }
6313 }
6314
6315 static inline int rtl8169_fragmented_frame(u32 status)
6316 {
6317         return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
6318 }
6319
6320 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
6321 {
6322         u32 status = opts1 & RxProtoMask;
6323
6324         if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
6325             ((status == RxProtoUDP) && !(opts1 & UDPFail)))
6326                 skb->ip_summed = CHECKSUM_UNNECESSARY;
6327         else
6328                 skb_checksum_none_assert(skb);
6329 }
6330
6331 static struct sk_buff *rtl8169_try_rx_copy(void *data,
6332                                            struct rtl8169_private *tp,
6333                                            int pkt_size,
6334                                            dma_addr_t addr)
6335 {
6336         struct sk_buff *skb;
6337         struct device *d = tp_to_dev(tp);
6338
6339         data = rtl8169_align(data);
6340         dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
6341         prefetch(data);
6342         skb = napi_alloc_skb(&tp->napi, pkt_size);
6343         if (skb)
6344                 skb_copy_to_linear_data(skb, data, pkt_size);
6345         dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
6346
6347         return skb;
6348 }
6349
6350 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget)
6351 {
6352         unsigned int cur_rx, rx_left;
6353         unsigned int count;
6354
6355         cur_rx = tp->cur_rx;
6356
6357         for (rx_left = min(budget, NUM_RX_DESC); rx_left > 0; rx_left--, cur_rx++) {
6358                 unsigned int entry = cur_rx % NUM_RX_DESC;
6359                 struct RxDesc *desc = tp->RxDescArray + entry;
6360                 u32 status;
6361
6362                 status = le32_to_cpu(desc->opts1);
6363                 if (status & DescOwn)
6364                         break;
6365
6366                 /* This barrier is needed to keep us from reading
6367                  * any other fields out of the Rx descriptor until
6368                  * we know the status of DescOwn
6369                  */
6370                 dma_rmb();
6371
6372                 if (unlikely(status & RxRES)) {
6373                         netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
6374                                    status);
6375                         dev->stats.rx_errors++;
6376                         if (status & (RxRWT | RxRUNT))
6377                                 dev->stats.rx_length_errors++;
6378                         if (status & RxCRC)
6379                                 dev->stats.rx_crc_errors++;
6380                         /* RxFOVF is a reserved bit on later chip versions */
6381                         if (tp->mac_version == RTL_GIGA_MAC_VER_01 &&
6382                             status & RxFOVF) {
6383                                 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
6384                                 dev->stats.rx_fifo_errors++;
6385                         } else if (status & (RxRUNT | RxCRC) &&
6386                                    !(status & RxRWT) &&
6387                                    dev->features & NETIF_F_RXALL) {
6388                                 goto process_pkt;
6389                         }
6390                 } else {
6391                         struct sk_buff *skb;
6392                         dma_addr_t addr;
6393                         int pkt_size;
6394
6395 process_pkt:
6396                         addr = le64_to_cpu(desc->addr);
6397                         if (likely(!(dev->features & NETIF_F_RXFCS)))
6398                                 pkt_size = (status & 0x00003fff) - 4;
6399                         else
6400                                 pkt_size = status & 0x00003fff;
6401
6402                         /*
6403                          * The driver does not support incoming fragmented
6404                          * frames. They are seen as a symptom of over-mtu
6405                          * sized frames.
6406                          */
6407                         if (unlikely(rtl8169_fragmented_frame(status))) {
6408                                 dev->stats.rx_dropped++;
6409                                 dev->stats.rx_length_errors++;
6410                                 goto release_descriptor;
6411                         }
6412
6413                         skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
6414                                                   tp, pkt_size, addr);
6415                         if (!skb) {
6416                                 dev->stats.rx_dropped++;
6417                                 goto release_descriptor;
6418                         }
6419
6420                         rtl8169_rx_csum(skb, status);
6421                         skb_put(skb, pkt_size);
6422                         skb->protocol = eth_type_trans(skb, dev);
6423
6424                         rtl8169_rx_vlan_tag(desc, skb);
6425
6426                         if (skb->pkt_type == PACKET_MULTICAST)
6427                                 dev->stats.multicast++;
6428
6429                         napi_gro_receive(&tp->napi, skb);
6430
6431                         u64_stats_update_begin(&tp->rx_stats.syncp);
6432                         tp->rx_stats.packets++;
6433                         tp->rx_stats.bytes += pkt_size;
6434                         u64_stats_update_end(&tp->rx_stats.syncp);
6435                 }
6436 release_descriptor:
6437                 desc->opts2 = 0;
6438                 rtl8169_mark_to_asic(desc);
6439         }
6440
6441         count = cur_rx - tp->cur_rx;
6442         tp->cur_rx = cur_rx;
6443
6444         return count;
6445 }
6446
6447 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
6448 {
6449         struct rtl8169_private *tp = dev_instance;
6450         u16 status = rtl_get_events(tp);
6451
6452         if (status == 0xffff || !(status & tp->irq_mask))
6453                 return IRQ_NONE;
6454
6455         if (unlikely(status & SYSErr)) {
6456                 rtl8169_pcierr_interrupt(tp->dev);
6457                 goto out;
6458         }
6459
6460         if (status & LinkChg)
6461                 phy_mac_interrupt(tp->dev->phydev);
6462
6463         if (unlikely(status & RxFIFOOver &&
6464             tp->mac_version == RTL_GIGA_MAC_VER_11)) {
6465                 netif_stop_queue(tp->dev);
6466                 /* XXX - Hack alert. See rtl_task(). */
6467                 set_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags);
6468         }
6469
6470         if (status & RTL_EVENT_NAPI) {
6471                 rtl_irq_disable(tp);
6472                 napi_schedule_irqoff(&tp->napi);
6473         }
6474 out:
6475         rtl_ack_events(tp, status);
6476
6477         return IRQ_HANDLED;
6478 }
6479
6480 static void rtl_task(struct work_struct *work)
6481 {
6482         static const struct {
6483                 int bitnr;
6484                 void (*action)(struct rtl8169_private *);
6485         } rtl_work[] = {
6486                 { RTL_FLAG_TASK_RESET_PENDING,  rtl_reset_work },
6487         };
6488         struct rtl8169_private *tp =
6489                 container_of(work, struct rtl8169_private, wk.work);
6490         struct net_device *dev = tp->dev;
6491         int i;
6492
6493         rtl_lock_work(tp);
6494
6495         if (!netif_running(dev) ||
6496             !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
6497                 goto out_unlock;
6498
6499         for (i = 0; i < ARRAY_SIZE(rtl_work); i++) {
6500                 bool pending;
6501
6502                 pending = test_and_clear_bit(rtl_work[i].bitnr, tp->wk.flags);
6503                 if (pending)
6504                         rtl_work[i].action(tp);
6505         }
6506
6507 out_unlock:
6508         rtl_unlock_work(tp);
6509 }
6510
6511 static int rtl8169_poll(struct napi_struct *napi, int budget)
6512 {
6513         struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
6514         struct net_device *dev = tp->dev;
6515         int work_done;
6516
6517         work_done = rtl_rx(dev, tp, (u32) budget);
6518
6519         rtl_tx(dev, tp);
6520
6521         if (work_done < budget) {
6522                 napi_complete_done(napi, work_done);
6523
6524                 rtl_irq_enable(tp);
6525                 mmiowb();
6526         }
6527
6528         return work_done;
6529 }
6530
6531 static void rtl8169_rx_missed(struct net_device *dev)
6532 {
6533         struct rtl8169_private *tp = netdev_priv(dev);
6534
6535         if (tp->mac_version > RTL_GIGA_MAC_VER_06)
6536                 return;
6537
6538         dev->stats.rx_missed_errors += RTL_R32(tp, RxMissed) & 0xffffff;
6539         RTL_W32(tp, RxMissed, 0);
6540 }
6541
6542 static void r8169_phylink_handler(struct net_device *ndev)
6543 {
6544         struct rtl8169_private *tp = netdev_priv(ndev);
6545
6546         if (netif_carrier_ok(ndev)) {
6547                 rtl_link_chg_patch(tp);
6548                 pm_request_resume(&tp->pci_dev->dev);
6549         } else {
6550                 pm_runtime_idle(&tp->pci_dev->dev);
6551         }
6552
6553         if (net_ratelimit())
6554                 phy_print_status(ndev->phydev);
6555 }
6556
6557 static int r8169_phy_connect(struct rtl8169_private *tp)
6558 {
6559         struct phy_device *phydev = mdiobus_get_phy(tp->mii_bus, 0);
6560         phy_interface_t phy_mode;
6561         int ret;
6562
6563         phy_mode = tp->supports_gmii ? PHY_INTERFACE_MODE_GMII :
6564                    PHY_INTERFACE_MODE_MII;
6565
6566         ret = phy_connect_direct(tp->dev, phydev, r8169_phylink_handler,
6567                                  phy_mode);
6568         if (ret)
6569                 return ret;
6570
6571         if (!tp->supports_gmii)
6572                 phy_set_max_speed(phydev, SPEED_100);
6573
6574         /* Ensure to advertise everything, incl. pause */
6575         linkmode_copy(phydev->advertising, phydev->supported);
6576
6577         phy_attached_info(phydev);
6578
6579         return 0;
6580 }
6581
6582 static void rtl8169_down(struct net_device *dev)
6583 {
6584         struct rtl8169_private *tp = netdev_priv(dev);
6585
6586         phy_stop(dev->phydev);
6587
6588         napi_disable(&tp->napi);
6589         netif_stop_queue(dev);
6590
6591         rtl8169_hw_reset(tp);
6592         /*
6593          * At this point device interrupts can not be enabled in any function,
6594          * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task)
6595          * and napi is disabled (rtl8169_poll).
6596          */
6597         rtl8169_rx_missed(dev);
6598
6599         /* Give a racing hard_start_xmit a few cycles to complete. */
6600         synchronize_sched();
6601
6602         rtl8169_tx_clear(tp);
6603
6604         rtl8169_rx_clear(tp);
6605
6606         rtl_pll_power_down(tp);
6607 }
6608
6609 static int rtl8169_close(struct net_device *dev)
6610 {
6611         struct rtl8169_private *tp = netdev_priv(dev);
6612         struct pci_dev *pdev = tp->pci_dev;
6613
6614         pm_runtime_get_sync(&pdev->dev);
6615
6616         /* Update counters before going down */
6617         rtl8169_update_counters(tp);
6618
6619         rtl_lock_work(tp);
6620         /* Clear all task flags */
6621         bitmap_zero(tp->wk.flags, RTL_FLAG_MAX);
6622
6623         rtl8169_down(dev);
6624         rtl_unlock_work(tp);
6625
6626         cancel_work_sync(&tp->wk.work);
6627
6628         phy_disconnect(dev->phydev);
6629
6630         pci_free_irq(pdev, 0, tp);
6631
6632         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6633                           tp->RxPhyAddr);
6634         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6635                           tp->TxPhyAddr);
6636         tp->TxDescArray = NULL;
6637         tp->RxDescArray = NULL;
6638
6639         pm_runtime_put_sync(&pdev->dev);
6640
6641         return 0;
6642 }
6643
6644 #ifdef CONFIG_NET_POLL_CONTROLLER
6645 static void rtl8169_netpoll(struct net_device *dev)
6646 {
6647         struct rtl8169_private *tp = netdev_priv(dev);
6648
6649         rtl8169_interrupt(pci_irq_vector(tp->pci_dev, 0), tp);
6650 }
6651 #endif
6652
6653 static int rtl_open(struct net_device *dev)
6654 {
6655         struct rtl8169_private *tp = netdev_priv(dev);
6656         struct pci_dev *pdev = tp->pci_dev;
6657         int retval = -ENOMEM;
6658
6659         pm_runtime_get_sync(&pdev->dev);
6660
6661         /*
6662          * Rx and Tx descriptors needs 256 bytes alignment.
6663          * dma_alloc_coherent provides more.
6664          */
6665         tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
6666                                              &tp->TxPhyAddr, GFP_KERNEL);
6667         if (!tp->TxDescArray)
6668                 goto err_pm_runtime_put;
6669
6670         tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
6671                                              &tp->RxPhyAddr, GFP_KERNEL);
6672         if (!tp->RxDescArray)
6673                 goto err_free_tx_0;
6674
6675         retval = rtl8169_init_ring(tp);
6676         if (retval < 0)
6677                 goto err_free_rx_1;
6678
6679         INIT_WORK(&tp->wk.work, rtl_task);
6680
6681         smp_mb();
6682
6683         rtl_request_firmware(tp);
6684
6685         retval = pci_request_irq(pdev, 0, rtl8169_interrupt, NULL, tp,
6686                                  dev->name);
6687         if (retval < 0)
6688                 goto err_release_fw_2;
6689
6690         retval = r8169_phy_connect(tp);
6691         if (retval)
6692                 goto err_free_irq;
6693
6694         rtl_lock_work(tp);
6695
6696         set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6697
6698         napi_enable(&tp->napi);
6699
6700         rtl8169_init_phy(dev, tp);
6701
6702         rtl_pll_power_up(tp);
6703
6704         rtl_hw_start(tp);
6705
6706         if (!rtl8169_init_counter_offsets(tp))
6707                 netif_warn(tp, hw, dev, "counter reset/update failed\n");
6708
6709         phy_start(dev->phydev);
6710         netif_start_queue(dev);
6711
6712         rtl_unlock_work(tp);
6713
6714         pm_runtime_put_sync(&pdev->dev);
6715 out:
6716         return retval;
6717
6718 err_free_irq:
6719         pci_free_irq(pdev, 0, tp);
6720 err_release_fw_2:
6721         rtl_release_firmware(tp);
6722         rtl8169_rx_clear(tp);
6723 err_free_rx_1:
6724         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6725                           tp->RxPhyAddr);
6726         tp->RxDescArray = NULL;
6727 err_free_tx_0:
6728         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6729                           tp->TxPhyAddr);
6730         tp->TxDescArray = NULL;
6731 err_pm_runtime_put:
6732         pm_runtime_put_noidle(&pdev->dev);
6733         goto out;
6734 }
6735
6736 static void
6737 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
6738 {
6739         struct rtl8169_private *tp = netdev_priv(dev);
6740         struct pci_dev *pdev = tp->pci_dev;
6741         struct rtl8169_counters *counters = tp->counters;
6742         unsigned int start;
6743
6744         pm_runtime_get_noresume(&pdev->dev);
6745
6746         if (netif_running(dev) && pm_runtime_active(&pdev->dev))
6747                 rtl8169_rx_missed(dev);
6748
6749         do {
6750                 start = u64_stats_fetch_begin_irq(&tp->rx_stats.syncp);
6751                 stats->rx_packets = tp->rx_stats.packets;
6752                 stats->rx_bytes = tp->rx_stats.bytes;
6753         } while (u64_stats_fetch_retry_irq(&tp->rx_stats.syncp, start));
6754
6755         do {
6756                 start = u64_stats_fetch_begin_irq(&tp->tx_stats.syncp);
6757                 stats->tx_packets = tp->tx_stats.packets;
6758                 stats->tx_bytes = tp->tx_stats.bytes;
6759         } while (u64_stats_fetch_retry_irq(&tp->tx_stats.syncp, start));
6760
6761         stats->rx_dropped       = dev->stats.rx_dropped;
6762         stats->tx_dropped       = dev->stats.tx_dropped;
6763         stats->rx_length_errors = dev->stats.rx_length_errors;
6764         stats->rx_errors        = dev->stats.rx_errors;
6765         stats->rx_crc_errors    = dev->stats.rx_crc_errors;
6766         stats->rx_fifo_errors   = dev->stats.rx_fifo_errors;
6767         stats->rx_missed_errors = dev->stats.rx_missed_errors;
6768         stats->multicast        = dev->stats.multicast;
6769
6770         /*
6771          * Fetch additonal counter values missing in stats collected by driver
6772          * from tally counters.
6773          */
6774         if (pm_runtime_active(&pdev->dev))
6775                 rtl8169_update_counters(tp);
6776
6777         /*
6778          * Subtract values fetched during initalization.
6779          * See rtl8169_init_counter_offsets for a description why we do that.
6780          */
6781         stats->tx_errors = le64_to_cpu(counters->tx_errors) -
6782                 le64_to_cpu(tp->tc_offset.tx_errors);
6783         stats->collisions = le32_to_cpu(counters->tx_multi_collision) -
6784                 le32_to_cpu(tp->tc_offset.tx_multi_collision);
6785         stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) -
6786                 le16_to_cpu(tp->tc_offset.tx_aborted);
6787
6788         pm_runtime_put_noidle(&pdev->dev);
6789 }
6790
6791 static void rtl8169_net_suspend(struct net_device *dev)
6792 {
6793         struct rtl8169_private *tp = netdev_priv(dev);
6794
6795         if (!netif_running(dev))
6796                 return;
6797
6798         phy_stop(dev->phydev);
6799         netif_device_detach(dev);
6800
6801         rtl_lock_work(tp);
6802         napi_disable(&tp->napi);
6803         /* Clear all task flags */
6804         bitmap_zero(tp->wk.flags, RTL_FLAG_MAX);
6805
6806         rtl_unlock_work(tp);
6807
6808         rtl_pll_power_down(tp);
6809 }
6810
6811 #ifdef CONFIG_PM
6812
6813 static int rtl8169_suspend(struct device *device)
6814 {
6815         struct net_device *dev = dev_get_drvdata(device);
6816         struct rtl8169_private *tp = netdev_priv(dev);
6817
6818         rtl8169_net_suspend(dev);
6819         clk_disable_unprepare(tp->clk);
6820
6821         return 0;
6822 }
6823
6824 static void __rtl8169_resume(struct net_device *dev)
6825 {
6826         struct rtl8169_private *tp = netdev_priv(dev);
6827
6828         netif_device_attach(dev);
6829
6830         rtl_pll_power_up(tp);
6831         rtl8169_init_phy(dev, tp);
6832
6833         phy_start(tp->dev->phydev);
6834
6835         rtl_lock_work(tp);
6836         napi_enable(&tp->napi);
6837         set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6838         rtl_unlock_work(tp);
6839
6840         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
6841 }
6842
6843 static int rtl8169_resume(struct device *device)
6844 {
6845         struct net_device *dev = dev_get_drvdata(device);
6846         struct rtl8169_private *tp = netdev_priv(dev);
6847
6848         clk_prepare_enable(tp->clk);
6849
6850         if (netif_running(dev))
6851                 __rtl8169_resume(dev);
6852
6853         return 0;
6854 }
6855
6856 static int rtl8169_runtime_suspend(struct device *device)
6857 {
6858         struct net_device *dev = dev_get_drvdata(device);
6859         struct rtl8169_private *tp = netdev_priv(dev);
6860
6861         if (!tp->TxDescArray)
6862                 return 0;
6863
6864         rtl_lock_work(tp);
6865         __rtl8169_set_wol(tp, WAKE_ANY);
6866         rtl_unlock_work(tp);
6867
6868         rtl8169_net_suspend(dev);
6869
6870         /* Update counters before going runtime suspend */
6871         rtl8169_rx_missed(dev);
6872         rtl8169_update_counters(tp);
6873
6874         return 0;
6875 }
6876
6877 static int rtl8169_runtime_resume(struct device *device)
6878 {
6879         struct net_device *dev = dev_get_drvdata(device);
6880         struct rtl8169_private *tp = netdev_priv(dev);
6881         rtl_rar_set(tp, dev->dev_addr);
6882
6883         if (!tp->TxDescArray)
6884                 return 0;
6885
6886         rtl_lock_work(tp);
6887         __rtl8169_set_wol(tp, tp->saved_wolopts);
6888         rtl_unlock_work(tp);
6889
6890         __rtl8169_resume(dev);
6891
6892         return 0;
6893 }
6894
6895 static int rtl8169_runtime_idle(struct device *device)
6896 {
6897         struct net_device *dev = dev_get_drvdata(device);
6898
6899         if (!netif_running(dev) || !netif_carrier_ok(dev))
6900                 pm_schedule_suspend(device, 10000);
6901
6902         return -EBUSY;
6903 }
6904
6905 static const struct dev_pm_ops rtl8169_pm_ops = {
6906         .suspend                = rtl8169_suspend,
6907         .resume                 = rtl8169_resume,
6908         .freeze                 = rtl8169_suspend,
6909         .thaw                   = rtl8169_resume,
6910         .poweroff               = rtl8169_suspend,
6911         .restore                = rtl8169_resume,
6912         .runtime_suspend        = rtl8169_runtime_suspend,
6913         .runtime_resume         = rtl8169_runtime_resume,
6914         .runtime_idle           = rtl8169_runtime_idle,
6915 };
6916
6917 #define RTL8169_PM_OPS  (&rtl8169_pm_ops)
6918
6919 #else /* !CONFIG_PM */
6920
6921 #define RTL8169_PM_OPS  NULL
6922
6923 #endif /* !CONFIG_PM */
6924
6925 static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
6926 {
6927         /* WoL fails with 8168b when the receiver is disabled. */
6928         switch (tp->mac_version) {
6929         case RTL_GIGA_MAC_VER_11:
6930         case RTL_GIGA_MAC_VER_12:
6931         case RTL_GIGA_MAC_VER_17:
6932                 pci_clear_master(tp->pci_dev);
6933
6934                 RTL_W8(tp, ChipCmd, CmdRxEnb);
6935                 /* PCI commit */
6936                 RTL_R8(tp, ChipCmd);
6937                 break;
6938         default:
6939                 break;
6940         }
6941 }
6942
6943 static void rtl_shutdown(struct pci_dev *pdev)
6944 {
6945         struct net_device *dev = pci_get_drvdata(pdev);
6946         struct rtl8169_private *tp = netdev_priv(dev);
6947
6948         rtl8169_net_suspend(dev);
6949
6950         /* Restore original MAC address */
6951         rtl_rar_set(tp, dev->perm_addr);
6952
6953         rtl8169_hw_reset(tp);
6954
6955         if (system_state == SYSTEM_POWER_OFF) {
6956                 if (tp->saved_wolopts) {
6957                         rtl_wol_suspend_quirk(tp);
6958                         rtl_wol_shutdown_quirk(tp);
6959                 }
6960
6961                 pci_wake_from_d3(pdev, true);
6962                 pci_set_power_state(pdev, PCI_D3hot);
6963         }
6964 }
6965
6966 static void rtl_remove_one(struct pci_dev *pdev)
6967 {
6968         struct net_device *dev = pci_get_drvdata(pdev);
6969         struct rtl8169_private *tp = netdev_priv(dev);
6970
6971         if (r8168_check_dash(tp))
6972                 rtl8168_driver_stop(tp);
6973
6974         netif_napi_del(&tp->napi);
6975
6976         unregister_netdev(dev);
6977         mdiobus_unregister(tp->mii_bus);
6978
6979         rtl_release_firmware(tp);
6980
6981         if (pci_dev_run_wake(pdev))
6982                 pm_runtime_get_noresume(&pdev->dev);
6983
6984         /* restore original MAC address */
6985         rtl_rar_set(tp, dev->perm_addr);
6986 }
6987
6988 static const struct net_device_ops rtl_netdev_ops = {
6989         .ndo_open               = rtl_open,
6990         .ndo_stop               = rtl8169_close,
6991         .ndo_get_stats64        = rtl8169_get_stats64,
6992         .ndo_start_xmit         = rtl8169_start_xmit,
6993         .ndo_tx_timeout         = rtl8169_tx_timeout,
6994         .ndo_validate_addr      = eth_validate_addr,
6995         .ndo_change_mtu         = rtl8169_change_mtu,
6996         .ndo_fix_features       = rtl8169_fix_features,
6997         .ndo_set_features       = rtl8169_set_features,
6998         .ndo_set_mac_address    = rtl_set_mac_address,
6999         .ndo_do_ioctl           = rtl8169_ioctl,
7000         .ndo_set_rx_mode        = rtl_set_rx_mode,
7001 #ifdef CONFIG_NET_POLL_CONTROLLER
7002         .ndo_poll_controller    = rtl8169_netpoll,
7003 #endif
7004
7005 };
7006
7007 static const struct rtl_cfg_info {
7008         void (*hw_start)(struct rtl8169_private *tp);
7009         u16 irq_mask;
7010         unsigned int has_gmii:1;
7011         const struct rtl_coalesce_info *coalesce_info;
7012         u8 default_ver;
7013 } rtl_cfg_infos [] = {
7014         [RTL_CFG_0] = {
7015                 .hw_start       = rtl_hw_start_8169,
7016                 .irq_mask       = SYSErr | LinkChg | RxOverflow | RxFIFOOver,
7017                 .has_gmii       = 1,
7018                 .coalesce_info  = rtl_coalesce_info_8169,
7019                 .default_ver    = RTL_GIGA_MAC_VER_01,
7020         },
7021         [RTL_CFG_1] = {
7022                 .hw_start       = rtl_hw_start_8168,
7023                 .irq_mask       = LinkChg | RxOverflow,
7024                 .has_gmii       = 1,
7025                 .coalesce_info  = rtl_coalesce_info_8168_8136,
7026                 .default_ver    = RTL_GIGA_MAC_VER_11,
7027         },
7028         [RTL_CFG_2] = {
7029                 .hw_start       = rtl_hw_start_8101,
7030                 .irq_mask       = LinkChg | RxOverflow | RxFIFOOver,
7031                 .coalesce_info  = rtl_coalesce_info_8168_8136,
7032                 .default_ver    = RTL_GIGA_MAC_VER_13,
7033         }
7034 };
7035
7036 static int rtl_alloc_irq(struct rtl8169_private *tp)
7037 {
7038         unsigned int flags;
7039
7040         if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
7041                 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
7042                 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~MSIEnable);
7043                 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
7044                 flags = PCI_IRQ_LEGACY;
7045         } else {
7046                 flags = PCI_IRQ_ALL_TYPES;
7047         }
7048
7049         return pci_alloc_irq_vectors(tp->pci_dev, 1, 1, flags);
7050 }
7051
7052 DECLARE_RTL_COND(rtl_link_list_ready_cond)
7053 {
7054         return RTL_R8(tp, MCU) & LINK_LIST_RDY;
7055 }
7056
7057 DECLARE_RTL_COND(rtl_rxtx_empty_cond)
7058 {
7059         return (RTL_R8(tp, MCU) & RXTX_EMPTY) == RXTX_EMPTY;
7060 }
7061
7062 static int r8169_mdio_read_reg(struct mii_bus *mii_bus, int phyaddr, int phyreg)
7063 {
7064         struct rtl8169_private *tp = mii_bus->priv;
7065
7066         if (phyaddr > 0)
7067                 return -ENODEV;
7068
7069         return rtl_readphy(tp, phyreg);
7070 }
7071
7072 static int r8169_mdio_write_reg(struct mii_bus *mii_bus, int phyaddr,
7073                                 int phyreg, u16 val)
7074 {
7075         struct rtl8169_private *tp = mii_bus->priv;
7076
7077         if (phyaddr > 0)
7078                 return -ENODEV;
7079
7080         rtl_writephy(tp, phyreg, val);
7081
7082         return 0;
7083 }
7084
7085 static int r8169_mdio_register(struct rtl8169_private *tp)
7086 {
7087         struct pci_dev *pdev = tp->pci_dev;
7088         struct phy_device *phydev;
7089         struct mii_bus *new_bus;
7090         int ret;
7091
7092         new_bus = devm_mdiobus_alloc(&pdev->dev);
7093         if (!new_bus)
7094                 return -ENOMEM;
7095
7096         new_bus->name = "r8169";
7097         new_bus->priv = tp;
7098         new_bus->parent = &pdev->dev;
7099         new_bus->irq[0] = PHY_IGNORE_INTERRUPT;
7100         snprintf(new_bus->id, MII_BUS_ID_SIZE, "r8169-%x",
7101                  PCI_DEVID(pdev->bus->number, pdev->devfn));
7102
7103         new_bus->read = r8169_mdio_read_reg;
7104         new_bus->write = r8169_mdio_write_reg;
7105
7106         ret = mdiobus_register(new_bus);
7107         if (ret)
7108                 return ret;
7109
7110         phydev = mdiobus_get_phy(new_bus, 0);
7111         if (!phydev) {
7112                 mdiobus_unregister(new_bus);
7113                 return -ENODEV;
7114         }
7115
7116         /* PHY will be woken up in rtl_open() */
7117         phy_suspend(phydev);
7118
7119         tp->mii_bus = new_bus;
7120
7121         return 0;
7122 }
7123
7124 static void rtl_hw_init_8168g(struct rtl8169_private *tp)
7125 {
7126         u32 data;
7127
7128         tp->ocp_base = OCP_STD_PHY_BASE;
7129
7130         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN);
7131
7132         if (!rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42))
7133                 return;
7134
7135         if (!rtl_udelay_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42))
7136                 return;
7137
7138         RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
7139         msleep(1);
7140         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
7141
7142         data = r8168_mac_ocp_read(tp, 0xe8de);
7143         data &= ~(1 << 14);
7144         r8168_mac_ocp_write(tp, 0xe8de, data);
7145
7146         if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
7147                 return;
7148
7149         data = r8168_mac_ocp_read(tp, 0xe8de);
7150         data |= (1 << 15);
7151         r8168_mac_ocp_write(tp, 0xe8de, data);
7152
7153         if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
7154                 return;
7155 }
7156
7157 static void rtl_hw_init_8168ep(struct rtl8169_private *tp)
7158 {
7159         rtl8168ep_stop_cmac(tp);
7160         rtl_hw_init_8168g(tp);
7161 }
7162
7163 static void rtl_hw_initialize(struct rtl8169_private *tp)
7164 {
7165         switch (tp->mac_version) {
7166         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_48:
7167                 rtl_hw_init_8168g(tp);
7168                 break;
7169         case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_51:
7170                 rtl_hw_init_8168ep(tp);
7171                 break;
7172         default:
7173                 break;
7174         }
7175 }
7176
7177 /* Versions RTL8102e and from RTL8168c onwards support csum_v2 */
7178 static bool rtl_chip_supports_csum_v2(struct rtl8169_private *tp)
7179 {
7180         switch (tp->mac_version) {
7181         case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_06:
7182         case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
7183                 return false;
7184         default:
7185                 return true;
7186         }
7187 }
7188
7189 static int rtl_jumbo_max(struct rtl8169_private *tp)
7190 {
7191         /* Non-GBit versions don't support jumbo frames */
7192         if (!tp->supports_gmii)
7193                 return JUMBO_1K;
7194
7195         switch (tp->mac_version) {
7196         /* RTL8169 */
7197         case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_06:
7198                 return JUMBO_7K;
7199         /* RTL8168b */
7200         case RTL_GIGA_MAC_VER_11:
7201         case RTL_GIGA_MAC_VER_12:
7202         case RTL_GIGA_MAC_VER_17:
7203                 return JUMBO_4K;
7204         /* RTL8168c */
7205         case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
7206                 return JUMBO_6K;
7207         default:
7208                 return JUMBO_9K;
7209         }
7210 }
7211
7212 static void rtl_disable_clk(void *data)
7213 {
7214         clk_disable_unprepare(data);
7215 }
7216
7217 static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
7218 {
7219         const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
7220         struct rtl8169_private *tp;
7221         struct net_device *dev;
7222         int chipset, region, i;
7223         int jumbo_max, rc;
7224
7225         dev = devm_alloc_etherdev(&pdev->dev, sizeof (*tp));
7226         if (!dev)
7227                 return -ENOMEM;
7228
7229         SET_NETDEV_DEV(dev, &pdev->dev);
7230         dev->netdev_ops = &rtl_netdev_ops;
7231         tp = netdev_priv(dev);
7232         tp->dev = dev;
7233         tp->pci_dev = pdev;
7234         tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
7235         tp->supports_gmii = cfg->has_gmii;
7236
7237         /* Get the *optional* external "ether_clk" used on some boards */
7238         tp->clk = devm_clk_get(&pdev->dev, "ether_clk");
7239         if (IS_ERR(tp->clk)) {
7240                 rc = PTR_ERR(tp->clk);
7241                 if (rc == -ENOENT) {
7242                         /* clk-core allows NULL (for suspend / resume) */
7243                         tp->clk = NULL;
7244                 } else if (rc == -EPROBE_DEFER) {
7245                         return rc;
7246                 } else {
7247                         dev_err(&pdev->dev, "failed to get clk: %d\n", rc);
7248                         return rc;
7249                 }
7250         } else {
7251                 rc = clk_prepare_enable(tp->clk);
7252                 if (rc) {
7253                         dev_err(&pdev->dev, "failed to enable clk: %d\n", rc);
7254                         return rc;
7255                 }
7256
7257                 rc = devm_add_action_or_reset(&pdev->dev, rtl_disable_clk,
7258                                               tp->clk);
7259                 if (rc)
7260                         return rc;
7261         }
7262
7263         /* enable device (incl. PCI PM wakeup and hotplug setup) */
7264         rc = pcim_enable_device(pdev);
7265         if (rc < 0) {
7266                 dev_err(&pdev->dev, "enable failure\n");
7267                 return rc;
7268         }
7269
7270         if (pcim_set_mwi(pdev) < 0)
7271                 dev_info(&pdev->dev, "Mem-Wr-Inval unavailable\n");
7272
7273         /* use first MMIO region */
7274         region = ffs(pci_select_bars(pdev, IORESOURCE_MEM)) - 1;
7275         if (region < 0) {
7276                 dev_err(&pdev->dev, "no MMIO resource found\n");
7277                 return -ENODEV;
7278         }
7279
7280         /* check for weird/broken PCI region reporting */
7281         if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
7282                 dev_err(&pdev->dev, "Invalid PCI region size(s), aborting\n");
7283                 return -ENODEV;
7284         }
7285
7286         rc = pcim_iomap_regions(pdev, BIT(region), MODULENAME);
7287         if (rc < 0) {
7288                 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
7289                 return rc;
7290         }
7291
7292         tp->mmio_addr = pcim_iomap_table(pdev)[region];
7293
7294         /* Identify chip attached to board */
7295         rtl8169_get_mac_version(tp, cfg->default_ver);
7296
7297         if (rtl_tbi_enabled(tp)) {
7298                 dev_err(&pdev->dev, "TBI fiber mode not supported\n");
7299                 return -ENODEV;
7300         }
7301
7302         tp->cp_cmd = RTL_R16(tp, CPlusCmd);
7303
7304         if (sizeof(dma_addr_t) > 4 && (use_dac == 1 || (use_dac == -1 &&
7305             tp->mac_version >= RTL_GIGA_MAC_VER_18)) &&
7306             !dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) {
7307
7308                 /* CPlusCmd Dual Access Cycle is only needed for non-PCIe */
7309                 if (!pci_is_pcie(pdev))
7310                         tp->cp_cmd |= PCIDAC;
7311                 dev->features |= NETIF_F_HIGHDMA;
7312         } else {
7313                 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
7314                 if (rc < 0) {
7315                         dev_err(&pdev->dev, "DMA configuration failed\n");
7316                         return rc;
7317                 }
7318         }
7319
7320         rtl_init_rxcfg(tp);
7321
7322         rtl8169_irq_mask_and_ack(tp);
7323
7324         rtl_hw_initialize(tp);
7325
7326         rtl_hw_reset(tp);
7327
7328         pci_set_master(pdev);
7329
7330         rtl_init_mdio_ops(tp);
7331         rtl_init_jumbo_ops(tp);
7332
7333         chipset = tp->mac_version;
7334
7335         rc = rtl_alloc_irq(tp);
7336         if (rc < 0) {
7337                 dev_err(&pdev->dev, "Can't allocate interrupt\n");
7338                 return rc;
7339         }
7340
7341         tp->saved_wolopts = __rtl8169_get_wol(tp);
7342
7343         mutex_init(&tp->wk.mutex);
7344         u64_stats_init(&tp->rx_stats.syncp);
7345         u64_stats_init(&tp->tx_stats.syncp);
7346
7347         /* Get MAC address */
7348         switch (tp->mac_version) {
7349                 u8 mac_addr[ETH_ALEN] __aligned(4);
7350         case RTL_GIGA_MAC_VER_35 ... RTL_GIGA_MAC_VER_38:
7351         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
7352                 *(u32 *)&mac_addr[0] = rtl_eri_read(tp, 0xe0, ERIAR_EXGMAC);
7353                 *(u16 *)&mac_addr[4] = rtl_eri_read(tp, 0xe4, ERIAR_EXGMAC);
7354
7355                 if (is_valid_ether_addr(mac_addr))
7356                         rtl_rar_set(tp, mac_addr);
7357                 break;
7358         default:
7359                 break;
7360         }
7361         for (i = 0; i < ETH_ALEN; i++)
7362                 dev->dev_addr[i] = RTL_R8(tp, MAC0 + i);
7363
7364         dev->ethtool_ops = &rtl8169_ethtool_ops;
7365
7366         netif_napi_add(dev, &tp->napi, rtl8169_poll, NAPI_POLL_WEIGHT);
7367
7368         /* don't enable SG, IP_CSUM and TSO by default - it might not work
7369          * properly for all devices */
7370         dev->features |= NETIF_F_RXCSUM |
7371                 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
7372
7373         dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
7374                 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_TX |
7375                 NETIF_F_HW_VLAN_CTAG_RX;
7376         dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
7377                 NETIF_F_HIGHDMA;
7378         dev->priv_flags |= IFF_LIVE_ADDR_CHANGE;
7379
7380         tp->cp_cmd |= RxChkSum | RxVlan;
7381
7382         /*
7383          * Pretend we are using VLANs; This bypasses a nasty bug where
7384          * Interrupts stop flowing on high load on 8110SCd controllers.
7385          */
7386         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
7387                 /* Disallow toggling */
7388                 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX;
7389
7390         if (rtl_chip_supports_csum_v2(tp)) {
7391                 tp->tso_csum = rtl8169_tso_csum_v2;
7392                 dev->hw_features |= NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
7393         } else {
7394                 tp->tso_csum = rtl8169_tso_csum_v1;
7395         }
7396
7397         dev->hw_features |= NETIF_F_RXALL;
7398         dev->hw_features |= NETIF_F_RXFCS;
7399
7400         /* MTU range: 60 - hw-specific max */
7401         dev->min_mtu = ETH_ZLEN;
7402         jumbo_max = rtl_jumbo_max(tp);
7403         dev->max_mtu = jumbo_max;
7404
7405         tp->hw_start = cfg->hw_start;
7406         tp->irq_mask = RTL_EVENT_NAPI | cfg->irq_mask;
7407         tp->coalesce_info = cfg->coalesce_info;
7408
7409         tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
7410
7411         tp->counters = dmam_alloc_coherent (&pdev->dev, sizeof(*tp->counters),
7412                                             &tp->counters_phys_addr,
7413                                             GFP_KERNEL);
7414         if (!tp->counters)
7415                 return -ENOMEM;
7416
7417         pci_set_drvdata(pdev, dev);
7418
7419         rc = r8169_mdio_register(tp);
7420         if (rc)
7421                 return rc;
7422
7423         /* chip gets powered up in rtl_open() */
7424         rtl_pll_power_down(tp);
7425
7426         rc = register_netdev(dev);
7427         if (rc)
7428                 goto err_mdio_unregister;
7429
7430         netif_info(tp, probe, dev, "%s, %pM, XID %08x, IRQ %d\n",
7431                    rtl_chip_infos[chipset].name, dev->dev_addr,
7432                    (u32)(RTL_R32(tp, TxConfig) & 0xfcf0f8ff),
7433                    pci_irq_vector(pdev, 0));
7434
7435         if (jumbo_max > JUMBO_1K)
7436                 netif_info(tp, probe, dev,
7437                            "jumbo features [frames: %d bytes, tx checksumming: %s]\n",
7438                            jumbo_max, tp->mac_version <= RTL_GIGA_MAC_VER_06 ?
7439                            "ok" : "ko");
7440
7441         if (r8168_check_dash(tp))
7442                 rtl8168_driver_start(tp);
7443
7444         if (pci_dev_run_wake(pdev))
7445                 pm_runtime_put_sync(&pdev->dev);
7446
7447         return 0;
7448
7449 err_mdio_unregister:
7450         mdiobus_unregister(tp->mii_bus);
7451         return rc;
7452 }
7453
7454 static struct pci_driver rtl8169_pci_driver = {
7455         .name           = MODULENAME,
7456         .id_table       = rtl8169_pci_tbl,
7457         .probe          = rtl_init_one,
7458         .remove         = rtl_remove_one,
7459         .shutdown       = rtl_shutdown,
7460         .driver.pm      = RTL8169_PM_OPS,
7461 };
7462
7463 module_pci_driver(rtl8169_pci_driver);