2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
8 * See MAINTAINERS file for support contact information.
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/pci.h>
14 #include <linux/netdevice.h>
15 #include <linux/etherdevice.h>
16 #include <linux/clk.h>
17 #include <linux/delay.h>
18 #include <linux/ethtool.h>
19 #include <linux/phy.h>
20 #include <linux/if_vlan.h>
21 #include <linux/crc32.h>
25 #include <linux/tcp.h>
26 #include <linux/interrupt.h>
27 #include <linux/dma-mapping.h>
28 #include <linux/pm_runtime.h>
29 #include <linux/firmware.h>
30 #include <linux/prefetch.h>
31 #include <linux/ipv6.h>
32 #include <net/ip6_checksum.h>
34 #define MODULENAME "r8169"
36 #define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
37 #define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
38 #define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw"
39 #define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw"
40 #define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw"
41 #define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw"
42 #define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw"
43 #define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw"
44 #define FIRMWARE_8402_1 "rtl_nic/rtl8402-1.fw"
45 #define FIRMWARE_8411_1 "rtl_nic/rtl8411-1.fw"
46 #define FIRMWARE_8411_2 "rtl_nic/rtl8411-2.fw"
47 #define FIRMWARE_8106E_1 "rtl_nic/rtl8106e-1.fw"
48 #define FIRMWARE_8106E_2 "rtl_nic/rtl8106e-2.fw"
49 #define FIRMWARE_8168G_2 "rtl_nic/rtl8168g-2.fw"
50 #define FIRMWARE_8168G_3 "rtl_nic/rtl8168g-3.fw"
51 #define FIRMWARE_8168H_1 "rtl_nic/rtl8168h-1.fw"
52 #define FIRMWARE_8168H_2 "rtl_nic/rtl8168h-2.fw"
53 #define FIRMWARE_8107E_1 "rtl_nic/rtl8107e-1.fw"
54 #define FIRMWARE_8107E_2 "rtl_nic/rtl8107e-2.fw"
56 #define R8169_MSG_DEFAULT \
57 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
59 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
60 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
61 static const int multicast_filter_limit = 32;
63 #define TX_DMA_BURST 7 /* Maximum PCI burst, '7' is unlimited */
64 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
66 #define R8169_REGS_SIZE 256
67 #define R8169_RX_BUF_SIZE (SZ_16K - 1)
68 #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
69 #define NUM_RX_DESC 256U /* Number of Rx descriptor registers */
70 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
71 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
73 /* write/read MMIO register */
74 #define RTL_W8(tp, reg, val8) writeb((val8), tp->mmio_addr + (reg))
75 #define RTL_W16(tp, reg, val16) writew((val16), tp->mmio_addr + (reg))
76 #define RTL_W32(tp, reg, val32) writel((val32), tp->mmio_addr + (reg))
77 #define RTL_R8(tp, reg) readb(tp->mmio_addr + (reg))
78 #define RTL_R16(tp, reg) readw(tp->mmio_addr + (reg))
79 #define RTL_R32(tp, reg) readl(tp->mmio_addr + (reg))
82 RTL_GIGA_MAC_VER_01 = 0,
133 RTL_GIGA_MAC_NONE = 0xff,
136 #define JUMBO_1K ETH_DATA_LEN
137 #define JUMBO_4K (4*1024 - ETH_HLEN - 2)
138 #define JUMBO_6K (6*1024 - ETH_HLEN - 2)
139 #define JUMBO_7K (7*1024 - ETH_HLEN - 2)
140 #define JUMBO_9K (9*1024 - ETH_HLEN - 2)
142 static const struct {
145 } rtl_chip_infos[] = {
147 [RTL_GIGA_MAC_VER_01] = {"RTL8169" },
148 [RTL_GIGA_MAC_VER_02] = {"RTL8169s" },
149 [RTL_GIGA_MAC_VER_03] = {"RTL8110s" },
150 [RTL_GIGA_MAC_VER_04] = {"RTL8169sb/8110sb" },
151 [RTL_GIGA_MAC_VER_05] = {"RTL8169sc/8110sc" },
152 [RTL_GIGA_MAC_VER_06] = {"RTL8169sc/8110sc" },
154 [RTL_GIGA_MAC_VER_07] = {"RTL8102e" },
155 [RTL_GIGA_MAC_VER_08] = {"RTL8102e" },
156 [RTL_GIGA_MAC_VER_09] = {"RTL8102e" },
157 [RTL_GIGA_MAC_VER_10] = {"RTL8101e" },
158 [RTL_GIGA_MAC_VER_11] = {"RTL8168b/8111b" },
159 [RTL_GIGA_MAC_VER_12] = {"RTL8168b/8111b" },
160 [RTL_GIGA_MAC_VER_13] = {"RTL8101e" },
161 [RTL_GIGA_MAC_VER_14] = {"RTL8100e" },
162 [RTL_GIGA_MAC_VER_15] = {"RTL8100e" },
163 [RTL_GIGA_MAC_VER_16] = {"RTL8101e" },
164 [RTL_GIGA_MAC_VER_17] = {"RTL8168b/8111b" },
165 [RTL_GIGA_MAC_VER_18] = {"RTL8168cp/8111cp" },
166 [RTL_GIGA_MAC_VER_19] = {"RTL8168c/8111c" },
167 [RTL_GIGA_MAC_VER_20] = {"RTL8168c/8111c" },
168 [RTL_GIGA_MAC_VER_21] = {"RTL8168c/8111c" },
169 [RTL_GIGA_MAC_VER_22] = {"RTL8168c/8111c" },
170 [RTL_GIGA_MAC_VER_23] = {"RTL8168cp/8111cp" },
171 [RTL_GIGA_MAC_VER_24] = {"RTL8168cp/8111cp" },
172 [RTL_GIGA_MAC_VER_25] = {"RTL8168d/8111d", FIRMWARE_8168D_1},
173 [RTL_GIGA_MAC_VER_26] = {"RTL8168d/8111d", FIRMWARE_8168D_2},
174 [RTL_GIGA_MAC_VER_27] = {"RTL8168dp/8111dp" },
175 [RTL_GIGA_MAC_VER_28] = {"RTL8168dp/8111dp" },
176 [RTL_GIGA_MAC_VER_29] = {"RTL8105e", FIRMWARE_8105E_1},
177 [RTL_GIGA_MAC_VER_30] = {"RTL8105e", FIRMWARE_8105E_1},
178 [RTL_GIGA_MAC_VER_31] = {"RTL8168dp/8111dp" },
179 [RTL_GIGA_MAC_VER_32] = {"RTL8168e/8111e", FIRMWARE_8168E_1},
180 [RTL_GIGA_MAC_VER_33] = {"RTL8168e/8111e", FIRMWARE_8168E_2},
181 [RTL_GIGA_MAC_VER_34] = {"RTL8168evl/8111evl", FIRMWARE_8168E_3},
182 [RTL_GIGA_MAC_VER_35] = {"RTL8168f/8111f", FIRMWARE_8168F_1},
183 [RTL_GIGA_MAC_VER_36] = {"RTL8168f/8111f", FIRMWARE_8168F_2},
184 [RTL_GIGA_MAC_VER_37] = {"RTL8402", FIRMWARE_8402_1 },
185 [RTL_GIGA_MAC_VER_38] = {"RTL8411", FIRMWARE_8411_1 },
186 [RTL_GIGA_MAC_VER_39] = {"RTL8106e", FIRMWARE_8106E_1},
187 [RTL_GIGA_MAC_VER_40] = {"RTL8168g/8111g", FIRMWARE_8168G_2},
188 [RTL_GIGA_MAC_VER_41] = {"RTL8168g/8111g" },
189 [RTL_GIGA_MAC_VER_42] = {"RTL8168g/8111g", FIRMWARE_8168G_3},
190 [RTL_GIGA_MAC_VER_43] = {"RTL8106e", FIRMWARE_8106E_2},
191 [RTL_GIGA_MAC_VER_44] = {"RTL8411", FIRMWARE_8411_2 },
192 [RTL_GIGA_MAC_VER_45] = {"RTL8168h/8111h", FIRMWARE_8168H_1},
193 [RTL_GIGA_MAC_VER_46] = {"RTL8168h/8111h", FIRMWARE_8168H_2},
194 [RTL_GIGA_MAC_VER_47] = {"RTL8107e", FIRMWARE_8107E_1},
195 [RTL_GIGA_MAC_VER_48] = {"RTL8107e", FIRMWARE_8107E_2},
196 [RTL_GIGA_MAC_VER_49] = {"RTL8168ep/8111ep" },
197 [RTL_GIGA_MAC_VER_50] = {"RTL8168ep/8111ep" },
198 [RTL_GIGA_MAC_VER_51] = {"RTL8168ep/8111ep" },
207 static const struct pci_device_id rtl8169_pci_tbl[] = {
208 { PCI_VDEVICE(REALTEK, 0x2502), RTL_CFG_1 },
209 { PCI_VDEVICE(REALTEK, 0x2600), RTL_CFG_1 },
210 { PCI_VDEVICE(REALTEK, 0x8129), RTL_CFG_0 },
211 { PCI_VDEVICE(REALTEK, 0x8136), RTL_CFG_2 },
212 { PCI_VDEVICE(REALTEK, 0x8161), RTL_CFG_1 },
213 { PCI_VDEVICE(REALTEK, 0x8167), RTL_CFG_0 },
214 { PCI_VDEVICE(REALTEK, 0x8168), RTL_CFG_1 },
215 { PCI_VDEVICE(NCUBE, 0x8168), RTL_CFG_1 },
216 { PCI_VDEVICE(REALTEK, 0x8169), RTL_CFG_0 },
217 { PCI_VENDOR_ID_DLINK, 0x4300,
218 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0, RTL_CFG_1 },
219 { PCI_VDEVICE(DLINK, 0x4300), RTL_CFG_0 },
220 { PCI_VDEVICE(DLINK, 0x4302), RTL_CFG_0 },
221 { PCI_VDEVICE(AT, 0xc107), RTL_CFG_0 },
222 { PCI_VDEVICE(USR, 0x0116), RTL_CFG_0 },
223 { PCI_VENDOR_ID_LINKSYS, 0x1032,
224 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
226 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
230 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
237 MAC0 = 0, /* Ethernet hardware address. */
239 MAR0 = 8, /* Multicast filter. */
240 CounterAddrLow = 0x10,
241 CounterAddrHigh = 0x14,
242 TxDescStartAddrLow = 0x20,
243 TxDescStartAddrHigh = 0x24,
244 TxHDescStartAddrLow = 0x28,
245 TxHDescStartAddrHigh = 0x2c,
254 #define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */
255 #define TXCFG_EMPTY (1 << 11) /* 8111e-vl */
258 #define RX128_INT_EN (1 << 15) /* 8111c and later */
259 #define RX_MULTI_EN (1 << 14) /* 8111c only */
260 #define RXCFG_FIFO_SHIFT 13
261 /* No threshold before first PCI xfer */
262 #define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT)
263 #define RX_EARLY_OFF (1 << 11)
264 #define RXCFG_DMA_SHIFT 8
265 /* Unlimited maximum PCI burst. */
266 #define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT)
273 #define PME_SIGNAL (1 << 5) /* 8168c and later */
285 #define RTL_COALESCE_MASK 0x0f
286 #define RTL_COALESCE_SHIFT 4
287 #define RTL_COALESCE_T_MAX (RTL_COALESCE_MASK)
288 #define RTL_COALESCE_FRAME_MAX (RTL_COALESCE_MASK << 2)
290 RxDescAddrLow = 0xe4,
291 RxDescAddrHigh = 0xe8,
292 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */
294 #define NoEarlyTx 0x3f /* Max value : no early transmit. */
296 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
298 #define TxPacketMax (8064 >> 7)
299 #define EarlySize 0x27
302 FuncEventMask = 0xf4,
303 FuncPresetState = 0xf8,
308 FuncForceEvent = 0xfc,
311 enum rtl8168_8101_registers {
314 #define CSIAR_FLAG 0x80000000
315 #define CSIAR_WRITE_CMD 0x80000000
316 #define CSIAR_BYTE_ENABLE 0x0000f000
317 #define CSIAR_ADDR_MASK 0x00000fff
320 #define EPHYAR_FLAG 0x80000000
321 #define EPHYAR_WRITE_CMD 0x80000000
322 #define EPHYAR_REG_MASK 0x1f
323 #define EPHYAR_REG_SHIFT 16
324 #define EPHYAR_DATA_MASK 0xffff
326 #define PFM_EN (1 << 6)
327 #define TX_10M_PS_EN (1 << 7)
329 #define FIX_NAK_1 (1 << 4)
330 #define FIX_NAK_2 (1 << 3)
333 #define NOW_IS_OOB (1 << 7)
334 #define TX_EMPTY (1 << 5)
335 #define RX_EMPTY (1 << 4)
336 #define RXTX_EMPTY (TX_EMPTY | RX_EMPTY)
337 #define EN_NDP (1 << 3)
338 #define EN_OOB_RESET (1 << 2)
339 #define LINK_LIST_RDY (1 << 1)
341 #define EFUSEAR_FLAG 0x80000000
342 #define EFUSEAR_WRITE_CMD 0x80000000
343 #define EFUSEAR_READ_CMD 0x00000000
344 #define EFUSEAR_REG_MASK 0x03ff
345 #define EFUSEAR_REG_SHIFT 8
346 #define EFUSEAR_DATA_MASK 0xff
348 #define PFM_D3COLD_EN (1 << 6)
351 enum rtl8168_registers {
356 #define ERIAR_FLAG 0x80000000
357 #define ERIAR_WRITE_CMD 0x80000000
358 #define ERIAR_READ_CMD 0x00000000
359 #define ERIAR_ADDR_BYTE_ALIGN 4
360 #define ERIAR_TYPE_SHIFT 16
361 #define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT)
362 #define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT)
363 #define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT)
364 #define ERIAR_OOB (0x02 << ERIAR_TYPE_SHIFT)
365 #define ERIAR_MASK_SHIFT 12
366 #define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT)
367 #define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT)
368 #define ERIAR_MASK_0100 (0x4 << ERIAR_MASK_SHIFT)
369 #define ERIAR_MASK_0101 (0x5 << ERIAR_MASK_SHIFT)
370 #define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT)
371 EPHY_RXER_NUM = 0x7c,
372 OCPDR = 0xb0, /* OCP GPHY access */
373 #define OCPDR_WRITE_CMD 0x80000000
374 #define OCPDR_READ_CMD 0x00000000
375 #define OCPDR_REG_MASK 0x7f
376 #define OCPDR_GPHY_REG_SHIFT 16
377 #define OCPDR_DATA_MASK 0xffff
379 #define OCPAR_FLAG 0x80000000
380 #define OCPAR_GPHY_WRITE_CMD 0x8000f060
381 #define OCPAR_GPHY_READ_CMD 0x0000f060
383 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */
384 MISC = 0xf0, /* 8168e only. */
385 #define TXPLA_RST (1 << 29)
386 #define DISABLE_LAN_EN (1 << 23) /* Enable GPIO pin */
387 #define PWM_EN (1 << 22)
388 #define RXDV_GATED_EN (1 << 19)
389 #define EARLY_TALLY_EN (1 << 16)
392 enum rtl_register_content {
393 /* InterruptStatusBits */
397 TxDescUnavail = 0x0080,
421 /* TXPoll register p.5 */
422 HPQ = 0x80, /* Poll cmd on the high prio queue */
423 NPQ = 0x40, /* Poll cmd on the low prio queue */
424 FSWInt = 0x01, /* Forced software interrupt */
428 Cfg9346_Unlock = 0xc0,
433 AcceptBroadcast = 0x08,
434 AcceptMulticast = 0x04,
436 AcceptAllPhys = 0x01,
437 #define RX_CONFIG_ACCEPT_MASK 0x3f
440 TxInterFrameGapShift = 24,
441 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
443 /* Config1 register p.24 */
446 Speed_down = (1 << 4),
450 PMEnable = (1 << 0), /* Power Management Enable */
452 /* Config2 register p. 25 */
453 ClkReqEn = (1 << 7), /* Clock Request Enable */
454 MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */
455 PCI_Clock_66MHz = 0x01,
456 PCI_Clock_33MHz = 0x00,
458 /* Config3 register p.25 */
459 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
460 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
461 Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */
462 Rdy_to_L23 = (1 << 1), /* L23 Enable */
463 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
465 /* Config4 register */
466 Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */
468 /* Config5 register p.27 */
469 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
470 MWF = (1 << 5), /* Accept Multicast wakeup frame */
471 UWF = (1 << 4), /* Accept Unicast wakeup frame */
473 LanWake = (1 << 1), /* LanWake enable/disable */
474 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
475 ASPM_en = (1 << 0), /* ASPM enable */
478 EnableBist = (1 << 15), // 8168 8101
479 Mac_dbgo_oe = (1 << 14), // 8168 8101
480 Normal_mode = (1 << 13), // unused
481 Force_half_dup = (1 << 12), // 8168 8101
482 Force_rxflow_en = (1 << 11), // 8168 8101
483 Force_txflow_en = (1 << 10), // 8168 8101
484 Cxpl_dbg_sel = (1 << 9), // 8168 8101
485 ASF = (1 << 8), // 8168 8101
486 PktCntrDisable = (1 << 7), // 8168 8101
487 Mac_dbgo_sel = 0x001c, // 8168
492 #define INTT_MASK GENMASK(1, 0)
493 INTT_0 = 0x0000, // 8168
494 INTT_1 = 0x0001, // 8168
495 INTT_2 = 0x0002, // 8168
496 INTT_3 = 0x0003, // 8168
498 /* rtl8169_PHYstatus */
509 TBILinkOK = 0x02000000,
511 /* ResetCounterCommand */
514 /* DumpCounterCommand */
517 /* magic enable v2 */
518 MagicPacket_v2 = (1 << 16), /* Wake up when receives a Magic Packet */
522 /* First doubleword. */
523 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
524 RingEnd = (1 << 30), /* End of descriptor ring */
525 FirstFrag = (1 << 29), /* First segment of a packet */
526 LastFrag = (1 << 28), /* Final segment of a packet */
530 enum rtl_tx_desc_bit {
531 /* First doubleword. */
532 TD_LSO = (1 << 27), /* Large Send Offload */
533 #define TD_MSS_MAX 0x07ffu /* MSS value */
535 /* Second doubleword. */
536 TxVlanTag = (1 << 17), /* Add VLAN tag */
539 /* 8169, 8168b and 810x except 8102e. */
540 enum rtl_tx_desc_bit_0 {
541 /* First doubleword. */
542 #define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */
543 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */
544 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */
545 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */
548 /* 8102e, 8168c and beyond. */
549 enum rtl_tx_desc_bit_1 {
550 /* First doubleword. */
551 TD1_GTSENV4 = (1 << 26), /* Giant Send for IPv4 */
552 TD1_GTSENV6 = (1 << 25), /* Giant Send for IPv6 */
553 #define GTTCPHO_SHIFT 18
554 #define GTTCPHO_MAX 0x7fU
556 /* Second doubleword. */
557 #define TCPHO_SHIFT 18
558 #define TCPHO_MAX 0x3ffU
559 #define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */
560 TD1_IPv6_CS = (1 << 28), /* Calculate IPv6 checksum */
561 TD1_IPv4_CS = (1 << 29), /* Calculate IPv4 checksum */
562 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */
563 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */
566 enum rtl_rx_desc_bit {
568 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
569 PID0 = (1 << 17), /* Protocol ID bit 0/2 */
571 #define RxProtoUDP (PID1)
572 #define RxProtoTCP (PID0)
573 #define RxProtoIP (PID1 | PID0)
574 #define RxProtoMask RxProtoIP
576 IPFail = (1 << 16), /* IP checksum failed */
577 UDPFail = (1 << 15), /* UDP/IP checksum failed */
578 TCPFail = (1 << 14), /* TCP/IP checksum failed */
579 RxVlanTag = (1 << 16), /* VLAN tag available */
582 #define RsvdMask 0x3fffc000
583 #define CPCMD_QUIRK_MASK (Normal_mode | RxVlan | RxChkSum | INTT_MASK)
602 struct rtl8169_counters {
609 __le32 tx_one_collision;
610 __le32 tx_multi_collision;
618 struct rtl8169_tc_offsets {
621 __le32 tx_multi_collision;
626 RTL_FLAG_TASK_ENABLED = 0,
627 RTL_FLAG_TASK_RESET_PENDING,
631 struct rtl8169_stats {
634 struct u64_stats_sync syncp;
637 struct rtl8169_private {
638 void __iomem *mmio_addr; /* memory map physical address */
639 struct pci_dev *pci_dev;
640 struct net_device *dev;
641 struct phy_device *phydev;
642 struct napi_struct napi;
645 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
646 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
648 struct rtl8169_stats rx_stats;
649 struct rtl8169_stats tx_stats;
650 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
651 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
652 dma_addr_t TxPhyAddr;
653 dma_addr_t RxPhyAddr;
654 void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
655 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
659 const struct rtl_coalesce_info *coalesce_info;
663 void (*write)(struct rtl8169_private *, int, int);
664 int (*read)(struct rtl8169_private *, int);
668 void (*enable)(struct rtl8169_private *);
669 void (*disable)(struct rtl8169_private *);
672 void (*hw_start)(struct rtl8169_private *tp);
673 bool (*tso_csum)(struct rtl8169_private *, struct sk_buff *, u32 *);
676 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
678 struct work_struct work;
681 unsigned irq_enabled:1;
682 unsigned supports_gmii:1;
683 dma_addr_t counters_phys_addr;
684 struct rtl8169_counters *counters;
685 struct rtl8169_tc_offsets tc_offset;
690 const struct firmware *fw;
692 #define RTL_VER_SIZE 32
694 char version[RTL_VER_SIZE];
696 struct rtl_fw_phy_action {
705 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
706 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
707 module_param_named(debug, debug.msg_enable, int, 0);
708 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
709 MODULE_SOFTDEP("pre: realtek");
710 MODULE_LICENSE("GPL");
711 MODULE_FIRMWARE(FIRMWARE_8168D_1);
712 MODULE_FIRMWARE(FIRMWARE_8168D_2);
713 MODULE_FIRMWARE(FIRMWARE_8168E_1);
714 MODULE_FIRMWARE(FIRMWARE_8168E_2);
715 MODULE_FIRMWARE(FIRMWARE_8168E_3);
716 MODULE_FIRMWARE(FIRMWARE_8105E_1);
717 MODULE_FIRMWARE(FIRMWARE_8168F_1);
718 MODULE_FIRMWARE(FIRMWARE_8168F_2);
719 MODULE_FIRMWARE(FIRMWARE_8402_1);
720 MODULE_FIRMWARE(FIRMWARE_8411_1);
721 MODULE_FIRMWARE(FIRMWARE_8411_2);
722 MODULE_FIRMWARE(FIRMWARE_8106E_1);
723 MODULE_FIRMWARE(FIRMWARE_8106E_2);
724 MODULE_FIRMWARE(FIRMWARE_8168G_2);
725 MODULE_FIRMWARE(FIRMWARE_8168G_3);
726 MODULE_FIRMWARE(FIRMWARE_8168H_1);
727 MODULE_FIRMWARE(FIRMWARE_8168H_2);
728 MODULE_FIRMWARE(FIRMWARE_8107E_1);
729 MODULE_FIRMWARE(FIRMWARE_8107E_2);
731 static inline struct device *tp_to_dev(struct rtl8169_private *tp)
733 return &tp->pci_dev->dev;
736 static void rtl_lock_work(struct rtl8169_private *tp)
738 mutex_lock(&tp->wk.mutex);
741 static void rtl_unlock_work(struct rtl8169_private *tp)
743 mutex_unlock(&tp->wk.mutex);
746 static void rtl_lock_config_regs(struct rtl8169_private *tp)
748 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
751 static void rtl_unlock_config_regs(struct rtl8169_private *tp)
753 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
756 static void rtl_tx_performance_tweak(struct rtl8169_private *tp, u16 force)
758 pcie_capability_clear_and_set_word(tp->pci_dev, PCI_EXP_DEVCTL,
759 PCI_EXP_DEVCTL_READRQ, force);
763 bool (*check)(struct rtl8169_private *);
767 static void rtl_udelay(unsigned int d)
772 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,
773 void (*delay)(unsigned int), unsigned int d, int n,
778 for (i = 0; i < n; i++) {
780 if (c->check(tp) == high)
783 netif_err(tp, drv, tp->dev, "%s == %d (loop: %d, delay: %d).\n",
784 c->msg, !high, n, d);
788 static bool rtl_udelay_loop_wait_high(struct rtl8169_private *tp,
789 const struct rtl_cond *c,
790 unsigned int d, int n)
792 return rtl_loop_wait(tp, c, rtl_udelay, d, n, true);
795 static bool rtl_udelay_loop_wait_low(struct rtl8169_private *tp,
796 const struct rtl_cond *c,
797 unsigned int d, int n)
799 return rtl_loop_wait(tp, c, rtl_udelay, d, n, false);
802 static bool rtl_msleep_loop_wait_high(struct rtl8169_private *tp,
803 const struct rtl_cond *c,
804 unsigned int d, int n)
806 return rtl_loop_wait(tp, c, msleep, d, n, true);
809 static bool rtl_msleep_loop_wait_low(struct rtl8169_private *tp,
810 const struct rtl_cond *c,
811 unsigned int d, int n)
813 return rtl_loop_wait(tp, c, msleep, d, n, false);
816 #define DECLARE_RTL_COND(name) \
817 static bool name ## _check(struct rtl8169_private *); \
819 static const struct rtl_cond name = { \
820 .check = name ## _check, \
824 static bool name ## _check(struct rtl8169_private *tp)
826 static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg)
828 if (reg & 0xffff0001) {
829 netif_err(tp, drv, tp->dev, "Invalid ocp reg %x!\n", reg);
835 DECLARE_RTL_COND(rtl_ocp_gphy_cond)
837 return RTL_R32(tp, GPHY_OCP) & OCPAR_FLAG;
840 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
842 if (rtl_ocp_reg_failure(tp, reg))
845 RTL_W32(tp, GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);
847 rtl_udelay_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);
850 static u16 r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
852 if (rtl_ocp_reg_failure(tp, reg))
855 RTL_W32(tp, GPHY_OCP, reg << 15);
857 return rtl_udelay_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?
858 (RTL_R32(tp, GPHY_OCP) & 0xffff) : ~0;
861 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
863 if (rtl_ocp_reg_failure(tp, reg))
866 RTL_W32(tp, OCPDR, OCPAR_FLAG | (reg << 15) | data);
869 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
871 if (rtl_ocp_reg_failure(tp, reg))
874 RTL_W32(tp, OCPDR, reg << 15);
876 return RTL_R32(tp, OCPDR);
879 #define OCP_STD_PHY_BASE 0xa400
881 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)
884 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;
888 if (tp->ocp_base != OCP_STD_PHY_BASE)
891 r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);
894 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)
896 if (tp->ocp_base != OCP_STD_PHY_BASE)
899 return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);
902 static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value)
905 tp->ocp_base = value << 4;
909 r8168_mac_ocp_write(tp, tp->ocp_base + reg, value);
912 static int mac_mcu_read(struct rtl8169_private *tp, int reg)
914 return r8168_mac_ocp_read(tp, tp->ocp_base + reg);
917 DECLARE_RTL_COND(rtl_phyar_cond)
919 return RTL_R32(tp, PHYAR) & 0x80000000;
922 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)
924 RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
926 rtl_udelay_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);
928 * According to hardware specs a 20us delay is required after write
929 * complete indication, but before sending next command.
934 static int r8169_mdio_read(struct rtl8169_private *tp, int reg)
938 RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16);
940 value = rtl_udelay_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?
941 RTL_R32(tp, PHYAR) & 0xffff : ~0;
944 * According to hardware specs a 20us delay is required after read
945 * complete indication, but before sending next command.
952 DECLARE_RTL_COND(rtl_ocpar_cond)
954 return RTL_R32(tp, OCPAR) & OCPAR_FLAG;
957 static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data)
959 RTL_W32(tp, OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
960 RTL_W32(tp, OCPAR, OCPAR_GPHY_WRITE_CMD);
961 RTL_W32(tp, EPHY_RXER_NUM, 0);
963 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100);
966 static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value)
968 r8168dp_1_mdio_access(tp, reg,
969 OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK));
972 static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg)
974 r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD);
977 RTL_W32(tp, OCPAR, OCPAR_GPHY_READ_CMD);
978 RTL_W32(tp, EPHY_RXER_NUM, 0);
980 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ?
981 RTL_R32(tp, OCPDR) & OCPDR_DATA_MASK : ~0;
984 #define R8168DP_1_MDIO_ACCESS_BIT 0x00020000
986 static void r8168dp_2_mdio_start(struct rtl8169_private *tp)
988 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
991 static void r8168dp_2_mdio_stop(struct rtl8169_private *tp)
993 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
996 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)
998 r8168dp_2_mdio_start(tp);
1000 r8169_mdio_write(tp, reg, value);
1002 r8168dp_2_mdio_stop(tp);
1005 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)
1009 r8168dp_2_mdio_start(tp);
1011 value = r8169_mdio_read(tp, reg);
1013 r8168dp_2_mdio_stop(tp);
1018 static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
1020 tp->mdio_ops.write(tp, location, val);
1023 static int rtl_readphy(struct rtl8169_private *tp, int location)
1025 return tp->mdio_ops.read(tp, location);
1028 static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
1030 rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
1033 static void rtl_w0w1_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
1037 val = rtl_readphy(tp, reg_addr);
1038 rtl_writephy(tp, reg_addr, (val & ~m) | p);
1041 DECLARE_RTL_COND(rtl_ephyar_cond)
1043 return RTL_R32(tp, EPHYAR) & EPHYAR_FLAG;
1046 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)
1048 RTL_W32(tp, EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1049 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1051 rtl_udelay_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);
1056 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)
1058 RTL_W32(tp, EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1060 return rtl_udelay_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?
1061 RTL_R32(tp, EPHYAR) & EPHYAR_DATA_MASK : ~0;
1064 DECLARE_RTL_COND(rtl_eriar_cond)
1066 return RTL_R32(tp, ERIAR) & ERIAR_FLAG;
1069 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1072 BUG_ON((addr & 3) || (mask == 0));
1073 RTL_W32(tp, ERIDR, val);
1074 RTL_W32(tp, ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
1076 rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);
1079 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
1081 RTL_W32(tp, ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
1083 return rtl_udelay_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?
1084 RTL_R32(tp, ERIDR) : ~0;
1087 static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 mask, u32 p,
1092 val = rtl_eri_read(tp, addr, type);
1093 rtl_eri_write(tp, addr, mask, (val & ~m) | p, type);
1096 static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1098 RTL_W32(tp, OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1099 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?
1100 RTL_R32(tp, OCPDR) : ~0;
1103 static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1105 return rtl_eri_read(tp, reg, ERIAR_OOB);
1108 static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1111 RTL_W32(tp, OCPDR, data);
1112 RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1113 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);
1116 static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1119 rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT,
1123 static void r8168dp_oob_notify(struct rtl8169_private *tp, u8 cmd)
1125 rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd, ERIAR_EXGMAC);
1127 r8168dp_ocp_write(tp, 0x1, 0x30, 0x00000001);
1130 #define OOB_CMD_RESET 0x00
1131 #define OOB_CMD_DRIVER_START 0x05
1132 #define OOB_CMD_DRIVER_STOP 0x06
1134 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
1136 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
1139 DECLARE_RTL_COND(rtl_dp_ocp_read_cond)
1143 reg = rtl8168_get_ocp_reg(tp);
1145 return r8168dp_ocp_read(tp, 0x0f, reg) & 0x00000800;
1148 DECLARE_RTL_COND(rtl_ep_ocp_read_cond)
1150 return r8168ep_ocp_read(tp, 0x0f, 0x124) & 0x00000001;
1153 DECLARE_RTL_COND(rtl_ocp_tx_cond)
1155 return RTL_R8(tp, IBISR0) & 0x20;
1158 static void rtl8168ep_stop_cmac(struct rtl8169_private *tp)
1160 RTL_W8(tp, IBCR2, RTL_R8(tp, IBCR2) & ~0x01);
1161 rtl_msleep_loop_wait_high(tp, &rtl_ocp_tx_cond, 50, 2000);
1162 RTL_W8(tp, IBISR0, RTL_R8(tp, IBISR0) | 0x20);
1163 RTL_W8(tp, IBCR0, RTL_R8(tp, IBCR0) & ~0x01);
1166 static void rtl8168dp_driver_start(struct rtl8169_private *tp)
1168 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_START);
1169 rtl_msleep_loop_wait_high(tp, &rtl_dp_ocp_read_cond, 10, 10);
1172 static void rtl8168ep_driver_start(struct rtl8169_private *tp)
1174 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START);
1175 r8168ep_ocp_write(tp, 0x01, 0x30,
1176 r8168ep_ocp_read(tp, 0x01, 0x30) | 0x01);
1177 rtl_msleep_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10, 10);
1180 static void rtl8168_driver_start(struct rtl8169_private *tp)
1182 switch (tp->mac_version) {
1183 case RTL_GIGA_MAC_VER_27:
1184 case RTL_GIGA_MAC_VER_28:
1185 case RTL_GIGA_MAC_VER_31:
1186 rtl8168dp_driver_start(tp);
1188 case RTL_GIGA_MAC_VER_49:
1189 case RTL_GIGA_MAC_VER_50:
1190 case RTL_GIGA_MAC_VER_51:
1191 rtl8168ep_driver_start(tp);
1199 static void rtl8168dp_driver_stop(struct rtl8169_private *tp)
1201 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_STOP);
1202 rtl_msleep_loop_wait_low(tp, &rtl_dp_ocp_read_cond, 10, 10);
1205 static void rtl8168ep_driver_stop(struct rtl8169_private *tp)
1207 rtl8168ep_stop_cmac(tp);
1208 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP);
1209 r8168ep_ocp_write(tp, 0x01, 0x30,
1210 r8168ep_ocp_read(tp, 0x01, 0x30) | 0x01);
1211 rtl_msleep_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10, 10);
1214 static void rtl8168_driver_stop(struct rtl8169_private *tp)
1216 switch (tp->mac_version) {
1217 case RTL_GIGA_MAC_VER_27:
1218 case RTL_GIGA_MAC_VER_28:
1219 case RTL_GIGA_MAC_VER_31:
1220 rtl8168dp_driver_stop(tp);
1222 case RTL_GIGA_MAC_VER_49:
1223 case RTL_GIGA_MAC_VER_50:
1224 case RTL_GIGA_MAC_VER_51:
1225 rtl8168ep_driver_stop(tp);
1233 static bool r8168dp_check_dash(struct rtl8169_private *tp)
1235 u16 reg = rtl8168_get_ocp_reg(tp);
1237 return !!(r8168dp_ocp_read(tp, 0x0f, reg) & 0x00008000);
1240 static bool r8168ep_check_dash(struct rtl8169_private *tp)
1242 return !!(r8168ep_ocp_read(tp, 0x0f, 0x128) & 0x00000001);
1245 static bool r8168_check_dash(struct rtl8169_private *tp)
1247 switch (tp->mac_version) {
1248 case RTL_GIGA_MAC_VER_27:
1249 case RTL_GIGA_MAC_VER_28:
1250 case RTL_GIGA_MAC_VER_31:
1251 return r8168dp_check_dash(tp);
1252 case RTL_GIGA_MAC_VER_49:
1253 case RTL_GIGA_MAC_VER_50:
1254 case RTL_GIGA_MAC_VER_51:
1255 return r8168ep_check_dash(tp);
1267 static void rtl_write_exgmac_batch(struct rtl8169_private *tp,
1268 const struct exgmac_reg *r, int len)
1271 rtl_eri_write(tp, r->addr, r->mask, r->val, ERIAR_EXGMAC);
1276 DECLARE_RTL_COND(rtl_efusear_cond)
1278 return RTL_R32(tp, EFUSEAR) & EFUSEAR_FLAG;
1281 static u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)
1283 RTL_W32(tp, EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1285 return rtl_udelay_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?
1286 RTL_R32(tp, EFUSEAR) & EFUSEAR_DATA_MASK : ~0;
1289 static void rtl_ack_events(struct rtl8169_private *tp, u16 bits)
1291 RTL_W16(tp, IntrStatus, bits);
1294 static void rtl_irq_disable(struct rtl8169_private *tp)
1296 RTL_W16(tp, IntrMask, 0);
1297 tp->irq_enabled = 0;
1300 #define RTL_EVENT_NAPI_RX (RxOK | RxErr)
1301 #define RTL_EVENT_NAPI_TX (TxOK | TxErr)
1302 #define RTL_EVENT_NAPI (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX)
1304 static void rtl_irq_enable(struct rtl8169_private *tp)
1306 tp->irq_enabled = 1;
1307 RTL_W16(tp, IntrMask, tp->irq_mask);
1310 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1312 rtl_irq_disable(tp);
1313 rtl_ack_events(tp, 0xffff);
1315 RTL_R8(tp, ChipCmd);
1318 static void rtl_link_chg_patch(struct rtl8169_private *tp)
1320 struct net_device *dev = tp->dev;
1321 struct phy_device *phydev = tp->phydev;
1323 if (!netif_running(dev))
1326 if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
1327 tp->mac_version == RTL_GIGA_MAC_VER_38) {
1328 if (phydev->speed == SPEED_1000) {
1329 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1331 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1333 } else if (phydev->speed == SPEED_100) {
1334 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1336 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1339 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1341 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1344 /* Reset packet filter */
1345 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01,
1347 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00,
1349 } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1350 tp->mac_version == RTL_GIGA_MAC_VER_36) {
1351 if (phydev->speed == SPEED_1000) {
1352 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1354 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1357 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1359 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1362 } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
1363 if (phydev->speed == SPEED_10) {
1364 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02,
1366 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060,
1369 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000,
1375 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1377 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1379 struct rtl8169_private *tp = netdev_priv(dev);
1382 wol->supported = WAKE_ANY;
1383 wol->wolopts = tp->saved_wolopts;
1384 rtl_unlock_work(tp);
1387 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1389 unsigned int i, tmp;
1390 static const struct {
1395 { WAKE_PHY, Config3, LinkUp },
1396 { WAKE_UCAST, Config5, UWF },
1397 { WAKE_BCAST, Config5, BWF },
1398 { WAKE_MCAST, Config5, MWF },
1399 { WAKE_ANY, Config5, LanWake },
1400 { WAKE_MAGIC, Config3, MagicPacket }
1404 rtl_unlock_config_regs(tp);
1406 switch (tp->mac_version) {
1407 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
1408 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
1409 tmp = ARRAY_SIZE(cfg) - 1;
1410 if (wolopts & WAKE_MAGIC)
1426 tmp = ARRAY_SIZE(cfg);
1430 for (i = 0; i < tmp; i++) {
1431 options = RTL_R8(tp, cfg[i].reg) & ~cfg[i].mask;
1432 if (wolopts & cfg[i].opt)
1433 options |= cfg[i].mask;
1434 RTL_W8(tp, cfg[i].reg, options);
1437 switch (tp->mac_version) {
1438 case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_17:
1439 options = RTL_R8(tp, Config1) & ~PMEnable;
1441 options |= PMEnable;
1442 RTL_W8(tp, Config1, options);
1445 options = RTL_R8(tp, Config2) & ~PME_SIGNAL;
1447 options |= PME_SIGNAL;
1448 RTL_W8(tp, Config2, options);
1452 rtl_lock_config_regs(tp);
1454 device_set_wakeup_enable(tp_to_dev(tp), wolopts);
1457 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1459 struct rtl8169_private *tp = netdev_priv(dev);
1460 struct device *d = tp_to_dev(tp);
1462 if (wol->wolopts & ~WAKE_ANY)
1465 pm_runtime_get_noresume(d);
1469 tp->saved_wolopts = wol->wolopts;
1471 if (pm_runtime_active(d))
1472 __rtl8169_set_wol(tp, tp->saved_wolopts);
1474 rtl_unlock_work(tp);
1476 pm_runtime_put_noidle(d);
1481 static void rtl8169_get_drvinfo(struct net_device *dev,
1482 struct ethtool_drvinfo *info)
1484 struct rtl8169_private *tp = netdev_priv(dev);
1485 struct rtl_fw *rtl_fw = tp->rtl_fw;
1487 strlcpy(info->driver, MODULENAME, sizeof(info->driver));
1488 strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1489 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
1491 strlcpy(info->fw_version, rtl_fw->version,
1492 sizeof(info->fw_version));
1495 static int rtl8169_get_regs_len(struct net_device *dev)
1497 return R8169_REGS_SIZE;
1500 static netdev_features_t rtl8169_fix_features(struct net_device *dev,
1501 netdev_features_t features)
1503 struct rtl8169_private *tp = netdev_priv(dev);
1505 if (dev->mtu > TD_MSS_MAX)
1506 features &= ~NETIF_F_ALL_TSO;
1508 if (dev->mtu > JUMBO_1K &&
1509 tp->mac_version > RTL_GIGA_MAC_VER_06)
1510 features &= ~NETIF_F_IP_CSUM;
1515 static int rtl8169_set_features(struct net_device *dev,
1516 netdev_features_t features)
1518 struct rtl8169_private *tp = netdev_priv(dev);
1523 rx_config = RTL_R32(tp, RxConfig);
1524 if (features & NETIF_F_RXALL)
1525 rx_config |= (AcceptErr | AcceptRunt);
1527 rx_config &= ~(AcceptErr | AcceptRunt);
1529 RTL_W32(tp, RxConfig, rx_config);
1531 if (features & NETIF_F_RXCSUM)
1532 tp->cp_cmd |= RxChkSum;
1534 tp->cp_cmd &= ~RxChkSum;
1536 if (features & NETIF_F_HW_VLAN_CTAG_RX)
1537 tp->cp_cmd |= RxVlan;
1539 tp->cp_cmd &= ~RxVlan;
1541 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1542 RTL_R16(tp, CPlusCmd);
1544 rtl_unlock_work(tp);
1549 static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb)
1551 return (skb_vlan_tag_present(skb)) ?
1552 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00;
1555 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1557 u32 opts2 = le32_to_cpu(desc->opts2);
1559 if (opts2 & RxVlanTag)
1560 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff));
1563 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1566 struct rtl8169_private *tp = netdev_priv(dev);
1567 u32 __iomem *data = tp->mmio_addr;
1572 for (i = 0; i < R8169_REGS_SIZE; i += 4)
1573 memcpy_fromio(dw++, data++, 4);
1574 rtl_unlock_work(tp);
1577 static u32 rtl8169_get_msglevel(struct net_device *dev)
1579 struct rtl8169_private *tp = netdev_priv(dev);
1581 return tp->msg_enable;
1584 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1586 struct rtl8169_private *tp = netdev_priv(dev);
1588 tp->msg_enable = value;
1591 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1598 "tx_single_collisions",
1599 "tx_multi_collisions",
1607 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1611 return ARRAY_SIZE(rtl8169_gstrings);
1617 DECLARE_RTL_COND(rtl_counters_cond)
1619 return RTL_R32(tp, CounterAddrLow) & (CounterReset | CounterDump);
1622 static bool rtl8169_do_counters(struct rtl8169_private *tp, u32 counter_cmd)
1624 dma_addr_t paddr = tp->counters_phys_addr;
1627 RTL_W32(tp, CounterAddrHigh, (u64)paddr >> 32);
1628 RTL_R32(tp, CounterAddrHigh);
1629 cmd = (u64)paddr & DMA_BIT_MASK(32);
1630 RTL_W32(tp, CounterAddrLow, cmd);
1631 RTL_W32(tp, CounterAddrLow, cmd | counter_cmd);
1633 return rtl_udelay_loop_wait_low(tp, &rtl_counters_cond, 10, 1000);
1636 static bool rtl8169_reset_counters(struct rtl8169_private *tp)
1639 * Versions prior to RTL_GIGA_MAC_VER_19 don't support resetting the
1642 if (tp->mac_version < RTL_GIGA_MAC_VER_19)
1645 return rtl8169_do_counters(tp, CounterReset);
1648 static bool rtl8169_update_counters(struct rtl8169_private *tp)
1650 u8 val = RTL_R8(tp, ChipCmd);
1653 * Some chips are unable to dump tally counters when the receiver
1654 * is disabled. If 0xff chip may be in a PCI power-save state.
1656 if (!(val & CmdRxEnb) || val == 0xff)
1659 return rtl8169_do_counters(tp, CounterDump);
1662 static bool rtl8169_init_counter_offsets(struct rtl8169_private *tp)
1664 struct rtl8169_counters *counters = tp->counters;
1668 * rtl8169_init_counter_offsets is called from rtl_open. On chip
1669 * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only
1670 * reset by a power cycle, while the counter values collected by the
1671 * driver are reset at every driver unload/load cycle.
1673 * To make sure the HW values returned by @get_stats64 match the SW
1674 * values, we collect the initial values at first open(*) and use them
1675 * as offsets to normalize the values returned by @get_stats64.
1677 * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one
1678 * for the reason stated in rtl8169_update_counters; CmdRxEnb is only
1679 * set at open time by rtl_hw_start.
1682 if (tp->tc_offset.inited)
1685 /* If both, reset and update fail, propagate to caller. */
1686 if (rtl8169_reset_counters(tp))
1689 if (rtl8169_update_counters(tp))
1692 tp->tc_offset.tx_errors = counters->tx_errors;
1693 tp->tc_offset.tx_multi_collision = counters->tx_multi_collision;
1694 tp->tc_offset.tx_aborted = counters->tx_aborted;
1695 tp->tc_offset.inited = true;
1700 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1701 struct ethtool_stats *stats, u64 *data)
1703 struct rtl8169_private *tp = netdev_priv(dev);
1704 struct device *d = tp_to_dev(tp);
1705 struct rtl8169_counters *counters = tp->counters;
1709 pm_runtime_get_noresume(d);
1711 if (pm_runtime_active(d))
1712 rtl8169_update_counters(tp);
1714 pm_runtime_put_noidle(d);
1716 data[0] = le64_to_cpu(counters->tx_packets);
1717 data[1] = le64_to_cpu(counters->rx_packets);
1718 data[2] = le64_to_cpu(counters->tx_errors);
1719 data[3] = le32_to_cpu(counters->rx_errors);
1720 data[4] = le16_to_cpu(counters->rx_missed);
1721 data[5] = le16_to_cpu(counters->align_errors);
1722 data[6] = le32_to_cpu(counters->tx_one_collision);
1723 data[7] = le32_to_cpu(counters->tx_multi_collision);
1724 data[8] = le64_to_cpu(counters->rx_unicast);
1725 data[9] = le64_to_cpu(counters->rx_broadcast);
1726 data[10] = le32_to_cpu(counters->rx_multicast);
1727 data[11] = le16_to_cpu(counters->tx_aborted);
1728 data[12] = le16_to_cpu(counters->tx_underun);
1731 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1735 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1741 * Interrupt coalescing
1743 * > 1 - the availability of the IntrMitigate (0xe2) register through the
1744 * > 8169, 8168 and 810x line of chipsets
1746 * 8169, 8168, and 8136(810x) serial chipsets support it.
1748 * > 2 - the Tx timer unit at gigabit speed
1750 * The unit of the timer depends on both the speed and the setting of CPlusCmd
1751 * (0xe0) bit 1 and bit 0.
1754 * bit[1:0] \ speed 1000M 100M 10M
1755 * 0 0 320ns 2.56us 40.96us
1756 * 0 1 2.56us 20.48us 327.7us
1757 * 1 0 5.12us 40.96us 655.4us
1758 * 1 1 10.24us 81.92us 1.31ms
1761 * bit[1:0] \ speed 1000M 100M 10M
1762 * 0 0 5us 2.56us 40.96us
1763 * 0 1 40us 20.48us 327.7us
1764 * 1 0 80us 40.96us 655.4us
1765 * 1 1 160us 81.92us 1.31ms
1768 /* rx/tx scale factors for one particular CPlusCmd[0:1] value */
1769 struct rtl_coalesce_scale {
1774 /* rx/tx scale factors for all CPlusCmd[0:1] cases */
1775 struct rtl_coalesce_info {
1777 struct rtl_coalesce_scale scalev[4]; /* each CPlusCmd[0:1] case */
1780 /* produce (r,t) pairs with each being in series of *1, *8, *8*2, *8*2*2 */
1781 #define rxtx_x1822(r, t) { \
1784 {{(r)*8*2, (t)*8*2}}, \
1785 {{(r)*8*2*2, (t)*8*2*2}}, \
1787 static const struct rtl_coalesce_info rtl_coalesce_info_8169[] = {
1788 /* speed delays: rx00 tx00 */
1789 { SPEED_10, rxtx_x1822(40960, 40960) },
1790 { SPEED_100, rxtx_x1822( 2560, 2560) },
1791 { SPEED_1000, rxtx_x1822( 320, 320) },
1795 static const struct rtl_coalesce_info rtl_coalesce_info_8168_8136[] = {
1796 /* speed delays: rx00 tx00 */
1797 { SPEED_10, rxtx_x1822(40960, 40960) },
1798 { SPEED_100, rxtx_x1822( 2560, 2560) },
1799 { SPEED_1000, rxtx_x1822( 5000, 5000) },
1804 /* get rx/tx scale vector corresponding to current speed */
1805 static const struct rtl_coalesce_info *rtl_coalesce_info(struct net_device *dev)
1807 struct rtl8169_private *tp = netdev_priv(dev);
1808 struct ethtool_link_ksettings ecmd;
1809 const struct rtl_coalesce_info *ci;
1812 rc = phy_ethtool_get_link_ksettings(dev, &ecmd);
1816 for (ci = tp->coalesce_info; ci->speed != 0; ci++) {
1817 if (ecmd.base.speed == ci->speed) {
1822 return ERR_PTR(-ELNRNG);
1825 static int rtl_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1827 struct rtl8169_private *tp = netdev_priv(dev);
1828 const struct rtl_coalesce_info *ci;
1829 const struct rtl_coalesce_scale *scale;
1833 } coal_settings [] = {
1834 { &ec->rx_max_coalesced_frames, &ec->rx_coalesce_usecs },
1835 { &ec->tx_max_coalesced_frames, &ec->tx_coalesce_usecs }
1836 }, *p = coal_settings;
1840 memset(ec, 0, sizeof(*ec));
1842 /* get rx/tx scale corresponding to current speed and CPlusCmd[0:1] */
1843 ci = rtl_coalesce_info(dev);
1847 scale = &ci->scalev[tp->cp_cmd & INTT_MASK];
1849 /* read IntrMitigate and adjust according to scale */
1850 for (w = RTL_R16(tp, IntrMitigate); w; w >>= RTL_COALESCE_SHIFT, p++) {
1851 *p->max_frames = (w & RTL_COALESCE_MASK) << 2;
1852 w >>= RTL_COALESCE_SHIFT;
1853 *p->usecs = w & RTL_COALESCE_MASK;
1856 for (i = 0; i < 2; i++) {
1857 p = coal_settings + i;
1858 *p->usecs = (*p->usecs * scale->nsecs[i]) / 1000;
1861 * ethtool_coalesce says it is illegal to set both usecs and
1864 if (!*p->usecs && !*p->max_frames)
1871 /* choose appropriate scale factor and CPlusCmd[0:1] for (speed, nsec) */
1872 static const struct rtl_coalesce_scale *rtl_coalesce_choose_scale(
1873 struct net_device *dev, u32 nsec, u16 *cp01)
1875 const struct rtl_coalesce_info *ci;
1878 ci = rtl_coalesce_info(dev);
1880 return ERR_CAST(ci);
1882 for (i = 0; i < 4; i++) {
1883 u32 rxtx_maxscale = max(ci->scalev[i].nsecs[0],
1884 ci->scalev[i].nsecs[1]);
1885 if (nsec <= rxtx_maxscale * RTL_COALESCE_T_MAX) {
1887 return &ci->scalev[i];
1891 return ERR_PTR(-EINVAL);
1894 static int rtl_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1896 struct rtl8169_private *tp = netdev_priv(dev);
1897 const struct rtl_coalesce_scale *scale;
1901 } coal_settings [] = {
1902 { ec->rx_max_coalesced_frames, ec->rx_coalesce_usecs },
1903 { ec->tx_max_coalesced_frames, ec->tx_coalesce_usecs }
1904 }, *p = coal_settings;
1908 scale = rtl_coalesce_choose_scale(dev,
1909 max(p[0].usecs, p[1].usecs) * 1000, &cp01);
1911 return PTR_ERR(scale);
1913 for (i = 0; i < 2; i++, p++) {
1917 * accept max_frames=1 we returned in rtl_get_coalesce.
1918 * accept it not only when usecs=0 because of e.g. the following scenario:
1920 * - both rx_usecs=0 & rx_frames=0 in hardware (no delay on RX)
1921 * - rtl_get_coalesce returns rx_usecs=0, rx_frames=1
1922 * - then user does `ethtool -C eth0 rx-usecs 100`
1924 * since ethtool sends to kernel whole ethtool_coalesce
1925 * settings, if we do not handle rx_usecs=!0, rx_frames=1
1926 * we'll reject it below in `frames % 4 != 0`.
1928 if (p->frames == 1) {
1932 units = p->usecs * 1000 / scale->nsecs[i];
1933 if (p->frames > RTL_COALESCE_FRAME_MAX || p->frames % 4)
1936 w <<= RTL_COALESCE_SHIFT;
1938 w <<= RTL_COALESCE_SHIFT;
1939 w |= p->frames >> 2;
1944 RTL_W16(tp, IntrMitigate, swab16(w));
1946 tp->cp_cmd = (tp->cp_cmd & ~INTT_MASK) | cp01;
1947 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1948 RTL_R16(tp, CPlusCmd);
1950 rtl_unlock_work(tp);
1955 static int rtl_get_eee_supp(struct rtl8169_private *tp)
1957 struct phy_device *phydev = tp->phydev;
1960 switch (tp->mac_version) {
1961 case RTL_GIGA_MAC_VER_34:
1962 case RTL_GIGA_MAC_VER_35:
1963 case RTL_GIGA_MAC_VER_36:
1964 case RTL_GIGA_MAC_VER_38:
1965 ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE);
1967 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
1968 phy_write(phydev, 0x1f, 0x0a5c);
1969 ret = phy_read(phydev, 0x12);
1970 phy_write(phydev, 0x1f, 0x0000);
1973 ret = -EPROTONOSUPPORT;
1980 static int rtl_get_eee_lpadv(struct rtl8169_private *tp)
1982 struct phy_device *phydev = tp->phydev;
1985 switch (tp->mac_version) {
1986 case RTL_GIGA_MAC_VER_34:
1987 case RTL_GIGA_MAC_VER_35:
1988 case RTL_GIGA_MAC_VER_36:
1989 case RTL_GIGA_MAC_VER_38:
1990 ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE);
1992 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
1993 phy_write(phydev, 0x1f, 0x0a5d);
1994 ret = phy_read(phydev, 0x11);
1995 phy_write(phydev, 0x1f, 0x0000);
1998 ret = -EPROTONOSUPPORT;
2005 static int rtl_get_eee_adv(struct rtl8169_private *tp)
2007 struct phy_device *phydev = tp->phydev;
2010 switch (tp->mac_version) {
2011 case RTL_GIGA_MAC_VER_34:
2012 case RTL_GIGA_MAC_VER_35:
2013 case RTL_GIGA_MAC_VER_36:
2014 case RTL_GIGA_MAC_VER_38:
2015 ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV);
2017 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
2018 phy_write(phydev, 0x1f, 0x0a5d);
2019 ret = phy_read(phydev, 0x10);
2020 phy_write(phydev, 0x1f, 0x0000);
2023 ret = -EPROTONOSUPPORT;
2030 static int rtl_set_eee_adv(struct rtl8169_private *tp, int val)
2032 struct phy_device *phydev = tp->phydev;
2035 switch (tp->mac_version) {
2036 case RTL_GIGA_MAC_VER_34:
2037 case RTL_GIGA_MAC_VER_35:
2038 case RTL_GIGA_MAC_VER_36:
2039 case RTL_GIGA_MAC_VER_38:
2040 ret = phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);
2042 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
2043 phy_write(phydev, 0x1f, 0x0a5d);
2044 phy_write(phydev, 0x10, val);
2045 phy_write(phydev, 0x1f, 0x0000);
2048 ret = -EPROTONOSUPPORT;
2055 static int rtl8169_get_eee(struct net_device *dev, struct ethtool_eee *data)
2057 struct rtl8169_private *tp = netdev_priv(dev);
2058 struct device *d = tp_to_dev(tp);
2061 pm_runtime_get_noresume(d);
2063 if (!pm_runtime_active(d)) {
2068 /* Get Supported EEE */
2069 ret = rtl_get_eee_supp(tp);
2072 data->supported = mmd_eee_cap_to_ethtool_sup_t(ret);
2074 /* Get advertisement EEE */
2075 ret = rtl_get_eee_adv(tp);
2078 data->advertised = mmd_eee_adv_to_ethtool_adv_t(ret);
2079 data->eee_enabled = !!data->advertised;
2081 /* Get LP advertisement EEE */
2082 ret = rtl_get_eee_lpadv(tp);
2085 data->lp_advertised = mmd_eee_adv_to_ethtool_adv_t(ret);
2086 data->eee_active = !!(data->advertised & data->lp_advertised);
2088 pm_runtime_put_noidle(d);
2089 return ret < 0 ? ret : 0;
2092 static int rtl8169_set_eee(struct net_device *dev, struct ethtool_eee *data)
2094 struct rtl8169_private *tp = netdev_priv(dev);
2095 struct device *d = tp_to_dev(tp);
2096 int old_adv, adv = 0, cap, ret;
2098 pm_runtime_get_noresume(d);
2100 if (!dev->phydev || !pm_runtime_active(d)) {
2105 if (dev->phydev->autoneg == AUTONEG_DISABLE ||
2106 dev->phydev->duplex != DUPLEX_FULL) {
2107 ret = -EPROTONOSUPPORT;
2111 /* Get Supported EEE */
2112 ret = rtl_get_eee_supp(tp);
2117 ret = rtl_get_eee_adv(tp);
2122 if (data->eee_enabled) {
2123 adv = !data->advertised ? cap :
2124 ethtool_adv_to_mmd_eee_adv_t(data->advertised) & cap;
2125 /* Mask prohibited EEE modes */
2126 adv &= ~dev->phydev->eee_broken_modes;
2129 if (old_adv != adv) {
2130 ret = rtl_set_eee_adv(tp, adv);
2134 /* Restart autonegotiation so the new modes get sent to the
2137 ret = phy_restart_aneg(dev->phydev);
2141 pm_runtime_put_noidle(d);
2142 return ret < 0 ? ret : 0;
2145 static const struct ethtool_ops rtl8169_ethtool_ops = {
2146 .get_drvinfo = rtl8169_get_drvinfo,
2147 .get_regs_len = rtl8169_get_regs_len,
2148 .get_link = ethtool_op_get_link,
2149 .get_coalesce = rtl_get_coalesce,
2150 .set_coalesce = rtl_set_coalesce,
2151 .get_msglevel = rtl8169_get_msglevel,
2152 .set_msglevel = rtl8169_set_msglevel,
2153 .get_regs = rtl8169_get_regs,
2154 .get_wol = rtl8169_get_wol,
2155 .set_wol = rtl8169_set_wol,
2156 .get_strings = rtl8169_get_strings,
2157 .get_sset_count = rtl8169_get_sset_count,
2158 .get_ethtool_stats = rtl8169_get_ethtool_stats,
2159 .get_ts_info = ethtool_op_get_ts_info,
2160 .nway_reset = phy_ethtool_nway_reset,
2161 .get_eee = rtl8169_get_eee,
2162 .set_eee = rtl8169_set_eee,
2163 .get_link_ksettings = phy_ethtool_get_link_ksettings,
2164 .set_link_ksettings = phy_ethtool_set_link_ksettings,
2167 static void rtl_enable_eee(struct rtl8169_private *tp)
2169 int supported = rtl_get_eee_supp(tp);
2172 rtl_set_eee_adv(tp, supported);
2175 static void rtl8169_get_mac_version(struct rtl8169_private *tp)
2178 * The driver currently handles the 8168Bf and the 8168Be identically
2179 * but they can be identified more specifically through the test below
2182 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
2184 * Same thing for the 8101Eb and the 8101Ec:
2186 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
2188 static const struct rtl_mac_info {
2193 /* 8168EP family. */
2194 { 0x7cf, 0x502, RTL_GIGA_MAC_VER_51 },
2195 { 0x7cf, 0x501, RTL_GIGA_MAC_VER_50 },
2196 { 0x7cf, 0x500, RTL_GIGA_MAC_VER_49 },
2199 { 0x7cf, 0x541, RTL_GIGA_MAC_VER_46 },
2200 { 0x7cf, 0x540, RTL_GIGA_MAC_VER_45 },
2203 { 0x7cf, 0x5c8, RTL_GIGA_MAC_VER_44 },
2204 { 0x7cf, 0x509, RTL_GIGA_MAC_VER_42 },
2205 { 0x7cf, 0x4c1, RTL_GIGA_MAC_VER_41 },
2206 { 0x7cf, 0x4c0, RTL_GIGA_MAC_VER_40 },
2209 { 0x7c8, 0x488, RTL_GIGA_MAC_VER_38 },
2210 { 0x7cf, 0x481, RTL_GIGA_MAC_VER_36 },
2211 { 0x7cf, 0x480, RTL_GIGA_MAC_VER_35 },
2214 { 0x7c8, 0x2c8, RTL_GIGA_MAC_VER_34 },
2215 { 0x7cf, 0x2c1, RTL_GIGA_MAC_VER_32 },
2216 { 0x7c8, 0x2c0, RTL_GIGA_MAC_VER_33 },
2219 { 0x7cf, 0x281, RTL_GIGA_MAC_VER_25 },
2220 { 0x7c8, 0x280, RTL_GIGA_MAC_VER_26 },
2222 /* 8168DP family. */
2223 { 0x7cf, 0x288, RTL_GIGA_MAC_VER_27 },
2224 { 0x7cf, 0x28a, RTL_GIGA_MAC_VER_28 },
2225 { 0x7cf, 0x28b, RTL_GIGA_MAC_VER_31 },
2228 { 0x7cf, 0x3c9, RTL_GIGA_MAC_VER_23 },
2229 { 0x7cf, 0x3c8, RTL_GIGA_MAC_VER_18 },
2230 { 0x7c8, 0x3c8, RTL_GIGA_MAC_VER_24 },
2231 { 0x7cf, 0x3c0, RTL_GIGA_MAC_VER_19 },
2232 { 0x7cf, 0x3c2, RTL_GIGA_MAC_VER_20 },
2233 { 0x7cf, 0x3c3, RTL_GIGA_MAC_VER_21 },
2234 { 0x7c8, 0x3c0, RTL_GIGA_MAC_VER_22 },
2237 { 0x7cf, 0x380, RTL_GIGA_MAC_VER_12 },
2238 { 0x7c8, 0x380, RTL_GIGA_MAC_VER_17 },
2239 { 0x7c8, 0x300, RTL_GIGA_MAC_VER_11 },
2242 { 0x7c8, 0x448, RTL_GIGA_MAC_VER_39 },
2243 { 0x7c8, 0x440, RTL_GIGA_MAC_VER_37 },
2244 { 0x7cf, 0x409, RTL_GIGA_MAC_VER_29 },
2245 { 0x7c8, 0x408, RTL_GIGA_MAC_VER_30 },
2246 { 0x7cf, 0x349, RTL_GIGA_MAC_VER_08 },
2247 { 0x7cf, 0x249, RTL_GIGA_MAC_VER_08 },
2248 { 0x7cf, 0x348, RTL_GIGA_MAC_VER_07 },
2249 { 0x7cf, 0x248, RTL_GIGA_MAC_VER_07 },
2250 { 0x7cf, 0x340, RTL_GIGA_MAC_VER_13 },
2251 { 0x7cf, 0x343, RTL_GIGA_MAC_VER_10 },
2252 { 0x7cf, 0x342, RTL_GIGA_MAC_VER_16 },
2253 { 0x7c8, 0x348, RTL_GIGA_MAC_VER_09 },
2254 { 0x7c8, 0x248, RTL_GIGA_MAC_VER_09 },
2255 { 0x7c8, 0x340, RTL_GIGA_MAC_VER_16 },
2256 /* FIXME: where did these entries come from ? -- FR */
2257 { 0xfc8, 0x388, RTL_GIGA_MAC_VER_15 },
2258 { 0xfc8, 0x308, RTL_GIGA_MAC_VER_14 },
2261 { 0xfc8, 0x980, RTL_GIGA_MAC_VER_06 },
2262 { 0xfc8, 0x180, RTL_GIGA_MAC_VER_05 },
2263 { 0xfc8, 0x100, RTL_GIGA_MAC_VER_04 },
2264 { 0xfc8, 0x040, RTL_GIGA_MAC_VER_03 },
2265 { 0xfc8, 0x008, RTL_GIGA_MAC_VER_02 },
2266 { 0xfc8, 0x000, RTL_GIGA_MAC_VER_01 },
2269 { 0x000, 0x000, RTL_GIGA_MAC_NONE }
2271 const struct rtl_mac_info *p = mac_info;
2272 u16 reg = RTL_R32(tp, TxConfig) >> 20;
2274 while ((reg & p->mask) != p->val)
2276 tp->mac_version = p->mac_version;
2278 if (tp->mac_version == RTL_GIGA_MAC_NONE) {
2279 dev_err(tp_to_dev(tp), "unknown chip XID %03x\n", reg & 0xfcf);
2280 } else if (!tp->supports_gmii) {
2281 if (tp->mac_version == RTL_GIGA_MAC_VER_42)
2282 tp->mac_version = RTL_GIGA_MAC_VER_43;
2283 else if (tp->mac_version == RTL_GIGA_MAC_VER_45)
2284 tp->mac_version = RTL_GIGA_MAC_VER_47;
2285 else if (tp->mac_version == RTL_GIGA_MAC_VER_46)
2286 tp->mac_version = RTL_GIGA_MAC_VER_48;
2295 static void rtl_writephy_batch(struct rtl8169_private *tp,
2296 const struct phy_reg *regs, int len)
2299 rtl_writephy(tp, regs->reg, regs->val);
2304 #define PHY_READ 0x00000000
2305 #define PHY_DATA_OR 0x10000000
2306 #define PHY_DATA_AND 0x20000000
2307 #define PHY_BJMPN 0x30000000
2308 #define PHY_MDIO_CHG 0x40000000
2309 #define PHY_CLEAR_READCOUNT 0x70000000
2310 #define PHY_WRITE 0x80000000
2311 #define PHY_READCOUNT_EQ_SKIP 0x90000000
2312 #define PHY_COMP_EQ_SKIPN 0xa0000000
2313 #define PHY_COMP_NEQ_SKIPN 0xb0000000
2314 #define PHY_WRITE_PREVIOUS 0xc0000000
2315 #define PHY_SKIPN 0xd0000000
2316 #define PHY_DELAY_MS 0xe0000000
2320 char version[RTL_VER_SIZE];
2326 #define FW_OPCODE_SIZE sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
2328 static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2330 const struct firmware *fw = rtl_fw->fw;
2331 struct fw_info *fw_info = (struct fw_info *)fw->data;
2332 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2333 char *version = rtl_fw->version;
2336 if (fw->size < FW_OPCODE_SIZE)
2339 if (!fw_info->magic) {
2340 size_t i, size, start;
2343 if (fw->size < sizeof(*fw_info))
2346 for (i = 0; i < fw->size; i++)
2347 checksum += fw->data[i];
2351 start = le32_to_cpu(fw_info->fw_start);
2352 if (start > fw->size)
2355 size = le32_to_cpu(fw_info->fw_len);
2356 if (size > (fw->size - start) / FW_OPCODE_SIZE)
2359 memcpy(version, fw_info->version, RTL_VER_SIZE);
2361 pa->code = (__le32 *)(fw->data + start);
2364 if (fw->size % FW_OPCODE_SIZE)
2367 strlcpy(version, tp->fw_name, RTL_VER_SIZE);
2369 pa->code = (__le32 *)fw->data;
2370 pa->size = fw->size / FW_OPCODE_SIZE;
2372 version[RTL_VER_SIZE - 1] = 0;
2379 static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev,
2380 struct rtl_fw_phy_action *pa)
2385 for (index = 0; index < pa->size; index++) {
2386 u32 action = le32_to_cpu(pa->code[index]);
2387 u32 regno = (action & 0x0fff0000) >> 16;
2389 switch(action & 0xf0000000) {
2394 case PHY_CLEAR_READCOUNT:
2396 case PHY_WRITE_PREVIOUS:
2401 if (regno > index) {
2402 netif_err(tp, ifup, tp->dev,
2403 "Out of range of firmware\n");
2407 case PHY_READCOUNT_EQ_SKIP:
2408 if (index + 2 >= pa->size) {
2409 netif_err(tp, ifup, tp->dev,
2410 "Out of range of firmware\n");
2414 case PHY_COMP_EQ_SKIPN:
2415 case PHY_COMP_NEQ_SKIPN:
2417 if (index + 1 + regno >= pa->size) {
2418 netif_err(tp, ifup, tp->dev,
2419 "Out of range of firmware\n");
2425 netif_err(tp, ifup, tp->dev,
2426 "Invalid action 0x%08x\n", action);
2435 static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2437 struct net_device *dev = tp->dev;
2440 if (!rtl_fw_format_ok(tp, rtl_fw)) {
2441 netif_err(tp, ifup, dev, "invalid firmware\n");
2445 if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action))
2451 static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2453 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2454 struct mdio_ops org, *ops = &tp->mdio_ops;
2458 predata = count = 0;
2459 org.write = ops->write;
2460 org.read = ops->read;
2462 for (index = 0; index < pa->size; ) {
2463 u32 action = le32_to_cpu(pa->code[index]);
2464 u32 data = action & 0x0000ffff;
2465 u32 regno = (action & 0x0fff0000) >> 16;
2470 switch(action & 0xf0000000) {
2472 predata = rtl_readphy(tp, regno);
2489 ops->write = org.write;
2490 ops->read = org.read;
2491 } else if (data == 1) {
2492 ops->write = mac_mcu_write;
2493 ops->read = mac_mcu_read;
2498 case PHY_CLEAR_READCOUNT:
2503 rtl_writephy(tp, regno, data);
2506 case PHY_READCOUNT_EQ_SKIP:
2507 index += (count == data) ? 2 : 1;
2509 case PHY_COMP_EQ_SKIPN:
2510 if (predata == data)
2514 case PHY_COMP_NEQ_SKIPN:
2515 if (predata != data)
2519 case PHY_WRITE_PREVIOUS:
2520 rtl_writephy(tp, regno, predata);
2536 ops->write = org.write;
2537 ops->read = org.read;
2540 static void rtl_release_firmware(struct rtl8169_private *tp)
2543 release_firmware(tp->rtl_fw->fw);
2549 static void rtl_apply_firmware(struct rtl8169_private *tp)
2551 /* TODO: release firmware once rtl_phy_write_fw signals failures. */
2553 rtl_phy_write_fw(tp, tp->rtl_fw);
2556 static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
2558 if (rtl_readphy(tp, reg) != val)
2559 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
2561 rtl_apply_firmware(tp);
2564 static void rtl8168_config_eee_mac(struct rtl8169_private *tp)
2566 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_1111, 0x0003, 0x0000, ERIAR_EXGMAC);
2569 static void rtl8168f_config_eee_phy(struct rtl8169_private *tp)
2571 struct phy_device *phydev = tp->phydev;
2573 phy_write(phydev, 0x1f, 0x0007);
2574 phy_write(phydev, 0x1e, 0x0020);
2575 phy_set_bits(phydev, 0x15, BIT(8));
2577 phy_write(phydev, 0x1f, 0x0005);
2578 phy_write(phydev, 0x05, 0x8b85);
2579 phy_set_bits(phydev, 0x06, BIT(13));
2581 phy_write(phydev, 0x1f, 0x0000);
2584 static void rtl8168g_config_eee_phy(struct rtl8169_private *tp)
2586 phy_write(tp->phydev, 0x1f, 0x0a43);
2587 phy_set_bits(tp->phydev, 0x11, BIT(4));
2588 phy_write(tp->phydev, 0x1f, 0x0000);
2591 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
2593 static const struct phy_reg phy_reg_init[] = {
2655 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2658 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
2660 static const struct phy_reg phy_reg_init[] = {
2666 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2669 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2671 struct pci_dev *pdev = tp->pci_dev;
2673 if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
2674 (pdev->subsystem_device != 0xe000))
2677 rtl_writephy(tp, 0x1f, 0x0001);
2678 rtl_writephy(tp, 0x10, 0xf01b);
2679 rtl_writephy(tp, 0x1f, 0x0000);
2682 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2684 static const struct phy_reg phy_reg_init[] = {
2724 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2726 rtl8169scd_hw_phy_config_quirk(tp);
2729 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
2731 static const struct phy_reg phy_reg_init[] = {
2779 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2782 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
2784 static const struct phy_reg phy_reg_init[] = {
2789 rtl_writephy(tp, 0x1f, 0x0001);
2790 rtl_patchphy(tp, 0x16, 1 << 0);
2792 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2795 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
2797 static const struct phy_reg phy_reg_init[] = {
2803 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2806 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
2808 static const struct phy_reg phy_reg_init[] = {
2816 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2819 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
2821 static const struct phy_reg phy_reg_init[] = {
2827 rtl_writephy(tp, 0x1f, 0x0000);
2828 rtl_patchphy(tp, 0x14, 1 << 5);
2829 rtl_patchphy(tp, 0x0d, 1 << 5);
2831 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2834 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
2836 static const struct phy_reg phy_reg_init[] = {
2856 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2858 rtl_patchphy(tp, 0x14, 1 << 5);
2859 rtl_patchphy(tp, 0x0d, 1 << 5);
2860 rtl_writephy(tp, 0x1f, 0x0000);
2863 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
2865 static const struct phy_reg phy_reg_init[] = {
2883 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2885 rtl_patchphy(tp, 0x16, 1 << 0);
2886 rtl_patchphy(tp, 0x14, 1 << 5);
2887 rtl_patchphy(tp, 0x0d, 1 << 5);
2888 rtl_writephy(tp, 0x1f, 0x0000);
2891 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
2893 static const struct phy_reg phy_reg_init[] = {
2905 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2907 rtl_patchphy(tp, 0x16, 1 << 0);
2908 rtl_patchphy(tp, 0x14, 1 << 5);
2909 rtl_patchphy(tp, 0x0d, 1 << 5);
2910 rtl_writephy(tp, 0x1f, 0x0000);
2913 static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
2915 rtl8168c_3_hw_phy_config(tp);
2918 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
2920 static const struct phy_reg phy_reg_init_0[] = {
2921 /* Channel Estimation */
2942 * Enhance line driver power
2951 * Can not link to 1Gbps with bad cable
2952 * Decrease SNR threshold form 21.07dB to 19.04dB
2961 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2965 * Fine Tune Switching regulator parameter
2967 rtl_writephy(tp, 0x1f, 0x0002);
2968 rtl_w0w1_phy(tp, 0x0b, 0x0010, 0x00ef);
2969 rtl_w0w1_phy(tp, 0x0c, 0xa200, 0x5d00);
2971 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
2972 static const struct phy_reg phy_reg_init[] = {
2982 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2984 val = rtl_readphy(tp, 0x0d);
2986 if ((val & 0x00ff) != 0x006c) {
2987 static const u32 set[] = {
2988 0x0065, 0x0066, 0x0067, 0x0068,
2989 0x0069, 0x006a, 0x006b, 0x006c
2993 rtl_writephy(tp, 0x1f, 0x0002);
2996 for (i = 0; i < ARRAY_SIZE(set); i++)
2997 rtl_writephy(tp, 0x0d, val | set[i]);
3000 static const struct phy_reg phy_reg_init[] = {
3008 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3011 /* RSET couple improve */
3012 rtl_writephy(tp, 0x1f, 0x0002);
3013 rtl_patchphy(tp, 0x0d, 0x0300);
3014 rtl_patchphy(tp, 0x0f, 0x0010);
3016 /* Fine tune PLL performance */
3017 rtl_writephy(tp, 0x1f, 0x0002);
3018 rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
3019 rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
3021 rtl_writephy(tp, 0x1f, 0x0005);
3022 rtl_writephy(tp, 0x05, 0x001b);
3024 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
3026 rtl_writephy(tp, 0x1f, 0x0000);
3029 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
3031 static const struct phy_reg phy_reg_init_0[] = {
3032 /* Channel Estimation */
3053 * Enhance line driver power
3062 * Can not link to 1Gbps with bad cable
3063 * Decrease SNR threshold form 21.07dB to 19.04dB
3072 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
3074 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
3075 static const struct phy_reg phy_reg_init[] = {
3086 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3088 val = rtl_readphy(tp, 0x0d);
3089 if ((val & 0x00ff) != 0x006c) {
3090 static const u32 set[] = {
3091 0x0065, 0x0066, 0x0067, 0x0068,
3092 0x0069, 0x006a, 0x006b, 0x006c
3096 rtl_writephy(tp, 0x1f, 0x0002);
3099 for (i = 0; i < ARRAY_SIZE(set); i++)
3100 rtl_writephy(tp, 0x0d, val | set[i]);
3103 static const struct phy_reg phy_reg_init[] = {
3111 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3114 /* Fine tune PLL performance */
3115 rtl_writephy(tp, 0x1f, 0x0002);
3116 rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
3117 rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
3119 /* Switching regulator Slew rate */
3120 rtl_writephy(tp, 0x1f, 0x0002);
3121 rtl_patchphy(tp, 0x0f, 0x0017);
3123 rtl_writephy(tp, 0x1f, 0x0005);
3124 rtl_writephy(tp, 0x05, 0x001b);
3126 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
3128 rtl_writephy(tp, 0x1f, 0x0000);
3131 static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
3133 static const struct phy_reg phy_reg_init[] = {
3189 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3192 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
3194 static const struct phy_reg phy_reg_init[] = {
3204 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3205 rtl_patchphy(tp, 0x0d, 1 << 5);
3208 static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
3210 static const struct phy_reg phy_reg_init[] = {
3211 /* Enable Delay cap */
3217 /* Channel estimation fine tune */
3226 /* Update PFM & 10M TX idle timer */
3238 rtl_apply_firmware(tp);
3240 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3242 /* DCO enable for 10M IDLE Power */
3243 rtl_writephy(tp, 0x1f, 0x0007);
3244 rtl_writephy(tp, 0x1e, 0x0023);
3245 rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
3246 rtl_writephy(tp, 0x1f, 0x0000);
3248 /* For impedance matching */
3249 rtl_writephy(tp, 0x1f, 0x0002);
3250 rtl_w0w1_phy(tp, 0x08, 0x8000, 0x7f00);
3251 rtl_writephy(tp, 0x1f, 0x0000);
3253 /* PHY auto speed down */
3254 rtl_writephy(tp, 0x1f, 0x0007);
3255 rtl_writephy(tp, 0x1e, 0x002d);
3256 rtl_w0w1_phy(tp, 0x18, 0x0050, 0x0000);
3257 rtl_writephy(tp, 0x1f, 0x0000);
3258 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3260 rtl_writephy(tp, 0x1f, 0x0005);
3261 rtl_writephy(tp, 0x05, 0x8b86);
3262 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3263 rtl_writephy(tp, 0x1f, 0x0000);
3265 rtl_writephy(tp, 0x1f, 0x0005);
3266 rtl_writephy(tp, 0x05, 0x8b85);
3267 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
3268 rtl_writephy(tp, 0x1f, 0x0007);
3269 rtl_writephy(tp, 0x1e, 0x0020);
3270 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x1100);
3271 rtl_writephy(tp, 0x1f, 0x0006);
3272 rtl_writephy(tp, 0x00, 0x5a00);
3273 rtl_writephy(tp, 0x1f, 0x0000);
3274 rtl_writephy(tp, 0x0d, 0x0007);
3275 rtl_writephy(tp, 0x0e, 0x003c);
3276 rtl_writephy(tp, 0x0d, 0x4007);
3277 rtl_writephy(tp, 0x0e, 0x0000);
3278 rtl_writephy(tp, 0x0d, 0x0000);
3281 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, u8 *addr)
3284 addr[0] | (addr[1] << 8),
3285 addr[2] | (addr[3] << 8),
3286 addr[4] | (addr[5] << 8)
3288 const struct exgmac_reg e[] = {
3289 { .addr = 0xe0, ERIAR_MASK_1111, .val = w[0] | (w[1] << 16) },
3290 { .addr = 0xe4, ERIAR_MASK_1111, .val = w[2] },
3291 { .addr = 0xf0, ERIAR_MASK_1111, .val = w[0] << 16 },
3292 { .addr = 0xf4, ERIAR_MASK_1111, .val = w[1] | (w[2] << 16) }
3295 rtl_write_exgmac_batch(tp, e, ARRAY_SIZE(e));
3298 static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
3300 static const struct phy_reg phy_reg_init[] = {
3301 /* Enable Delay cap */
3310 /* Channel estimation fine tune */
3327 rtl_apply_firmware(tp);
3329 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3331 /* For 4-corner performance improve */
3332 rtl_writephy(tp, 0x1f, 0x0005);
3333 rtl_writephy(tp, 0x05, 0x8b80);
3334 rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
3335 rtl_writephy(tp, 0x1f, 0x0000);
3337 /* PHY auto speed down */
3338 rtl_writephy(tp, 0x1f, 0x0004);
3339 rtl_writephy(tp, 0x1f, 0x0007);
3340 rtl_writephy(tp, 0x1e, 0x002d);
3341 rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
3342 rtl_writephy(tp, 0x1f, 0x0002);
3343 rtl_writephy(tp, 0x1f, 0x0000);
3344 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3346 /* improve 10M EEE waveform */
3347 rtl_writephy(tp, 0x1f, 0x0005);
3348 rtl_writephy(tp, 0x05, 0x8b86);
3349 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3350 rtl_writephy(tp, 0x1f, 0x0000);
3352 /* Improve 2-pair detection performance */
3353 rtl_writephy(tp, 0x1f, 0x0005);
3354 rtl_writephy(tp, 0x05, 0x8b85);
3355 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3356 rtl_writephy(tp, 0x1f, 0x0000);
3358 rtl8168f_config_eee_phy(tp);
3362 rtl_writephy(tp, 0x1f, 0x0003);
3363 rtl_w0w1_phy(tp, 0x19, 0x0001, 0x0000);
3364 rtl_w0w1_phy(tp, 0x10, 0x0400, 0x0000);
3365 rtl_writephy(tp, 0x1f, 0x0000);
3366 rtl_writephy(tp, 0x1f, 0x0005);
3367 rtl_w0w1_phy(tp, 0x01, 0x0100, 0x0000);
3368 rtl_writephy(tp, 0x1f, 0x0000);
3370 /* Broken BIOS workaround: feed GigaMAC registers with MAC address. */
3371 rtl_rar_exgmac_set(tp, tp->dev->dev_addr);
3374 static void rtl8168f_hw_phy_config(struct rtl8169_private *tp)
3376 /* For 4-corner performance improve */
3377 rtl_writephy(tp, 0x1f, 0x0005);
3378 rtl_writephy(tp, 0x05, 0x8b80);
3379 rtl_w0w1_phy(tp, 0x06, 0x0006, 0x0000);
3380 rtl_writephy(tp, 0x1f, 0x0000);
3382 /* PHY auto speed down */
3383 rtl_writephy(tp, 0x1f, 0x0007);
3384 rtl_writephy(tp, 0x1e, 0x002d);
3385 rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
3386 rtl_writephy(tp, 0x1f, 0x0000);
3387 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3389 /* Improve 10M EEE waveform */
3390 rtl_writephy(tp, 0x1f, 0x0005);
3391 rtl_writephy(tp, 0x05, 0x8b86);
3392 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3393 rtl_writephy(tp, 0x1f, 0x0000);
3395 rtl8168f_config_eee_phy(tp);
3399 static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp)
3401 static const struct phy_reg phy_reg_init[] = {
3402 /* Channel estimation fine tune */
3407 /* Modify green table for giga & fnet */
3424 /* Modify green table for 10M */
3430 /* Disable hiimpedance detection (RTCT) */
3436 rtl_apply_firmware(tp);
3438 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3440 rtl8168f_hw_phy_config(tp);
3442 /* Improve 2-pair detection performance */
3443 rtl_writephy(tp, 0x1f, 0x0005);
3444 rtl_writephy(tp, 0x05, 0x8b85);
3445 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3446 rtl_writephy(tp, 0x1f, 0x0000);
3449 static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp)
3451 rtl_apply_firmware(tp);
3453 rtl8168f_hw_phy_config(tp);
3456 static void rtl8411_hw_phy_config(struct rtl8169_private *tp)
3458 static const struct phy_reg phy_reg_init[] = {
3459 /* Channel estimation fine tune */
3464 /* Modify green table for giga & fnet */
3481 /* Modify green table for 10M */
3487 /* Disable hiimpedance detection (RTCT) */
3494 rtl_apply_firmware(tp);
3496 rtl8168f_hw_phy_config(tp);
3498 /* Improve 2-pair detection performance */
3499 rtl_writephy(tp, 0x1f, 0x0005);
3500 rtl_writephy(tp, 0x05, 0x8b85);
3501 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3502 rtl_writephy(tp, 0x1f, 0x0000);
3504 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3506 /* Modify green table for giga */
3507 rtl_writephy(tp, 0x1f, 0x0005);
3508 rtl_writephy(tp, 0x05, 0x8b54);
3509 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
3510 rtl_writephy(tp, 0x05, 0x8b5d);
3511 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
3512 rtl_writephy(tp, 0x05, 0x8a7c);
3513 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3514 rtl_writephy(tp, 0x05, 0x8a7f);
3515 rtl_w0w1_phy(tp, 0x06, 0x0100, 0x0000);
3516 rtl_writephy(tp, 0x05, 0x8a82);
3517 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3518 rtl_writephy(tp, 0x05, 0x8a85);
3519 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3520 rtl_writephy(tp, 0x05, 0x8a88);
3521 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3522 rtl_writephy(tp, 0x1f, 0x0000);
3524 /* uc same-seed solution */
3525 rtl_writephy(tp, 0x1f, 0x0005);
3526 rtl_writephy(tp, 0x05, 0x8b85);
3527 rtl_w0w1_phy(tp, 0x06, 0x8000, 0x0000);
3528 rtl_writephy(tp, 0x1f, 0x0000);
3531 rtl_writephy(tp, 0x1f, 0x0003);
3532 rtl_w0w1_phy(tp, 0x19, 0x0000, 0x0001);
3533 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0400);
3534 rtl_writephy(tp, 0x1f, 0x0000);
3537 static void rtl8168g_disable_aldps(struct rtl8169_private *tp)
3539 phy_write(tp->phydev, 0x1f, 0x0a43);
3540 phy_clear_bits(tp->phydev, 0x10, BIT(2));
3543 static void rtl8168g_phy_adjust_10m_aldps(struct rtl8169_private *tp)
3545 struct phy_device *phydev = tp->phydev;
3547 phy_write(phydev, 0x1f, 0x0bcc);
3548 phy_clear_bits(phydev, 0x14, BIT(8));
3550 phy_write(phydev, 0x1f, 0x0a44);
3551 phy_set_bits(phydev, 0x11, BIT(7) | BIT(6));
3553 phy_write(phydev, 0x1f, 0x0a43);
3554 phy_write(phydev, 0x13, 0x8084);
3555 phy_clear_bits(phydev, 0x14, BIT(14) | BIT(13));
3556 phy_set_bits(phydev, 0x10, BIT(12) | BIT(1) | BIT(0));
3558 phy_write(phydev, 0x1f, 0x0000);
3561 static void rtl8168g_1_hw_phy_config(struct rtl8169_private *tp)
3563 rtl_apply_firmware(tp);
3565 rtl_writephy(tp, 0x1f, 0x0a46);
3566 if (rtl_readphy(tp, 0x10) & 0x0100) {
3567 rtl_writephy(tp, 0x1f, 0x0bcc);
3568 rtl_w0w1_phy(tp, 0x12, 0x0000, 0x8000);
3570 rtl_writephy(tp, 0x1f, 0x0bcc);
3571 rtl_w0w1_phy(tp, 0x12, 0x8000, 0x0000);
3574 rtl_writephy(tp, 0x1f, 0x0a46);
3575 if (rtl_readphy(tp, 0x13) & 0x0100) {
3576 rtl_writephy(tp, 0x1f, 0x0c41);
3577 rtl_w0w1_phy(tp, 0x15, 0x0002, 0x0000);
3579 rtl_writephy(tp, 0x1f, 0x0c41);
3580 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x0002);
3583 /* Enable PHY auto speed down */
3584 rtl_writephy(tp, 0x1f, 0x0a44);
3585 rtl_w0w1_phy(tp, 0x11, 0x000c, 0x0000);
3587 rtl8168g_phy_adjust_10m_aldps(tp);
3589 /* EEE auto-fallback function */
3590 rtl_writephy(tp, 0x1f, 0x0a4b);
3591 rtl_w0w1_phy(tp, 0x11, 0x0004, 0x0000);
3593 /* Enable UC LPF tune function */
3594 rtl_writephy(tp, 0x1f, 0x0a43);
3595 rtl_writephy(tp, 0x13, 0x8012);
3596 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3598 rtl_writephy(tp, 0x1f, 0x0c42);
3599 rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
3601 /* Improve SWR Efficiency */
3602 rtl_writephy(tp, 0x1f, 0x0bcd);
3603 rtl_writephy(tp, 0x14, 0x5065);
3604 rtl_writephy(tp, 0x14, 0xd065);
3605 rtl_writephy(tp, 0x1f, 0x0bc8);
3606 rtl_writephy(tp, 0x11, 0x5655);
3607 rtl_writephy(tp, 0x1f, 0x0bcd);
3608 rtl_writephy(tp, 0x14, 0x1065);
3609 rtl_writephy(tp, 0x14, 0x9065);
3610 rtl_writephy(tp, 0x14, 0x1065);
3612 rtl8168g_disable_aldps(tp);
3613 rtl8168g_config_eee_phy(tp);
3617 static void rtl8168g_2_hw_phy_config(struct rtl8169_private *tp)
3619 rtl_apply_firmware(tp);
3620 rtl8168g_config_eee_phy(tp);
3624 static void rtl8168h_1_hw_phy_config(struct rtl8169_private *tp)
3629 rtl_apply_firmware(tp);
3631 /* CHN EST parameters adjust - giga master */
3632 rtl_writephy(tp, 0x1f, 0x0a43);
3633 rtl_writephy(tp, 0x13, 0x809b);
3634 rtl_w0w1_phy(tp, 0x14, 0x8000, 0xf800);
3635 rtl_writephy(tp, 0x13, 0x80a2);
3636 rtl_w0w1_phy(tp, 0x14, 0x8000, 0xff00);
3637 rtl_writephy(tp, 0x13, 0x80a4);
3638 rtl_w0w1_phy(tp, 0x14, 0x8500, 0xff00);
3639 rtl_writephy(tp, 0x13, 0x809c);
3640 rtl_w0w1_phy(tp, 0x14, 0xbd00, 0xff00);
3641 rtl_writephy(tp, 0x1f, 0x0000);
3643 /* CHN EST parameters adjust - giga slave */
3644 rtl_writephy(tp, 0x1f, 0x0a43);
3645 rtl_writephy(tp, 0x13, 0x80ad);
3646 rtl_w0w1_phy(tp, 0x14, 0x7000, 0xf800);
3647 rtl_writephy(tp, 0x13, 0x80b4);
3648 rtl_w0w1_phy(tp, 0x14, 0x5000, 0xff00);
3649 rtl_writephy(tp, 0x13, 0x80ac);
3650 rtl_w0w1_phy(tp, 0x14, 0x4000, 0xff00);
3651 rtl_writephy(tp, 0x1f, 0x0000);
3653 /* CHN EST parameters adjust - fnet */
3654 rtl_writephy(tp, 0x1f, 0x0a43);
3655 rtl_writephy(tp, 0x13, 0x808e);
3656 rtl_w0w1_phy(tp, 0x14, 0x1200, 0xff00);
3657 rtl_writephy(tp, 0x13, 0x8090);
3658 rtl_w0w1_phy(tp, 0x14, 0xe500, 0xff00);
3659 rtl_writephy(tp, 0x13, 0x8092);
3660 rtl_w0w1_phy(tp, 0x14, 0x9f00, 0xff00);
3661 rtl_writephy(tp, 0x1f, 0x0000);
3663 /* enable R-tune & PGA-retune function */
3665 rtl_writephy(tp, 0x1f, 0x0a46);
3666 data = rtl_readphy(tp, 0x13);
3669 dout_tapbin |= data;
3670 data = rtl_readphy(tp, 0x12);
3673 dout_tapbin |= data;
3674 dout_tapbin = ~(dout_tapbin^0x08);
3676 dout_tapbin &= 0xf000;
3677 rtl_writephy(tp, 0x1f, 0x0a43);
3678 rtl_writephy(tp, 0x13, 0x827a);
3679 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3680 rtl_writephy(tp, 0x13, 0x827b);
3681 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3682 rtl_writephy(tp, 0x13, 0x827c);
3683 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3684 rtl_writephy(tp, 0x13, 0x827d);
3685 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3687 rtl_writephy(tp, 0x1f, 0x0a43);
3688 rtl_writephy(tp, 0x13, 0x0811);
3689 rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
3690 rtl_writephy(tp, 0x1f, 0x0a42);
3691 rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
3692 rtl_writephy(tp, 0x1f, 0x0000);
3694 /* enable GPHY 10M */
3695 rtl_writephy(tp, 0x1f, 0x0a44);
3696 rtl_w0w1_phy(tp, 0x11, 0x0800, 0x0000);
3697 rtl_writephy(tp, 0x1f, 0x0000);
3699 /* SAR ADC performance */
3700 rtl_writephy(tp, 0x1f, 0x0bca);
3701 rtl_w0w1_phy(tp, 0x17, 0x4000, 0x3000);
3702 rtl_writephy(tp, 0x1f, 0x0000);
3704 rtl_writephy(tp, 0x1f, 0x0a43);
3705 rtl_writephy(tp, 0x13, 0x803f);
3706 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3707 rtl_writephy(tp, 0x13, 0x8047);
3708 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3709 rtl_writephy(tp, 0x13, 0x804f);
3710 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3711 rtl_writephy(tp, 0x13, 0x8057);
3712 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3713 rtl_writephy(tp, 0x13, 0x805f);
3714 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3715 rtl_writephy(tp, 0x13, 0x8067);
3716 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3717 rtl_writephy(tp, 0x13, 0x806f);
3718 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3719 rtl_writephy(tp, 0x1f, 0x0000);
3721 /* disable phy pfm mode */
3722 rtl_writephy(tp, 0x1f, 0x0a44);
3723 rtl_w0w1_phy(tp, 0x11, 0x0000, 0x0080);
3724 rtl_writephy(tp, 0x1f, 0x0000);
3726 rtl8168g_disable_aldps(tp);
3727 rtl8168g_config_eee_phy(tp);
3731 static void rtl8168h_2_hw_phy_config(struct rtl8169_private *tp)
3733 u16 ioffset_p3, ioffset_p2, ioffset_p1, ioffset_p0;
3737 rtl_apply_firmware(tp);
3739 /* CHIN EST parameter update */
3740 rtl_writephy(tp, 0x1f, 0x0a43);
3741 rtl_writephy(tp, 0x13, 0x808a);
3742 rtl_w0w1_phy(tp, 0x14, 0x000a, 0x003f);
3743 rtl_writephy(tp, 0x1f, 0x0000);
3745 /* enable R-tune & PGA-retune function */
3746 rtl_writephy(tp, 0x1f, 0x0a43);
3747 rtl_writephy(tp, 0x13, 0x0811);
3748 rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
3749 rtl_writephy(tp, 0x1f, 0x0a42);
3750 rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
3751 rtl_writephy(tp, 0x1f, 0x0000);
3753 /* enable GPHY 10M */
3754 rtl_writephy(tp, 0x1f, 0x0a44);
3755 rtl_w0w1_phy(tp, 0x11, 0x0800, 0x0000);
3756 rtl_writephy(tp, 0x1f, 0x0000);
3758 r8168_mac_ocp_write(tp, 0xdd02, 0x807d);
3759 data = r8168_mac_ocp_read(tp, 0xdd02);
3760 ioffset_p3 = ((data & 0x80)>>7);
3763 data = r8168_mac_ocp_read(tp, 0xdd00);
3764 ioffset_p3 |= ((data & (0xe000))>>13);
3765 ioffset_p2 = ((data & (0x1e00))>>9);
3766 ioffset_p1 = ((data & (0x01e0))>>5);
3767 ioffset_p0 = ((data & 0x0010)>>4);
3769 ioffset_p0 |= (data & (0x07));
3770 data = (ioffset_p3<<12)|(ioffset_p2<<8)|(ioffset_p1<<4)|(ioffset_p0);
3772 if ((ioffset_p3 != 0x0f) || (ioffset_p2 != 0x0f) ||
3773 (ioffset_p1 != 0x0f) || (ioffset_p0 != 0x0f)) {
3774 rtl_writephy(tp, 0x1f, 0x0bcf);
3775 rtl_writephy(tp, 0x16, data);
3776 rtl_writephy(tp, 0x1f, 0x0000);
3779 /* Modify rlen (TX LPF corner frequency) level */
3780 rtl_writephy(tp, 0x1f, 0x0bcd);
3781 data = rtl_readphy(tp, 0x16);
3786 data = rlen | (rlen<<4) | (rlen<<8) | (rlen<<12);
3787 rtl_writephy(tp, 0x17, data);
3788 rtl_writephy(tp, 0x1f, 0x0bcd);
3789 rtl_writephy(tp, 0x1f, 0x0000);
3791 /* disable phy pfm mode */
3792 rtl_writephy(tp, 0x1f, 0x0a44);
3793 rtl_w0w1_phy(tp, 0x11, 0x0000, 0x0080);
3794 rtl_writephy(tp, 0x1f, 0x0000);
3796 rtl8168g_disable_aldps(tp);
3797 rtl8168g_config_eee_phy(tp);
3801 static void rtl8168ep_1_hw_phy_config(struct rtl8169_private *tp)
3803 /* Enable PHY auto speed down */
3804 rtl_writephy(tp, 0x1f, 0x0a44);
3805 rtl_w0w1_phy(tp, 0x11, 0x000c, 0x0000);
3806 rtl_writephy(tp, 0x1f, 0x0000);
3808 rtl8168g_phy_adjust_10m_aldps(tp);
3810 /* Enable EEE auto-fallback function */
3811 rtl_writephy(tp, 0x1f, 0x0a4b);
3812 rtl_w0w1_phy(tp, 0x11, 0x0004, 0x0000);
3813 rtl_writephy(tp, 0x1f, 0x0000);
3815 /* Enable UC LPF tune function */
3816 rtl_writephy(tp, 0x1f, 0x0a43);
3817 rtl_writephy(tp, 0x13, 0x8012);
3818 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3819 rtl_writephy(tp, 0x1f, 0x0000);
3821 /* set rg_sel_sdm_rate */
3822 rtl_writephy(tp, 0x1f, 0x0c42);
3823 rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
3824 rtl_writephy(tp, 0x1f, 0x0000);
3826 rtl8168g_disable_aldps(tp);
3827 rtl8168g_config_eee_phy(tp);
3831 static void rtl8168ep_2_hw_phy_config(struct rtl8169_private *tp)
3833 rtl8168g_phy_adjust_10m_aldps(tp);
3835 /* Enable UC LPF tune function */
3836 rtl_writephy(tp, 0x1f, 0x0a43);
3837 rtl_writephy(tp, 0x13, 0x8012);
3838 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3839 rtl_writephy(tp, 0x1f, 0x0000);
3841 /* Set rg_sel_sdm_rate */
3842 rtl_writephy(tp, 0x1f, 0x0c42);
3843 rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
3844 rtl_writephy(tp, 0x1f, 0x0000);
3846 /* Channel estimation parameters */
3847 rtl_writephy(tp, 0x1f, 0x0a43);
3848 rtl_writephy(tp, 0x13, 0x80f3);
3849 rtl_w0w1_phy(tp, 0x14, 0x8b00, ~0x8bff);
3850 rtl_writephy(tp, 0x13, 0x80f0);
3851 rtl_w0w1_phy(tp, 0x14, 0x3a00, ~0x3aff);
3852 rtl_writephy(tp, 0x13, 0x80ef);
3853 rtl_w0w1_phy(tp, 0x14, 0x0500, ~0x05ff);
3854 rtl_writephy(tp, 0x13, 0x80f6);
3855 rtl_w0w1_phy(tp, 0x14, 0x6e00, ~0x6eff);
3856 rtl_writephy(tp, 0x13, 0x80ec);
3857 rtl_w0w1_phy(tp, 0x14, 0x6800, ~0x68ff);
3858 rtl_writephy(tp, 0x13, 0x80ed);
3859 rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
3860 rtl_writephy(tp, 0x13, 0x80f2);
3861 rtl_w0w1_phy(tp, 0x14, 0xf400, ~0xf4ff);
3862 rtl_writephy(tp, 0x13, 0x80f4);
3863 rtl_w0w1_phy(tp, 0x14, 0x8500, ~0x85ff);
3864 rtl_writephy(tp, 0x1f, 0x0a43);
3865 rtl_writephy(tp, 0x13, 0x8110);
3866 rtl_w0w1_phy(tp, 0x14, 0xa800, ~0xa8ff);
3867 rtl_writephy(tp, 0x13, 0x810f);
3868 rtl_w0w1_phy(tp, 0x14, 0x1d00, ~0x1dff);
3869 rtl_writephy(tp, 0x13, 0x8111);
3870 rtl_w0w1_phy(tp, 0x14, 0xf500, ~0xf5ff);
3871 rtl_writephy(tp, 0x13, 0x8113);
3872 rtl_w0w1_phy(tp, 0x14, 0x6100, ~0x61ff);
3873 rtl_writephy(tp, 0x13, 0x8115);
3874 rtl_w0w1_phy(tp, 0x14, 0x9200, ~0x92ff);
3875 rtl_writephy(tp, 0x13, 0x810e);
3876 rtl_w0w1_phy(tp, 0x14, 0x0400, ~0x04ff);
3877 rtl_writephy(tp, 0x13, 0x810c);
3878 rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
3879 rtl_writephy(tp, 0x13, 0x810b);
3880 rtl_w0w1_phy(tp, 0x14, 0x5a00, ~0x5aff);
3881 rtl_writephy(tp, 0x1f, 0x0a43);
3882 rtl_writephy(tp, 0x13, 0x80d1);
3883 rtl_w0w1_phy(tp, 0x14, 0xff00, ~0xffff);
3884 rtl_writephy(tp, 0x13, 0x80cd);
3885 rtl_w0w1_phy(tp, 0x14, 0x9e00, ~0x9eff);
3886 rtl_writephy(tp, 0x13, 0x80d3);
3887 rtl_w0w1_phy(tp, 0x14, 0x0e00, ~0x0eff);
3888 rtl_writephy(tp, 0x13, 0x80d5);
3889 rtl_w0w1_phy(tp, 0x14, 0xca00, ~0xcaff);
3890 rtl_writephy(tp, 0x13, 0x80d7);
3891 rtl_w0w1_phy(tp, 0x14, 0x8400, ~0x84ff);
3893 /* Force PWM-mode */
3894 rtl_writephy(tp, 0x1f, 0x0bcd);
3895 rtl_writephy(tp, 0x14, 0x5065);
3896 rtl_writephy(tp, 0x14, 0xd065);
3897 rtl_writephy(tp, 0x1f, 0x0bc8);
3898 rtl_writephy(tp, 0x12, 0x00ed);
3899 rtl_writephy(tp, 0x1f, 0x0bcd);
3900 rtl_writephy(tp, 0x14, 0x1065);
3901 rtl_writephy(tp, 0x14, 0x9065);
3902 rtl_writephy(tp, 0x14, 0x1065);
3903 rtl_writephy(tp, 0x1f, 0x0000);
3905 rtl8168g_disable_aldps(tp);
3906 rtl8168g_config_eee_phy(tp);
3910 static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
3912 static const struct phy_reg phy_reg_init[] = {
3919 rtl_writephy(tp, 0x1f, 0x0000);
3920 rtl_patchphy(tp, 0x11, 1 << 12);
3921 rtl_patchphy(tp, 0x19, 1 << 13);
3922 rtl_patchphy(tp, 0x10, 1 << 15);
3924 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3927 static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
3929 static const struct phy_reg phy_reg_init[] = {
3943 /* Disable ALDPS before ram code */
3944 rtl_writephy(tp, 0x1f, 0x0000);
3945 rtl_writephy(tp, 0x18, 0x0310);
3948 rtl_apply_firmware(tp);
3950 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3953 static void rtl8402_hw_phy_config(struct rtl8169_private *tp)
3955 /* Disable ALDPS before setting firmware */
3956 rtl_writephy(tp, 0x1f, 0x0000);
3957 rtl_writephy(tp, 0x18, 0x0310);
3960 rtl_apply_firmware(tp);
3963 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
3964 rtl_writephy(tp, 0x1f, 0x0004);
3965 rtl_writephy(tp, 0x10, 0x401f);
3966 rtl_writephy(tp, 0x19, 0x7030);
3967 rtl_writephy(tp, 0x1f, 0x0000);
3970 static void rtl8106e_hw_phy_config(struct rtl8169_private *tp)
3972 static const struct phy_reg phy_reg_init[] = {
3979 /* Disable ALDPS before ram code */
3980 rtl_writephy(tp, 0x1f, 0x0000);
3981 rtl_writephy(tp, 0x18, 0x0310);
3984 rtl_apply_firmware(tp);
3986 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
3987 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3989 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
3992 static void rtl_hw_phy_config(struct net_device *dev)
3994 struct rtl8169_private *tp = netdev_priv(dev);
3996 switch (tp->mac_version) {
3997 case RTL_GIGA_MAC_VER_01:
3999 case RTL_GIGA_MAC_VER_02:
4000 case RTL_GIGA_MAC_VER_03:
4001 rtl8169s_hw_phy_config(tp);
4003 case RTL_GIGA_MAC_VER_04:
4004 rtl8169sb_hw_phy_config(tp);
4006 case RTL_GIGA_MAC_VER_05:
4007 rtl8169scd_hw_phy_config(tp);
4009 case RTL_GIGA_MAC_VER_06:
4010 rtl8169sce_hw_phy_config(tp);
4012 case RTL_GIGA_MAC_VER_07:
4013 case RTL_GIGA_MAC_VER_08:
4014 case RTL_GIGA_MAC_VER_09:
4015 rtl8102e_hw_phy_config(tp);
4017 case RTL_GIGA_MAC_VER_11:
4018 rtl8168bb_hw_phy_config(tp);
4020 case RTL_GIGA_MAC_VER_12:
4021 rtl8168bef_hw_phy_config(tp);
4023 case RTL_GIGA_MAC_VER_17:
4024 rtl8168bef_hw_phy_config(tp);
4026 case RTL_GIGA_MAC_VER_18:
4027 rtl8168cp_1_hw_phy_config(tp);
4029 case RTL_GIGA_MAC_VER_19:
4030 rtl8168c_1_hw_phy_config(tp);
4032 case RTL_GIGA_MAC_VER_20:
4033 rtl8168c_2_hw_phy_config(tp);
4035 case RTL_GIGA_MAC_VER_21:
4036 rtl8168c_3_hw_phy_config(tp);
4038 case RTL_GIGA_MAC_VER_22:
4039 rtl8168c_4_hw_phy_config(tp);
4041 case RTL_GIGA_MAC_VER_23:
4042 case RTL_GIGA_MAC_VER_24:
4043 rtl8168cp_2_hw_phy_config(tp);
4045 case RTL_GIGA_MAC_VER_25:
4046 rtl8168d_1_hw_phy_config(tp);
4048 case RTL_GIGA_MAC_VER_26:
4049 rtl8168d_2_hw_phy_config(tp);
4051 case RTL_GIGA_MAC_VER_27:
4052 rtl8168d_3_hw_phy_config(tp);
4054 case RTL_GIGA_MAC_VER_28:
4055 rtl8168d_4_hw_phy_config(tp);
4057 case RTL_GIGA_MAC_VER_29:
4058 case RTL_GIGA_MAC_VER_30:
4059 rtl8105e_hw_phy_config(tp);
4061 case RTL_GIGA_MAC_VER_31:
4064 case RTL_GIGA_MAC_VER_32:
4065 case RTL_GIGA_MAC_VER_33:
4066 rtl8168e_1_hw_phy_config(tp);
4068 case RTL_GIGA_MAC_VER_34:
4069 rtl8168e_2_hw_phy_config(tp);
4071 case RTL_GIGA_MAC_VER_35:
4072 rtl8168f_1_hw_phy_config(tp);
4074 case RTL_GIGA_MAC_VER_36:
4075 rtl8168f_2_hw_phy_config(tp);
4078 case RTL_GIGA_MAC_VER_37:
4079 rtl8402_hw_phy_config(tp);
4082 case RTL_GIGA_MAC_VER_38:
4083 rtl8411_hw_phy_config(tp);
4086 case RTL_GIGA_MAC_VER_39:
4087 rtl8106e_hw_phy_config(tp);
4090 case RTL_GIGA_MAC_VER_40:
4091 rtl8168g_1_hw_phy_config(tp);
4093 case RTL_GIGA_MAC_VER_42:
4094 case RTL_GIGA_MAC_VER_43:
4095 case RTL_GIGA_MAC_VER_44:
4096 rtl8168g_2_hw_phy_config(tp);
4098 case RTL_GIGA_MAC_VER_45:
4099 case RTL_GIGA_MAC_VER_47:
4100 rtl8168h_1_hw_phy_config(tp);
4102 case RTL_GIGA_MAC_VER_46:
4103 case RTL_GIGA_MAC_VER_48:
4104 rtl8168h_2_hw_phy_config(tp);
4107 case RTL_GIGA_MAC_VER_49:
4108 rtl8168ep_1_hw_phy_config(tp);
4110 case RTL_GIGA_MAC_VER_50:
4111 case RTL_GIGA_MAC_VER_51:
4112 rtl8168ep_2_hw_phy_config(tp);
4115 case RTL_GIGA_MAC_VER_41:
4121 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
4123 if (!test_and_set_bit(flag, tp->wk.flags))
4124 schedule_work(&tp->wk.work);
4127 static bool rtl_tbi_enabled(struct rtl8169_private *tp)
4129 return (tp->mac_version == RTL_GIGA_MAC_VER_01) &&
4130 (RTL_R8(tp, PHYstatus) & TBI_Enable);
4133 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
4135 rtl_hw_phy_config(dev);
4137 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
4138 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
4139 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4140 netif_dbg(tp, drv, dev,
4141 "Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
4142 RTL_W8(tp, 0x82, 0x01);
4145 /* We may have called phy_speed_down before */
4146 phy_speed_up(tp->phydev);
4148 genphy_soft_reset(tp->phydev);
4150 /* It was reported that several chips end up with 10MBit/Half on a
4151 * 1GBit link after resuming from S3. For whatever reason the PHY on
4152 * these chips doesn't properly start a renegotiation when soft-reset.
4153 * Explicitly requesting a renegotiation fixes this.
4155 if (tp->phydev->autoneg == AUTONEG_ENABLE)
4156 phy_restart_aneg(tp->phydev);
4159 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
4163 rtl_unlock_config_regs(tp);
4165 RTL_W32(tp, MAC4, addr[4] | addr[5] << 8);
4168 RTL_W32(tp, MAC0, addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24);
4171 if (tp->mac_version == RTL_GIGA_MAC_VER_34)
4172 rtl_rar_exgmac_set(tp, addr);
4174 rtl_lock_config_regs(tp);
4176 rtl_unlock_work(tp);
4179 static int rtl_set_mac_address(struct net_device *dev, void *p)
4181 struct rtl8169_private *tp = netdev_priv(dev);
4182 struct device *d = tp_to_dev(tp);
4185 ret = eth_mac_addr(dev, p);
4189 pm_runtime_get_noresume(d);
4191 if (pm_runtime_active(d))
4192 rtl_rar_set(tp, dev->dev_addr);
4194 pm_runtime_put_noidle(d);
4199 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
4201 struct rtl8169_private *tp = netdev_priv(dev);
4203 if (!netif_running(dev))
4206 return phy_mii_ioctl(tp->phydev, ifr, cmd);
4209 static void rtl_init_mdio_ops(struct rtl8169_private *tp)
4211 struct mdio_ops *ops = &tp->mdio_ops;
4213 switch (tp->mac_version) {
4214 case RTL_GIGA_MAC_VER_27:
4215 ops->write = r8168dp_1_mdio_write;
4216 ops->read = r8168dp_1_mdio_read;
4218 case RTL_GIGA_MAC_VER_28:
4219 case RTL_GIGA_MAC_VER_31:
4220 ops->write = r8168dp_2_mdio_write;
4221 ops->read = r8168dp_2_mdio_read;
4223 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
4224 ops->write = r8168g_mdio_write;
4225 ops->read = r8168g_mdio_read;
4228 ops->write = r8169_mdio_write;
4229 ops->read = r8169_mdio_read;
4234 static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
4236 switch (tp->mac_version) {
4237 case RTL_GIGA_MAC_VER_25:
4238 case RTL_GIGA_MAC_VER_26:
4239 case RTL_GIGA_MAC_VER_29:
4240 case RTL_GIGA_MAC_VER_30:
4241 case RTL_GIGA_MAC_VER_32:
4242 case RTL_GIGA_MAC_VER_33:
4243 case RTL_GIGA_MAC_VER_34:
4244 case RTL_GIGA_MAC_VER_37 ... RTL_GIGA_MAC_VER_51:
4245 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) |
4246 AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
4253 static void r8168_pll_power_down(struct rtl8169_private *tp)
4255 if (r8168_check_dash(tp))
4258 if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
4259 tp->mac_version == RTL_GIGA_MAC_VER_33)
4260 rtl_ephy_write(tp, 0x19, 0xff64);
4262 if (device_may_wakeup(tp_to_dev(tp))) {
4263 phy_speed_down(tp->phydev, false);
4264 rtl_wol_suspend_quirk(tp);
4268 switch (tp->mac_version) {
4269 case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_33:
4270 case RTL_GIGA_MAC_VER_37:
4271 case RTL_GIGA_MAC_VER_39:
4272 case RTL_GIGA_MAC_VER_43:
4273 case RTL_GIGA_MAC_VER_44:
4274 case RTL_GIGA_MAC_VER_45:
4275 case RTL_GIGA_MAC_VER_46:
4276 case RTL_GIGA_MAC_VER_47:
4277 case RTL_GIGA_MAC_VER_48:
4278 case RTL_GIGA_MAC_VER_50:
4279 case RTL_GIGA_MAC_VER_51:
4280 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80);
4282 case RTL_GIGA_MAC_VER_40:
4283 case RTL_GIGA_MAC_VER_41:
4284 case RTL_GIGA_MAC_VER_49:
4285 rtl_w0w1_eri(tp, 0x1a8, ERIAR_MASK_1111, 0x00000000,
4286 0xfc000000, ERIAR_EXGMAC);
4287 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80);
4292 static void r8168_pll_power_up(struct rtl8169_private *tp)
4294 switch (tp->mac_version) {
4295 case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_33:
4296 case RTL_GIGA_MAC_VER_37:
4297 case RTL_GIGA_MAC_VER_39:
4298 case RTL_GIGA_MAC_VER_43:
4299 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0x80);
4301 case RTL_GIGA_MAC_VER_44:
4302 case RTL_GIGA_MAC_VER_45:
4303 case RTL_GIGA_MAC_VER_46:
4304 case RTL_GIGA_MAC_VER_47:
4305 case RTL_GIGA_MAC_VER_48:
4306 case RTL_GIGA_MAC_VER_50:
4307 case RTL_GIGA_MAC_VER_51:
4308 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0);
4310 case RTL_GIGA_MAC_VER_40:
4311 case RTL_GIGA_MAC_VER_41:
4312 case RTL_GIGA_MAC_VER_49:
4313 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0);
4314 rtl_w0w1_eri(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000,
4315 0x00000000, ERIAR_EXGMAC);
4319 phy_resume(tp->phydev);
4320 /* give MAC/PHY some time to resume */
4324 static void rtl_pll_power_down(struct rtl8169_private *tp)
4326 switch (tp->mac_version) {
4327 case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_06:
4328 case RTL_GIGA_MAC_VER_13 ... RTL_GIGA_MAC_VER_15:
4331 r8168_pll_power_down(tp);
4335 static void rtl_pll_power_up(struct rtl8169_private *tp)
4337 switch (tp->mac_version) {
4338 case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_06:
4339 case RTL_GIGA_MAC_VER_13 ... RTL_GIGA_MAC_VER_15:
4342 r8168_pll_power_up(tp);
4346 static void rtl_init_rxcfg(struct rtl8169_private *tp)
4348 switch (tp->mac_version) {
4349 case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_06:
4350 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
4351 RTL_W32(tp, RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
4353 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
4354 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36:
4355 case RTL_GIGA_MAC_VER_38:
4356 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
4358 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
4359 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF);
4362 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_DMA_BURST);
4367 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
4369 tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0;
4372 static void rtl_hw_jumbo_enable(struct rtl8169_private *tp)
4374 if (tp->jumbo_ops.enable) {
4375 rtl_unlock_config_regs(tp);
4376 tp->jumbo_ops.enable(tp);
4377 rtl_lock_config_regs(tp);
4381 static void rtl_hw_jumbo_disable(struct rtl8169_private *tp)
4383 if (tp->jumbo_ops.disable) {
4384 rtl_unlock_config_regs(tp);
4385 tp->jumbo_ops.disable(tp);
4386 rtl_lock_config_regs(tp);
4390 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
4392 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
4393 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | Jumbo_En1);
4394 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_512B);
4397 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
4399 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
4400 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~Jumbo_En1);
4401 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4404 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
4406 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
4409 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
4411 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
4414 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
4416 RTL_W8(tp, MaxTxPacketSize, 0x3f);
4417 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
4418 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | 0x01);
4419 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_512B);
4422 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
4424 RTL_W8(tp, MaxTxPacketSize, 0x0c);
4425 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
4426 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~0x01);
4427 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4430 static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp)
4432 rtl_tx_performance_tweak(tp,
4433 PCI_EXP_DEVCTL_READRQ_512B | PCI_EXP_DEVCTL_NOSNOOP_EN);
4436 static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp)
4438 rtl_tx_performance_tweak(tp,
4439 PCI_EXP_DEVCTL_READRQ_4096B | PCI_EXP_DEVCTL_NOSNOOP_EN);
4442 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
4444 r8168b_0_hw_jumbo_enable(tp);
4446 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | (1 << 0));
4449 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
4451 r8168b_0_hw_jumbo_disable(tp);
4453 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0));
4456 static void rtl_init_jumbo_ops(struct rtl8169_private *tp)
4458 struct jumbo_ops *ops = &tp->jumbo_ops;
4460 switch (tp->mac_version) {
4461 case RTL_GIGA_MAC_VER_11:
4462 ops->disable = r8168b_0_hw_jumbo_disable;
4463 ops->enable = r8168b_0_hw_jumbo_enable;
4465 case RTL_GIGA_MAC_VER_12:
4466 case RTL_GIGA_MAC_VER_17:
4467 ops->disable = r8168b_1_hw_jumbo_disable;
4468 ops->enable = r8168b_1_hw_jumbo_enable;
4470 case RTL_GIGA_MAC_VER_18: /* Wild guess. Needs info from Realtek. */
4471 case RTL_GIGA_MAC_VER_19:
4472 case RTL_GIGA_MAC_VER_20:
4473 case RTL_GIGA_MAC_VER_21: /* Wild guess. Needs info from Realtek. */
4474 case RTL_GIGA_MAC_VER_22:
4475 case RTL_GIGA_MAC_VER_23:
4476 case RTL_GIGA_MAC_VER_24:
4477 case RTL_GIGA_MAC_VER_25:
4478 case RTL_GIGA_MAC_VER_26:
4479 ops->disable = r8168c_hw_jumbo_disable;
4480 ops->enable = r8168c_hw_jumbo_enable;
4482 case RTL_GIGA_MAC_VER_27:
4483 case RTL_GIGA_MAC_VER_28:
4484 ops->disable = r8168dp_hw_jumbo_disable;
4485 ops->enable = r8168dp_hw_jumbo_enable;
4487 case RTL_GIGA_MAC_VER_31: /* Wild guess. Needs info from Realtek. */
4488 case RTL_GIGA_MAC_VER_32:
4489 case RTL_GIGA_MAC_VER_33:
4490 case RTL_GIGA_MAC_VER_34:
4491 ops->disable = r8168e_hw_jumbo_disable;
4492 ops->enable = r8168e_hw_jumbo_enable;
4496 * No action needed for jumbo frames with 8169.
4497 * No jumbo for 810x at all.
4499 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
4501 ops->disable = NULL;
4507 DECLARE_RTL_COND(rtl_chipcmd_cond)
4509 return RTL_R8(tp, ChipCmd) & CmdReset;
4512 static void rtl_hw_reset(struct rtl8169_private *tp)
4514 RTL_W8(tp, ChipCmd, CmdReset);
4516 rtl_udelay_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100);
4519 static void rtl_request_firmware(struct rtl8169_private *tp)
4521 struct rtl_fw *rtl_fw;
4524 /* firmware loaded already or no firmware available */
4525 if (tp->rtl_fw || !tp->fw_name)
4528 rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
4532 rc = request_firmware(&rtl_fw->fw, tp->fw_name, tp_to_dev(tp));
4536 rc = rtl_check_firmware(tp, rtl_fw);
4538 goto err_release_firmware;
4540 tp->rtl_fw = rtl_fw;
4544 err_release_firmware:
4545 release_firmware(rtl_fw->fw);
4549 netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n",
4553 static void rtl_rx_close(struct rtl8169_private *tp)
4555 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
4558 DECLARE_RTL_COND(rtl_npq_cond)
4560 return RTL_R8(tp, TxPoll) & NPQ;
4563 DECLARE_RTL_COND(rtl_txcfg_empty_cond)
4565 return RTL_R32(tp, TxConfig) & TXCFG_EMPTY;
4568 static void rtl8169_hw_reset(struct rtl8169_private *tp)
4570 /* Disable interrupts */
4571 rtl8169_irq_mask_and_ack(tp);
4575 switch (tp->mac_version) {
4576 case RTL_GIGA_MAC_VER_27:
4577 case RTL_GIGA_MAC_VER_28:
4578 case RTL_GIGA_MAC_VER_31:
4579 rtl_udelay_loop_wait_low(tp, &rtl_npq_cond, 20, 42*42);
4581 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
4582 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
4583 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
4584 rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);
4587 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
4595 static void rtl_set_tx_config_registers(struct rtl8169_private *tp)
4597 u32 val = TX_DMA_BURST << TxDMAShift |
4598 InterFrameGap << TxInterFrameGapShift;
4600 if (tp->mac_version >= RTL_GIGA_MAC_VER_34 &&
4601 tp->mac_version != RTL_GIGA_MAC_VER_39)
4602 val |= TXCFG_AUTO_FIFO;
4604 RTL_W32(tp, TxConfig, val);
4607 static void rtl_set_rx_max_size(struct rtl8169_private *tp)
4609 /* Low hurts. Let's disable the filtering. */
4610 RTL_W16(tp, RxMaxSize, R8169_RX_BUF_SIZE + 1);
4613 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp)
4616 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
4617 * register to be written before TxDescAddrLow to work.
4618 * Switching from MMIO to I/O access fixes the issue as well.
4620 RTL_W32(tp, TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
4621 RTL_W32(tp, TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
4622 RTL_W32(tp, RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
4623 RTL_W32(tp, RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
4626 static void rtl8169_set_magic_reg(struct rtl8169_private *tp, unsigned mac_version)
4630 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
4632 else if (tp->mac_version == RTL_GIGA_MAC_VER_06)
4637 if (RTL_R8(tp, Config2) & PCI_Clock_66MHz)
4640 RTL_W32(tp, 0x7c, val);
4643 static void rtl_set_rx_mode(struct net_device *dev)
4645 struct rtl8169_private *tp = netdev_priv(dev);
4646 u32 mc_filter[2]; /* Multicast hash filter */
4650 if (dev->flags & IFF_PROMISC) {
4651 /* Unconditionally log net taps. */
4652 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
4654 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
4656 mc_filter[1] = mc_filter[0] = 0xffffffff;
4657 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
4658 (dev->flags & IFF_ALLMULTI)) {
4659 /* Too many to filter perfectly -- accept all multicasts. */
4660 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
4661 mc_filter[1] = mc_filter[0] = 0xffffffff;
4663 struct netdev_hw_addr *ha;
4665 rx_mode = AcceptBroadcast | AcceptMyPhys;
4666 mc_filter[1] = mc_filter[0] = 0;
4667 netdev_for_each_mc_addr(ha, dev) {
4668 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
4669 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
4670 rx_mode |= AcceptMulticast;
4674 if (dev->features & NETIF_F_RXALL)
4675 rx_mode |= (AcceptErr | AcceptRunt);
4677 tmp = (RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK) | rx_mode;
4679 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
4680 u32 data = mc_filter[0];
4682 mc_filter[0] = swab32(mc_filter[1]);
4683 mc_filter[1] = swab32(data);
4686 if (tp->mac_version == RTL_GIGA_MAC_VER_35)
4687 mc_filter[1] = mc_filter[0] = 0xffffffff;
4689 RTL_W32(tp, MAR0 + 4, mc_filter[1]);
4690 RTL_W32(tp, MAR0 + 0, mc_filter[0]);
4692 RTL_W32(tp, RxConfig, tmp);
4695 static void rtl_hw_start(struct rtl8169_private *tp)
4697 rtl_unlock_config_regs(tp);
4701 rtl_set_rx_max_size(tp);
4702 rtl_set_rx_tx_desc_registers(tp);
4703 rtl_lock_config_regs(tp);
4705 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
4706 RTL_R8(tp, IntrMask);
4707 RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb);
4709 rtl_set_tx_config_registers(tp);
4711 rtl_set_rx_mode(tp->dev);
4712 /* no early-rx interrupts */
4713 RTL_W16(tp, MultiIntr, RTL_R16(tp, MultiIntr) & 0xf000);
4717 static void rtl_hw_start_8169(struct rtl8169_private *tp)
4719 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
4720 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4722 RTL_W8(tp, EarlyTxThres, NoEarlyTx);
4724 tp->cp_cmd |= PCIMulRW;
4726 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4727 tp->mac_version == RTL_GIGA_MAC_VER_03) {
4728 netif_dbg(tp, drv, tp->dev,
4729 "Set MAC Reg C+CR Offset 0xe0. Bit 3 and Bit 14 MUST be 1\n");
4730 tp->cp_cmd |= (1 << 14);
4733 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4735 rtl8169_set_magic_reg(tp, tp->mac_version);
4738 * Undocumented corner. Supposedly:
4739 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
4741 RTL_W16(tp, IntrMitigate, 0x0000);
4743 RTL_W32(tp, RxMissed, 0);
4746 DECLARE_RTL_COND(rtl_csiar_cond)
4748 return RTL_R32(tp, CSIAR) & CSIAR_FLAG;
4751 static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)
4753 u32 func = PCI_FUNC(tp->pci_dev->devfn);
4755 RTL_W32(tp, CSIDR, value);
4756 RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
4757 CSIAR_BYTE_ENABLE | func << 16);
4759 rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
4762 static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)
4764 u32 func = PCI_FUNC(tp->pci_dev->devfn);
4766 RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) | func << 16 |
4769 return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
4770 RTL_R32(tp, CSIDR) : ~0;
4773 static void rtl_csi_access_enable(struct rtl8169_private *tp, u8 val)
4775 struct pci_dev *pdev = tp->pci_dev;
4778 /* According to Realtek the value at config space address 0x070f
4779 * controls the L0s/L1 entrance latency. We try standard ECAM access
4780 * first and if it fails fall back to CSI.
4782 if (pdev->cfg_size > 0x070f &&
4783 pci_write_config_byte(pdev, 0x070f, val) == PCIBIOS_SUCCESSFUL)
4786 netdev_notice_once(tp->dev,
4787 "No native access to PCI extended config space, falling back to CSI\n");
4788 csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff;
4789 rtl_csi_write(tp, 0x070c, csi | val << 24);
4792 static void rtl_set_def_aspm_entry_latency(struct rtl8169_private *tp)
4794 rtl_csi_access_enable(tp, 0x27);
4798 unsigned int offset;
4803 static void rtl_ephy_init(struct rtl8169_private *tp, const struct ephy_info *e,
4809 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits;
4810 rtl_ephy_write(tp, e->offset, w);
4815 static void rtl_disable_clock_request(struct rtl8169_private *tp)
4817 pcie_capability_clear_word(tp->pci_dev, PCI_EXP_LNKCTL,
4818 PCI_EXP_LNKCTL_CLKREQ_EN);
4821 static void rtl_enable_clock_request(struct rtl8169_private *tp)
4823 pcie_capability_set_word(tp->pci_dev, PCI_EXP_LNKCTL,
4824 PCI_EXP_LNKCTL_CLKREQ_EN);
4827 static void rtl_pcie_state_l2l3_disable(struct rtl8169_private *tp)
4829 /* work around an issue when PCI reset occurs during L2/L3 state */
4830 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Rdy_to_L23);
4833 static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable)
4836 RTL_W8(tp, Config5, RTL_R8(tp, Config5) | ASPM_en);
4837 RTL_W8(tp, Config2, RTL_R8(tp, Config2) | ClkReqEn);
4839 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
4840 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
4846 static void rtl_hw_start_8168bb(struct rtl8169_private *tp)
4848 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4850 tp->cp_cmd &= CPCMD_QUIRK_MASK;
4851 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4853 if (tp->dev->mtu <= ETH_DATA_LEN) {
4854 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B |
4855 PCI_EXP_DEVCTL_NOSNOOP_EN);
4859 static void rtl_hw_start_8168bef(struct rtl8169_private *tp)
4861 rtl_hw_start_8168bb(tp);
4863 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4865 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0));
4868 static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)
4870 RTL_W8(tp, Config1, RTL_R8(tp, Config1) | Speed_down);
4872 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4874 if (tp->dev->mtu <= ETH_DATA_LEN)
4875 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4877 rtl_disable_clock_request(tp);
4879 tp->cp_cmd &= CPCMD_QUIRK_MASK;
4880 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4883 static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp)
4885 static const struct ephy_info e_info_8168cp[] = {
4886 { 0x01, 0, 0x0001 },
4887 { 0x02, 0x0800, 0x1000 },
4888 { 0x03, 0, 0x0042 },
4889 { 0x06, 0x0080, 0x0000 },
4893 rtl_set_def_aspm_entry_latency(tp);
4895 rtl_ephy_init(tp, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
4897 __rtl_hw_start_8168cp(tp);
4900 static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)
4902 rtl_set_def_aspm_entry_latency(tp);
4904 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4906 if (tp->dev->mtu <= ETH_DATA_LEN)
4907 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4909 tp->cp_cmd &= CPCMD_QUIRK_MASK;
4910 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4913 static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)
4915 rtl_set_def_aspm_entry_latency(tp);
4917 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4920 RTL_W8(tp, DBG_REG, 0x20);
4922 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4924 if (tp->dev->mtu <= ETH_DATA_LEN)
4925 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4927 tp->cp_cmd &= CPCMD_QUIRK_MASK;
4928 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4931 static void rtl_hw_start_8168c_1(struct rtl8169_private *tp)
4933 static const struct ephy_info e_info_8168c_1[] = {
4934 { 0x02, 0x0800, 0x1000 },
4935 { 0x03, 0, 0x0002 },
4936 { 0x06, 0x0080, 0x0000 }
4939 rtl_set_def_aspm_entry_latency(tp);
4941 RTL_W8(tp, DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
4943 rtl_ephy_init(tp, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
4945 __rtl_hw_start_8168cp(tp);
4948 static void rtl_hw_start_8168c_2(struct rtl8169_private *tp)
4950 static const struct ephy_info e_info_8168c_2[] = {
4951 { 0x01, 0, 0x0001 },
4952 { 0x03, 0x0400, 0x0220 }
4955 rtl_set_def_aspm_entry_latency(tp);
4957 rtl_ephy_init(tp, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
4959 __rtl_hw_start_8168cp(tp);
4962 static void rtl_hw_start_8168c_3(struct rtl8169_private *tp)
4964 rtl_hw_start_8168c_2(tp);
4967 static void rtl_hw_start_8168c_4(struct rtl8169_private *tp)
4969 rtl_set_def_aspm_entry_latency(tp);
4971 __rtl_hw_start_8168cp(tp);
4974 static void rtl_hw_start_8168d(struct rtl8169_private *tp)
4976 rtl_set_def_aspm_entry_latency(tp);
4978 rtl_disable_clock_request(tp);
4980 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4982 if (tp->dev->mtu <= ETH_DATA_LEN)
4983 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4985 tp->cp_cmd &= CPCMD_QUIRK_MASK;
4986 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4989 static void rtl_hw_start_8168dp(struct rtl8169_private *tp)
4991 rtl_set_def_aspm_entry_latency(tp);
4993 if (tp->dev->mtu <= ETH_DATA_LEN)
4994 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4996 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4998 rtl_disable_clock_request(tp);
5001 static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
5003 static const struct ephy_info e_info_8168d_4[] = {
5004 { 0x0b, 0x0000, 0x0048 },
5005 { 0x19, 0x0020, 0x0050 },
5006 { 0x0c, 0x0100, 0x0020 }
5009 rtl_set_def_aspm_entry_latency(tp);
5011 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5013 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
5015 rtl_ephy_init(tp, e_info_8168d_4, ARRAY_SIZE(e_info_8168d_4));
5017 rtl_enable_clock_request(tp);
5020 static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)
5022 static const struct ephy_info e_info_8168e_1[] = {
5023 { 0x00, 0x0200, 0x0100 },
5024 { 0x00, 0x0000, 0x0004 },
5025 { 0x06, 0x0002, 0x0001 },
5026 { 0x06, 0x0000, 0x0030 },
5027 { 0x07, 0x0000, 0x2000 },
5028 { 0x00, 0x0000, 0x0020 },
5029 { 0x03, 0x5800, 0x2000 },
5030 { 0x03, 0x0000, 0x0001 },
5031 { 0x01, 0x0800, 0x1000 },
5032 { 0x07, 0x0000, 0x4000 },
5033 { 0x1e, 0x0000, 0x2000 },
5034 { 0x19, 0xffff, 0xfe6c },
5035 { 0x0a, 0x0000, 0x0040 }
5038 rtl_set_def_aspm_entry_latency(tp);
5040 rtl_ephy_init(tp, e_info_8168e_1, ARRAY_SIZE(e_info_8168e_1));
5042 if (tp->dev->mtu <= ETH_DATA_LEN)
5043 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5045 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
5047 rtl_disable_clock_request(tp);
5049 /* Reset tx FIFO pointer */
5050 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | TXPLA_RST);
5051 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~TXPLA_RST);
5053 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
5056 static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
5058 static const struct ephy_info e_info_8168e_2[] = {
5059 { 0x09, 0x0000, 0x0080 },
5060 { 0x19, 0x0000, 0x0224 }
5063 rtl_set_def_aspm_entry_latency(tp);
5065 rtl_ephy_init(tp, e_info_8168e_2, ARRAY_SIZE(e_info_8168e_2));
5067 if (tp->dev->mtu <= ETH_DATA_LEN)
5068 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5070 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5071 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5072 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
5073 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5074 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
5075 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060, ERIAR_EXGMAC);
5076 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5077 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
5079 RTL_W8(tp, MaxTxPacketSize, EarlySize);
5081 rtl_disable_clock_request(tp);
5083 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
5085 /* Adjust EEE LED frequency */
5086 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
5088 rtl8168_config_eee_mac(tp);
5090 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
5091 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
5092 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
5094 rtl_hw_aspm_clkreq_enable(tp, true);
5097 static void rtl_hw_start_8168f(struct rtl8169_private *tp)
5099 rtl_set_def_aspm_entry_latency(tp);
5101 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5103 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5104 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5105 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
5106 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5107 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5108 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5109 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5110 rtl_w0w1_eri(tp, 0x1d0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5111 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
5112 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060, ERIAR_EXGMAC);
5114 RTL_W8(tp, MaxTxPacketSize, EarlySize);
5116 rtl_disable_clock_request(tp);
5118 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
5119 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
5120 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
5121 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
5123 rtl8168_config_eee_mac(tp);
5126 static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
5128 static const struct ephy_info e_info_8168f_1[] = {
5129 { 0x06, 0x00c0, 0x0020 },
5130 { 0x08, 0x0001, 0x0002 },
5131 { 0x09, 0x0000, 0x0080 },
5132 { 0x19, 0x0000, 0x0224 }
5135 rtl_hw_start_8168f(tp);
5137 rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
5139 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
5141 /* Adjust EEE LED frequency */
5142 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
5145 static void rtl_hw_start_8411(struct rtl8169_private *tp)
5147 static const struct ephy_info e_info_8168f_1[] = {
5148 { 0x06, 0x00c0, 0x0020 },
5149 { 0x0f, 0xffff, 0x5200 },
5150 { 0x1e, 0x0000, 0x4000 },
5151 { 0x19, 0x0000, 0x0224 }
5154 rtl_hw_start_8168f(tp);
5155 rtl_pcie_state_l2l3_disable(tp);
5157 rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
5159 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0x0000, ERIAR_EXGMAC);
5162 static void rtl_hw_start_8168g(struct rtl8169_private *tp)
5164 rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x080002, ERIAR_EXGMAC);
5165 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
5166 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
5167 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5169 rtl_set_def_aspm_entry_latency(tp);
5171 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5173 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5174 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5175 rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f, ERIAR_EXGMAC);
5177 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
5178 RTL_W8(tp, MaxTxPacketSize, EarlySize);
5180 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5181 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5183 /* Adjust EEE LED frequency */
5184 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
5186 rtl8168_config_eee_mac(tp);
5188 rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06, ERIAR_EXGMAC);
5189 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC);
5191 rtl_pcie_state_l2l3_disable(tp);
5194 static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
5196 static const struct ephy_info e_info_8168g_1[] = {
5197 { 0x00, 0x0000, 0x0008 },
5198 { 0x0c, 0x37d0, 0x0820 },
5199 { 0x1e, 0x0000, 0x0001 },
5200 { 0x19, 0x8000, 0x0000 }
5203 rtl_hw_start_8168g(tp);
5205 /* disable aspm and clock request before access ephy */
5206 rtl_hw_aspm_clkreq_enable(tp, false);
5207 rtl_ephy_init(tp, e_info_8168g_1, ARRAY_SIZE(e_info_8168g_1));
5208 rtl_hw_aspm_clkreq_enable(tp, true);
5211 static void rtl_hw_start_8168g_2(struct rtl8169_private *tp)
5213 static const struct ephy_info e_info_8168g_2[] = {
5214 { 0x00, 0x0000, 0x0008 },
5215 { 0x0c, 0x3df0, 0x0200 },
5216 { 0x19, 0xffff, 0xfc00 },
5217 { 0x1e, 0xffff, 0x20eb }
5220 rtl_hw_start_8168g(tp);
5222 /* disable aspm and clock request before access ephy */
5223 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
5224 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
5225 rtl_ephy_init(tp, e_info_8168g_2, ARRAY_SIZE(e_info_8168g_2));
5228 static void rtl_hw_start_8411_2(struct rtl8169_private *tp)
5230 static const struct ephy_info e_info_8411_2[] = {
5231 { 0x00, 0x0000, 0x0008 },
5232 { 0x0c, 0x3df0, 0x0200 },
5233 { 0x0f, 0xffff, 0x5200 },
5234 { 0x19, 0x0020, 0x0000 },
5235 { 0x1e, 0x0000, 0x2000 }
5238 rtl_hw_start_8168g(tp);
5240 /* disable aspm and clock request before access ephy */
5241 rtl_hw_aspm_clkreq_enable(tp, false);
5242 rtl_ephy_init(tp, e_info_8411_2, ARRAY_SIZE(e_info_8411_2));
5243 rtl_hw_aspm_clkreq_enable(tp, true);
5246 static void rtl_hw_start_8168h_1(struct rtl8169_private *tp)
5250 static const struct ephy_info e_info_8168h_1[] = {
5251 { 0x1e, 0x0800, 0x0001 },
5252 { 0x1d, 0x0000, 0x0800 },
5253 { 0x05, 0xffff, 0x2089 },
5254 { 0x06, 0xffff, 0x5881 },
5255 { 0x04, 0xffff, 0x154a },
5256 { 0x01, 0xffff, 0x068b }
5259 /* disable aspm and clock request before access ephy */
5260 rtl_hw_aspm_clkreq_enable(tp, false);
5261 rtl_ephy_init(tp, e_info_8168h_1, ARRAY_SIZE(e_info_8168h_1));
5263 rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x00080002, ERIAR_EXGMAC);
5264 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
5265 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
5266 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5268 rtl_set_def_aspm_entry_latency(tp);
5270 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5272 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5273 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5275 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_1111, 0x0010, 0x00, ERIAR_EXGMAC);
5277 rtl_w0w1_eri(tp, 0xd4, ERIAR_MASK_1111, 0x1f00, 0x00, ERIAR_EXGMAC);
5279 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87, ERIAR_EXGMAC);
5281 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
5282 RTL_W8(tp, MaxTxPacketSize, EarlySize);
5284 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5285 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5287 /* Adjust EEE LED frequency */
5288 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
5290 rtl8168_config_eee_mac(tp);
5292 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5293 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
5295 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
5297 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC);
5299 rtl_pcie_state_l2l3_disable(tp);
5301 rtl_writephy(tp, 0x1f, 0x0c42);
5302 rg_saw_cnt = (rtl_readphy(tp, 0x13) & 0x3fff);
5303 rtl_writephy(tp, 0x1f, 0x0000);
5304 if (rg_saw_cnt > 0) {
5307 sw_cnt_1ms_ini = 16000000/rg_saw_cnt;
5308 sw_cnt_1ms_ini &= 0x0fff;
5309 data = r8168_mac_ocp_read(tp, 0xd412);
5311 data |= sw_cnt_1ms_ini;
5312 r8168_mac_ocp_write(tp, 0xd412, data);
5315 data = r8168_mac_ocp_read(tp, 0xe056);
5318 r8168_mac_ocp_write(tp, 0xe056, data);
5320 data = r8168_mac_ocp_read(tp, 0xe052);
5323 r8168_mac_ocp_write(tp, 0xe052, data);
5325 data = r8168_mac_ocp_read(tp, 0xe0d6);
5328 r8168_mac_ocp_write(tp, 0xe0d6, data);
5330 data = r8168_mac_ocp_read(tp, 0xd420);
5333 r8168_mac_ocp_write(tp, 0xd420, data);
5335 r8168_mac_ocp_write(tp, 0xe63e, 0x0001);
5336 r8168_mac_ocp_write(tp, 0xe63e, 0x0000);
5337 r8168_mac_ocp_write(tp, 0xc094, 0x0000);
5338 r8168_mac_ocp_write(tp, 0xc09e, 0x0000);
5340 rtl_hw_aspm_clkreq_enable(tp, true);
5343 static void rtl_hw_start_8168ep(struct rtl8169_private *tp)
5345 rtl8168ep_stop_cmac(tp);
5347 rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x00080002, ERIAR_EXGMAC);
5348 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x2f, ERIAR_EXGMAC);
5349 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x5f, ERIAR_EXGMAC);
5350 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5352 rtl_set_def_aspm_entry_latency(tp);
5354 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5356 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5357 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5359 rtl_w0w1_eri(tp, 0xd4, ERIAR_MASK_1111, 0x1f80, 0x00, ERIAR_EXGMAC);
5361 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87, ERIAR_EXGMAC);
5363 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
5364 RTL_W8(tp, MaxTxPacketSize, EarlySize);
5366 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5367 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5369 /* Adjust EEE LED frequency */
5370 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
5372 rtl8168_config_eee_mac(tp);
5374 rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06, ERIAR_EXGMAC);
5376 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
5378 rtl_pcie_state_l2l3_disable(tp);
5381 static void rtl_hw_start_8168ep_1(struct rtl8169_private *tp)
5383 static const struct ephy_info e_info_8168ep_1[] = {
5384 { 0x00, 0xffff, 0x10ab },
5385 { 0x06, 0xffff, 0xf030 },
5386 { 0x08, 0xffff, 0x2006 },
5387 { 0x0d, 0xffff, 0x1666 },
5388 { 0x0c, 0x3ff0, 0x0000 }
5391 /* disable aspm and clock request before access ephy */
5392 rtl_hw_aspm_clkreq_enable(tp, false);
5393 rtl_ephy_init(tp, e_info_8168ep_1, ARRAY_SIZE(e_info_8168ep_1));
5395 rtl_hw_start_8168ep(tp);
5397 rtl_hw_aspm_clkreq_enable(tp, true);
5400 static void rtl_hw_start_8168ep_2(struct rtl8169_private *tp)
5402 static const struct ephy_info e_info_8168ep_2[] = {
5403 { 0x00, 0xffff, 0x10a3 },
5404 { 0x19, 0xffff, 0xfc00 },
5405 { 0x1e, 0xffff, 0x20ea }
5408 /* disable aspm and clock request before access ephy */
5409 rtl_hw_aspm_clkreq_enable(tp, false);
5410 rtl_ephy_init(tp, e_info_8168ep_2, ARRAY_SIZE(e_info_8168ep_2));
5412 rtl_hw_start_8168ep(tp);
5414 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5415 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
5417 rtl_hw_aspm_clkreq_enable(tp, true);
5420 static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp)
5423 static const struct ephy_info e_info_8168ep_3[] = {
5424 { 0x00, 0xffff, 0x10a3 },
5425 { 0x19, 0xffff, 0x7c00 },
5426 { 0x1e, 0xffff, 0x20eb },
5427 { 0x0d, 0xffff, 0x1666 }
5430 /* disable aspm and clock request before access ephy */
5431 rtl_hw_aspm_clkreq_enable(tp, false);
5432 rtl_ephy_init(tp, e_info_8168ep_3, ARRAY_SIZE(e_info_8168ep_3));
5434 rtl_hw_start_8168ep(tp);
5436 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5437 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
5439 data = r8168_mac_ocp_read(tp, 0xd3e2);
5442 r8168_mac_ocp_write(tp, 0xd3e2, data);
5444 data = r8168_mac_ocp_read(tp, 0xd3e4);
5446 r8168_mac_ocp_write(tp, 0xd3e4, data);
5448 data = r8168_mac_ocp_read(tp, 0xe860);
5450 r8168_mac_ocp_write(tp, 0xe860, data);
5452 rtl_hw_aspm_clkreq_enable(tp, true);
5455 static void rtl_hw_start_8168(struct rtl8169_private *tp)
5457 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
5459 tp->cp_cmd &= ~INTT_MASK;
5460 tp->cp_cmd |= PktCntrDisable | INTT_1;
5461 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
5463 RTL_W16(tp, IntrMitigate, 0x5151);
5465 /* Work around for RxFIFO overflow. */
5466 if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
5467 tp->irq_mask |= RxFIFOOver;
5468 tp->irq_mask &= ~RxOverflow;
5471 switch (tp->mac_version) {
5472 case RTL_GIGA_MAC_VER_11:
5473 rtl_hw_start_8168bb(tp);
5476 case RTL_GIGA_MAC_VER_12:
5477 case RTL_GIGA_MAC_VER_17:
5478 rtl_hw_start_8168bef(tp);
5481 case RTL_GIGA_MAC_VER_18:
5482 rtl_hw_start_8168cp_1(tp);
5485 case RTL_GIGA_MAC_VER_19:
5486 rtl_hw_start_8168c_1(tp);
5489 case RTL_GIGA_MAC_VER_20:
5490 rtl_hw_start_8168c_2(tp);
5493 case RTL_GIGA_MAC_VER_21:
5494 rtl_hw_start_8168c_3(tp);
5497 case RTL_GIGA_MAC_VER_22:
5498 rtl_hw_start_8168c_4(tp);
5501 case RTL_GIGA_MAC_VER_23:
5502 rtl_hw_start_8168cp_2(tp);
5505 case RTL_GIGA_MAC_VER_24:
5506 rtl_hw_start_8168cp_3(tp);
5509 case RTL_GIGA_MAC_VER_25:
5510 case RTL_GIGA_MAC_VER_26:
5511 case RTL_GIGA_MAC_VER_27:
5512 rtl_hw_start_8168d(tp);
5515 case RTL_GIGA_MAC_VER_28:
5516 rtl_hw_start_8168d_4(tp);
5519 case RTL_GIGA_MAC_VER_31:
5520 rtl_hw_start_8168dp(tp);
5523 case RTL_GIGA_MAC_VER_32:
5524 case RTL_GIGA_MAC_VER_33:
5525 rtl_hw_start_8168e_1(tp);
5527 case RTL_GIGA_MAC_VER_34:
5528 rtl_hw_start_8168e_2(tp);
5531 case RTL_GIGA_MAC_VER_35:
5532 case RTL_GIGA_MAC_VER_36:
5533 rtl_hw_start_8168f_1(tp);
5536 case RTL_GIGA_MAC_VER_38:
5537 rtl_hw_start_8411(tp);
5540 case RTL_GIGA_MAC_VER_40:
5541 case RTL_GIGA_MAC_VER_41:
5542 rtl_hw_start_8168g_1(tp);
5544 case RTL_GIGA_MAC_VER_42:
5545 rtl_hw_start_8168g_2(tp);
5548 case RTL_GIGA_MAC_VER_44:
5549 rtl_hw_start_8411_2(tp);
5552 case RTL_GIGA_MAC_VER_45:
5553 case RTL_GIGA_MAC_VER_46:
5554 rtl_hw_start_8168h_1(tp);
5557 case RTL_GIGA_MAC_VER_49:
5558 rtl_hw_start_8168ep_1(tp);
5561 case RTL_GIGA_MAC_VER_50:
5562 rtl_hw_start_8168ep_2(tp);
5565 case RTL_GIGA_MAC_VER_51:
5566 rtl_hw_start_8168ep_3(tp);
5570 netif_err(tp, drv, tp->dev,
5571 "unknown chipset (mac_version = %d)\n",
5577 static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)
5579 static const struct ephy_info e_info_8102e_1[] = {
5580 { 0x01, 0, 0x6e65 },
5581 { 0x02, 0, 0x091f },
5582 { 0x03, 0, 0xc2f9 },
5583 { 0x06, 0, 0xafb5 },
5584 { 0x07, 0, 0x0e00 },
5585 { 0x19, 0, 0xec80 },
5586 { 0x01, 0, 0x2e65 },
5591 rtl_set_def_aspm_entry_latency(tp);
5593 RTL_W8(tp, DBG_REG, FIX_NAK_1);
5595 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5598 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
5599 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
5601 cfg1 = RTL_R8(tp, Config1);
5602 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
5603 RTL_W8(tp, Config1, cfg1 & ~LEDS0);
5605 rtl_ephy_init(tp, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
5608 static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)
5610 rtl_set_def_aspm_entry_latency(tp);
5612 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5614 RTL_W8(tp, Config1, MEMMAP | IOMAP | VPD | PMEnable);
5615 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
5618 static void rtl_hw_start_8102e_3(struct rtl8169_private *tp)
5620 rtl_hw_start_8102e_2(tp);
5622 rtl_ephy_write(tp, 0x03, 0xc2f9);
5625 static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)
5627 static const struct ephy_info e_info_8105e_1[] = {
5628 { 0x07, 0, 0x4000 },
5629 { 0x19, 0, 0x0200 },
5630 { 0x19, 0, 0x0020 },
5631 { 0x1e, 0, 0x2000 },
5632 { 0x03, 0, 0x0001 },
5633 { 0x19, 0, 0x0100 },
5634 { 0x19, 0, 0x0004 },
5638 /* Force LAN exit from ASPM if Rx/Tx are not idle */
5639 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
5641 /* Disable Early Tally Counter */
5642 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) & ~0x010000);
5644 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
5645 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
5647 rtl_ephy_init(tp, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
5649 rtl_pcie_state_l2l3_disable(tp);
5652 static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)
5654 rtl_hw_start_8105e_1(tp);
5655 rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000);
5658 static void rtl_hw_start_8402(struct rtl8169_private *tp)
5660 static const struct ephy_info e_info_8402[] = {
5661 { 0x19, 0xffff, 0xff64 },
5665 rtl_set_def_aspm_entry_latency(tp);
5667 /* Force LAN exit from ASPM if Rx/Tx are not idle */
5668 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
5670 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
5672 rtl_ephy_init(tp, e_info_8402, ARRAY_SIZE(e_info_8402));
5674 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5676 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00000002, ERIAR_EXGMAC);
5677 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00000006, ERIAR_EXGMAC);
5678 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5679 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5680 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5681 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5682 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0e00, 0xff00, ERIAR_EXGMAC);
5684 rtl_pcie_state_l2l3_disable(tp);
5687 static void rtl_hw_start_8106(struct rtl8169_private *tp)
5689 rtl_hw_aspm_clkreq_enable(tp, false);
5691 /* Force LAN exit from ASPM if Rx/Tx are not idle */
5692 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
5694 RTL_W32(tp, MISC, (RTL_R32(tp, MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);
5695 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
5696 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5698 rtl_pcie_state_l2l3_disable(tp);
5699 rtl_hw_aspm_clkreq_enable(tp, true);
5702 static void rtl_hw_start_8101(struct rtl8169_private *tp)
5704 if (tp->mac_version >= RTL_GIGA_MAC_VER_30)
5705 tp->irq_mask &= ~RxFIFOOver;
5707 if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
5708 tp->mac_version == RTL_GIGA_MAC_VER_16)
5709 pcie_capability_set_word(tp->pci_dev, PCI_EXP_DEVCTL,
5710 PCI_EXP_DEVCTL_NOSNOOP_EN);
5712 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
5714 tp->cp_cmd &= CPCMD_QUIRK_MASK;
5715 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
5717 switch (tp->mac_version) {
5718 case RTL_GIGA_MAC_VER_07:
5719 rtl_hw_start_8102e_1(tp);
5722 case RTL_GIGA_MAC_VER_08:
5723 rtl_hw_start_8102e_3(tp);
5726 case RTL_GIGA_MAC_VER_09:
5727 rtl_hw_start_8102e_2(tp);
5730 case RTL_GIGA_MAC_VER_29:
5731 rtl_hw_start_8105e_1(tp);
5733 case RTL_GIGA_MAC_VER_30:
5734 rtl_hw_start_8105e_2(tp);
5737 case RTL_GIGA_MAC_VER_37:
5738 rtl_hw_start_8402(tp);
5741 case RTL_GIGA_MAC_VER_39:
5742 rtl_hw_start_8106(tp);
5744 case RTL_GIGA_MAC_VER_43:
5745 rtl_hw_start_8168g_2(tp);
5747 case RTL_GIGA_MAC_VER_47:
5748 case RTL_GIGA_MAC_VER_48:
5749 rtl_hw_start_8168h_1(tp);
5753 RTL_W16(tp, IntrMitigate, 0x0000);
5756 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
5758 struct rtl8169_private *tp = netdev_priv(dev);
5760 if (new_mtu > ETH_DATA_LEN)
5761 rtl_hw_jumbo_enable(tp);
5763 rtl_hw_jumbo_disable(tp);
5766 netdev_update_features(dev);
5771 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
5773 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
5774 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
5777 static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
5778 void **data_buff, struct RxDesc *desc)
5780 dma_unmap_single(tp_to_dev(tp), le64_to_cpu(desc->addr),
5781 R8169_RX_BUF_SIZE, DMA_FROM_DEVICE);
5785 rtl8169_make_unusable_by_asic(desc);
5788 static inline void rtl8169_mark_to_asic(struct RxDesc *desc)
5790 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
5792 /* Force memory writes to complete before releasing descriptor */
5795 desc->opts1 = cpu_to_le32(DescOwn | eor | R8169_RX_BUF_SIZE);
5798 static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
5799 struct RxDesc *desc)
5803 struct device *d = tp_to_dev(tp);
5804 int node = dev_to_node(d);
5806 data = kmalloc_node(R8169_RX_BUF_SIZE, GFP_KERNEL, node);
5810 /* Memory should be properly aligned, but better check. */
5811 if (!IS_ALIGNED((unsigned long)data, 8)) {
5812 netdev_err_once(tp->dev, "RX buffer not 8-byte-aligned\n");
5816 mapping = dma_map_single(d, data, R8169_RX_BUF_SIZE, DMA_FROM_DEVICE);
5817 if (unlikely(dma_mapping_error(d, mapping))) {
5818 if (net_ratelimit())
5819 netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
5823 desc->addr = cpu_to_le64(mapping);
5824 rtl8169_mark_to_asic(desc);
5832 static void rtl8169_rx_clear(struct rtl8169_private *tp)
5836 for (i = 0; i < NUM_RX_DESC; i++) {
5837 if (tp->Rx_databuff[i]) {
5838 rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
5839 tp->RxDescArray + i);
5844 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
5846 desc->opts1 |= cpu_to_le32(RingEnd);
5849 static int rtl8169_rx_fill(struct rtl8169_private *tp)
5853 for (i = 0; i < NUM_RX_DESC; i++) {
5856 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
5858 rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
5861 tp->Rx_databuff[i] = data;
5864 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
5868 rtl8169_rx_clear(tp);
5872 static int rtl8169_init_ring(struct rtl8169_private *tp)
5874 rtl8169_init_ring_indexes(tp);
5876 memset(tp->tx_skb, 0, sizeof(tp->tx_skb));
5877 memset(tp->Rx_databuff, 0, sizeof(tp->Rx_databuff));
5879 return rtl8169_rx_fill(tp);
5882 static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
5883 struct TxDesc *desc)
5885 unsigned int len = tx_skb->len;
5887 dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
5895 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
5900 for (i = 0; i < n; i++) {
5901 unsigned int entry = (start + i) % NUM_TX_DESC;
5902 struct ring_info *tx_skb = tp->tx_skb + entry;
5903 unsigned int len = tx_skb->len;
5906 struct sk_buff *skb = tx_skb->skb;
5908 rtl8169_unmap_tx_skb(tp_to_dev(tp), tx_skb,
5909 tp->TxDescArray + entry);
5911 dev_consume_skb_any(skb);
5918 static void rtl8169_tx_clear(struct rtl8169_private *tp)
5920 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
5921 tp->cur_tx = tp->dirty_tx = 0;
5922 netdev_reset_queue(tp->dev);
5925 static void rtl_reset_work(struct rtl8169_private *tp)
5927 struct net_device *dev = tp->dev;
5930 napi_disable(&tp->napi);
5931 netif_stop_queue(dev);
5934 rtl8169_hw_reset(tp);
5936 for (i = 0; i < NUM_RX_DESC; i++)
5937 rtl8169_mark_to_asic(tp->RxDescArray + i);
5939 rtl8169_tx_clear(tp);
5940 rtl8169_init_ring_indexes(tp);
5942 napi_enable(&tp->napi);
5944 netif_wake_queue(dev);
5947 static void rtl8169_tx_timeout(struct net_device *dev)
5949 struct rtl8169_private *tp = netdev_priv(dev);
5951 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
5954 static __le32 rtl8169_get_txd_opts1(u32 opts0, u32 len, unsigned int entry)
5956 u32 status = opts0 | len;
5958 if (entry == NUM_TX_DESC - 1)
5961 return cpu_to_le32(status);
5964 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
5967 struct skb_shared_info *info = skb_shinfo(skb);
5968 unsigned int cur_frag, entry;
5969 struct TxDesc *uninitialized_var(txd);
5970 struct device *d = tp_to_dev(tp);
5973 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
5974 const skb_frag_t *frag = info->frags + cur_frag;
5979 entry = (entry + 1) % NUM_TX_DESC;
5981 txd = tp->TxDescArray + entry;
5982 len = skb_frag_size(frag);
5983 addr = skb_frag_address(frag);
5984 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
5985 if (unlikely(dma_mapping_error(d, mapping))) {
5986 if (net_ratelimit())
5987 netif_err(tp, drv, tp->dev,
5988 "Failed to map TX fragments DMA!\n");
5992 txd->opts1 = rtl8169_get_txd_opts1(opts[0], len, entry);
5993 txd->opts2 = cpu_to_le32(opts[1]);
5994 txd->addr = cpu_to_le64(mapping);
5996 tp->tx_skb[entry].len = len;
6000 tp->tx_skb[entry].skb = skb;
6001 txd->opts1 |= cpu_to_le32(LastFrag);
6007 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
6011 static bool rtl_test_hw_pad_bug(struct rtl8169_private *tp, struct sk_buff *skb)
6013 return skb->len < ETH_ZLEN && tp->mac_version == RTL_GIGA_MAC_VER_34;
6016 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
6017 struct net_device *dev);
6018 /* r8169_csum_workaround()
6019 * The hw limites the value the transport offset. When the offset is out of the
6020 * range, calculate the checksum by sw.
6022 static void r8169_csum_workaround(struct rtl8169_private *tp,
6023 struct sk_buff *skb)
6025 if (skb_shinfo(skb)->gso_size) {
6026 netdev_features_t features = tp->dev->features;
6027 struct sk_buff *segs, *nskb;
6029 features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
6030 segs = skb_gso_segment(skb, features);
6031 if (IS_ERR(segs) || !segs)
6038 rtl8169_start_xmit(nskb, tp->dev);
6041 dev_consume_skb_any(skb);
6042 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
6043 if (skb_checksum_help(skb) < 0)
6046 rtl8169_start_xmit(skb, tp->dev);
6048 struct net_device_stats *stats;
6051 stats = &tp->dev->stats;
6052 stats->tx_dropped++;
6053 dev_kfree_skb_any(skb);
6057 /* msdn_giant_send_check()
6058 * According to the document of microsoft, the TCP Pseudo Header excludes the
6059 * packet length for IPv6 TCP large packets.
6061 static int msdn_giant_send_check(struct sk_buff *skb)
6063 const struct ipv6hdr *ipv6h;
6067 ret = skb_cow_head(skb, 0);
6071 ipv6h = ipv6_hdr(skb);
6075 th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0);
6080 static bool rtl8169_tso_csum_v1(struct rtl8169_private *tp,
6081 struct sk_buff *skb, u32 *opts)
6083 u32 mss = skb_shinfo(skb)->gso_size;
6087 opts[0] |= min(mss, TD_MSS_MAX) << TD0_MSS_SHIFT;
6088 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
6089 const struct iphdr *ip = ip_hdr(skb);
6091 if (ip->protocol == IPPROTO_TCP)
6092 opts[0] |= TD0_IP_CS | TD0_TCP_CS;
6093 else if (ip->protocol == IPPROTO_UDP)
6094 opts[0] |= TD0_IP_CS | TD0_UDP_CS;
6102 static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp,
6103 struct sk_buff *skb, u32 *opts)
6105 u32 transport_offset = (u32)skb_transport_offset(skb);
6106 u32 mss = skb_shinfo(skb)->gso_size;
6109 if (transport_offset > GTTCPHO_MAX) {
6110 netif_warn(tp, tx_err, tp->dev,
6111 "Invalid transport offset 0x%x for TSO\n",
6116 switch (vlan_get_protocol(skb)) {
6117 case htons(ETH_P_IP):
6118 opts[0] |= TD1_GTSENV4;
6121 case htons(ETH_P_IPV6):
6122 if (msdn_giant_send_check(skb))
6125 opts[0] |= TD1_GTSENV6;
6133 opts[0] |= transport_offset << GTTCPHO_SHIFT;
6134 opts[1] |= min(mss, TD_MSS_MAX) << TD1_MSS_SHIFT;
6135 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
6138 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
6139 return !(skb_checksum_help(skb) || eth_skb_pad(skb));
6141 if (transport_offset > TCPHO_MAX) {
6142 netif_warn(tp, tx_err, tp->dev,
6143 "Invalid transport offset 0x%x\n",
6148 switch (vlan_get_protocol(skb)) {
6149 case htons(ETH_P_IP):
6150 opts[1] |= TD1_IPv4_CS;
6151 ip_protocol = ip_hdr(skb)->protocol;
6154 case htons(ETH_P_IPV6):
6155 opts[1] |= TD1_IPv6_CS;
6156 ip_protocol = ipv6_hdr(skb)->nexthdr;
6160 ip_protocol = IPPROTO_RAW;
6164 if (ip_protocol == IPPROTO_TCP)
6165 opts[1] |= TD1_TCP_CS;
6166 else if (ip_protocol == IPPROTO_UDP)
6167 opts[1] |= TD1_UDP_CS;
6171 opts[1] |= transport_offset << TCPHO_SHIFT;
6173 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
6174 return !eth_skb_pad(skb);
6180 static bool rtl_tx_slots_avail(struct rtl8169_private *tp,
6181 unsigned int nr_frags)
6183 unsigned int slots_avail = tp->dirty_tx + NUM_TX_DESC - tp->cur_tx;
6185 /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
6186 return slots_avail > nr_frags;
6189 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
6190 struct net_device *dev)
6192 struct rtl8169_private *tp = netdev_priv(dev);
6193 unsigned int entry = tp->cur_tx % NUM_TX_DESC;
6194 struct TxDesc *txd = tp->TxDescArray + entry;
6195 struct device *d = tp_to_dev(tp);
6200 if (unlikely(!rtl_tx_slots_avail(tp, skb_shinfo(skb)->nr_frags))) {
6201 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
6205 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
6208 opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(skb));
6211 if (!tp->tso_csum(tp, skb, opts)) {
6212 r8169_csum_workaround(tp, skb);
6213 return NETDEV_TX_OK;
6216 len = skb_headlen(skb);
6217 mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
6218 if (unlikely(dma_mapping_error(d, mapping))) {
6219 if (net_ratelimit())
6220 netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
6224 tp->tx_skb[entry].len = len;
6225 txd->addr = cpu_to_le64(mapping);
6227 frags = rtl8169_xmit_frags(tp, skb, opts);
6231 opts[0] |= FirstFrag;
6233 opts[0] |= FirstFrag | LastFrag;
6234 tp->tx_skb[entry].skb = skb;
6237 txd->opts2 = cpu_to_le32(opts[1]);
6239 netdev_sent_queue(dev, skb->len);
6241 skb_tx_timestamp(skb);
6243 /* Force memory writes to complete before releasing descriptor */
6246 txd->opts1 = rtl8169_get_txd_opts1(opts[0], len, entry);
6248 /* Force all memory writes to complete before notifying device */
6251 tp->cur_tx += frags + 1;
6253 RTL_W8(tp, TxPoll, NPQ);
6255 if (!rtl_tx_slots_avail(tp, MAX_SKB_FRAGS)) {
6256 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
6257 * not miss a ring update when it notices a stopped queue.
6260 netif_stop_queue(dev);
6261 /* Sync with rtl_tx:
6262 * - publish queue status and cur_tx ring index (write barrier)
6263 * - refresh dirty_tx ring index (read barrier).
6264 * May the current thread have a pessimistic view of the ring
6265 * status and forget to wake up queue, a racing rtl_tx thread
6269 if (rtl_tx_slots_avail(tp, MAX_SKB_FRAGS))
6270 netif_wake_queue(dev);
6273 return NETDEV_TX_OK;
6276 rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
6278 dev_kfree_skb_any(skb);
6279 dev->stats.tx_dropped++;
6280 return NETDEV_TX_OK;
6283 netif_stop_queue(dev);
6284 dev->stats.tx_dropped++;
6285 return NETDEV_TX_BUSY;
6288 static void rtl8169_pcierr_interrupt(struct net_device *dev)
6290 struct rtl8169_private *tp = netdev_priv(dev);
6291 struct pci_dev *pdev = tp->pci_dev;
6292 u16 pci_status, pci_cmd;
6294 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
6295 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
6297 netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
6298 pci_cmd, pci_status);
6301 * The recovery sequence below admits a very elaborated explanation:
6302 * - it seems to work;
6303 * - I did not see what else could be done;
6304 * - it makes iop3xx happy.
6306 * Feel free to adjust to your needs.
6308 if (pdev->broken_parity_status)
6309 pci_cmd &= ~PCI_COMMAND_PARITY;
6311 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
6313 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
6315 pci_write_config_word(pdev, PCI_STATUS,
6316 pci_status & (PCI_STATUS_DETECTED_PARITY |
6317 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
6318 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
6320 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
6323 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp,
6326 unsigned int dirty_tx, tx_left, bytes_compl = 0, pkts_compl = 0;
6328 dirty_tx = tp->dirty_tx;
6330 tx_left = tp->cur_tx - dirty_tx;
6332 while (tx_left > 0) {
6333 unsigned int entry = dirty_tx % NUM_TX_DESC;
6334 struct ring_info *tx_skb = tp->tx_skb + entry;
6337 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
6338 if (status & DescOwn)
6341 /* This barrier is needed to keep us from reading
6342 * any other fields out of the Tx descriptor until
6343 * we know the status of DescOwn
6347 rtl8169_unmap_tx_skb(tp_to_dev(tp), tx_skb,
6348 tp->TxDescArray + entry);
6349 if (status & LastFrag) {
6351 bytes_compl += tx_skb->skb->len;
6352 napi_consume_skb(tx_skb->skb, budget);
6359 if (tp->dirty_tx != dirty_tx) {
6360 netdev_completed_queue(dev, pkts_compl, bytes_compl);
6362 u64_stats_update_begin(&tp->tx_stats.syncp);
6363 tp->tx_stats.packets += pkts_compl;
6364 tp->tx_stats.bytes += bytes_compl;
6365 u64_stats_update_end(&tp->tx_stats.syncp);
6367 tp->dirty_tx = dirty_tx;
6368 /* Sync with rtl8169_start_xmit:
6369 * - publish dirty_tx ring index (write barrier)
6370 * - refresh cur_tx ring index and queue status (read barrier)
6371 * May the current thread miss the stopped queue condition,
6372 * a racing xmit thread can only have a right view of the
6376 if (netif_queue_stopped(dev) &&
6377 rtl_tx_slots_avail(tp, MAX_SKB_FRAGS)) {
6378 netif_wake_queue(dev);
6381 * 8168 hack: TxPoll requests are lost when the Tx packets are
6382 * too close. Let's kick an extra TxPoll request when a burst
6383 * of start_xmit activity is detected (if it is not detected,
6384 * it is slow enough). -- FR
6386 if (tp->cur_tx != dirty_tx)
6387 RTL_W8(tp, TxPoll, NPQ);
6391 static inline int rtl8169_fragmented_frame(u32 status)
6393 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
6396 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
6398 u32 status = opts1 & RxProtoMask;
6400 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
6401 ((status == RxProtoUDP) && !(opts1 & UDPFail)))
6402 skb->ip_summed = CHECKSUM_UNNECESSARY;
6404 skb_checksum_none_assert(skb);
6407 static struct sk_buff *rtl8169_try_rx_copy(void *data,
6408 struct rtl8169_private *tp,
6412 struct sk_buff *skb;
6413 struct device *d = tp_to_dev(tp);
6415 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
6417 skb = napi_alloc_skb(&tp->napi, pkt_size);
6419 skb_copy_to_linear_data(skb, data, pkt_size);
6420 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
6425 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget)
6427 unsigned int cur_rx, rx_left;
6430 cur_rx = tp->cur_rx;
6432 for (rx_left = min(budget, NUM_RX_DESC); rx_left > 0; rx_left--, cur_rx++) {
6433 unsigned int entry = cur_rx % NUM_RX_DESC;
6434 struct RxDesc *desc = tp->RxDescArray + entry;
6437 status = le32_to_cpu(desc->opts1);
6438 if (status & DescOwn)
6441 /* This barrier is needed to keep us from reading
6442 * any other fields out of the Rx descriptor until
6443 * we know the status of DescOwn
6447 if (unlikely(status & RxRES)) {
6448 netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
6450 dev->stats.rx_errors++;
6451 if (status & (RxRWT | RxRUNT))
6452 dev->stats.rx_length_errors++;
6454 dev->stats.rx_crc_errors++;
6455 /* RxFOVF is a reserved bit on later chip versions */
6456 if (tp->mac_version == RTL_GIGA_MAC_VER_01 &&
6458 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
6459 dev->stats.rx_fifo_errors++;
6460 } else if (status & (RxRUNT | RxCRC) &&
6461 !(status & RxRWT) &&
6462 dev->features & NETIF_F_RXALL) {
6466 struct sk_buff *skb;
6471 addr = le64_to_cpu(desc->addr);
6472 if (likely(!(dev->features & NETIF_F_RXFCS)))
6473 pkt_size = (status & 0x00003fff) - 4;
6475 pkt_size = status & 0x00003fff;
6478 * The driver does not support incoming fragmented
6479 * frames. They are seen as a symptom of over-mtu
6482 if (unlikely(rtl8169_fragmented_frame(status))) {
6483 dev->stats.rx_dropped++;
6484 dev->stats.rx_length_errors++;
6485 goto release_descriptor;
6488 skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
6489 tp, pkt_size, addr);
6491 dev->stats.rx_dropped++;
6492 goto release_descriptor;
6495 rtl8169_rx_csum(skb, status);
6496 skb_put(skb, pkt_size);
6497 skb->protocol = eth_type_trans(skb, dev);
6499 rtl8169_rx_vlan_tag(desc, skb);
6501 if (skb->pkt_type == PACKET_MULTICAST)
6502 dev->stats.multicast++;
6504 napi_gro_receive(&tp->napi, skb);
6506 u64_stats_update_begin(&tp->rx_stats.syncp);
6507 tp->rx_stats.packets++;
6508 tp->rx_stats.bytes += pkt_size;
6509 u64_stats_update_end(&tp->rx_stats.syncp);
6513 rtl8169_mark_to_asic(desc);
6516 count = cur_rx - tp->cur_rx;
6517 tp->cur_rx = cur_rx;
6522 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
6524 struct rtl8169_private *tp = dev_instance;
6525 u16 status = RTL_R16(tp, IntrStatus);
6527 if (!tp->irq_enabled || status == 0xffff || !(status & tp->irq_mask))
6530 if (unlikely(status & SYSErr)) {
6531 rtl8169_pcierr_interrupt(tp->dev);
6535 if (status & LinkChg)
6536 phy_mac_interrupt(tp->phydev);
6538 if (unlikely(status & RxFIFOOver &&
6539 tp->mac_version == RTL_GIGA_MAC_VER_11)) {
6540 netif_stop_queue(tp->dev);
6541 /* XXX - Hack alert. See rtl_task(). */
6542 set_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags);
6545 if (status & (RTL_EVENT_NAPI | LinkChg)) {
6546 rtl_irq_disable(tp);
6547 napi_schedule_irqoff(&tp->napi);
6550 rtl_ack_events(tp, status);
6555 static void rtl_task(struct work_struct *work)
6557 static const struct {
6559 void (*action)(struct rtl8169_private *);
6561 { RTL_FLAG_TASK_RESET_PENDING, rtl_reset_work },
6563 struct rtl8169_private *tp =
6564 container_of(work, struct rtl8169_private, wk.work);
6565 struct net_device *dev = tp->dev;
6570 if (!netif_running(dev) ||
6571 !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
6574 for (i = 0; i < ARRAY_SIZE(rtl_work); i++) {
6577 pending = test_and_clear_bit(rtl_work[i].bitnr, tp->wk.flags);
6579 rtl_work[i].action(tp);
6583 rtl_unlock_work(tp);
6586 static int rtl8169_poll(struct napi_struct *napi, int budget)
6588 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
6589 struct net_device *dev = tp->dev;
6592 work_done = rtl_rx(dev, tp, (u32) budget);
6594 rtl_tx(dev, tp, budget);
6596 if (work_done < budget) {
6597 napi_complete_done(napi, work_done);
6604 static void rtl8169_rx_missed(struct net_device *dev)
6606 struct rtl8169_private *tp = netdev_priv(dev);
6608 if (tp->mac_version > RTL_GIGA_MAC_VER_06)
6611 dev->stats.rx_missed_errors += RTL_R32(tp, RxMissed) & 0xffffff;
6612 RTL_W32(tp, RxMissed, 0);
6615 static void r8169_phylink_handler(struct net_device *ndev)
6617 struct rtl8169_private *tp = netdev_priv(ndev);
6619 if (netif_carrier_ok(ndev)) {
6620 rtl_link_chg_patch(tp);
6621 pm_request_resume(&tp->pci_dev->dev);
6623 pm_runtime_idle(&tp->pci_dev->dev);
6626 if (net_ratelimit())
6627 phy_print_status(tp->phydev);
6630 static int r8169_phy_connect(struct rtl8169_private *tp)
6632 struct phy_device *phydev = tp->phydev;
6633 phy_interface_t phy_mode;
6636 phy_mode = tp->supports_gmii ? PHY_INTERFACE_MODE_GMII :
6637 PHY_INTERFACE_MODE_MII;
6639 ret = phy_connect_direct(tp->dev, phydev, r8169_phylink_handler,
6644 if (!tp->supports_gmii)
6645 phy_set_max_speed(phydev, SPEED_100);
6647 /* Ensure to advertise everything, incl. pause */
6648 linkmode_copy(phydev->advertising, phydev->supported);
6650 phy_attached_info(phydev);
6655 static void rtl8169_down(struct net_device *dev)
6657 struct rtl8169_private *tp = netdev_priv(dev);
6659 phy_stop(tp->phydev);
6661 napi_disable(&tp->napi);
6662 netif_stop_queue(dev);
6664 rtl8169_hw_reset(tp);
6666 * At this point device interrupts can not be enabled in any function,
6667 * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task)
6668 * and napi is disabled (rtl8169_poll).
6670 rtl8169_rx_missed(dev);
6672 /* Give a racing hard_start_xmit a few cycles to complete. */
6675 rtl8169_tx_clear(tp);
6677 rtl8169_rx_clear(tp);
6679 rtl_pll_power_down(tp);
6682 static int rtl8169_close(struct net_device *dev)
6684 struct rtl8169_private *tp = netdev_priv(dev);
6685 struct pci_dev *pdev = tp->pci_dev;
6687 pm_runtime_get_sync(&pdev->dev);
6689 /* Update counters before going down */
6690 rtl8169_update_counters(tp);
6693 /* Clear all task flags */
6694 bitmap_zero(tp->wk.flags, RTL_FLAG_MAX);
6697 rtl_unlock_work(tp);
6699 cancel_work_sync(&tp->wk.work);
6701 phy_disconnect(tp->phydev);
6703 pci_free_irq(pdev, 0, tp);
6705 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6707 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6709 tp->TxDescArray = NULL;
6710 tp->RxDescArray = NULL;
6712 pm_runtime_put_sync(&pdev->dev);
6717 #ifdef CONFIG_NET_POLL_CONTROLLER
6718 static void rtl8169_netpoll(struct net_device *dev)
6720 struct rtl8169_private *tp = netdev_priv(dev);
6722 rtl8169_interrupt(pci_irq_vector(tp->pci_dev, 0), tp);
6726 static int rtl_open(struct net_device *dev)
6728 struct rtl8169_private *tp = netdev_priv(dev);
6729 struct pci_dev *pdev = tp->pci_dev;
6730 int retval = -ENOMEM;
6732 pm_runtime_get_sync(&pdev->dev);
6735 * Rx and Tx descriptors needs 256 bytes alignment.
6736 * dma_alloc_coherent provides more.
6738 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
6739 &tp->TxPhyAddr, GFP_KERNEL);
6740 if (!tp->TxDescArray)
6741 goto err_pm_runtime_put;
6743 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
6744 &tp->RxPhyAddr, GFP_KERNEL);
6745 if (!tp->RxDescArray)
6748 retval = rtl8169_init_ring(tp);
6752 rtl_request_firmware(tp);
6754 retval = pci_request_irq(pdev, 0, rtl8169_interrupt, NULL, tp,
6757 goto err_release_fw_2;
6759 retval = r8169_phy_connect(tp);
6765 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6767 napi_enable(&tp->napi);
6769 rtl8169_init_phy(dev, tp);
6771 rtl_pll_power_up(tp);
6775 if (!rtl8169_init_counter_offsets(tp))
6776 netif_warn(tp, hw, dev, "counter reset/update failed\n");
6778 phy_start(tp->phydev);
6779 netif_start_queue(dev);
6781 rtl_unlock_work(tp);
6783 pm_runtime_put_sync(&pdev->dev);
6788 pci_free_irq(pdev, 0, tp);
6790 rtl_release_firmware(tp);
6791 rtl8169_rx_clear(tp);
6793 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6795 tp->RxDescArray = NULL;
6797 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6799 tp->TxDescArray = NULL;
6801 pm_runtime_put_noidle(&pdev->dev);
6806 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
6808 struct rtl8169_private *tp = netdev_priv(dev);
6809 struct pci_dev *pdev = tp->pci_dev;
6810 struct rtl8169_counters *counters = tp->counters;
6813 pm_runtime_get_noresume(&pdev->dev);
6815 if (netif_running(dev) && pm_runtime_active(&pdev->dev))
6816 rtl8169_rx_missed(dev);
6819 start = u64_stats_fetch_begin_irq(&tp->rx_stats.syncp);
6820 stats->rx_packets = tp->rx_stats.packets;
6821 stats->rx_bytes = tp->rx_stats.bytes;
6822 } while (u64_stats_fetch_retry_irq(&tp->rx_stats.syncp, start));
6825 start = u64_stats_fetch_begin_irq(&tp->tx_stats.syncp);
6826 stats->tx_packets = tp->tx_stats.packets;
6827 stats->tx_bytes = tp->tx_stats.bytes;
6828 } while (u64_stats_fetch_retry_irq(&tp->tx_stats.syncp, start));
6830 stats->rx_dropped = dev->stats.rx_dropped;
6831 stats->tx_dropped = dev->stats.tx_dropped;
6832 stats->rx_length_errors = dev->stats.rx_length_errors;
6833 stats->rx_errors = dev->stats.rx_errors;
6834 stats->rx_crc_errors = dev->stats.rx_crc_errors;
6835 stats->rx_fifo_errors = dev->stats.rx_fifo_errors;
6836 stats->rx_missed_errors = dev->stats.rx_missed_errors;
6837 stats->multicast = dev->stats.multicast;
6840 * Fetch additonal counter values missing in stats collected by driver
6841 * from tally counters.
6843 if (pm_runtime_active(&pdev->dev))
6844 rtl8169_update_counters(tp);
6847 * Subtract values fetched during initalization.
6848 * See rtl8169_init_counter_offsets for a description why we do that.
6850 stats->tx_errors = le64_to_cpu(counters->tx_errors) -
6851 le64_to_cpu(tp->tc_offset.tx_errors);
6852 stats->collisions = le32_to_cpu(counters->tx_multi_collision) -
6853 le32_to_cpu(tp->tc_offset.tx_multi_collision);
6854 stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) -
6855 le16_to_cpu(tp->tc_offset.tx_aborted);
6857 pm_runtime_put_noidle(&pdev->dev);
6860 static void rtl8169_net_suspend(struct net_device *dev)
6862 struct rtl8169_private *tp = netdev_priv(dev);
6864 if (!netif_running(dev))
6867 phy_stop(tp->phydev);
6868 netif_device_detach(dev);
6871 napi_disable(&tp->napi);
6872 /* Clear all task flags */
6873 bitmap_zero(tp->wk.flags, RTL_FLAG_MAX);
6875 rtl_unlock_work(tp);
6877 rtl_pll_power_down(tp);
6882 static int rtl8169_suspend(struct device *device)
6884 struct net_device *dev = dev_get_drvdata(device);
6885 struct rtl8169_private *tp = netdev_priv(dev);
6887 rtl8169_net_suspend(dev);
6888 clk_disable_unprepare(tp->clk);
6893 static void __rtl8169_resume(struct net_device *dev)
6895 struct rtl8169_private *tp = netdev_priv(dev);
6897 netif_device_attach(dev);
6899 rtl_pll_power_up(tp);
6900 rtl8169_init_phy(dev, tp);
6902 phy_start(tp->phydev);
6905 napi_enable(&tp->napi);
6906 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6908 rtl_unlock_work(tp);
6911 static int rtl8169_resume(struct device *device)
6913 struct net_device *dev = dev_get_drvdata(device);
6914 struct rtl8169_private *tp = netdev_priv(dev);
6916 clk_prepare_enable(tp->clk);
6918 if (netif_running(dev))
6919 __rtl8169_resume(dev);
6924 static int rtl8169_runtime_suspend(struct device *device)
6926 struct net_device *dev = dev_get_drvdata(device);
6927 struct rtl8169_private *tp = netdev_priv(dev);
6929 if (!tp->TxDescArray)
6933 __rtl8169_set_wol(tp, WAKE_ANY);
6934 rtl_unlock_work(tp);
6936 rtl8169_net_suspend(dev);
6938 /* Update counters before going runtime suspend */
6939 rtl8169_rx_missed(dev);
6940 rtl8169_update_counters(tp);
6945 static int rtl8169_runtime_resume(struct device *device)
6947 struct net_device *dev = dev_get_drvdata(device);
6948 struct rtl8169_private *tp = netdev_priv(dev);
6949 rtl_rar_set(tp, dev->dev_addr);
6951 if (!tp->TxDescArray)
6955 __rtl8169_set_wol(tp, tp->saved_wolopts);
6956 rtl_unlock_work(tp);
6958 __rtl8169_resume(dev);
6963 static int rtl8169_runtime_idle(struct device *device)
6965 struct net_device *dev = dev_get_drvdata(device);
6967 if (!netif_running(dev) || !netif_carrier_ok(dev))
6968 pm_schedule_suspend(device, 10000);
6973 static const struct dev_pm_ops rtl8169_pm_ops = {
6974 .suspend = rtl8169_suspend,
6975 .resume = rtl8169_resume,
6976 .freeze = rtl8169_suspend,
6977 .thaw = rtl8169_resume,
6978 .poweroff = rtl8169_suspend,
6979 .restore = rtl8169_resume,
6980 .runtime_suspend = rtl8169_runtime_suspend,
6981 .runtime_resume = rtl8169_runtime_resume,
6982 .runtime_idle = rtl8169_runtime_idle,
6985 #define RTL8169_PM_OPS (&rtl8169_pm_ops)
6987 #else /* !CONFIG_PM */
6989 #define RTL8169_PM_OPS NULL
6991 #endif /* !CONFIG_PM */
6993 static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
6995 /* WoL fails with 8168b when the receiver is disabled. */
6996 switch (tp->mac_version) {
6997 case RTL_GIGA_MAC_VER_11:
6998 case RTL_GIGA_MAC_VER_12:
6999 case RTL_GIGA_MAC_VER_17:
7000 pci_clear_master(tp->pci_dev);
7002 RTL_W8(tp, ChipCmd, CmdRxEnb);
7004 RTL_R8(tp, ChipCmd);
7011 static void rtl_shutdown(struct pci_dev *pdev)
7013 struct net_device *dev = pci_get_drvdata(pdev);
7014 struct rtl8169_private *tp = netdev_priv(dev);
7016 rtl8169_net_suspend(dev);
7018 /* Restore original MAC address */
7019 rtl_rar_set(tp, dev->perm_addr);
7021 rtl8169_hw_reset(tp);
7023 if (system_state == SYSTEM_POWER_OFF) {
7024 if (tp->saved_wolopts) {
7025 rtl_wol_suspend_quirk(tp);
7026 rtl_wol_shutdown_quirk(tp);
7029 pci_wake_from_d3(pdev, true);
7030 pci_set_power_state(pdev, PCI_D3hot);
7034 static void rtl_remove_one(struct pci_dev *pdev)
7036 struct net_device *dev = pci_get_drvdata(pdev);
7037 struct rtl8169_private *tp = netdev_priv(dev);
7039 if (r8168_check_dash(tp))
7040 rtl8168_driver_stop(tp);
7042 netif_napi_del(&tp->napi);
7044 unregister_netdev(dev);
7045 mdiobus_unregister(tp->phydev->mdio.bus);
7047 rtl_release_firmware(tp);
7049 if (pci_dev_run_wake(pdev))
7050 pm_runtime_get_noresume(&pdev->dev);
7052 /* restore original MAC address */
7053 rtl_rar_set(tp, dev->perm_addr);
7056 static const struct net_device_ops rtl_netdev_ops = {
7057 .ndo_open = rtl_open,
7058 .ndo_stop = rtl8169_close,
7059 .ndo_get_stats64 = rtl8169_get_stats64,
7060 .ndo_start_xmit = rtl8169_start_xmit,
7061 .ndo_tx_timeout = rtl8169_tx_timeout,
7062 .ndo_validate_addr = eth_validate_addr,
7063 .ndo_change_mtu = rtl8169_change_mtu,
7064 .ndo_fix_features = rtl8169_fix_features,
7065 .ndo_set_features = rtl8169_set_features,
7066 .ndo_set_mac_address = rtl_set_mac_address,
7067 .ndo_do_ioctl = rtl8169_ioctl,
7068 .ndo_set_rx_mode = rtl_set_rx_mode,
7069 #ifdef CONFIG_NET_POLL_CONTROLLER
7070 .ndo_poll_controller = rtl8169_netpoll,
7075 static const struct rtl_cfg_info {
7076 void (*hw_start)(struct rtl8169_private *tp);
7078 unsigned int has_gmii:1;
7079 const struct rtl_coalesce_info *coalesce_info;
7080 } rtl_cfg_infos [] = {
7082 .hw_start = rtl_hw_start_8169,
7083 .irq_mask = SYSErr | LinkChg | RxOverflow | RxFIFOOver,
7085 .coalesce_info = rtl_coalesce_info_8169,
7088 .hw_start = rtl_hw_start_8168,
7089 .irq_mask = LinkChg | RxOverflow,
7091 .coalesce_info = rtl_coalesce_info_8168_8136,
7094 .hw_start = rtl_hw_start_8101,
7095 .irq_mask = LinkChg | RxOverflow | RxFIFOOver,
7096 .coalesce_info = rtl_coalesce_info_8168_8136,
7100 static int rtl_alloc_irq(struct rtl8169_private *tp)
7104 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
7105 rtl_unlock_config_regs(tp);
7106 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~MSIEnable);
7107 rtl_lock_config_regs(tp);
7108 flags = PCI_IRQ_LEGACY;
7110 flags = PCI_IRQ_ALL_TYPES;
7113 return pci_alloc_irq_vectors(tp->pci_dev, 1, 1, flags);
7116 static void rtl_read_mac_address(struct rtl8169_private *tp,
7117 u8 mac_addr[ETH_ALEN])
7121 /* Get MAC address */
7122 switch (tp->mac_version) {
7123 case RTL_GIGA_MAC_VER_35 ... RTL_GIGA_MAC_VER_38:
7124 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
7125 value = rtl_eri_read(tp, 0xe0, ERIAR_EXGMAC);
7126 mac_addr[0] = (value >> 0) & 0xff;
7127 mac_addr[1] = (value >> 8) & 0xff;
7128 mac_addr[2] = (value >> 16) & 0xff;
7129 mac_addr[3] = (value >> 24) & 0xff;
7131 value = rtl_eri_read(tp, 0xe4, ERIAR_EXGMAC);
7132 mac_addr[4] = (value >> 0) & 0xff;
7133 mac_addr[5] = (value >> 8) & 0xff;
7140 DECLARE_RTL_COND(rtl_link_list_ready_cond)
7142 return RTL_R8(tp, MCU) & LINK_LIST_RDY;
7145 DECLARE_RTL_COND(rtl_rxtx_empty_cond)
7147 return (RTL_R8(tp, MCU) & RXTX_EMPTY) == RXTX_EMPTY;
7150 static int r8169_mdio_read_reg(struct mii_bus *mii_bus, int phyaddr, int phyreg)
7152 struct rtl8169_private *tp = mii_bus->priv;
7157 return rtl_readphy(tp, phyreg);
7160 static int r8169_mdio_write_reg(struct mii_bus *mii_bus, int phyaddr,
7161 int phyreg, u16 val)
7163 struct rtl8169_private *tp = mii_bus->priv;
7168 rtl_writephy(tp, phyreg, val);
7173 static int r8169_mdio_register(struct rtl8169_private *tp)
7175 struct pci_dev *pdev = tp->pci_dev;
7176 struct mii_bus *new_bus;
7179 new_bus = devm_mdiobus_alloc(&pdev->dev);
7183 new_bus->name = "r8169";
7185 new_bus->parent = &pdev->dev;
7186 new_bus->irq[0] = PHY_IGNORE_INTERRUPT;
7187 snprintf(new_bus->id, MII_BUS_ID_SIZE, "r8169-%x",
7188 PCI_DEVID(pdev->bus->number, pdev->devfn));
7190 new_bus->read = r8169_mdio_read_reg;
7191 new_bus->write = r8169_mdio_write_reg;
7193 ret = mdiobus_register(new_bus);
7197 tp->phydev = mdiobus_get_phy(new_bus, 0);
7199 mdiobus_unregister(new_bus);
7203 /* PHY will be woken up in rtl_open() */
7204 phy_suspend(tp->phydev);
7209 static void rtl_hw_init_8168g(struct rtl8169_private *tp)
7213 tp->ocp_base = OCP_STD_PHY_BASE;
7215 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN);
7217 if (!rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42))
7220 if (!rtl_udelay_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42))
7223 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
7225 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
7227 data = r8168_mac_ocp_read(tp, 0xe8de);
7229 r8168_mac_ocp_write(tp, 0xe8de, data);
7231 if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
7234 data = r8168_mac_ocp_read(tp, 0xe8de);
7236 r8168_mac_ocp_write(tp, 0xe8de, data);
7238 if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
7242 static void rtl_hw_init_8168ep(struct rtl8169_private *tp)
7244 rtl8168ep_stop_cmac(tp);
7245 rtl_hw_init_8168g(tp);
7248 static void rtl_hw_initialize(struct rtl8169_private *tp)
7250 switch (tp->mac_version) {
7251 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_48:
7252 rtl_hw_init_8168g(tp);
7254 case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_51:
7255 rtl_hw_init_8168ep(tp);
7262 /* Versions RTL8102e and from RTL8168c onwards support csum_v2 */
7263 static bool rtl_chip_supports_csum_v2(struct rtl8169_private *tp)
7265 switch (tp->mac_version) {
7266 case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_06:
7267 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
7274 static int rtl_jumbo_max(struct rtl8169_private *tp)
7276 /* Non-GBit versions don't support jumbo frames */
7277 if (!tp->supports_gmii)
7280 switch (tp->mac_version) {
7282 case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_06:
7285 case RTL_GIGA_MAC_VER_11:
7286 case RTL_GIGA_MAC_VER_12:
7287 case RTL_GIGA_MAC_VER_17:
7290 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
7297 static void rtl_disable_clk(void *data)
7299 clk_disable_unprepare(data);
7302 static int rtl_get_ether_clk(struct rtl8169_private *tp)
7304 struct device *d = tp_to_dev(tp);
7308 clk = devm_clk_get(d, "ether_clk");
7312 /* clk-core allows NULL (for suspend / resume) */
7314 else if (rc != -EPROBE_DEFER)
7315 dev_err(d, "failed to get clk: %d\n", rc);
7318 rc = clk_prepare_enable(clk);
7320 dev_err(d, "failed to enable clk: %d\n", rc);
7322 rc = devm_add_action_or_reset(d, rtl_disable_clk, clk);
7328 static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
7330 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
7331 /* align to u16 for is_valid_ether_addr() */
7332 u8 mac_addr[ETH_ALEN] __aligned(2) = {};
7333 struct rtl8169_private *tp;
7334 struct net_device *dev;
7335 int chipset, region, i;
7338 dev = devm_alloc_etherdev(&pdev->dev, sizeof (*tp));
7342 SET_NETDEV_DEV(dev, &pdev->dev);
7343 dev->netdev_ops = &rtl_netdev_ops;
7344 tp = netdev_priv(dev);
7347 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
7348 tp->supports_gmii = cfg->has_gmii;
7350 /* Get the *optional* external "ether_clk" used on some boards */
7351 rc = rtl_get_ether_clk(tp);
7355 /* enable device (incl. PCI PM wakeup and hotplug setup) */
7356 rc = pcim_enable_device(pdev);
7358 dev_err(&pdev->dev, "enable failure\n");
7362 if (pcim_set_mwi(pdev) < 0)
7363 dev_info(&pdev->dev, "Mem-Wr-Inval unavailable\n");
7365 /* use first MMIO region */
7366 region = ffs(pci_select_bars(pdev, IORESOURCE_MEM)) - 1;
7368 dev_err(&pdev->dev, "no MMIO resource found\n");
7372 /* check for weird/broken PCI region reporting */
7373 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
7374 dev_err(&pdev->dev, "Invalid PCI region size(s), aborting\n");
7378 rc = pcim_iomap_regions(pdev, BIT(region), MODULENAME);
7380 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
7384 tp->mmio_addr = pcim_iomap_table(pdev)[region];
7386 /* Identify chip attached to board */
7387 rtl8169_get_mac_version(tp);
7388 if (tp->mac_version == RTL_GIGA_MAC_NONE)
7391 if (rtl_tbi_enabled(tp)) {
7392 dev_err(&pdev->dev, "TBI fiber mode not supported\n");
7396 tp->cp_cmd = RTL_R16(tp, CPlusCmd);
7398 if (sizeof(dma_addr_t) > 4 && tp->mac_version >= RTL_GIGA_MAC_VER_18 &&
7399 !dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) {
7400 dev->features |= NETIF_F_HIGHDMA;
7402 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
7404 dev_err(&pdev->dev, "DMA configuration failed\n");
7411 rtl8169_irq_mask_and_ack(tp);
7413 rtl_hw_initialize(tp);
7417 pci_set_master(pdev);
7419 rtl_init_mdio_ops(tp);
7420 rtl_init_jumbo_ops(tp);
7422 chipset = tp->mac_version;
7424 rc = rtl_alloc_irq(tp);
7426 dev_err(&pdev->dev, "Can't allocate interrupt\n");
7430 mutex_init(&tp->wk.mutex);
7431 INIT_WORK(&tp->wk.work, rtl_task);
7432 u64_stats_init(&tp->rx_stats.syncp);
7433 u64_stats_init(&tp->tx_stats.syncp);
7435 /* get MAC address */
7436 rc = eth_platform_get_mac_address(&pdev->dev, mac_addr);
7438 rtl_read_mac_address(tp, mac_addr);
7440 if (is_valid_ether_addr(mac_addr))
7441 rtl_rar_set(tp, mac_addr);
7443 for (i = 0; i < ETH_ALEN; i++)
7444 dev->dev_addr[i] = RTL_R8(tp, MAC0 + i);
7446 dev->ethtool_ops = &rtl8169_ethtool_ops;
7448 netif_napi_add(dev, &tp->napi, rtl8169_poll, NAPI_POLL_WEIGHT);
7450 /* don't enable SG, IP_CSUM and TSO by default - it might not work
7451 * properly for all devices */
7452 dev->features |= NETIF_F_RXCSUM |
7453 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
7455 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
7456 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_TX |
7457 NETIF_F_HW_VLAN_CTAG_RX;
7458 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
7460 dev->priv_flags |= IFF_LIVE_ADDR_CHANGE;
7462 tp->cp_cmd |= RxChkSum | RxVlan;
7465 * Pretend we are using VLANs; This bypasses a nasty bug where
7466 * Interrupts stop flowing on high load on 8110SCd controllers.
7468 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
7469 /* Disallow toggling */
7470 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX;
7472 if (rtl_chip_supports_csum_v2(tp)) {
7473 tp->tso_csum = rtl8169_tso_csum_v2;
7474 dev->hw_features |= NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
7476 tp->tso_csum = rtl8169_tso_csum_v1;
7479 dev->hw_features |= NETIF_F_RXALL;
7480 dev->hw_features |= NETIF_F_RXFCS;
7482 /* MTU range: 60 - hw-specific max */
7483 dev->min_mtu = ETH_ZLEN;
7484 jumbo_max = rtl_jumbo_max(tp);
7485 dev->max_mtu = jumbo_max;
7487 tp->hw_start = cfg->hw_start;
7488 tp->irq_mask = RTL_EVENT_NAPI | cfg->irq_mask;
7489 tp->coalesce_info = cfg->coalesce_info;
7491 tp->fw_name = rtl_chip_infos[chipset].fw_name;
7493 tp->counters = dmam_alloc_coherent (&pdev->dev, sizeof(*tp->counters),
7494 &tp->counters_phys_addr,
7499 pci_set_drvdata(pdev, dev);
7501 rc = r8169_mdio_register(tp);
7505 /* chip gets powered up in rtl_open() */
7506 rtl_pll_power_down(tp);
7508 rc = register_netdev(dev);
7510 goto err_mdio_unregister;
7512 netif_info(tp, probe, dev, "%s, %pM, XID %03x, IRQ %d\n",
7513 rtl_chip_infos[chipset].name, dev->dev_addr,
7514 (RTL_R32(tp, TxConfig) >> 20) & 0xfcf,
7515 pci_irq_vector(pdev, 0));
7517 if (jumbo_max > JUMBO_1K)
7518 netif_info(tp, probe, dev,
7519 "jumbo features [frames: %d bytes, tx checksumming: %s]\n",
7520 jumbo_max, tp->mac_version <= RTL_GIGA_MAC_VER_06 ?
7523 if (r8168_check_dash(tp))
7524 rtl8168_driver_start(tp);
7526 if (pci_dev_run_wake(pdev))
7527 pm_runtime_put_sync(&pdev->dev);
7531 err_mdio_unregister:
7532 mdiobus_unregister(tp->phydev->mdio.bus);
7536 static struct pci_driver rtl8169_pci_driver = {
7538 .id_table = rtl8169_pci_tbl,
7539 .probe = rtl_init_one,
7540 .remove = rtl_remove_one,
7541 .shutdown = rtl_shutdown,
7542 .driver.pm = RTL8169_PM_OPS,
7545 module_pci_driver(rtl8169_pci_driver);