drivers/net/ethernet/realtek/r8169.c

   1 /*
   2  * r8169.c: RealTek 8169/8168/8101 ethernet driver.
   3  *
   4  * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
   5  * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
   6  * Copyright (c) a lot of people too. Please respect their work.
   7  *
   8  * See MAINTAINERS file for support contact information.
   9  */
  10
  11 #include <linux/module.h>
  12 #include <linux/moduleparam.h>
  13 #include <linux/pci.h>
  14 #include <linux/netdevice.h>
  15 #include <linux/etherdevice.h>
  16 #include <linux/clk.h>
  17 #include <linux/delay.h>
  18 #include <linux/ethtool.h>
  19 #include <linux/phy.h>
  20 #include <linux/if_vlan.h>
  21 #include <linux/crc32.h>
  22 #include <linux/in.h>
  23 #include <linux/io.h>
  24 #include <linux/ip.h>
  25 #include <linux/tcp.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/dma-mapping.h>
  28 #include <linux/pm_runtime.h>
  29 #include <linux/firmware.h>
  30 #include <linux/prefetch.h>
  31 #include <linux/ipv6.h>
  32 #include <net/ip6_checksum.h>
  33
  34 #define MODULENAME "r8169"
  35
  36 #define FIRMWARE_8168D_1        "rtl_nic/rtl8168d-1.fw"
  37 #define FIRMWARE_8168D_2        "rtl_nic/rtl8168d-2.fw"
  38 #define FIRMWARE_8168E_1        "rtl_nic/rtl8168e-1.fw"
  39 #define FIRMWARE_8168E_2        "rtl_nic/rtl8168e-2.fw"
  40 #define FIRMWARE_8168E_3        "rtl_nic/rtl8168e-3.fw"
  41 #define FIRMWARE_8168F_1        "rtl_nic/rtl8168f-1.fw"
  42 #define FIRMWARE_8168F_2        "rtl_nic/rtl8168f-2.fw"
  43 #define FIRMWARE_8105E_1        "rtl_nic/rtl8105e-1.fw"
  44 #define FIRMWARE_8402_1         "rtl_nic/rtl8402-1.fw"
  45 #define FIRMWARE_8411_1         "rtl_nic/rtl8411-1.fw"
  46 #define FIRMWARE_8411_2         "rtl_nic/rtl8411-2.fw"
  47 #define FIRMWARE_8106E_1        "rtl_nic/rtl8106e-1.fw"
  48 #define FIRMWARE_8106E_2        "rtl_nic/rtl8106e-2.fw"
  49 #define FIRMWARE_8168G_2        "rtl_nic/rtl8168g-2.fw"
  50 #define FIRMWARE_8168G_3        "rtl_nic/rtl8168g-3.fw"
  51 #define FIRMWARE_8168H_1        "rtl_nic/rtl8168h-1.fw"
  52 #define FIRMWARE_8168H_2        "rtl_nic/rtl8168h-2.fw"
  53 #define FIRMWARE_8107E_1        "rtl_nic/rtl8107e-1.fw"
  54 #define FIRMWARE_8107E_2        "rtl_nic/rtl8107e-2.fw"
  55
  56 #define R8169_MSG_DEFAULT \
  57         (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
  58
  59 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
  60    The RTL chips use a 64 element hash table based on the Ethernet CRC. */
  61 static const int multicast_filter_limit = 32;
  62
  63 #define TX_DMA_BURST    7       /* Maximum PCI burst, '7' is unlimited */
  64 #define InterFrameGap   0x03    /* 3 means InterFrameGap = the shortest one */
  65
  66 #define R8169_REGS_SIZE         256
  67 #define R8169_RX_BUF_SIZE       (SZ_16K - 1)
  68 #define NUM_TX_DESC     64      /* Number of Tx descriptor registers */
  69 #define NUM_RX_DESC     256U    /* Number of Rx descriptor registers */
  70 #define R8169_TX_RING_BYTES     (NUM_TX_DESC * sizeof(struct TxDesc))
  71 #define R8169_RX_RING_BYTES     (NUM_RX_DESC * sizeof(struct RxDesc))
  72
  73 /* write/read MMIO register */
  74 #define RTL_W8(tp, reg, val8)   writeb((val8), tp->mmio_addr + (reg))
  75 #define RTL_W16(tp, reg, val16) writew((val16), tp->mmio_addr + (reg))
  76 #define RTL_W32(tp, reg, val32) writel((val32), tp->mmio_addr + (reg))
  77 #define RTL_R8(tp, reg)         readb(tp->mmio_addr + (reg))
  78 #define RTL_R16(tp, reg)                readw(tp->mmio_addr + (reg))
  79 #define RTL_R32(tp, reg)                readl(tp->mmio_addr + (reg))
  80
  81 enum mac_version {
  82         RTL_GIGA_MAC_VER_01 = 0,
  83         RTL_GIGA_MAC_VER_02,
  84         RTL_GIGA_MAC_VER_03,
  85         RTL_GIGA_MAC_VER_04,
  86         RTL_GIGA_MAC_VER_05,
  87         RTL_GIGA_MAC_VER_06,
  88         RTL_GIGA_MAC_VER_07,
  89         RTL_GIGA_MAC_VER_08,
  90         RTL_GIGA_MAC_VER_09,
  91         RTL_GIGA_MAC_VER_10,
  92         RTL_GIGA_MAC_VER_11,
  93         RTL_GIGA_MAC_VER_12,
  94         RTL_GIGA_MAC_VER_13,
  95         RTL_GIGA_MAC_VER_14,
  96         RTL_GIGA_MAC_VER_15,
  97         RTL_GIGA_MAC_VER_16,
  98         RTL_GIGA_MAC_VER_17,
  99         RTL_GIGA_MAC_VER_18,
 100         RTL_GIGA_MAC_VER_19,
 101         RTL_GIGA_MAC_VER_20,
 102         RTL_GIGA_MAC_VER_21,
 103         RTL_GIGA_MAC_VER_22,
 104         RTL_GIGA_MAC_VER_23,
 105         RTL_GIGA_MAC_VER_24,
 106         RTL_GIGA_MAC_VER_25,
 107         RTL_GIGA_MAC_VER_26,
 108         RTL_GIGA_MAC_VER_27,
 109         RTL_GIGA_MAC_VER_28,
 110         RTL_GIGA_MAC_VER_29,
 111         RTL_GIGA_MAC_VER_30,
 112         RTL_GIGA_MAC_VER_31,
 113         RTL_GIGA_MAC_VER_32,
 114         RTL_GIGA_MAC_VER_33,
 115         RTL_GIGA_MAC_VER_34,
 116         RTL_GIGA_MAC_VER_35,
 117         RTL_GIGA_MAC_VER_36,
 118         RTL_GIGA_MAC_VER_37,
 119         RTL_GIGA_MAC_VER_38,
 120         RTL_GIGA_MAC_VER_39,
 121         RTL_GIGA_MAC_VER_40,
 122         RTL_GIGA_MAC_VER_41,
 123         RTL_GIGA_MAC_VER_42,
 124         RTL_GIGA_MAC_VER_43,
 125         RTL_GIGA_MAC_VER_44,
 126         RTL_GIGA_MAC_VER_45,
 127         RTL_GIGA_MAC_VER_46,
 128         RTL_GIGA_MAC_VER_47,
 129         RTL_GIGA_MAC_VER_48,
 130         RTL_GIGA_MAC_VER_49,
 131         RTL_GIGA_MAC_VER_50,
 132         RTL_GIGA_MAC_VER_51,
 133         RTL_GIGA_MAC_NONE   = 0xff,
 134 };
 135
 136 #define JUMBO_1K        ETH_DATA_LEN
 137 #define JUMBO_4K        (4*1024 - ETH_HLEN - 2)
 138 #define JUMBO_6K        (6*1024 - ETH_HLEN - 2)
 139 #define JUMBO_7K        (7*1024 - ETH_HLEN - 2)
 140 #define JUMBO_9K        (9*1024 - ETH_HLEN - 2)
 141
 142 static const struct {
 143         const char *name;
 144         const char *fw_name;
 145 } rtl_chip_infos[] = {
 146         /* PCI devices. */
 147         [RTL_GIGA_MAC_VER_01] = {"RTL8169"                              },
 148         [RTL_GIGA_MAC_VER_02] = {"RTL8169s"                             },
 149         [RTL_GIGA_MAC_VER_03] = {"RTL8110s"                             },
 150         [RTL_GIGA_MAC_VER_04] = {"RTL8169sb/8110sb"                     },
 151         [RTL_GIGA_MAC_VER_05] = {"RTL8169sc/8110sc"                     },
 152         [RTL_GIGA_MAC_VER_06] = {"RTL8169sc/8110sc"                     },
 153         /* PCI-E devices. */
 154         [RTL_GIGA_MAC_VER_07] = {"RTL8102e"                             },
 155         [RTL_GIGA_MAC_VER_08] = {"RTL8102e"                             },
 156         [RTL_GIGA_MAC_VER_09] = {"RTL8102e"                             },
 157         [RTL_GIGA_MAC_VER_10] = {"RTL8101e"                             },
 158         [RTL_GIGA_MAC_VER_11] = {"RTL8168b/8111b"                       },
 159         [RTL_GIGA_MAC_VER_12] = {"RTL8168b/8111b"                       },
 160         [RTL_GIGA_MAC_VER_13] = {"RTL8101e"                             },
 161         [RTL_GIGA_MAC_VER_14] = {"RTL8100e"                             },
 162         [RTL_GIGA_MAC_VER_15] = {"RTL8100e"                             },
 163         [RTL_GIGA_MAC_VER_16] = {"RTL8101e"                             },
 164         [RTL_GIGA_MAC_VER_17] = {"RTL8168b/8111b"                       },
 165         [RTL_GIGA_MAC_VER_18] = {"RTL8168cp/8111cp"                     },
 166         [RTL_GIGA_MAC_VER_19] = {"RTL8168c/8111c"                       },
 167         [RTL_GIGA_MAC_VER_20] = {"RTL8168c/8111c"                       },
 168         [RTL_GIGA_MAC_VER_21] = {"RTL8168c/8111c"                       },
 169         [RTL_GIGA_MAC_VER_22] = {"RTL8168c/8111c"                       },
 170         [RTL_GIGA_MAC_VER_23] = {"RTL8168cp/8111cp"                     },
 171         [RTL_GIGA_MAC_VER_24] = {"RTL8168cp/8111cp"                     },
 172         [RTL_GIGA_MAC_VER_25] = {"RTL8168d/8111d",      FIRMWARE_8168D_1},
 173         [RTL_GIGA_MAC_VER_26] = {"RTL8168d/8111d",      FIRMWARE_8168D_2},
 174         [RTL_GIGA_MAC_VER_27] = {"RTL8168dp/8111dp"                     },
 175         [RTL_GIGA_MAC_VER_28] = {"RTL8168dp/8111dp"                     },
 176         [RTL_GIGA_MAC_VER_29] = {"RTL8105e",            FIRMWARE_8105E_1},
 177         [RTL_GIGA_MAC_VER_30] = {"RTL8105e",            FIRMWARE_8105E_1},
 178         [RTL_GIGA_MAC_VER_31] = {"RTL8168dp/8111dp"                     },
 179         [RTL_GIGA_MAC_VER_32] = {"RTL8168e/8111e",      FIRMWARE_8168E_1},
 180         [RTL_GIGA_MAC_VER_33] = {"RTL8168e/8111e",      FIRMWARE_8168E_2},
 181         [RTL_GIGA_MAC_VER_34] = {"RTL8168evl/8111evl",  FIRMWARE_8168E_3},
 182         [RTL_GIGA_MAC_VER_35] = {"RTL8168f/8111f",      FIRMWARE_8168F_1},
 183         [RTL_GIGA_MAC_VER_36] = {"RTL8168f/8111f",      FIRMWARE_8168F_2},
 184         [RTL_GIGA_MAC_VER_37] = {"RTL8402",             FIRMWARE_8402_1 },
 185         [RTL_GIGA_MAC_VER_38] = {"RTL8411",             FIRMWARE_8411_1 },
 186         [RTL_GIGA_MAC_VER_39] = {"RTL8106e",            FIRMWARE_8106E_1},
 187         [RTL_GIGA_MAC_VER_40] = {"RTL8168g/8111g",      FIRMWARE_8168G_2},
 188         [RTL_GIGA_MAC_VER_41] = {"RTL8168g/8111g"                       },
 189         [RTL_GIGA_MAC_VER_42] = {"RTL8168g/8111g",      FIRMWARE_8168G_3},
 190         [RTL_GIGA_MAC_VER_43] = {"RTL8106e",            FIRMWARE_8106E_2},
 191         [RTL_GIGA_MAC_VER_44] = {"RTL8411",             FIRMWARE_8411_2 },
 192         [RTL_GIGA_MAC_VER_45] = {"RTL8168h/8111h",      FIRMWARE_8168H_1},
 193         [RTL_GIGA_MAC_VER_46] = {"RTL8168h/8111h",      FIRMWARE_8168H_2},
 194         [RTL_GIGA_MAC_VER_47] = {"RTL8107e",            FIRMWARE_8107E_1},
 195         [RTL_GIGA_MAC_VER_48] = {"RTL8107e",            FIRMWARE_8107E_2},
 196         [RTL_GIGA_MAC_VER_49] = {"RTL8168ep/8111ep"                     },
 197         [RTL_GIGA_MAC_VER_50] = {"RTL8168ep/8111ep"                     },
 198         [RTL_GIGA_MAC_VER_51] = {"RTL8168ep/8111ep"                     },
 199 };
 200
 201 enum cfg_version {
 202         RTL_CFG_0 = 0x00,
 203         RTL_CFG_1,
 204         RTL_CFG_2
 205 };
 206
 207 static const struct pci_device_id rtl8169_pci_tbl[] = {
 208         { PCI_VDEVICE(REALTEK,  0x2502), RTL_CFG_1 },
 209         { PCI_VDEVICE(REALTEK,  0x2600), RTL_CFG_1 },
 210         { PCI_VDEVICE(REALTEK,  0x8129), RTL_CFG_0 },
 211         { PCI_VDEVICE(REALTEK,  0x8136), RTL_CFG_2 },
 212         { PCI_VDEVICE(REALTEK,  0x8161), RTL_CFG_1 },
 213         { PCI_VDEVICE(REALTEK,  0x8167), RTL_CFG_0 },
 214         { PCI_VDEVICE(REALTEK,  0x8168), RTL_CFG_1 },
 215         { PCI_VDEVICE(NCUBE,    0x8168), RTL_CFG_1 },
 216         { PCI_VDEVICE(REALTEK,  0x8169), RTL_CFG_0 },
 217         { PCI_VENDOR_ID_DLINK,  0x4300,
 218                 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0, RTL_CFG_1 },
 219         { PCI_VDEVICE(DLINK,    0x4300), RTL_CFG_0 },
 220         { PCI_VDEVICE(DLINK,    0x4302), RTL_CFG_0 },
 221         { PCI_VDEVICE(AT,       0xc107), RTL_CFG_0 },
 222         { PCI_VDEVICE(USR,      0x0116), RTL_CFG_0 },
 223         { PCI_VENDOR_ID_LINKSYS,                0x1032,
 224                 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
 225         { 0x0001,                               0x8168,
 226                 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
 227         {}
 228 };
 229
 230 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
 231
 232 static struct {
 233         u32 msg_enable;
 234 } debug = { -1 };
 235
 236 enum rtl_registers {
 237         MAC0            = 0,    /* Ethernet hardware address. */
 238         MAC4            = 4,
 239         MAR0            = 8,    /* Multicast filter. */
 240         CounterAddrLow          = 0x10,
 241         CounterAddrHigh         = 0x14,
 242         TxDescStartAddrLow      = 0x20,
 243         TxDescStartAddrHigh     = 0x24,
 244         TxHDescStartAddrLow     = 0x28,
 245         TxHDescStartAddrHigh    = 0x2c,
 246         FLASH           = 0x30,
 247         ERSR            = 0x36,
 248         ChipCmd         = 0x37,
 249         TxPoll          = 0x38,
 250         IntrMask        = 0x3c,
 251         IntrStatus      = 0x3e,
 252
 253         TxConfig        = 0x40,
 254 #define TXCFG_AUTO_FIFO                 (1 << 7)        /* 8111e-vl */
 255 #define TXCFG_EMPTY                     (1 << 11)       /* 8111e-vl */
 256
 257         RxConfig        = 0x44,
 258 #define RX128_INT_EN                    (1 << 15)       /* 8111c and later */
 259 #define RX_MULTI_EN                     (1 << 14)       /* 8111c only */
 260 #define RXCFG_FIFO_SHIFT                13
 261                                         /* No threshold before first PCI xfer */
 262 #define RX_FIFO_THRESH                  (7 << RXCFG_FIFO_SHIFT)
 263 #define RX_EARLY_OFF                    (1 << 11)
 264 #define RXCFG_DMA_SHIFT                 8
 265                                         /* Unlimited maximum PCI burst. */
 266 #define RX_DMA_BURST                    (7 << RXCFG_DMA_SHIFT)
 267
 268         RxMissed        = 0x4c,
 269         Cfg9346         = 0x50,
 270         Config0         = 0x51,
 271         Config1         = 0x52,
 272         Config2         = 0x53,
 273 #define PME_SIGNAL                      (1 << 5)        /* 8168c and later */
 274
 275         Config3         = 0x54,
 276         Config4         = 0x55,
 277         Config5         = 0x56,
 278         MultiIntr       = 0x5c,
 279         PHYAR           = 0x60,
 280         PHYstatus       = 0x6c,
 281         RxMaxSize       = 0xda,
 282         CPlusCmd        = 0xe0,
 283         IntrMitigate    = 0xe2,
 284
 285 #define RTL_COALESCE_MASK       0x0f
 286 #define RTL_COALESCE_SHIFT      4
 287 #define RTL_COALESCE_T_MAX      (RTL_COALESCE_MASK)
 288 #define RTL_COALESCE_FRAME_MAX  (RTL_COALESCE_MASK << 2)
 289
 290         RxDescAddrLow   = 0xe4,
 291         RxDescAddrHigh  = 0xe8,
 292         EarlyTxThres    = 0xec, /* 8169. Unit of 32 bytes. */
 293
 294 #define NoEarlyTx       0x3f    /* Max value : no early transmit. */
 295
 296         MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
 297
 298 #define TxPacketMax     (8064 >> 7)
 299 #define EarlySize       0x27
 300
 301         FuncEvent       = 0xf0,
 302         FuncEventMask   = 0xf4,
 303         FuncPresetState = 0xf8,
 304         IBCR0           = 0xf8,
 305         IBCR2           = 0xf9,
 306         IBIMR0          = 0xfa,
 307         IBISR0          = 0xfb,
 308         FuncForceEvent  = 0xfc,
 309 };
 310
 311 enum rtl8168_8101_registers {
 312         CSIDR                   = 0x64,
 313         CSIAR                   = 0x68,
 314 #define CSIAR_FLAG                      0x80000000
 315 #define CSIAR_WRITE_CMD                 0x80000000
 316 #define CSIAR_BYTE_ENABLE               0x0000f000
 317 #define CSIAR_ADDR_MASK                 0x00000fff
 318         PMCH                    = 0x6f,
 319         EPHYAR                  = 0x80,
 320 #define EPHYAR_FLAG                     0x80000000
 321 #define EPHYAR_WRITE_CMD                0x80000000
 322 #define EPHYAR_REG_MASK                 0x1f
 323 #define EPHYAR_REG_SHIFT                16
 324 #define EPHYAR_DATA_MASK                0xffff
 325         DLLPR                   = 0xd0,
 326 #define PFM_EN                          (1 << 6)
 327 #define TX_10M_PS_EN                    (1 << 7)
 328         DBG_REG                 = 0xd1,
 329 #define FIX_NAK_1                       (1 << 4)
 330 #define FIX_NAK_2                       (1 << 3)
 331         TWSI                    = 0xd2,
 332         MCU                     = 0xd3,
 333 #define NOW_IS_OOB                      (1 << 7)
 334 #define TX_EMPTY                        (1 << 5)
 335 #define RX_EMPTY                        (1 << 4)
 336 #define RXTX_EMPTY                      (TX_EMPTY | RX_EMPTY)
 337 #define EN_NDP                          (1 << 3)
 338 #define EN_OOB_RESET                    (1 << 2)
 339 #define LINK_LIST_RDY                   (1 << 1)
 340         EFUSEAR                 = 0xdc,
 341 #define EFUSEAR_FLAG                    0x80000000
 342 #define EFUSEAR_WRITE_CMD               0x80000000
 343 #define EFUSEAR_READ_CMD                0x00000000
 344 #define EFUSEAR_REG_MASK                0x03ff
 345 #define EFUSEAR_REG_SHIFT               8
 346 #define EFUSEAR_DATA_MASK               0xff
 347         MISC_1                  = 0xf2,
 348 #define PFM_D3COLD_EN                   (1 << 6)
 349 };
 350
 351 enum rtl8168_registers {
 352         LED_FREQ                = 0x1a,
 353         EEE_LED                 = 0x1b,
 354         ERIDR                   = 0x70,
 355         ERIAR                   = 0x74,
 356 #define ERIAR_FLAG                      0x80000000
 357 #define ERIAR_WRITE_CMD                 0x80000000
 358 #define ERIAR_READ_CMD                  0x00000000
 359 #define ERIAR_ADDR_BYTE_ALIGN           4
 360 #define ERIAR_TYPE_SHIFT                16
 361 #define ERIAR_EXGMAC                    (0x00 << ERIAR_TYPE_SHIFT)
 362 #define ERIAR_MSIX                      (0x01 << ERIAR_TYPE_SHIFT)
 363 #define ERIAR_ASF                       (0x02 << ERIAR_TYPE_SHIFT)
 364 #define ERIAR_OOB                       (0x02 << ERIAR_TYPE_SHIFT)
 365 #define ERIAR_MASK_SHIFT                12
 366 #define ERIAR_MASK_0001                 (0x1 << ERIAR_MASK_SHIFT)
 367 #define ERIAR_MASK_0011                 (0x3 << ERIAR_MASK_SHIFT)
 368 #define ERIAR_MASK_0100                 (0x4 << ERIAR_MASK_SHIFT)
 369 #define ERIAR_MASK_0101                 (0x5 << ERIAR_MASK_SHIFT)
 370 #define ERIAR_MASK_1111                 (0xf << ERIAR_MASK_SHIFT)
 371         EPHY_RXER_NUM           = 0x7c,
 372         OCPDR                   = 0xb0, /* OCP GPHY access */
 373 #define OCPDR_WRITE_CMD                 0x80000000
 374 #define OCPDR_READ_CMD                  0x00000000
 375 #define OCPDR_REG_MASK                  0x7f
 376 #define OCPDR_GPHY_REG_SHIFT            16
 377 #define OCPDR_DATA_MASK                 0xffff
 378         OCPAR                   = 0xb4,
 379 #define OCPAR_FLAG                      0x80000000
 380 #define OCPAR_GPHY_WRITE_CMD            0x8000f060
 381 #define OCPAR_GPHY_READ_CMD             0x0000f060
 382         GPHY_OCP                = 0xb8,
 383         RDSAR1                  = 0xd0, /* 8168c only. Undocumented on 8168dp */
 384         MISC                    = 0xf0, /* 8168e only. */
 385 #define TXPLA_RST                       (1 << 29)
 386 #define DISABLE_LAN_EN                  (1 << 23) /* Enable GPIO pin */
 387 #define PWM_EN                          (1 << 22)
 388 #define RXDV_GATED_EN                   (1 << 19)
 389 #define EARLY_TALLY_EN                  (1 << 16)
 390 };
 391
 392 enum rtl_register_content {
 393         /* InterruptStatusBits */
 394         SYSErr          = 0x8000,
 395         PCSTimeout      = 0x4000,
 396         SWInt           = 0x0100,
 397         TxDescUnavail   = 0x0080,
 398         RxFIFOOver      = 0x0040,
 399         LinkChg         = 0x0020,
 400         RxOverflow      = 0x0010,
 401         TxErr           = 0x0008,
 402         TxOK            = 0x0004,
 403         RxErr           = 0x0002,
 404         RxOK            = 0x0001,
 405
 406         /* RxStatusDesc */
 407         RxBOVF  = (1 << 24),
 408         RxFOVF  = (1 << 23),
 409         RxRWT   = (1 << 22),
 410         RxRES   = (1 << 21),
 411         RxRUNT  = (1 << 20),
 412         RxCRC   = (1 << 19),
 413
 414         /* ChipCmdBits */
 415         StopReq         = 0x80,
 416         CmdReset        = 0x10,
 417         CmdRxEnb        = 0x08,
 418         CmdTxEnb        = 0x04,
 419         RxBufEmpty      = 0x01,
 420
 421         /* TXPoll register p.5 */
 422         HPQ             = 0x80,         /* Poll cmd on the high prio queue */
 423         NPQ             = 0x40,         /* Poll cmd on the low prio queue */
 424         FSWInt          = 0x01,         /* Forced software interrupt */
 425
 426         /* Cfg9346Bits */
 427         Cfg9346_Lock    = 0x00,
 428         Cfg9346_Unlock  = 0xc0,
 429
 430         /* rx_mode_bits */
 431         AcceptErr       = 0x20,
 432         AcceptRunt      = 0x10,
 433         AcceptBroadcast = 0x08,
 434         AcceptMulticast = 0x04,
 435         AcceptMyPhys    = 0x02,
 436         AcceptAllPhys   = 0x01,
 437 #define RX_CONFIG_ACCEPT_MASK           0x3f
 438
 439         /* TxConfigBits */
 440         TxInterFrameGapShift = 24,
 441         TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
 442
 443         /* Config1 register p.24 */
 444         LEDS1           = (1 << 7),
 445         LEDS0           = (1 << 6),
 446         Speed_down      = (1 << 4),
 447         MEMMAP          = (1 << 3),
 448         IOMAP           = (1 << 2),
 449         VPD             = (1 << 1),
 450         PMEnable        = (1 << 0),     /* Power Management Enable */
 451
 452         /* Config2 register p. 25 */
 453         ClkReqEn        = (1 << 7),     /* Clock Request Enable */
 454         MSIEnable       = (1 << 5),     /* 8169 only. Reserved in the 8168. */
 455         PCI_Clock_66MHz = 0x01,
 456         PCI_Clock_33MHz = 0x00,
 457
 458         /* Config3 register p.25 */
 459         MagicPacket     = (1 << 5),     /* Wake up when receives a Magic Packet */
 460         LinkUp          = (1 << 4),     /* Wake up when the cable connection is re-established */
 461         Jumbo_En0       = (1 << 2),     /* 8168 only. Reserved in the 8168b */
 462         Rdy_to_L23      = (1 << 1),     /* L23 Enable */
 463         Beacon_en       = (1 << 0),     /* 8168 only. Reserved in the 8168b */
 464
 465         /* Config4 register */
 466         Jumbo_En1       = (1 << 1),     /* 8168 only. Reserved in the 8168b */
 467
 468         /* Config5 register p.27 */
 469         BWF             = (1 << 6),     /* Accept Broadcast wakeup frame */
 470         MWF             = (1 << 5),     /* Accept Multicast wakeup frame */
 471         UWF             = (1 << 4),     /* Accept Unicast wakeup frame */
 472         Spi_en          = (1 << 3),
 473         LanWake         = (1 << 1),     /* LanWake enable/disable */
 474         PMEStatus       = (1 << 0),     /* PME status can be reset by PCI RST# */
 475         ASPM_en         = (1 << 0),     /* ASPM enable */
 476
 477         /* CPlusCmd p.31 */
 478         EnableBist      = (1 << 15),    // 8168 8101
 479         Mac_dbgo_oe     = (1 << 14),    // 8168 8101
 480         Normal_mode     = (1 << 13),    // unused
 481         Force_half_dup  = (1 << 12),    // 8168 8101
 482         Force_rxflow_en = (1 << 11),    // 8168 8101
 483         Force_txflow_en = (1 << 10),    // 8168 8101
 484         Cxpl_dbg_sel    = (1 << 9),     // 8168 8101
 485         ASF             = (1 << 8),     // 8168 8101
 486         PktCntrDisable  = (1 << 7),     // 8168 8101
 487         Mac_dbgo_sel    = 0x001c,       // 8168
 488         RxVlan          = (1 << 6),
 489         RxChkSum        = (1 << 5),
 490         PCIDAC          = (1 << 4),
 491         PCIMulRW        = (1 << 3),
 492 #define INTT_MASK       GENMASK(1, 0)
 493         INTT_0          = 0x0000,       // 8168
 494         INTT_1          = 0x0001,       // 8168
 495         INTT_2          = 0x0002,       // 8168
 496         INTT_3          = 0x0003,       // 8168
 497
 498         /* rtl8169_PHYstatus */
 499         TBI_Enable      = 0x80,
 500         TxFlowCtrl      = 0x40,
 501         RxFlowCtrl      = 0x20,
 502         _1000bpsF       = 0x10,
 503         _100bps         = 0x08,
 504         _10bps          = 0x04,
 505         LinkStatus      = 0x02,
 506         FullDup         = 0x01,
 507
 508         /* _TBICSRBit */
 509         TBILinkOK       = 0x02000000,
 510
 511         /* ResetCounterCommand */
 512         CounterReset    = 0x1,
 513
 514         /* DumpCounterCommand */
 515         CounterDump     = 0x8,
 516
 517         /* magic enable v2 */
 518         MagicPacket_v2  = (1 << 16),    /* Wake up when receives a Magic Packet */
 519 };
 520
 521 enum rtl_desc_bit {
 522         /* First doubleword. */
 523         DescOwn         = (1 << 31), /* Descriptor is owned by NIC */
 524         RingEnd         = (1 << 30), /* End of descriptor ring */
 525         FirstFrag       = (1 << 29), /* First segment of a packet */
 526         LastFrag        = (1 << 28), /* Final segment of a packet */
 527 };
 528
 529 /* Generic case. */
 530 enum rtl_tx_desc_bit {
 531         /* First doubleword. */
 532         TD_LSO          = (1 << 27),            /* Large Send Offload */
 533 #define TD_MSS_MAX                      0x07ffu /* MSS value */
 534
 535         /* Second doubleword. */
 536         TxVlanTag       = (1 << 17),            /* Add VLAN tag */
 537 };
 538
 539 /* 8169, 8168b and 810x except 8102e. */
 540 enum rtl_tx_desc_bit_0 {
 541         /* First doubleword. */
 542 #define TD0_MSS_SHIFT                   16      /* MSS position (11 bits) */
 543         TD0_TCP_CS      = (1 << 16),            /* Calculate TCP/IP checksum */
 544         TD0_UDP_CS      = (1 << 17),            /* Calculate UDP/IP checksum */
 545         TD0_IP_CS       = (1 << 18),            /* Calculate IP checksum */
 546 };
 547
 548 /* 8102e, 8168c and beyond. */
 549 enum rtl_tx_desc_bit_1 {
 550         /* First doubleword. */
 551         TD1_GTSENV4     = (1 << 26),            /* Giant Send for IPv4 */
 552         TD1_GTSENV6     = (1 << 25),            /* Giant Send for IPv6 */
 553 #define GTTCPHO_SHIFT                   18
 554 #define GTTCPHO_MAX                     0x7fU
 555
 556         /* Second doubleword. */
 557 #define TCPHO_SHIFT                     18
 558 #define TCPHO_MAX                       0x3ffU
 559 #define TD1_MSS_SHIFT                   18      /* MSS position (11 bits) */
 560         TD1_IPv6_CS     = (1 << 28),            /* Calculate IPv6 checksum */
 561         TD1_IPv4_CS     = (1 << 29),            /* Calculate IPv4 checksum */
 562         TD1_TCP_CS      = (1 << 30),            /* Calculate TCP/IP checksum */
 563         TD1_UDP_CS      = (1 << 31),            /* Calculate UDP/IP checksum */
 564 };
 565
 566 enum rtl_rx_desc_bit {
 567         /* Rx private */
 568         PID1            = (1 << 18), /* Protocol ID bit 1/2 */
 569         PID0            = (1 << 17), /* Protocol ID bit 0/2 */
 570
 571 #define RxProtoUDP      (PID1)
 572 #define RxProtoTCP      (PID0)
 573 #define RxProtoIP       (PID1 | PID0)
 574 #define RxProtoMask     RxProtoIP
 575
 576         IPFail          = (1 << 16), /* IP checksum failed */
 577         UDPFail         = (1 << 15), /* UDP/IP checksum failed */
 578         TCPFail         = (1 << 14), /* TCP/IP checksum failed */
 579         RxVlanTag       = (1 << 16), /* VLAN tag available */
 580 };
 581
 582 #define RsvdMask        0x3fffc000
 583 #define CPCMD_QUIRK_MASK        (Normal_mode | RxVlan | RxChkSum | INTT_MASK)
 584
 585 struct TxDesc {
 586         __le32 opts1;
 587         __le32 opts2;
 588         __le64 addr;
 589 };
 590
 591 struct RxDesc {
 592         __le32 opts1;
 593         __le32 opts2;
 594         __le64 addr;
 595 };
 596
 597 struct ring_info {
 598         struct sk_buff  *skb;
 599         u32             len;
 600 };
 601
 602 struct rtl8169_counters {
 603         __le64  tx_packets;
 604         __le64  rx_packets;
 605         __le64  tx_errors;
 606         __le32  rx_errors;
 607         __le16  rx_missed;
 608         __le16  align_errors;
 609         __le32  tx_one_collision;
 610         __le32  tx_multi_collision;
 611         __le64  rx_unicast;
 612         __le64  rx_broadcast;
 613         __le32  rx_multicast;
 614         __le16  tx_aborted;
 615         __le16  tx_underun;
 616 };
 617
 618 struct rtl8169_tc_offsets {
 619         bool    inited;
 620         __le64  tx_errors;
 621         __le32  tx_multi_collision;
 622         __le16  tx_aborted;
 623 };
 624
 625 enum rtl_flag {
 626         RTL_FLAG_TASK_ENABLED = 0,
 627         RTL_FLAG_TASK_RESET_PENDING,
 628         RTL_FLAG_MAX
 629 };
 630
 631 struct rtl8169_stats {
 632         u64                     packets;
 633         u64                     bytes;
 634         struct u64_stats_sync   syncp;
 635 };
 636
 637 struct rtl8169_private {
 638         void __iomem *mmio_addr;        /* memory map physical address */
 639         struct pci_dev *pci_dev;
 640         struct net_device *dev;
 641         struct phy_device *phydev;
 642         struct napi_struct napi;
 643         u32 msg_enable;
 644         u16 mac_version;
 645         u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
 646         u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
 647         u32 dirty_tx;
 648         struct rtl8169_stats rx_stats;
 649         struct rtl8169_stats tx_stats;
 650         struct TxDesc *TxDescArray;     /* 256-aligned Tx descriptor ring */
 651         struct RxDesc *RxDescArray;     /* 256-aligned Rx descriptor ring */
 652         dma_addr_t TxPhyAddr;
 653         dma_addr_t RxPhyAddr;
 654         void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
 655         struct ring_info tx_skb[NUM_TX_DESC];   /* Tx data buffers */
 656         u16 cp_cmd;
 657
 658         u16 irq_mask;
 659         const struct rtl_coalesce_info *coalesce_info;
 660         struct clk *clk;
 661
 662         struct mdio_ops {
 663                 void (*write)(struct rtl8169_private *, int, int);
 664                 int (*read)(struct rtl8169_private *, int);
 665         } mdio_ops;
 666
 667         struct jumbo_ops {
 668                 void (*enable)(struct rtl8169_private *);
 669                 void (*disable)(struct rtl8169_private *);
 670         } jumbo_ops;
 671
 672         void (*hw_start)(struct rtl8169_private *tp);
 673         bool (*tso_csum)(struct rtl8169_private *, struct sk_buff *, u32 *);
 674
 675         struct {
 676                 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
 677                 struct mutex mutex;
 678                 struct work_struct work;
 679         } wk;
 680
 681         unsigned supports_gmii:1;
 682         dma_addr_t counters_phys_addr;
 683         struct rtl8169_counters *counters;
 684         struct rtl8169_tc_offsets tc_offset;
 685         u32 saved_wolopts;
 686
 687         const char *fw_name;
 688         struct rtl_fw {
 689                 const struct firmware *fw;
 690
 691 #define RTL_VER_SIZE            32
 692
 693                 char version[RTL_VER_SIZE];
 694
 695                 struct rtl_fw_phy_action {
 696                         __le32 *code;
 697                         size_t size;
 698                 } phy_action;
 699         } *rtl_fw;
 700
 701         u32 ocp_base;
 702 };
 703
 704 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
 705 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
 706 module_param_named(debug, debug.msg_enable, int, 0);
 707 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
 708 MODULE_SOFTDEP("pre: realtek");
 709 MODULE_LICENSE("GPL");
 710 MODULE_FIRMWARE(FIRMWARE_8168D_1);
 711 MODULE_FIRMWARE(FIRMWARE_8168D_2);
 712 MODULE_FIRMWARE(FIRMWARE_8168E_1);
 713 MODULE_FIRMWARE(FIRMWARE_8168E_2);
 714 MODULE_FIRMWARE(FIRMWARE_8168E_3);
 715 MODULE_FIRMWARE(FIRMWARE_8105E_1);
 716 MODULE_FIRMWARE(FIRMWARE_8168F_1);
 717 MODULE_FIRMWARE(FIRMWARE_8168F_2);
 718 MODULE_FIRMWARE(FIRMWARE_8402_1);
 719 MODULE_FIRMWARE(FIRMWARE_8411_1);
 720 MODULE_FIRMWARE(FIRMWARE_8411_2);
 721 MODULE_FIRMWARE(FIRMWARE_8106E_1);
 722 MODULE_FIRMWARE(FIRMWARE_8106E_2);
 723 MODULE_FIRMWARE(FIRMWARE_8168G_2);
 724 MODULE_FIRMWARE(FIRMWARE_8168G_3);
 725 MODULE_FIRMWARE(FIRMWARE_8168H_1);
 726 MODULE_FIRMWARE(FIRMWARE_8168H_2);
 727 MODULE_FIRMWARE(FIRMWARE_8107E_1);
 728 MODULE_FIRMWARE(FIRMWARE_8107E_2);
 729
 730 static inline struct device *tp_to_dev(struct rtl8169_private *tp)
 731 {
 732         return &tp->pci_dev->dev;
 733 }
 734
 735 static void rtl_lock_work(struct rtl8169_private *tp)
 736 {
 737         mutex_lock(&tp->wk.mutex);
 738 }
 739
 740 static void rtl_unlock_work(struct rtl8169_private *tp)
 741 {
 742         mutex_unlock(&tp->wk.mutex);
 743 }
 744
 745 static void rtl_lock_config_regs(struct rtl8169_private *tp)
 746 {
 747         RTL_W8(tp, Cfg9346, Cfg9346_Lock);
 748 }
 749
 750 static void rtl_unlock_config_regs(struct rtl8169_private *tp)
 751 {
 752         RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
 753 }
 754
 755 static void rtl_tx_performance_tweak(struct rtl8169_private *tp, u16 force)
 756 {
 757         pcie_capability_clear_and_set_word(tp->pci_dev, PCI_EXP_DEVCTL,
 758                                            PCI_EXP_DEVCTL_READRQ, force);
 759 }
 760
 761 struct rtl_cond {
 762         bool (*check)(struct rtl8169_private *);
 763         const char *msg;
 764 };
 765
 766 static void rtl_udelay(unsigned int d)
 767 {
 768         udelay(d);
 769 }
 770
 771 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,
 772                           void (*delay)(unsigned int), unsigned int d, int n,
 773                           bool high)
 774 {
 775         int i;
 776
 777         for (i = 0; i < n; i++) {
 778                 delay(d);
 779                 if (c->check(tp) == high)
 780                         return true;
 781         }
 782         netif_err(tp, drv, tp->dev, "%s == %d (loop: %d, delay: %d).\n",
 783                   c->msg, !high, n, d);
 784         return false;
 785 }
 786
 787 static bool rtl_udelay_loop_wait_high(struct rtl8169_private *tp,
 788                                       const struct rtl_cond *c,
 789                                       unsigned int d, int n)
 790 {
 791         return rtl_loop_wait(tp, c, rtl_udelay, d, n, true);
 792 }
 793
 794 static bool rtl_udelay_loop_wait_low(struct rtl8169_private *tp,
 795                                      const struct rtl_cond *c,
 796                                      unsigned int d, int n)
 797 {
 798         return rtl_loop_wait(tp, c, rtl_udelay, d, n, false);
 799 }
 800
 801 static bool rtl_msleep_loop_wait_high(struct rtl8169_private *tp,
 802                                       const struct rtl_cond *c,
 803                                       unsigned int d, int n)
 804 {
 805         return rtl_loop_wait(tp, c, msleep, d, n, true);
 806 }
 807
 808 static bool rtl_msleep_loop_wait_low(struct rtl8169_private *tp,
 809                                      const struct rtl_cond *c,
 810                                      unsigned int d, int n)
 811 {
 812         return rtl_loop_wait(tp, c, msleep, d, n, false);
 813 }
 814
 815 #define DECLARE_RTL_COND(name)                          \
 816 static bool name ## _check(struct rtl8169_private *);   \
 817                                                         \
 818 static const struct rtl_cond name = {                   \
 819         .check  = name ## _check,                       \
 820         .msg    = #name                                 \
 821 };                                                      \
 822                                                         \
 823 static bool name ## _check(struct rtl8169_private *tp)
 824
 825 static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg)
 826 {
 827         if (reg & 0xffff0001) {
 828                 netif_err(tp, drv, tp->dev, "Invalid ocp reg %x!\n", reg);
 829                 return true;
 830         }
 831         return false;
 832 }
 833
 834 DECLARE_RTL_COND(rtl_ocp_gphy_cond)
 835 {
 836         return RTL_R32(tp, GPHY_OCP) & OCPAR_FLAG;
 837 }
 838
 839 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
 840 {
 841         if (rtl_ocp_reg_failure(tp, reg))
 842                 return;
 843
 844         RTL_W32(tp, GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);
 845
 846         rtl_udelay_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);
 847 }
 848
 849 static u16 r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
 850 {
 851         if (rtl_ocp_reg_failure(tp, reg))
 852                 return 0;
 853
 854         RTL_W32(tp, GPHY_OCP, reg << 15);
 855
 856         return rtl_udelay_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?
 857                 (RTL_R32(tp, GPHY_OCP) & 0xffff) : ~0;
 858 }
 859
 860 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
 861 {
 862         if (rtl_ocp_reg_failure(tp, reg))
 863                 return;
 864
 865         RTL_W32(tp, OCPDR, OCPAR_FLAG | (reg << 15) | data);
 866 }
 867
 868 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
 869 {
 870         if (rtl_ocp_reg_failure(tp, reg))
 871                 return 0;
 872
 873         RTL_W32(tp, OCPDR, reg << 15);
 874
 875         return RTL_R32(tp, OCPDR);
 876 }
 877
 878 #define OCP_STD_PHY_BASE        0xa400
 879
 880 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)
 881 {
 882         if (reg == 0x1f) {
 883                 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;
 884                 return;
 885         }
 886
 887         if (tp->ocp_base != OCP_STD_PHY_BASE)
 888                 reg -= 0x10;
 889
 890         r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);
 891 }
 892
 893 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)
 894 {
 895         if (tp->ocp_base != OCP_STD_PHY_BASE)
 896                 reg -= 0x10;
 897
 898         return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);
 899 }
 900
 901 static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value)
 902 {
 903         if (reg == 0x1f) {
 904                 tp->ocp_base = value << 4;
 905                 return;
 906         }
 907
 908         r8168_mac_ocp_write(tp, tp->ocp_base + reg, value);
 909 }
 910
 911 static int mac_mcu_read(struct rtl8169_private *tp, int reg)
 912 {
 913         return r8168_mac_ocp_read(tp, tp->ocp_base + reg);
 914 }
 915
 916 DECLARE_RTL_COND(rtl_phyar_cond)
 917 {
 918         return RTL_R32(tp, PHYAR) & 0x80000000;
 919 }
 920
 921 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)
 922 {
 923         RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
 924
 925         rtl_udelay_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);
 926         /*
 927          * According to hardware specs a 20us delay is required after write
 928          * complete indication, but before sending next command.
 929          */
 930         udelay(20);
 931 }
 932
 933 static int r8169_mdio_read(struct rtl8169_private *tp, int reg)
 934 {
 935         int value;
 936
 937         RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16);
 938
 939         value = rtl_udelay_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?
 940                 RTL_R32(tp, PHYAR) & 0xffff : ~0;
 941
 942         /*
 943          * According to hardware specs a 20us delay is required after read
 944          * complete indication, but before sending next command.
 945          */
 946         udelay(20);
 947
 948         return value;
 949 }
 950
 951 DECLARE_RTL_COND(rtl_ocpar_cond)
 952 {
 953         return RTL_R32(tp, OCPAR) & OCPAR_FLAG;
 954 }
 955
 956 static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data)
 957 {
 958         RTL_W32(tp, OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
 959         RTL_W32(tp, OCPAR, OCPAR_GPHY_WRITE_CMD);
 960         RTL_W32(tp, EPHY_RXER_NUM, 0);
 961
 962         rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100);
 963 }
 964
 965 static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value)
 966 {
 967         r8168dp_1_mdio_access(tp, reg,
 968                               OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK));
 969 }
 970
 971 static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg)
 972 {
 973         r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD);
 974
 975         mdelay(1);
 976         RTL_W32(tp, OCPAR, OCPAR_GPHY_READ_CMD);
 977         RTL_W32(tp, EPHY_RXER_NUM, 0);
 978
 979         return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ?
 980                 RTL_R32(tp, OCPDR) & OCPDR_DATA_MASK : ~0;
 981 }
 982
 983 #define R8168DP_1_MDIO_ACCESS_BIT       0x00020000
 984
 985 static void r8168dp_2_mdio_start(struct rtl8169_private *tp)
 986 {
 987         RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
 988 }
 989
 990 static void r8168dp_2_mdio_stop(struct rtl8169_private *tp)
 991 {
 992         RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
 993 }
 994
 995 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)
 996 {
 997         r8168dp_2_mdio_start(tp);
 998
 999         r8169_mdio_write(tp, reg, value);
1000
1001         r8168dp_2_mdio_stop(tp);
1002 }
1003
1004 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)
1005 {
1006         int value;
1007
1008         r8168dp_2_mdio_start(tp);
1009
1010         value = r8169_mdio_read(tp, reg);
1011
1012         r8168dp_2_mdio_stop(tp);
1013
1014         return value;
1015 }
1016
1017 static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
1018 {
1019         tp->mdio_ops.write(tp, location, val);
1020 }
1021
1022 static int rtl_readphy(struct rtl8169_private *tp, int location)
1023 {
1024         return tp->mdio_ops.read(tp, location);
1025 }
1026
1027 static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
1028 {
1029         rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
1030 }
1031
1032 static void rtl_w0w1_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
1033 {
1034         int val;
1035
1036         val = rtl_readphy(tp, reg_addr);
1037         rtl_writephy(tp, reg_addr, (val & ~m) | p);
1038 }
1039
1040 DECLARE_RTL_COND(rtl_ephyar_cond)
1041 {
1042         return RTL_R32(tp, EPHYAR) & EPHYAR_FLAG;
1043 }
1044
1045 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)
1046 {
1047         RTL_W32(tp, EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1048                 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1049
1050         rtl_udelay_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);
1051
1052         udelay(10);
1053 }
1054
1055 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)
1056 {
1057         RTL_W32(tp, EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1058
1059         return rtl_udelay_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?
1060                 RTL_R32(tp, EPHYAR) & EPHYAR_DATA_MASK : ~0;
1061 }
1062
1063 DECLARE_RTL_COND(rtl_eriar_cond)
1064 {
1065         return RTL_R32(tp, ERIAR) & ERIAR_FLAG;
1066 }
1067
1068 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1069                           u32 val, int type)
1070 {
1071         BUG_ON((addr & 3) || (mask == 0));
1072         RTL_W32(tp, ERIDR, val);
1073         RTL_W32(tp, ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
1074
1075         rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);
1076 }
1077
1078 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
1079 {
1080         RTL_W32(tp, ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
1081
1082         return rtl_udelay_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?
1083                 RTL_R32(tp, ERIDR) : ~0;
1084 }
1085
1086 static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 mask, u32 p,
1087                          u32 m, int type)
1088 {
1089         u32 val;
1090
1091         val = rtl_eri_read(tp, addr, type);
1092         rtl_eri_write(tp, addr, mask, (val & ~m) | p, type);
1093 }
1094
1095 static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1096 {
1097         RTL_W32(tp, OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1098         return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?
1099                 RTL_R32(tp, OCPDR) : ~0;
1100 }
1101
1102 static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1103 {
1104         return rtl_eri_read(tp, reg, ERIAR_OOB);
1105 }
1106
1107 static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1108                               u32 data)
1109 {
1110         RTL_W32(tp, OCPDR, data);
1111         RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1112         rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);
1113 }
1114
1115 static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1116                               u32 data)
1117 {
1118         rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT,
1119                       data, ERIAR_OOB);
1120 }
1121
1122 static void r8168dp_oob_notify(struct rtl8169_private *tp, u8 cmd)
1123 {
1124         rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd, ERIAR_EXGMAC);
1125
1126         r8168dp_ocp_write(tp, 0x1, 0x30, 0x00000001);
1127 }
1128
1129 #define OOB_CMD_RESET           0x00
1130 #define OOB_CMD_DRIVER_START    0x05
1131 #define OOB_CMD_DRIVER_STOP     0x06
1132
1133 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
1134 {
1135         return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
1136 }
1137
1138 DECLARE_RTL_COND(rtl_dp_ocp_read_cond)
1139 {
1140         u16 reg;
1141
1142         reg = rtl8168_get_ocp_reg(tp);
1143
1144         return r8168dp_ocp_read(tp, 0x0f, reg) & 0x00000800;
1145 }
1146
1147 DECLARE_RTL_COND(rtl_ep_ocp_read_cond)
1148 {
1149         return r8168ep_ocp_read(tp, 0x0f, 0x124) & 0x00000001;
1150 }
1151
1152 DECLARE_RTL_COND(rtl_ocp_tx_cond)
1153 {
1154         return RTL_R8(tp, IBISR0) & 0x20;
1155 }
1156
1157 static void rtl8168ep_stop_cmac(struct rtl8169_private *tp)
1158 {
1159         RTL_W8(tp, IBCR2, RTL_R8(tp, IBCR2) & ~0x01);
1160         rtl_msleep_loop_wait_high(tp, &rtl_ocp_tx_cond, 50, 2000);
1161         RTL_W8(tp, IBISR0, RTL_R8(tp, IBISR0) | 0x20);
1162         RTL_W8(tp, IBCR0, RTL_R8(tp, IBCR0) & ~0x01);
1163 }
1164
1165 static void rtl8168dp_driver_start(struct rtl8169_private *tp)
1166 {
1167         r8168dp_oob_notify(tp, OOB_CMD_DRIVER_START);
1168         rtl_msleep_loop_wait_high(tp, &rtl_dp_ocp_read_cond, 10, 10);
1169 }
1170
1171 static void rtl8168ep_driver_start(struct rtl8169_private *tp)
1172 {
1173         r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START);
1174         r8168ep_ocp_write(tp, 0x01, 0x30,
1175                           r8168ep_ocp_read(tp, 0x01, 0x30) | 0x01);
1176         rtl_msleep_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10, 10);
1177 }
1178
1179 static void rtl8168_driver_start(struct rtl8169_private *tp)
1180 {
1181         switch (tp->mac_version) {
1182         case RTL_GIGA_MAC_VER_27:
1183         case RTL_GIGA_MAC_VER_28:
1184         case RTL_GIGA_MAC_VER_31:
1185                 rtl8168dp_driver_start(tp);
1186                 break;
1187         case RTL_GIGA_MAC_VER_49:
1188         case RTL_GIGA_MAC_VER_50:
1189         case RTL_GIGA_MAC_VER_51:
1190                 rtl8168ep_driver_start(tp);
1191                 break;
1192         default:
1193                 BUG();
1194                 break;
1195         }
1196 }
1197
1198 static void rtl8168dp_driver_stop(struct rtl8169_private *tp)
1199 {
1200         r8168dp_oob_notify(tp, OOB_CMD_DRIVER_STOP);
1201         rtl_msleep_loop_wait_low(tp, &rtl_dp_ocp_read_cond, 10, 10);
1202 }
1203
1204 static void rtl8168ep_driver_stop(struct rtl8169_private *tp)
1205 {
1206         rtl8168ep_stop_cmac(tp);
1207         r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP);
1208         r8168ep_ocp_write(tp, 0x01, 0x30,
1209                           r8168ep_ocp_read(tp, 0x01, 0x30) | 0x01);
1210         rtl_msleep_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10, 10);
1211 }
1212
1213 static void rtl8168_driver_stop(struct rtl8169_private *tp)
1214 {
1215         switch (tp->mac_version) {
1216         case RTL_GIGA_MAC_VER_27:
1217         case RTL_GIGA_MAC_VER_28:
1218         case RTL_GIGA_MAC_VER_31:
1219                 rtl8168dp_driver_stop(tp);
1220                 break;
1221         case RTL_GIGA_MAC_VER_49:
1222         case RTL_GIGA_MAC_VER_50:
1223         case RTL_GIGA_MAC_VER_51:
1224                 rtl8168ep_driver_stop(tp);
1225                 break;
1226         default:
1227                 BUG();
1228                 break;
1229         }
1230 }
1231
1232 static bool r8168dp_check_dash(struct rtl8169_private *tp)
1233 {
1234         u16 reg = rtl8168_get_ocp_reg(tp);
1235
1236         return !!(r8168dp_ocp_read(tp, 0x0f, reg) & 0x00008000);
1237 }
1238
1239 static bool r8168ep_check_dash(struct rtl8169_private *tp)
1240 {
1241         return !!(r8168ep_ocp_read(tp, 0x0f, 0x128) & 0x00000001);
1242 }
1243
1244 static bool r8168_check_dash(struct rtl8169_private *tp)
1245 {
1246         switch (tp->mac_version) {
1247         case RTL_GIGA_MAC_VER_27:
1248         case RTL_GIGA_MAC_VER_28:
1249         case RTL_GIGA_MAC_VER_31:
1250                 return r8168dp_check_dash(tp);
1251         case RTL_GIGA_MAC_VER_49:
1252         case RTL_GIGA_MAC_VER_50:
1253         case RTL_GIGA_MAC_VER_51:
1254                 return r8168ep_check_dash(tp);
1255         default:
1256                 return false;
1257         }
1258 }
1259
1260 struct exgmac_reg {
1261         u16 addr;
1262         u16 mask;
1263         u32 val;
1264 };
1265
1266 static void rtl_write_exgmac_batch(struct rtl8169_private *tp,
1267                                    const struct exgmac_reg *r, int len)
1268 {
1269         while (len-- > 0) {
1270                 rtl_eri_write(tp, r->addr, r->mask, r->val, ERIAR_EXGMAC);
1271                 r++;
1272         }
1273 }
1274
1275 DECLARE_RTL_COND(rtl_efusear_cond)
1276 {
1277         return RTL_R32(tp, EFUSEAR) & EFUSEAR_FLAG;
1278 }
1279
1280 static u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)
1281 {
1282         RTL_W32(tp, EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1283
1284         return rtl_udelay_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?
1285                 RTL_R32(tp, EFUSEAR) & EFUSEAR_DATA_MASK : ~0;
1286 }
1287
1288 static void rtl_ack_events(struct rtl8169_private *tp, u16 bits)
1289 {
1290         RTL_W16(tp, IntrStatus, bits);
1291 }
1292
1293 static void rtl_irq_disable(struct rtl8169_private *tp)
1294 {
1295         RTL_W16(tp, IntrMask, 0);
1296 }
1297
1298 #define RTL_EVENT_NAPI_RX       (RxOK | RxErr)
1299 #define RTL_EVENT_NAPI_TX       (TxOK | TxErr)
1300 #define RTL_EVENT_NAPI          (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX)
1301
1302 static void rtl_irq_enable(struct rtl8169_private *tp)
1303 {
1304         RTL_W16(tp, IntrMask, tp->irq_mask);
1305 }
1306
1307 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1308 {
1309         rtl_irq_disable(tp);
1310         rtl_ack_events(tp, 0xffff);
1311         /* PCI commit */
1312         RTL_R8(tp, ChipCmd);
1313 }
1314
1315 static void rtl_link_chg_patch(struct rtl8169_private *tp)
1316 {
1317         struct net_device *dev = tp->dev;
1318         struct phy_device *phydev = tp->phydev;
1319
1320         if (!netif_running(dev))
1321                 return;
1322
1323         if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
1324             tp->mac_version == RTL_GIGA_MAC_VER_38) {
1325                 if (phydev->speed == SPEED_1000) {
1326                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1327                                       ERIAR_EXGMAC);
1328                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1329                                       ERIAR_EXGMAC);
1330                 } else if (phydev->speed == SPEED_100) {
1331                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1332                                       ERIAR_EXGMAC);
1333                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1334                                       ERIAR_EXGMAC);
1335                 } else {
1336                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1337                                       ERIAR_EXGMAC);
1338                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1339                                       ERIAR_EXGMAC);
1340                 }
1341                 /* Reset packet filter */
1342                 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01,
1343                              ERIAR_EXGMAC);
1344                 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00,
1345                              ERIAR_EXGMAC);
1346         } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1347                    tp->mac_version == RTL_GIGA_MAC_VER_36) {
1348                 if (phydev->speed == SPEED_1000) {
1349                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1350                                       ERIAR_EXGMAC);
1351                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1352                                       ERIAR_EXGMAC);
1353                 } else {
1354                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1355                                       ERIAR_EXGMAC);
1356                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1357                                       ERIAR_EXGMAC);
1358                 }
1359         } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
1360                 if (phydev->speed == SPEED_10) {
1361                         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02,
1362                                       ERIAR_EXGMAC);
1363                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060,
1364                                       ERIAR_EXGMAC);
1365                 } else {
1366                         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000,
1367                                       ERIAR_EXGMAC);
1368                 }
1369         }
1370 }
1371
1372 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1373
1374 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1375 {
1376         struct rtl8169_private *tp = netdev_priv(dev);
1377
1378         rtl_lock_work(tp);
1379         wol->supported = WAKE_ANY;
1380         wol->wolopts = tp->saved_wolopts;
1381         rtl_unlock_work(tp);
1382 }
1383
1384 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1385 {
1386         unsigned int i, tmp;
1387         static const struct {
1388                 u32 opt;
1389                 u16 reg;
1390                 u8  mask;
1391         } cfg[] = {
1392                 { WAKE_PHY,   Config3, LinkUp },
1393                 { WAKE_UCAST, Config5, UWF },
1394                 { WAKE_BCAST, Config5, BWF },
1395                 { WAKE_MCAST, Config5, MWF },
1396                 { WAKE_ANY,   Config5, LanWake },
1397                 { WAKE_MAGIC, Config3, MagicPacket }
1398         };
1399         u8 options;
1400
1401         rtl_unlock_config_regs(tp);
1402
1403         switch (tp->mac_version) {
1404         case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
1405         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
1406                 tmp = ARRAY_SIZE(cfg) - 1;
1407                 if (wolopts & WAKE_MAGIC)
1408                         rtl_w0w1_eri(tp,
1409                                      0x0dc,
1410                                      ERIAR_MASK_0100,
1411                                      MagicPacket_v2,
1412                                      0x0000,
1413                                      ERIAR_EXGMAC);
1414                 else
1415                         rtl_w0w1_eri(tp,
1416                                      0x0dc,
1417                                      ERIAR_MASK_0100,
1418                                      0x0000,
1419                                      MagicPacket_v2,
1420                                      ERIAR_EXGMAC);
1421                 break;
1422         default:
1423                 tmp = ARRAY_SIZE(cfg);
1424                 break;
1425         }
1426
1427         for (i = 0; i < tmp; i++) {
1428                 options = RTL_R8(tp, cfg[i].reg) & ~cfg[i].mask;
1429                 if (wolopts & cfg[i].opt)
1430                         options |= cfg[i].mask;
1431                 RTL_W8(tp, cfg[i].reg, options);
1432         }
1433
1434         switch (tp->mac_version) {
1435         case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_17:
1436                 options = RTL_R8(tp, Config1) & ~PMEnable;
1437                 if (wolopts)
1438                         options |= PMEnable;
1439                 RTL_W8(tp, Config1, options);
1440                 break;
1441         default:
1442                 options = RTL_R8(tp, Config2) & ~PME_SIGNAL;
1443                 if (wolopts)
1444                         options |= PME_SIGNAL;
1445                 RTL_W8(tp, Config2, options);
1446                 break;
1447         }
1448
1449         rtl_lock_config_regs(tp);
1450
1451         device_set_wakeup_enable(tp_to_dev(tp), wolopts);
1452 }
1453
1454 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1455 {
1456         struct rtl8169_private *tp = netdev_priv(dev);
1457         struct device *d = tp_to_dev(tp);
1458
1459         if (wol->wolopts & ~WAKE_ANY)
1460                 return -EINVAL;
1461
1462         pm_runtime_get_noresume(d);
1463
1464         rtl_lock_work(tp);
1465
1466         tp->saved_wolopts = wol->wolopts;
1467
1468         if (pm_runtime_active(d))
1469                 __rtl8169_set_wol(tp, tp->saved_wolopts);
1470
1471         rtl_unlock_work(tp);
1472
1473         pm_runtime_put_noidle(d);
1474
1475         return 0;
1476 }
1477
1478 static void rtl8169_get_drvinfo(struct net_device *dev,
1479                                 struct ethtool_drvinfo *info)
1480 {
1481         struct rtl8169_private *tp = netdev_priv(dev);
1482         struct rtl_fw *rtl_fw = tp->rtl_fw;
1483
1484         strlcpy(info->driver, MODULENAME, sizeof(info->driver));
1485         strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1486         BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
1487         if (rtl_fw)
1488                 strlcpy(info->fw_version, rtl_fw->version,
1489                         sizeof(info->fw_version));
1490 }
1491
1492 static int rtl8169_get_regs_len(struct net_device *dev)
1493 {
1494         return R8169_REGS_SIZE;
1495 }
1496
1497 static netdev_features_t rtl8169_fix_features(struct net_device *dev,
1498         netdev_features_t features)
1499 {
1500         struct rtl8169_private *tp = netdev_priv(dev);
1501
1502         if (dev->mtu > TD_MSS_MAX)
1503                 features &= ~NETIF_F_ALL_TSO;
1504
1505         if (dev->mtu > JUMBO_1K &&
1506             tp->mac_version > RTL_GIGA_MAC_VER_06)
1507                 features &= ~NETIF_F_IP_CSUM;
1508
1509         return features;
1510 }
1511
1512 static int rtl8169_set_features(struct net_device *dev,
1513                                 netdev_features_t features)
1514 {
1515         struct rtl8169_private *tp = netdev_priv(dev);
1516         u32 rx_config;
1517
1518         rtl_lock_work(tp);
1519
1520         rx_config = RTL_R32(tp, RxConfig);
1521         if (features & NETIF_F_RXALL)
1522                 rx_config |= (AcceptErr | AcceptRunt);
1523         else
1524                 rx_config &= ~(AcceptErr | AcceptRunt);
1525
1526         RTL_W32(tp, RxConfig, rx_config);
1527
1528         if (features & NETIF_F_RXCSUM)
1529                 tp->cp_cmd |= RxChkSum;
1530         else
1531                 tp->cp_cmd &= ~RxChkSum;
1532
1533         if (features & NETIF_F_HW_VLAN_CTAG_RX)
1534                 tp->cp_cmd |= RxVlan;
1535         else
1536                 tp->cp_cmd &= ~RxVlan;
1537
1538         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1539         RTL_R16(tp, CPlusCmd);
1540
1541         rtl_unlock_work(tp);
1542
1543         return 0;
1544 }
1545
1546 static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb)
1547 {
1548         return (skb_vlan_tag_present(skb)) ?
1549                 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00;
1550 }
1551
1552 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1553 {
1554         u32 opts2 = le32_to_cpu(desc->opts2);
1555
1556         if (opts2 & RxVlanTag)
1557                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff));
1558 }
1559
1560 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1561                              void *p)
1562 {
1563         struct rtl8169_private *tp = netdev_priv(dev);
1564         u32 __iomem *data = tp->mmio_addr;
1565         u32 *dw = p;
1566         int i;
1567
1568         rtl_lock_work(tp);
1569         for (i = 0; i < R8169_REGS_SIZE; i += 4)
1570                 memcpy_fromio(dw++, data++, 4);
1571         rtl_unlock_work(tp);
1572 }
1573
1574 static u32 rtl8169_get_msglevel(struct net_device *dev)
1575 {
1576         struct rtl8169_private *tp = netdev_priv(dev);
1577
1578         return tp->msg_enable;
1579 }
1580
1581 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1582 {
1583         struct rtl8169_private *tp = netdev_priv(dev);
1584
1585         tp->msg_enable = value;
1586 }
1587
1588 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1589         "tx_packets",
1590         "rx_packets",
1591         "tx_errors",
1592         "rx_errors",
1593         "rx_missed",
1594         "align_errors",
1595         "tx_single_collisions",
1596         "tx_multi_collisions",
1597         "unicast",
1598         "broadcast",
1599         "multicast",
1600         "tx_aborted",
1601         "tx_underrun",
1602 };
1603
1604 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1605 {
1606         switch (sset) {
1607         case ETH_SS_STATS:
1608                 return ARRAY_SIZE(rtl8169_gstrings);
1609         default:
1610                 return -EOPNOTSUPP;
1611         }
1612 }
1613
1614 DECLARE_RTL_COND(rtl_counters_cond)
1615 {
1616         return RTL_R32(tp, CounterAddrLow) & (CounterReset | CounterDump);
1617 }
1618
1619 static bool rtl8169_do_counters(struct rtl8169_private *tp, u32 counter_cmd)
1620 {
1621         dma_addr_t paddr = tp->counters_phys_addr;
1622         u32 cmd;
1623
1624         RTL_W32(tp, CounterAddrHigh, (u64)paddr >> 32);
1625         RTL_R32(tp, CounterAddrHigh);
1626         cmd = (u64)paddr & DMA_BIT_MASK(32);
1627         RTL_W32(tp, CounterAddrLow, cmd);
1628         RTL_W32(tp, CounterAddrLow, cmd | counter_cmd);
1629
1630         return rtl_udelay_loop_wait_low(tp, &rtl_counters_cond, 10, 1000);
1631 }
1632
1633 static bool rtl8169_reset_counters(struct rtl8169_private *tp)
1634 {
1635         /*
1636          * Versions prior to RTL_GIGA_MAC_VER_19 don't support resetting the
1637          * tally counters.
1638          */
1639         if (tp->mac_version < RTL_GIGA_MAC_VER_19)
1640                 return true;
1641
1642         return rtl8169_do_counters(tp, CounterReset);
1643 }
1644
1645 static bool rtl8169_update_counters(struct rtl8169_private *tp)
1646 {
1647         u8 val = RTL_R8(tp, ChipCmd);
1648
1649         /*
1650          * Some chips are unable to dump tally counters when the receiver
1651          * is disabled. If 0xff chip may be in a PCI power-save state.
1652          */
1653         if (!(val & CmdRxEnb) || val == 0xff)
1654                 return true;
1655
1656         return rtl8169_do_counters(tp, CounterDump);
1657 }
1658
1659 static bool rtl8169_init_counter_offsets(struct rtl8169_private *tp)
1660 {
1661         struct rtl8169_counters *counters = tp->counters;
1662         bool ret = false;
1663
1664         /*
1665          * rtl8169_init_counter_offsets is called from rtl_open.  On chip
1666          * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only
1667          * reset by a power cycle, while the counter values collected by the
1668          * driver are reset at every driver unload/load cycle.
1669          *
1670          * To make sure the HW values returned by @get_stats64 match the SW
1671          * values, we collect the initial values at first open(*) and use them
1672          * as offsets to normalize the values returned by @get_stats64.
1673          *
1674          * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one
1675          * for the reason stated in rtl8169_update_counters; CmdRxEnb is only
1676          * set at open time by rtl_hw_start.
1677          */
1678
1679         if (tp->tc_offset.inited)
1680                 return true;
1681
1682         /* If both, reset and update fail, propagate to caller. */
1683         if (rtl8169_reset_counters(tp))
1684                 ret = true;
1685
1686         if (rtl8169_update_counters(tp))
1687                 ret = true;
1688
1689         tp->tc_offset.tx_errors = counters->tx_errors;
1690         tp->tc_offset.tx_multi_collision = counters->tx_multi_collision;
1691         tp->tc_offset.tx_aborted = counters->tx_aborted;
1692         tp->tc_offset.inited = true;
1693
1694         return ret;
1695 }
1696
1697 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1698                                       struct ethtool_stats *stats, u64 *data)
1699 {
1700         struct rtl8169_private *tp = netdev_priv(dev);
1701         struct device *d = tp_to_dev(tp);
1702         struct rtl8169_counters *counters = tp->counters;
1703
1704         ASSERT_RTNL();
1705
1706         pm_runtime_get_noresume(d);
1707
1708         if (pm_runtime_active(d))
1709                 rtl8169_update_counters(tp);
1710
1711         pm_runtime_put_noidle(d);
1712
1713         data[0] = le64_to_cpu(counters->tx_packets);
1714         data[1] = le64_to_cpu(counters->rx_packets);
1715         data[2] = le64_to_cpu(counters->tx_errors);
1716         data[3] = le32_to_cpu(counters->rx_errors);
1717         data[4] = le16_to_cpu(counters->rx_missed);
1718         data[5] = le16_to_cpu(counters->align_errors);
1719         data[6] = le32_to_cpu(counters->tx_one_collision);
1720         data[7] = le32_to_cpu(counters->tx_multi_collision);
1721         data[8] = le64_to_cpu(counters->rx_unicast);
1722         data[9] = le64_to_cpu(counters->rx_broadcast);
1723         data[10] = le32_to_cpu(counters->rx_multicast);
1724         data[11] = le16_to_cpu(counters->tx_aborted);
1725         data[12] = le16_to_cpu(counters->tx_underun);
1726 }
1727
1728 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1729 {
1730         switch(stringset) {
1731         case ETH_SS_STATS:
1732                 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1733                 break;
1734         }
1735 }
1736
1737 /*
1738  * Interrupt coalescing
1739  *
1740  * > 1 - the availability of the IntrMitigate (0xe2) register through the
1741  * >     8169, 8168 and 810x line of chipsets
1742  *
1743  * 8169, 8168, and 8136(810x) serial chipsets support it.
1744  *
1745  * > 2 - the Tx timer unit at gigabit speed
1746  *
1747  * The unit of the timer depends on both the speed and the setting of CPlusCmd
1748  * (0xe0) bit 1 and bit 0.
1749  *
1750  * For 8169
1751  * bit[1:0] \ speed        1000M           100M            10M
1752  * 0 0                     320ns           2.56us          40.96us
1753  * 0 1                     2.56us          20.48us         327.7us
1754  * 1 0                     5.12us          40.96us         655.4us
1755  * 1 1                     10.24us         81.92us         1.31ms
1756  *
1757  * For the other
1758  * bit[1:0] \ speed        1000M           100M            10M
1759  * 0 0                     5us             2.56us          40.96us
1760  * 0 1                     40us            20.48us         327.7us
1761  * 1 0                     80us            40.96us         655.4us
1762  * 1 1                     160us           81.92us         1.31ms
1763  */
1764
1765 /* rx/tx scale factors for one particular CPlusCmd[0:1] value */
1766 struct rtl_coalesce_scale {
1767         /* Rx / Tx */
1768         u32 nsecs[2];
1769 };
1770
1771 /* rx/tx scale factors for all CPlusCmd[0:1] cases */
1772 struct rtl_coalesce_info {
1773         u32 speed;
1774         struct rtl_coalesce_scale scalev[4];    /* each CPlusCmd[0:1] case */
1775 };
1776
1777 /* produce (r,t) pairs with each being in series of *1, *8, *8*2, *8*2*2 */
1778 #define rxtx_x1822(r, t) {              \
1779         {{(r),          (t)}},          \
1780         {{(r)*8,        (t)*8}},        \
1781         {{(r)*8*2,      (t)*8*2}},      \
1782         {{(r)*8*2*2,    (t)*8*2*2}},    \
1783 }
1784 static const struct rtl_coalesce_info rtl_coalesce_info_8169[] = {
1785         /* speed        delays:     rx00   tx00 */
1786         { SPEED_10,     rxtx_x1822(40960, 40960)        },
1787         { SPEED_100,    rxtx_x1822( 2560,  2560)        },
1788         { SPEED_1000,   rxtx_x1822(  320,   320)        },
1789         { 0 },
1790 };
1791
1792 static const struct rtl_coalesce_info rtl_coalesce_info_8168_8136[] = {
1793         /* speed        delays:     rx00   tx00 */
1794         { SPEED_10,     rxtx_x1822(40960, 40960)        },
1795         { SPEED_100,    rxtx_x1822( 2560,  2560)        },
1796         { SPEED_1000,   rxtx_x1822( 5000,  5000)        },
1797         { 0 },
1798 };
1799 #undef rxtx_x1822
1800
1801 /* get rx/tx scale vector corresponding to current speed */
1802 static const struct rtl_coalesce_info *rtl_coalesce_info(struct net_device *dev)
1803 {
1804         struct rtl8169_private *tp = netdev_priv(dev);
1805         struct ethtool_link_ksettings ecmd;
1806         const struct rtl_coalesce_info *ci;
1807         int rc;
1808
1809         rc = phy_ethtool_get_link_ksettings(dev, &ecmd);
1810         if (rc < 0)
1811                 return ERR_PTR(rc);
1812
1813         for (ci = tp->coalesce_info; ci->speed != 0; ci++) {
1814                 if (ecmd.base.speed == ci->speed) {
1815                         return ci;
1816                 }
1817         }
1818
1819         return ERR_PTR(-ELNRNG);
1820 }
1821
1822 static int rtl_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1823 {
1824         struct rtl8169_private *tp = netdev_priv(dev);
1825         const struct rtl_coalesce_info *ci;
1826         const struct rtl_coalesce_scale *scale;
1827         struct {
1828                 u32 *max_frames;
1829                 u32 *usecs;
1830         } coal_settings [] = {
1831                 { &ec->rx_max_coalesced_frames, &ec->rx_coalesce_usecs },
1832                 { &ec->tx_max_coalesced_frames, &ec->tx_coalesce_usecs }
1833         }, *p = coal_settings;
1834         int i;
1835         u16 w;
1836
1837         memset(ec, 0, sizeof(*ec));
1838
1839         /* get rx/tx scale corresponding to current speed and CPlusCmd[0:1] */
1840         ci = rtl_coalesce_info(dev);
1841         if (IS_ERR(ci))
1842                 return PTR_ERR(ci);
1843
1844         scale = &ci->scalev[tp->cp_cmd & INTT_MASK];
1845
1846         /* read IntrMitigate and adjust according to scale */
1847         for (w = RTL_R16(tp, IntrMitigate); w; w >>= RTL_COALESCE_SHIFT, p++) {
1848                 *p->max_frames = (w & RTL_COALESCE_MASK) << 2;
1849                 w >>= RTL_COALESCE_SHIFT;
1850                 *p->usecs = w & RTL_COALESCE_MASK;
1851         }
1852
1853         for (i = 0; i < 2; i++) {
1854                 p = coal_settings + i;
1855                 *p->usecs = (*p->usecs * scale->nsecs[i]) / 1000;
1856
1857                 /*
1858                  * ethtool_coalesce says it is illegal to set both usecs and
1859                  * max_frames to 0.
1860                  */
1861                 if (!*p->usecs && !*p->max_frames)
1862                         *p->max_frames = 1;
1863         }
1864
1865         return 0;
1866 }
1867
1868 /* choose appropriate scale factor and CPlusCmd[0:1] for (speed, nsec) */
1869 static const struct rtl_coalesce_scale *rtl_coalesce_choose_scale(
1870                         struct net_device *dev, u32 nsec, u16 *cp01)
1871 {
1872         const struct rtl_coalesce_info *ci;
1873         u16 i;
1874
1875         ci = rtl_coalesce_info(dev);
1876         if (IS_ERR(ci))
1877                 return ERR_CAST(ci);
1878
1879         for (i = 0; i < 4; i++) {
1880                 u32 rxtx_maxscale = max(ci->scalev[i].nsecs[0],
1881                                         ci->scalev[i].nsecs[1]);
1882                 if (nsec <= rxtx_maxscale * RTL_COALESCE_T_MAX) {
1883                         *cp01 = i;
1884                         return &ci->scalev[i];
1885                 }
1886         }
1887
1888         return ERR_PTR(-EINVAL);
1889 }
1890
1891 static int rtl_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1892 {
1893         struct rtl8169_private *tp = netdev_priv(dev);
1894         const struct rtl_coalesce_scale *scale;
1895         struct {
1896                 u32 frames;
1897                 u32 usecs;
1898         } coal_settings [] = {
1899                 { ec->rx_max_coalesced_frames, ec->rx_coalesce_usecs },
1900                 { ec->tx_max_coalesced_frames, ec->tx_coalesce_usecs }
1901         }, *p = coal_settings;
1902         u16 w = 0, cp01;
1903         int i;
1904
1905         scale = rtl_coalesce_choose_scale(dev,
1906                         max(p[0].usecs, p[1].usecs) * 1000, &cp01);
1907         if (IS_ERR(scale))
1908                 return PTR_ERR(scale);
1909
1910         for (i = 0; i < 2; i++, p++) {
1911                 u32 units;
1912
1913                 /*
1914                  * accept max_frames=1 we returned in rtl_get_coalesce.
1915                  * accept it not only when usecs=0 because of e.g. the following scenario:
1916                  *
1917                  * - both rx_usecs=0 & rx_frames=0 in hardware (no delay on RX)
1918                  * - rtl_get_coalesce returns rx_usecs=0, rx_frames=1
1919                  * - then user does `ethtool -C eth0 rx-usecs 100`
1920                  *
1921                  * since ethtool sends to kernel whole ethtool_coalesce
1922                  * settings, if we do not handle rx_usecs=!0, rx_frames=1
1923                  * we'll reject it below in `frames % 4 != 0`.
1924                  */
1925                 if (p->frames == 1) {
1926                         p->frames = 0;
1927                 }
1928
1929                 units = p->usecs * 1000 / scale->nsecs[i];
1930                 if (p->frames > RTL_COALESCE_FRAME_MAX || p->frames % 4)
1931                         return -EINVAL;
1932
1933                 w <<= RTL_COALESCE_SHIFT;
1934                 w |= units;
1935                 w <<= RTL_COALESCE_SHIFT;
1936                 w |= p->frames >> 2;
1937         }
1938
1939         rtl_lock_work(tp);
1940
1941         RTL_W16(tp, IntrMitigate, swab16(w));
1942
1943         tp->cp_cmd = (tp->cp_cmd & ~INTT_MASK) | cp01;
1944         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1945         RTL_R16(tp, CPlusCmd);
1946
1947         rtl_unlock_work(tp);
1948
1949         return 0;
1950 }
1951
1952 static int rtl_get_eee_supp(struct rtl8169_private *tp)
1953 {
1954         struct phy_device *phydev = tp->phydev;
1955         int ret;
1956
1957         switch (tp->mac_version) {
1958         case RTL_GIGA_MAC_VER_34:
1959         case RTL_GIGA_MAC_VER_35:
1960         case RTL_GIGA_MAC_VER_36:
1961         case RTL_GIGA_MAC_VER_38:
1962                 ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE);
1963                 break;
1964         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
1965                 phy_write(phydev, 0x1f, 0x0a5c);
1966                 ret = phy_read(phydev, 0x12);
1967                 phy_write(phydev, 0x1f, 0x0000);
1968                 break;
1969         default:
1970                 ret = -EPROTONOSUPPORT;
1971                 break;
1972         }
1973
1974         return ret;
1975 }
1976
1977 static int rtl_get_eee_lpadv(struct rtl8169_private *tp)
1978 {
1979         struct phy_device *phydev = tp->phydev;
1980         int ret;
1981
1982         switch (tp->mac_version) {
1983         case RTL_GIGA_MAC_VER_34:
1984         case RTL_GIGA_MAC_VER_35:
1985         case RTL_GIGA_MAC_VER_36:
1986         case RTL_GIGA_MAC_VER_38:
1987                 ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE);
1988                 break;
1989         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
1990                 phy_write(phydev, 0x1f, 0x0a5d);
1991                 ret = phy_read(phydev, 0x11);
1992                 phy_write(phydev, 0x1f, 0x0000);
1993                 break;
1994         default:
1995                 ret = -EPROTONOSUPPORT;
1996                 break;
1997         }
1998
1999         return ret;
2000 }
2001
2002 static int rtl_get_eee_adv(struct rtl8169_private *tp)
2003 {
2004         struct phy_device *phydev = tp->phydev;
2005         int ret;
2006
2007         switch (tp->mac_version) {
2008         case RTL_GIGA_MAC_VER_34:
2009         case RTL_GIGA_MAC_VER_35:
2010         case RTL_GIGA_MAC_VER_36:
2011         case RTL_GIGA_MAC_VER_38:
2012                 ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV);
2013                 break;
2014         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
2015                 phy_write(phydev, 0x1f, 0x0a5d);
2016                 ret = phy_read(phydev, 0x10);
2017                 phy_write(phydev, 0x1f, 0x0000);
2018                 break;
2019         default:
2020                 ret = -EPROTONOSUPPORT;
2021                 break;
2022         }
2023
2024         return ret;
2025 }
2026
2027 static int rtl_set_eee_adv(struct rtl8169_private *tp, int val)
2028 {
2029         struct phy_device *phydev = tp->phydev;
2030         int ret = 0;
2031
2032         switch (tp->mac_version) {
2033         case RTL_GIGA_MAC_VER_34:
2034         case RTL_GIGA_MAC_VER_35:
2035         case RTL_GIGA_MAC_VER_36:
2036         case RTL_GIGA_MAC_VER_38:
2037                 ret = phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);
2038                 break;
2039         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
2040                 phy_write(phydev, 0x1f, 0x0a5d);
2041                 phy_write(phydev, 0x10, val);
2042                 phy_write(phydev, 0x1f, 0x0000);
2043                 break;
2044         default:
2045                 ret = -EPROTONOSUPPORT;
2046                 break;
2047         }
2048
2049         return ret;
2050 }
2051
2052 static int rtl8169_get_eee(struct net_device *dev, struct ethtool_eee *data)
2053 {
2054         struct rtl8169_private *tp = netdev_priv(dev);
2055         struct device *d = tp_to_dev(tp);
2056         int ret;
2057
2058         pm_runtime_get_noresume(d);
2059
2060         if (!pm_runtime_active(d)) {
2061                 ret = -EOPNOTSUPP;
2062                 goto out;
2063         }
2064
2065         /* Get Supported EEE */
2066         ret = rtl_get_eee_supp(tp);
2067         if (ret < 0)
2068                 goto out;
2069         data->supported = mmd_eee_cap_to_ethtool_sup_t(ret);
2070
2071         /* Get advertisement EEE */
2072         ret = rtl_get_eee_adv(tp);
2073         if (ret < 0)
2074                 goto out;
2075         data->advertised = mmd_eee_adv_to_ethtool_adv_t(ret);
2076         data->eee_enabled = !!data->advertised;
2077
2078         /* Get LP advertisement EEE */
2079         ret = rtl_get_eee_lpadv(tp);
2080         if (ret < 0)
2081                 goto out;
2082         data->lp_advertised = mmd_eee_adv_to_ethtool_adv_t(ret);
2083         data->eee_active = !!(data->advertised & data->lp_advertised);
2084 out:
2085         pm_runtime_put_noidle(d);
2086         return ret < 0 ? ret : 0;
2087 }
2088
2089 static int rtl8169_set_eee(struct net_device *dev, struct ethtool_eee *data)
2090 {
2091         struct rtl8169_private *tp = netdev_priv(dev);
2092         struct device *d = tp_to_dev(tp);
2093         int old_adv, adv = 0, cap, ret;
2094
2095         pm_runtime_get_noresume(d);
2096
2097         if (!dev->phydev || !pm_runtime_active(d)) {
2098                 ret = -EOPNOTSUPP;
2099                 goto out;
2100         }
2101
2102         if (dev->phydev->autoneg == AUTONEG_DISABLE ||
2103             dev->phydev->duplex != DUPLEX_FULL) {
2104                 ret = -EPROTONOSUPPORT;
2105                 goto out;
2106         }
2107
2108         /* Get Supported EEE */
2109         ret = rtl_get_eee_supp(tp);
2110         if (ret < 0)
2111                 goto out;
2112         cap = ret;
2113
2114         ret = rtl_get_eee_adv(tp);
2115         if (ret < 0)
2116                 goto out;
2117         old_adv = ret;
2118
2119         if (data->eee_enabled) {
2120                 adv = !data->advertised ? cap :
2121                       ethtool_adv_to_mmd_eee_adv_t(data->advertised) & cap;
2122                 /* Mask prohibited EEE modes */
2123                 adv &= ~dev->phydev->eee_broken_modes;
2124         }
2125
2126         if (old_adv != adv) {
2127                 ret = rtl_set_eee_adv(tp, adv);
2128                 if (ret < 0)
2129                         goto out;
2130
2131                 /* Restart autonegotiation so the new modes get sent to the
2132                  * link partner.
2133                  */
2134                 ret = phy_restart_aneg(dev->phydev);
2135         }
2136
2137 out:
2138         pm_runtime_put_noidle(d);
2139         return ret < 0 ? ret : 0;
2140 }
2141
2142 static const struct ethtool_ops rtl8169_ethtool_ops = {
2143         .get_drvinfo            = rtl8169_get_drvinfo,
2144         .get_regs_len           = rtl8169_get_regs_len,
2145         .get_link               = ethtool_op_get_link,
2146         .get_coalesce           = rtl_get_coalesce,
2147         .set_coalesce           = rtl_set_coalesce,
2148         .get_msglevel           = rtl8169_get_msglevel,
2149         .set_msglevel           = rtl8169_set_msglevel,
2150         .get_regs               = rtl8169_get_regs,
2151         .get_wol                = rtl8169_get_wol,
2152         .set_wol                = rtl8169_set_wol,
2153         .get_strings            = rtl8169_get_strings,
2154         .get_sset_count         = rtl8169_get_sset_count,
2155         .get_ethtool_stats      = rtl8169_get_ethtool_stats,
2156         .get_ts_info            = ethtool_op_get_ts_info,
2157         .nway_reset             = phy_ethtool_nway_reset,
2158         .get_eee                = rtl8169_get_eee,
2159         .set_eee                = rtl8169_set_eee,
2160         .get_link_ksettings     = phy_ethtool_get_link_ksettings,
2161         .set_link_ksettings     = phy_ethtool_set_link_ksettings,
2162 };
2163
2164 static void rtl_enable_eee(struct rtl8169_private *tp)
2165 {
2166         int supported = rtl_get_eee_supp(tp);
2167
2168         if (supported > 0)
2169                 rtl_set_eee_adv(tp, supported);
2170 }
2171
2172 static void rtl8169_get_mac_version(struct rtl8169_private *tp)
2173 {
2174         /*
2175          * The driver currently handles the 8168Bf and the 8168Be identically
2176          * but they can be identified more specifically through the test below
2177          * if needed:
2178          *
2179          * (RTL_R32(tp, TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
2180          *
2181          * Same thing for the 8101Eb and the 8101Ec:
2182          *
2183          * (RTL_R32(tp, TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
2184          */
2185         static const struct rtl_mac_info {
2186                 u16 mask;
2187                 u16 val;
2188                 u16 mac_version;
2189         } mac_info[] = {
2190                 /* 8168EP family. */
2191                 { 0x7cf, 0x502, RTL_GIGA_MAC_VER_51 },
2192                 { 0x7cf, 0x501, RTL_GIGA_MAC_VER_50 },
2193                 { 0x7cf, 0x500, RTL_GIGA_MAC_VER_49 },
2194
2195                 /* 8168H family. */
2196                 { 0x7cf, 0x541, RTL_GIGA_MAC_VER_46 },
2197                 { 0x7cf, 0x540, RTL_GIGA_MAC_VER_45 },
2198
2199                 /* 8168G family. */
2200                 { 0x7cf, 0x5c8, RTL_GIGA_MAC_VER_44 },
2201                 { 0x7cf, 0x509, RTL_GIGA_MAC_VER_42 },
2202                 { 0x7cf, 0x4c1, RTL_GIGA_MAC_VER_41 },
2203                 { 0x7cf, 0x4c0, RTL_GIGA_MAC_VER_40 },
2204
2205                 /* 8168F family. */
2206                 { 0x7c8, 0x488, RTL_GIGA_MAC_VER_38 },
2207                 { 0x7cf, 0x481, RTL_GIGA_MAC_VER_36 },
2208                 { 0x7cf, 0x480, RTL_GIGA_MAC_VER_35 },
2209
2210                 /* 8168E family. */
2211                 { 0x7c8, 0x2c8, RTL_GIGA_MAC_VER_34 },
2212                 { 0x7cf, 0x2c1, RTL_GIGA_MAC_VER_32 },
2213                 { 0x7c8, 0x2c0, RTL_GIGA_MAC_VER_33 },
2214
2215                 /* 8168D family. */
2216                 { 0x7cf, 0x281, RTL_GIGA_MAC_VER_25 },
2217                 { 0x7c8, 0x280, RTL_GIGA_MAC_VER_26 },
2218
2219                 /* 8168DP family. */
2220                 { 0x7cf, 0x288, RTL_GIGA_MAC_VER_27 },
2221                 { 0x7cf, 0x28a, RTL_GIGA_MAC_VER_28 },
2222                 { 0x7cf, 0x28b, RTL_GIGA_MAC_VER_31 },
2223
2224                 /* 8168C family. */
2225                 { 0x7cf, 0x3c9, RTL_GIGA_MAC_VER_23 },
2226                 { 0x7cf, 0x3c8, RTL_GIGA_MAC_VER_18 },
2227                 { 0x7c8, 0x3c8, RTL_GIGA_MAC_VER_24 },
2228                 { 0x7cf, 0x3c0, RTL_GIGA_MAC_VER_19 },
2229                 { 0x7cf, 0x3c2, RTL_GIGA_MAC_VER_20 },
2230                 { 0x7cf, 0x3c3, RTL_GIGA_MAC_VER_21 },
2231                 { 0x7c8, 0x3c0, RTL_GIGA_MAC_VER_22 },
2232
2233                 /* 8168B family. */
2234                 { 0x7cf, 0x380, RTL_GIGA_MAC_VER_12 },
2235                 { 0x7c8, 0x380, RTL_GIGA_MAC_VER_17 },
2236                 { 0x7c8, 0x300, RTL_GIGA_MAC_VER_11 },
2237
2238                 /* 8101 family. */
2239                 { 0x7c8, 0x448, RTL_GIGA_MAC_VER_39 },
2240                 { 0x7c8, 0x440, RTL_GIGA_MAC_VER_37 },
2241                 { 0x7cf, 0x409, RTL_GIGA_MAC_VER_29 },
2242                 { 0x7c8, 0x408, RTL_GIGA_MAC_VER_30 },
2243                 { 0x7cf, 0x349, RTL_GIGA_MAC_VER_08 },
2244                 { 0x7cf, 0x249, RTL_GIGA_MAC_VER_08 },
2245                 { 0x7cf, 0x348, RTL_GIGA_MAC_VER_07 },
2246                 { 0x7cf, 0x248, RTL_GIGA_MAC_VER_07 },
2247                 { 0x7cf, 0x340, RTL_GIGA_MAC_VER_13 },
2248                 { 0x7cf, 0x343, RTL_GIGA_MAC_VER_10 },
2249                 { 0x7cf, 0x342, RTL_GIGA_MAC_VER_16 },
2250                 { 0x7c8, 0x348, RTL_GIGA_MAC_VER_09 },
2251                 { 0x7c8, 0x248, RTL_GIGA_MAC_VER_09 },
2252                 { 0x7c8, 0x340, RTL_GIGA_MAC_VER_16 },
2253                 /* FIXME: where did these entries come from ? -- FR */
2254                 { 0xfc8, 0x388, RTL_GIGA_MAC_VER_15 },
2255                 { 0xfc8, 0x308, RTL_GIGA_MAC_VER_14 },
2256
2257                 /* 8110 family. */
2258                 { 0xfc8, 0x980, RTL_GIGA_MAC_VER_06 },
2259                 { 0xfc8, 0x180, RTL_GIGA_MAC_VER_05 },
2260                 { 0xfc8, 0x100, RTL_GIGA_MAC_VER_04 },
2261                 { 0xfc8, 0x040, RTL_GIGA_MAC_VER_03 },
2262                 { 0xfc8, 0x008, RTL_GIGA_MAC_VER_02 },
2263                 { 0xfc8, 0x000, RTL_GIGA_MAC_VER_01 },
2264
2265                 /* Catch-all */
2266                 { 0x000, 0x000, RTL_GIGA_MAC_NONE   }
2267         };
2268         const struct rtl_mac_info *p = mac_info;
2269         u16 reg = RTL_R32(tp, TxConfig) >> 20;
2270
2271         while ((reg & p->mask) != p->val)
2272                 p++;
2273         tp->mac_version = p->mac_version;
2274
2275         if (tp->mac_version == RTL_GIGA_MAC_NONE) {
2276                 dev_err(tp_to_dev(tp), "unknown chip XID %03x\n", reg & 0xfcf);
2277         } else if (!tp->supports_gmii) {
2278                 if (tp->mac_version == RTL_GIGA_MAC_VER_42)
2279                         tp->mac_version = RTL_GIGA_MAC_VER_43;
2280                 else if (tp->mac_version == RTL_GIGA_MAC_VER_45)
2281                         tp->mac_version = RTL_GIGA_MAC_VER_47;
2282                 else if (tp->mac_version == RTL_GIGA_MAC_VER_46)
2283                         tp->mac_version = RTL_GIGA_MAC_VER_48;
2284         }
2285 }
2286
2287 struct phy_reg {
2288         u16 reg;
2289         u16 val;
2290 };
2291
2292 static void rtl_writephy_batch(struct rtl8169_private *tp,
2293                                const struct phy_reg *regs, int len)
2294 {
2295         while (len-- > 0) {
2296                 rtl_writephy(tp, regs->reg, regs->val);
2297                 regs++;
2298         }
2299 }
2300
2301 #define PHY_READ                0x00000000
2302 #define PHY_DATA_OR             0x10000000
2303 #define PHY_DATA_AND            0x20000000
2304 #define PHY_BJMPN               0x30000000
2305 #define PHY_MDIO_CHG            0x40000000
2306 #define PHY_CLEAR_READCOUNT     0x70000000
2307 #define PHY_WRITE               0x80000000
2308 #define PHY_READCOUNT_EQ_SKIP   0x90000000
2309 #define PHY_COMP_EQ_SKIPN       0xa0000000
2310 #define PHY_COMP_NEQ_SKIPN      0xb0000000
2311 #define PHY_WRITE_PREVIOUS      0xc0000000
2312 #define PHY_SKIPN               0xd0000000
2313 #define PHY_DELAY_MS            0xe0000000
2314
2315 struct fw_info {
2316         u32     magic;
2317         char    version[RTL_VER_SIZE];
2318         __le32  fw_start;
2319         __le32  fw_len;
2320         u8      chksum;
2321 } __packed;
2322
2323 #define FW_OPCODE_SIZE  sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
2324
2325 static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2326 {
2327         const struct firmware *fw = rtl_fw->fw;
2328         struct fw_info *fw_info = (struct fw_info *)fw->data;
2329         struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2330         char *version = rtl_fw->version;
2331         bool rc = false;
2332
2333         if (fw->size < FW_OPCODE_SIZE)
2334                 goto out;
2335
2336         if (!fw_info->magic) {
2337                 size_t i, size, start;
2338                 u8 checksum = 0;
2339
2340                 if (fw->size < sizeof(*fw_info))
2341                         goto out;
2342
2343                 for (i = 0; i < fw->size; i++)
2344                         checksum += fw->data[i];
2345                 if (checksum != 0)
2346                         goto out;
2347
2348                 start = le32_to_cpu(fw_info->fw_start);
2349                 if (start > fw->size)
2350                         goto out;
2351
2352                 size = le32_to_cpu(fw_info->fw_len);
2353                 if (size > (fw->size - start) / FW_OPCODE_SIZE)
2354                         goto out;
2355
2356                 memcpy(version, fw_info->version, RTL_VER_SIZE);
2357
2358                 pa->code = (__le32 *)(fw->data + start);
2359                 pa->size = size;
2360         } else {
2361                 if (fw->size % FW_OPCODE_SIZE)
2362                         goto out;
2363
2364                 strlcpy(version, tp->fw_name, RTL_VER_SIZE);
2365
2366                 pa->code = (__le32 *)fw->data;
2367                 pa->size = fw->size / FW_OPCODE_SIZE;
2368         }
2369         version[RTL_VER_SIZE - 1] = 0;
2370
2371         rc = true;
2372 out:
2373         return rc;
2374 }
2375
2376 static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev,
2377                            struct rtl_fw_phy_action *pa)
2378 {
2379         bool rc = false;
2380         size_t index;
2381
2382         for (index = 0; index < pa->size; index++) {
2383                 u32 action = le32_to_cpu(pa->code[index]);
2384                 u32 regno = (action & 0x0fff0000) >> 16;
2385
2386                 switch(action & 0xf0000000) {
2387                 case PHY_READ:
2388                 case PHY_DATA_OR:
2389                 case PHY_DATA_AND:
2390                 case PHY_MDIO_CHG:
2391                 case PHY_CLEAR_READCOUNT:
2392                 case PHY_WRITE:
2393                 case PHY_WRITE_PREVIOUS:
2394                 case PHY_DELAY_MS:
2395                         break;
2396
2397                 case PHY_BJMPN:
2398                         if (regno > index) {
2399                                 netif_err(tp, ifup, tp->dev,
2400                                           "Out of range of firmware\n");
2401                                 goto out;
2402                         }
2403                         break;
2404                 case PHY_READCOUNT_EQ_SKIP:
2405                         if (index + 2 >= pa->size) {
2406                                 netif_err(tp, ifup, tp->dev,
2407                                           "Out of range of firmware\n");
2408                                 goto out;
2409                         }
2410                         break;
2411                 case PHY_COMP_EQ_SKIPN:
2412                 case PHY_COMP_NEQ_SKIPN:
2413                 case PHY_SKIPN:
2414                         if (index + 1 + regno >= pa->size) {
2415                                 netif_err(tp, ifup, tp->dev,
2416                                           "Out of range of firmware\n");
2417                                 goto out;
2418                         }
2419                         break;
2420
2421                 default:
2422                         netif_err(tp, ifup, tp->dev,
2423                                   "Invalid action 0x%08x\n", action);
2424                         goto out;
2425                 }
2426         }
2427         rc = true;
2428 out:
2429         return rc;
2430 }
2431
2432 static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2433 {
2434         struct net_device *dev = tp->dev;
2435         int rc = -EINVAL;
2436
2437         if (!rtl_fw_format_ok(tp, rtl_fw)) {
2438                 netif_err(tp, ifup, dev, "invalid firmware\n");
2439                 goto out;
2440         }
2441
2442         if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action))
2443                 rc = 0;
2444 out:
2445         return rc;
2446 }
2447
2448 static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2449 {
2450         struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2451         struct mdio_ops org, *ops = &tp->mdio_ops;
2452         u32 predata, count;
2453         size_t index;
2454
2455         predata = count = 0;
2456         org.write = ops->write;
2457         org.read = ops->read;
2458
2459         for (index = 0; index < pa->size; ) {
2460                 u32 action = le32_to_cpu(pa->code[index]);
2461                 u32 data = action & 0x0000ffff;
2462                 u32 regno = (action & 0x0fff0000) >> 16;
2463
2464                 if (!action)
2465                         break;
2466
2467                 switch(action & 0xf0000000) {
2468                 case PHY_READ:
2469                         predata = rtl_readphy(tp, regno);
2470                         count++;
2471                         index++;
2472                         break;
2473                 case PHY_DATA_OR:
2474                         predata |= data;
2475                         index++;
2476                         break;
2477                 case PHY_DATA_AND:
2478                         predata &= data;
2479                         index++;
2480                         break;
2481                 case PHY_BJMPN:
2482                         index -= regno;
2483                         break;
2484                 case PHY_MDIO_CHG:
2485                         if (data == 0) {
2486                                 ops->write = org.write;
2487                                 ops->read = org.read;
2488                         } else if (data == 1) {
2489                                 ops->write = mac_mcu_write;
2490                                 ops->read = mac_mcu_read;
2491                         }
2492
2493                         index++;
2494                         break;
2495                 case PHY_CLEAR_READCOUNT:
2496                         count = 0;
2497                         index++;
2498                         break;
2499                 case PHY_WRITE:
2500                         rtl_writephy(tp, regno, data);
2501                         index++;
2502                         break;
2503                 case PHY_READCOUNT_EQ_SKIP:
2504                         index += (count == data) ? 2 : 1;
2505                         break;
2506                 case PHY_COMP_EQ_SKIPN:
2507                         if (predata == data)
2508                                 index += regno;
2509                         index++;
2510                         break;
2511                 case PHY_COMP_NEQ_SKIPN:
2512                         if (predata != data)
2513                                 index += regno;
2514                         index++;
2515                         break;
2516                 case PHY_WRITE_PREVIOUS:
2517                         rtl_writephy(tp, regno, predata);
2518                         index++;
2519                         break;
2520                 case PHY_SKIPN:
2521                         index += regno + 1;
2522                         break;
2523                 case PHY_DELAY_MS:
2524                         mdelay(data);
2525                         index++;
2526                         break;
2527
2528                 default:
2529                         BUG();
2530                 }
2531         }
2532
2533         ops->write = org.write;
2534         ops->read = org.read;
2535 }
2536
2537 static void rtl_release_firmware(struct rtl8169_private *tp)
2538 {
2539         if (tp->rtl_fw) {
2540                 release_firmware(tp->rtl_fw->fw);
2541                 kfree(tp->rtl_fw);
2542                 tp->rtl_fw = NULL;
2543         }
2544 }
2545
2546 static void rtl_apply_firmware(struct rtl8169_private *tp)
2547 {
2548         /* TODO: release firmware once rtl_phy_write_fw signals failures. */
2549         if (tp->rtl_fw)
2550                 rtl_phy_write_fw(tp, tp->rtl_fw);
2551 }
2552
2553 static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
2554 {
2555         if (rtl_readphy(tp, reg) != val)
2556                 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
2557         else
2558                 rtl_apply_firmware(tp);
2559 }
2560
2561 static void rtl8168_config_eee_mac(struct rtl8169_private *tp)
2562 {
2563         rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_1111, 0x0003, 0x0000, ERIAR_EXGMAC);
2564 }
2565
2566 static void rtl8168f_config_eee_phy(struct rtl8169_private *tp)
2567 {
2568         struct phy_device *phydev = tp->phydev;
2569
2570         phy_write(phydev, 0x1f, 0x0007);
2571         phy_write(phydev, 0x1e, 0x0020);
2572         phy_set_bits(phydev, 0x15, BIT(8));
2573
2574         phy_write(phydev, 0x1f, 0x0005);
2575         phy_write(phydev, 0x05, 0x8b85);
2576         phy_set_bits(phydev, 0x06, BIT(13));
2577
2578         phy_write(phydev, 0x1f, 0x0000);
2579 }
2580
2581 static void rtl8168g_config_eee_phy(struct rtl8169_private *tp)
2582 {
2583         phy_write(tp->phydev, 0x1f, 0x0a43);
2584         phy_set_bits(tp->phydev, 0x11, BIT(4));
2585         phy_write(tp->phydev, 0x1f, 0x0000);
2586 }
2587
2588 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
2589 {
2590         static const struct phy_reg phy_reg_init[] = {
2591                 { 0x1f, 0x0001 },
2592                 { 0x06, 0x006e },
2593                 { 0x08, 0x0708 },
2594                 { 0x15, 0x4000 },
2595                 { 0x18, 0x65c7 },
2596
2597                 { 0x1f, 0x0001 },
2598                 { 0x03, 0x00a1 },
2599                 { 0x02, 0x0008 },
2600                 { 0x01, 0x0120 },
2601                 { 0x00, 0x1000 },
2602                 { 0x04, 0x0800 },
2603                 { 0x04, 0x0000 },
2604
2605                 { 0x03, 0xff41 },
2606                 { 0x02, 0xdf60 },
2607                 { 0x01, 0x0140 },
2608                 { 0x00, 0x0077 },
2609                 { 0x04, 0x7800 },
2610                 { 0x04, 0x7000 },
2611
2612                 { 0x03, 0x802f },
2613                 { 0x02, 0x4f02 },
2614                 { 0x01, 0x0409 },
2615                 { 0x00, 0xf0f9 },
2616                 { 0x04, 0x9800 },
2617                 { 0x04, 0x9000 },
2618
2619                 { 0x03, 0xdf01 },
2620                 { 0x02, 0xdf20 },
2621                 { 0x01, 0xff95 },
2622                 { 0x00, 0xba00 },
2623                 { 0x04, 0xa800 },
2624                 { 0x04, 0xa000 },
2625
2626                 { 0x03, 0xff41 },
2627                 { 0x02, 0xdf20 },
2628                 { 0x01, 0x0140 },
2629                 { 0x00, 0x00bb },
2630                 { 0x04, 0xb800 },
2631                 { 0x04, 0xb000 },
2632
2633                 { 0x03, 0xdf41 },
2634                 { 0x02, 0xdc60 },
2635                 { 0x01, 0x6340 },
2636                 { 0x00, 0x007d },
2637                 { 0x04, 0xd800 },
2638                 { 0x04, 0xd000 },
2639
2640                 { 0x03, 0xdf01 },
2641                 { 0x02, 0xdf20 },
2642                 { 0x01, 0x100a },
2643                 { 0x00, 0xa0ff },
2644                 { 0x04, 0xf800 },
2645                 { 0x04, 0xf000 },
2646
2647                 { 0x1f, 0x0000 },
2648                 { 0x0b, 0x0000 },
2649                 { 0x00, 0x9200 }
2650         };
2651
2652         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2653 }
2654
2655 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
2656 {
2657         static const struct phy_reg phy_reg_init[] = {
2658                 { 0x1f, 0x0002 },
2659                 { 0x01, 0x90d0 },
2660                 { 0x1f, 0x0000 }
2661         };
2662
2663         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2664 }
2665
2666 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2667 {
2668         struct pci_dev *pdev = tp->pci_dev;
2669
2670         if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
2671             (pdev->subsystem_device != 0xe000))
2672                 return;
2673
2674         rtl_writephy(tp, 0x1f, 0x0001);
2675         rtl_writephy(tp, 0x10, 0xf01b);
2676         rtl_writephy(tp, 0x1f, 0x0000);
2677 }
2678
2679 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2680 {
2681         static const struct phy_reg phy_reg_init[] = {
2682                 { 0x1f, 0x0001 },
2683                 { 0x04, 0x0000 },
2684                 { 0x03, 0x00a1 },
2685                 { 0x02, 0x0008 },
2686                 { 0x01, 0x0120 },
2687                 { 0x00, 0x1000 },
2688                 { 0x04, 0x0800 },
2689                 { 0x04, 0x9000 },
2690                 { 0x03, 0x802f },
2691                 { 0x02, 0x4f02 },
2692                 { 0x01, 0x0409 },
2693                 { 0x00, 0xf099 },
2694                 { 0x04, 0x9800 },
2695                 { 0x04, 0xa000 },
2696                 { 0x03, 0xdf01 },
2697                 { 0x02, 0xdf20 },
2698                 { 0x01, 0xff95 },
2699                 { 0x00, 0xba00 },
2700                 { 0x04, 0xa800 },
2701                 { 0x04, 0xf000 },
2702                 { 0x03, 0xdf01 },
2703                 { 0x02, 0xdf20 },
2704                 { 0x01, 0x101a },
2705                 { 0x00, 0xa0ff },
2706                 { 0x04, 0xf800 },
2707                 { 0x04, 0x0000 },
2708                 { 0x1f, 0x0000 },
2709
2710                 { 0x1f, 0x0001 },
2711                 { 0x10, 0xf41b },
2712                 { 0x14, 0xfb54 },
2713                 { 0x18, 0xf5c7 },
2714                 { 0x1f, 0x0000 },
2715
2716                 { 0x1f, 0x0001 },
2717                 { 0x17, 0x0cc0 },
2718                 { 0x1f, 0x0000 }
2719         };
2720
2721         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2722
2723         rtl8169scd_hw_phy_config_quirk(tp);
2724 }
2725
2726 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
2727 {
2728         static const struct phy_reg phy_reg_init[] = {
2729                 { 0x1f, 0x0001 },
2730                 { 0x04, 0x0000 },
2731                 { 0x03, 0x00a1 },
2732                 { 0x02, 0x0008 },
2733                 { 0x01, 0x0120 },
2734                 { 0x00, 0x1000 },
2735                 { 0x04, 0x0800 },
2736                 { 0x04, 0x9000 },
2737                 { 0x03, 0x802f },
2738                 { 0x02, 0x4f02 },
2739                 { 0x01, 0x0409 },
2740                 { 0x00, 0xf099 },
2741                 { 0x04, 0x9800 },
2742                 { 0x04, 0xa000 },
2743                 { 0x03, 0xdf01 },
2744                 { 0x02, 0xdf20 },
2745                 { 0x01, 0xff95 },
2746                 { 0x00, 0xba00 },
2747                 { 0x04, 0xa800 },
2748                 { 0x04, 0xf000 },
2749                 { 0x03, 0xdf01 },
2750                 { 0x02, 0xdf20 },
2751                 { 0x01, 0x101a },
2752                 { 0x00, 0xa0ff },
2753                 { 0x04, 0xf800 },
2754                 { 0x04, 0x0000 },
2755                 { 0x1f, 0x0000 },
2756
2757                 { 0x1f, 0x0001 },
2758                 { 0x0b, 0x8480 },
2759                 { 0x1f, 0x0000 },
2760
2761                 { 0x1f, 0x0001 },
2762                 { 0x18, 0x67c7 },
2763                 { 0x04, 0x2000 },
2764                 { 0x03, 0x002f },
2765                 { 0x02, 0x4360 },
2766                 { 0x01, 0x0109 },
2767                 { 0x00, 0x3022 },
2768                 { 0x04, 0x2800 },
2769                 { 0x1f, 0x0000 },
2770
2771                 { 0x1f, 0x0001 },
2772                 { 0x17, 0x0cc0 },
2773                 { 0x1f, 0x0000 }
2774         };
2775
2776         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2777 }
2778
2779 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
2780 {
2781         static const struct phy_reg phy_reg_init[] = {
2782                 { 0x10, 0xf41b },
2783                 { 0x1f, 0x0000 }
2784         };
2785
2786         rtl_writephy(tp, 0x1f, 0x0001);
2787         rtl_patchphy(tp, 0x16, 1 << 0);
2788
2789         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2790 }
2791
2792 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
2793 {
2794         static const struct phy_reg phy_reg_init[] = {
2795                 { 0x1f, 0x0001 },
2796                 { 0x10, 0xf41b },
2797                 { 0x1f, 0x0000 }
2798         };
2799
2800         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2801 }
2802
2803 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
2804 {
2805         static const struct phy_reg phy_reg_init[] = {
2806                 { 0x1f, 0x0000 },
2807                 { 0x1d, 0x0f00 },
2808                 { 0x1f, 0x0002 },
2809                 { 0x0c, 0x1ec8 },
2810                 { 0x1f, 0x0000 }
2811         };
2812
2813         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2814 }
2815
2816 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
2817 {
2818         static const struct phy_reg phy_reg_init[] = {
2819                 { 0x1f, 0x0001 },
2820                 { 0x1d, 0x3d98 },
2821                 { 0x1f, 0x0000 }
2822         };
2823
2824         rtl_writephy(tp, 0x1f, 0x0000);
2825         rtl_patchphy(tp, 0x14, 1 << 5);
2826         rtl_patchphy(tp, 0x0d, 1 << 5);
2827
2828         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2829 }
2830
2831 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
2832 {
2833         static const struct phy_reg phy_reg_init[] = {
2834                 { 0x1f, 0x0001 },
2835                 { 0x12, 0x2300 },
2836                 { 0x1f, 0x0002 },
2837                 { 0x00, 0x88d4 },
2838                 { 0x01, 0x82b1 },
2839                 { 0x03, 0x7002 },
2840                 { 0x08, 0x9e30 },
2841                 { 0x09, 0x01f0 },
2842                 { 0x0a, 0x5500 },
2843                 { 0x0c, 0x00c8 },
2844                 { 0x1f, 0x0003 },
2845                 { 0x12, 0xc096 },
2846                 { 0x16, 0x000a },
2847                 { 0x1f, 0x0000 },
2848                 { 0x1f, 0x0000 },
2849                 { 0x09, 0x2000 },
2850                 { 0x09, 0x0000 }
2851         };
2852
2853         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2854
2855         rtl_patchphy(tp, 0x14, 1 << 5);
2856         rtl_patchphy(tp, 0x0d, 1 << 5);
2857         rtl_writephy(tp, 0x1f, 0x0000);
2858 }
2859
2860 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
2861 {
2862         static const struct phy_reg phy_reg_init[] = {
2863                 { 0x1f, 0x0001 },
2864                 { 0x12, 0x2300 },
2865                 { 0x03, 0x802f },
2866                 { 0x02, 0x4f02 },
2867                 { 0x01, 0x0409 },
2868                 { 0x00, 0xf099 },
2869                 { 0x04, 0x9800 },
2870                 { 0x04, 0x9000 },
2871                 { 0x1d, 0x3d98 },
2872                 { 0x1f, 0x0002 },
2873                 { 0x0c, 0x7eb8 },
2874                 { 0x06, 0x0761 },
2875                 { 0x1f, 0x0003 },
2876                 { 0x16, 0x0f0a },
2877                 { 0x1f, 0x0000 }
2878         };
2879
2880         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2881
2882         rtl_patchphy(tp, 0x16, 1 << 0);
2883         rtl_patchphy(tp, 0x14, 1 << 5);
2884         rtl_patchphy(tp, 0x0d, 1 << 5);
2885         rtl_writephy(tp, 0x1f, 0x0000);
2886 }
2887
2888 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
2889 {
2890         static const struct phy_reg phy_reg_init[] = {
2891                 { 0x1f, 0x0001 },
2892                 { 0x12, 0x2300 },
2893                 { 0x1d, 0x3d98 },
2894                 { 0x1f, 0x0002 },
2895                 { 0x0c, 0x7eb8 },
2896                 { 0x06, 0x5461 },
2897                 { 0x1f, 0x0003 },
2898                 { 0x16, 0x0f0a },
2899                 { 0x1f, 0x0000 }
2900         };
2901
2902         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2903
2904         rtl_patchphy(tp, 0x16, 1 << 0);
2905         rtl_patchphy(tp, 0x14, 1 << 5);
2906         rtl_patchphy(tp, 0x0d, 1 << 5);
2907         rtl_writephy(tp, 0x1f, 0x0000);
2908 }
2909
2910 static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
2911 {
2912         rtl8168c_3_hw_phy_config(tp);
2913 }
2914
2915 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
2916 {
2917         static const struct phy_reg phy_reg_init_0[] = {
2918                 /* Channel Estimation */
2919                 { 0x1f, 0x0001 },
2920                 { 0x06, 0x4064 },
2921                 { 0x07, 0x2863 },
2922                 { 0x08, 0x059c },
2923                 { 0x09, 0x26b4 },
2924                 { 0x0a, 0x6a19 },
2925                 { 0x0b, 0xdcc8 },
2926                 { 0x10, 0xf06d },
2927                 { 0x14, 0x7f68 },
2928                 { 0x18, 0x7fd9 },
2929                 { 0x1c, 0xf0ff },
2930                 { 0x1d, 0x3d9c },
2931                 { 0x1f, 0x0003 },
2932                 { 0x12, 0xf49f },
2933                 { 0x13, 0x070b },
2934                 { 0x1a, 0x05ad },
2935                 { 0x14, 0x94c0 },
2936
2937                 /*
2938                  * Tx Error Issue
2939                  * Enhance line driver power
2940                  */
2941                 { 0x1f, 0x0002 },
2942                 { 0x06, 0x5561 },
2943                 { 0x1f, 0x0005 },
2944                 { 0x05, 0x8332 },
2945                 { 0x06, 0x5561 },
2946
2947                 /*
2948                  * Can not link to 1Gbps with bad cable
2949                  * Decrease SNR threshold form 21.07dB to 19.04dB
2950                  */
2951                 { 0x1f, 0x0001 },
2952                 { 0x17, 0x0cc0 },
2953
2954                 { 0x1f, 0x0000 },
2955                 { 0x0d, 0xf880 }
2956         };
2957
2958         rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2959
2960         /*
2961          * Rx Error Issue
2962          * Fine Tune Switching regulator parameter
2963          */
2964         rtl_writephy(tp, 0x1f, 0x0002);
2965         rtl_w0w1_phy(tp, 0x0b, 0x0010, 0x00ef);
2966         rtl_w0w1_phy(tp, 0x0c, 0xa200, 0x5d00);
2967
2968         if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
2969                 static const struct phy_reg phy_reg_init[] = {
2970                         { 0x1f, 0x0002 },
2971                         { 0x05, 0x669a },
2972                         { 0x1f, 0x0005 },
2973                         { 0x05, 0x8330 },
2974                         { 0x06, 0x669a },
2975                         { 0x1f, 0x0002 }
2976                 };
2977                 int val;
2978
2979                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2980
2981                 val = rtl_readphy(tp, 0x0d);
2982
2983                 if ((val & 0x00ff) != 0x006c) {
2984                         static const u32 set[] = {
2985                                 0x0065, 0x0066, 0x0067, 0x0068,
2986                                 0x0069, 0x006a, 0x006b, 0x006c
2987                         };
2988                         int i;
2989
2990                         rtl_writephy(tp, 0x1f, 0x0002);
2991
2992                         val &= 0xff00;
2993                         for (i = 0; i < ARRAY_SIZE(set); i++)
2994                                 rtl_writephy(tp, 0x0d, val | set[i]);
2995                 }
2996         } else {
2997                 static const struct phy_reg phy_reg_init[] = {
2998                         { 0x1f, 0x0002 },
2999                         { 0x05, 0x6662 },
3000                         { 0x1f, 0x0005 },
3001                         { 0x05, 0x8330 },
3002                         { 0x06, 0x6662 }
3003                 };
3004
3005                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3006         }
3007
3008         /* RSET couple improve */
3009         rtl_writephy(tp, 0x1f, 0x0002);
3010         rtl_patchphy(tp, 0x0d, 0x0300);
3011         rtl_patchphy(tp, 0x0f, 0x0010);
3012
3013         /* Fine tune PLL performance */
3014         rtl_writephy(tp, 0x1f, 0x0002);
3015         rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
3016         rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
3017
3018         rtl_writephy(tp, 0x1f, 0x0005);
3019         rtl_writephy(tp, 0x05, 0x001b);
3020
3021         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
3022
3023         rtl_writephy(tp, 0x1f, 0x0000);
3024 }
3025
3026 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
3027 {
3028         static const struct phy_reg phy_reg_init_0[] = {
3029                 /* Channel Estimation */
3030                 { 0x1f, 0x0001 },
3031                 { 0x06, 0x4064 },
3032                 { 0x07, 0x2863 },
3033                 { 0x08, 0x059c },
3034                 { 0x09, 0x26b4 },
3035                 { 0x0a, 0x6a19 },
3036                 { 0x0b, 0xdcc8 },
3037                 { 0x10, 0xf06d },
3038                 { 0x14, 0x7f68 },
3039                 { 0x18, 0x7fd9 },
3040                 { 0x1c, 0xf0ff },
3041                 { 0x1d, 0x3d9c },
3042                 { 0x1f, 0x0003 },
3043                 { 0x12, 0xf49f },
3044                 { 0x13, 0x070b },
3045                 { 0x1a, 0x05ad },
3046                 { 0x14, 0x94c0 },
3047
3048                 /*
3049                  * Tx Error Issue
3050                  * Enhance line driver power
3051                  */
3052                 { 0x1f, 0x0002 },
3053                 { 0x06, 0x5561 },
3054                 { 0x1f, 0x0005 },
3055                 { 0x05, 0x8332 },
3056                 { 0x06, 0x5561 },
3057
3058                 /*
3059                  * Can not link to 1Gbps with bad cable
3060                  * Decrease SNR threshold form 21.07dB to 19.04dB
3061                  */
3062                 { 0x1f, 0x0001 },
3063                 { 0x17, 0x0cc0 },
3064
3065                 { 0x1f, 0x0000 },
3066                 { 0x0d, 0xf880 }
3067         };
3068
3069         rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
3070
3071         if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
3072                 static const struct phy_reg phy_reg_init[] = {
3073                         { 0x1f, 0x0002 },
3074                         { 0x05, 0x669a },
3075                         { 0x1f, 0x0005 },
3076                         { 0x05, 0x8330 },
3077                         { 0x06, 0x669a },
3078
3079                         { 0x1f, 0x0002 }
3080                 };
3081                 int val;
3082
3083                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3084
3085                 val = rtl_readphy(tp, 0x0d);
3086                 if ((val & 0x00ff) != 0x006c) {
3087                         static const u32 set[] = {
3088                                 0x0065, 0x0066, 0x0067, 0x0068,
3089                                 0x0069, 0x006a, 0x006b, 0x006c
3090                         };
3091                         int i;
3092
3093                         rtl_writephy(tp, 0x1f, 0x0002);
3094
3095                         val &= 0xff00;
3096                         for (i = 0; i < ARRAY_SIZE(set); i++)
3097                                 rtl_writephy(tp, 0x0d, val | set[i]);
3098                 }
3099         } else {
3100                 static const struct phy_reg phy_reg_init[] = {
3101                         { 0x1f, 0x0002 },
3102                         { 0x05, 0x2642 },
3103                         { 0x1f, 0x0005 },
3104                         { 0x05, 0x8330 },
3105                         { 0x06, 0x2642 }
3106                 };
3107
3108                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3109         }
3110
3111         /* Fine tune PLL performance */
3112         rtl_writephy(tp, 0x1f, 0x0002);
3113         rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
3114         rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
3115
3116         /* Switching regulator Slew rate */
3117         rtl_writephy(tp, 0x1f, 0x0002);
3118         rtl_patchphy(tp, 0x0f, 0x0017);
3119
3120         rtl_writephy(tp, 0x1f, 0x0005);
3121         rtl_writephy(tp, 0x05, 0x001b);
3122
3123         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
3124
3125         rtl_writephy(tp, 0x1f, 0x0000);
3126 }
3127
3128 static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
3129 {
3130         static const struct phy_reg phy_reg_init[] = {
3131                 { 0x1f, 0x0002 },
3132                 { 0x10, 0x0008 },
3133                 { 0x0d, 0x006c },
3134
3135                 { 0x1f, 0x0000 },
3136                 { 0x0d, 0xf880 },
3137
3138                 { 0x1f, 0x0001 },
3139                 { 0x17, 0x0cc0 },
3140
3141                 { 0x1f, 0x0001 },
3142                 { 0x0b, 0xa4d8 },
3143                 { 0x09, 0x281c },
3144                 { 0x07, 0x2883 },
3145                 { 0x0a, 0x6b35 },
3146                 { 0x1d, 0x3da4 },
3147                 { 0x1c, 0xeffd },
3148                 { 0x14, 0x7f52 },
3149                 { 0x18, 0x7fc6 },
3150                 { 0x08, 0x0601 },
3151                 { 0x06, 0x4063 },
3152                 { 0x10, 0xf074 },
3153                 { 0x1f, 0x0003 },
3154                 { 0x13, 0x0789 },
3155                 { 0x12, 0xf4bd },
3156                 { 0x1a, 0x04fd },
3157                 { 0x14, 0x84b0 },
3158                 { 0x1f, 0x0000 },
3159                 { 0x00, 0x9200 },
3160
3161                 { 0x1f, 0x0005 },
3162                 { 0x01, 0x0340 },
3163                 { 0x1f, 0x0001 },
3164                 { 0x04, 0x4000 },
3165                 { 0x03, 0x1d21 },
3166                 { 0x02, 0x0c32 },
3167                 { 0x01, 0x0200 },
3168                 { 0x00, 0x5554 },
3169                 { 0x04, 0x4800 },
3170                 { 0x04, 0x4000 },
3171                 { 0x04, 0xf000 },
3172                 { 0x03, 0xdf01 },
3173                 { 0x02, 0xdf20 },
3174                 { 0x01, 0x101a },
3175                 { 0x00, 0xa0ff },
3176                 { 0x04, 0xf800 },
3177                 { 0x04, 0xf000 },
3178                 { 0x1f, 0x0000 },
3179
3180                 { 0x1f, 0x0007 },
3181                 { 0x1e, 0x0023 },
3182                 { 0x16, 0x0000 },
3183                 { 0x1f, 0x0000 }
3184         };
3185
3186         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3187 }
3188
3189 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
3190 {
3191         static const struct phy_reg phy_reg_init[] = {
3192                 { 0x1f, 0x0001 },
3193                 { 0x17, 0x0cc0 },
3194
3195                 { 0x1f, 0x0007 },
3196                 { 0x1e, 0x002d },
3197                 { 0x18, 0x0040 },
3198                 { 0x1f, 0x0000 }
3199         };
3200
3201         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3202         rtl_patchphy(tp, 0x0d, 1 << 5);
3203 }
3204
3205 static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
3206 {
3207         static const struct phy_reg phy_reg_init[] = {
3208                 /* Enable Delay cap */
3209                 { 0x1f, 0x0005 },
3210                 { 0x05, 0x8b80 },
3211                 { 0x06, 0xc896 },
3212                 { 0x1f, 0x0000 },
3213
3214                 /* Channel estimation fine tune */
3215                 { 0x1f, 0x0001 },
3216                 { 0x0b, 0x6c20 },
3217                 { 0x07, 0x2872 },
3218                 { 0x1c, 0xefff },
3219                 { 0x1f, 0x0003 },
3220                 { 0x14, 0x6420 },
3221                 { 0x1f, 0x0000 },
3222
3223                 /* Update PFM & 10M TX idle timer */
3224                 { 0x1f, 0x0007 },
3225                 { 0x1e, 0x002f },
3226                 { 0x15, 0x1919 },
3227                 { 0x1f, 0x0000 },
3228
3229                 { 0x1f, 0x0007 },
3230                 { 0x1e, 0x00ac },
3231                 { 0x18, 0x0006 },
3232                 { 0x1f, 0x0000 }
3233         };
3234
3235         rtl_apply_firmware(tp);
3236
3237         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3238
3239         /* DCO enable for 10M IDLE Power */
3240         rtl_writephy(tp, 0x1f, 0x0007);
3241         rtl_writephy(tp, 0x1e, 0x0023);
3242         rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
3243         rtl_writephy(tp, 0x1f, 0x0000);
3244
3245         /* For impedance matching */
3246         rtl_writephy(tp, 0x1f, 0x0002);
3247         rtl_w0w1_phy(tp, 0x08, 0x8000, 0x7f00);
3248         rtl_writephy(tp, 0x1f, 0x0000);
3249
3250         /* PHY auto speed down */
3251         rtl_writephy(tp, 0x1f, 0x0007);
3252         rtl_writephy(tp, 0x1e, 0x002d);
3253         rtl_w0w1_phy(tp, 0x18, 0x0050, 0x0000);
3254         rtl_writephy(tp, 0x1f, 0x0000);
3255         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3256
3257         rtl_writephy(tp, 0x1f, 0x0005);
3258         rtl_writephy(tp, 0x05, 0x8b86);
3259         rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3260         rtl_writephy(tp, 0x1f, 0x0000);
3261
3262         rtl_writephy(tp, 0x1f, 0x0005);
3263         rtl_writephy(tp, 0x05, 0x8b85);
3264         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
3265         rtl_writephy(tp, 0x1f, 0x0007);
3266         rtl_writephy(tp, 0x1e, 0x0020);
3267         rtl_w0w1_phy(tp, 0x15, 0x0000, 0x1100);
3268         rtl_writephy(tp, 0x1f, 0x0006);
3269         rtl_writephy(tp, 0x00, 0x5a00);
3270         rtl_writephy(tp, 0x1f, 0x0000);
3271         rtl_writephy(tp, 0x0d, 0x0007);
3272         rtl_writephy(tp, 0x0e, 0x003c);
3273         rtl_writephy(tp, 0x0d, 0x4007);
3274         rtl_writephy(tp, 0x0e, 0x0000);
3275         rtl_writephy(tp, 0x0d, 0x0000);
3276 }
3277
3278 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, u8 *addr)
3279 {
3280         const u16 w[] = {
3281                 addr[0] | (addr[1] << 8),
3282                 addr[2] | (addr[3] << 8),
3283                 addr[4] | (addr[5] << 8)
3284         };
3285         const struct exgmac_reg e[] = {
3286                 { .addr = 0xe0, ERIAR_MASK_1111, .val = w[0] | (w[1] << 16) },
3287                 { .addr = 0xe4, ERIAR_MASK_1111, .val = w[2] },
3288                 { .addr = 0xf0, ERIAR_MASK_1111, .val = w[0] << 16 },
3289                 { .addr = 0xf4, ERIAR_MASK_1111, .val = w[1] | (w[2] << 16) }
3290         };
3291
3292         rtl_write_exgmac_batch(tp, e, ARRAY_SIZE(e));
3293 }
3294
3295 static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
3296 {
3297         static const struct phy_reg phy_reg_init[] = {
3298                 /* Enable Delay cap */
3299                 { 0x1f, 0x0004 },
3300                 { 0x1f, 0x0007 },
3301                 { 0x1e, 0x00ac },
3302                 { 0x18, 0x0006 },
3303                 { 0x1f, 0x0002 },
3304                 { 0x1f, 0x0000 },
3305                 { 0x1f, 0x0000 },
3306
3307                 /* Channel estimation fine tune */
3308                 { 0x1f, 0x0003 },
3309                 { 0x09, 0xa20f },
3310                 { 0x1f, 0x0000 },
3311                 { 0x1f, 0x0000 },
3312
3313                 /* Green Setting */
3314                 { 0x1f, 0x0005 },
3315                 { 0x05, 0x8b5b },
3316                 { 0x06, 0x9222 },
3317                 { 0x05, 0x8b6d },
3318                 { 0x06, 0x8000 },
3319                 { 0x05, 0x8b76 },
3320                 { 0x06, 0x8000 },
3321                 { 0x1f, 0x0000 }
3322         };
3323
3324         rtl_apply_firmware(tp);
3325
3326         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3327
3328         /* For 4-corner performance improve */
3329         rtl_writephy(tp, 0x1f, 0x0005);
3330         rtl_writephy(tp, 0x05, 0x8b80);
3331         rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
3332         rtl_writephy(tp, 0x1f, 0x0000);
3333
3334         /* PHY auto speed down */
3335         rtl_writephy(tp, 0x1f, 0x0004);
3336         rtl_writephy(tp, 0x1f, 0x0007);
3337         rtl_writephy(tp, 0x1e, 0x002d);
3338         rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
3339         rtl_writephy(tp, 0x1f, 0x0002);
3340         rtl_writephy(tp, 0x1f, 0x0000);
3341         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3342
3343         /* improve 10M EEE waveform */
3344         rtl_writephy(tp, 0x1f, 0x0005);
3345         rtl_writephy(tp, 0x05, 0x8b86);
3346         rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3347         rtl_writephy(tp, 0x1f, 0x0000);
3348
3349         /* Improve 2-pair detection performance */
3350         rtl_writephy(tp, 0x1f, 0x0005);
3351         rtl_writephy(tp, 0x05, 0x8b85);
3352         rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3353         rtl_writephy(tp, 0x1f, 0x0000);
3354
3355         rtl8168f_config_eee_phy(tp);
3356         rtl_enable_eee(tp);
3357
3358         /* Green feature */
3359         rtl_writephy(tp, 0x1f, 0x0003);
3360         rtl_w0w1_phy(tp, 0x19, 0x0001, 0x0000);
3361         rtl_w0w1_phy(tp, 0x10, 0x0400, 0x0000);
3362         rtl_writephy(tp, 0x1f, 0x0000);
3363         rtl_writephy(tp, 0x1f, 0x0005);
3364         rtl_w0w1_phy(tp, 0x01, 0x0100, 0x0000);
3365         rtl_writephy(tp, 0x1f, 0x0000);
3366
3367         /* Broken BIOS workaround: feed GigaMAC registers with MAC address. */
3368         rtl_rar_exgmac_set(tp, tp->dev->dev_addr);
3369 }
3370
3371 static void rtl8168f_hw_phy_config(struct rtl8169_private *tp)
3372 {
3373         /* For 4-corner performance improve */
3374         rtl_writephy(tp, 0x1f, 0x0005);
3375         rtl_writephy(tp, 0x05, 0x8b80);
3376         rtl_w0w1_phy(tp, 0x06, 0x0006, 0x0000);
3377         rtl_writephy(tp, 0x1f, 0x0000);
3378
3379         /* PHY auto speed down */
3380         rtl_writephy(tp, 0x1f, 0x0007);
3381         rtl_writephy(tp, 0x1e, 0x002d);
3382         rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
3383         rtl_writephy(tp, 0x1f, 0x0000);
3384         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3385
3386         /* Improve 10M EEE waveform */
3387         rtl_writephy(tp, 0x1f, 0x0005);
3388         rtl_writephy(tp, 0x05, 0x8b86);
3389         rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3390         rtl_writephy(tp, 0x1f, 0x0000);
3391
3392         rtl8168f_config_eee_phy(tp);
3393         rtl_enable_eee(tp);
3394 }
3395
3396 static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp)
3397 {
3398         static const struct phy_reg phy_reg_init[] = {
3399                 /* Channel estimation fine tune */
3400                 { 0x1f, 0x0003 },
3401                 { 0x09, 0xa20f },
3402                 { 0x1f, 0x0000 },
3403
3404                 /* Modify green table for giga & fnet */
3405                 { 0x1f, 0x0005 },
3406                 { 0x05, 0x8b55 },
3407                 { 0x06, 0x0000 },
3408                 { 0x05, 0x8b5e },
3409                 { 0x06, 0x0000 },
3410                 { 0x05, 0x8b67 },
3411                 { 0x06, 0x0000 },
3412                 { 0x05, 0x8b70 },
3413                 { 0x06, 0x0000 },
3414                 { 0x1f, 0x0000 },
3415                 { 0x1f, 0x0007 },
3416                 { 0x1e, 0x0078 },
3417                 { 0x17, 0x0000 },
3418                 { 0x19, 0x00fb },
3419                 { 0x1f, 0x0000 },
3420
3421                 /* Modify green table for 10M */
3422                 { 0x1f, 0x0005 },
3423                 { 0x05, 0x8b79 },
3424                 { 0x06, 0xaa00 },
3425                 { 0x1f, 0x0000 },
3426
3427                 /* Disable hiimpedance detection (RTCT) */
3428                 { 0x1f, 0x0003 },
3429                 { 0x01, 0x328a },
3430                 { 0x1f, 0x0000 }
3431         };
3432
3433         rtl_apply_firmware(tp);
3434
3435         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3436
3437         rtl8168f_hw_phy_config(tp);
3438
3439         /* Improve 2-pair detection performance */
3440         rtl_writephy(tp, 0x1f, 0x0005);
3441         rtl_writephy(tp, 0x05, 0x8b85);
3442         rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3443         rtl_writephy(tp, 0x1f, 0x0000);
3444 }
3445
3446 static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp)
3447 {
3448         rtl_apply_firmware(tp);
3449
3450         rtl8168f_hw_phy_config(tp);
3451 }
3452
3453 static void rtl8411_hw_phy_config(struct rtl8169_private *tp)
3454 {
3455         static const struct phy_reg phy_reg_init[] = {
3456                 /* Channel estimation fine tune */
3457                 { 0x1f, 0x0003 },
3458                 { 0x09, 0xa20f },
3459                 { 0x1f, 0x0000 },
3460
3461                 /* Modify green table for giga & fnet */
3462                 { 0x1f, 0x0005 },
3463                 { 0x05, 0x8b55 },
3464                 { 0x06, 0x0000 },
3465                 { 0x05, 0x8b5e },
3466                 { 0x06, 0x0000 },
3467                 { 0x05, 0x8b67 },
3468                 { 0x06, 0x0000 },
3469                 { 0x05, 0x8b70 },
3470                 { 0x06, 0x0000 },
3471                 { 0x1f, 0x0000 },
3472                 { 0x1f, 0x0007 },
3473                 { 0x1e, 0x0078 },
3474                 { 0x17, 0x0000 },
3475                 { 0x19, 0x00aa },
3476                 { 0x1f, 0x0000 },
3477
3478                 /* Modify green table for 10M */
3479                 { 0x1f, 0x0005 },
3480                 { 0x05, 0x8b79 },
3481                 { 0x06, 0xaa00 },
3482                 { 0x1f, 0x0000 },
3483
3484                 /* Disable hiimpedance detection (RTCT) */
3485                 { 0x1f, 0x0003 },
3486                 { 0x01, 0x328a },
3487                 { 0x1f, 0x0000 }
3488         };
3489
3490
3491         rtl_apply_firmware(tp);
3492
3493         rtl8168f_hw_phy_config(tp);
3494
3495         /* Improve 2-pair detection performance */
3496         rtl_writephy(tp, 0x1f, 0x0005);
3497         rtl_writephy(tp, 0x05, 0x8b85);
3498         rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3499         rtl_writephy(tp, 0x1f, 0x0000);
3500
3501         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3502
3503         /* Modify green table for giga */
3504         rtl_writephy(tp, 0x1f, 0x0005);
3505         rtl_writephy(tp, 0x05, 0x8b54);
3506         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
3507         rtl_writephy(tp, 0x05, 0x8b5d);
3508         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
3509         rtl_writephy(tp, 0x05, 0x8a7c);
3510         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3511         rtl_writephy(tp, 0x05, 0x8a7f);
3512         rtl_w0w1_phy(tp, 0x06, 0x0100, 0x0000);
3513         rtl_writephy(tp, 0x05, 0x8a82);
3514         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3515         rtl_writephy(tp, 0x05, 0x8a85);
3516         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3517         rtl_writephy(tp, 0x05, 0x8a88);
3518         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3519         rtl_writephy(tp, 0x1f, 0x0000);
3520
3521         /* uc same-seed solution */
3522         rtl_writephy(tp, 0x1f, 0x0005);
3523         rtl_writephy(tp, 0x05, 0x8b85);
3524         rtl_w0w1_phy(tp, 0x06, 0x8000, 0x0000);
3525         rtl_writephy(tp, 0x1f, 0x0000);
3526
3527         /* Green feature */
3528         rtl_writephy(tp, 0x1f, 0x0003);
3529         rtl_w0w1_phy(tp, 0x19, 0x0000, 0x0001);
3530         rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0400);
3531         rtl_writephy(tp, 0x1f, 0x0000);
3532 }
3533
3534 static void rtl8168g_disable_aldps(struct rtl8169_private *tp)
3535 {
3536         phy_write(tp->phydev, 0x1f, 0x0a43);
3537         phy_clear_bits(tp->phydev, 0x10, BIT(2));
3538 }
3539
3540 static void rtl8168g_phy_adjust_10m_aldps(struct rtl8169_private *tp)
3541 {
3542         struct phy_device *phydev = tp->phydev;
3543
3544         phy_write(phydev, 0x1f, 0x0bcc);
3545         phy_clear_bits(phydev, 0x14, BIT(8));
3546
3547         phy_write(phydev, 0x1f, 0x0a44);
3548         phy_set_bits(phydev, 0x11, BIT(7) | BIT(6));
3549
3550         phy_write(phydev, 0x1f, 0x0a43);
3551         phy_write(phydev, 0x13, 0x8084);
3552         phy_clear_bits(phydev, 0x14, BIT(14) | BIT(13));
3553         phy_set_bits(phydev, 0x10, BIT(12) | BIT(1) | BIT(0));
3554
3555         phy_write(phydev, 0x1f, 0x0000);
3556 }
3557
3558 static void rtl8168g_1_hw_phy_config(struct rtl8169_private *tp)
3559 {
3560         rtl_apply_firmware(tp);
3561
3562         rtl_writephy(tp, 0x1f, 0x0a46);
3563         if (rtl_readphy(tp, 0x10) & 0x0100) {
3564                 rtl_writephy(tp, 0x1f, 0x0bcc);
3565                 rtl_w0w1_phy(tp, 0x12, 0x0000, 0x8000);
3566         } else {
3567                 rtl_writephy(tp, 0x1f, 0x0bcc);
3568                 rtl_w0w1_phy(tp, 0x12, 0x8000, 0x0000);
3569         }
3570
3571         rtl_writephy(tp, 0x1f, 0x0a46);
3572         if (rtl_readphy(tp, 0x13) & 0x0100) {
3573                 rtl_writephy(tp, 0x1f, 0x0c41);
3574                 rtl_w0w1_phy(tp, 0x15, 0x0002, 0x0000);
3575         } else {
3576                 rtl_writephy(tp, 0x1f, 0x0c41);
3577                 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x0002);
3578         }
3579
3580         /* Enable PHY auto speed down */
3581         rtl_writephy(tp, 0x1f, 0x0a44);
3582         rtl_w0w1_phy(tp, 0x11, 0x000c, 0x0000);
3583
3584         rtl8168g_phy_adjust_10m_aldps(tp);
3585
3586         /* EEE auto-fallback function */
3587         rtl_writephy(tp, 0x1f, 0x0a4b);
3588         rtl_w0w1_phy(tp, 0x11, 0x0004, 0x0000);
3589
3590         /* Enable UC LPF tune function */
3591         rtl_writephy(tp, 0x1f, 0x0a43);
3592         rtl_writephy(tp, 0x13, 0x8012);
3593         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3594
3595         rtl_writephy(tp, 0x1f, 0x0c42);
3596         rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
3597
3598         /* Improve SWR Efficiency */
3599         rtl_writephy(tp, 0x1f, 0x0bcd);
3600         rtl_writephy(tp, 0x14, 0x5065);
3601         rtl_writephy(tp, 0x14, 0xd065);
3602         rtl_writephy(tp, 0x1f, 0x0bc8);
3603         rtl_writephy(tp, 0x11, 0x5655);
3604         rtl_writephy(tp, 0x1f, 0x0bcd);
3605         rtl_writephy(tp, 0x14, 0x1065);
3606         rtl_writephy(tp, 0x14, 0x9065);
3607         rtl_writephy(tp, 0x14, 0x1065);
3608
3609         rtl8168g_disable_aldps(tp);
3610         rtl8168g_config_eee_phy(tp);
3611         rtl_enable_eee(tp);
3612 }
3613
3614 static void rtl8168g_2_hw_phy_config(struct rtl8169_private *tp)
3615 {
3616         rtl_apply_firmware(tp);
3617         rtl8168g_config_eee_phy(tp);
3618         rtl_enable_eee(tp);
3619 }
3620
3621 static void rtl8168h_1_hw_phy_config(struct rtl8169_private *tp)
3622 {
3623         u16 dout_tapbin;
3624         u32 data;
3625
3626         rtl_apply_firmware(tp);
3627
3628         /* CHN EST parameters adjust - giga master */
3629         rtl_writephy(tp, 0x1f, 0x0a43);
3630         rtl_writephy(tp, 0x13, 0x809b);
3631         rtl_w0w1_phy(tp, 0x14, 0x8000, 0xf800);
3632         rtl_writephy(tp, 0x13, 0x80a2);
3633         rtl_w0w1_phy(tp, 0x14, 0x8000, 0xff00);
3634         rtl_writephy(tp, 0x13, 0x80a4);
3635         rtl_w0w1_phy(tp, 0x14, 0x8500, 0xff00);
3636         rtl_writephy(tp, 0x13, 0x809c);
3637         rtl_w0w1_phy(tp, 0x14, 0xbd00, 0xff00);
3638         rtl_writephy(tp, 0x1f, 0x0000);
3639
3640         /* CHN EST parameters adjust - giga slave */
3641         rtl_writephy(tp, 0x1f, 0x0a43);
3642         rtl_writephy(tp, 0x13, 0x80ad);
3643         rtl_w0w1_phy(tp, 0x14, 0x7000, 0xf800);
3644         rtl_writephy(tp, 0x13, 0x80b4);
3645         rtl_w0w1_phy(tp, 0x14, 0x5000, 0xff00);
3646         rtl_writephy(tp, 0x13, 0x80ac);
3647         rtl_w0w1_phy(tp, 0x14, 0x4000, 0xff00);
3648         rtl_writephy(tp, 0x1f, 0x0000);
3649
3650         /* CHN EST parameters adjust - fnet */
3651         rtl_writephy(tp, 0x1f, 0x0a43);
3652         rtl_writephy(tp, 0x13, 0x808e);
3653         rtl_w0w1_phy(tp, 0x14, 0x1200, 0xff00);
3654         rtl_writephy(tp, 0x13, 0x8090);
3655         rtl_w0w1_phy(tp, 0x14, 0xe500, 0xff00);
3656         rtl_writephy(tp, 0x13, 0x8092);
3657         rtl_w0w1_phy(tp, 0x14, 0x9f00, 0xff00);
3658         rtl_writephy(tp, 0x1f, 0x0000);
3659
3660         /* enable R-tune & PGA-retune function */
3661         dout_tapbin = 0;
3662         rtl_writephy(tp, 0x1f, 0x0a46);
3663         data = rtl_readphy(tp, 0x13);
3664         data &= 3;
3665         data <<= 2;
3666         dout_tapbin |= data;
3667         data = rtl_readphy(tp, 0x12);
3668         data &= 0xc000;
3669         data >>= 14;
3670         dout_tapbin |= data;
3671         dout_tapbin = ~(dout_tapbin^0x08);
3672         dout_tapbin <<= 12;
3673         dout_tapbin &= 0xf000;
3674         rtl_writephy(tp, 0x1f, 0x0a43);
3675         rtl_writephy(tp, 0x13, 0x827a);
3676         rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3677         rtl_writephy(tp, 0x13, 0x827b);
3678         rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3679         rtl_writephy(tp, 0x13, 0x827c);
3680         rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3681         rtl_writephy(tp, 0x13, 0x827d);
3682         rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3683
3684         rtl_writephy(tp, 0x1f, 0x0a43);
3685         rtl_writephy(tp, 0x13, 0x0811);
3686         rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
3687         rtl_writephy(tp, 0x1f, 0x0a42);
3688         rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
3689         rtl_writephy(tp, 0x1f, 0x0000);
3690
3691         /* enable GPHY 10M */
3692         rtl_writephy(tp, 0x1f, 0x0a44);
3693         rtl_w0w1_phy(tp, 0x11, 0x0800, 0x0000);
3694         rtl_writephy(tp, 0x1f, 0x0000);
3695
3696         /* SAR ADC performance */
3697         rtl_writephy(tp, 0x1f, 0x0bca);
3698         rtl_w0w1_phy(tp, 0x17, 0x4000, 0x3000);
3699         rtl_writephy(tp, 0x1f, 0x0000);
3700
3701         rtl_writephy(tp, 0x1f, 0x0a43);
3702         rtl_writephy(tp, 0x13, 0x803f);
3703         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3704         rtl_writephy(tp, 0x13, 0x8047);
3705         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3706         rtl_writephy(tp, 0x13, 0x804f);
3707         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3708         rtl_writephy(tp, 0x13, 0x8057);
3709         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3710         rtl_writephy(tp, 0x13, 0x805f);
3711         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3712         rtl_writephy(tp, 0x13, 0x8067);
3713         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3714         rtl_writephy(tp, 0x13, 0x806f);
3715         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3716         rtl_writephy(tp, 0x1f, 0x0000);
3717
3718         /* disable phy pfm mode */
3719         rtl_writephy(tp, 0x1f, 0x0a44);
3720         rtl_w0w1_phy(tp, 0x11, 0x0000, 0x0080);
3721         rtl_writephy(tp, 0x1f, 0x0000);
3722
3723         rtl8168g_disable_aldps(tp);
3724         rtl8168g_config_eee_phy(tp);
3725         rtl_enable_eee(tp);
3726 }
3727
3728 static void rtl8168h_2_hw_phy_config(struct rtl8169_private *tp)
3729 {
3730         u16 ioffset_p3, ioffset_p2, ioffset_p1, ioffset_p0;
3731         u16 rlen;
3732         u32 data;
3733
3734         rtl_apply_firmware(tp);
3735
3736         /* CHIN EST parameter update */
3737         rtl_writephy(tp, 0x1f, 0x0a43);
3738         rtl_writephy(tp, 0x13, 0x808a);
3739         rtl_w0w1_phy(tp, 0x14, 0x000a, 0x003f);
3740         rtl_writephy(tp, 0x1f, 0x0000);
3741
3742         /* enable R-tune & PGA-retune function */
3743         rtl_writephy(tp, 0x1f, 0x0a43);
3744         rtl_writephy(tp, 0x13, 0x0811);
3745         rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
3746         rtl_writephy(tp, 0x1f, 0x0a42);
3747         rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
3748         rtl_writephy(tp, 0x1f, 0x0000);
3749
3750         /* enable GPHY 10M */
3751         rtl_writephy(tp, 0x1f, 0x0a44);
3752         rtl_w0w1_phy(tp, 0x11, 0x0800, 0x0000);
3753         rtl_writephy(tp, 0x1f, 0x0000);
3754
3755         r8168_mac_ocp_write(tp, 0xdd02, 0x807d);
3756         data = r8168_mac_ocp_read(tp, 0xdd02);
3757         ioffset_p3 = ((data & 0x80)>>7);
3758         ioffset_p3 <<= 3;
3759
3760         data = r8168_mac_ocp_read(tp, 0xdd00);
3761         ioffset_p3 |= ((data & (0xe000))>>13);
3762         ioffset_p2 = ((data & (0x1e00))>>9);
3763         ioffset_p1 = ((data & (0x01e0))>>5);
3764         ioffset_p0 = ((data & 0x0010)>>4);
3765         ioffset_p0 <<= 3;
3766         ioffset_p0 |= (data & (0x07));
3767         data = (ioffset_p3<<12)|(ioffset_p2<<8)|(ioffset_p1<<4)|(ioffset_p0);
3768
3769         if ((ioffset_p3 != 0x0f) || (ioffset_p2 != 0x0f) ||
3770             (ioffset_p1 != 0x0f) || (ioffset_p0 != 0x0f)) {
3771                 rtl_writephy(tp, 0x1f, 0x0bcf);
3772                 rtl_writephy(tp, 0x16, data);
3773                 rtl_writephy(tp, 0x1f, 0x0000);
3774         }
3775
3776         /* Modify rlen (TX LPF corner frequency) level */
3777         rtl_writephy(tp, 0x1f, 0x0bcd);
3778         data = rtl_readphy(tp, 0x16);
3779         data &= 0x000f;
3780         rlen = 0;
3781         if (data > 3)
3782                 rlen = data - 3;
3783         data = rlen | (rlen<<4) | (rlen<<8) | (rlen<<12);
3784         rtl_writephy(tp, 0x17, data);
3785         rtl_writephy(tp, 0x1f, 0x0bcd);
3786         rtl_writephy(tp, 0x1f, 0x0000);
3787
3788         /* disable phy pfm mode */
3789         rtl_writephy(tp, 0x1f, 0x0a44);
3790         rtl_w0w1_phy(tp, 0x11, 0x0000, 0x0080);
3791         rtl_writephy(tp, 0x1f, 0x0000);
3792
3793         rtl8168g_disable_aldps(tp);
3794         rtl8168g_config_eee_phy(tp);
3795         rtl_enable_eee(tp);
3796 }
3797
3798 static void rtl8168ep_1_hw_phy_config(struct rtl8169_private *tp)
3799 {
3800         /* Enable PHY auto speed down */
3801         rtl_writephy(tp, 0x1f, 0x0a44);
3802         rtl_w0w1_phy(tp, 0x11, 0x000c, 0x0000);
3803         rtl_writephy(tp, 0x1f, 0x0000);
3804
3805         rtl8168g_phy_adjust_10m_aldps(tp);
3806
3807         /* Enable EEE auto-fallback function */
3808         rtl_writephy(tp, 0x1f, 0x0a4b);
3809         rtl_w0w1_phy(tp, 0x11, 0x0004, 0x0000);
3810         rtl_writephy(tp, 0x1f, 0x0000);
3811
3812         /* Enable UC LPF tune function */
3813         rtl_writephy(tp, 0x1f, 0x0a43);
3814         rtl_writephy(tp, 0x13, 0x8012);
3815         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3816         rtl_writephy(tp, 0x1f, 0x0000);
3817
3818         /* set rg_sel_sdm_rate */
3819         rtl_writephy(tp, 0x1f, 0x0c42);
3820         rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
3821         rtl_writephy(tp, 0x1f, 0x0000);
3822
3823         rtl8168g_disable_aldps(tp);
3824         rtl8168g_config_eee_phy(tp);
3825         rtl_enable_eee(tp);
3826 }
3827
3828 static void rtl8168ep_2_hw_phy_config(struct rtl8169_private *tp)
3829 {
3830         rtl8168g_phy_adjust_10m_aldps(tp);
3831
3832         /* Enable UC LPF tune function */
3833         rtl_writephy(tp, 0x1f, 0x0a43);
3834         rtl_writephy(tp, 0x13, 0x8012);
3835         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3836         rtl_writephy(tp, 0x1f, 0x0000);
3837
3838         /* Set rg_sel_sdm_rate */
3839         rtl_writephy(tp, 0x1f, 0x0c42);
3840         rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
3841         rtl_writephy(tp, 0x1f, 0x0000);
3842
3843         /* Channel estimation parameters */
3844         rtl_writephy(tp, 0x1f, 0x0a43);
3845         rtl_writephy(tp, 0x13, 0x80f3);
3846         rtl_w0w1_phy(tp, 0x14, 0x8b00, ~0x8bff);
3847         rtl_writephy(tp, 0x13, 0x80f0);
3848         rtl_w0w1_phy(tp, 0x14, 0x3a00, ~0x3aff);
3849         rtl_writephy(tp, 0x13, 0x80ef);
3850         rtl_w0w1_phy(tp, 0x14, 0x0500, ~0x05ff);
3851         rtl_writephy(tp, 0x13, 0x80f6);
3852         rtl_w0w1_phy(tp, 0x14, 0x6e00, ~0x6eff);
3853         rtl_writephy(tp, 0x13, 0x80ec);
3854         rtl_w0w1_phy(tp, 0x14, 0x6800, ~0x68ff);
3855         rtl_writephy(tp, 0x13, 0x80ed);
3856         rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
3857         rtl_writephy(tp, 0x13, 0x80f2);
3858         rtl_w0w1_phy(tp, 0x14, 0xf400, ~0xf4ff);
3859         rtl_writephy(tp, 0x13, 0x80f4);
3860         rtl_w0w1_phy(tp, 0x14, 0x8500, ~0x85ff);
3861         rtl_writephy(tp, 0x1f, 0x0a43);
3862         rtl_writephy(tp, 0x13, 0x8110);
3863         rtl_w0w1_phy(tp, 0x14, 0xa800, ~0xa8ff);
3864         rtl_writephy(tp, 0x13, 0x810f);
3865         rtl_w0w1_phy(tp, 0x14, 0x1d00, ~0x1dff);
3866         rtl_writephy(tp, 0x13, 0x8111);
3867         rtl_w0w1_phy(tp, 0x14, 0xf500, ~0xf5ff);
3868         rtl_writephy(tp, 0x13, 0x8113);
3869         rtl_w0w1_phy(tp, 0x14, 0x6100, ~0x61ff);
3870         rtl_writephy(tp, 0x13, 0x8115);
3871         rtl_w0w1_phy(tp, 0x14, 0x9200, ~0x92ff);
3872         rtl_writephy(tp, 0x13, 0x810e);
3873         rtl_w0w1_phy(tp, 0x14, 0x0400, ~0x04ff);
3874         rtl_writephy(tp, 0x13, 0x810c);
3875         rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
3876         rtl_writephy(tp, 0x13, 0x810b);
3877         rtl_w0w1_phy(tp, 0x14, 0x5a00, ~0x5aff);
3878         rtl_writephy(tp, 0x1f, 0x0a43);
3879         rtl_writephy(tp, 0x13, 0x80d1);
3880         rtl_w0w1_phy(tp, 0x14, 0xff00, ~0xffff);
3881         rtl_writephy(tp, 0x13, 0x80cd);
3882         rtl_w0w1_phy(tp, 0x14, 0x9e00, ~0x9eff);
3883         rtl_writephy(tp, 0x13, 0x80d3);
3884         rtl_w0w1_phy(tp, 0x14, 0x0e00, ~0x0eff);
3885         rtl_writephy(tp, 0x13, 0x80d5);
3886         rtl_w0w1_phy(tp, 0x14, 0xca00, ~0xcaff);
3887         rtl_writephy(tp, 0x13, 0x80d7);
3888         rtl_w0w1_phy(tp, 0x14, 0x8400, ~0x84ff);
3889
3890         /* Force PWM-mode */
3891         rtl_writephy(tp, 0x1f, 0x0bcd);
3892         rtl_writephy(tp, 0x14, 0x5065);
3893         rtl_writephy(tp, 0x14, 0xd065);
3894         rtl_writephy(tp, 0x1f, 0x0bc8);
3895         rtl_writephy(tp, 0x12, 0x00ed);
3896         rtl_writephy(tp, 0x1f, 0x0bcd);
3897         rtl_writephy(tp, 0x14, 0x1065);
3898         rtl_writephy(tp, 0x14, 0x9065);
3899         rtl_writephy(tp, 0x14, 0x1065);
3900         rtl_writephy(tp, 0x1f, 0x0000);
3901
3902         rtl8168g_disable_aldps(tp);
3903         rtl8168g_config_eee_phy(tp);
3904         rtl_enable_eee(tp);
3905 }
3906
3907 static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
3908 {
3909         static const struct phy_reg phy_reg_init[] = {
3910                 { 0x1f, 0x0003 },
3911                 { 0x08, 0x441d },
3912                 { 0x01, 0x9100 },
3913                 { 0x1f, 0x0000 }
3914         };
3915
3916         rtl_writephy(tp, 0x1f, 0x0000);
3917         rtl_patchphy(tp, 0x11, 1 << 12);
3918         rtl_patchphy(tp, 0x19, 1 << 13);
3919         rtl_patchphy(tp, 0x10, 1 << 15);
3920
3921         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3922 }
3923
3924 static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
3925 {
3926         static const struct phy_reg phy_reg_init[] = {
3927                 { 0x1f, 0x0005 },
3928                 { 0x1a, 0x0000 },
3929                 { 0x1f, 0x0000 },
3930
3931                 { 0x1f, 0x0004 },
3932                 { 0x1c, 0x0000 },
3933                 { 0x1f, 0x0000 },
3934
3935                 { 0x1f, 0x0001 },
3936                 { 0x15, 0x7701 },
3937                 { 0x1f, 0x0000 }
3938         };
3939
3940         /* Disable ALDPS before ram code */
3941         rtl_writephy(tp, 0x1f, 0x0000);
3942         rtl_writephy(tp, 0x18, 0x0310);
3943         msleep(100);
3944
3945         rtl_apply_firmware(tp);
3946
3947         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3948 }
3949
3950 static void rtl8402_hw_phy_config(struct rtl8169_private *tp)
3951 {
3952         /* Disable ALDPS before setting firmware */
3953         rtl_writephy(tp, 0x1f, 0x0000);
3954         rtl_writephy(tp, 0x18, 0x0310);
3955         msleep(20);
3956
3957         rtl_apply_firmware(tp);
3958
3959         /* EEE setting */
3960         rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
3961         rtl_writephy(tp, 0x1f, 0x0004);
3962         rtl_writephy(tp, 0x10, 0x401f);
3963         rtl_writephy(tp, 0x19, 0x7030);
3964         rtl_writephy(tp, 0x1f, 0x0000);
3965 }
3966
3967 static void rtl8106e_hw_phy_config(struct rtl8169_private *tp)
3968 {
3969         static const struct phy_reg phy_reg_init[] = {
3970                 { 0x1f, 0x0004 },
3971                 { 0x10, 0xc07f },
3972                 { 0x19, 0x7030 },
3973                 { 0x1f, 0x0000 }
3974         };
3975
3976         /* Disable ALDPS before ram code */
3977         rtl_writephy(tp, 0x1f, 0x0000);
3978         rtl_writephy(tp, 0x18, 0x0310);
3979         msleep(100);
3980
3981         rtl_apply_firmware(tp);
3982
3983         rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
3984         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3985
3986         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
3987 }
3988
3989 static void rtl_hw_phy_config(struct net_device *dev)
3990 {
3991         struct rtl8169_private *tp = netdev_priv(dev);
3992
3993         switch (tp->mac_version) {
3994         case RTL_GIGA_MAC_VER_01:
3995                 break;
3996         case RTL_GIGA_MAC_VER_02:
3997         case RTL_GIGA_MAC_VER_03:
3998                 rtl8169s_hw_phy_config(tp);
3999                 break;
4000         case RTL_GIGA_MAC_VER_04:
4001                 rtl8169sb_hw_phy_config(tp);
4002                 break;
4003         case RTL_GIGA_MAC_VER_05:
4004                 rtl8169scd_hw_phy_config(tp);
4005                 break;
4006         case RTL_GIGA_MAC_VER_06:
4007                 rtl8169sce_hw_phy_config(tp);
4008                 break;
4009         case RTL_GIGA_MAC_VER_07:
4010         case RTL_GIGA_MAC_VER_08:
4011         case RTL_GIGA_MAC_VER_09:
4012                 rtl8102e_hw_phy_config(tp);
4013                 break;
4014         case RTL_GIGA_MAC_VER_11:
4015                 rtl8168bb_hw_phy_config(tp);
4016                 break;
4017         case RTL_GIGA_MAC_VER_12:
4018                 rtl8168bef_hw_phy_config(tp);
4019                 break;
4020         case RTL_GIGA_MAC_VER_17:
4021                 rtl8168bef_hw_phy_config(tp);
4022                 break;
4023         case RTL_GIGA_MAC_VER_18:
4024                 rtl8168cp_1_hw_phy_config(tp);
4025                 break;
4026         case RTL_GIGA_MAC_VER_19:
4027                 rtl8168c_1_hw_phy_config(tp);
4028                 break;
4029         case RTL_GIGA_MAC_VER_20:
4030                 rtl8168c_2_hw_phy_config(tp);
4031                 break;
4032         case RTL_GIGA_MAC_VER_21:
4033                 rtl8168c_3_hw_phy_config(tp);
4034                 break;
4035         case RTL_GIGA_MAC_VER_22:
4036                 rtl8168c_4_hw_phy_config(tp);
4037                 break;
4038         case RTL_GIGA_MAC_VER_23:
4039         case RTL_GIGA_MAC_VER_24:
4040                 rtl8168cp_2_hw_phy_config(tp);
4041                 break;
4042         case RTL_GIGA_MAC_VER_25:
4043                 rtl8168d_1_hw_phy_config(tp);
4044                 break;
4045         case RTL_GIGA_MAC_VER_26:
4046                 rtl8168d_2_hw_phy_config(tp);
4047                 break;
4048         case RTL_GIGA_MAC_VER_27:
4049                 rtl8168d_3_hw_phy_config(tp);
4050                 break;
4051         case RTL_GIGA_MAC_VER_28:
4052                 rtl8168d_4_hw_phy_config(tp);
4053                 break;
4054         case RTL_GIGA_MAC_VER_29:
4055         case RTL_GIGA_MAC_VER_30:
4056                 rtl8105e_hw_phy_config(tp);
4057                 break;
4058         case RTL_GIGA_MAC_VER_31:
4059                 /* None. */
4060                 break;
4061         case RTL_GIGA_MAC_VER_32:
4062         case RTL_GIGA_MAC_VER_33:
4063                 rtl8168e_1_hw_phy_config(tp);
4064                 break;
4065         case RTL_GIGA_MAC_VER_34:
4066                 rtl8168e_2_hw_phy_config(tp);
4067                 break;
4068         case RTL_GIGA_MAC_VER_35:
4069                 rtl8168f_1_hw_phy_config(tp);
4070                 break;
4071         case RTL_GIGA_MAC_VER_36:
4072                 rtl8168f_2_hw_phy_config(tp);
4073                 break;
4074
4075         case RTL_GIGA_MAC_VER_37:
4076                 rtl8402_hw_phy_config(tp);
4077                 break;
4078
4079         case RTL_GIGA_MAC_VER_38:
4080                 rtl8411_hw_phy_config(tp);
4081                 break;
4082
4083         case RTL_GIGA_MAC_VER_39:
4084                 rtl8106e_hw_phy_config(tp);
4085                 break;
4086
4087         case RTL_GIGA_MAC_VER_40:
4088                 rtl8168g_1_hw_phy_config(tp);
4089                 break;
4090         case RTL_GIGA_MAC_VER_42:
4091         case RTL_GIGA_MAC_VER_43:
4092         case RTL_GIGA_MAC_VER_44:
4093                 rtl8168g_2_hw_phy_config(tp);
4094                 break;
4095         case RTL_GIGA_MAC_VER_45:
4096         case RTL_GIGA_MAC_VER_47:
4097                 rtl8168h_1_hw_phy_config(tp);
4098                 break;
4099         case RTL_GIGA_MAC_VER_46:
4100         case RTL_GIGA_MAC_VER_48:
4101                 rtl8168h_2_hw_phy_config(tp);
4102                 break;
4103
4104         case RTL_GIGA_MAC_VER_49:
4105                 rtl8168ep_1_hw_phy_config(tp);
4106                 break;
4107         case RTL_GIGA_MAC_VER_50:
4108         case RTL_GIGA_MAC_VER_51:
4109                 rtl8168ep_2_hw_phy_config(tp);
4110                 break;
4111
4112         case RTL_GIGA_MAC_VER_41:
4113         default:
4114                 break;
4115         }
4116 }
4117
4118 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
4119 {
4120         if (!test_and_set_bit(flag, tp->wk.flags))
4121                 schedule_work(&tp->wk.work);
4122 }
4123
4124 static bool rtl_tbi_enabled(struct rtl8169_private *tp)
4125 {
4126         return (tp->mac_version == RTL_GIGA_MAC_VER_01) &&
4127                (RTL_R8(tp, PHYstatus) & TBI_Enable);
4128 }
4129
4130 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
4131 {
4132         rtl_hw_phy_config(dev);
4133
4134         if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
4135                 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
4136                 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4137                 netif_dbg(tp, drv, dev,
4138                           "Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
4139                 RTL_W8(tp, 0x82, 0x01);
4140         }
4141
4142         /* We may have called phy_speed_down before */
4143         phy_speed_up(tp->phydev);
4144
4145         genphy_soft_reset(tp->phydev);
4146
4147         /* It was reported that several chips end up with 10MBit/Half on a
4148          * 1GBit link after resuming from S3. For whatever reason the PHY on
4149          * these chips doesn't properly start a renegotiation when soft-reset.
4150          * Explicitly requesting a renegotiation fixes this.
4151          */
4152         if (tp->phydev->autoneg == AUTONEG_ENABLE)
4153                 phy_restart_aneg(tp->phydev);
4154 }
4155
4156 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
4157 {
4158         rtl_lock_work(tp);
4159
4160         rtl_unlock_config_regs(tp);
4161
4162         RTL_W32(tp, MAC4, addr[4] | addr[5] << 8);
4163         RTL_R32(tp, MAC4);
4164
4165         RTL_W32(tp, MAC0, addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24);
4166         RTL_R32(tp, MAC0);
4167
4168         if (tp->mac_version == RTL_GIGA_MAC_VER_34)
4169                 rtl_rar_exgmac_set(tp, addr);
4170
4171         rtl_lock_config_regs(tp);
4172
4173         rtl_unlock_work(tp);
4174 }
4175
4176 static int rtl_set_mac_address(struct net_device *dev, void *p)
4177 {
4178         struct rtl8169_private *tp = netdev_priv(dev);
4179         struct device *d = tp_to_dev(tp);
4180         int ret;
4181
4182         ret = eth_mac_addr(dev, p);
4183         if (ret)
4184                 return ret;
4185
4186         pm_runtime_get_noresume(d);
4187
4188         if (pm_runtime_active(d))
4189                 rtl_rar_set(tp, dev->dev_addr);
4190
4191         pm_runtime_put_noidle(d);
4192
4193         return 0;
4194 }
4195
4196 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
4197 {
4198         struct rtl8169_private *tp = netdev_priv(dev);
4199
4200         if (!netif_running(dev))
4201                 return -ENODEV;
4202
4203         return phy_mii_ioctl(tp->phydev, ifr, cmd);
4204 }
4205
4206 static void rtl_init_mdio_ops(struct rtl8169_private *tp)
4207 {
4208         struct mdio_ops *ops = &tp->mdio_ops;
4209
4210         switch (tp->mac_version) {
4211         case RTL_GIGA_MAC_VER_27:
4212                 ops->write      = r8168dp_1_mdio_write;
4213                 ops->read       = r8168dp_1_mdio_read;
4214                 break;
4215         case RTL_GIGA_MAC_VER_28:
4216         case RTL_GIGA_MAC_VER_31:
4217                 ops->write      = r8168dp_2_mdio_write;
4218                 ops->read       = r8168dp_2_mdio_read;
4219                 break;
4220         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
4221                 ops->write      = r8168g_mdio_write;
4222                 ops->read       = r8168g_mdio_read;
4223                 break;
4224         default:
4225                 ops->write      = r8169_mdio_write;
4226                 ops->read       = r8169_mdio_read;
4227                 break;
4228         }
4229 }
4230
4231 static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
4232 {
4233         switch (tp->mac_version) {
4234         case RTL_GIGA_MAC_VER_25:
4235         case RTL_GIGA_MAC_VER_26:
4236         case RTL_GIGA_MAC_VER_29:
4237         case RTL_GIGA_MAC_VER_30:
4238         case RTL_GIGA_MAC_VER_32:
4239         case RTL_GIGA_MAC_VER_33:
4240         case RTL_GIGA_MAC_VER_34:
4241         case RTL_GIGA_MAC_VER_37 ... RTL_GIGA_MAC_VER_51:
4242                 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) |
4243                         AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
4244                 break;
4245         default:
4246                 break;
4247         }
4248 }
4249
4250 static void r8168_pll_power_down(struct rtl8169_private *tp)
4251 {
4252         if (r8168_check_dash(tp))
4253                 return;
4254
4255         if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
4256             tp->mac_version == RTL_GIGA_MAC_VER_33)
4257                 rtl_ephy_write(tp, 0x19, 0xff64);
4258
4259         if (device_may_wakeup(tp_to_dev(tp))) {
4260                 phy_speed_down(tp->phydev, false);
4261                 rtl_wol_suspend_quirk(tp);
4262                 return;
4263         }
4264
4265         switch (tp->mac_version) {
4266         case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_33:
4267         case RTL_GIGA_MAC_VER_37:
4268         case RTL_GIGA_MAC_VER_39:
4269         case RTL_GIGA_MAC_VER_43:
4270         case RTL_GIGA_MAC_VER_44:
4271         case RTL_GIGA_MAC_VER_45:
4272         case RTL_GIGA_MAC_VER_46:
4273         case RTL_GIGA_MAC_VER_47:
4274         case RTL_GIGA_MAC_VER_48:
4275         case RTL_GIGA_MAC_VER_50:
4276         case RTL_GIGA_MAC_VER_51:
4277                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80);
4278                 break;
4279         case RTL_GIGA_MAC_VER_40:
4280         case RTL_GIGA_MAC_VER_41:
4281         case RTL_GIGA_MAC_VER_49:
4282                 rtl_w0w1_eri(tp, 0x1a8, ERIAR_MASK_1111, 0x00000000,
4283                              0xfc000000, ERIAR_EXGMAC);
4284                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80);
4285                 break;
4286         }
4287 }
4288
4289 static void r8168_pll_power_up(struct rtl8169_private *tp)
4290 {
4291         switch (tp->mac_version) {
4292         case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_33:
4293         case RTL_GIGA_MAC_VER_37:
4294         case RTL_GIGA_MAC_VER_39:
4295         case RTL_GIGA_MAC_VER_43:
4296                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0x80);
4297                 break;
4298         case RTL_GIGA_MAC_VER_44:
4299         case RTL_GIGA_MAC_VER_45:
4300         case RTL_GIGA_MAC_VER_46:
4301         case RTL_GIGA_MAC_VER_47:
4302         case RTL_GIGA_MAC_VER_48:
4303         case RTL_GIGA_MAC_VER_50:
4304         case RTL_GIGA_MAC_VER_51:
4305                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0);
4306                 break;
4307         case RTL_GIGA_MAC_VER_40:
4308         case RTL_GIGA_MAC_VER_41:
4309         case RTL_GIGA_MAC_VER_49:
4310                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0);
4311                 rtl_w0w1_eri(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000,
4312                              0x00000000, ERIAR_EXGMAC);
4313                 break;
4314         }
4315
4316         phy_resume(tp->phydev);
4317         /* give MAC/PHY some time to resume */
4318         msleep(20);
4319 }
4320
4321 static void rtl_pll_power_down(struct rtl8169_private *tp)
4322 {
4323         switch (tp->mac_version) {
4324         case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_06:
4325         case RTL_GIGA_MAC_VER_13 ... RTL_GIGA_MAC_VER_15:
4326                 break;
4327         default:
4328                 r8168_pll_power_down(tp);
4329         }
4330 }
4331
4332 static void rtl_pll_power_up(struct rtl8169_private *tp)
4333 {
4334         switch (tp->mac_version) {
4335         case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_06:
4336         case RTL_GIGA_MAC_VER_13 ... RTL_GIGA_MAC_VER_15:
4337                 break;
4338         default:
4339                 r8168_pll_power_up(tp);
4340         }
4341 }
4342
4343 static void rtl_init_rxcfg(struct rtl8169_private *tp)
4344 {
4345         switch (tp->mac_version) {
4346         case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_06:
4347         case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
4348                 RTL_W32(tp, RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
4349                 break;
4350         case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
4351         case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36:
4352         case RTL_GIGA_MAC_VER_38:
4353                 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
4354                 break;
4355         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
4356                 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF);
4357                 break;
4358         default:
4359                 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_DMA_BURST);
4360                 break;
4361         }
4362 }
4363
4364 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
4365 {
4366         tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0;
4367 }
4368
4369 static void rtl_hw_jumbo_enable(struct rtl8169_private *tp)
4370 {
4371         if (tp->jumbo_ops.enable) {
4372                 rtl_unlock_config_regs(tp);
4373                 tp->jumbo_ops.enable(tp);
4374                 rtl_lock_config_regs(tp);
4375         }
4376 }
4377
4378 static void rtl_hw_jumbo_disable(struct rtl8169_private *tp)
4379 {
4380         if (tp->jumbo_ops.disable) {
4381                 rtl_unlock_config_regs(tp);
4382                 tp->jumbo_ops.disable(tp);
4383                 rtl_lock_config_regs(tp);
4384         }
4385 }
4386
4387 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
4388 {
4389         RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
4390         RTL_W8(tp, Config4, RTL_R8(tp, Config4) | Jumbo_En1);
4391         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_512B);
4392 }
4393
4394 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
4395 {
4396         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
4397         RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~Jumbo_En1);
4398         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4399 }
4400
4401 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
4402 {
4403         RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
4404 }
4405
4406 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
4407 {
4408         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
4409 }
4410
4411 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
4412 {
4413         RTL_W8(tp, MaxTxPacketSize, 0x3f);
4414         RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
4415         RTL_W8(tp, Config4, RTL_R8(tp, Config4) | 0x01);
4416         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_512B);
4417 }
4418
4419 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
4420 {
4421         RTL_W8(tp, MaxTxPacketSize, 0x0c);
4422         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
4423         RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~0x01);
4424         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4425 }
4426
4427 static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp)
4428 {
4429         rtl_tx_performance_tweak(tp,
4430                 PCI_EXP_DEVCTL_READRQ_512B | PCI_EXP_DEVCTL_NOSNOOP_EN);
4431 }
4432
4433 static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp)
4434 {
4435         rtl_tx_performance_tweak(tp,
4436                 PCI_EXP_DEVCTL_READRQ_4096B | PCI_EXP_DEVCTL_NOSNOOP_EN);
4437 }
4438
4439 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
4440 {
4441         r8168b_0_hw_jumbo_enable(tp);
4442
4443         RTL_W8(tp, Config4, RTL_R8(tp, Config4) | (1 << 0));
4444 }
4445
4446 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
4447 {
4448         r8168b_0_hw_jumbo_disable(tp);
4449
4450         RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0));
4451 }
4452
4453 static void rtl_init_jumbo_ops(struct rtl8169_private *tp)
4454 {
4455         struct jumbo_ops *ops = &tp->jumbo_ops;
4456
4457         switch (tp->mac_version) {
4458         case RTL_GIGA_MAC_VER_11:
4459                 ops->disable    = r8168b_0_hw_jumbo_disable;
4460                 ops->enable     = r8168b_0_hw_jumbo_enable;
4461                 break;
4462         case RTL_GIGA_MAC_VER_12:
4463         case RTL_GIGA_MAC_VER_17:
4464                 ops->disable    = r8168b_1_hw_jumbo_disable;
4465                 ops->enable     = r8168b_1_hw_jumbo_enable;
4466                 break;
4467         case RTL_GIGA_MAC_VER_18: /* Wild guess. Needs info from Realtek. */
4468         case RTL_GIGA_MAC_VER_19:
4469         case RTL_GIGA_MAC_VER_20:
4470         case RTL_GIGA_MAC_VER_21: /* Wild guess. Needs info from Realtek. */
4471         case RTL_GIGA_MAC_VER_22:
4472         case RTL_GIGA_MAC_VER_23:
4473         case RTL_GIGA_MAC_VER_24:
4474         case RTL_GIGA_MAC_VER_25:
4475         case RTL_GIGA_MAC_VER_26:
4476                 ops->disable    = r8168c_hw_jumbo_disable;
4477                 ops->enable     = r8168c_hw_jumbo_enable;
4478                 break;
4479         case RTL_GIGA_MAC_VER_27:
4480         case RTL_GIGA_MAC_VER_28:
4481                 ops->disable    = r8168dp_hw_jumbo_disable;
4482                 ops->enable     = r8168dp_hw_jumbo_enable;
4483                 break;
4484         case RTL_GIGA_MAC_VER_31: /* Wild guess. Needs info from Realtek. */
4485         case RTL_GIGA_MAC_VER_32:
4486         case RTL_GIGA_MAC_VER_33:
4487         case RTL_GIGA_MAC_VER_34:
4488                 ops->disable    = r8168e_hw_jumbo_disable;
4489                 ops->enable     = r8168e_hw_jumbo_enable;
4490                 break;
4491
4492         /*
4493          * No action needed for jumbo frames with 8169.
4494          * No jumbo for 810x at all.
4495          */
4496         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
4497         default:
4498                 ops->disable    = NULL;
4499                 ops->enable     = NULL;
4500                 break;
4501         }
4502 }
4503
4504 DECLARE_RTL_COND(rtl_chipcmd_cond)
4505 {
4506         return RTL_R8(tp, ChipCmd) & CmdReset;
4507 }
4508
4509 static void rtl_hw_reset(struct rtl8169_private *tp)
4510 {
4511         RTL_W8(tp, ChipCmd, CmdReset);
4512
4513         rtl_udelay_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100);
4514 }
4515
4516 static void rtl_request_firmware(struct rtl8169_private *tp)
4517 {
4518         struct rtl_fw *rtl_fw;
4519         int rc = -ENOMEM;
4520
4521         /* firmware loaded already or no firmware available */
4522         if (tp->rtl_fw || !tp->fw_name)
4523                 return;
4524
4525         rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
4526         if (!rtl_fw)
4527                 goto err_warn;
4528
4529         rc = request_firmware(&rtl_fw->fw, tp->fw_name, tp_to_dev(tp));
4530         if (rc < 0)
4531                 goto err_free;
4532
4533         rc = rtl_check_firmware(tp, rtl_fw);
4534         if (rc < 0)
4535                 goto err_release_firmware;
4536
4537         tp->rtl_fw = rtl_fw;
4538
4539         return;
4540
4541 err_release_firmware:
4542         release_firmware(rtl_fw->fw);
4543 err_free:
4544         kfree(rtl_fw);
4545 err_warn:
4546         netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n",
4547                    tp->fw_name, rc);
4548 }
4549
4550 static void rtl_rx_close(struct rtl8169_private *tp)
4551 {
4552         RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
4553 }
4554
4555 DECLARE_RTL_COND(rtl_npq_cond)
4556 {
4557         return RTL_R8(tp, TxPoll) & NPQ;
4558 }
4559
4560 DECLARE_RTL_COND(rtl_txcfg_empty_cond)
4561 {
4562         return RTL_R32(tp, TxConfig) & TXCFG_EMPTY;
4563 }
4564
4565 static void rtl8169_hw_reset(struct rtl8169_private *tp)
4566 {
4567         /* Disable interrupts */
4568         rtl8169_irq_mask_and_ack(tp);
4569
4570         rtl_rx_close(tp);
4571
4572         switch (tp->mac_version) {
4573         case RTL_GIGA_MAC_VER_27:
4574         case RTL_GIGA_MAC_VER_28:
4575         case RTL_GIGA_MAC_VER_31:
4576                 rtl_udelay_loop_wait_low(tp, &rtl_npq_cond, 20, 42*42);
4577                 break;
4578         case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
4579         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
4580                 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
4581                 rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);
4582                 break;
4583         default:
4584                 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
4585                 udelay(100);
4586                 break;
4587         }
4588
4589         rtl_hw_reset(tp);
4590 }
4591
4592 static void rtl_set_tx_config_registers(struct rtl8169_private *tp)
4593 {
4594         u32 val = TX_DMA_BURST << TxDMAShift |
4595                   InterFrameGap << TxInterFrameGapShift;
4596
4597         if (tp->mac_version >= RTL_GIGA_MAC_VER_34 &&
4598             tp->mac_version != RTL_GIGA_MAC_VER_39)
4599                 val |= TXCFG_AUTO_FIFO;
4600
4601         RTL_W32(tp, TxConfig, val);
4602 }
4603
4604 static void rtl_set_rx_max_size(struct rtl8169_private *tp)
4605 {
4606         /* Low hurts. Let's disable the filtering. */
4607         RTL_W16(tp, RxMaxSize, R8169_RX_BUF_SIZE + 1);
4608 }
4609
4610 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp)
4611 {
4612         /*
4613          * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
4614          * register to be written before TxDescAddrLow to work.
4615          * Switching from MMIO to I/O access fixes the issue as well.
4616          */
4617         RTL_W32(tp, TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
4618         RTL_W32(tp, TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
4619         RTL_W32(tp, RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
4620         RTL_W32(tp, RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
4621 }
4622
4623 static void rtl8169_set_magic_reg(struct rtl8169_private *tp, unsigned mac_version)
4624 {
4625         u32 val;
4626
4627         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
4628                 val = 0x000fff00;
4629         else if (tp->mac_version == RTL_GIGA_MAC_VER_06)
4630                 val = 0x00ffff00;
4631         else
4632                 return;
4633
4634         if (RTL_R8(tp, Config2) & PCI_Clock_66MHz)
4635                 val |= 0xff;
4636
4637         RTL_W32(tp, 0x7c, val);
4638 }
4639
4640 static void rtl_set_rx_mode(struct net_device *dev)
4641 {
4642         struct rtl8169_private *tp = netdev_priv(dev);
4643         u32 mc_filter[2];       /* Multicast hash filter */
4644         int rx_mode;
4645         u32 tmp = 0;
4646
4647         if (dev->flags & IFF_PROMISC) {
4648                 /* Unconditionally log net taps. */
4649                 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
4650                 rx_mode =
4651                     AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
4652                     AcceptAllPhys;
4653                 mc_filter[1] = mc_filter[0] = 0xffffffff;
4654         } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
4655                    (dev->flags & IFF_ALLMULTI)) {
4656                 /* Too many to filter perfectly -- accept all multicasts. */
4657                 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
4658                 mc_filter[1] = mc_filter[0] = 0xffffffff;
4659         } else {
4660                 struct netdev_hw_addr *ha;
4661
4662                 rx_mode = AcceptBroadcast | AcceptMyPhys;
4663                 mc_filter[1] = mc_filter[0] = 0;
4664                 netdev_for_each_mc_addr(ha, dev) {
4665                         int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
4666                         mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
4667                         rx_mode |= AcceptMulticast;
4668                 }
4669         }
4670
4671         if (dev->features & NETIF_F_RXALL)
4672                 rx_mode |= (AcceptErr | AcceptRunt);
4673
4674         tmp = (RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK) | rx_mode;
4675
4676         if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
4677                 u32 data = mc_filter[0];
4678
4679                 mc_filter[0] = swab32(mc_filter[1]);
4680                 mc_filter[1] = swab32(data);
4681         }
4682
4683         if (tp->mac_version == RTL_GIGA_MAC_VER_35)
4684                 mc_filter[1] = mc_filter[0] = 0xffffffff;
4685
4686         RTL_W32(tp, MAR0 + 4, mc_filter[1]);
4687         RTL_W32(tp, MAR0 + 0, mc_filter[0]);
4688
4689         RTL_W32(tp, RxConfig, tmp);
4690 }
4691
4692 static void rtl_hw_start(struct  rtl8169_private *tp)
4693 {
4694         rtl_unlock_config_regs(tp);
4695
4696         tp->hw_start(tp);
4697
4698         rtl_set_rx_max_size(tp);
4699         rtl_set_rx_tx_desc_registers(tp);
4700         rtl_lock_config_regs(tp);
4701
4702         /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
4703         RTL_R8(tp, IntrMask);
4704         RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb);
4705         rtl_init_rxcfg(tp);
4706         rtl_set_tx_config_registers(tp);
4707
4708         rtl_set_rx_mode(tp->dev);
4709         /* no early-rx interrupts */
4710         RTL_W16(tp, MultiIntr, RTL_R16(tp, MultiIntr) & 0xf000);
4711         rtl_irq_enable(tp);
4712 }
4713
4714 static void rtl_hw_start_8169(struct rtl8169_private *tp)
4715 {
4716         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
4717                 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4718
4719         RTL_W8(tp, EarlyTxThres, NoEarlyTx);
4720
4721         tp->cp_cmd |= PCIMulRW;
4722
4723         if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4724             tp->mac_version == RTL_GIGA_MAC_VER_03) {
4725                 netif_dbg(tp, drv, tp->dev,
4726                           "Set MAC Reg C+CR Offset 0xe0. Bit 3 and Bit 14 MUST be 1\n");
4727                 tp->cp_cmd |= (1 << 14);
4728         }
4729
4730         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4731
4732         rtl8169_set_magic_reg(tp, tp->mac_version);
4733
4734         /*
4735          * Undocumented corner. Supposedly:
4736          * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
4737          */
4738         RTL_W16(tp, IntrMitigate, 0x0000);
4739
4740         RTL_W32(tp, RxMissed, 0);
4741 }
4742
4743 DECLARE_RTL_COND(rtl_csiar_cond)
4744 {
4745         return RTL_R32(tp, CSIAR) & CSIAR_FLAG;
4746 }
4747
4748 static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)
4749 {
4750         u32 func = PCI_FUNC(tp->pci_dev->devfn);
4751
4752         RTL_W32(tp, CSIDR, value);
4753         RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
4754                 CSIAR_BYTE_ENABLE | func << 16);
4755
4756         rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
4757 }
4758
4759 static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)
4760 {
4761         u32 func = PCI_FUNC(tp->pci_dev->devfn);
4762
4763         RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) | func << 16 |
4764                 CSIAR_BYTE_ENABLE);
4765
4766         return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
4767                 RTL_R32(tp, CSIDR) : ~0;
4768 }
4769
4770 static void rtl_csi_access_enable(struct rtl8169_private *tp, u8 val)
4771 {
4772         struct pci_dev *pdev = tp->pci_dev;
4773         u32 csi;
4774
4775         /* According to Realtek the value at config space address 0x070f
4776          * controls the L0s/L1 entrance latency. We try standard ECAM access
4777          * first and if it fails fall back to CSI.
4778          */
4779         if (pdev->cfg_size > 0x070f &&
4780             pci_write_config_byte(pdev, 0x070f, val) == PCIBIOS_SUCCESSFUL)
4781                 return;
4782
4783         netdev_notice_once(tp->dev,
4784                 "No native access to PCI extended config space, falling back to CSI\n");
4785         csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff;
4786         rtl_csi_write(tp, 0x070c, csi | val << 24);
4787 }
4788
4789 static void rtl_set_def_aspm_entry_latency(struct rtl8169_private *tp)
4790 {
4791         rtl_csi_access_enable(tp, 0x27);
4792 }
4793
4794 struct ephy_info {
4795         unsigned int offset;
4796         u16 mask;
4797         u16 bits;
4798 };
4799
4800 static void rtl_ephy_init(struct rtl8169_private *tp, const struct ephy_info *e,
4801                           int len)
4802 {
4803         u16 w;
4804
4805         while (len-- > 0) {
4806                 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits;
4807                 rtl_ephy_write(tp, e->offset, w);
4808                 e++;
4809         }
4810 }
4811
4812 static void rtl_disable_clock_request(struct rtl8169_private *tp)
4813 {
4814         pcie_capability_clear_word(tp->pci_dev, PCI_EXP_LNKCTL,
4815                                    PCI_EXP_LNKCTL_CLKREQ_EN);
4816 }
4817
4818 static void rtl_enable_clock_request(struct rtl8169_private *tp)
4819 {
4820         pcie_capability_set_word(tp->pci_dev, PCI_EXP_LNKCTL,
4821                                  PCI_EXP_LNKCTL_CLKREQ_EN);
4822 }
4823
4824 static void rtl_pcie_state_l2l3_disable(struct rtl8169_private *tp)
4825 {
4826         /* work around an issue when PCI reset occurs during L2/L3 state */
4827         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Rdy_to_L23);
4828 }
4829
4830 static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable)
4831 {
4832         if (enable) {
4833                 RTL_W8(tp, Config5, RTL_R8(tp, Config5) | ASPM_en);
4834                 RTL_W8(tp, Config2, RTL_R8(tp, Config2) | ClkReqEn);
4835         } else {
4836                 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
4837                 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
4838         }
4839
4840         udelay(10);
4841 }
4842
4843 static void rtl_hw_start_8168bb(struct rtl8169_private *tp)
4844 {
4845         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4846
4847         tp->cp_cmd &= CPCMD_QUIRK_MASK;
4848         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4849
4850         if (tp->dev->mtu <= ETH_DATA_LEN) {
4851                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B |
4852                                          PCI_EXP_DEVCTL_NOSNOOP_EN);
4853         }
4854 }
4855
4856 static void rtl_hw_start_8168bef(struct rtl8169_private *tp)
4857 {
4858         rtl_hw_start_8168bb(tp);
4859
4860         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4861
4862         RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0));
4863 }
4864
4865 static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)
4866 {
4867         RTL_W8(tp, Config1, RTL_R8(tp, Config1) | Speed_down);
4868
4869         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4870
4871         if (tp->dev->mtu <= ETH_DATA_LEN)
4872                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4873
4874         rtl_disable_clock_request(tp);
4875
4876         tp->cp_cmd &= CPCMD_QUIRK_MASK;
4877         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4878 }
4879
4880 static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp)
4881 {
4882         static const struct ephy_info e_info_8168cp[] = {
4883                 { 0x01, 0,      0x0001 },
4884                 { 0x02, 0x0800, 0x1000 },
4885                 { 0x03, 0,      0x0042 },
4886                 { 0x06, 0x0080, 0x0000 },
4887                 { 0x07, 0,      0x2000 }
4888         };
4889
4890         rtl_set_def_aspm_entry_latency(tp);
4891
4892         rtl_ephy_init(tp, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
4893
4894         __rtl_hw_start_8168cp(tp);
4895 }
4896
4897 static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)
4898 {
4899         rtl_set_def_aspm_entry_latency(tp);
4900
4901         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4902
4903         if (tp->dev->mtu <= ETH_DATA_LEN)
4904                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4905
4906         tp->cp_cmd &= CPCMD_QUIRK_MASK;
4907         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4908 }
4909
4910 static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)
4911 {
4912         rtl_set_def_aspm_entry_latency(tp);
4913
4914         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4915
4916         /* Magic. */
4917         RTL_W8(tp, DBG_REG, 0x20);
4918
4919         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4920
4921         if (tp->dev->mtu <= ETH_DATA_LEN)
4922                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4923
4924         tp->cp_cmd &= CPCMD_QUIRK_MASK;
4925         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4926 }
4927
4928 static void rtl_hw_start_8168c_1(struct rtl8169_private *tp)
4929 {
4930         static const struct ephy_info e_info_8168c_1[] = {
4931                 { 0x02, 0x0800, 0x1000 },
4932                 { 0x03, 0,      0x0002 },
4933                 { 0x06, 0x0080, 0x0000 }
4934         };
4935
4936         rtl_set_def_aspm_entry_latency(tp);
4937
4938         RTL_W8(tp, DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
4939
4940         rtl_ephy_init(tp, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
4941
4942         __rtl_hw_start_8168cp(tp);
4943 }
4944
4945 static void rtl_hw_start_8168c_2(struct rtl8169_private *tp)
4946 {
4947         static const struct ephy_info e_info_8168c_2[] = {
4948                 { 0x01, 0,      0x0001 },
4949                 { 0x03, 0x0400, 0x0220 }
4950         };
4951
4952         rtl_set_def_aspm_entry_latency(tp);
4953
4954         rtl_ephy_init(tp, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
4955
4956         __rtl_hw_start_8168cp(tp);
4957 }
4958
4959 static void rtl_hw_start_8168c_3(struct rtl8169_private *tp)
4960 {
4961         rtl_hw_start_8168c_2(tp);
4962 }
4963
4964 static void rtl_hw_start_8168c_4(struct rtl8169_private *tp)
4965 {
4966         rtl_set_def_aspm_entry_latency(tp);
4967
4968         __rtl_hw_start_8168cp(tp);
4969 }
4970
4971 static void rtl_hw_start_8168d(struct rtl8169_private *tp)
4972 {
4973         rtl_set_def_aspm_entry_latency(tp);
4974
4975         rtl_disable_clock_request(tp);
4976
4977         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4978
4979         if (tp->dev->mtu <= ETH_DATA_LEN)
4980                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4981
4982         tp->cp_cmd &= CPCMD_QUIRK_MASK;
4983         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4984 }
4985
4986 static void rtl_hw_start_8168dp(struct rtl8169_private *tp)
4987 {
4988         rtl_set_def_aspm_entry_latency(tp);
4989
4990         if (tp->dev->mtu <= ETH_DATA_LEN)
4991                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4992
4993         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4994
4995         rtl_disable_clock_request(tp);
4996 }
4997
4998 static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
4999 {
5000         static const struct ephy_info e_info_8168d_4[] = {
5001                 { 0x0b, 0x0000, 0x0048 },
5002                 { 0x19, 0x0020, 0x0050 },
5003                 { 0x0c, 0x0100, 0x0020 }
5004         };
5005
5006         rtl_set_def_aspm_entry_latency(tp);
5007
5008         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5009
5010         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
5011
5012         rtl_ephy_init(tp, e_info_8168d_4, ARRAY_SIZE(e_info_8168d_4));
5013
5014         rtl_enable_clock_request(tp);
5015 }
5016
5017 static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)
5018 {
5019         static const struct ephy_info e_info_8168e_1[] = {
5020                 { 0x00, 0x0200, 0x0100 },
5021                 { 0x00, 0x0000, 0x0004 },
5022                 { 0x06, 0x0002, 0x0001 },
5023                 { 0x06, 0x0000, 0x0030 },
5024                 { 0x07, 0x0000, 0x2000 },
5025                 { 0x00, 0x0000, 0x0020 },
5026                 { 0x03, 0x5800, 0x2000 },
5027                 { 0x03, 0x0000, 0x0001 },
5028                 { 0x01, 0x0800, 0x1000 },
5029                 { 0x07, 0x0000, 0x4000 },
5030                 { 0x1e, 0x0000, 0x2000 },
5031                 { 0x19, 0xffff, 0xfe6c },
5032                 { 0x0a, 0x0000, 0x0040 }
5033         };
5034
5035         rtl_set_def_aspm_entry_latency(tp);
5036
5037         rtl_ephy_init(tp, e_info_8168e_1, ARRAY_SIZE(e_info_8168e_1));
5038
5039         if (tp->dev->mtu <= ETH_DATA_LEN)
5040                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5041
5042         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
5043
5044         rtl_disable_clock_request(tp);
5045
5046         /* Reset tx FIFO pointer */
5047         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | TXPLA_RST);
5048         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~TXPLA_RST);
5049
5050         RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
5051 }
5052
5053 static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
5054 {
5055         static const struct ephy_info e_info_8168e_2[] = {
5056                 { 0x09, 0x0000, 0x0080 },
5057                 { 0x19, 0x0000, 0x0224 }
5058         };
5059
5060         rtl_set_def_aspm_entry_latency(tp);
5061
5062         rtl_ephy_init(tp, e_info_8168e_2, ARRAY_SIZE(e_info_8168e_2));
5063
5064         if (tp->dev->mtu <= ETH_DATA_LEN)
5065                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5066
5067         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5068         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5069         rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
5070         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5071         rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
5072         rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060, ERIAR_EXGMAC);
5073         rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5074         rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
5075
5076         RTL_W8(tp, MaxTxPacketSize, EarlySize);
5077
5078         rtl_disable_clock_request(tp);
5079
5080         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
5081
5082         /* Adjust EEE LED frequency */
5083         RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
5084
5085         rtl8168_config_eee_mac(tp);
5086
5087         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
5088         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
5089         RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
5090
5091         rtl_hw_aspm_clkreq_enable(tp, true);
5092 }
5093
5094 static void rtl_hw_start_8168f(struct rtl8169_private *tp)
5095 {
5096         rtl_set_def_aspm_entry_latency(tp);
5097
5098         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5099
5100         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5101         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5102         rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
5103         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5104         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5105         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5106         rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5107         rtl_w0w1_eri(tp, 0x1d0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5108         rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
5109         rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060, ERIAR_EXGMAC);
5110
5111         RTL_W8(tp, MaxTxPacketSize, EarlySize);
5112
5113         rtl_disable_clock_request(tp);
5114
5115         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
5116         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
5117         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
5118         RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
5119
5120         rtl8168_config_eee_mac(tp);
5121 }
5122
5123 static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
5124 {
5125         static const struct ephy_info e_info_8168f_1[] = {
5126                 { 0x06, 0x00c0, 0x0020 },
5127                 { 0x08, 0x0001, 0x0002 },
5128                 { 0x09, 0x0000, 0x0080 },
5129                 { 0x19, 0x0000, 0x0224 }
5130         };
5131
5132         rtl_hw_start_8168f(tp);
5133
5134         rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
5135
5136         rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
5137
5138         /* Adjust EEE LED frequency */
5139         RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
5140 }
5141
5142 static void rtl_hw_start_8411(struct rtl8169_private *tp)
5143 {
5144         static const struct ephy_info e_info_8168f_1[] = {
5145                 { 0x06, 0x00c0, 0x0020 },
5146                 { 0x0f, 0xffff, 0x5200 },
5147                 { 0x1e, 0x0000, 0x4000 },
5148                 { 0x19, 0x0000, 0x0224 }
5149         };
5150
5151         rtl_hw_start_8168f(tp);
5152         rtl_pcie_state_l2l3_disable(tp);
5153
5154         rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
5155
5156         rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0x0000, ERIAR_EXGMAC);
5157 }
5158
5159 static void rtl_hw_start_8168g(struct rtl8169_private *tp)
5160 {
5161         rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x080002, ERIAR_EXGMAC);
5162         rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
5163         rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
5164         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5165
5166         rtl_set_def_aspm_entry_latency(tp);
5167
5168         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5169
5170         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5171         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5172         rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f, ERIAR_EXGMAC);
5173
5174         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
5175         RTL_W8(tp, MaxTxPacketSize, EarlySize);
5176
5177         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5178         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5179
5180         /* Adjust EEE LED frequency */
5181         RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
5182
5183         rtl8168_config_eee_mac(tp);
5184
5185         rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06, ERIAR_EXGMAC);
5186         rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC);
5187
5188         rtl_pcie_state_l2l3_disable(tp);
5189 }
5190
5191 static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
5192 {
5193         static const struct ephy_info e_info_8168g_1[] = {
5194                 { 0x00, 0x0000, 0x0008 },
5195                 { 0x0c, 0x37d0, 0x0820 },
5196                 { 0x1e, 0x0000, 0x0001 },
5197                 { 0x19, 0x8000, 0x0000 }
5198         };
5199
5200         rtl_hw_start_8168g(tp);
5201
5202         /* disable aspm and clock request before access ephy */
5203         rtl_hw_aspm_clkreq_enable(tp, false);
5204         rtl_ephy_init(tp, e_info_8168g_1, ARRAY_SIZE(e_info_8168g_1));
5205         rtl_hw_aspm_clkreq_enable(tp, true);
5206 }
5207
5208 static void rtl_hw_start_8168g_2(struct rtl8169_private *tp)
5209 {
5210         static const struct ephy_info e_info_8168g_2[] = {
5211                 { 0x00, 0x0000, 0x0008 },
5212                 { 0x0c, 0x3df0, 0x0200 },
5213                 { 0x19, 0xffff, 0xfc00 },
5214                 { 0x1e, 0xffff, 0x20eb }
5215         };
5216
5217         rtl_hw_start_8168g(tp);
5218
5219         /* disable aspm and clock request before access ephy */
5220         RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
5221         RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
5222         rtl_ephy_init(tp, e_info_8168g_2, ARRAY_SIZE(e_info_8168g_2));
5223 }
5224
5225 static void rtl_hw_start_8411_2(struct rtl8169_private *tp)
5226 {
5227         static const struct ephy_info e_info_8411_2[] = {
5228                 { 0x00, 0x0000, 0x0008 },
5229                 { 0x0c, 0x3df0, 0x0200 },
5230                 { 0x0f, 0xffff, 0x5200 },
5231                 { 0x19, 0x0020, 0x0000 },
5232                 { 0x1e, 0x0000, 0x2000 }
5233         };
5234
5235         rtl_hw_start_8168g(tp);
5236
5237         /* disable aspm and clock request before access ephy */
5238         rtl_hw_aspm_clkreq_enable(tp, false);
5239         rtl_ephy_init(tp, e_info_8411_2, ARRAY_SIZE(e_info_8411_2));
5240         rtl_hw_aspm_clkreq_enable(tp, true);
5241 }
5242
5243 static void rtl_hw_start_8168h_1(struct rtl8169_private *tp)
5244 {
5245         int rg_saw_cnt;
5246         u32 data;
5247         static const struct ephy_info e_info_8168h_1[] = {
5248                 { 0x1e, 0x0800, 0x0001 },
5249                 { 0x1d, 0x0000, 0x0800 },
5250                 { 0x05, 0xffff, 0x2089 },
5251                 { 0x06, 0xffff, 0x5881 },
5252                 { 0x04, 0xffff, 0x154a },
5253                 { 0x01, 0xffff, 0x068b }
5254         };
5255
5256         /* disable aspm and clock request before access ephy */
5257         rtl_hw_aspm_clkreq_enable(tp, false);
5258         rtl_ephy_init(tp, e_info_8168h_1, ARRAY_SIZE(e_info_8168h_1));
5259
5260         rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x00080002, ERIAR_EXGMAC);
5261         rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
5262         rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
5263         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5264
5265         rtl_set_def_aspm_entry_latency(tp);
5266
5267         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5268
5269         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5270         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5271
5272         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_1111, 0x0010, 0x00, ERIAR_EXGMAC);
5273
5274         rtl_w0w1_eri(tp, 0xd4, ERIAR_MASK_1111, 0x1f00, 0x00, ERIAR_EXGMAC);
5275
5276         rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87, ERIAR_EXGMAC);
5277
5278         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
5279         RTL_W8(tp, MaxTxPacketSize, EarlySize);
5280
5281         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5282         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5283
5284         /* Adjust EEE LED frequency */
5285         RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
5286
5287         rtl8168_config_eee_mac(tp);
5288
5289         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5290         RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
5291
5292         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
5293
5294         rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC);
5295
5296         rtl_pcie_state_l2l3_disable(tp);
5297
5298         rtl_writephy(tp, 0x1f, 0x0c42);
5299         rg_saw_cnt = (rtl_readphy(tp, 0x13) & 0x3fff);
5300         rtl_writephy(tp, 0x1f, 0x0000);
5301         if (rg_saw_cnt > 0) {
5302                 u16 sw_cnt_1ms_ini;
5303
5304                 sw_cnt_1ms_ini = 16000000/rg_saw_cnt;
5305                 sw_cnt_1ms_ini &= 0x0fff;
5306                 data = r8168_mac_ocp_read(tp, 0xd412);
5307                 data &= ~0x0fff;
5308                 data |= sw_cnt_1ms_ini;
5309                 r8168_mac_ocp_write(tp, 0xd412, data);
5310         }
5311
5312         data = r8168_mac_ocp_read(tp, 0xe056);
5313         data &= ~0xf0;
5314         data |= 0x70;
5315         r8168_mac_ocp_write(tp, 0xe056, data);
5316
5317         data = r8168_mac_ocp_read(tp, 0xe052);
5318         data &= ~0x6000;
5319         data |= 0x8008;
5320         r8168_mac_ocp_write(tp, 0xe052, data);
5321
5322         data = r8168_mac_ocp_read(tp, 0xe0d6);
5323         data &= ~0x01ff;
5324         data |= 0x017f;
5325         r8168_mac_ocp_write(tp, 0xe0d6, data);
5326
5327         data = r8168_mac_ocp_read(tp, 0xd420);
5328         data &= ~0x0fff;
5329         data |= 0x047f;
5330         r8168_mac_ocp_write(tp, 0xd420, data);
5331
5332         r8168_mac_ocp_write(tp, 0xe63e, 0x0001);
5333         r8168_mac_ocp_write(tp, 0xe63e, 0x0000);
5334         r8168_mac_ocp_write(tp, 0xc094, 0x0000);
5335         r8168_mac_ocp_write(tp, 0xc09e, 0x0000);
5336
5337         rtl_hw_aspm_clkreq_enable(tp, true);
5338 }
5339
5340 static void rtl_hw_start_8168ep(struct rtl8169_private *tp)
5341 {
5342         rtl8168ep_stop_cmac(tp);
5343
5344         rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x00080002, ERIAR_EXGMAC);
5345         rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x2f, ERIAR_EXGMAC);
5346         rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x5f, ERIAR_EXGMAC);
5347         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5348
5349         rtl_set_def_aspm_entry_latency(tp);
5350
5351         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5352
5353         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5354         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5355
5356         rtl_w0w1_eri(tp, 0xd4, ERIAR_MASK_1111, 0x1f80, 0x00, ERIAR_EXGMAC);
5357
5358         rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87, ERIAR_EXGMAC);
5359
5360         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
5361         RTL_W8(tp, MaxTxPacketSize, EarlySize);
5362
5363         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5364         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5365
5366         /* Adjust EEE LED frequency */
5367         RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
5368
5369         rtl8168_config_eee_mac(tp);
5370
5371         rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06, ERIAR_EXGMAC);
5372
5373         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
5374
5375         rtl_pcie_state_l2l3_disable(tp);
5376 }
5377
5378 static void rtl_hw_start_8168ep_1(struct rtl8169_private *tp)
5379 {
5380         static const struct ephy_info e_info_8168ep_1[] = {
5381                 { 0x00, 0xffff, 0x10ab },
5382                 { 0x06, 0xffff, 0xf030 },
5383                 { 0x08, 0xffff, 0x2006 },
5384                 { 0x0d, 0xffff, 0x1666 },
5385                 { 0x0c, 0x3ff0, 0x0000 }
5386         };
5387
5388         /* disable aspm and clock request before access ephy */
5389         rtl_hw_aspm_clkreq_enable(tp, false);
5390         rtl_ephy_init(tp, e_info_8168ep_1, ARRAY_SIZE(e_info_8168ep_1));
5391
5392         rtl_hw_start_8168ep(tp);
5393
5394         rtl_hw_aspm_clkreq_enable(tp, true);
5395 }
5396
5397 static void rtl_hw_start_8168ep_2(struct rtl8169_private *tp)
5398 {
5399         static const struct ephy_info e_info_8168ep_2[] = {
5400                 { 0x00, 0xffff, 0x10a3 },
5401                 { 0x19, 0xffff, 0xfc00 },
5402                 { 0x1e, 0xffff, 0x20ea }
5403         };
5404
5405         /* disable aspm and clock request before access ephy */
5406         rtl_hw_aspm_clkreq_enable(tp, false);
5407         rtl_ephy_init(tp, e_info_8168ep_2, ARRAY_SIZE(e_info_8168ep_2));
5408
5409         rtl_hw_start_8168ep(tp);
5410
5411         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5412         RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
5413
5414         rtl_hw_aspm_clkreq_enable(tp, true);
5415 }
5416
5417 static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp)
5418 {
5419         u32 data;
5420         static const struct ephy_info e_info_8168ep_3[] = {
5421                 { 0x00, 0xffff, 0x10a3 },
5422                 { 0x19, 0xffff, 0x7c00 },
5423                 { 0x1e, 0xffff, 0x20eb },
5424                 { 0x0d, 0xffff, 0x1666 }
5425         };
5426
5427         /* disable aspm and clock request before access ephy */
5428         rtl_hw_aspm_clkreq_enable(tp, false);
5429         rtl_ephy_init(tp, e_info_8168ep_3, ARRAY_SIZE(e_info_8168ep_3));
5430
5431         rtl_hw_start_8168ep(tp);
5432
5433         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5434         RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
5435
5436         data = r8168_mac_ocp_read(tp, 0xd3e2);
5437         data &= 0xf000;
5438         data |= 0x0271;
5439         r8168_mac_ocp_write(tp, 0xd3e2, data);
5440
5441         data = r8168_mac_ocp_read(tp, 0xd3e4);
5442         data &= 0xff00;
5443         r8168_mac_ocp_write(tp, 0xd3e4, data);
5444
5445         data = r8168_mac_ocp_read(tp, 0xe860);
5446         data |= 0x0080;
5447         r8168_mac_ocp_write(tp, 0xe860, data);
5448
5449         rtl_hw_aspm_clkreq_enable(tp, true);
5450 }
5451
5452 static void rtl_hw_start_8168(struct rtl8169_private *tp)
5453 {
5454         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
5455
5456         tp->cp_cmd &= ~INTT_MASK;
5457         tp->cp_cmd |= PktCntrDisable | INTT_1;
5458         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
5459
5460         RTL_W16(tp, IntrMitigate, 0x5151);
5461
5462         /* Work around for RxFIFO overflow. */
5463         if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
5464                 tp->irq_mask |= RxFIFOOver;
5465                 tp->irq_mask &= ~RxOverflow;
5466         }
5467
5468         switch (tp->mac_version) {
5469         case RTL_GIGA_MAC_VER_11:
5470                 rtl_hw_start_8168bb(tp);
5471                 break;
5472
5473         case RTL_GIGA_MAC_VER_12:
5474         case RTL_GIGA_MAC_VER_17:
5475                 rtl_hw_start_8168bef(tp);
5476                 break;
5477
5478         case RTL_GIGA_MAC_VER_18:
5479                 rtl_hw_start_8168cp_1(tp);
5480                 break;
5481
5482         case RTL_GIGA_MAC_VER_19:
5483                 rtl_hw_start_8168c_1(tp);
5484                 break;
5485
5486         case RTL_GIGA_MAC_VER_20:
5487                 rtl_hw_start_8168c_2(tp);
5488                 break;
5489
5490         case RTL_GIGA_MAC_VER_21:
5491                 rtl_hw_start_8168c_3(tp);
5492                 break;
5493
5494         case RTL_GIGA_MAC_VER_22:
5495                 rtl_hw_start_8168c_4(tp);
5496                 break;
5497
5498         case RTL_GIGA_MAC_VER_23:
5499                 rtl_hw_start_8168cp_2(tp);
5500                 break;
5501
5502         case RTL_GIGA_MAC_VER_24:
5503                 rtl_hw_start_8168cp_3(tp);
5504                 break;
5505
5506         case RTL_GIGA_MAC_VER_25:
5507         case RTL_GIGA_MAC_VER_26:
5508         case RTL_GIGA_MAC_VER_27:
5509                 rtl_hw_start_8168d(tp);
5510                 break;
5511
5512         case RTL_GIGA_MAC_VER_28:
5513                 rtl_hw_start_8168d_4(tp);
5514                 break;
5515
5516         case RTL_GIGA_MAC_VER_31:
5517                 rtl_hw_start_8168dp(tp);
5518                 break;
5519
5520         case RTL_GIGA_MAC_VER_32:
5521         case RTL_GIGA_MAC_VER_33:
5522                 rtl_hw_start_8168e_1(tp);
5523                 break;
5524         case RTL_GIGA_MAC_VER_34:
5525                 rtl_hw_start_8168e_2(tp);
5526                 break;
5527
5528         case RTL_GIGA_MAC_VER_35:
5529         case RTL_GIGA_MAC_VER_36:
5530                 rtl_hw_start_8168f_1(tp);
5531                 break;
5532
5533         case RTL_GIGA_MAC_VER_38:
5534                 rtl_hw_start_8411(tp);
5535                 break;
5536
5537         case RTL_GIGA_MAC_VER_40:
5538         case RTL_GIGA_MAC_VER_41:
5539                 rtl_hw_start_8168g_1(tp);
5540                 break;
5541         case RTL_GIGA_MAC_VER_42:
5542                 rtl_hw_start_8168g_2(tp);
5543                 break;
5544
5545         case RTL_GIGA_MAC_VER_44:
5546                 rtl_hw_start_8411_2(tp);
5547                 break;
5548
5549         case RTL_GIGA_MAC_VER_45:
5550         case RTL_GIGA_MAC_VER_46:
5551                 rtl_hw_start_8168h_1(tp);
5552                 break;
5553
5554         case RTL_GIGA_MAC_VER_49:
5555                 rtl_hw_start_8168ep_1(tp);
5556                 break;
5557
5558         case RTL_GIGA_MAC_VER_50:
5559                 rtl_hw_start_8168ep_2(tp);
5560                 break;
5561
5562         case RTL_GIGA_MAC_VER_51:
5563                 rtl_hw_start_8168ep_3(tp);
5564                 break;
5565
5566         default:
5567                 netif_err(tp, drv, tp->dev,
5568                           "unknown chipset (mac_version = %d)\n",
5569                           tp->mac_version);
5570                 break;
5571         }
5572 }
5573
5574 static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)
5575 {
5576         static const struct ephy_info e_info_8102e_1[] = {
5577                 { 0x01, 0, 0x6e65 },
5578                 { 0x02, 0, 0x091f },
5579                 { 0x03, 0, 0xc2f9 },
5580                 { 0x06, 0, 0xafb5 },
5581                 { 0x07, 0, 0x0e00 },
5582                 { 0x19, 0, 0xec80 },
5583                 { 0x01, 0, 0x2e65 },
5584                 { 0x01, 0, 0x6e65 }
5585         };
5586         u8 cfg1;
5587
5588         rtl_set_def_aspm_entry_latency(tp);
5589
5590         RTL_W8(tp, DBG_REG, FIX_NAK_1);
5591
5592         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5593
5594         RTL_W8(tp, Config1,
5595                LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
5596         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
5597
5598         cfg1 = RTL_R8(tp, Config1);
5599         if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
5600                 RTL_W8(tp, Config1, cfg1 & ~LEDS0);
5601
5602         rtl_ephy_init(tp, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
5603 }
5604
5605 static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)
5606 {
5607         rtl_set_def_aspm_entry_latency(tp);
5608
5609         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5610
5611         RTL_W8(tp, Config1, MEMMAP | IOMAP | VPD | PMEnable);
5612         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
5613 }
5614
5615 static void rtl_hw_start_8102e_3(struct rtl8169_private *tp)
5616 {
5617         rtl_hw_start_8102e_2(tp);
5618
5619         rtl_ephy_write(tp, 0x03, 0xc2f9);
5620 }
5621
5622 static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)
5623 {
5624         static const struct ephy_info e_info_8105e_1[] = {
5625                 { 0x07, 0, 0x4000 },
5626                 { 0x19, 0, 0x0200 },
5627                 { 0x19, 0, 0x0020 },
5628                 { 0x1e, 0, 0x2000 },
5629                 { 0x03, 0, 0x0001 },
5630                 { 0x19, 0, 0x0100 },
5631                 { 0x19, 0, 0x0004 },
5632                 { 0x0a, 0, 0x0020 }
5633         };
5634
5635         /* Force LAN exit from ASPM if Rx/Tx are not idle */
5636         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
5637
5638         /* Disable Early Tally Counter */
5639         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) & ~0x010000);
5640
5641         RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
5642         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
5643
5644         rtl_ephy_init(tp, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
5645
5646         rtl_pcie_state_l2l3_disable(tp);
5647 }
5648
5649 static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)
5650 {
5651         rtl_hw_start_8105e_1(tp);
5652         rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000);
5653 }
5654
5655 static void rtl_hw_start_8402(struct rtl8169_private *tp)
5656 {
5657         static const struct ephy_info e_info_8402[] = {
5658                 { 0x19, 0xffff, 0xff64 },
5659                 { 0x1e, 0, 0x4000 }
5660         };
5661
5662         rtl_set_def_aspm_entry_latency(tp);
5663
5664         /* Force LAN exit from ASPM if Rx/Tx are not idle */
5665         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
5666
5667         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
5668
5669         rtl_ephy_init(tp, e_info_8402, ARRAY_SIZE(e_info_8402));
5670
5671         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5672
5673         rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00000002, ERIAR_EXGMAC);
5674         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00000006, ERIAR_EXGMAC);
5675         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5676         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5677         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5678         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5679         rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0e00, 0xff00, ERIAR_EXGMAC);
5680
5681         rtl_pcie_state_l2l3_disable(tp);
5682 }
5683
5684 static void rtl_hw_start_8106(struct rtl8169_private *tp)
5685 {
5686         rtl_hw_aspm_clkreq_enable(tp, false);
5687
5688         /* Force LAN exit from ASPM if Rx/Tx are not idle */
5689         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
5690
5691         RTL_W32(tp, MISC, (RTL_R32(tp, MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);
5692         RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
5693         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5694
5695         rtl_pcie_state_l2l3_disable(tp);
5696         rtl_hw_aspm_clkreq_enable(tp, true);
5697 }
5698
5699 static void rtl_hw_start_8101(struct rtl8169_private *tp)
5700 {
5701         if (tp->mac_version >= RTL_GIGA_MAC_VER_30)
5702                 tp->irq_mask &= ~RxFIFOOver;
5703
5704         if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
5705             tp->mac_version == RTL_GIGA_MAC_VER_16)
5706                 pcie_capability_set_word(tp->pci_dev, PCI_EXP_DEVCTL,
5707                                          PCI_EXP_DEVCTL_NOSNOOP_EN);
5708
5709         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
5710
5711         tp->cp_cmd &= CPCMD_QUIRK_MASK;
5712         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
5713
5714         switch (tp->mac_version) {
5715         case RTL_GIGA_MAC_VER_07:
5716                 rtl_hw_start_8102e_1(tp);
5717                 break;
5718
5719         case RTL_GIGA_MAC_VER_08:
5720                 rtl_hw_start_8102e_3(tp);
5721                 break;
5722
5723         case RTL_GIGA_MAC_VER_09:
5724                 rtl_hw_start_8102e_2(tp);
5725                 break;
5726
5727         case RTL_GIGA_MAC_VER_29:
5728                 rtl_hw_start_8105e_1(tp);
5729                 break;
5730         case RTL_GIGA_MAC_VER_30:
5731                 rtl_hw_start_8105e_2(tp);
5732                 break;
5733
5734         case RTL_GIGA_MAC_VER_37:
5735                 rtl_hw_start_8402(tp);
5736                 break;
5737
5738         case RTL_GIGA_MAC_VER_39:
5739                 rtl_hw_start_8106(tp);
5740                 break;
5741         case RTL_GIGA_MAC_VER_43:
5742                 rtl_hw_start_8168g_2(tp);
5743                 break;
5744         case RTL_GIGA_MAC_VER_47:
5745         case RTL_GIGA_MAC_VER_48:
5746                 rtl_hw_start_8168h_1(tp);
5747                 break;
5748         }
5749
5750         RTL_W16(tp, IntrMitigate, 0x0000);
5751 }
5752
5753 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
5754 {
5755         struct rtl8169_private *tp = netdev_priv(dev);
5756
5757         if (new_mtu > ETH_DATA_LEN)
5758                 rtl_hw_jumbo_enable(tp);
5759         else
5760                 rtl_hw_jumbo_disable(tp);
5761
5762         dev->mtu = new_mtu;
5763         netdev_update_features(dev);
5764
5765         return 0;
5766 }
5767
5768 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
5769 {
5770         desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
5771         desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
5772 }
5773
5774 static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
5775                                      void **data_buff, struct RxDesc *desc)
5776 {
5777         dma_unmap_single(tp_to_dev(tp), le64_to_cpu(desc->addr),
5778                          R8169_RX_BUF_SIZE, DMA_FROM_DEVICE);
5779
5780         kfree(*data_buff);
5781         *data_buff = NULL;
5782         rtl8169_make_unusable_by_asic(desc);
5783 }
5784
5785 static inline void rtl8169_mark_to_asic(struct RxDesc *desc)
5786 {
5787         u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
5788
5789         /* Force memory writes to complete before releasing descriptor */
5790         dma_wmb();
5791
5792         desc->opts1 = cpu_to_le32(DescOwn | eor | R8169_RX_BUF_SIZE);
5793 }
5794
5795 static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
5796                                              struct RxDesc *desc)
5797 {
5798         void *data;
5799         dma_addr_t mapping;
5800         struct device *d = tp_to_dev(tp);
5801         int node = dev_to_node(d);
5802
5803         data = kmalloc_node(R8169_RX_BUF_SIZE, GFP_KERNEL, node);
5804         if (!data)
5805                 return NULL;
5806
5807         /* Memory should be properly aligned, but better check. */
5808         if (!IS_ALIGNED((unsigned long)data, 8)) {
5809                 netdev_err_once(tp->dev, "RX buffer not 8-byte-aligned\n");
5810                 goto err_out;
5811         }
5812
5813         mapping = dma_map_single(d, data, R8169_RX_BUF_SIZE, DMA_FROM_DEVICE);
5814         if (unlikely(dma_mapping_error(d, mapping))) {
5815                 if (net_ratelimit())
5816                         netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
5817                 goto err_out;
5818         }
5819
5820         desc->addr = cpu_to_le64(mapping);
5821         rtl8169_mark_to_asic(desc);
5822         return data;
5823
5824 err_out:
5825         kfree(data);
5826         return NULL;
5827 }
5828
5829 static void rtl8169_rx_clear(struct rtl8169_private *tp)
5830 {
5831         unsigned int i;
5832
5833         for (i = 0; i < NUM_RX_DESC; i++) {
5834                 if (tp->Rx_databuff[i]) {
5835                         rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
5836                                             tp->RxDescArray + i);
5837                 }
5838         }
5839 }
5840
5841 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
5842 {
5843         desc->opts1 |= cpu_to_le32(RingEnd);
5844 }
5845
5846 static int rtl8169_rx_fill(struct rtl8169_private *tp)
5847 {
5848         unsigned int i;
5849
5850         for (i = 0; i < NUM_RX_DESC; i++) {
5851                 void *data;
5852
5853                 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
5854                 if (!data) {
5855                         rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
5856                         goto err_out;
5857                 }
5858                 tp->Rx_databuff[i] = data;
5859         }
5860
5861         rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
5862         return 0;
5863
5864 err_out:
5865         rtl8169_rx_clear(tp);
5866         return -ENOMEM;
5867 }
5868
5869 static int rtl8169_init_ring(struct rtl8169_private *tp)
5870 {
5871         rtl8169_init_ring_indexes(tp);
5872
5873         memset(tp->tx_skb, 0, sizeof(tp->tx_skb));
5874         memset(tp->Rx_databuff, 0, sizeof(tp->Rx_databuff));
5875
5876         return rtl8169_rx_fill(tp);
5877 }
5878
5879 static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
5880                                  struct TxDesc *desc)
5881 {
5882         unsigned int len = tx_skb->len;
5883
5884         dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
5885
5886         desc->opts1 = 0x00;
5887         desc->opts2 = 0x00;
5888         desc->addr = 0x00;
5889         tx_skb->len = 0;
5890 }
5891
5892 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
5893                                    unsigned int n)
5894 {
5895         unsigned int i;
5896
5897         for (i = 0; i < n; i++) {
5898                 unsigned int entry = (start + i) % NUM_TX_DESC;
5899                 struct ring_info *tx_skb = tp->tx_skb + entry;
5900                 unsigned int len = tx_skb->len;
5901
5902                 if (len) {
5903                         struct sk_buff *skb = tx_skb->skb;
5904
5905                         rtl8169_unmap_tx_skb(tp_to_dev(tp), tx_skb,
5906                                              tp->TxDescArray + entry);
5907                         if (skb) {
5908                                 dev_consume_skb_any(skb);
5909                                 tx_skb->skb = NULL;
5910                         }
5911                 }
5912         }
5913 }
5914
5915 static void rtl8169_tx_clear(struct rtl8169_private *tp)
5916 {
5917         rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
5918         tp->cur_tx = tp->dirty_tx = 0;
5919         netdev_reset_queue(tp->dev);
5920 }
5921
5922 static void rtl_reset_work(struct rtl8169_private *tp)
5923 {
5924         struct net_device *dev = tp->dev;
5925         int i;
5926
5927         napi_disable(&tp->napi);
5928         netif_stop_queue(dev);
5929         synchronize_rcu();
5930
5931         rtl8169_hw_reset(tp);
5932
5933         for (i = 0; i < NUM_RX_DESC; i++)
5934                 rtl8169_mark_to_asic(tp->RxDescArray + i);
5935
5936         rtl8169_tx_clear(tp);
5937         rtl8169_init_ring_indexes(tp);
5938
5939         napi_enable(&tp->napi);
5940         rtl_hw_start(tp);
5941         netif_wake_queue(dev);
5942 }
5943
5944 static void rtl8169_tx_timeout(struct net_device *dev)
5945 {
5946         struct rtl8169_private *tp = netdev_priv(dev);
5947
5948         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
5949 }
5950
5951 static __le32 rtl8169_get_txd_opts1(u32 opts0, u32 len, unsigned int entry)
5952 {
5953         u32 status = opts0 | len;
5954
5955         if (entry == NUM_TX_DESC - 1)
5956                 status |= RingEnd;
5957
5958         return cpu_to_le32(status);
5959 }
5960
5961 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
5962                               u32 *opts)
5963 {
5964         struct skb_shared_info *info = skb_shinfo(skb);
5965         unsigned int cur_frag, entry;
5966         struct TxDesc *uninitialized_var(txd);
5967         struct device *d = tp_to_dev(tp);
5968
5969         entry = tp->cur_tx;
5970         for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
5971                 const skb_frag_t *frag = info->frags + cur_frag;
5972                 dma_addr_t mapping;
5973                 u32 len;
5974                 void *addr;
5975
5976                 entry = (entry + 1) % NUM_TX_DESC;
5977
5978                 txd = tp->TxDescArray + entry;
5979                 len = skb_frag_size(frag);
5980                 addr = skb_frag_address(frag);
5981                 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
5982                 if (unlikely(dma_mapping_error(d, mapping))) {
5983                         if (net_ratelimit())
5984                                 netif_err(tp, drv, tp->dev,
5985                                           "Failed to map TX fragments DMA!\n");
5986                         goto err_out;
5987                 }
5988
5989                 txd->opts1 = rtl8169_get_txd_opts1(opts[0], len, entry);
5990                 txd->opts2 = cpu_to_le32(opts[1]);
5991                 txd->addr = cpu_to_le64(mapping);
5992
5993                 tp->tx_skb[entry].len = len;
5994         }
5995
5996         if (cur_frag) {
5997                 tp->tx_skb[entry].skb = skb;
5998                 txd->opts1 |= cpu_to_le32(LastFrag);
5999         }
6000
6001         return cur_frag;
6002
6003 err_out:
6004         rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
6005         return -EIO;
6006 }
6007
6008 static bool rtl_test_hw_pad_bug(struct rtl8169_private *tp, struct sk_buff *skb)
6009 {
6010         return skb->len < ETH_ZLEN && tp->mac_version == RTL_GIGA_MAC_VER_34;
6011 }
6012
6013 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
6014                                       struct net_device *dev);
6015 /* r8169_csum_workaround()
6016  * The hw limites the value the transport offset. When the offset is out of the
6017  * range, calculate the checksum by sw.
6018  */
6019 static void r8169_csum_workaround(struct rtl8169_private *tp,
6020                                   struct sk_buff *skb)
6021 {
6022         if (skb_shinfo(skb)->gso_size) {
6023                 netdev_features_t features = tp->dev->features;
6024                 struct sk_buff *segs, *nskb;
6025
6026                 features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
6027                 segs = skb_gso_segment(skb, features);
6028                 if (IS_ERR(segs) || !segs)
6029                         goto drop;
6030
6031                 do {
6032                         nskb = segs;
6033                         segs = segs->next;
6034                         nskb->next = NULL;
6035                         rtl8169_start_xmit(nskb, tp->dev);
6036                 } while (segs);
6037
6038                 dev_consume_skb_any(skb);
6039         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
6040                 if (skb_checksum_help(skb) < 0)
6041                         goto drop;
6042
6043                 rtl8169_start_xmit(skb, tp->dev);
6044         } else {
6045                 struct net_device_stats *stats;
6046
6047 drop:
6048                 stats = &tp->dev->stats;
6049                 stats->tx_dropped++;
6050                 dev_kfree_skb_any(skb);
6051         }
6052 }
6053
6054 /* msdn_giant_send_check()
6055  * According to the document of microsoft, the TCP Pseudo Header excludes the
6056  * packet length for IPv6 TCP large packets.
6057  */
6058 static int msdn_giant_send_check(struct sk_buff *skb)
6059 {
6060         const struct ipv6hdr *ipv6h;
6061         struct tcphdr *th;
6062         int ret;
6063
6064         ret = skb_cow_head(skb, 0);
6065         if (ret)
6066                 return ret;
6067
6068         ipv6h = ipv6_hdr(skb);
6069         th = tcp_hdr(skb);
6070
6071         th->check = 0;
6072         th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0);
6073
6074         return ret;
6075 }
6076
6077 static bool rtl8169_tso_csum_v1(struct rtl8169_private *tp,
6078                                 struct sk_buff *skb, u32 *opts)
6079 {
6080         u32 mss = skb_shinfo(skb)->gso_size;
6081
6082         if (mss) {
6083                 opts[0] |= TD_LSO;
6084                 opts[0] |= min(mss, TD_MSS_MAX) << TD0_MSS_SHIFT;
6085         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
6086                 const struct iphdr *ip = ip_hdr(skb);
6087
6088                 if (ip->protocol == IPPROTO_TCP)
6089                         opts[0] |= TD0_IP_CS | TD0_TCP_CS;
6090                 else if (ip->protocol == IPPROTO_UDP)
6091                         opts[0] |= TD0_IP_CS | TD0_UDP_CS;
6092                 else
6093                         WARN_ON_ONCE(1);
6094         }
6095
6096         return true;
6097 }
6098
6099 static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp,
6100                                 struct sk_buff *skb, u32 *opts)
6101 {
6102         u32 transport_offset = (u32)skb_transport_offset(skb);
6103         u32 mss = skb_shinfo(skb)->gso_size;
6104
6105         if (mss) {
6106                 if (transport_offset > GTTCPHO_MAX) {
6107                         netif_warn(tp, tx_err, tp->dev,
6108                                    "Invalid transport offset 0x%x for TSO\n",
6109                                    transport_offset);
6110                         return false;
6111                 }
6112
6113                 switch (vlan_get_protocol(skb)) {
6114                 case htons(ETH_P_IP):
6115                         opts[0] |= TD1_GTSENV4;
6116                         break;
6117
6118                 case htons(ETH_P_IPV6):
6119                         if (msdn_giant_send_check(skb))
6120                                 return false;
6121
6122                         opts[0] |= TD1_GTSENV6;
6123                         break;
6124
6125                 default:
6126                         WARN_ON_ONCE(1);
6127                         break;
6128                 }
6129
6130                 opts[0] |= transport_offset << GTTCPHO_SHIFT;
6131                 opts[1] |= min(mss, TD_MSS_MAX) << TD1_MSS_SHIFT;
6132         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
6133                 u8 ip_protocol;
6134
6135                 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
6136                         return !(skb_checksum_help(skb) || eth_skb_pad(skb));
6137
6138                 if (transport_offset > TCPHO_MAX) {
6139                         netif_warn(tp, tx_err, tp->dev,
6140                                    "Invalid transport offset 0x%x\n",
6141                                    transport_offset);
6142                         return false;
6143                 }
6144
6145                 switch (vlan_get_protocol(skb)) {
6146                 case htons(ETH_P_IP):
6147                         opts[1] |= TD1_IPv4_CS;
6148                         ip_protocol = ip_hdr(skb)->protocol;
6149                         break;
6150
6151                 case htons(ETH_P_IPV6):
6152                         opts[1] |= TD1_IPv6_CS;
6153                         ip_protocol = ipv6_hdr(skb)->nexthdr;
6154                         break;
6155
6156                 default:
6157                         ip_protocol = IPPROTO_RAW;
6158                         break;
6159                 }
6160
6161                 if (ip_protocol == IPPROTO_TCP)
6162                         opts[1] |= TD1_TCP_CS;
6163                 else if (ip_protocol == IPPROTO_UDP)
6164                         opts[1] |= TD1_UDP_CS;
6165                 else
6166                         WARN_ON_ONCE(1);
6167
6168                 opts[1] |= transport_offset << TCPHO_SHIFT;
6169         } else {
6170                 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
6171                         return !eth_skb_pad(skb);
6172         }
6173
6174         return true;
6175 }
6176
6177 static bool rtl_tx_slots_avail(struct rtl8169_private *tp,
6178                                unsigned int nr_frags)
6179 {
6180         unsigned int slots_avail = tp->dirty_tx + NUM_TX_DESC - tp->cur_tx;
6181
6182         /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
6183         return slots_avail > nr_frags;
6184 }
6185
6186 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
6187                                       struct net_device *dev)
6188 {
6189         struct rtl8169_private *tp = netdev_priv(dev);
6190         unsigned int entry = tp->cur_tx % NUM_TX_DESC;
6191         struct TxDesc *txd = tp->TxDescArray + entry;
6192         struct device *d = tp_to_dev(tp);
6193         dma_addr_t mapping;
6194         u32 opts[2], len;
6195         int frags;
6196
6197         if (unlikely(!rtl_tx_slots_avail(tp, skb_shinfo(skb)->nr_frags))) {
6198                 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
6199                 goto err_stop_0;
6200         }
6201
6202         if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
6203                 goto err_stop_0;
6204
6205         opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(skb));
6206         opts[0] = DescOwn;
6207
6208         if (!tp->tso_csum(tp, skb, opts)) {
6209                 r8169_csum_workaround(tp, skb);
6210                 return NETDEV_TX_OK;
6211         }
6212
6213         len = skb_headlen(skb);
6214         mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
6215         if (unlikely(dma_mapping_error(d, mapping))) {
6216                 if (net_ratelimit())
6217                         netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
6218                 goto err_dma_0;
6219         }
6220
6221         tp->tx_skb[entry].len = len;
6222         txd->addr = cpu_to_le64(mapping);
6223
6224         frags = rtl8169_xmit_frags(tp, skb, opts);
6225         if (frags < 0)
6226                 goto err_dma_1;
6227         else if (frags)
6228                 opts[0] |= FirstFrag;
6229         else {
6230                 opts[0] |= FirstFrag | LastFrag;
6231                 tp->tx_skb[entry].skb = skb;
6232         }
6233
6234         txd->opts2 = cpu_to_le32(opts[1]);
6235
6236         netdev_sent_queue(dev, skb->len);
6237
6238         skb_tx_timestamp(skb);
6239
6240         /* Force memory writes to complete before releasing descriptor */
6241         dma_wmb();
6242
6243         txd->opts1 = rtl8169_get_txd_opts1(opts[0], len, entry);
6244
6245         /* Force all memory writes to complete before notifying device */
6246         wmb();
6247
6248         tp->cur_tx += frags + 1;
6249
6250         RTL_W8(tp, TxPoll, NPQ);
6251
6252         if (!rtl_tx_slots_avail(tp, MAX_SKB_FRAGS)) {
6253                 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
6254                  * not miss a ring update when it notices a stopped queue.
6255                  */
6256                 smp_wmb();
6257                 netif_stop_queue(dev);
6258                 /* Sync with rtl_tx:
6259                  * - publish queue status and cur_tx ring index (write barrier)
6260                  * - refresh dirty_tx ring index (read barrier).
6261                  * May the current thread have a pessimistic view of the ring
6262                  * status and forget to wake up queue, a racing rtl_tx thread
6263                  * can't.
6264                  */
6265                 smp_mb();
6266                 if (rtl_tx_slots_avail(tp, MAX_SKB_FRAGS))
6267                         netif_wake_queue(dev);
6268         }
6269
6270         return NETDEV_TX_OK;
6271
6272 err_dma_1:
6273         rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
6274 err_dma_0:
6275         dev_kfree_skb_any(skb);
6276         dev->stats.tx_dropped++;
6277         return NETDEV_TX_OK;
6278
6279 err_stop_0:
6280         netif_stop_queue(dev);
6281         dev->stats.tx_dropped++;
6282         return NETDEV_TX_BUSY;
6283 }
6284
6285 static void rtl8169_pcierr_interrupt(struct net_device *dev)
6286 {
6287         struct rtl8169_private *tp = netdev_priv(dev);
6288         struct pci_dev *pdev = tp->pci_dev;
6289         u16 pci_status, pci_cmd;
6290
6291         pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
6292         pci_read_config_word(pdev, PCI_STATUS, &pci_status);
6293
6294         netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
6295                   pci_cmd, pci_status);
6296
6297         /*
6298          * The recovery sequence below admits a very elaborated explanation:
6299          * - it seems to work;
6300          * - I did not see what else could be done;
6301          * - it makes iop3xx happy.
6302          *
6303          * Feel free to adjust to your needs.
6304          */
6305         if (pdev->broken_parity_status)
6306                 pci_cmd &= ~PCI_COMMAND_PARITY;
6307         else
6308                 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
6309
6310         pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
6311
6312         pci_write_config_word(pdev, PCI_STATUS,
6313                 pci_status & (PCI_STATUS_DETECTED_PARITY |
6314                 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
6315                 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
6316
6317         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
6318 }
6319
6320 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp,
6321                    int budget)
6322 {
6323         unsigned int dirty_tx, tx_left, bytes_compl = 0, pkts_compl = 0;
6324
6325         dirty_tx = tp->dirty_tx;
6326         smp_rmb();
6327         tx_left = tp->cur_tx - dirty_tx;
6328
6329         while (tx_left > 0) {
6330                 unsigned int entry = dirty_tx % NUM_TX_DESC;
6331                 struct ring_info *tx_skb = tp->tx_skb + entry;
6332                 u32 status;
6333
6334                 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
6335                 if (status & DescOwn)
6336                         break;
6337
6338                 /* This barrier is needed to keep us from reading
6339                  * any other fields out of the Tx descriptor until
6340                  * we know the status of DescOwn
6341                  */
6342                 dma_rmb();
6343
6344                 rtl8169_unmap_tx_skb(tp_to_dev(tp), tx_skb,
6345                                      tp->TxDescArray + entry);
6346                 if (status & LastFrag) {
6347                         pkts_compl++;
6348                         bytes_compl += tx_skb->skb->len;
6349                         napi_consume_skb(tx_skb->skb, budget);
6350                         tx_skb->skb = NULL;
6351                 }
6352                 dirty_tx++;
6353                 tx_left--;
6354         }
6355
6356         if (tp->dirty_tx != dirty_tx) {
6357                 netdev_completed_queue(dev, pkts_compl, bytes_compl);
6358
6359                 u64_stats_update_begin(&tp->tx_stats.syncp);
6360                 tp->tx_stats.packets += pkts_compl;
6361                 tp->tx_stats.bytes += bytes_compl;
6362                 u64_stats_update_end(&tp->tx_stats.syncp);
6363
6364                 tp->dirty_tx = dirty_tx;
6365                 /* Sync with rtl8169_start_xmit:
6366                  * - publish dirty_tx ring index (write barrier)
6367                  * - refresh cur_tx ring index and queue status (read barrier)
6368                  * May the current thread miss the stopped queue condition,
6369                  * a racing xmit thread can only have a right view of the
6370                  * ring status.
6371                  */
6372                 smp_mb();
6373                 if (netif_queue_stopped(dev) &&
6374                     rtl_tx_slots_avail(tp, MAX_SKB_FRAGS)) {
6375                         netif_wake_queue(dev);
6376                 }
6377                 /*
6378                  * 8168 hack: TxPoll requests are lost when the Tx packets are
6379                  * too close. Let's kick an extra TxPoll request when a burst
6380                  * of start_xmit activity is detected (if it is not detected,
6381                  * it is slow enough). -- FR
6382                  */
6383                 if (tp->cur_tx != dirty_tx)
6384                         RTL_W8(tp, TxPoll, NPQ);
6385         }
6386 }
6387
6388 static inline int rtl8169_fragmented_frame(u32 status)
6389 {
6390         return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
6391 }
6392
6393 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
6394 {
6395         u32 status = opts1 & RxProtoMask;
6396
6397         if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
6398             ((status == RxProtoUDP) && !(opts1 & UDPFail)))
6399                 skb->ip_summed = CHECKSUM_UNNECESSARY;
6400         else
6401                 skb_checksum_none_assert(skb);
6402 }
6403
6404 static struct sk_buff *rtl8169_try_rx_copy(void *data,
6405                                            struct rtl8169_private *tp,
6406                                            int pkt_size,
6407                                            dma_addr_t addr)
6408 {
6409         struct sk_buff *skb;
6410         struct device *d = tp_to_dev(tp);
6411
6412         dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
6413         prefetch(data);
6414         skb = napi_alloc_skb(&tp->napi, pkt_size);
6415         if (skb)
6416                 skb_copy_to_linear_data(skb, data, pkt_size);
6417         dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
6418
6419         return skb;
6420 }
6421
6422 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget)
6423 {
6424         unsigned int cur_rx, rx_left;
6425         unsigned int count;
6426
6427         cur_rx = tp->cur_rx;
6428
6429         for (rx_left = min(budget, NUM_RX_DESC); rx_left > 0; rx_left--, cur_rx++) {
6430                 unsigned int entry = cur_rx % NUM_RX_DESC;
6431                 struct RxDesc *desc = tp->RxDescArray + entry;
6432                 u32 status;
6433
6434                 status = le32_to_cpu(desc->opts1);
6435                 if (status & DescOwn)
6436                         break;
6437
6438                 /* This barrier is needed to keep us from reading
6439                  * any other fields out of the Rx descriptor until
6440                  * we know the status of DescOwn
6441                  */
6442                 dma_rmb();
6443
6444                 if (unlikely(status & RxRES)) {
6445                         netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
6446                                    status);
6447                         dev->stats.rx_errors++;
6448                         if (status & (RxRWT | RxRUNT))
6449                                 dev->stats.rx_length_errors++;
6450                         if (status & RxCRC)
6451                                 dev->stats.rx_crc_errors++;
6452                         /* RxFOVF is a reserved bit on later chip versions */
6453                         if (tp->mac_version == RTL_GIGA_MAC_VER_01 &&
6454                             status & RxFOVF) {
6455                                 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
6456                                 dev->stats.rx_fifo_errors++;
6457                         } else if (status & (RxRUNT | RxCRC) &&
6458                                    !(status & RxRWT) &&
6459                                    dev->features & NETIF_F_RXALL) {
6460                                 goto process_pkt;
6461                         }
6462                 } else {
6463                         struct sk_buff *skb;
6464                         dma_addr_t addr;
6465                         int pkt_size;
6466
6467 process_pkt:
6468                         addr = le64_to_cpu(desc->addr);
6469                         if (likely(!(dev->features & NETIF_F_RXFCS)))
6470                                 pkt_size = (status & 0x00003fff) - 4;
6471                         else
6472                                 pkt_size = status & 0x00003fff;
6473
6474                         /*
6475                          * The driver does not support incoming fragmented
6476                          * frames. They are seen as a symptom of over-mtu
6477                          * sized frames.
6478                          */
6479                         if (unlikely(rtl8169_fragmented_frame(status))) {
6480                                 dev->stats.rx_dropped++;
6481                                 dev->stats.rx_length_errors++;
6482                                 goto release_descriptor;
6483                         }
6484
6485                         skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
6486                                                   tp, pkt_size, addr);
6487                         if (!skb) {
6488                                 dev->stats.rx_dropped++;
6489                                 goto release_descriptor;
6490                         }
6491
6492                         rtl8169_rx_csum(skb, status);
6493                         skb_put(skb, pkt_size);
6494                         skb->protocol = eth_type_trans(skb, dev);
6495
6496                         rtl8169_rx_vlan_tag(desc, skb);
6497
6498                         if (skb->pkt_type == PACKET_MULTICAST)
6499                                 dev->stats.multicast++;
6500
6501                         napi_gro_receive(&tp->napi, skb);
6502
6503                         u64_stats_update_begin(&tp->rx_stats.syncp);
6504                         tp->rx_stats.packets++;
6505                         tp->rx_stats.bytes += pkt_size;
6506                         u64_stats_update_end(&tp->rx_stats.syncp);
6507                 }
6508 release_descriptor:
6509                 desc->opts2 = 0;
6510                 rtl8169_mark_to_asic(desc);
6511         }
6512
6513         count = cur_rx - tp->cur_rx;
6514         tp->cur_rx = cur_rx;
6515
6516         return count;
6517 }
6518
6519 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
6520 {
6521         struct rtl8169_private *tp = dev_instance;
6522         u16 status = RTL_R16(tp, IntrStatus);
6523         u16 irq_mask = RTL_R16(tp, IntrMask);
6524
6525         if (status == 0xffff || !(status & irq_mask))
6526                 return IRQ_NONE;
6527
6528         if (unlikely(status & SYSErr)) {
6529                 rtl8169_pcierr_interrupt(tp->dev);
6530                 goto out;
6531         }
6532
6533         if (status & LinkChg)
6534                 phy_mac_interrupt(tp->phydev);
6535
6536         if (unlikely(status & RxFIFOOver &&
6537             tp->mac_version == RTL_GIGA_MAC_VER_11)) {
6538                 netif_stop_queue(tp->dev);
6539                 /* XXX - Hack alert. See rtl_task(). */
6540                 set_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags);
6541         }
6542
6543         if (status & RTL_EVENT_NAPI) {
6544                 rtl_irq_disable(tp);
6545                 napi_schedule_irqoff(&tp->napi);
6546         }
6547 out:
6548         rtl_ack_events(tp, status);
6549
6550         return IRQ_HANDLED;
6551 }
6552
6553 static void rtl_task(struct work_struct *work)
6554 {
6555         static const struct {
6556                 int bitnr;
6557                 void (*action)(struct rtl8169_private *);
6558         } rtl_work[] = {
6559                 { RTL_FLAG_TASK_RESET_PENDING,  rtl_reset_work },
6560         };
6561         struct rtl8169_private *tp =
6562                 container_of(work, struct rtl8169_private, wk.work);
6563         struct net_device *dev = tp->dev;
6564         int i;
6565
6566         rtl_lock_work(tp);
6567
6568         if (!netif_running(dev) ||
6569             !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
6570                 goto out_unlock;
6571
6572         for (i = 0; i < ARRAY_SIZE(rtl_work); i++) {
6573                 bool pending;
6574
6575                 pending = test_and_clear_bit(rtl_work[i].bitnr, tp->wk.flags);
6576                 if (pending)
6577                         rtl_work[i].action(tp);
6578         }
6579
6580 out_unlock:
6581         rtl_unlock_work(tp);
6582 }
6583
6584 static int rtl8169_poll(struct napi_struct *napi, int budget)
6585 {
6586         struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
6587         struct net_device *dev = tp->dev;
6588         int work_done;
6589
6590         work_done = rtl_rx(dev, tp, (u32) budget);
6591
6592         rtl_tx(dev, tp, budget);
6593
6594         if (work_done < budget) {
6595                 napi_complete_done(napi, work_done);
6596                 rtl_irq_enable(tp);
6597         }
6598
6599         return work_done;
6600 }
6601
6602 static void rtl8169_rx_missed(struct net_device *dev)
6603 {
6604         struct rtl8169_private *tp = netdev_priv(dev);
6605
6606         if (tp->mac_version > RTL_GIGA_MAC_VER_06)
6607                 return;
6608
6609         dev->stats.rx_missed_errors += RTL_R32(tp, RxMissed) & 0xffffff;
6610         RTL_W32(tp, RxMissed, 0);
6611 }
6612
6613 static void r8169_phylink_handler(struct net_device *ndev)
6614 {
6615         struct rtl8169_private *tp = netdev_priv(ndev);
6616
6617         if (netif_carrier_ok(ndev)) {
6618                 rtl_link_chg_patch(tp);
6619                 pm_request_resume(&tp->pci_dev->dev);
6620         } else {
6621                 pm_runtime_idle(&tp->pci_dev->dev);
6622         }
6623
6624         if (net_ratelimit())
6625                 phy_print_status(tp->phydev);
6626 }
6627
6628 static int r8169_phy_connect(struct rtl8169_private *tp)
6629 {
6630         struct phy_device *phydev = tp->phydev;
6631         phy_interface_t phy_mode;
6632         int ret;
6633
6634         phy_mode = tp->supports_gmii ? PHY_INTERFACE_MODE_GMII :
6635                    PHY_INTERFACE_MODE_MII;
6636
6637         ret = phy_connect_direct(tp->dev, phydev, r8169_phylink_handler,
6638                                  phy_mode);
6639         if (ret)
6640                 return ret;
6641
6642         if (!tp->supports_gmii)
6643                 phy_set_max_speed(phydev, SPEED_100);
6644
6645         /* Ensure to advertise everything, incl. pause */
6646         linkmode_copy(phydev->advertising, phydev->supported);
6647
6648         phy_attached_info(phydev);
6649
6650         return 0;
6651 }
6652
6653 static void rtl8169_down(struct net_device *dev)
6654 {
6655         struct rtl8169_private *tp = netdev_priv(dev);
6656
6657         phy_stop(tp->phydev);
6658
6659         napi_disable(&tp->napi);
6660         netif_stop_queue(dev);
6661
6662         rtl8169_hw_reset(tp);
6663         /*
6664          * At this point device interrupts can not be enabled in any function,
6665          * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task)
6666          * and napi is disabled (rtl8169_poll).
6667          */
6668         rtl8169_rx_missed(dev);
6669
6670         /* Give a racing hard_start_xmit a few cycles to complete. */
6671         synchronize_rcu();
6672
6673         rtl8169_tx_clear(tp);
6674
6675         rtl8169_rx_clear(tp);
6676
6677         rtl_pll_power_down(tp);
6678 }
6679
6680 static int rtl8169_close(struct net_device *dev)
6681 {
6682         struct rtl8169_private *tp = netdev_priv(dev);
6683         struct pci_dev *pdev = tp->pci_dev;
6684
6685         pm_runtime_get_sync(&pdev->dev);
6686
6687         /* Update counters before going down */
6688         rtl8169_update_counters(tp);
6689
6690         rtl_lock_work(tp);
6691         /* Clear all task flags */
6692         bitmap_zero(tp->wk.flags, RTL_FLAG_MAX);
6693
6694         rtl8169_down(dev);
6695         rtl_unlock_work(tp);
6696
6697         cancel_work_sync(&tp->wk.work);
6698
6699         phy_disconnect(tp->phydev);
6700
6701         pci_free_irq(pdev, 0, tp);
6702
6703         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6704                           tp->RxPhyAddr);
6705         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6706                           tp->TxPhyAddr);
6707         tp->TxDescArray = NULL;
6708         tp->RxDescArray = NULL;
6709
6710         pm_runtime_put_sync(&pdev->dev);
6711
6712         return 0;
6713 }
6714
6715 #ifdef CONFIG_NET_POLL_CONTROLLER
6716 static void rtl8169_netpoll(struct net_device *dev)
6717 {
6718         struct rtl8169_private *tp = netdev_priv(dev);
6719
6720         rtl8169_interrupt(pci_irq_vector(tp->pci_dev, 0), tp);
6721 }
6722 #endif
6723
6724 static int rtl_open(struct net_device *dev)
6725 {
6726         struct rtl8169_private *tp = netdev_priv(dev);
6727         struct pci_dev *pdev = tp->pci_dev;
6728         int retval = -ENOMEM;
6729
6730         pm_runtime_get_sync(&pdev->dev);
6731
6732         /*
6733          * Rx and Tx descriptors needs 256 bytes alignment.
6734          * dma_alloc_coherent provides more.
6735          */
6736         tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
6737                                              &tp->TxPhyAddr, GFP_KERNEL);
6738         if (!tp->TxDescArray)
6739                 goto err_pm_runtime_put;
6740
6741         tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
6742                                              &tp->RxPhyAddr, GFP_KERNEL);
6743         if (!tp->RxDescArray)
6744                 goto err_free_tx_0;
6745
6746         retval = rtl8169_init_ring(tp);
6747         if (retval < 0)
6748                 goto err_free_rx_1;
6749
6750         rtl_request_firmware(tp);
6751
6752         retval = pci_request_irq(pdev, 0, rtl8169_interrupt, NULL, tp,
6753                                  dev->name);
6754         if (retval < 0)
6755                 goto err_release_fw_2;
6756
6757         retval = r8169_phy_connect(tp);
6758         if (retval)
6759                 goto err_free_irq;
6760
6761         rtl_lock_work(tp);
6762
6763         set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6764
6765         napi_enable(&tp->napi);
6766
6767         rtl8169_init_phy(dev, tp);
6768
6769         rtl_pll_power_up(tp);
6770
6771         rtl_hw_start(tp);
6772
6773         if (!rtl8169_init_counter_offsets(tp))
6774                 netif_warn(tp, hw, dev, "counter reset/update failed\n");
6775
6776         phy_start(tp->phydev);
6777         netif_start_queue(dev);
6778
6779         rtl_unlock_work(tp);
6780
6781         pm_runtime_put_sync(&pdev->dev);
6782 out:
6783         return retval;
6784
6785 err_free_irq:
6786         pci_free_irq(pdev, 0, tp);
6787 err_release_fw_2:
6788         rtl_release_firmware(tp);
6789         rtl8169_rx_clear(tp);
6790 err_free_rx_1:
6791         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6792                           tp->RxPhyAddr);
6793         tp->RxDescArray = NULL;
6794 err_free_tx_0:
6795         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6796                           tp->TxPhyAddr);
6797         tp->TxDescArray = NULL;
6798 err_pm_runtime_put:
6799         pm_runtime_put_noidle(&pdev->dev);
6800         goto out;
6801 }
6802
6803 static void
6804 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
6805 {
6806         struct rtl8169_private *tp = netdev_priv(dev);
6807         struct pci_dev *pdev = tp->pci_dev;
6808         struct rtl8169_counters *counters = tp->counters;
6809         unsigned int start;
6810
6811         pm_runtime_get_noresume(&pdev->dev);
6812
6813         if (netif_running(dev) && pm_runtime_active(&pdev->dev))
6814                 rtl8169_rx_missed(dev);
6815
6816         do {
6817                 start = u64_stats_fetch_begin_irq(&tp->rx_stats.syncp);
6818                 stats->rx_packets = tp->rx_stats.packets;
6819                 stats->rx_bytes = tp->rx_stats.bytes;
6820         } while (u64_stats_fetch_retry_irq(&tp->rx_stats.syncp, start));
6821
6822         do {
6823                 start = u64_stats_fetch_begin_irq(&tp->tx_stats.syncp);
6824                 stats->tx_packets = tp->tx_stats.packets;
6825                 stats->tx_bytes = tp->tx_stats.bytes;
6826         } while (u64_stats_fetch_retry_irq(&tp->tx_stats.syncp, start));
6827
6828         stats->rx_dropped       = dev->stats.rx_dropped;
6829         stats->tx_dropped       = dev->stats.tx_dropped;
6830         stats->rx_length_errors = dev->stats.rx_length_errors;
6831         stats->rx_errors        = dev->stats.rx_errors;
6832         stats->rx_crc_errors    = dev->stats.rx_crc_errors;
6833         stats->rx_fifo_errors   = dev->stats.rx_fifo_errors;
6834         stats->rx_missed_errors = dev->stats.rx_missed_errors;
6835         stats->multicast        = dev->stats.multicast;
6836
6837         /*
6838          * Fetch additonal counter values missing in stats collected by driver
6839          * from tally counters.
6840          */
6841         if (pm_runtime_active(&pdev->dev))
6842                 rtl8169_update_counters(tp);
6843
6844         /*
6845          * Subtract values fetched during initalization.
6846          * See rtl8169_init_counter_offsets for a description why we do that.
6847          */
6848         stats->tx_errors = le64_to_cpu(counters->tx_errors) -
6849                 le64_to_cpu(tp->tc_offset.tx_errors);
6850         stats->collisions = le32_to_cpu(counters->tx_multi_collision) -
6851                 le32_to_cpu(tp->tc_offset.tx_multi_collision);
6852         stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) -
6853                 le16_to_cpu(tp->tc_offset.tx_aborted);
6854
6855         pm_runtime_put_noidle(&pdev->dev);
6856 }
6857
6858 static void rtl8169_net_suspend(struct net_device *dev)
6859 {
6860         struct rtl8169_private *tp = netdev_priv(dev);
6861
6862         if (!netif_running(dev))
6863                 return;
6864
6865         phy_stop(tp->phydev);
6866         netif_device_detach(dev);
6867
6868         rtl_lock_work(tp);
6869         napi_disable(&tp->napi);
6870         /* Clear all task flags */
6871         bitmap_zero(tp->wk.flags, RTL_FLAG_MAX);
6872
6873         rtl_unlock_work(tp);
6874
6875         rtl_pll_power_down(tp);
6876 }
6877
6878 #ifdef CONFIG_PM
6879
6880 static int rtl8169_suspend(struct device *device)
6881 {
6882         struct net_device *dev = dev_get_drvdata(device);
6883         struct rtl8169_private *tp = netdev_priv(dev);
6884
6885         rtl8169_net_suspend(dev);
6886         clk_disable_unprepare(tp->clk);
6887
6888         return 0;
6889 }
6890
6891 static void __rtl8169_resume(struct net_device *dev)
6892 {
6893         struct rtl8169_private *tp = netdev_priv(dev);
6894
6895         netif_device_attach(dev);
6896
6897         rtl_pll_power_up(tp);
6898         rtl8169_init_phy(dev, tp);
6899
6900         phy_start(tp->phydev);
6901
6902         rtl_lock_work(tp);
6903         napi_enable(&tp->napi);
6904         set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6905         rtl_reset_work(tp);
6906         rtl_unlock_work(tp);
6907 }
6908
6909 static int rtl8169_resume(struct device *device)
6910 {
6911         struct net_device *dev = dev_get_drvdata(device);
6912         struct rtl8169_private *tp = netdev_priv(dev);
6913
6914         clk_prepare_enable(tp->clk);
6915
6916         if (netif_running(dev))
6917                 __rtl8169_resume(dev);
6918
6919         return 0;
6920 }
6921
6922 static int rtl8169_runtime_suspend(struct device *device)
6923 {
6924         struct net_device *dev = dev_get_drvdata(device);
6925         struct rtl8169_private *tp = netdev_priv(dev);
6926
6927         if (!tp->TxDescArray)
6928                 return 0;
6929
6930         rtl_lock_work(tp);
6931         __rtl8169_set_wol(tp, WAKE_ANY);
6932         rtl_unlock_work(tp);
6933
6934         rtl8169_net_suspend(dev);
6935
6936         /* Update counters before going runtime suspend */
6937         rtl8169_rx_missed(dev);
6938         rtl8169_update_counters(tp);
6939
6940         return 0;
6941 }
6942
6943 static int rtl8169_runtime_resume(struct device *device)
6944 {
6945         struct net_device *dev = dev_get_drvdata(device);
6946         struct rtl8169_private *tp = netdev_priv(dev);
6947         rtl_rar_set(tp, dev->dev_addr);
6948
6949         if (!tp->TxDescArray)
6950                 return 0;
6951
6952         rtl_lock_work(tp);
6953         __rtl8169_set_wol(tp, tp->saved_wolopts);
6954         rtl_unlock_work(tp);
6955
6956         __rtl8169_resume(dev);
6957
6958         return 0;
6959 }
6960
6961 static int rtl8169_runtime_idle(struct device *device)
6962 {
6963         struct net_device *dev = dev_get_drvdata(device);
6964
6965         if (!netif_running(dev) || !netif_carrier_ok(dev))
6966                 pm_schedule_suspend(device, 10000);
6967
6968         return -EBUSY;
6969 }
6970
6971 static const struct dev_pm_ops rtl8169_pm_ops = {
6972         .suspend                = rtl8169_suspend,
6973         .resume                 = rtl8169_resume,
6974         .freeze                 = rtl8169_suspend,
6975         .thaw                   = rtl8169_resume,
6976         .poweroff               = rtl8169_suspend,
6977         .restore                = rtl8169_resume,
6978         .runtime_suspend        = rtl8169_runtime_suspend,
6979         .runtime_resume         = rtl8169_runtime_resume,
6980         .runtime_idle           = rtl8169_runtime_idle,
6981 };
6982
6983 #define RTL8169_PM_OPS  (&rtl8169_pm_ops)
6984
6985 #else /* !CONFIG_PM */
6986
6987 #define RTL8169_PM_OPS  NULL
6988
6989 #endif /* !CONFIG_PM */
6990
6991 static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
6992 {
6993         /* WoL fails with 8168b when the receiver is disabled. */
6994         switch (tp->mac_version) {
6995         case RTL_GIGA_MAC_VER_11:
6996         case RTL_GIGA_MAC_VER_12:
6997         case RTL_GIGA_MAC_VER_17:
6998                 pci_clear_master(tp->pci_dev);
6999
7000                 RTL_W8(tp, ChipCmd, CmdRxEnb);
7001                 /* PCI commit */
7002                 RTL_R8(tp, ChipCmd);
7003                 break;
7004         default:
7005                 break;
7006         }
7007 }
7008
7009 static void rtl_shutdown(struct pci_dev *pdev)
7010 {
7011         struct net_device *dev = pci_get_drvdata(pdev);
7012         struct rtl8169_private *tp = netdev_priv(dev);
7013
7014         rtl8169_net_suspend(dev);
7015
7016         /* Restore original MAC address */
7017         rtl_rar_set(tp, dev->perm_addr);
7018
7019         rtl8169_hw_reset(tp);
7020
7021         if (system_state == SYSTEM_POWER_OFF) {
7022                 if (tp->saved_wolopts) {
7023                         rtl_wol_suspend_quirk(tp);
7024                         rtl_wol_shutdown_quirk(tp);
7025                 }
7026
7027                 pci_wake_from_d3(pdev, true);
7028                 pci_set_power_state(pdev, PCI_D3hot);
7029         }
7030 }
7031
7032 static void rtl_remove_one(struct pci_dev *pdev)
7033 {
7034         struct net_device *dev = pci_get_drvdata(pdev);
7035         struct rtl8169_private *tp = netdev_priv(dev);
7036
7037         if (r8168_check_dash(tp))
7038                 rtl8168_driver_stop(tp);
7039
7040         netif_napi_del(&tp->napi);
7041
7042         unregister_netdev(dev);
7043         mdiobus_unregister(tp->phydev->mdio.bus);
7044
7045         rtl_release_firmware(tp);
7046
7047         if (pci_dev_run_wake(pdev))
7048                 pm_runtime_get_noresume(&pdev->dev);
7049
7050         /* restore original MAC address */
7051         rtl_rar_set(tp, dev->perm_addr);
7052 }
7053
7054 static const struct net_device_ops rtl_netdev_ops = {
7055         .ndo_open               = rtl_open,
7056         .ndo_stop               = rtl8169_close,
7057         .ndo_get_stats64        = rtl8169_get_stats64,
7058         .ndo_start_xmit         = rtl8169_start_xmit,
7059         .ndo_tx_timeout         = rtl8169_tx_timeout,
7060         .ndo_validate_addr      = eth_validate_addr,
7061         .ndo_change_mtu         = rtl8169_change_mtu,
7062         .ndo_fix_features       = rtl8169_fix_features,
7063         .ndo_set_features       = rtl8169_set_features,
7064         .ndo_set_mac_address    = rtl_set_mac_address,
7065         .ndo_do_ioctl           = rtl8169_ioctl,
7066         .ndo_set_rx_mode        = rtl_set_rx_mode,
7067 #ifdef CONFIG_NET_POLL_CONTROLLER
7068         .ndo_poll_controller    = rtl8169_netpoll,
7069 #endif
7070
7071 };
7072
7073 static const struct rtl_cfg_info {
7074         void (*hw_start)(struct rtl8169_private *tp);
7075         u16 irq_mask;
7076         unsigned int has_gmii:1;
7077         const struct rtl_coalesce_info *coalesce_info;
7078 } rtl_cfg_infos [] = {
7079         [RTL_CFG_0] = {
7080                 .hw_start       = rtl_hw_start_8169,
7081                 .irq_mask       = SYSErr | LinkChg | RxOverflow | RxFIFOOver,
7082                 .has_gmii       = 1,
7083                 .coalesce_info  = rtl_coalesce_info_8169,
7084         },
7085         [RTL_CFG_1] = {
7086                 .hw_start       = rtl_hw_start_8168,
7087                 .irq_mask       = LinkChg | RxOverflow,
7088                 .has_gmii       = 1,
7089                 .coalesce_info  = rtl_coalesce_info_8168_8136,
7090         },
7091         [RTL_CFG_2] = {
7092                 .hw_start       = rtl_hw_start_8101,
7093                 .irq_mask       = LinkChg | RxOverflow | RxFIFOOver,
7094                 .coalesce_info  = rtl_coalesce_info_8168_8136,
7095         }
7096 };
7097
7098 static int rtl_alloc_irq(struct rtl8169_private *tp)
7099 {
7100         unsigned int flags;
7101
7102         if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
7103                 rtl_unlock_config_regs(tp);
7104                 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~MSIEnable);
7105                 rtl_lock_config_regs(tp);
7106                 flags = PCI_IRQ_LEGACY;
7107         } else {
7108                 flags = PCI_IRQ_ALL_TYPES;
7109         }
7110
7111         return pci_alloc_irq_vectors(tp->pci_dev, 1, 1, flags);
7112 }
7113
7114 static void rtl_read_mac_address(struct rtl8169_private *tp,
7115                                  u8 mac_addr[ETH_ALEN])
7116 {
7117         u32 value;
7118
7119         /* Get MAC address */
7120         switch (tp->mac_version) {
7121         case RTL_GIGA_MAC_VER_35 ... RTL_GIGA_MAC_VER_38:
7122         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
7123                 value = rtl_eri_read(tp, 0xe0, ERIAR_EXGMAC);
7124                 mac_addr[0] = (value >>  0) & 0xff;
7125                 mac_addr[1] = (value >>  8) & 0xff;
7126                 mac_addr[2] = (value >> 16) & 0xff;
7127                 mac_addr[3] = (value >> 24) & 0xff;
7128
7129                 value = rtl_eri_read(tp, 0xe4, ERIAR_EXGMAC);
7130                 mac_addr[4] = (value >>  0) & 0xff;
7131                 mac_addr[5] = (value >>  8) & 0xff;
7132                 break;
7133         default:
7134                 break;
7135         }
7136 }
7137
7138 DECLARE_RTL_COND(rtl_link_list_ready_cond)
7139 {
7140         return RTL_R8(tp, MCU) & LINK_LIST_RDY;
7141 }
7142
7143 DECLARE_RTL_COND(rtl_rxtx_empty_cond)
7144 {
7145         return (RTL_R8(tp, MCU) & RXTX_EMPTY) == RXTX_EMPTY;
7146 }
7147
7148 static int r8169_mdio_read_reg(struct mii_bus *mii_bus, int phyaddr, int phyreg)
7149 {
7150         struct rtl8169_private *tp = mii_bus->priv;
7151
7152         if (phyaddr > 0)
7153                 return -ENODEV;
7154
7155         return rtl_readphy(tp, phyreg);
7156 }
7157
7158 static int r8169_mdio_write_reg(struct mii_bus *mii_bus, int phyaddr,
7159                                 int phyreg, u16 val)
7160 {
7161         struct rtl8169_private *tp = mii_bus->priv;
7162
7163         if (phyaddr > 0)
7164                 return -ENODEV;
7165
7166         rtl_writephy(tp, phyreg, val);
7167
7168         return 0;
7169 }
7170
7171 static int r8169_mdio_register(struct rtl8169_private *tp)
7172 {
7173         struct pci_dev *pdev = tp->pci_dev;
7174         struct mii_bus *new_bus;
7175         int ret;
7176
7177         new_bus = devm_mdiobus_alloc(&pdev->dev);
7178         if (!new_bus)
7179                 return -ENOMEM;
7180
7181         new_bus->name = "r8169";
7182         new_bus->priv = tp;
7183         new_bus->parent = &pdev->dev;
7184         new_bus->irq[0] = PHY_IGNORE_INTERRUPT;
7185         snprintf(new_bus->id, MII_BUS_ID_SIZE, "r8169-%x",
7186                  PCI_DEVID(pdev->bus->number, pdev->devfn));
7187
7188         new_bus->read = r8169_mdio_read_reg;
7189         new_bus->write = r8169_mdio_write_reg;
7190
7191         ret = mdiobus_register(new_bus);
7192         if (ret)
7193                 return ret;
7194
7195         tp->phydev = mdiobus_get_phy(new_bus, 0);
7196         if (!tp->phydev) {
7197                 mdiobus_unregister(new_bus);
7198                 return -ENODEV;
7199         }
7200
7201         /* PHY will be woken up in rtl_open() */
7202         phy_suspend(tp->phydev);
7203
7204         return 0;
7205 }
7206
7207 static void rtl_hw_init_8168g(struct rtl8169_private *tp)
7208 {
7209         u32 data;
7210
7211         tp->ocp_base = OCP_STD_PHY_BASE;
7212
7213         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN);
7214
7215         if (!rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42))
7216                 return;
7217
7218         if (!rtl_udelay_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42))
7219                 return;
7220
7221         RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
7222         msleep(1);
7223         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
7224
7225         data = r8168_mac_ocp_read(tp, 0xe8de);
7226         data &= ~(1 << 14);
7227         r8168_mac_ocp_write(tp, 0xe8de, data);
7228
7229         if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
7230                 return;
7231
7232         data = r8168_mac_ocp_read(tp, 0xe8de);
7233         data |= (1 << 15);
7234         r8168_mac_ocp_write(tp, 0xe8de, data);
7235
7236         if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
7237                 return;
7238 }
7239
7240 static void rtl_hw_init_8168ep(struct rtl8169_private *tp)
7241 {
7242         rtl8168ep_stop_cmac(tp);
7243         rtl_hw_init_8168g(tp);
7244 }
7245
7246 static void rtl_hw_initialize(struct rtl8169_private *tp)
7247 {
7248         switch (tp->mac_version) {
7249         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_48:
7250                 rtl_hw_init_8168g(tp);
7251                 break;
7252         case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_51:
7253                 rtl_hw_init_8168ep(tp);
7254                 break;
7255         default:
7256                 break;
7257         }
7258 }
7259
7260 /* Versions RTL8102e and from RTL8168c onwards support csum_v2 */
7261 static bool rtl_chip_supports_csum_v2(struct rtl8169_private *tp)
7262 {
7263         switch (tp->mac_version) {
7264         case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_06:
7265         case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
7266                 return false;
7267         default:
7268                 return true;
7269         }
7270 }
7271
7272 static int rtl_jumbo_max(struct rtl8169_private *tp)
7273 {
7274         /* Non-GBit versions don't support jumbo frames */
7275         if (!tp->supports_gmii)
7276                 return JUMBO_1K;
7277
7278         switch (tp->mac_version) {
7279         /* RTL8169 */
7280         case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_06:
7281                 return JUMBO_7K;
7282         /* RTL8168b */
7283         case RTL_GIGA_MAC_VER_11:
7284         case RTL_GIGA_MAC_VER_12:
7285         case RTL_GIGA_MAC_VER_17:
7286                 return JUMBO_4K;
7287         /* RTL8168c */
7288         case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
7289                 return JUMBO_6K;
7290         default:
7291                 return JUMBO_9K;
7292         }
7293 }
7294
7295 static void rtl_disable_clk(void *data)
7296 {
7297         clk_disable_unprepare(data);
7298 }
7299
7300 static int rtl_get_ether_clk(struct rtl8169_private *tp)
7301 {
7302         struct device *d = tp_to_dev(tp);
7303         struct clk *clk;
7304         int rc;
7305
7306         clk = devm_clk_get(d, "ether_clk");
7307         if (IS_ERR(clk)) {
7308                 rc = PTR_ERR(clk);
7309                 if (rc == -ENOENT)
7310                         /* clk-core allows NULL (for suspend / resume) */
7311                         rc = 0;
7312                 else if (rc != -EPROBE_DEFER)
7313                         dev_err(d, "failed to get clk: %d\n", rc);
7314         } else {
7315                 tp->clk = clk;
7316                 rc = clk_prepare_enable(clk);
7317                 if (rc)
7318                         dev_err(d, "failed to enable clk: %d\n", rc);
7319                 else
7320                         rc = devm_add_action_or_reset(d, rtl_disable_clk, clk);
7321         }
7322
7323         return rc;
7324 }
7325
7326 static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
7327 {
7328         const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
7329         /* align to u16 for is_valid_ether_addr() */
7330         u8 mac_addr[ETH_ALEN] __aligned(2) = {};
7331         struct rtl8169_private *tp;
7332         struct net_device *dev;
7333         int chipset, region, i;
7334         int jumbo_max, rc;
7335
7336         dev = devm_alloc_etherdev(&pdev->dev, sizeof (*tp));
7337         if (!dev)
7338                 return -ENOMEM;
7339
7340         SET_NETDEV_DEV(dev, &pdev->dev);
7341         dev->netdev_ops = &rtl_netdev_ops;
7342         tp = netdev_priv(dev);
7343         tp->dev = dev;
7344         tp->pci_dev = pdev;
7345         tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
7346         tp->supports_gmii = cfg->has_gmii;
7347
7348         /* Get the *optional* external "ether_clk" used on some boards */
7349         rc = rtl_get_ether_clk(tp);
7350         if (rc)
7351                 return rc;
7352
7353         /* enable device (incl. PCI PM wakeup and hotplug setup) */
7354         rc = pcim_enable_device(pdev);
7355         if (rc < 0) {
7356                 dev_err(&pdev->dev, "enable failure\n");
7357                 return rc;
7358         }
7359
7360         if (pcim_set_mwi(pdev) < 0)
7361                 dev_info(&pdev->dev, "Mem-Wr-Inval unavailable\n");
7362
7363         /* use first MMIO region */
7364         region = ffs(pci_select_bars(pdev, IORESOURCE_MEM)) - 1;
7365         if (region < 0) {
7366                 dev_err(&pdev->dev, "no MMIO resource found\n");
7367                 return -ENODEV;
7368         }
7369
7370         /* check for weird/broken PCI region reporting */
7371         if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
7372                 dev_err(&pdev->dev, "Invalid PCI region size(s), aborting\n");
7373                 return -ENODEV;
7374         }
7375
7376         rc = pcim_iomap_regions(pdev, BIT(region), MODULENAME);
7377         if (rc < 0) {
7378                 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
7379                 return rc;
7380         }
7381
7382         tp->mmio_addr = pcim_iomap_table(pdev)[region];
7383
7384         /* Identify chip attached to board */
7385         rtl8169_get_mac_version(tp);
7386         if (tp->mac_version == RTL_GIGA_MAC_NONE)
7387                 return -ENODEV;
7388
7389         if (rtl_tbi_enabled(tp)) {
7390                 dev_err(&pdev->dev, "TBI fiber mode not supported\n");
7391                 return -ENODEV;
7392         }
7393
7394         tp->cp_cmd = RTL_R16(tp, CPlusCmd);
7395
7396         if (sizeof(dma_addr_t) > 4 && tp->mac_version >= RTL_GIGA_MAC_VER_18 &&
7397             !dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) {
7398                 dev->features |= NETIF_F_HIGHDMA;
7399         } else {
7400                 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
7401                 if (rc < 0) {
7402                         dev_err(&pdev->dev, "DMA configuration failed\n");
7403                         return rc;
7404                 }
7405         }
7406
7407         rtl_init_rxcfg(tp);
7408
7409         rtl8169_irq_mask_and_ack(tp);
7410
7411         rtl_hw_initialize(tp);
7412
7413         rtl_hw_reset(tp);
7414
7415         pci_set_master(pdev);
7416
7417         rtl_init_mdio_ops(tp);
7418         rtl_init_jumbo_ops(tp);
7419
7420         chipset = tp->mac_version;
7421
7422         rc = rtl_alloc_irq(tp);
7423         if (rc < 0) {
7424                 dev_err(&pdev->dev, "Can't allocate interrupt\n");
7425                 return rc;
7426         }
7427
7428         mutex_init(&tp->wk.mutex);
7429         INIT_WORK(&tp->wk.work, rtl_task);
7430         u64_stats_init(&tp->rx_stats.syncp);
7431         u64_stats_init(&tp->tx_stats.syncp);
7432
7433         /* get MAC address */
7434         rc = eth_platform_get_mac_address(&pdev->dev, mac_addr);
7435         if (rc)
7436                 rtl_read_mac_address(tp, mac_addr);
7437
7438         if (is_valid_ether_addr(mac_addr))
7439                 rtl_rar_set(tp, mac_addr);
7440
7441         for (i = 0; i < ETH_ALEN; i++)
7442                 dev->dev_addr[i] = RTL_R8(tp, MAC0 + i);
7443
7444         dev->ethtool_ops = &rtl8169_ethtool_ops;
7445
7446         netif_napi_add(dev, &tp->napi, rtl8169_poll, NAPI_POLL_WEIGHT);
7447
7448         /* don't enable SG, IP_CSUM and TSO by default - it might not work
7449          * properly for all devices */
7450         dev->features |= NETIF_F_RXCSUM |
7451                 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
7452
7453         dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
7454                 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_TX |
7455                 NETIF_F_HW_VLAN_CTAG_RX;
7456         dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
7457                 NETIF_F_HIGHDMA;
7458         dev->priv_flags |= IFF_LIVE_ADDR_CHANGE;
7459
7460         tp->cp_cmd |= RxChkSum | RxVlan;
7461
7462         /*
7463          * Pretend we are using VLANs; This bypasses a nasty bug where
7464          * Interrupts stop flowing on high load on 8110SCd controllers.
7465          */
7466         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
7467                 /* Disallow toggling */
7468                 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX;
7469
7470         if (rtl_chip_supports_csum_v2(tp)) {
7471                 tp->tso_csum = rtl8169_tso_csum_v2;
7472                 dev->hw_features |= NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
7473         } else {
7474                 tp->tso_csum = rtl8169_tso_csum_v1;
7475         }
7476
7477         dev->hw_features |= NETIF_F_RXALL;
7478         dev->hw_features |= NETIF_F_RXFCS;
7479
7480         /* MTU range: 60 - hw-specific max */
7481         dev->min_mtu = ETH_ZLEN;
7482         jumbo_max = rtl_jumbo_max(tp);
7483         dev->max_mtu = jumbo_max;
7484
7485         tp->hw_start = cfg->hw_start;
7486         tp->irq_mask = RTL_EVENT_NAPI | cfg->irq_mask;
7487         tp->coalesce_info = cfg->coalesce_info;
7488
7489         tp->fw_name = rtl_chip_infos[chipset].fw_name;
7490
7491         tp->counters = dmam_alloc_coherent (&pdev->dev, sizeof(*tp->counters),
7492                                             &tp->counters_phys_addr,
7493                                             GFP_KERNEL);
7494         if (!tp->counters)
7495                 return -ENOMEM;
7496
7497         pci_set_drvdata(pdev, dev);
7498
7499         rc = r8169_mdio_register(tp);
7500         if (rc)
7501                 return rc;
7502
7503         /* chip gets powered up in rtl_open() */
7504         rtl_pll_power_down(tp);
7505
7506         rc = register_netdev(dev);
7507         if (rc)
7508                 goto err_mdio_unregister;
7509
7510         netif_info(tp, probe, dev, "%s, %pM, XID %03x, IRQ %d\n",
7511                    rtl_chip_infos[chipset].name, dev->dev_addr,
7512                    (RTL_R32(tp, TxConfig) >> 20) & 0xfcf,
7513                    pci_irq_vector(pdev, 0));
7514
7515         if (jumbo_max > JUMBO_1K)
7516                 netif_info(tp, probe, dev,
7517                            "jumbo features [frames: %d bytes, tx checksumming: %s]\n",
7518                            jumbo_max, tp->mac_version <= RTL_GIGA_MAC_VER_06 ?
7519                            "ok" : "ko");
7520
7521         if (r8168_check_dash(tp))
7522                 rtl8168_driver_start(tp);
7523
7524         if (pci_dev_run_wake(pdev))
7525                 pm_runtime_put_sync(&pdev->dev);
7526
7527         return 0;
7528
7529 err_mdio_unregister:
7530         mdiobus_unregister(tp->phydev->mdio.bus);
7531         return rc;
7532 }
7533
7534 static struct pci_driver rtl8169_pci_driver = {
7535         .name           = MODULENAME,
7536         .id_table       = rtl8169_pci_tbl,
7537         .probe          = rtl_init_one,
7538         .remove         = rtl_remove_one,
7539         .shutdown       = rtl_shutdown,
7540         .driver.pm      = RTL8169_PM_OPS,
7541 };
7542
7543 module_pci_driver(rtl8169_pci_driver);