drivers/net/ethernet/realtek/r8169_main.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * r8169.c: RealTek 8169/8168/8101 ethernet driver.
   4  *
   5  * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
   6  * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
   7  * Copyright (c) a lot of people too. Please respect their work.
   8  *
   9  * See MAINTAINERS file for support contact information.
  10  */
  11
  12 #include <linux/module.h>
  13 #include <linux/moduleparam.h>
  14 #include <linux/pci.h>
  15 #include <linux/netdevice.h>
  16 #include <linux/etherdevice.h>
  17 #include <linux/clk.h>
  18 #include <linux/delay.h>
  19 #include <linux/ethtool.h>
  20 #include <linux/phy.h>
  21 #include <linux/if_vlan.h>
  22 #include <linux/crc32.h>
  23 #include <linux/in.h>
  24 #include <linux/io.h>
  25 #include <linux/ip.h>
  26 #include <linux/tcp.h>
  27 #include <linux/interrupt.h>
  28 #include <linux/dma-mapping.h>
  29 #include <linux/pm_runtime.h>
  30 #include <linux/prefetch.h>
  31 #include <linux/pci-aspm.h>
  32 #include <linux/ipv6.h>
  33 #include <net/ip6_checksum.h>
  34
  35 #include "r8169_firmware.h"
  36
  37 #define MODULENAME "r8169"
  38
  39 #define FIRMWARE_8168D_1        "rtl_nic/rtl8168d-1.fw"
  40 #define FIRMWARE_8168D_2        "rtl_nic/rtl8168d-2.fw"
  41 #define FIRMWARE_8168E_1        "rtl_nic/rtl8168e-1.fw"
  42 #define FIRMWARE_8168E_2        "rtl_nic/rtl8168e-2.fw"
  43 #define FIRMWARE_8168E_3        "rtl_nic/rtl8168e-3.fw"
  44 #define FIRMWARE_8168F_1        "rtl_nic/rtl8168f-1.fw"
  45 #define FIRMWARE_8168F_2        "rtl_nic/rtl8168f-2.fw"
  46 #define FIRMWARE_8105E_1        "rtl_nic/rtl8105e-1.fw"
  47 #define FIRMWARE_8402_1         "rtl_nic/rtl8402-1.fw"
  48 #define FIRMWARE_8411_1         "rtl_nic/rtl8411-1.fw"
  49 #define FIRMWARE_8411_2         "rtl_nic/rtl8411-2.fw"
  50 #define FIRMWARE_8106E_1        "rtl_nic/rtl8106e-1.fw"
  51 #define FIRMWARE_8106E_2        "rtl_nic/rtl8106e-2.fw"
  52 #define FIRMWARE_8168G_2        "rtl_nic/rtl8168g-2.fw"
  53 #define FIRMWARE_8168G_3        "rtl_nic/rtl8168g-3.fw"
  54 #define FIRMWARE_8168H_1        "rtl_nic/rtl8168h-1.fw"
  55 #define FIRMWARE_8168H_2        "rtl_nic/rtl8168h-2.fw"
  56 #define FIRMWARE_8107E_1        "rtl_nic/rtl8107e-1.fw"
  57 #define FIRMWARE_8107E_2        "rtl_nic/rtl8107e-2.fw"
  58
  59 #define R8169_MSG_DEFAULT \
  60         (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
  61
  62 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
  63    The RTL chips use a 64 element hash table based on the Ethernet CRC. */
  64 #define MC_FILTER_LIMIT 32
  65
  66 #define TX_DMA_BURST    7       /* Maximum PCI burst, '7' is unlimited */
  67 #define InterFrameGap   0x03    /* 3 means InterFrameGap = the shortest one */
  68
  69 #define R8169_REGS_SIZE         256
  70 #define R8169_RX_BUF_SIZE       (SZ_16K - 1)
  71 #define NUM_TX_DESC     64      /* Number of Tx descriptor registers */
  72 #define NUM_RX_DESC     256U    /* Number of Rx descriptor registers */
  73 #define R8169_TX_RING_BYTES     (NUM_TX_DESC * sizeof(struct TxDesc))
  74 #define R8169_RX_RING_BYTES     (NUM_RX_DESC * sizeof(struct RxDesc))
  75
  76 #define RTL_CFG_NO_GBIT 1
  77
  78 /* write/read MMIO register */
  79 #define RTL_W8(tp, reg, val8)   writeb((val8), tp->mmio_addr + (reg))
  80 #define RTL_W16(tp, reg, val16) writew((val16), tp->mmio_addr + (reg))
  81 #define RTL_W32(tp, reg, val32) writel((val32), tp->mmio_addr + (reg))
  82 #define RTL_R8(tp, reg)         readb(tp->mmio_addr + (reg))
  83 #define RTL_R16(tp, reg)                readw(tp->mmio_addr + (reg))
  84 #define RTL_R32(tp, reg)                readl(tp->mmio_addr + (reg))
  85
  86 enum mac_version {
  87         /* support for ancient RTL_GIGA_MAC_VER_01 has been removed */
  88         RTL_GIGA_MAC_VER_02,
  89         RTL_GIGA_MAC_VER_03,
  90         RTL_GIGA_MAC_VER_04,
  91         RTL_GIGA_MAC_VER_05,
  92         RTL_GIGA_MAC_VER_06,
  93         RTL_GIGA_MAC_VER_07,
  94         RTL_GIGA_MAC_VER_08,
  95         RTL_GIGA_MAC_VER_09,
  96         RTL_GIGA_MAC_VER_10,
  97         RTL_GIGA_MAC_VER_11,
  98         RTL_GIGA_MAC_VER_12,
  99         RTL_GIGA_MAC_VER_13,
 100         RTL_GIGA_MAC_VER_14,
 101         RTL_GIGA_MAC_VER_15,
 102         RTL_GIGA_MAC_VER_16,
 103         RTL_GIGA_MAC_VER_17,
 104         RTL_GIGA_MAC_VER_18,
 105         RTL_GIGA_MAC_VER_19,
 106         RTL_GIGA_MAC_VER_20,
 107         RTL_GIGA_MAC_VER_21,
 108         RTL_GIGA_MAC_VER_22,
 109         RTL_GIGA_MAC_VER_23,
 110         RTL_GIGA_MAC_VER_24,
 111         RTL_GIGA_MAC_VER_25,
 112         RTL_GIGA_MAC_VER_26,
 113         RTL_GIGA_MAC_VER_27,
 114         RTL_GIGA_MAC_VER_28,
 115         RTL_GIGA_MAC_VER_29,
 116         RTL_GIGA_MAC_VER_30,
 117         RTL_GIGA_MAC_VER_31,
 118         RTL_GIGA_MAC_VER_32,
 119         RTL_GIGA_MAC_VER_33,
 120         RTL_GIGA_MAC_VER_34,
 121         RTL_GIGA_MAC_VER_35,
 122         RTL_GIGA_MAC_VER_36,
 123         RTL_GIGA_MAC_VER_37,
 124         RTL_GIGA_MAC_VER_38,
 125         RTL_GIGA_MAC_VER_39,
 126         RTL_GIGA_MAC_VER_40,
 127         RTL_GIGA_MAC_VER_41,
 128         RTL_GIGA_MAC_VER_42,
 129         RTL_GIGA_MAC_VER_43,
 130         RTL_GIGA_MAC_VER_44,
 131         RTL_GIGA_MAC_VER_45,
 132         RTL_GIGA_MAC_VER_46,
 133         RTL_GIGA_MAC_VER_47,
 134         RTL_GIGA_MAC_VER_48,
 135         RTL_GIGA_MAC_VER_49,
 136         RTL_GIGA_MAC_VER_50,
 137         RTL_GIGA_MAC_VER_51,
 138         RTL_GIGA_MAC_NONE
 139 };
 140
 141 #define JUMBO_1K        ETH_DATA_LEN
 142 #define JUMBO_4K        (4*1024 - ETH_HLEN - 2)
 143 #define JUMBO_6K        (6*1024 - ETH_HLEN - 2)
 144 #define JUMBO_7K        (7*1024 - ETH_HLEN - 2)
 145 #define JUMBO_9K        (9*1024 - ETH_HLEN - 2)
 146
 147 static const struct {
 148         const char *name;
 149         const char *fw_name;
 150 } rtl_chip_infos[] = {
 151         /* PCI devices. */
 152         [RTL_GIGA_MAC_VER_02] = {"RTL8169s"                             },
 153         [RTL_GIGA_MAC_VER_03] = {"RTL8110s"                             },
 154         [RTL_GIGA_MAC_VER_04] = {"RTL8169sb/8110sb"                     },
 155         [RTL_GIGA_MAC_VER_05] = {"RTL8169sc/8110sc"                     },
 156         [RTL_GIGA_MAC_VER_06] = {"RTL8169sc/8110sc"                     },
 157         /* PCI-E devices. */
 158         [RTL_GIGA_MAC_VER_07] = {"RTL8102e"                             },
 159         [RTL_GIGA_MAC_VER_08] = {"RTL8102e"                             },
 160         [RTL_GIGA_MAC_VER_09] = {"RTL8102e/RTL8103e"                    },
 161         [RTL_GIGA_MAC_VER_10] = {"RTL8101e"                             },
 162         [RTL_GIGA_MAC_VER_11] = {"RTL8168b/8111b"                       },
 163         [RTL_GIGA_MAC_VER_12] = {"RTL8168b/8111b"                       },
 164         [RTL_GIGA_MAC_VER_13] = {"RTL8101e"                             },
 165         [RTL_GIGA_MAC_VER_14] = {"RTL8100e"                             },
 166         [RTL_GIGA_MAC_VER_15] = {"RTL8100e"                             },
 167         [RTL_GIGA_MAC_VER_16] = {"RTL8101e"                             },
 168         [RTL_GIGA_MAC_VER_17] = {"RTL8168b/8111b"                       },
 169         [RTL_GIGA_MAC_VER_18] = {"RTL8168cp/8111cp"                     },
 170         [RTL_GIGA_MAC_VER_19] = {"RTL8168c/8111c"                       },
 171         [RTL_GIGA_MAC_VER_20] = {"RTL8168c/8111c"                       },
 172         [RTL_GIGA_MAC_VER_21] = {"RTL8168c/8111c"                       },
 173         [RTL_GIGA_MAC_VER_22] = {"RTL8168c/8111c"                       },
 174         [RTL_GIGA_MAC_VER_23] = {"RTL8168cp/8111cp"                     },
 175         [RTL_GIGA_MAC_VER_24] = {"RTL8168cp/8111cp"                     },
 176         [RTL_GIGA_MAC_VER_25] = {"RTL8168d/8111d",      FIRMWARE_8168D_1},
 177         [RTL_GIGA_MAC_VER_26] = {"RTL8168d/8111d",      FIRMWARE_8168D_2},
 178         [RTL_GIGA_MAC_VER_27] = {"RTL8168dp/8111dp"                     },
 179         [RTL_GIGA_MAC_VER_28] = {"RTL8168dp/8111dp"                     },
 180         [RTL_GIGA_MAC_VER_29] = {"RTL8105e",            FIRMWARE_8105E_1},
 181         [RTL_GIGA_MAC_VER_30] = {"RTL8105e",            FIRMWARE_8105E_1},
 182         [RTL_GIGA_MAC_VER_31] = {"RTL8168dp/8111dp"                     },
 183         [RTL_GIGA_MAC_VER_32] = {"RTL8168e/8111e",      FIRMWARE_8168E_1},
 184         [RTL_GIGA_MAC_VER_33] = {"RTL8168e/8111e",      FIRMWARE_8168E_2},
 185         [RTL_GIGA_MAC_VER_34] = {"RTL8168evl/8111evl",  FIRMWARE_8168E_3},
 186         [RTL_GIGA_MAC_VER_35] = {"RTL8168f/8111f",      FIRMWARE_8168F_1},
 187         [RTL_GIGA_MAC_VER_36] = {"RTL8168f/8111f",      FIRMWARE_8168F_2},
 188         [RTL_GIGA_MAC_VER_37] = {"RTL8402",             FIRMWARE_8402_1 },
 189         [RTL_GIGA_MAC_VER_38] = {"RTL8411",             FIRMWARE_8411_1 },
 190         [RTL_GIGA_MAC_VER_39] = {"RTL8106e",            FIRMWARE_8106E_1},
 191         [RTL_GIGA_MAC_VER_40] = {"RTL8168g/8111g",      FIRMWARE_8168G_2},
 192         [RTL_GIGA_MAC_VER_41] = {"RTL8168g/8111g"                       },
 193         [RTL_GIGA_MAC_VER_42] = {"RTL8168gu/8111gu",    FIRMWARE_8168G_3},
 194         [RTL_GIGA_MAC_VER_43] = {"RTL8106eus",          FIRMWARE_8106E_2},
 195         [RTL_GIGA_MAC_VER_44] = {"RTL8411b",            FIRMWARE_8411_2 },
 196         [RTL_GIGA_MAC_VER_45] = {"RTL8168h/8111h",      FIRMWARE_8168H_1},
 197         [RTL_GIGA_MAC_VER_46] = {"RTL8168h/8111h",      FIRMWARE_8168H_2},
 198         [RTL_GIGA_MAC_VER_47] = {"RTL8107e",            FIRMWARE_8107E_1},
 199         [RTL_GIGA_MAC_VER_48] = {"RTL8107e",            FIRMWARE_8107E_2},
 200         [RTL_GIGA_MAC_VER_49] = {"RTL8168ep/8111ep"                     },
 201         [RTL_GIGA_MAC_VER_50] = {"RTL8168ep/8111ep"                     },
 202         [RTL_GIGA_MAC_VER_51] = {"RTL8168ep/8111ep"                     },
 203 };
 204
 205 static const struct pci_device_id rtl8169_pci_tbl[] = {
 206         { PCI_VDEVICE(REALTEK,  0x2502) },
 207         { PCI_VDEVICE(REALTEK,  0x2600) },
 208         { PCI_VDEVICE(REALTEK,  0x8129) },
 209         { PCI_VDEVICE(REALTEK,  0x8136), RTL_CFG_NO_GBIT },
 210         { PCI_VDEVICE(REALTEK,  0x8161) },
 211         { PCI_VDEVICE(REALTEK,  0x8167) },
 212         { PCI_VDEVICE(REALTEK,  0x8168) },
 213         { PCI_VDEVICE(NCUBE,    0x8168) },
 214         { PCI_VDEVICE(REALTEK,  0x8169) },
 215         { PCI_VENDOR_ID_DLINK,  0x4300,
 216                 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0 },
 217         { PCI_VDEVICE(DLINK,    0x4300) },
 218         { PCI_VDEVICE(DLINK,    0x4302) },
 219         { PCI_VDEVICE(AT,       0xc107) },
 220         { PCI_VDEVICE(USR,      0x0116) },
 221         { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0024 },
 222         { 0x0001, 0x8168, PCI_ANY_ID, 0x2410 },
 223         {}
 224 };
 225
 226 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
 227
 228 static struct {
 229         u32 msg_enable;
 230 } debug = { -1 };
 231
 232 enum rtl_registers {
 233         MAC0            = 0,    /* Ethernet hardware address. */
 234         MAC4            = 4,
 235         MAR0            = 8,    /* Multicast filter. */
 236         CounterAddrLow          = 0x10,
 237         CounterAddrHigh         = 0x14,
 238         TxDescStartAddrLow      = 0x20,
 239         TxDescStartAddrHigh     = 0x24,
 240         TxHDescStartAddrLow     = 0x28,
 241         TxHDescStartAddrHigh    = 0x2c,
 242         FLASH           = 0x30,
 243         ERSR            = 0x36,
 244         ChipCmd         = 0x37,
 245         TxPoll          = 0x38,
 246         IntrMask        = 0x3c,
 247         IntrStatus      = 0x3e,
 248
 249         TxConfig        = 0x40,
 250 #define TXCFG_AUTO_FIFO                 (1 << 7)        /* 8111e-vl */
 251 #define TXCFG_EMPTY                     (1 << 11)       /* 8111e-vl */
 252
 253         RxConfig        = 0x44,
 254 #define RX128_INT_EN                    (1 << 15)       /* 8111c and later */
 255 #define RX_MULTI_EN                     (1 << 14)       /* 8111c only */
 256 #define RXCFG_FIFO_SHIFT                13
 257                                         /* No threshold before first PCI xfer */
 258 #define RX_FIFO_THRESH                  (7 << RXCFG_FIFO_SHIFT)
 259 #define RX_EARLY_OFF                    (1 << 11)
 260 #define RXCFG_DMA_SHIFT                 8
 261                                         /* Unlimited maximum PCI burst. */
 262 #define RX_DMA_BURST                    (7 << RXCFG_DMA_SHIFT)
 263
 264         RxMissed        = 0x4c,
 265         Cfg9346         = 0x50,
 266         Config0         = 0x51,
 267         Config1         = 0x52,
 268         Config2         = 0x53,
 269 #define PME_SIGNAL                      (1 << 5)        /* 8168c and later */
 270
 271         Config3         = 0x54,
 272         Config4         = 0x55,
 273         Config5         = 0x56,
 274         PHYAR           = 0x60,
 275         PHYstatus       = 0x6c,
 276         RxMaxSize       = 0xda,
 277         CPlusCmd        = 0xe0,
 278         IntrMitigate    = 0xe2,
 279
 280 #define RTL_COALESCE_MASK       0x0f
 281 #define RTL_COALESCE_SHIFT      4
 282 #define RTL_COALESCE_T_MAX      (RTL_COALESCE_MASK)
 283 #define RTL_COALESCE_FRAME_MAX  (RTL_COALESCE_MASK << 2)
 284
 285         RxDescAddrLow   = 0xe4,
 286         RxDescAddrHigh  = 0xe8,
 287         EarlyTxThres    = 0xec, /* 8169. Unit of 32 bytes. */
 288
 289 #define NoEarlyTx       0x3f    /* Max value : no early transmit. */
 290
 291         MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
 292
 293 #define TxPacketMax     (8064 >> 7)
 294 #define EarlySize       0x27
 295
 296         FuncEvent       = 0xf0,
 297         FuncEventMask   = 0xf4,
 298         FuncPresetState = 0xf8,
 299         IBCR0           = 0xf8,
 300         IBCR2           = 0xf9,
 301         IBIMR0          = 0xfa,
 302         IBISR0          = 0xfb,
 303         FuncForceEvent  = 0xfc,
 304 };
 305
 306 enum rtl8168_8101_registers {
 307         CSIDR                   = 0x64,
 308         CSIAR                   = 0x68,
 309 #define CSIAR_FLAG                      0x80000000
 310 #define CSIAR_WRITE_CMD                 0x80000000
 311 #define CSIAR_BYTE_ENABLE               0x0000f000
 312 #define CSIAR_ADDR_MASK                 0x00000fff
 313         PMCH                    = 0x6f,
 314         EPHYAR                  = 0x80,
 315 #define EPHYAR_FLAG                     0x80000000
 316 #define EPHYAR_WRITE_CMD                0x80000000
 317 #define EPHYAR_REG_MASK                 0x1f
 318 #define EPHYAR_REG_SHIFT                16
 319 #define EPHYAR_DATA_MASK                0xffff
 320         DLLPR                   = 0xd0,
 321 #define PFM_EN                          (1 << 6)
 322 #define TX_10M_PS_EN                    (1 << 7)
 323         DBG_REG                 = 0xd1,
 324 #define FIX_NAK_1                       (1 << 4)
 325 #define FIX_NAK_2                       (1 << 3)
 326         TWSI                    = 0xd2,
 327         MCU                     = 0xd3,
 328 #define NOW_IS_OOB                      (1 << 7)
 329 #define TX_EMPTY                        (1 << 5)
 330 #define RX_EMPTY                        (1 << 4)
 331 #define RXTX_EMPTY                      (TX_EMPTY | RX_EMPTY)
 332 #define EN_NDP                          (1 << 3)
 333 #define EN_OOB_RESET                    (1 << 2)
 334 #define LINK_LIST_RDY                   (1 << 1)
 335         EFUSEAR                 = 0xdc,
 336 #define EFUSEAR_FLAG                    0x80000000
 337 #define EFUSEAR_WRITE_CMD               0x80000000
 338 #define EFUSEAR_READ_CMD                0x00000000
 339 #define EFUSEAR_REG_MASK                0x03ff
 340 #define EFUSEAR_REG_SHIFT               8
 341 #define EFUSEAR_DATA_MASK               0xff
 342         MISC_1                  = 0xf2,
 343 #define PFM_D3COLD_EN                   (1 << 6)
 344 };
 345
 346 enum rtl8168_registers {
 347         LED_FREQ                = 0x1a,
 348         EEE_LED                 = 0x1b,
 349         ERIDR                   = 0x70,
 350         ERIAR                   = 0x74,
 351 #define ERIAR_FLAG                      0x80000000
 352 #define ERIAR_WRITE_CMD                 0x80000000
 353 #define ERIAR_READ_CMD                  0x00000000
 354 #define ERIAR_ADDR_BYTE_ALIGN           4
 355 #define ERIAR_TYPE_SHIFT                16
 356 #define ERIAR_EXGMAC                    (0x00 << ERIAR_TYPE_SHIFT)
 357 #define ERIAR_MSIX                      (0x01 << ERIAR_TYPE_SHIFT)
 358 #define ERIAR_ASF                       (0x02 << ERIAR_TYPE_SHIFT)
 359 #define ERIAR_OOB                       (0x02 << ERIAR_TYPE_SHIFT)
 360 #define ERIAR_MASK_SHIFT                12
 361 #define ERIAR_MASK_0001                 (0x1 << ERIAR_MASK_SHIFT)
 362 #define ERIAR_MASK_0011                 (0x3 << ERIAR_MASK_SHIFT)
 363 #define ERIAR_MASK_0100                 (0x4 << ERIAR_MASK_SHIFT)
 364 #define ERIAR_MASK_0101                 (0x5 << ERIAR_MASK_SHIFT)
 365 #define ERIAR_MASK_1111                 (0xf << ERIAR_MASK_SHIFT)
 366         EPHY_RXER_NUM           = 0x7c,
 367         OCPDR                   = 0xb0, /* OCP GPHY access */
 368 #define OCPDR_WRITE_CMD                 0x80000000
 369 #define OCPDR_READ_CMD                  0x00000000
 370 #define OCPDR_REG_MASK                  0x7f
 371 #define OCPDR_GPHY_REG_SHIFT            16
 372 #define OCPDR_DATA_MASK                 0xffff
 373         OCPAR                   = 0xb4,
 374 #define OCPAR_FLAG                      0x80000000
 375 #define OCPAR_GPHY_WRITE_CMD            0x8000f060
 376 #define OCPAR_GPHY_READ_CMD             0x0000f060
 377         GPHY_OCP                = 0xb8,
 378         RDSAR1                  = 0xd0, /* 8168c only. Undocumented on 8168dp */
 379         MISC                    = 0xf0, /* 8168e only. */
 380 #define TXPLA_RST                       (1 << 29)
 381 #define DISABLE_LAN_EN                  (1 << 23) /* Enable GPIO pin */
 382 #define PWM_EN                          (1 << 22)
 383 #define RXDV_GATED_EN                   (1 << 19)
 384 #define EARLY_TALLY_EN                  (1 << 16)
 385 };
 386
 387 enum rtl_register_content {
 388         /* InterruptStatusBits */
 389         SYSErr          = 0x8000,
 390         PCSTimeout      = 0x4000,
 391         SWInt           = 0x0100,
 392         TxDescUnavail   = 0x0080,
 393         RxFIFOOver      = 0x0040,
 394         LinkChg         = 0x0020,
 395         RxOverflow      = 0x0010,
 396         TxErr           = 0x0008,
 397         TxOK            = 0x0004,
 398         RxErr           = 0x0002,
 399         RxOK            = 0x0001,
 400
 401         /* RxStatusDesc */
 402         RxRWT   = (1 << 22),
 403         RxRES   = (1 << 21),
 404         RxRUNT  = (1 << 20),
 405         RxCRC   = (1 << 19),
 406
 407         /* ChipCmdBits */
 408         StopReq         = 0x80,
 409         CmdReset        = 0x10,
 410         CmdRxEnb        = 0x08,
 411         CmdTxEnb        = 0x04,
 412         RxBufEmpty      = 0x01,
 413
 414         /* TXPoll register p.5 */
 415         HPQ             = 0x80,         /* Poll cmd on the high prio queue */
 416         NPQ             = 0x40,         /* Poll cmd on the low prio queue */
 417         FSWInt          = 0x01,         /* Forced software interrupt */
 418
 419         /* Cfg9346Bits */
 420         Cfg9346_Lock    = 0x00,
 421         Cfg9346_Unlock  = 0xc0,
 422
 423         /* rx_mode_bits */
 424         AcceptErr       = 0x20,
 425         AcceptRunt      = 0x10,
 426         AcceptBroadcast = 0x08,
 427         AcceptMulticast = 0x04,
 428         AcceptMyPhys    = 0x02,
 429         AcceptAllPhys   = 0x01,
 430 #define RX_CONFIG_ACCEPT_MASK           0x3f
 431
 432         /* TxConfigBits */
 433         TxInterFrameGapShift = 24,
 434         TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
 435
 436         /* Config1 register p.24 */
 437         LEDS1           = (1 << 7),
 438         LEDS0           = (1 << 6),
 439         Speed_down      = (1 << 4),
 440         MEMMAP          = (1 << 3),
 441         IOMAP           = (1 << 2),
 442         VPD             = (1 << 1),
 443         PMEnable        = (1 << 0),     /* Power Management Enable */
 444
 445         /* Config2 register p. 25 */
 446         ClkReqEn        = (1 << 7),     /* Clock Request Enable */
 447         MSIEnable       = (1 << 5),     /* 8169 only. Reserved in the 8168. */
 448         PCI_Clock_66MHz = 0x01,
 449         PCI_Clock_33MHz = 0x00,
 450
 451         /* Config3 register p.25 */
 452         MagicPacket     = (1 << 5),     /* Wake up when receives a Magic Packet */
 453         LinkUp          = (1 << 4),     /* Wake up when the cable connection is re-established */
 454         Jumbo_En0       = (1 << 2),     /* 8168 only. Reserved in the 8168b */
 455         Rdy_to_L23      = (1 << 1),     /* L23 Enable */
 456         Beacon_en       = (1 << 0),     /* 8168 only. Reserved in the 8168b */
 457
 458         /* Config4 register */
 459         Jumbo_En1       = (1 << 1),     /* 8168 only. Reserved in the 8168b */
 460
 461         /* Config5 register p.27 */
 462         BWF             = (1 << 6),     /* Accept Broadcast wakeup frame */
 463         MWF             = (1 << 5),     /* Accept Multicast wakeup frame */
 464         UWF             = (1 << 4),     /* Accept Unicast wakeup frame */
 465         Spi_en          = (1 << 3),
 466         LanWake         = (1 << 1),     /* LanWake enable/disable */
 467         PMEStatus       = (1 << 0),     /* PME status can be reset by PCI RST# */
 468         ASPM_en         = (1 << 0),     /* ASPM enable */
 469
 470         /* CPlusCmd p.31 */
 471         EnableBist      = (1 << 15),    // 8168 8101
 472         Mac_dbgo_oe     = (1 << 14),    // 8168 8101
 473         Normal_mode     = (1 << 13),    // unused
 474         Force_half_dup  = (1 << 12),    // 8168 8101
 475         Force_rxflow_en = (1 << 11),    // 8168 8101
 476         Force_txflow_en = (1 << 10),    // 8168 8101
 477         Cxpl_dbg_sel    = (1 << 9),     // 8168 8101
 478         ASF             = (1 << 8),     // 8168 8101
 479         PktCntrDisable  = (1 << 7),     // 8168 8101
 480         Mac_dbgo_sel    = 0x001c,       // 8168
 481         RxVlan          = (1 << 6),
 482         RxChkSum        = (1 << 5),
 483         PCIDAC          = (1 << 4),
 484         PCIMulRW        = (1 << 3),
 485 #define INTT_MASK       GENMASK(1, 0)
 486 #define CPCMD_MASK      (Normal_mode | RxVlan | RxChkSum | INTT_MASK)
 487
 488         /* rtl8169_PHYstatus */
 489         TBI_Enable      = 0x80,
 490         TxFlowCtrl      = 0x40,
 491         RxFlowCtrl      = 0x20,
 492         _1000bpsF       = 0x10,
 493         _100bps         = 0x08,
 494         _10bps          = 0x04,
 495         LinkStatus      = 0x02,
 496         FullDup         = 0x01,
 497
 498         /* ResetCounterCommand */
 499         CounterReset    = 0x1,
 500
 501         /* DumpCounterCommand */
 502         CounterDump     = 0x8,
 503
 504         /* magic enable v2 */
 505         MagicPacket_v2  = (1 << 16),    /* Wake up when receives a Magic Packet */
 506 };
 507
 508 enum rtl_desc_bit {
 509         /* First doubleword. */
 510         DescOwn         = (1 << 31), /* Descriptor is owned by NIC */
 511         RingEnd         = (1 << 30), /* End of descriptor ring */
 512         FirstFrag       = (1 << 29), /* First segment of a packet */
 513         LastFrag        = (1 << 28), /* Final segment of a packet */
 514 };
 515
 516 /* Generic case. */
 517 enum rtl_tx_desc_bit {
 518         /* First doubleword. */
 519         TD_LSO          = (1 << 27),            /* Large Send Offload */
 520 #define TD_MSS_MAX                      0x07ffu /* MSS value */
 521
 522         /* Second doubleword. */
 523         TxVlanTag       = (1 << 17),            /* Add VLAN tag */
 524 };
 525
 526 /* 8169, 8168b and 810x except 8102e. */
 527 enum rtl_tx_desc_bit_0 {
 528         /* First doubleword. */
 529 #define TD0_MSS_SHIFT                   16      /* MSS position (11 bits) */
 530         TD0_TCP_CS      = (1 << 16),            /* Calculate TCP/IP checksum */
 531         TD0_UDP_CS      = (1 << 17),            /* Calculate UDP/IP checksum */
 532         TD0_IP_CS       = (1 << 18),            /* Calculate IP checksum */
 533 };
 534
 535 /* 8102e, 8168c and beyond. */
 536 enum rtl_tx_desc_bit_1 {
 537         /* First doubleword. */
 538         TD1_GTSENV4     = (1 << 26),            /* Giant Send for IPv4 */
 539         TD1_GTSENV6     = (1 << 25),            /* Giant Send for IPv6 */
 540 #define GTTCPHO_SHIFT                   18
 541 #define GTTCPHO_MAX                     0x7f
 542
 543         /* Second doubleword. */
 544 #define TCPHO_SHIFT                     18
 545 #define TCPHO_MAX                       0x3ff
 546 #define TD1_MSS_SHIFT                   18      /* MSS position (11 bits) */
 547         TD1_IPv6_CS     = (1 << 28),            /* Calculate IPv6 checksum */
 548         TD1_IPv4_CS     = (1 << 29),            /* Calculate IPv4 checksum */
 549         TD1_TCP_CS      = (1 << 30),            /* Calculate TCP/IP checksum */
 550         TD1_UDP_CS      = (1 << 31),            /* Calculate UDP/IP checksum */
 551 };
 552
 553 enum rtl_rx_desc_bit {
 554         /* Rx private */
 555         PID1            = (1 << 18), /* Protocol ID bit 1/2 */
 556         PID0            = (1 << 17), /* Protocol ID bit 0/2 */
 557
 558 #define RxProtoUDP      (PID1)
 559 #define RxProtoTCP      (PID0)
 560 #define RxProtoIP       (PID1 | PID0)
 561 #define RxProtoMask     RxProtoIP
 562
 563         IPFail          = (1 << 16), /* IP checksum failed */
 564         UDPFail         = (1 << 15), /* UDP/IP checksum failed */
 565         TCPFail         = (1 << 14), /* TCP/IP checksum failed */
 566         RxVlanTag       = (1 << 16), /* VLAN tag available */
 567 };
 568
 569 #define RsvdMask        0x3fffc000
 570
 571 #define RTL_GSO_MAX_SIZE_V1     32000
 572 #define RTL_GSO_MAX_SEGS_V1     24
 573 #define RTL_GSO_MAX_SIZE_V2     64000
 574 #define RTL_GSO_MAX_SEGS_V2     64
 575
 576 struct TxDesc {
 577         __le32 opts1;
 578         __le32 opts2;
 579         __le64 addr;
 580 };
 581
 582 struct RxDesc {
 583         __le32 opts1;
 584         __le32 opts2;
 585         __le64 addr;
 586 };
 587
 588 struct ring_info {
 589         struct sk_buff  *skb;
 590         u32             len;
 591 };
 592
 593 struct rtl8169_counters {
 594         __le64  tx_packets;
 595         __le64  rx_packets;
 596         __le64  tx_errors;
 597         __le32  rx_errors;
 598         __le16  rx_missed;
 599         __le16  align_errors;
 600         __le32  tx_one_collision;
 601         __le32  tx_multi_collision;
 602         __le64  rx_unicast;
 603         __le64  rx_broadcast;
 604         __le32  rx_multicast;
 605         __le16  tx_aborted;
 606         __le16  tx_underun;
 607 };
 608
 609 struct rtl8169_tc_offsets {
 610         bool    inited;
 611         __le64  tx_errors;
 612         __le32  tx_multi_collision;
 613         __le16  tx_aborted;
 614 };
 615
 616 enum rtl_flag {
 617         RTL_FLAG_TASK_ENABLED = 0,
 618         RTL_FLAG_TASK_RESET_PENDING,
 619         RTL_FLAG_MAX
 620 };
 621
 622 struct rtl8169_stats {
 623         u64                     packets;
 624         u64                     bytes;
 625         struct u64_stats_sync   syncp;
 626 };
 627
 628 struct rtl8169_private {
 629         void __iomem *mmio_addr;        /* memory map physical address */
 630         struct pci_dev *pci_dev;
 631         struct net_device *dev;
 632         struct phy_device *phydev;
 633         struct napi_struct napi;
 634         u32 msg_enable;
 635         enum mac_version mac_version;
 636         u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
 637         u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
 638         u32 dirty_tx;
 639         struct rtl8169_stats rx_stats;
 640         struct rtl8169_stats tx_stats;
 641         struct TxDesc *TxDescArray;     /* 256-aligned Tx descriptor ring */
 642         struct RxDesc *RxDescArray;     /* 256-aligned Rx descriptor ring */
 643         dma_addr_t TxPhyAddr;
 644         dma_addr_t RxPhyAddr;
 645         void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
 646         struct ring_info tx_skb[NUM_TX_DESC];   /* Tx data buffers */
 647         u16 cp_cmd;
 648         u16 irq_mask;
 649         struct clk *clk;
 650
 651         struct {
 652                 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
 653                 struct mutex mutex;
 654                 struct work_struct work;
 655         } wk;
 656
 657         unsigned irq_enabled:1;
 658         unsigned supports_gmii:1;
 659         unsigned aspm_manageable:1;
 660         dma_addr_t counters_phys_addr;
 661         struct rtl8169_counters *counters;
 662         struct rtl8169_tc_offsets tc_offset;
 663         u32 saved_wolopts;
 664
 665         const char *fw_name;
 666         struct rtl_fw *rtl_fw;
 667
 668         u32 ocp_base;
 669 };
 670
 671 typedef void (*rtl_generic_fct)(struct rtl8169_private *tp);
 672
 673 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
 674 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
 675 module_param_named(debug, debug.msg_enable, int, 0);
 676 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
 677 MODULE_SOFTDEP("pre: realtek");
 678 MODULE_LICENSE("GPL");
 679 MODULE_FIRMWARE(FIRMWARE_8168D_1);
 680 MODULE_FIRMWARE(FIRMWARE_8168D_2);
 681 MODULE_FIRMWARE(FIRMWARE_8168E_1);
 682 MODULE_FIRMWARE(FIRMWARE_8168E_2);
 683 MODULE_FIRMWARE(FIRMWARE_8168E_3);
 684 MODULE_FIRMWARE(FIRMWARE_8105E_1);
 685 MODULE_FIRMWARE(FIRMWARE_8168F_1);
 686 MODULE_FIRMWARE(FIRMWARE_8168F_2);
 687 MODULE_FIRMWARE(FIRMWARE_8402_1);
 688 MODULE_FIRMWARE(FIRMWARE_8411_1);
 689 MODULE_FIRMWARE(FIRMWARE_8411_2);
 690 MODULE_FIRMWARE(FIRMWARE_8106E_1);
 691 MODULE_FIRMWARE(FIRMWARE_8106E_2);
 692 MODULE_FIRMWARE(FIRMWARE_8168G_2);
 693 MODULE_FIRMWARE(FIRMWARE_8168G_3);
 694 MODULE_FIRMWARE(FIRMWARE_8168H_1);
 695 MODULE_FIRMWARE(FIRMWARE_8168H_2);
 696 MODULE_FIRMWARE(FIRMWARE_8107E_1);
 697 MODULE_FIRMWARE(FIRMWARE_8107E_2);
 698
 699 static inline struct device *tp_to_dev(struct rtl8169_private *tp)
 700 {
 701         return &tp->pci_dev->dev;
 702 }
 703
 704 static void rtl_lock_work(struct rtl8169_private *tp)
 705 {
 706         mutex_lock(&tp->wk.mutex);
 707 }
 708
 709 static void rtl_unlock_work(struct rtl8169_private *tp)
 710 {
 711         mutex_unlock(&tp->wk.mutex);
 712 }
 713
 714 static void rtl_lock_config_regs(struct rtl8169_private *tp)
 715 {
 716         RTL_W8(tp, Cfg9346, Cfg9346_Lock);
 717 }
 718
 719 static void rtl_unlock_config_regs(struct rtl8169_private *tp)
 720 {
 721         RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
 722 }
 723
 724 static void rtl_tx_performance_tweak(struct rtl8169_private *tp, u16 force)
 725 {
 726         pcie_capability_clear_and_set_word(tp->pci_dev, PCI_EXP_DEVCTL,
 727                                            PCI_EXP_DEVCTL_READRQ, force);
 728 }
 729
 730 static bool rtl_is_8168evl_up(struct rtl8169_private *tp)
 731 {
 732         return tp->mac_version >= RTL_GIGA_MAC_VER_34 &&
 733                tp->mac_version != RTL_GIGA_MAC_VER_39;
 734 }
 735
 736 struct rtl_cond {
 737         bool (*check)(struct rtl8169_private *);
 738         const char *msg;
 739 };
 740
 741 static void rtl_udelay(unsigned int d)
 742 {
 743         udelay(d);
 744 }
 745
 746 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,
 747                           void (*delay)(unsigned int), unsigned int d, int n,
 748                           bool high)
 749 {
 750         int i;
 751
 752         for (i = 0; i < n; i++) {
 753                 if (c->check(tp) == high)
 754                         return true;
 755                 delay(d);
 756         }
 757         netif_err(tp, drv, tp->dev, "%s == %d (loop: %d, delay: %d).\n",
 758                   c->msg, !high, n, d);
 759         return false;
 760 }
 761
 762 static bool rtl_udelay_loop_wait_high(struct rtl8169_private *tp,
 763                                       const struct rtl_cond *c,
 764                                       unsigned int d, int n)
 765 {
 766         return rtl_loop_wait(tp, c, rtl_udelay, d, n, true);
 767 }
 768
 769 static bool rtl_udelay_loop_wait_low(struct rtl8169_private *tp,
 770                                      const struct rtl_cond *c,
 771                                      unsigned int d, int n)
 772 {
 773         return rtl_loop_wait(tp, c, rtl_udelay, d, n, false);
 774 }
 775
 776 static bool rtl_msleep_loop_wait_high(struct rtl8169_private *tp,
 777                                       const struct rtl_cond *c,
 778                                       unsigned int d, int n)
 779 {
 780         return rtl_loop_wait(tp, c, msleep, d, n, true);
 781 }
 782
 783 static bool rtl_msleep_loop_wait_low(struct rtl8169_private *tp,
 784                                      const struct rtl_cond *c,
 785                                      unsigned int d, int n)
 786 {
 787         return rtl_loop_wait(tp, c, msleep, d, n, false);
 788 }
 789
 790 #define DECLARE_RTL_COND(name)                          \
 791 static bool name ## _check(struct rtl8169_private *);   \
 792                                                         \
 793 static const struct rtl_cond name = {                   \
 794         .check  = name ## _check,                       \
 795         .msg    = #name                                 \
 796 };                                                      \
 797                                                         \
 798 static bool name ## _check(struct rtl8169_private *tp)
 799
 800 static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg)
 801 {
 802         if (reg & 0xffff0001) {
 803                 netif_err(tp, drv, tp->dev, "Invalid ocp reg %x!\n", reg);
 804                 return true;
 805         }
 806         return false;
 807 }
 808
 809 DECLARE_RTL_COND(rtl_ocp_gphy_cond)
 810 {
 811         return RTL_R32(tp, GPHY_OCP) & OCPAR_FLAG;
 812 }
 813
 814 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
 815 {
 816         if (rtl_ocp_reg_failure(tp, reg))
 817                 return;
 818
 819         RTL_W32(tp, GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);
 820
 821         rtl_udelay_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);
 822 }
 823
 824 static int r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
 825 {
 826         if (rtl_ocp_reg_failure(tp, reg))
 827                 return 0;
 828
 829         RTL_W32(tp, GPHY_OCP, reg << 15);
 830
 831         return rtl_udelay_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?
 832                 (RTL_R32(tp, GPHY_OCP) & 0xffff) : -ETIMEDOUT;
 833 }
 834
 835 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
 836 {
 837         if (rtl_ocp_reg_failure(tp, reg))
 838                 return;
 839
 840         RTL_W32(tp, OCPDR, OCPAR_FLAG | (reg << 15) | data);
 841 }
 842
 843 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
 844 {
 845         if (rtl_ocp_reg_failure(tp, reg))
 846                 return 0;
 847
 848         RTL_W32(tp, OCPDR, reg << 15);
 849
 850         return RTL_R32(tp, OCPDR);
 851 }
 852
 853 static void r8168_mac_ocp_modify(struct rtl8169_private *tp, u32 reg, u16 mask,
 854                                  u16 set)
 855 {
 856         u16 data = r8168_mac_ocp_read(tp, reg);
 857
 858         r8168_mac_ocp_write(tp, reg, (data & ~mask) | set);
 859 }
 860
 861 #define OCP_STD_PHY_BASE        0xa400
 862
 863 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)
 864 {
 865         if (reg == 0x1f) {
 866                 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;
 867                 return;
 868         }
 869
 870         if (tp->ocp_base != OCP_STD_PHY_BASE)
 871                 reg -= 0x10;
 872
 873         r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);
 874 }
 875
 876 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)
 877 {
 878         if (tp->ocp_base != OCP_STD_PHY_BASE)
 879                 reg -= 0x10;
 880
 881         return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);
 882 }
 883
 884 static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value)
 885 {
 886         if (reg == 0x1f) {
 887                 tp->ocp_base = value << 4;
 888                 return;
 889         }
 890
 891         r8168_mac_ocp_write(tp, tp->ocp_base + reg, value);
 892 }
 893
 894 static int mac_mcu_read(struct rtl8169_private *tp, int reg)
 895 {
 896         return r8168_mac_ocp_read(tp, tp->ocp_base + reg);
 897 }
 898
 899 DECLARE_RTL_COND(rtl_phyar_cond)
 900 {
 901         return RTL_R32(tp, PHYAR) & 0x80000000;
 902 }
 903
 904 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)
 905 {
 906         RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
 907
 908         rtl_udelay_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);
 909         /*
 910          * According to hardware specs a 20us delay is required after write
 911          * complete indication, but before sending next command.
 912          */
 913         udelay(20);
 914 }
 915
 916 static int r8169_mdio_read(struct rtl8169_private *tp, int reg)
 917 {
 918         int value;
 919
 920         RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16);
 921
 922         value = rtl_udelay_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?
 923                 RTL_R32(tp, PHYAR) & 0xffff : -ETIMEDOUT;
 924
 925         /*
 926          * According to hardware specs a 20us delay is required after read
 927          * complete indication, but before sending next command.
 928          */
 929         udelay(20);
 930
 931         return value;
 932 }
 933
 934 DECLARE_RTL_COND(rtl_ocpar_cond)
 935 {
 936         return RTL_R32(tp, OCPAR) & OCPAR_FLAG;
 937 }
 938
 939 static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data)
 940 {
 941         RTL_W32(tp, OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
 942         RTL_W32(tp, OCPAR, OCPAR_GPHY_WRITE_CMD);
 943         RTL_W32(tp, EPHY_RXER_NUM, 0);
 944
 945         rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100);
 946 }
 947
 948 static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value)
 949 {
 950         r8168dp_1_mdio_access(tp, reg,
 951                               OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK));
 952 }
 953
 954 static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg)
 955 {
 956         r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD);
 957
 958         mdelay(1);
 959         RTL_W32(tp, OCPAR, OCPAR_GPHY_READ_CMD);
 960         RTL_W32(tp, EPHY_RXER_NUM, 0);
 961
 962         return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ?
 963                 RTL_R32(tp, OCPDR) & OCPDR_DATA_MASK : -ETIMEDOUT;
 964 }
 965
 966 #define R8168DP_1_MDIO_ACCESS_BIT       0x00020000
 967
 968 static void r8168dp_2_mdio_start(struct rtl8169_private *tp)
 969 {
 970         RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
 971 }
 972
 973 static void r8168dp_2_mdio_stop(struct rtl8169_private *tp)
 974 {
 975         RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
 976 }
 977
 978 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)
 979 {
 980         r8168dp_2_mdio_start(tp);
 981
 982         r8169_mdio_write(tp, reg, value);
 983
 984         r8168dp_2_mdio_stop(tp);
 985 }
 986
 987 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)
 988 {
 989         int value;
 990
 991         r8168dp_2_mdio_start(tp);
 992
 993         value = r8169_mdio_read(tp, reg);
 994
 995         r8168dp_2_mdio_stop(tp);
 996
 997         return value;
 998 }
 999
1000 static void rtl_writephy(struct rtl8169_private *tp, int location, int val)
1001 {
1002         switch (tp->mac_version) {
1003         case RTL_GIGA_MAC_VER_27:
1004                 r8168dp_1_mdio_write(tp, location, val);
1005                 break;
1006         case RTL_GIGA_MAC_VER_28:
1007         case RTL_GIGA_MAC_VER_31:
1008                 r8168dp_2_mdio_write(tp, location, val);
1009                 break;
1010         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
1011                 r8168g_mdio_write(tp, location, val);
1012                 break;
1013         default:
1014                 r8169_mdio_write(tp, location, val);
1015                 break;
1016         }
1017 }
1018
1019 static int rtl_readphy(struct rtl8169_private *tp, int location)
1020 {
1021         switch (tp->mac_version) {
1022         case RTL_GIGA_MAC_VER_27:
1023                 return r8168dp_1_mdio_read(tp, location);
1024         case RTL_GIGA_MAC_VER_28:
1025         case RTL_GIGA_MAC_VER_31:
1026                 return r8168dp_2_mdio_read(tp, location);
1027         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
1028                 return r8168g_mdio_read(tp, location);
1029         default:
1030                 return r8169_mdio_read(tp, location);
1031         }
1032 }
1033
1034 static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
1035 {
1036         rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
1037 }
1038
1039 static void rtl_w0w1_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
1040 {
1041         int val;
1042
1043         val = rtl_readphy(tp, reg_addr);
1044         rtl_writephy(tp, reg_addr, (val & ~m) | p);
1045 }
1046
1047 DECLARE_RTL_COND(rtl_ephyar_cond)
1048 {
1049         return RTL_R32(tp, EPHYAR) & EPHYAR_FLAG;
1050 }
1051
1052 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)
1053 {
1054         RTL_W32(tp, EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1055                 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1056
1057         rtl_udelay_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);
1058
1059         udelay(10);
1060 }
1061
1062 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)
1063 {
1064         RTL_W32(tp, EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1065
1066         return rtl_udelay_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?
1067                 RTL_R32(tp, EPHYAR) & EPHYAR_DATA_MASK : ~0;
1068 }
1069
1070 DECLARE_RTL_COND(rtl_eriar_cond)
1071 {
1072         return RTL_R32(tp, ERIAR) & ERIAR_FLAG;
1073 }
1074
1075 static void _rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1076                            u32 val, int type)
1077 {
1078         BUG_ON((addr & 3) || (mask == 0));
1079         RTL_W32(tp, ERIDR, val);
1080         RTL_W32(tp, ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
1081
1082         rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);
1083 }
1084
1085 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1086                           u32 val)
1087 {
1088         _rtl_eri_write(tp, addr, mask, val, ERIAR_EXGMAC);
1089 }
1090
1091 static u32 _rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
1092 {
1093         RTL_W32(tp, ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
1094
1095         return rtl_udelay_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?
1096                 RTL_R32(tp, ERIDR) : ~0;
1097 }
1098
1099 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr)
1100 {
1101         return _rtl_eri_read(tp, addr, ERIAR_EXGMAC);
1102 }
1103
1104 static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 mask, u32 p,
1105                          u32 m)
1106 {
1107         u32 val;
1108
1109         val = rtl_eri_read(tp, addr);
1110         rtl_eri_write(tp, addr, mask, (val & ~m) | p);
1111 }
1112
1113 static void rtl_eri_set_bits(struct rtl8169_private *tp, int addr, u32 mask,
1114                              u32 p)
1115 {
1116         rtl_w0w1_eri(tp, addr, mask, p, 0);
1117 }
1118
1119 static void rtl_eri_clear_bits(struct rtl8169_private *tp, int addr, u32 mask,
1120                                u32 m)
1121 {
1122         rtl_w0w1_eri(tp, addr, mask, 0, m);
1123 }
1124
1125 static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1126 {
1127         RTL_W32(tp, OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1128         return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?
1129                 RTL_R32(tp, OCPDR) : ~0;
1130 }
1131
1132 static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1133 {
1134         return _rtl_eri_read(tp, reg, ERIAR_OOB);
1135 }
1136
1137 static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1138                               u32 data)
1139 {
1140         RTL_W32(tp, OCPDR, data);
1141         RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1142         rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);
1143 }
1144
1145 static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1146                               u32 data)
1147 {
1148         _rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT,
1149                        data, ERIAR_OOB);
1150 }
1151
1152 static void r8168dp_oob_notify(struct rtl8169_private *tp, u8 cmd)
1153 {
1154         rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd);
1155
1156         r8168dp_ocp_write(tp, 0x1, 0x30, 0x00000001);
1157 }
1158
1159 #define OOB_CMD_RESET           0x00
1160 #define OOB_CMD_DRIVER_START    0x05
1161 #define OOB_CMD_DRIVER_STOP     0x06
1162
1163 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
1164 {
1165         return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
1166 }
1167
1168 DECLARE_RTL_COND(rtl_dp_ocp_read_cond)
1169 {
1170         u16 reg;
1171
1172         reg = rtl8168_get_ocp_reg(tp);
1173
1174         return r8168dp_ocp_read(tp, 0x0f, reg) & 0x00000800;
1175 }
1176
1177 DECLARE_RTL_COND(rtl_ep_ocp_read_cond)
1178 {
1179         return r8168ep_ocp_read(tp, 0x0f, 0x124) & 0x00000001;
1180 }
1181
1182 DECLARE_RTL_COND(rtl_ocp_tx_cond)
1183 {
1184         return RTL_R8(tp, IBISR0) & 0x20;
1185 }
1186
1187 static void rtl8168ep_stop_cmac(struct rtl8169_private *tp)
1188 {
1189         RTL_W8(tp, IBCR2, RTL_R8(tp, IBCR2) & ~0x01);
1190         rtl_msleep_loop_wait_high(tp, &rtl_ocp_tx_cond, 50, 2000);
1191         RTL_W8(tp, IBISR0, RTL_R8(tp, IBISR0) | 0x20);
1192         RTL_W8(tp, IBCR0, RTL_R8(tp, IBCR0) & ~0x01);
1193 }
1194
1195 static void rtl8168dp_driver_start(struct rtl8169_private *tp)
1196 {
1197         r8168dp_oob_notify(tp, OOB_CMD_DRIVER_START);
1198         rtl_msleep_loop_wait_high(tp, &rtl_dp_ocp_read_cond, 10, 10);
1199 }
1200
1201 static void rtl8168ep_driver_start(struct rtl8169_private *tp)
1202 {
1203         r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START);
1204         r8168ep_ocp_write(tp, 0x01, 0x30,
1205                           r8168ep_ocp_read(tp, 0x01, 0x30) | 0x01);
1206         rtl_msleep_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10, 10);
1207 }
1208
1209 static void rtl8168_driver_start(struct rtl8169_private *tp)
1210 {
1211         switch (tp->mac_version) {
1212         case RTL_GIGA_MAC_VER_27:
1213         case RTL_GIGA_MAC_VER_28:
1214         case RTL_GIGA_MAC_VER_31:
1215                 rtl8168dp_driver_start(tp);
1216                 break;
1217         case RTL_GIGA_MAC_VER_49:
1218         case RTL_GIGA_MAC_VER_50:
1219         case RTL_GIGA_MAC_VER_51:
1220                 rtl8168ep_driver_start(tp);
1221                 break;
1222         default:
1223                 BUG();
1224                 break;
1225         }
1226 }
1227
1228 static void rtl8168dp_driver_stop(struct rtl8169_private *tp)
1229 {
1230         r8168dp_oob_notify(tp, OOB_CMD_DRIVER_STOP);
1231         rtl_msleep_loop_wait_low(tp, &rtl_dp_ocp_read_cond, 10, 10);
1232 }
1233
1234 static void rtl8168ep_driver_stop(struct rtl8169_private *tp)
1235 {
1236         rtl8168ep_stop_cmac(tp);
1237         r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP);
1238         r8168ep_ocp_write(tp, 0x01, 0x30,
1239                           r8168ep_ocp_read(tp, 0x01, 0x30) | 0x01);
1240         rtl_msleep_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10, 10);
1241 }
1242
1243 static void rtl8168_driver_stop(struct rtl8169_private *tp)
1244 {
1245         switch (tp->mac_version) {
1246         case RTL_GIGA_MAC_VER_27:
1247         case RTL_GIGA_MAC_VER_28:
1248         case RTL_GIGA_MAC_VER_31:
1249                 rtl8168dp_driver_stop(tp);
1250                 break;
1251         case RTL_GIGA_MAC_VER_49:
1252         case RTL_GIGA_MAC_VER_50:
1253         case RTL_GIGA_MAC_VER_51:
1254                 rtl8168ep_driver_stop(tp);
1255                 break;
1256         default:
1257                 BUG();
1258                 break;
1259         }
1260 }
1261
1262 static bool r8168dp_check_dash(struct rtl8169_private *tp)
1263 {
1264         u16 reg = rtl8168_get_ocp_reg(tp);
1265
1266         return !!(r8168dp_ocp_read(tp, 0x0f, reg) & 0x00008000);
1267 }
1268
1269 static bool r8168ep_check_dash(struct rtl8169_private *tp)
1270 {
1271         return !!(r8168ep_ocp_read(tp, 0x0f, 0x128) & 0x00000001);
1272 }
1273
1274 static bool r8168_check_dash(struct rtl8169_private *tp)
1275 {
1276         switch (tp->mac_version) {
1277         case RTL_GIGA_MAC_VER_27:
1278         case RTL_GIGA_MAC_VER_28:
1279         case RTL_GIGA_MAC_VER_31:
1280                 return r8168dp_check_dash(tp);
1281         case RTL_GIGA_MAC_VER_49:
1282         case RTL_GIGA_MAC_VER_50:
1283         case RTL_GIGA_MAC_VER_51:
1284                 return r8168ep_check_dash(tp);
1285         default:
1286                 return false;
1287         }
1288 }
1289
1290 static void rtl_reset_packet_filter(struct rtl8169_private *tp)
1291 {
1292         rtl_eri_clear_bits(tp, 0xdc, ERIAR_MASK_0001, BIT(0));
1293         rtl_eri_set_bits(tp, 0xdc, ERIAR_MASK_0001, BIT(0));
1294 }
1295
1296 DECLARE_RTL_COND(rtl_efusear_cond)
1297 {
1298         return RTL_R32(tp, EFUSEAR) & EFUSEAR_FLAG;
1299 }
1300
1301 static u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)
1302 {
1303         RTL_W32(tp, EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1304
1305         return rtl_udelay_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?
1306                 RTL_R32(tp, EFUSEAR) & EFUSEAR_DATA_MASK : ~0;
1307 }
1308
1309 static void rtl_ack_events(struct rtl8169_private *tp, u16 bits)
1310 {
1311         RTL_W16(tp, IntrStatus, bits);
1312 }
1313
1314 static void rtl_irq_disable(struct rtl8169_private *tp)
1315 {
1316         RTL_W16(tp, IntrMask, 0);
1317         tp->irq_enabled = 0;
1318 }
1319
1320 #define RTL_EVENT_NAPI_RX       (RxOK | RxErr)
1321 #define RTL_EVENT_NAPI_TX       (TxOK | TxErr)
1322 #define RTL_EVENT_NAPI          (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX)
1323
1324 static void rtl_irq_enable(struct rtl8169_private *tp)
1325 {
1326         tp->irq_enabled = 1;
1327         RTL_W16(tp, IntrMask, tp->irq_mask);
1328 }
1329
1330 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1331 {
1332         rtl_irq_disable(tp);
1333         rtl_ack_events(tp, 0xffff);
1334         /* PCI commit */
1335         RTL_R8(tp, ChipCmd);
1336 }
1337
1338 static void rtl_link_chg_patch(struct rtl8169_private *tp)
1339 {
1340         struct net_device *dev = tp->dev;
1341         struct phy_device *phydev = tp->phydev;
1342
1343         if (!netif_running(dev))
1344                 return;
1345
1346         if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
1347             tp->mac_version == RTL_GIGA_MAC_VER_38) {
1348                 if (phydev->speed == SPEED_1000) {
1349                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011);
1350                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
1351                 } else if (phydev->speed == SPEED_100) {
1352                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1353                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
1354                 } else {
1355                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1356                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f);
1357                 }
1358                 rtl_reset_packet_filter(tp);
1359         } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1360                    tp->mac_version == RTL_GIGA_MAC_VER_36) {
1361                 if (phydev->speed == SPEED_1000) {
1362                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011);
1363                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
1364                 } else {
1365                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1366                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f);
1367                 }
1368         } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
1369                 if (phydev->speed == SPEED_10) {
1370                         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02);
1371                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060a);
1372                 } else {
1373                         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000);
1374                 }
1375         }
1376 }
1377
1378 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1379
1380 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1381 {
1382         struct rtl8169_private *tp = netdev_priv(dev);
1383
1384         rtl_lock_work(tp);
1385         wol->supported = WAKE_ANY;
1386         wol->wolopts = tp->saved_wolopts;
1387         rtl_unlock_work(tp);
1388 }
1389
1390 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1391 {
1392         unsigned int i, tmp;
1393         static const struct {
1394                 u32 opt;
1395                 u16 reg;
1396                 u8  mask;
1397         } cfg[] = {
1398                 { WAKE_PHY,   Config3, LinkUp },
1399                 { WAKE_UCAST, Config5, UWF },
1400                 { WAKE_BCAST, Config5, BWF },
1401                 { WAKE_MCAST, Config5, MWF },
1402                 { WAKE_ANY,   Config5, LanWake },
1403                 { WAKE_MAGIC, Config3, MagicPacket }
1404         };
1405         u8 options;
1406
1407         rtl_unlock_config_regs(tp);
1408
1409         if (rtl_is_8168evl_up(tp)) {
1410                 tmp = ARRAY_SIZE(cfg) - 1;
1411                 if (wolopts & WAKE_MAGIC)
1412                         rtl_eri_set_bits(tp, 0x0dc, ERIAR_MASK_0100,
1413                                          MagicPacket_v2);
1414                 else
1415                         rtl_eri_clear_bits(tp, 0x0dc, ERIAR_MASK_0100,
1416                                            MagicPacket_v2);
1417         } else {
1418                 tmp = ARRAY_SIZE(cfg);
1419         }
1420
1421         for (i = 0; i < tmp; i++) {
1422                 options = RTL_R8(tp, cfg[i].reg) & ~cfg[i].mask;
1423                 if (wolopts & cfg[i].opt)
1424                         options |= cfg[i].mask;
1425                 RTL_W8(tp, cfg[i].reg, options);
1426         }
1427
1428         switch (tp->mac_version) {
1429         case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
1430                 options = RTL_R8(tp, Config1) & ~PMEnable;
1431                 if (wolopts)
1432                         options |= PMEnable;
1433                 RTL_W8(tp, Config1, options);
1434                 break;
1435         case RTL_GIGA_MAC_VER_34:
1436         case RTL_GIGA_MAC_VER_37:
1437         case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_51:
1438                 options = RTL_R8(tp, Config2) & ~PME_SIGNAL;
1439                 if (wolopts)
1440                         options |= PME_SIGNAL;
1441                 RTL_W8(tp, Config2, options);
1442                 break;
1443         default:
1444                 break;
1445         }
1446
1447         rtl_lock_config_regs(tp);
1448
1449         device_set_wakeup_enable(tp_to_dev(tp), wolopts);
1450 }
1451
1452 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1453 {
1454         struct rtl8169_private *tp = netdev_priv(dev);
1455         struct device *d = tp_to_dev(tp);
1456
1457         if (wol->wolopts & ~WAKE_ANY)
1458                 return -EINVAL;
1459
1460         pm_runtime_get_noresume(d);
1461
1462         rtl_lock_work(tp);
1463
1464         tp->saved_wolopts = wol->wolopts;
1465
1466         if (pm_runtime_active(d))
1467                 __rtl8169_set_wol(tp, tp->saved_wolopts);
1468
1469         rtl_unlock_work(tp);
1470
1471         pm_runtime_put_noidle(d);
1472
1473         return 0;
1474 }
1475
1476 static void rtl8169_get_drvinfo(struct net_device *dev,
1477                                 struct ethtool_drvinfo *info)
1478 {
1479         struct rtl8169_private *tp = netdev_priv(dev);
1480         struct rtl_fw *rtl_fw = tp->rtl_fw;
1481
1482         strlcpy(info->driver, MODULENAME, sizeof(info->driver));
1483         strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1484         BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
1485         if (rtl_fw)
1486                 strlcpy(info->fw_version, rtl_fw->version,
1487                         sizeof(info->fw_version));
1488 }
1489
1490 static int rtl8169_get_regs_len(struct net_device *dev)
1491 {
1492         return R8169_REGS_SIZE;
1493 }
1494
1495 static netdev_features_t rtl8169_fix_features(struct net_device *dev,
1496         netdev_features_t features)
1497 {
1498         struct rtl8169_private *tp = netdev_priv(dev);
1499
1500         if (dev->mtu > TD_MSS_MAX)
1501                 features &= ~NETIF_F_ALL_TSO;
1502
1503         if (dev->mtu > JUMBO_1K &&
1504             tp->mac_version > RTL_GIGA_MAC_VER_06)
1505                 features &= ~NETIF_F_IP_CSUM;
1506
1507         return features;
1508 }
1509
1510 static int rtl8169_set_features(struct net_device *dev,
1511                                 netdev_features_t features)
1512 {
1513         struct rtl8169_private *tp = netdev_priv(dev);
1514         u32 rx_config;
1515
1516         rtl_lock_work(tp);
1517
1518         rx_config = RTL_R32(tp, RxConfig);
1519         if (features & NETIF_F_RXALL)
1520                 rx_config |= (AcceptErr | AcceptRunt);
1521         else
1522                 rx_config &= ~(AcceptErr | AcceptRunt);
1523
1524         RTL_W32(tp, RxConfig, rx_config);
1525
1526         if (features & NETIF_F_RXCSUM)
1527                 tp->cp_cmd |= RxChkSum;
1528         else
1529                 tp->cp_cmd &= ~RxChkSum;
1530
1531         if (features & NETIF_F_HW_VLAN_CTAG_RX)
1532                 tp->cp_cmd |= RxVlan;
1533         else
1534                 tp->cp_cmd &= ~RxVlan;
1535
1536         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1537         RTL_R16(tp, CPlusCmd);
1538
1539         rtl_unlock_work(tp);
1540
1541         return 0;
1542 }
1543
1544 static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb)
1545 {
1546         return (skb_vlan_tag_present(skb)) ?
1547                 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00;
1548 }
1549
1550 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1551 {
1552         u32 opts2 = le32_to_cpu(desc->opts2);
1553
1554         if (opts2 & RxVlanTag)
1555                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff));
1556 }
1557
1558 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1559                              void *p)
1560 {
1561         struct rtl8169_private *tp = netdev_priv(dev);
1562         u32 __iomem *data = tp->mmio_addr;
1563         u32 *dw = p;
1564         int i;
1565
1566         rtl_lock_work(tp);
1567         for (i = 0; i < R8169_REGS_SIZE; i += 4)
1568                 memcpy_fromio(dw++, data++, 4);
1569         rtl_unlock_work(tp);
1570 }
1571
1572 static u32 rtl8169_get_msglevel(struct net_device *dev)
1573 {
1574         struct rtl8169_private *tp = netdev_priv(dev);
1575
1576         return tp->msg_enable;
1577 }
1578
1579 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1580 {
1581         struct rtl8169_private *tp = netdev_priv(dev);
1582
1583         tp->msg_enable = value;
1584 }
1585
1586 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1587         "tx_packets",
1588         "rx_packets",
1589         "tx_errors",
1590         "rx_errors",
1591         "rx_missed",
1592         "align_errors",
1593         "tx_single_collisions",
1594         "tx_multi_collisions",
1595         "unicast",
1596         "broadcast",
1597         "multicast",
1598         "tx_aborted",
1599         "tx_underrun",
1600 };
1601
1602 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1603 {
1604         switch (sset) {
1605         case ETH_SS_STATS:
1606                 return ARRAY_SIZE(rtl8169_gstrings);
1607         default:
1608                 return -EOPNOTSUPP;
1609         }
1610 }
1611
1612 DECLARE_RTL_COND(rtl_counters_cond)
1613 {
1614         return RTL_R32(tp, CounterAddrLow) & (CounterReset | CounterDump);
1615 }
1616
1617 static bool rtl8169_do_counters(struct rtl8169_private *tp, u32 counter_cmd)
1618 {
1619         dma_addr_t paddr = tp->counters_phys_addr;
1620         u32 cmd;
1621
1622         RTL_W32(tp, CounterAddrHigh, (u64)paddr >> 32);
1623         RTL_R32(tp, CounterAddrHigh);
1624         cmd = (u64)paddr & DMA_BIT_MASK(32);
1625         RTL_W32(tp, CounterAddrLow, cmd);
1626         RTL_W32(tp, CounterAddrLow, cmd | counter_cmd);
1627
1628         return rtl_udelay_loop_wait_low(tp, &rtl_counters_cond, 10, 1000);
1629 }
1630
1631 static bool rtl8169_reset_counters(struct rtl8169_private *tp)
1632 {
1633         /*
1634          * Versions prior to RTL_GIGA_MAC_VER_19 don't support resetting the
1635          * tally counters.
1636          */
1637         if (tp->mac_version < RTL_GIGA_MAC_VER_19)
1638                 return true;
1639
1640         return rtl8169_do_counters(tp, CounterReset);
1641 }
1642
1643 static bool rtl8169_update_counters(struct rtl8169_private *tp)
1644 {
1645         u8 val = RTL_R8(tp, ChipCmd);
1646
1647         /*
1648          * Some chips are unable to dump tally counters when the receiver
1649          * is disabled. If 0xff chip may be in a PCI power-save state.
1650          */
1651         if (!(val & CmdRxEnb) || val == 0xff)
1652                 return true;
1653
1654         return rtl8169_do_counters(tp, CounterDump);
1655 }
1656
1657 static bool rtl8169_init_counter_offsets(struct rtl8169_private *tp)
1658 {
1659         struct rtl8169_counters *counters = tp->counters;
1660         bool ret = false;
1661
1662         /*
1663          * rtl8169_init_counter_offsets is called from rtl_open.  On chip
1664          * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only
1665          * reset by a power cycle, while the counter values collected by the
1666          * driver are reset at every driver unload/load cycle.
1667          *
1668          * To make sure the HW values returned by @get_stats64 match the SW
1669          * values, we collect the initial values at first open(*) and use them
1670          * as offsets to normalize the values returned by @get_stats64.
1671          *
1672          * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one
1673          * for the reason stated in rtl8169_update_counters; CmdRxEnb is only
1674          * set at open time by rtl_hw_start.
1675          */
1676
1677         if (tp->tc_offset.inited)
1678                 return true;
1679
1680         /* If both, reset and update fail, propagate to caller. */
1681         if (rtl8169_reset_counters(tp))
1682                 ret = true;
1683
1684         if (rtl8169_update_counters(tp))
1685                 ret = true;
1686
1687         tp->tc_offset.tx_errors = counters->tx_errors;
1688         tp->tc_offset.tx_multi_collision = counters->tx_multi_collision;
1689         tp->tc_offset.tx_aborted = counters->tx_aborted;
1690         tp->tc_offset.inited = true;
1691
1692         return ret;
1693 }
1694
1695 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1696                                       struct ethtool_stats *stats, u64 *data)
1697 {
1698         struct rtl8169_private *tp = netdev_priv(dev);
1699         struct device *d = tp_to_dev(tp);
1700         struct rtl8169_counters *counters = tp->counters;
1701
1702         ASSERT_RTNL();
1703
1704         pm_runtime_get_noresume(d);
1705
1706         if (pm_runtime_active(d))
1707                 rtl8169_update_counters(tp);
1708
1709         pm_runtime_put_noidle(d);
1710
1711         data[0] = le64_to_cpu(counters->tx_packets);
1712         data[1] = le64_to_cpu(counters->rx_packets);
1713         data[2] = le64_to_cpu(counters->tx_errors);
1714         data[3] = le32_to_cpu(counters->rx_errors);
1715         data[4] = le16_to_cpu(counters->rx_missed);
1716         data[5] = le16_to_cpu(counters->align_errors);
1717         data[6] = le32_to_cpu(counters->tx_one_collision);
1718         data[7] = le32_to_cpu(counters->tx_multi_collision);
1719         data[8] = le64_to_cpu(counters->rx_unicast);
1720         data[9] = le64_to_cpu(counters->rx_broadcast);
1721         data[10] = le32_to_cpu(counters->rx_multicast);
1722         data[11] = le16_to_cpu(counters->tx_aborted);
1723         data[12] = le16_to_cpu(counters->tx_underun);
1724 }
1725
1726 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1727 {
1728         switch(stringset) {
1729         case ETH_SS_STATS:
1730                 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1731                 break;
1732         }
1733 }
1734
1735 /*
1736  * Interrupt coalescing
1737  *
1738  * > 1 - the availability of the IntrMitigate (0xe2) register through the
1739  * >     8169, 8168 and 810x line of chipsets
1740  *
1741  * 8169, 8168, and 8136(810x) serial chipsets support it.
1742  *
1743  * > 2 - the Tx timer unit at gigabit speed
1744  *
1745  * The unit of the timer depends on both the speed and the setting of CPlusCmd
1746  * (0xe0) bit 1 and bit 0.
1747  *
1748  * For 8169
1749  * bit[1:0] \ speed        1000M           100M            10M
1750  * 0 0                     320ns           2.56us          40.96us
1751  * 0 1                     2.56us          20.48us         327.7us
1752  * 1 0                     5.12us          40.96us         655.4us
1753  * 1 1                     10.24us         81.92us         1.31ms
1754  *
1755  * For the other
1756  * bit[1:0] \ speed        1000M           100M            10M
1757  * 0 0                     5us             2.56us          40.96us
1758  * 0 1                     40us            20.48us         327.7us
1759  * 1 0                     80us            40.96us         655.4us
1760  * 1 1                     160us           81.92us         1.31ms
1761  */
1762
1763 /* rx/tx scale factors for one particular CPlusCmd[0:1] value */
1764 struct rtl_coalesce_scale {
1765         /* Rx / Tx */
1766         u32 nsecs[2];
1767 };
1768
1769 /* rx/tx scale factors for all CPlusCmd[0:1] cases */
1770 struct rtl_coalesce_info {
1771         u32 speed;
1772         struct rtl_coalesce_scale scalev[4];    /* each CPlusCmd[0:1] case */
1773 };
1774
1775 /* produce (r,t) pairs with each being in series of *1, *8, *8*2, *8*2*2 */
1776 #define rxtx_x1822(r, t) {              \
1777         {{(r),          (t)}},          \
1778         {{(r)*8,        (t)*8}},        \
1779         {{(r)*8*2,      (t)*8*2}},      \
1780         {{(r)*8*2*2,    (t)*8*2*2}},    \
1781 }
1782 static const struct rtl_coalesce_info rtl_coalesce_info_8169[] = {
1783         /* speed        delays:     rx00   tx00 */
1784         { SPEED_10,     rxtx_x1822(40960, 40960)        },
1785         { SPEED_100,    rxtx_x1822( 2560,  2560)        },
1786         { SPEED_1000,   rxtx_x1822(  320,   320)        },
1787         { 0 },
1788 };
1789
1790 static const struct rtl_coalesce_info rtl_coalesce_info_8168_8136[] = {
1791         /* speed        delays:     rx00   tx00 */
1792         { SPEED_10,     rxtx_x1822(40960, 40960)        },
1793         { SPEED_100,    rxtx_x1822( 2560,  2560)        },
1794         { SPEED_1000,   rxtx_x1822( 5000,  5000)        },
1795         { 0 },
1796 };
1797 #undef rxtx_x1822
1798
1799 /* get rx/tx scale vector corresponding to current speed */
1800 static const struct rtl_coalesce_info *rtl_coalesce_info(struct net_device *dev)
1801 {
1802         struct rtl8169_private *tp = netdev_priv(dev);
1803         const struct rtl_coalesce_info *ci;
1804
1805         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
1806                 ci = rtl_coalesce_info_8169;
1807         else
1808                 ci = rtl_coalesce_info_8168_8136;
1809
1810         for (; ci->speed; ci++) {
1811                 if (tp->phydev->speed == ci->speed)
1812                         return ci;
1813         }
1814
1815         return ERR_PTR(-ELNRNG);
1816 }
1817
1818 static int rtl_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1819 {
1820         struct rtl8169_private *tp = netdev_priv(dev);
1821         const struct rtl_coalesce_info *ci;
1822         const struct rtl_coalesce_scale *scale;
1823         struct {
1824                 u32 *max_frames;
1825                 u32 *usecs;
1826         } coal_settings [] = {
1827                 { &ec->rx_max_coalesced_frames, &ec->rx_coalesce_usecs },
1828                 { &ec->tx_max_coalesced_frames, &ec->tx_coalesce_usecs }
1829         }, *p = coal_settings;
1830         int i;
1831         u16 w;
1832
1833         memset(ec, 0, sizeof(*ec));
1834
1835         /* get rx/tx scale corresponding to current speed and CPlusCmd[0:1] */
1836         ci = rtl_coalesce_info(dev);
1837         if (IS_ERR(ci))
1838                 return PTR_ERR(ci);
1839
1840         scale = &ci->scalev[tp->cp_cmd & INTT_MASK];
1841
1842         /* read IntrMitigate and adjust according to scale */
1843         for (w = RTL_R16(tp, IntrMitigate); w; w >>= RTL_COALESCE_SHIFT, p++) {
1844                 *p->max_frames = (w & RTL_COALESCE_MASK) << 2;
1845                 w >>= RTL_COALESCE_SHIFT;
1846                 *p->usecs = w & RTL_COALESCE_MASK;
1847         }
1848
1849         for (i = 0; i < 2; i++) {
1850                 p = coal_settings + i;
1851                 *p->usecs = (*p->usecs * scale->nsecs[i]) / 1000;
1852
1853                 /*
1854                  * ethtool_coalesce says it is illegal to set both usecs and
1855                  * max_frames to 0.
1856                  */
1857                 if (!*p->usecs && !*p->max_frames)
1858                         *p->max_frames = 1;
1859         }
1860
1861         return 0;
1862 }
1863
1864 /* choose appropriate scale factor and CPlusCmd[0:1] for (speed, nsec) */
1865 static const struct rtl_coalesce_scale *rtl_coalesce_choose_scale(
1866                         struct net_device *dev, u32 nsec, u16 *cp01)
1867 {
1868         const struct rtl_coalesce_info *ci;
1869         u16 i;
1870
1871         ci = rtl_coalesce_info(dev);
1872         if (IS_ERR(ci))
1873                 return ERR_CAST(ci);
1874
1875         for (i = 0; i < 4; i++) {
1876                 u32 rxtx_maxscale = max(ci->scalev[i].nsecs[0],
1877                                         ci->scalev[i].nsecs[1]);
1878                 if (nsec <= rxtx_maxscale * RTL_COALESCE_T_MAX) {
1879                         *cp01 = i;
1880                         return &ci->scalev[i];
1881                 }
1882         }
1883
1884         return ERR_PTR(-EINVAL);
1885 }
1886
1887 static int rtl_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1888 {
1889         struct rtl8169_private *tp = netdev_priv(dev);
1890         const struct rtl_coalesce_scale *scale;
1891         struct {
1892                 u32 frames;
1893                 u32 usecs;
1894         } coal_settings [] = {
1895                 { ec->rx_max_coalesced_frames, ec->rx_coalesce_usecs },
1896                 { ec->tx_max_coalesced_frames, ec->tx_coalesce_usecs }
1897         }, *p = coal_settings;
1898         u16 w = 0, cp01;
1899         int i;
1900
1901         scale = rtl_coalesce_choose_scale(dev,
1902                         max(p[0].usecs, p[1].usecs) * 1000, &cp01);
1903         if (IS_ERR(scale))
1904                 return PTR_ERR(scale);
1905
1906         for (i = 0; i < 2; i++, p++) {
1907                 u32 units;
1908
1909                 /*
1910                  * accept max_frames=1 we returned in rtl_get_coalesce.
1911                  * accept it not only when usecs=0 because of e.g. the following scenario:
1912                  *
1913                  * - both rx_usecs=0 & rx_frames=0 in hardware (no delay on RX)
1914                  * - rtl_get_coalesce returns rx_usecs=0, rx_frames=1
1915                  * - then user does `ethtool -C eth0 rx-usecs 100`
1916                  *
1917                  * since ethtool sends to kernel whole ethtool_coalesce
1918                  * settings, if we do not handle rx_usecs=!0, rx_frames=1
1919                  * we'll reject it below in `frames % 4 != 0`.
1920                  */
1921                 if (p->frames == 1) {
1922                         p->frames = 0;
1923                 }
1924
1925                 units = p->usecs * 1000 / scale->nsecs[i];
1926                 if (p->frames > RTL_COALESCE_FRAME_MAX || p->frames % 4)
1927                         return -EINVAL;
1928
1929                 w <<= RTL_COALESCE_SHIFT;
1930                 w |= units;
1931                 w <<= RTL_COALESCE_SHIFT;
1932                 w |= p->frames >> 2;
1933         }
1934
1935         rtl_lock_work(tp);
1936
1937         RTL_W16(tp, IntrMitigate, swab16(w));
1938
1939         tp->cp_cmd = (tp->cp_cmd & ~INTT_MASK) | cp01;
1940         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1941         RTL_R16(tp, CPlusCmd);
1942
1943         rtl_unlock_work(tp);
1944
1945         return 0;
1946 }
1947
1948 static int rtl_get_eee_supp(struct rtl8169_private *tp)
1949 {
1950         struct phy_device *phydev = tp->phydev;
1951         int ret;
1952
1953         switch (tp->mac_version) {
1954         case RTL_GIGA_MAC_VER_34:
1955         case RTL_GIGA_MAC_VER_35:
1956         case RTL_GIGA_MAC_VER_36:
1957         case RTL_GIGA_MAC_VER_38:
1958                 ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE);
1959                 break;
1960         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
1961                 ret = phy_read_paged(phydev, 0x0a5c, 0x12);
1962                 break;
1963         default:
1964                 ret = -EPROTONOSUPPORT;
1965                 break;
1966         }
1967
1968         return ret;
1969 }
1970
1971 static int rtl_get_eee_lpadv(struct rtl8169_private *tp)
1972 {
1973         struct phy_device *phydev = tp->phydev;
1974         int ret;
1975
1976         switch (tp->mac_version) {
1977         case RTL_GIGA_MAC_VER_34:
1978         case RTL_GIGA_MAC_VER_35:
1979         case RTL_GIGA_MAC_VER_36:
1980         case RTL_GIGA_MAC_VER_38:
1981                 ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE);
1982                 break;
1983         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
1984                 ret = phy_read_paged(phydev, 0x0a5d, 0x11);
1985                 break;
1986         default:
1987                 ret = -EPROTONOSUPPORT;
1988                 break;
1989         }
1990
1991         return ret;
1992 }
1993
1994 static int rtl_get_eee_adv(struct rtl8169_private *tp)
1995 {
1996         struct phy_device *phydev = tp->phydev;
1997         int ret;
1998
1999         switch (tp->mac_version) {
2000         case RTL_GIGA_MAC_VER_34:
2001         case RTL_GIGA_MAC_VER_35:
2002         case RTL_GIGA_MAC_VER_36:
2003         case RTL_GIGA_MAC_VER_38:
2004                 ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV);
2005                 break;
2006         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
2007                 ret = phy_read_paged(phydev, 0x0a5d, 0x10);
2008                 break;
2009         default:
2010                 ret = -EPROTONOSUPPORT;
2011                 break;
2012         }
2013
2014         return ret;
2015 }
2016
2017 static int rtl_set_eee_adv(struct rtl8169_private *tp, int val)
2018 {
2019         struct phy_device *phydev = tp->phydev;
2020         int ret = 0;
2021
2022         switch (tp->mac_version) {
2023         case RTL_GIGA_MAC_VER_34:
2024         case RTL_GIGA_MAC_VER_35:
2025         case RTL_GIGA_MAC_VER_36:
2026         case RTL_GIGA_MAC_VER_38:
2027                 ret = phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);
2028                 break;
2029         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
2030                 phy_write_paged(phydev, 0x0a5d, 0x10, val);
2031                 break;
2032         default:
2033                 ret = -EPROTONOSUPPORT;
2034                 break;
2035         }
2036
2037         return ret;
2038 }
2039
2040 static int rtl8169_get_eee(struct net_device *dev, struct ethtool_eee *data)
2041 {
2042         struct rtl8169_private *tp = netdev_priv(dev);
2043         struct device *d = tp_to_dev(tp);
2044         int ret;
2045
2046         pm_runtime_get_noresume(d);
2047
2048         if (!pm_runtime_active(d)) {
2049                 ret = -EOPNOTSUPP;
2050                 goto out;
2051         }
2052
2053         /* Get Supported EEE */
2054         ret = rtl_get_eee_supp(tp);
2055         if (ret < 0)
2056                 goto out;
2057         data->supported = mmd_eee_cap_to_ethtool_sup_t(ret);
2058
2059         /* Get advertisement EEE */
2060         ret = rtl_get_eee_adv(tp);
2061         if (ret < 0)
2062                 goto out;
2063         data->advertised = mmd_eee_adv_to_ethtool_adv_t(ret);
2064         data->eee_enabled = !!data->advertised;
2065
2066         /* Get LP advertisement EEE */
2067         ret = rtl_get_eee_lpadv(tp);
2068         if (ret < 0)
2069                 goto out;
2070         data->lp_advertised = mmd_eee_adv_to_ethtool_adv_t(ret);
2071         data->eee_active = !!(data->advertised & data->lp_advertised);
2072 out:
2073         pm_runtime_put_noidle(d);
2074         return ret < 0 ? ret : 0;
2075 }
2076
2077 static int rtl8169_set_eee(struct net_device *dev, struct ethtool_eee *data)
2078 {
2079         struct rtl8169_private *tp = netdev_priv(dev);
2080         struct device *d = tp_to_dev(tp);
2081         int old_adv, adv = 0, cap, ret;
2082
2083         pm_runtime_get_noresume(d);
2084
2085         if (!dev->phydev || !pm_runtime_active(d)) {
2086                 ret = -EOPNOTSUPP;
2087                 goto out;
2088         }
2089
2090         if (dev->phydev->autoneg == AUTONEG_DISABLE ||
2091             dev->phydev->duplex != DUPLEX_FULL) {
2092                 ret = -EPROTONOSUPPORT;
2093                 goto out;
2094         }
2095
2096         /* Get Supported EEE */
2097         ret = rtl_get_eee_supp(tp);
2098         if (ret < 0)
2099                 goto out;
2100         cap = ret;
2101
2102         ret = rtl_get_eee_adv(tp);
2103         if (ret < 0)
2104                 goto out;
2105         old_adv = ret;
2106
2107         if (data->eee_enabled) {
2108                 adv = !data->advertised ? cap :
2109                       ethtool_adv_to_mmd_eee_adv_t(data->advertised) & cap;
2110                 /* Mask prohibited EEE modes */
2111                 adv &= ~dev->phydev->eee_broken_modes;
2112         }
2113
2114         if (old_adv != adv) {
2115                 ret = rtl_set_eee_adv(tp, adv);
2116                 if (ret < 0)
2117                         goto out;
2118
2119                 /* Restart autonegotiation so the new modes get sent to the
2120                  * link partner.
2121                  */
2122                 ret = phy_restart_aneg(dev->phydev);
2123         }
2124
2125 out:
2126         pm_runtime_put_noidle(d);
2127         return ret < 0 ? ret : 0;
2128 }
2129
2130 static const struct ethtool_ops rtl8169_ethtool_ops = {
2131         .get_drvinfo            = rtl8169_get_drvinfo,
2132         .get_regs_len           = rtl8169_get_regs_len,
2133         .get_link               = ethtool_op_get_link,
2134         .get_coalesce           = rtl_get_coalesce,
2135         .set_coalesce           = rtl_set_coalesce,
2136         .get_msglevel           = rtl8169_get_msglevel,
2137         .set_msglevel           = rtl8169_set_msglevel,
2138         .get_regs               = rtl8169_get_regs,
2139         .get_wol                = rtl8169_get_wol,
2140         .set_wol                = rtl8169_set_wol,
2141         .get_strings            = rtl8169_get_strings,
2142         .get_sset_count         = rtl8169_get_sset_count,
2143         .get_ethtool_stats      = rtl8169_get_ethtool_stats,
2144         .get_ts_info            = ethtool_op_get_ts_info,
2145         .nway_reset             = phy_ethtool_nway_reset,
2146         .get_eee                = rtl8169_get_eee,
2147         .set_eee                = rtl8169_set_eee,
2148         .get_link_ksettings     = phy_ethtool_get_link_ksettings,
2149         .set_link_ksettings     = phy_ethtool_set_link_ksettings,
2150 };
2151
2152 static void rtl_enable_eee(struct rtl8169_private *tp)
2153 {
2154         int supported = rtl_get_eee_supp(tp);
2155
2156         if (supported > 0)
2157                 rtl_set_eee_adv(tp, supported);
2158 }
2159
2160 static void rtl8169_get_mac_version(struct rtl8169_private *tp)
2161 {
2162         /*
2163          * The driver currently handles the 8168Bf and the 8168Be identically
2164          * but they can be identified more specifically through the test below
2165          * if needed:
2166          *
2167          * (RTL_R32(tp, TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
2168          *
2169          * Same thing for the 8101Eb and the 8101Ec:
2170          *
2171          * (RTL_R32(tp, TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
2172          */
2173         static const struct rtl_mac_info {
2174                 u16 mask;
2175                 u16 val;
2176                 u16 mac_version;
2177         } mac_info[] = {
2178                 /* 8168EP family. */
2179                 { 0x7cf, 0x502, RTL_GIGA_MAC_VER_51 },
2180                 { 0x7cf, 0x501, RTL_GIGA_MAC_VER_50 },
2181                 { 0x7cf, 0x500, RTL_GIGA_MAC_VER_49 },
2182
2183                 /* 8168H family. */
2184                 { 0x7cf, 0x541, RTL_GIGA_MAC_VER_46 },
2185                 { 0x7cf, 0x540, RTL_GIGA_MAC_VER_45 },
2186
2187                 /* 8168G family. */
2188                 { 0x7cf, 0x5c8, RTL_GIGA_MAC_VER_44 },
2189                 { 0x7cf, 0x509, RTL_GIGA_MAC_VER_42 },
2190                 { 0x7cf, 0x4c1, RTL_GIGA_MAC_VER_41 },
2191                 { 0x7cf, 0x4c0, RTL_GIGA_MAC_VER_40 },
2192
2193                 /* 8168F family. */
2194                 { 0x7c8, 0x488, RTL_GIGA_MAC_VER_38 },
2195                 { 0x7cf, 0x481, RTL_GIGA_MAC_VER_36 },
2196                 { 0x7cf, 0x480, RTL_GIGA_MAC_VER_35 },
2197
2198                 /* 8168E family. */
2199                 { 0x7c8, 0x2c8, RTL_GIGA_MAC_VER_34 },
2200                 { 0x7cf, 0x2c1, RTL_GIGA_MAC_VER_32 },
2201                 { 0x7c8, 0x2c0, RTL_GIGA_MAC_VER_33 },
2202
2203                 /* 8168D family. */
2204                 { 0x7cf, 0x281, RTL_GIGA_MAC_VER_25 },
2205                 { 0x7c8, 0x280, RTL_GIGA_MAC_VER_26 },
2206
2207                 /* 8168DP family. */
2208                 { 0x7cf, 0x288, RTL_GIGA_MAC_VER_27 },
2209                 { 0x7cf, 0x28a, RTL_GIGA_MAC_VER_28 },
2210                 { 0x7cf, 0x28b, RTL_GIGA_MAC_VER_31 },
2211
2212                 /* 8168C family. */
2213                 { 0x7cf, 0x3c9, RTL_GIGA_MAC_VER_23 },
2214                 { 0x7cf, 0x3c8, RTL_GIGA_MAC_VER_18 },
2215                 { 0x7c8, 0x3c8, RTL_GIGA_MAC_VER_24 },
2216                 { 0x7cf, 0x3c0, RTL_GIGA_MAC_VER_19 },
2217                 { 0x7cf, 0x3c2, RTL_GIGA_MAC_VER_20 },
2218                 { 0x7cf, 0x3c3, RTL_GIGA_MAC_VER_21 },
2219                 { 0x7c8, 0x3c0, RTL_GIGA_MAC_VER_22 },
2220
2221                 /* 8168B family. */
2222                 { 0x7cf, 0x380, RTL_GIGA_MAC_VER_12 },
2223                 { 0x7c8, 0x380, RTL_GIGA_MAC_VER_17 },
2224                 { 0x7c8, 0x300, RTL_GIGA_MAC_VER_11 },
2225
2226                 /* 8101 family. */
2227                 { 0x7c8, 0x448, RTL_GIGA_MAC_VER_39 },
2228                 { 0x7c8, 0x440, RTL_GIGA_MAC_VER_37 },
2229                 { 0x7cf, 0x409, RTL_GIGA_MAC_VER_29 },
2230                 { 0x7c8, 0x408, RTL_GIGA_MAC_VER_30 },
2231                 { 0x7cf, 0x349, RTL_GIGA_MAC_VER_08 },
2232                 { 0x7cf, 0x249, RTL_GIGA_MAC_VER_08 },
2233                 { 0x7cf, 0x348, RTL_GIGA_MAC_VER_07 },
2234                 { 0x7cf, 0x248, RTL_GIGA_MAC_VER_07 },
2235                 { 0x7cf, 0x340, RTL_GIGA_MAC_VER_13 },
2236                 { 0x7cf, 0x343, RTL_GIGA_MAC_VER_10 },
2237                 { 0x7cf, 0x342, RTL_GIGA_MAC_VER_16 },
2238                 { 0x7c8, 0x348, RTL_GIGA_MAC_VER_09 },
2239                 { 0x7c8, 0x248, RTL_GIGA_MAC_VER_09 },
2240                 { 0x7c8, 0x340, RTL_GIGA_MAC_VER_16 },
2241                 /* FIXME: where did these entries come from ? -- FR */
2242                 { 0xfc8, 0x388, RTL_GIGA_MAC_VER_15 },
2243                 { 0xfc8, 0x308, RTL_GIGA_MAC_VER_14 },
2244
2245                 /* 8110 family. */
2246                 { 0xfc8, 0x980, RTL_GIGA_MAC_VER_06 },
2247                 { 0xfc8, 0x180, RTL_GIGA_MAC_VER_05 },
2248                 { 0xfc8, 0x100, RTL_GIGA_MAC_VER_04 },
2249                 { 0xfc8, 0x040, RTL_GIGA_MAC_VER_03 },
2250                 { 0xfc8, 0x008, RTL_GIGA_MAC_VER_02 },
2251
2252                 /* Catch-all */
2253                 { 0x000, 0x000, RTL_GIGA_MAC_NONE   }
2254         };
2255         const struct rtl_mac_info *p = mac_info;
2256         u16 reg = RTL_R32(tp, TxConfig) >> 20;
2257
2258         while ((reg & p->mask) != p->val)
2259                 p++;
2260         tp->mac_version = p->mac_version;
2261
2262         if (tp->mac_version == RTL_GIGA_MAC_NONE) {
2263                 dev_err(tp_to_dev(tp), "unknown chip XID %03x\n", reg & 0xfcf);
2264         } else if (!tp->supports_gmii) {
2265                 if (tp->mac_version == RTL_GIGA_MAC_VER_42)
2266                         tp->mac_version = RTL_GIGA_MAC_VER_43;
2267                 else if (tp->mac_version == RTL_GIGA_MAC_VER_45)
2268                         tp->mac_version = RTL_GIGA_MAC_VER_47;
2269                 else if (tp->mac_version == RTL_GIGA_MAC_VER_46)
2270                         tp->mac_version = RTL_GIGA_MAC_VER_48;
2271         }
2272 }
2273
2274 struct phy_reg {
2275         u16 reg;
2276         u16 val;
2277 };
2278
2279 static void __rtl_writephy_batch(struct rtl8169_private *tp,
2280                                  const struct phy_reg *regs, int len)
2281 {
2282         while (len-- > 0) {
2283                 rtl_writephy(tp, regs->reg, regs->val);
2284                 regs++;
2285         }
2286 }
2287
2288 #define rtl_writephy_batch(tp, a) __rtl_writephy_batch(tp, a, ARRAY_SIZE(a))
2289
2290 static void rtl_release_firmware(struct rtl8169_private *tp)
2291 {
2292         if (tp->rtl_fw) {
2293                 rtl_fw_release_firmware(tp->rtl_fw);
2294                 kfree(tp->rtl_fw);
2295                 tp->rtl_fw = NULL;
2296         }
2297 }
2298
2299 static void rtl_apply_firmware(struct rtl8169_private *tp)
2300 {
2301         /* TODO: release firmware if rtl_fw_write_firmware signals failure. */
2302         if (tp->rtl_fw)
2303                 rtl_fw_write_firmware(tp, tp->rtl_fw);
2304 }
2305
2306 static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
2307 {
2308         if (rtl_readphy(tp, reg) != val)
2309                 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
2310         else
2311                 rtl_apply_firmware(tp);
2312 }
2313
2314 static void rtl8168_config_eee_mac(struct rtl8169_private *tp)
2315 {
2316         /* Adjust EEE LED frequency */
2317         if (tp->mac_version != RTL_GIGA_MAC_VER_38)
2318                 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
2319
2320         rtl_eri_set_bits(tp, 0x1b0, ERIAR_MASK_1111, 0x0003);
2321 }
2322
2323 static void rtl8168f_config_eee_phy(struct rtl8169_private *tp)
2324 {
2325         struct phy_device *phydev = tp->phydev;
2326
2327         phy_write(phydev, 0x1f, 0x0007);
2328         phy_write(phydev, 0x1e, 0x0020);
2329         phy_set_bits(phydev, 0x15, BIT(8));
2330
2331         phy_write(phydev, 0x1f, 0x0005);
2332         phy_write(phydev, 0x05, 0x8b85);
2333         phy_set_bits(phydev, 0x06, BIT(13));
2334
2335         phy_write(phydev, 0x1f, 0x0000);
2336 }
2337
2338 static void rtl8168g_config_eee_phy(struct rtl8169_private *tp)
2339 {
2340         phy_modify_paged(tp->phydev, 0x0a43, 0x11, 0, BIT(4));
2341 }
2342
2343 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
2344 {
2345         static const struct phy_reg phy_reg_init[] = {
2346                 { 0x1f, 0x0001 },
2347                 { 0x06, 0x006e },
2348                 { 0x08, 0x0708 },
2349                 { 0x15, 0x4000 },
2350                 { 0x18, 0x65c7 },
2351
2352                 { 0x1f, 0x0001 },
2353                 { 0x03, 0x00a1 },
2354                 { 0x02, 0x0008 },
2355                 { 0x01, 0x0120 },
2356                 { 0x00, 0x1000 },
2357                 { 0x04, 0x0800 },
2358                 { 0x04, 0x0000 },
2359
2360                 { 0x03, 0xff41 },
2361                 { 0x02, 0xdf60 },
2362                 { 0x01, 0x0140 },
2363                 { 0x00, 0x0077 },
2364                 { 0x04, 0x7800 },
2365                 { 0x04, 0x7000 },
2366
2367                 { 0x03, 0x802f },
2368                 { 0x02, 0x4f02 },
2369                 { 0x01, 0x0409 },
2370                 { 0x00, 0xf0f9 },
2371                 { 0x04, 0x9800 },
2372                 { 0x04, 0x9000 },
2373
2374                 { 0x03, 0xdf01 },
2375                 { 0x02, 0xdf20 },
2376                 { 0x01, 0xff95 },
2377                 { 0x00, 0xba00 },
2378                 { 0x04, 0xa800 },
2379                 { 0x04, 0xa000 },
2380
2381                 { 0x03, 0xff41 },
2382                 { 0x02, 0xdf20 },
2383                 { 0x01, 0x0140 },
2384                 { 0x00, 0x00bb },
2385                 { 0x04, 0xb800 },
2386                 { 0x04, 0xb000 },
2387
2388                 { 0x03, 0xdf41 },
2389                 { 0x02, 0xdc60 },
2390                 { 0x01, 0x6340 },
2391                 { 0x00, 0x007d },
2392                 { 0x04, 0xd800 },
2393                 { 0x04, 0xd000 },
2394
2395                 { 0x03, 0xdf01 },
2396                 { 0x02, 0xdf20 },
2397                 { 0x01, 0x100a },
2398                 { 0x00, 0xa0ff },
2399                 { 0x04, 0xf800 },
2400                 { 0x04, 0xf000 },
2401
2402                 { 0x1f, 0x0000 },
2403                 { 0x0b, 0x0000 },
2404                 { 0x00, 0x9200 }
2405         };
2406
2407         rtl_writephy_batch(tp, phy_reg_init);
2408 }
2409
2410 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
2411 {
2412         static const struct phy_reg phy_reg_init[] = {
2413                 { 0x1f, 0x0002 },
2414                 { 0x01, 0x90d0 },
2415                 { 0x1f, 0x0000 }
2416         };
2417
2418         rtl_writephy_batch(tp, phy_reg_init);
2419 }
2420
2421 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2422 {
2423         struct pci_dev *pdev = tp->pci_dev;
2424
2425         if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
2426             (pdev->subsystem_device != 0xe000))
2427                 return;
2428
2429         rtl_writephy(tp, 0x1f, 0x0001);
2430         rtl_writephy(tp, 0x10, 0xf01b);
2431         rtl_writephy(tp, 0x1f, 0x0000);
2432 }
2433
2434 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2435 {
2436         static const struct phy_reg phy_reg_init[] = {
2437                 { 0x1f, 0x0001 },
2438                 { 0x04, 0x0000 },
2439                 { 0x03, 0x00a1 },
2440                 { 0x02, 0x0008 },
2441                 { 0x01, 0x0120 },
2442                 { 0x00, 0x1000 },
2443                 { 0x04, 0x0800 },
2444                 { 0x04, 0x9000 },
2445                 { 0x03, 0x802f },
2446                 { 0x02, 0x4f02 },
2447                 { 0x01, 0x0409 },
2448                 { 0x00, 0xf099 },
2449                 { 0x04, 0x9800 },
2450                 { 0x04, 0xa000 },
2451                 { 0x03, 0xdf01 },
2452                 { 0x02, 0xdf20 },
2453                 { 0x01, 0xff95 },
2454                 { 0x00, 0xba00 },
2455                 { 0x04, 0xa800 },
2456                 { 0x04, 0xf000 },
2457                 { 0x03, 0xdf01 },
2458                 { 0x02, 0xdf20 },
2459                 { 0x01, 0x101a },
2460                 { 0x00, 0xa0ff },
2461                 { 0x04, 0xf800 },
2462                 { 0x04, 0x0000 },
2463                 { 0x1f, 0x0000 },
2464
2465                 { 0x1f, 0x0001 },
2466                 { 0x10, 0xf41b },
2467                 { 0x14, 0xfb54 },
2468                 { 0x18, 0xf5c7 },
2469                 { 0x1f, 0x0000 },
2470
2471                 { 0x1f, 0x0001 },
2472                 { 0x17, 0x0cc0 },
2473                 { 0x1f, 0x0000 }
2474         };
2475
2476         rtl_writephy_batch(tp, phy_reg_init);
2477
2478         rtl8169scd_hw_phy_config_quirk(tp);
2479 }
2480
2481 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
2482 {
2483         static const struct phy_reg phy_reg_init[] = {
2484                 { 0x1f, 0x0001 },
2485                 { 0x04, 0x0000 },
2486                 { 0x03, 0x00a1 },
2487                 { 0x02, 0x0008 },
2488                 { 0x01, 0x0120 },
2489                 { 0x00, 0x1000 },
2490                 { 0x04, 0x0800 },
2491                 { 0x04, 0x9000 },
2492                 { 0x03, 0x802f },
2493                 { 0x02, 0x4f02 },
2494                 { 0x01, 0x0409 },
2495                 { 0x00, 0xf099 },
2496                 { 0x04, 0x9800 },
2497                 { 0x04, 0xa000 },
2498                 { 0x03, 0xdf01 },
2499                 { 0x02, 0xdf20 },
2500                 { 0x01, 0xff95 },
2501                 { 0x00, 0xba00 },
2502                 { 0x04, 0xa800 },
2503                 { 0x04, 0xf000 },
2504                 { 0x03, 0xdf01 },
2505                 { 0x02, 0xdf20 },
2506                 { 0x01, 0x101a },
2507                 { 0x00, 0xa0ff },
2508                 { 0x04, 0xf800 },
2509                 { 0x04, 0x0000 },
2510                 { 0x1f, 0x0000 },
2511
2512                 { 0x1f, 0x0001 },
2513                 { 0x0b, 0x8480 },
2514                 { 0x1f, 0x0000 },
2515
2516                 { 0x1f, 0x0001 },
2517                 { 0x18, 0x67c7 },
2518                 { 0x04, 0x2000 },
2519                 { 0x03, 0x002f },
2520                 { 0x02, 0x4360 },
2521                 { 0x01, 0x0109 },
2522                 { 0x00, 0x3022 },
2523                 { 0x04, 0x2800 },
2524                 { 0x1f, 0x0000 },
2525
2526                 { 0x1f, 0x0001 },
2527                 { 0x17, 0x0cc0 },
2528                 { 0x1f, 0x0000 }
2529         };
2530
2531         rtl_writephy_batch(tp, phy_reg_init);
2532 }
2533
2534 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
2535 {
2536         static const struct phy_reg phy_reg_init[] = {
2537                 { 0x10, 0xf41b },
2538                 { 0x1f, 0x0000 }
2539         };
2540
2541         rtl_writephy(tp, 0x1f, 0x0001);
2542         rtl_patchphy(tp, 0x16, 1 << 0);
2543
2544         rtl_writephy_batch(tp, phy_reg_init);
2545 }
2546
2547 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
2548 {
2549         static const struct phy_reg phy_reg_init[] = {
2550                 { 0x1f, 0x0001 },
2551                 { 0x10, 0xf41b },
2552                 { 0x1f, 0x0000 }
2553         };
2554
2555         rtl_writephy_batch(tp, phy_reg_init);
2556 }
2557
2558 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
2559 {
2560         static const struct phy_reg phy_reg_init[] = {
2561                 { 0x1f, 0x0000 },
2562                 { 0x1d, 0x0f00 },
2563                 { 0x1f, 0x0002 },
2564                 { 0x0c, 0x1ec8 },
2565                 { 0x1f, 0x0000 }
2566         };
2567
2568         rtl_writephy_batch(tp, phy_reg_init);
2569 }
2570
2571 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
2572 {
2573         static const struct phy_reg phy_reg_init[] = {
2574                 { 0x1f, 0x0001 },
2575                 { 0x1d, 0x3d98 },
2576                 { 0x1f, 0x0000 }
2577         };
2578
2579         rtl_writephy(tp, 0x1f, 0x0000);
2580         rtl_patchphy(tp, 0x14, 1 << 5);
2581         rtl_patchphy(tp, 0x0d, 1 << 5);
2582
2583         rtl_writephy_batch(tp, phy_reg_init);
2584 }
2585
2586 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
2587 {
2588         static const struct phy_reg phy_reg_init[] = {
2589                 { 0x1f, 0x0001 },
2590                 { 0x12, 0x2300 },
2591                 { 0x1f, 0x0002 },
2592                 { 0x00, 0x88d4 },
2593                 { 0x01, 0x82b1 },
2594                 { 0x03, 0x7002 },
2595                 { 0x08, 0x9e30 },
2596                 { 0x09, 0x01f0 },
2597                 { 0x0a, 0x5500 },
2598                 { 0x0c, 0x00c8 },
2599                 { 0x1f, 0x0003 },
2600                 { 0x12, 0xc096 },
2601                 { 0x16, 0x000a },
2602                 { 0x1f, 0x0000 },
2603                 { 0x1f, 0x0000 },
2604                 { 0x09, 0x2000 },
2605                 { 0x09, 0x0000 }
2606         };
2607
2608         rtl_writephy_batch(tp, phy_reg_init);
2609
2610         rtl_patchphy(tp, 0x14, 1 << 5);
2611         rtl_patchphy(tp, 0x0d, 1 << 5);
2612         rtl_writephy(tp, 0x1f, 0x0000);
2613 }
2614
2615 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
2616 {
2617         static const struct phy_reg phy_reg_init[] = {
2618                 { 0x1f, 0x0001 },
2619                 { 0x12, 0x2300 },
2620                 { 0x03, 0x802f },
2621                 { 0x02, 0x4f02 },
2622                 { 0x01, 0x0409 },
2623                 { 0x00, 0xf099 },
2624                 { 0x04, 0x9800 },
2625                 { 0x04, 0x9000 },
2626                 { 0x1d, 0x3d98 },
2627                 { 0x1f, 0x0002 },
2628                 { 0x0c, 0x7eb8 },
2629                 { 0x06, 0x0761 },
2630                 { 0x1f, 0x0003 },
2631                 { 0x16, 0x0f0a },
2632                 { 0x1f, 0x0000 }
2633         };
2634
2635         rtl_writephy_batch(tp, phy_reg_init);
2636
2637         rtl_patchphy(tp, 0x16, 1 << 0);
2638         rtl_patchphy(tp, 0x14, 1 << 5);
2639         rtl_patchphy(tp, 0x0d, 1 << 5);
2640         rtl_writephy(tp, 0x1f, 0x0000);
2641 }
2642
2643 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
2644 {
2645         static const struct phy_reg phy_reg_init[] = {
2646                 { 0x1f, 0x0001 },
2647                 { 0x12, 0x2300 },
2648                 { 0x1d, 0x3d98 },
2649                 { 0x1f, 0x0002 },
2650                 { 0x0c, 0x7eb8 },
2651                 { 0x06, 0x5461 },
2652                 { 0x1f, 0x0003 },
2653                 { 0x16, 0x0f0a },
2654                 { 0x1f, 0x0000 }
2655         };
2656
2657         rtl_writephy_batch(tp, phy_reg_init);
2658
2659         rtl_patchphy(tp, 0x16, 1 << 0);
2660         rtl_patchphy(tp, 0x14, 1 << 5);
2661         rtl_patchphy(tp, 0x0d, 1 << 5);
2662         rtl_writephy(tp, 0x1f, 0x0000);
2663 }
2664
2665 static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
2666 {
2667         rtl8168c_3_hw_phy_config(tp);
2668 }
2669
2670 static const struct phy_reg rtl8168d_1_phy_reg_init_0[] = {
2671         /* Channel Estimation */
2672         { 0x1f, 0x0001 },
2673         { 0x06, 0x4064 },
2674         { 0x07, 0x2863 },
2675         { 0x08, 0x059c },
2676         { 0x09, 0x26b4 },
2677         { 0x0a, 0x6a19 },
2678         { 0x0b, 0xdcc8 },
2679         { 0x10, 0xf06d },
2680         { 0x14, 0x7f68 },
2681         { 0x18, 0x7fd9 },
2682         { 0x1c, 0xf0ff },
2683         { 0x1d, 0x3d9c },
2684         { 0x1f, 0x0003 },
2685         { 0x12, 0xf49f },
2686         { 0x13, 0x070b },
2687         { 0x1a, 0x05ad },
2688         { 0x14, 0x94c0 },
2689
2690         /*
2691          * Tx Error Issue
2692          * Enhance line driver power
2693          */
2694         { 0x1f, 0x0002 },
2695         { 0x06, 0x5561 },
2696         { 0x1f, 0x0005 },
2697         { 0x05, 0x8332 },
2698         { 0x06, 0x5561 },
2699
2700         /*
2701          * Can not link to 1Gbps with bad cable
2702          * Decrease SNR threshold form 21.07dB to 19.04dB
2703          */
2704         { 0x1f, 0x0001 },
2705         { 0x17, 0x0cc0 },
2706
2707         { 0x1f, 0x0000 },
2708         { 0x0d, 0xf880 }
2709 };
2710
2711 static const struct phy_reg rtl8168d_1_phy_reg_init_1[] = {
2712         { 0x1f, 0x0002 },
2713         { 0x05, 0x669a },
2714         { 0x1f, 0x0005 },
2715         { 0x05, 0x8330 },
2716         { 0x06, 0x669a },
2717         { 0x1f, 0x0002 }
2718 };
2719
2720 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
2721 {
2722         rtl_writephy_batch(tp, rtl8168d_1_phy_reg_init_0);
2723
2724         /*
2725          * Rx Error Issue
2726          * Fine Tune Switching regulator parameter
2727          */
2728         rtl_writephy(tp, 0x1f, 0x0002);
2729         rtl_w0w1_phy(tp, 0x0b, 0x0010, 0x00ef);
2730         rtl_w0w1_phy(tp, 0x0c, 0xa200, 0x5d00);
2731
2732         if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
2733                 int val;
2734
2735                 rtl_writephy_batch(tp, rtl8168d_1_phy_reg_init_1);
2736
2737                 val = rtl_readphy(tp, 0x0d);
2738
2739                 if ((val & 0x00ff) != 0x006c) {
2740                         static const u32 set[] = {
2741                                 0x0065, 0x0066, 0x0067, 0x0068,
2742                                 0x0069, 0x006a, 0x006b, 0x006c
2743                         };
2744                         int i;
2745
2746                         rtl_writephy(tp, 0x1f, 0x0002);
2747
2748                         val &= 0xff00;
2749                         for (i = 0; i < ARRAY_SIZE(set); i++)
2750                                 rtl_writephy(tp, 0x0d, val | set[i]);
2751                 }
2752         } else {
2753                 static const struct phy_reg phy_reg_init[] = {
2754                         { 0x1f, 0x0002 },
2755                         { 0x05, 0x6662 },
2756                         { 0x1f, 0x0005 },
2757                         { 0x05, 0x8330 },
2758                         { 0x06, 0x6662 }
2759                 };
2760
2761                 rtl_writephy_batch(tp, phy_reg_init);
2762         }
2763
2764         /* RSET couple improve */
2765         rtl_writephy(tp, 0x1f, 0x0002);
2766         rtl_patchphy(tp, 0x0d, 0x0300);
2767         rtl_patchphy(tp, 0x0f, 0x0010);
2768
2769         /* Fine tune PLL performance */
2770         rtl_writephy(tp, 0x1f, 0x0002);
2771         rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
2772         rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
2773
2774         rtl_writephy(tp, 0x1f, 0x0005);
2775         rtl_writephy(tp, 0x05, 0x001b);
2776
2777         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
2778
2779         rtl_writephy(tp, 0x1f, 0x0000);
2780 }
2781
2782 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
2783 {
2784         rtl_writephy_batch(tp, rtl8168d_1_phy_reg_init_0);
2785
2786         if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
2787                 int val;
2788
2789                 rtl_writephy_batch(tp, rtl8168d_1_phy_reg_init_1);
2790
2791                 val = rtl_readphy(tp, 0x0d);
2792                 if ((val & 0x00ff) != 0x006c) {
2793                         static const u32 set[] = {
2794                                 0x0065, 0x0066, 0x0067, 0x0068,
2795                                 0x0069, 0x006a, 0x006b, 0x006c
2796                         };
2797                         int i;
2798
2799                         rtl_writephy(tp, 0x1f, 0x0002);
2800
2801                         val &= 0xff00;
2802                         for (i = 0; i < ARRAY_SIZE(set); i++)
2803                                 rtl_writephy(tp, 0x0d, val | set[i]);
2804                 }
2805         } else {
2806                 static const struct phy_reg phy_reg_init[] = {
2807                         { 0x1f, 0x0002 },
2808                         { 0x05, 0x2642 },
2809                         { 0x1f, 0x0005 },
2810                         { 0x05, 0x8330 },
2811                         { 0x06, 0x2642 }
2812                 };
2813
2814                 rtl_writephy_batch(tp, phy_reg_init);
2815         }
2816
2817         /* Fine tune PLL performance */
2818         rtl_writephy(tp, 0x1f, 0x0002);
2819         rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
2820         rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
2821
2822         /* Switching regulator Slew rate */
2823         rtl_writephy(tp, 0x1f, 0x0002);
2824         rtl_patchphy(tp, 0x0f, 0x0017);
2825
2826         rtl_writephy(tp, 0x1f, 0x0005);
2827         rtl_writephy(tp, 0x05, 0x001b);
2828
2829         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
2830
2831         rtl_writephy(tp, 0x1f, 0x0000);
2832 }
2833
2834 static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
2835 {
2836         static const struct phy_reg phy_reg_init[] = {
2837                 { 0x1f, 0x0002 },
2838                 { 0x10, 0x0008 },
2839                 { 0x0d, 0x006c },
2840
2841                 { 0x1f, 0x0000 },
2842                 { 0x0d, 0xf880 },
2843
2844                 { 0x1f, 0x0001 },
2845                 { 0x17, 0x0cc0 },
2846
2847                 { 0x1f, 0x0001 },
2848                 { 0x0b, 0xa4d8 },
2849                 { 0x09, 0x281c },
2850                 { 0x07, 0x2883 },
2851                 { 0x0a, 0x6b35 },
2852                 { 0x1d, 0x3da4 },
2853                 { 0x1c, 0xeffd },
2854                 { 0x14, 0x7f52 },
2855                 { 0x18, 0x7fc6 },
2856                 { 0x08, 0x0601 },
2857                 { 0x06, 0x4063 },
2858                 { 0x10, 0xf074 },
2859                 { 0x1f, 0x0003 },
2860                 { 0x13, 0x0789 },
2861                 { 0x12, 0xf4bd },
2862                 { 0x1a, 0x04fd },
2863                 { 0x14, 0x84b0 },
2864                 { 0x1f, 0x0000 },
2865                 { 0x00, 0x9200 },
2866
2867                 { 0x1f, 0x0005 },
2868                 { 0x01, 0x0340 },
2869                 { 0x1f, 0x0001 },
2870                 { 0x04, 0x4000 },
2871                 { 0x03, 0x1d21 },
2872                 { 0x02, 0x0c32 },
2873                 { 0x01, 0x0200 },
2874                 { 0x00, 0x5554 },
2875                 { 0x04, 0x4800 },
2876                 { 0x04, 0x4000 },
2877                 { 0x04, 0xf000 },
2878                 { 0x03, 0xdf01 },
2879                 { 0x02, 0xdf20 },
2880                 { 0x01, 0x101a },
2881                 { 0x00, 0xa0ff },
2882                 { 0x04, 0xf800 },
2883                 { 0x04, 0xf000 },
2884                 { 0x1f, 0x0000 },
2885
2886                 { 0x1f, 0x0007 },
2887                 { 0x1e, 0x0023 },
2888                 { 0x16, 0x0000 },
2889                 { 0x1f, 0x0000 }
2890         };
2891
2892         rtl_writephy_batch(tp, phy_reg_init);
2893 }
2894
2895 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
2896 {
2897         static const struct phy_reg phy_reg_init[] = {
2898                 { 0x1f, 0x0001 },
2899                 { 0x17, 0x0cc0 },
2900
2901                 { 0x1f, 0x0007 },
2902                 { 0x1e, 0x002d },
2903                 { 0x18, 0x0040 },
2904                 { 0x1f, 0x0000 }
2905         };
2906
2907         rtl_writephy_batch(tp, phy_reg_init);
2908         rtl_patchphy(tp, 0x0d, 1 << 5);
2909 }
2910
2911 static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
2912 {
2913         static const struct phy_reg phy_reg_init[] = {
2914                 /* Enable Delay cap */
2915                 { 0x1f, 0x0005 },
2916                 { 0x05, 0x8b80 },
2917                 { 0x06, 0xc896 },
2918                 { 0x1f, 0x0000 },
2919
2920                 /* Channel estimation fine tune */
2921                 { 0x1f, 0x0001 },
2922                 { 0x0b, 0x6c20 },
2923                 { 0x07, 0x2872 },
2924                 { 0x1c, 0xefff },
2925                 { 0x1f, 0x0003 },
2926                 { 0x14, 0x6420 },
2927                 { 0x1f, 0x0000 },
2928
2929                 /* Update PFM & 10M TX idle timer */
2930                 { 0x1f, 0x0007 },
2931                 { 0x1e, 0x002f },
2932                 { 0x15, 0x1919 },
2933                 { 0x1f, 0x0000 },
2934
2935                 { 0x1f, 0x0007 },
2936                 { 0x1e, 0x00ac },
2937                 { 0x18, 0x0006 },
2938                 { 0x1f, 0x0000 }
2939         };
2940
2941         rtl_apply_firmware(tp);
2942
2943         rtl_writephy_batch(tp, phy_reg_init);
2944
2945         /* DCO enable for 10M IDLE Power */
2946         rtl_writephy(tp, 0x1f, 0x0007);
2947         rtl_writephy(tp, 0x1e, 0x0023);
2948         rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
2949         rtl_writephy(tp, 0x1f, 0x0000);
2950
2951         /* For impedance matching */
2952         rtl_writephy(tp, 0x1f, 0x0002);
2953         rtl_w0w1_phy(tp, 0x08, 0x8000, 0x7f00);
2954         rtl_writephy(tp, 0x1f, 0x0000);
2955
2956         /* PHY auto speed down */
2957         rtl_writephy(tp, 0x1f, 0x0007);
2958         rtl_writephy(tp, 0x1e, 0x002d);
2959         rtl_w0w1_phy(tp, 0x18, 0x0050, 0x0000);
2960         rtl_writephy(tp, 0x1f, 0x0000);
2961         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
2962
2963         rtl_writephy(tp, 0x1f, 0x0005);
2964         rtl_writephy(tp, 0x05, 0x8b86);
2965         rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
2966         rtl_writephy(tp, 0x1f, 0x0000);
2967
2968         rtl_writephy(tp, 0x1f, 0x0005);
2969         rtl_writephy(tp, 0x05, 0x8b85);
2970         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
2971         rtl_writephy(tp, 0x1f, 0x0007);
2972         rtl_writephy(tp, 0x1e, 0x0020);
2973         rtl_w0w1_phy(tp, 0x15, 0x0000, 0x1100);
2974         rtl_writephy(tp, 0x1f, 0x0006);
2975         rtl_writephy(tp, 0x00, 0x5a00);
2976         rtl_writephy(tp, 0x1f, 0x0000);
2977         rtl_writephy(tp, 0x0d, 0x0007);
2978         rtl_writephy(tp, 0x0e, 0x003c);
2979         rtl_writephy(tp, 0x0d, 0x4007);
2980         rtl_writephy(tp, 0x0e, 0x0000);
2981         rtl_writephy(tp, 0x0d, 0x0000);
2982 }
2983
2984 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, u8 *addr)
2985 {
2986         const u16 w[] = {
2987                 addr[0] | (addr[1] << 8),
2988                 addr[2] | (addr[3] << 8),
2989                 addr[4] | (addr[5] << 8)
2990         };
2991
2992         rtl_eri_write(tp, 0xe0, ERIAR_MASK_1111, w[0] | (w[1] << 16));
2993         rtl_eri_write(tp, 0xe4, ERIAR_MASK_1111, w[2]);
2994         rtl_eri_write(tp, 0xf0, ERIAR_MASK_1111, w[0] << 16);
2995         rtl_eri_write(tp, 0xf4, ERIAR_MASK_1111, w[1] | (w[2] << 16));
2996 }
2997
2998 static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
2999 {
3000         static const struct phy_reg phy_reg_init[] = {
3001                 /* Enable Delay cap */
3002                 { 0x1f, 0x0004 },
3003                 { 0x1f, 0x0007 },
3004                 { 0x1e, 0x00ac },
3005                 { 0x18, 0x0006 },
3006                 { 0x1f, 0x0002 },
3007                 { 0x1f, 0x0000 },
3008                 { 0x1f, 0x0000 },
3009
3010                 /* Channel estimation fine tune */
3011                 { 0x1f, 0x0003 },
3012                 { 0x09, 0xa20f },
3013                 { 0x1f, 0x0000 },
3014                 { 0x1f, 0x0000 },
3015
3016                 /* Green Setting */
3017                 { 0x1f, 0x0005 },
3018                 { 0x05, 0x8b5b },
3019                 { 0x06, 0x9222 },
3020                 { 0x05, 0x8b6d },
3021                 { 0x06, 0x8000 },
3022                 { 0x05, 0x8b76 },
3023                 { 0x06, 0x8000 },
3024                 { 0x1f, 0x0000 }
3025         };
3026
3027         rtl_apply_firmware(tp);
3028
3029         rtl_writephy_batch(tp, phy_reg_init);
3030
3031         /* For 4-corner performance improve */
3032         rtl_writephy(tp, 0x1f, 0x0005);
3033         rtl_writephy(tp, 0x05, 0x8b80);
3034         rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
3035         rtl_writephy(tp, 0x1f, 0x0000);
3036
3037         /* PHY auto speed down */
3038         rtl_writephy(tp, 0x1f, 0x0004);
3039         rtl_writephy(tp, 0x1f, 0x0007);
3040         rtl_writephy(tp, 0x1e, 0x002d);
3041         rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
3042         rtl_writephy(tp, 0x1f, 0x0002);
3043         rtl_writephy(tp, 0x1f, 0x0000);
3044         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3045
3046         /* improve 10M EEE waveform */
3047         rtl_writephy(tp, 0x1f, 0x0005);
3048         rtl_writephy(tp, 0x05, 0x8b86);
3049         rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3050         rtl_writephy(tp, 0x1f, 0x0000);
3051
3052         /* Improve 2-pair detection performance */
3053         rtl_writephy(tp, 0x1f, 0x0005);
3054         rtl_writephy(tp, 0x05, 0x8b85);
3055         rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3056         rtl_writephy(tp, 0x1f, 0x0000);
3057
3058         rtl8168f_config_eee_phy(tp);
3059         rtl_enable_eee(tp);
3060
3061         /* Green feature */
3062         rtl_writephy(tp, 0x1f, 0x0003);
3063         rtl_w0w1_phy(tp, 0x19, 0x0001, 0x0000);
3064         rtl_w0w1_phy(tp, 0x10, 0x0400, 0x0000);
3065         rtl_writephy(tp, 0x1f, 0x0000);
3066         rtl_writephy(tp, 0x1f, 0x0005);
3067         rtl_w0w1_phy(tp, 0x01, 0x0100, 0x0000);
3068         rtl_writephy(tp, 0x1f, 0x0000);
3069
3070         /* Broken BIOS workaround: feed GigaMAC registers with MAC address. */
3071         rtl_rar_exgmac_set(tp, tp->dev->dev_addr);
3072 }
3073
3074 static void rtl8168f_hw_phy_config(struct rtl8169_private *tp)
3075 {
3076         /* For 4-corner performance improve */
3077         rtl_writephy(tp, 0x1f, 0x0005);
3078         rtl_writephy(tp, 0x05, 0x8b80);
3079         rtl_w0w1_phy(tp, 0x06, 0x0006, 0x0000);
3080         rtl_writephy(tp, 0x1f, 0x0000);
3081
3082         /* PHY auto speed down */
3083         rtl_writephy(tp, 0x1f, 0x0007);
3084         rtl_writephy(tp, 0x1e, 0x002d);
3085         rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
3086         rtl_writephy(tp, 0x1f, 0x0000);
3087         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3088
3089         /* Improve 10M EEE waveform */
3090         rtl_writephy(tp, 0x1f, 0x0005);
3091         rtl_writephy(tp, 0x05, 0x8b86);
3092         rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3093         rtl_writephy(tp, 0x1f, 0x0000);
3094
3095         rtl8168f_config_eee_phy(tp);
3096         rtl_enable_eee(tp);
3097 }
3098
3099 static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp)
3100 {
3101         static const struct phy_reg phy_reg_init[] = {
3102                 /* Channel estimation fine tune */
3103                 { 0x1f, 0x0003 },
3104                 { 0x09, 0xa20f },
3105                 { 0x1f, 0x0000 },
3106
3107                 /* Modify green table for giga & fnet */
3108                 { 0x1f, 0x0005 },
3109                 { 0x05, 0x8b55 },
3110                 { 0x06, 0x0000 },
3111                 { 0x05, 0x8b5e },
3112                 { 0x06, 0x0000 },
3113                 { 0x05, 0x8b67 },
3114                 { 0x06, 0x0000 },
3115                 { 0x05, 0x8b70 },
3116                 { 0x06, 0x0000 },
3117                 { 0x1f, 0x0000 },
3118                 { 0x1f, 0x0007 },
3119                 { 0x1e, 0x0078 },
3120                 { 0x17, 0x0000 },
3121                 { 0x19, 0x00fb },
3122                 { 0x1f, 0x0000 },
3123
3124                 /* Modify green table for 10M */
3125                 { 0x1f, 0x0005 },
3126                 { 0x05, 0x8b79 },
3127                 { 0x06, 0xaa00 },
3128                 { 0x1f, 0x0000 },
3129
3130                 /* Disable hiimpedance detection (RTCT) */
3131                 { 0x1f, 0x0003 },
3132                 { 0x01, 0x328a },
3133                 { 0x1f, 0x0000 }
3134         };
3135
3136         rtl_apply_firmware(tp);
3137
3138         rtl_writephy_batch(tp, phy_reg_init);
3139
3140         rtl8168f_hw_phy_config(tp);
3141
3142         /* Improve 2-pair detection performance */
3143         rtl_writephy(tp, 0x1f, 0x0005);
3144         rtl_writephy(tp, 0x05, 0x8b85);
3145         rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3146         rtl_writephy(tp, 0x1f, 0x0000);
3147 }
3148
3149 static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp)
3150 {
3151         rtl_apply_firmware(tp);
3152
3153         rtl8168f_hw_phy_config(tp);
3154 }
3155
3156 static void rtl8411_hw_phy_config(struct rtl8169_private *tp)
3157 {
3158         static const struct phy_reg phy_reg_init[] = {
3159                 /* Channel estimation fine tune */
3160                 { 0x1f, 0x0003 },
3161                 { 0x09, 0xa20f },
3162                 { 0x1f, 0x0000 },
3163
3164                 /* Modify green table for giga & fnet */
3165                 { 0x1f, 0x0005 },
3166                 { 0x05, 0x8b55 },
3167                 { 0x06, 0x0000 },
3168                 { 0x05, 0x8b5e },
3169                 { 0x06, 0x0000 },
3170                 { 0x05, 0x8b67 },
3171                 { 0x06, 0x0000 },
3172                 { 0x05, 0x8b70 },
3173                 { 0x06, 0x0000 },
3174                 { 0x1f, 0x0000 },
3175                 { 0x1f, 0x0007 },
3176                 { 0x1e, 0x0078 },
3177                 { 0x17, 0x0000 },
3178                 { 0x19, 0x00aa },
3179                 { 0x1f, 0x0000 },
3180
3181                 /* Modify green table for 10M */
3182                 { 0x1f, 0x0005 },
3183                 { 0x05, 0x8b79 },
3184                 { 0x06, 0xaa00 },
3185                 { 0x1f, 0x0000 },
3186
3187                 /* Disable hiimpedance detection (RTCT) */
3188                 { 0x1f, 0x0003 },
3189                 { 0x01, 0x328a },
3190                 { 0x1f, 0x0000 }
3191         };
3192
3193
3194         rtl_apply_firmware(tp);
3195
3196         rtl8168f_hw_phy_config(tp);
3197
3198         /* Improve 2-pair detection performance */
3199         rtl_writephy(tp, 0x1f, 0x0005);
3200         rtl_writephy(tp, 0x05, 0x8b85);
3201         rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3202         rtl_writephy(tp, 0x1f, 0x0000);
3203
3204         rtl_writephy_batch(tp, phy_reg_init);
3205
3206         /* Modify green table for giga */
3207         rtl_writephy(tp, 0x1f, 0x0005);
3208         rtl_writephy(tp, 0x05, 0x8b54);
3209         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
3210         rtl_writephy(tp, 0x05, 0x8b5d);
3211         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
3212         rtl_writephy(tp, 0x05, 0x8a7c);
3213         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3214         rtl_writephy(tp, 0x05, 0x8a7f);
3215         rtl_w0w1_phy(tp, 0x06, 0x0100, 0x0000);
3216         rtl_writephy(tp, 0x05, 0x8a82);
3217         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3218         rtl_writephy(tp, 0x05, 0x8a85);
3219         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3220         rtl_writephy(tp, 0x05, 0x8a88);
3221         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3222         rtl_writephy(tp, 0x1f, 0x0000);
3223
3224         /* uc same-seed solution */
3225         rtl_writephy(tp, 0x1f, 0x0005);
3226         rtl_writephy(tp, 0x05, 0x8b85);
3227         rtl_w0w1_phy(tp, 0x06, 0x8000, 0x0000);
3228         rtl_writephy(tp, 0x1f, 0x0000);
3229
3230         /* Green feature */
3231         rtl_writephy(tp, 0x1f, 0x0003);
3232         rtl_w0w1_phy(tp, 0x19, 0x0000, 0x0001);
3233         rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0400);
3234         rtl_writephy(tp, 0x1f, 0x0000);
3235 }
3236
3237 static void rtl8168g_disable_aldps(struct rtl8169_private *tp)
3238 {
3239         phy_modify_paged(tp->phydev, 0x0a43, 0x10, BIT(2), 0);
3240 }
3241
3242 static void rtl8168g_phy_adjust_10m_aldps(struct rtl8169_private *tp)
3243 {
3244         struct phy_device *phydev = tp->phydev;
3245
3246         phy_modify_paged(phydev, 0x0bcc, 0x14, BIT(8), 0);
3247         phy_modify_paged(phydev, 0x0a44, 0x11, 0, BIT(7) | BIT(6));
3248         phy_write(phydev, 0x1f, 0x0a43);
3249         phy_write(phydev, 0x13, 0x8084);
3250         phy_clear_bits(phydev, 0x14, BIT(14) | BIT(13));
3251         phy_set_bits(phydev, 0x10, BIT(12) | BIT(1) | BIT(0));
3252
3253         phy_write(phydev, 0x1f, 0x0000);
3254 }
3255
3256 static void rtl8168g_1_hw_phy_config(struct rtl8169_private *tp)
3257 {
3258         int ret;
3259
3260         rtl_apply_firmware(tp);
3261
3262         ret = phy_read_paged(tp->phydev, 0x0a46, 0x10);
3263         if (ret & BIT(8))
3264                 phy_modify_paged(tp->phydev, 0x0bcc, 0x12, BIT(15), 0);
3265         else
3266                 phy_modify_paged(tp->phydev, 0x0bcc, 0x12, 0, BIT(15));
3267
3268         ret = phy_read_paged(tp->phydev, 0x0a46, 0x13);
3269         if (ret & BIT(8))
3270                 phy_modify_paged(tp->phydev, 0x0c41, 0x15, 0, BIT(1));
3271         else
3272                 phy_modify_paged(tp->phydev, 0x0c41, 0x15, BIT(1), 0);
3273
3274         /* Enable PHY auto speed down */
3275         phy_modify_paged(tp->phydev, 0x0a44, 0x11, 0, BIT(3) | BIT(2));
3276
3277         rtl8168g_phy_adjust_10m_aldps(tp);
3278
3279         /* EEE auto-fallback function */
3280         phy_modify_paged(tp->phydev, 0x0a4b, 0x11, 0, BIT(2));
3281
3282         /* Enable UC LPF tune function */
3283         rtl_writephy(tp, 0x1f, 0x0a43);
3284         rtl_writephy(tp, 0x13, 0x8012);
3285         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3286
3287         phy_modify_paged(tp->phydev, 0x0c42, 0x11, BIT(13), BIT(14));
3288
3289         /* Improve SWR Efficiency */
3290         rtl_writephy(tp, 0x1f, 0x0bcd);
3291         rtl_writephy(tp, 0x14, 0x5065);
3292         rtl_writephy(tp, 0x14, 0xd065);
3293         rtl_writephy(tp, 0x1f, 0x0bc8);
3294         rtl_writephy(tp, 0x11, 0x5655);
3295         rtl_writephy(tp, 0x1f, 0x0bcd);
3296         rtl_writephy(tp, 0x14, 0x1065);
3297         rtl_writephy(tp, 0x14, 0x9065);
3298         rtl_writephy(tp, 0x14, 0x1065);
3299         rtl_writephy(tp, 0x1f, 0x0000);
3300
3301         rtl8168g_disable_aldps(tp);
3302         rtl8168g_config_eee_phy(tp);
3303         rtl_enable_eee(tp);
3304 }
3305
3306 static void rtl8168g_2_hw_phy_config(struct rtl8169_private *tp)
3307 {
3308         rtl_apply_firmware(tp);
3309         rtl8168g_config_eee_phy(tp);
3310         rtl_enable_eee(tp);
3311 }
3312
3313 static void rtl8168h_1_hw_phy_config(struct rtl8169_private *tp)
3314 {
3315         u16 dout_tapbin;
3316         u32 data;
3317
3318         rtl_apply_firmware(tp);
3319
3320         /* CHN EST parameters adjust - giga master */
3321         rtl_writephy(tp, 0x1f, 0x0a43);
3322         rtl_writephy(tp, 0x13, 0x809b);
3323         rtl_w0w1_phy(tp, 0x14, 0x8000, 0xf800);
3324         rtl_writephy(tp, 0x13, 0x80a2);
3325         rtl_w0w1_phy(tp, 0x14, 0x8000, 0xff00);
3326         rtl_writephy(tp, 0x13, 0x80a4);
3327         rtl_w0w1_phy(tp, 0x14, 0x8500, 0xff00);
3328         rtl_writephy(tp, 0x13, 0x809c);
3329         rtl_w0w1_phy(tp, 0x14, 0xbd00, 0xff00);
3330         rtl_writephy(tp, 0x1f, 0x0000);
3331
3332         /* CHN EST parameters adjust - giga slave */
3333         rtl_writephy(tp, 0x1f, 0x0a43);
3334         rtl_writephy(tp, 0x13, 0x80ad);
3335         rtl_w0w1_phy(tp, 0x14, 0x7000, 0xf800);
3336         rtl_writephy(tp, 0x13, 0x80b4);
3337         rtl_w0w1_phy(tp, 0x14, 0x5000, 0xff00);
3338         rtl_writephy(tp, 0x13, 0x80ac);
3339         rtl_w0w1_phy(tp, 0x14, 0x4000, 0xff00);
3340         rtl_writephy(tp, 0x1f, 0x0000);
3341
3342         /* CHN EST parameters adjust - fnet */
3343         rtl_writephy(tp, 0x1f, 0x0a43);
3344         rtl_writephy(tp, 0x13, 0x808e);
3345         rtl_w0w1_phy(tp, 0x14, 0x1200, 0xff00);
3346         rtl_writephy(tp, 0x13, 0x8090);
3347         rtl_w0w1_phy(tp, 0x14, 0xe500, 0xff00);
3348         rtl_writephy(tp, 0x13, 0x8092);
3349         rtl_w0w1_phy(tp, 0x14, 0x9f00, 0xff00);
3350         rtl_writephy(tp, 0x1f, 0x0000);
3351
3352         /* enable R-tune & PGA-retune function */
3353         dout_tapbin = 0;
3354         rtl_writephy(tp, 0x1f, 0x0a46);
3355         data = rtl_readphy(tp, 0x13);
3356         data &= 3;
3357         data <<= 2;
3358         dout_tapbin |= data;
3359         data = rtl_readphy(tp, 0x12);
3360         data &= 0xc000;
3361         data >>= 14;
3362         dout_tapbin |= data;
3363         dout_tapbin = ~(dout_tapbin^0x08);
3364         dout_tapbin <<= 12;
3365         dout_tapbin &= 0xf000;
3366         rtl_writephy(tp, 0x1f, 0x0a43);
3367         rtl_writephy(tp, 0x13, 0x827a);
3368         rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3369         rtl_writephy(tp, 0x13, 0x827b);
3370         rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3371         rtl_writephy(tp, 0x13, 0x827c);
3372         rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3373         rtl_writephy(tp, 0x13, 0x827d);
3374         rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3375
3376         rtl_writephy(tp, 0x1f, 0x0a43);
3377         rtl_writephy(tp, 0x13, 0x0811);
3378         rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
3379         rtl_writephy(tp, 0x1f, 0x0a42);
3380         rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
3381         rtl_writephy(tp, 0x1f, 0x0000);
3382
3383         /* enable GPHY 10M */
3384         phy_modify_paged(tp->phydev, 0x0a44, 0x11, 0, BIT(11));
3385
3386         /* SAR ADC performance */
3387         phy_modify_paged(tp->phydev, 0x0bca, 0x17, BIT(12) | BIT(13), BIT(14));
3388
3389         rtl_writephy(tp, 0x1f, 0x0a43);
3390         rtl_writephy(tp, 0x13, 0x803f);
3391         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3392         rtl_writephy(tp, 0x13, 0x8047);
3393         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3394         rtl_writephy(tp, 0x13, 0x804f);
3395         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3396         rtl_writephy(tp, 0x13, 0x8057);
3397         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3398         rtl_writephy(tp, 0x13, 0x805f);
3399         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3400         rtl_writephy(tp, 0x13, 0x8067);
3401         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3402         rtl_writephy(tp, 0x13, 0x806f);
3403         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3404         rtl_writephy(tp, 0x1f, 0x0000);
3405
3406         /* disable phy pfm mode */
3407         phy_modify_paged(tp->phydev, 0x0a44, 0x11, BIT(7), 0);
3408
3409         rtl8168g_disable_aldps(tp);
3410         rtl8168g_config_eee_phy(tp);
3411         rtl_enable_eee(tp);
3412 }
3413
3414 static void rtl8168h_2_hw_phy_config(struct rtl8169_private *tp)
3415 {
3416         u16 ioffset_p3, ioffset_p2, ioffset_p1, ioffset_p0;
3417         u16 rlen;
3418         u32 data;
3419
3420         rtl_apply_firmware(tp);
3421
3422         /* CHIN EST parameter update */
3423         rtl_writephy(tp, 0x1f, 0x0a43);
3424         rtl_writephy(tp, 0x13, 0x808a);
3425         rtl_w0w1_phy(tp, 0x14, 0x000a, 0x003f);
3426         rtl_writephy(tp, 0x1f, 0x0000);
3427
3428         /* enable R-tune & PGA-retune function */
3429         rtl_writephy(tp, 0x1f, 0x0a43);
3430         rtl_writephy(tp, 0x13, 0x0811);
3431         rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
3432         rtl_writephy(tp, 0x1f, 0x0a42);
3433         rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
3434         rtl_writephy(tp, 0x1f, 0x0000);
3435
3436         /* enable GPHY 10M */
3437         phy_modify_paged(tp->phydev, 0x0a44, 0x11, 0, BIT(11));
3438
3439         r8168_mac_ocp_write(tp, 0xdd02, 0x807d);
3440         data = r8168_mac_ocp_read(tp, 0xdd02);
3441         ioffset_p3 = ((data & 0x80)>>7);
3442         ioffset_p3 <<= 3;
3443
3444         data = r8168_mac_ocp_read(tp, 0xdd00);
3445         ioffset_p3 |= ((data & (0xe000))>>13);
3446         ioffset_p2 = ((data & (0x1e00))>>9);
3447         ioffset_p1 = ((data & (0x01e0))>>5);
3448         ioffset_p0 = ((data & 0x0010)>>4);
3449         ioffset_p0 <<= 3;
3450         ioffset_p0 |= (data & (0x07));
3451         data = (ioffset_p3<<12)|(ioffset_p2<<8)|(ioffset_p1<<4)|(ioffset_p0);
3452
3453         if ((ioffset_p3 != 0x0f) || (ioffset_p2 != 0x0f) ||
3454             (ioffset_p1 != 0x0f) || (ioffset_p0 != 0x0f)) {
3455                 rtl_writephy(tp, 0x1f, 0x0bcf);
3456                 rtl_writephy(tp, 0x16, data);
3457                 rtl_writephy(tp, 0x1f, 0x0000);
3458         }
3459
3460         /* Modify rlen (TX LPF corner frequency) level */
3461         rtl_writephy(tp, 0x1f, 0x0bcd);
3462         data = rtl_readphy(tp, 0x16);
3463         data &= 0x000f;
3464         rlen = 0;
3465         if (data > 3)
3466                 rlen = data - 3;
3467         data = rlen | (rlen<<4) | (rlen<<8) | (rlen<<12);
3468         rtl_writephy(tp, 0x17, data);
3469         rtl_writephy(tp, 0x1f, 0x0bcd);
3470         rtl_writephy(tp, 0x1f, 0x0000);
3471
3472         /* disable phy pfm mode */
3473         phy_modify_paged(tp->phydev, 0x0a44, 0x11, BIT(7), 0);
3474
3475         rtl8168g_disable_aldps(tp);
3476         rtl8168g_config_eee_phy(tp);
3477         rtl_enable_eee(tp);
3478 }
3479
3480 static void rtl8168ep_1_hw_phy_config(struct rtl8169_private *tp)
3481 {
3482         /* Enable PHY auto speed down */
3483         phy_modify_paged(tp->phydev, 0x0a44, 0x11, 0, BIT(3) | BIT(2));
3484
3485         rtl8168g_phy_adjust_10m_aldps(tp);
3486
3487         /* Enable EEE auto-fallback function */
3488         phy_modify_paged(tp->phydev, 0x0a4b, 0x11, 0, BIT(2));
3489
3490         /* Enable UC LPF tune function */
3491         rtl_writephy(tp, 0x1f, 0x0a43);
3492         rtl_writephy(tp, 0x13, 0x8012);
3493         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3494         rtl_writephy(tp, 0x1f, 0x0000);
3495
3496         /* set rg_sel_sdm_rate */
3497         phy_modify_paged(tp->phydev, 0x0c42, 0x11, BIT(13), BIT(14));
3498
3499         rtl8168g_disable_aldps(tp);
3500         rtl8168g_config_eee_phy(tp);
3501         rtl_enable_eee(tp);
3502 }
3503
3504 static void rtl8168ep_2_hw_phy_config(struct rtl8169_private *tp)
3505 {
3506         rtl8168g_phy_adjust_10m_aldps(tp);
3507
3508         /* Enable UC LPF tune function */
3509         rtl_writephy(tp, 0x1f, 0x0a43);
3510         rtl_writephy(tp, 0x13, 0x8012);
3511         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3512         rtl_writephy(tp, 0x1f, 0x0000);
3513
3514         /* Set rg_sel_sdm_rate */
3515         phy_modify_paged(tp->phydev, 0x0c42, 0x11, BIT(13), BIT(14));
3516
3517         /* Channel estimation parameters */
3518         rtl_writephy(tp, 0x1f, 0x0a43);
3519         rtl_writephy(tp, 0x13, 0x80f3);
3520         rtl_w0w1_phy(tp, 0x14, 0x8b00, ~0x8bff);
3521         rtl_writephy(tp, 0x13, 0x80f0);
3522         rtl_w0w1_phy(tp, 0x14, 0x3a00, ~0x3aff);
3523         rtl_writephy(tp, 0x13, 0x80ef);
3524         rtl_w0w1_phy(tp, 0x14, 0x0500, ~0x05ff);
3525         rtl_writephy(tp, 0x13, 0x80f6);
3526         rtl_w0w1_phy(tp, 0x14, 0x6e00, ~0x6eff);
3527         rtl_writephy(tp, 0x13, 0x80ec);
3528         rtl_w0w1_phy(tp, 0x14, 0x6800, ~0x68ff);
3529         rtl_writephy(tp, 0x13, 0x80ed);
3530         rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
3531         rtl_writephy(tp, 0x13, 0x80f2);
3532         rtl_w0w1_phy(tp, 0x14, 0xf400, ~0xf4ff);
3533         rtl_writephy(tp, 0x13, 0x80f4);
3534         rtl_w0w1_phy(tp, 0x14, 0x8500, ~0x85ff);
3535         rtl_writephy(tp, 0x1f, 0x0a43);
3536         rtl_writephy(tp, 0x13, 0x8110);
3537         rtl_w0w1_phy(tp, 0x14, 0xa800, ~0xa8ff);
3538         rtl_writephy(tp, 0x13, 0x810f);
3539         rtl_w0w1_phy(tp, 0x14, 0x1d00, ~0x1dff);
3540         rtl_writephy(tp, 0x13, 0x8111);
3541         rtl_w0w1_phy(tp, 0x14, 0xf500, ~0xf5ff);
3542         rtl_writephy(tp, 0x13, 0x8113);
3543         rtl_w0w1_phy(tp, 0x14, 0x6100, ~0x61ff);
3544         rtl_writephy(tp, 0x13, 0x8115);
3545         rtl_w0w1_phy(tp, 0x14, 0x9200, ~0x92ff);
3546         rtl_writephy(tp, 0x13, 0x810e);
3547         rtl_w0w1_phy(tp, 0x14, 0x0400, ~0x04ff);
3548         rtl_writephy(tp, 0x13, 0x810c);
3549         rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
3550         rtl_writephy(tp, 0x13, 0x810b);
3551         rtl_w0w1_phy(tp, 0x14, 0x5a00, ~0x5aff);
3552         rtl_writephy(tp, 0x1f, 0x0a43);
3553         rtl_writephy(tp, 0x13, 0x80d1);
3554         rtl_w0w1_phy(tp, 0x14, 0xff00, ~0xffff);
3555         rtl_writephy(tp, 0x13, 0x80cd);
3556         rtl_w0w1_phy(tp, 0x14, 0x9e00, ~0x9eff);
3557         rtl_writephy(tp, 0x13, 0x80d3);
3558         rtl_w0w1_phy(tp, 0x14, 0x0e00, ~0x0eff);
3559         rtl_writephy(tp, 0x13, 0x80d5);
3560         rtl_w0w1_phy(tp, 0x14, 0xca00, ~0xcaff);
3561         rtl_writephy(tp, 0x13, 0x80d7);
3562         rtl_w0w1_phy(tp, 0x14, 0x8400, ~0x84ff);
3563
3564         /* Force PWM-mode */
3565         rtl_writephy(tp, 0x1f, 0x0bcd);
3566         rtl_writephy(tp, 0x14, 0x5065);
3567         rtl_writephy(tp, 0x14, 0xd065);
3568         rtl_writephy(tp, 0x1f, 0x0bc8);
3569         rtl_writephy(tp, 0x12, 0x00ed);
3570         rtl_writephy(tp, 0x1f, 0x0bcd);
3571         rtl_writephy(tp, 0x14, 0x1065);
3572         rtl_writephy(tp, 0x14, 0x9065);
3573         rtl_writephy(tp, 0x14, 0x1065);
3574         rtl_writephy(tp, 0x1f, 0x0000);
3575
3576         rtl8168g_disable_aldps(tp);
3577         rtl8168g_config_eee_phy(tp);
3578         rtl_enable_eee(tp);
3579 }
3580
3581 static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
3582 {
3583         static const struct phy_reg phy_reg_init[] = {
3584                 { 0x1f, 0x0003 },
3585                 { 0x08, 0x441d },
3586                 { 0x01, 0x9100 },
3587                 { 0x1f, 0x0000 }
3588         };
3589
3590         rtl_writephy(tp, 0x1f, 0x0000);
3591         rtl_patchphy(tp, 0x11, 1 << 12);
3592         rtl_patchphy(tp, 0x19, 1 << 13);
3593         rtl_patchphy(tp, 0x10, 1 << 15);
3594
3595         rtl_writephy_batch(tp, phy_reg_init);
3596 }
3597
3598 static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
3599 {
3600         static const struct phy_reg phy_reg_init[] = {
3601                 { 0x1f, 0x0005 },
3602                 { 0x1a, 0x0000 },
3603                 { 0x1f, 0x0000 },
3604
3605                 { 0x1f, 0x0004 },
3606                 { 0x1c, 0x0000 },
3607                 { 0x1f, 0x0000 },
3608
3609                 { 0x1f, 0x0001 },
3610                 { 0x15, 0x7701 },
3611                 { 0x1f, 0x0000 }
3612         };
3613
3614         /* Disable ALDPS before ram code */
3615         rtl_writephy(tp, 0x1f, 0x0000);
3616         rtl_writephy(tp, 0x18, 0x0310);
3617         msleep(100);
3618
3619         rtl_apply_firmware(tp);
3620
3621         rtl_writephy_batch(tp, phy_reg_init);
3622 }
3623
3624 static void rtl8402_hw_phy_config(struct rtl8169_private *tp)
3625 {
3626         /* Disable ALDPS before setting firmware */
3627         rtl_writephy(tp, 0x1f, 0x0000);
3628         rtl_writephy(tp, 0x18, 0x0310);
3629         msleep(20);
3630
3631         rtl_apply_firmware(tp);
3632
3633         /* EEE setting */
3634         rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000);
3635         rtl_writephy(tp, 0x1f, 0x0004);
3636         rtl_writephy(tp, 0x10, 0x401f);
3637         rtl_writephy(tp, 0x19, 0x7030);
3638         rtl_writephy(tp, 0x1f, 0x0000);
3639 }
3640
3641 static void rtl8106e_hw_phy_config(struct rtl8169_private *tp)
3642 {
3643         static const struct phy_reg phy_reg_init[] = {
3644                 { 0x1f, 0x0004 },
3645                 { 0x10, 0xc07f },
3646                 { 0x19, 0x7030 },
3647                 { 0x1f, 0x0000 }
3648         };
3649
3650         /* Disable ALDPS before ram code */
3651         rtl_writephy(tp, 0x1f, 0x0000);
3652         rtl_writephy(tp, 0x18, 0x0310);
3653         msleep(100);
3654
3655         rtl_apply_firmware(tp);
3656
3657         rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000);
3658         rtl_writephy_batch(tp, phy_reg_init);
3659
3660         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000);
3661 }
3662
3663 static void rtl_hw_phy_config(struct net_device *dev)
3664 {
3665         static const rtl_generic_fct phy_configs[] = {
3666                 /* PCI devices. */
3667                 [RTL_GIGA_MAC_VER_02] = rtl8169s_hw_phy_config,
3668                 [RTL_GIGA_MAC_VER_03] = rtl8169s_hw_phy_config,
3669                 [RTL_GIGA_MAC_VER_04] = rtl8169sb_hw_phy_config,
3670                 [RTL_GIGA_MAC_VER_05] = rtl8169scd_hw_phy_config,
3671                 [RTL_GIGA_MAC_VER_06] = rtl8169sce_hw_phy_config,
3672                 /* PCI-E devices. */
3673                 [RTL_GIGA_MAC_VER_07] = rtl8102e_hw_phy_config,
3674                 [RTL_GIGA_MAC_VER_08] = rtl8102e_hw_phy_config,
3675                 [RTL_GIGA_MAC_VER_09] = rtl8102e_hw_phy_config,
3676                 [RTL_GIGA_MAC_VER_10] = NULL,
3677                 [RTL_GIGA_MAC_VER_11] = rtl8168bb_hw_phy_config,
3678                 [RTL_GIGA_MAC_VER_12] = rtl8168bef_hw_phy_config,
3679                 [RTL_GIGA_MAC_VER_13] = NULL,
3680                 [RTL_GIGA_MAC_VER_14] = NULL,
3681                 [RTL_GIGA_MAC_VER_15] = NULL,
3682                 [RTL_GIGA_MAC_VER_16] = NULL,
3683                 [RTL_GIGA_MAC_VER_17] = rtl8168bef_hw_phy_config,
3684                 [RTL_GIGA_MAC_VER_18] = rtl8168cp_1_hw_phy_config,
3685                 [RTL_GIGA_MAC_VER_19] = rtl8168c_1_hw_phy_config,
3686                 [RTL_GIGA_MAC_VER_20] = rtl8168c_2_hw_phy_config,
3687                 [RTL_GIGA_MAC_VER_21] = rtl8168c_3_hw_phy_config,
3688                 [RTL_GIGA_MAC_VER_22] = rtl8168c_4_hw_phy_config,
3689                 [RTL_GIGA_MAC_VER_23] = rtl8168cp_2_hw_phy_config,
3690                 [RTL_GIGA_MAC_VER_24] = rtl8168cp_2_hw_phy_config,
3691                 [RTL_GIGA_MAC_VER_25] = rtl8168d_1_hw_phy_config,
3692                 [RTL_GIGA_MAC_VER_26] = rtl8168d_2_hw_phy_config,
3693                 [RTL_GIGA_MAC_VER_27] = rtl8168d_3_hw_phy_config,
3694                 [RTL_GIGA_MAC_VER_28] = rtl8168d_4_hw_phy_config,
3695                 [RTL_GIGA_MAC_VER_29] = rtl8105e_hw_phy_config,
3696                 [RTL_GIGA_MAC_VER_30] = rtl8105e_hw_phy_config,
3697                 [RTL_GIGA_MAC_VER_31] = NULL,
3698                 [RTL_GIGA_MAC_VER_32] = rtl8168e_1_hw_phy_config,
3699                 [RTL_GIGA_MAC_VER_33] = rtl8168e_1_hw_phy_config,
3700                 [RTL_GIGA_MAC_VER_34] = rtl8168e_2_hw_phy_config,
3701                 [RTL_GIGA_MAC_VER_35] = rtl8168f_1_hw_phy_config,
3702                 [RTL_GIGA_MAC_VER_36] = rtl8168f_2_hw_phy_config,
3703                 [RTL_GIGA_MAC_VER_37] = rtl8402_hw_phy_config,
3704                 [RTL_GIGA_MAC_VER_38] = rtl8411_hw_phy_config,
3705                 [RTL_GIGA_MAC_VER_39] = rtl8106e_hw_phy_config,
3706                 [RTL_GIGA_MAC_VER_40] = rtl8168g_1_hw_phy_config,
3707                 [RTL_GIGA_MAC_VER_41] = NULL,
3708                 [RTL_GIGA_MAC_VER_42] = rtl8168g_2_hw_phy_config,
3709                 [RTL_GIGA_MAC_VER_43] = rtl8168g_2_hw_phy_config,
3710                 [RTL_GIGA_MAC_VER_44] = rtl8168g_2_hw_phy_config,
3711                 [RTL_GIGA_MAC_VER_45] = rtl8168h_1_hw_phy_config,
3712                 [RTL_GIGA_MAC_VER_46] = rtl8168h_2_hw_phy_config,
3713                 [RTL_GIGA_MAC_VER_47] = rtl8168h_1_hw_phy_config,
3714                 [RTL_GIGA_MAC_VER_48] = rtl8168h_2_hw_phy_config,
3715                 [RTL_GIGA_MAC_VER_49] = rtl8168ep_1_hw_phy_config,
3716                 [RTL_GIGA_MAC_VER_50] = rtl8168ep_2_hw_phy_config,
3717                 [RTL_GIGA_MAC_VER_51] = rtl8168ep_2_hw_phy_config,
3718         };
3719         struct rtl8169_private *tp = netdev_priv(dev);
3720
3721         if (phy_configs[tp->mac_version])
3722                 phy_configs[tp->mac_version](tp);
3723 }
3724
3725 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
3726 {
3727         if (!test_and_set_bit(flag, tp->wk.flags))
3728                 schedule_work(&tp->wk.work);
3729 }
3730
3731 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
3732 {
3733         rtl_hw_phy_config(dev);
3734
3735         if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
3736                 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
3737                 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
3738                 netif_dbg(tp, drv, dev,
3739                           "Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3740                 RTL_W8(tp, 0x82, 0x01);
3741         }
3742
3743         /* We may have called phy_speed_down before */
3744         phy_speed_up(tp->phydev);
3745
3746         genphy_soft_reset(tp->phydev);
3747 }
3748
3749 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
3750 {
3751         rtl_lock_work(tp);
3752
3753         rtl_unlock_config_regs(tp);
3754
3755         RTL_W32(tp, MAC4, addr[4] | addr[5] << 8);
3756         RTL_R32(tp, MAC4);
3757
3758         RTL_W32(tp, MAC0, addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24);
3759         RTL_R32(tp, MAC0);
3760
3761         if (tp->mac_version == RTL_GIGA_MAC_VER_34)
3762                 rtl_rar_exgmac_set(tp, addr);
3763
3764         rtl_lock_config_regs(tp);
3765
3766         rtl_unlock_work(tp);
3767 }
3768
3769 static int rtl_set_mac_address(struct net_device *dev, void *p)
3770 {
3771         struct rtl8169_private *tp = netdev_priv(dev);
3772         struct device *d = tp_to_dev(tp);
3773         int ret;
3774
3775         ret = eth_mac_addr(dev, p);
3776         if (ret)
3777                 return ret;
3778
3779         pm_runtime_get_noresume(d);
3780
3781         if (pm_runtime_active(d))
3782                 rtl_rar_set(tp, dev->dev_addr);
3783
3784         pm_runtime_put_noidle(d);
3785
3786         return 0;
3787 }
3788
3789 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
3790 {
3791         struct rtl8169_private *tp = netdev_priv(dev);
3792
3793         if (!netif_running(dev))
3794                 return -ENODEV;
3795
3796         return phy_mii_ioctl(tp->phydev, ifr, cmd);
3797 }
3798
3799 static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
3800 {
3801         switch (tp->mac_version) {
3802         case RTL_GIGA_MAC_VER_25:
3803         case RTL_GIGA_MAC_VER_26:
3804         case RTL_GIGA_MAC_VER_29:
3805         case RTL_GIGA_MAC_VER_30:
3806         case RTL_GIGA_MAC_VER_32:
3807         case RTL_GIGA_MAC_VER_33:
3808         case RTL_GIGA_MAC_VER_34:
3809         case RTL_GIGA_MAC_VER_37 ... RTL_GIGA_MAC_VER_51:
3810                 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) |
3811                         AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
3812                 break;
3813         default:
3814                 break;
3815         }
3816 }
3817
3818 static void rtl_pll_power_down(struct rtl8169_private *tp)
3819 {
3820         if (r8168_check_dash(tp))
3821                 return;
3822
3823         if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
3824             tp->mac_version == RTL_GIGA_MAC_VER_33)
3825                 rtl_ephy_write(tp, 0x19, 0xff64);
3826
3827         if (device_may_wakeup(tp_to_dev(tp))) {
3828                 phy_speed_down(tp->phydev, false);
3829                 rtl_wol_suspend_quirk(tp);
3830                 return;
3831         }
3832
3833         switch (tp->mac_version) {
3834         case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_33:
3835         case RTL_GIGA_MAC_VER_37:
3836         case RTL_GIGA_MAC_VER_39:
3837         case RTL_GIGA_MAC_VER_43:
3838         case RTL_GIGA_MAC_VER_44:
3839         case RTL_GIGA_MAC_VER_45:
3840         case RTL_GIGA_MAC_VER_46:
3841         case RTL_GIGA_MAC_VER_47:
3842         case RTL_GIGA_MAC_VER_48:
3843         case RTL_GIGA_MAC_VER_50:
3844         case RTL_GIGA_MAC_VER_51:
3845                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80);
3846                 break;
3847         case RTL_GIGA_MAC_VER_40:
3848         case RTL_GIGA_MAC_VER_41:
3849         case RTL_GIGA_MAC_VER_49:
3850                 rtl_eri_clear_bits(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000);
3851                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80);
3852                 break;
3853         default:
3854                 break;
3855         }
3856 }
3857
3858 static void rtl_pll_power_up(struct rtl8169_private *tp)
3859 {
3860         switch (tp->mac_version) {
3861         case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_33:
3862         case RTL_GIGA_MAC_VER_37:
3863         case RTL_GIGA_MAC_VER_39:
3864         case RTL_GIGA_MAC_VER_43:
3865                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0x80);
3866                 break;
3867         case RTL_GIGA_MAC_VER_44:
3868         case RTL_GIGA_MAC_VER_45:
3869         case RTL_GIGA_MAC_VER_46:
3870         case RTL_GIGA_MAC_VER_47:
3871         case RTL_GIGA_MAC_VER_48:
3872         case RTL_GIGA_MAC_VER_50:
3873         case RTL_GIGA_MAC_VER_51:
3874                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0);
3875                 break;
3876         case RTL_GIGA_MAC_VER_40:
3877         case RTL_GIGA_MAC_VER_41:
3878         case RTL_GIGA_MAC_VER_49:
3879                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0);
3880                 rtl_eri_set_bits(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000);
3881                 break;
3882         default:
3883                 break;
3884         }
3885
3886         phy_resume(tp->phydev);
3887         /* give MAC/PHY some time to resume */
3888         msleep(20);
3889 }
3890
3891 static void rtl_init_rxcfg(struct rtl8169_private *tp)
3892 {
3893         switch (tp->mac_version) {
3894         case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
3895         case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
3896                 RTL_W32(tp, RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
3897                 break;
3898         case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
3899         case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36:
3900         case RTL_GIGA_MAC_VER_38:
3901                 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
3902                 break;
3903         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
3904                 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF);
3905                 break;
3906         default:
3907                 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_DMA_BURST);
3908                 break;
3909         }
3910 }
3911
3912 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
3913 {
3914         tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0;
3915 }
3916
3917 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
3918 {
3919         RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
3920         RTL_W8(tp, Config4, RTL_R8(tp, Config4) | Jumbo_En1);
3921         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_512B);
3922 }
3923
3924 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
3925 {
3926         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
3927         RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~Jumbo_En1);
3928         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
3929 }
3930
3931 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
3932 {
3933         RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
3934 }
3935
3936 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
3937 {
3938         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
3939 }
3940
3941 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
3942 {
3943         RTL_W8(tp, MaxTxPacketSize, 0x3f);
3944         RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
3945         RTL_W8(tp, Config4, RTL_R8(tp, Config4) | 0x01);
3946         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_512B);
3947 }
3948
3949 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
3950 {
3951         RTL_W8(tp, MaxTxPacketSize, 0x0c);
3952         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
3953         RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~0x01);
3954         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
3955 }
3956
3957 static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp)
3958 {
3959         rtl_tx_performance_tweak(tp,
3960                 PCI_EXP_DEVCTL_READRQ_512B | PCI_EXP_DEVCTL_NOSNOOP_EN);
3961 }
3962
3963 static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp)
3964 {
3965         rtl_tx_performance_tweak(tp,
3966                 PCI_EXP_DEVCTL_READRQ_4096B | PCI_EXP_DEVCTL_NOSNOOP_EN);
3967 }
3968
3969 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
3970 {
3971         r8168b_0_hw_jumbo_enable(tp);
3972
3973         RTL_W8(tp, Config4, RTL_R8(tp, Config4) | (1 << 0));
3974 }
3975
3976 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
3977 {
3978         r8168b_0_hw_jumbo_disable(tp);
3979
3980         RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0));
3981 }
3982
3983 static void rtl_hw_jumbo_enable(struct rtl8169_private *tp)
3984 {
3985         rtl_unlock_config_regs(tp);
3986         switch (tp->mac_version) {
3987         case RTL_GIGA_MAC_VER_11:
3988                 r8168b_0_hw_jumbo_enable(tp);
3989                 break;
3990         case RTL_GIGA_MAC_VER_12:
3991         case RTL_GIGA_MAC_VER_17:
3992                 r8168b_1_hw_jumbo_enable(tp);
3993                 break;
3994         case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_26:
3995                 r8168c_hw_jumbo_enable(tp);
3996                 break;
3997         case RTL_GIGA_MAC_VER_27 ... RTL_GIGA_MAC_VER_28:
3998                 r8168dp_hw_jumbo_enable(tp);
3999                 break;
4000         case RTL_GIGA_MAC_VER_31 ... RTL_GIGA_MAC_VER_34:
4001                 r8168e_hw_jumbo_enable(tp);
4002                 break;
4003         default:
4004                 break;
4005         }
4006         rtl_lock_config_regs(tp);
4007 }
4008
4009 static void rtl_hw_jumbo_disable(struct rtl8169_private *tp)
4010 {
4011         rtl_unlock_config_regs(tp);
4012         switch (tp->mac_version) {
4013         case RTL_GIGA_MAC_VER_11:
4014                 r8168b_0_hw_jumbo_disable(tp);
4015                 break;
4016         case RTL_GIGA_MAC_VER_12:
4017         case RTL_GIGA_MAC_VER_17:
4018                 r8168b_1_hw_jumbo_disable(tp);
4019                 break;
4020         case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_26:
4021                 r8168c_hw_jumbo_disable(tp);
4022                 break;
4023         case RTL_GIGA_MAC_VER_27 ... RTL_GIGA_MAC_VER_28:
4024                 r8168dp_hw_jumbo_disable(tp);
4025                 break;
4026         case RTL_GIGA_MAC_VER_31 ... RTL_GIGA_MAC_VER_34:
4027                 r8168e_hw_jumbo_disable(tp);
4028                 break;
4029         default:
4030                 break;
4031         }
4032         rtl_lock_config_regs(tp);
4033 }
4034
4035 DECLARE_RTL_COND(rtl_chipcmd_cond)
4036 {
4037         return RTL_R8(tp, ChipCmd) & CmdReset;
4038 }
4039
4040 static void rtl_hw_reset(struct rtl8169_private *tp)
4041 {
4042         RTL_W8(tp, ChipCmd, CmdReset);
4043
4044         rtl_udelay_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100);
4045 }
4046
4047 static void rtl_request_firmware(struct rtl8169_private *tp)
4048 {
4049         struct rtl_fw *rtl_fw;
4050
4051         /* firmware loaded already or no firmware available */
4052         if (tp->rtl_fw || !tp->fw_name)
4053                 return;
4054
4055         rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
4056         if (!rtl_fw) {
4057                 netif_warn(tp, ifup, tp->dev, "Unable to load firmware, out of memory\n");
4058                 return;
4059         }
4060
4061         rtl_fw->phy_write = rtl_writephy;
4062         rtl_fw->phy_read = rtl_readphy;
4063         rtl_fw->mac_mcu_write = mac_mcu_write;
4064         rtl_fw->mac_mcu_read = mac_mcu_read;
4065         rtl_fw->fw_name = tp->fw_name;
4066         rtl_fw->dev = tp_to_dev(tp);
4067
4068         if (rtl_fw_request_firmware(rtl_fw))
4069                 kfree(rtl_fw);
4070         else
4071                 tp->rtl_fw = rtl_fw;
4072 }
4073
4074 static void rtl_rx_close(struct rtl8169_private *tp)
4075 {
4076         RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
4077 }
4078
4079 DECLARE_RTL_COND(rtl_npq_cond)
4080 {
4081         return RTL_R8(tp, TxPoll) & NPQ;
4082 }
4083
4084 DECLARE_RTL_COND(rtl_txcfg_empty_cond)
4085 {
4086         return RTL_R32(tp, TxConfig) & TXCFG_EMPTY;
4087 }
4088
4089 static void rtl8169_hw_reset(struct rtl8169_private *tp)
4090 {
4091         /* Disable interrupts */
4092         rtl8169_irq_mask_and_ack(tp);
4093
4094         rtl_rx_close(tp);
4095
4096         switch (tp->mac_version) {
4097         case RTL_GIGA_MAC_VER_27:
4098         case RTL_GIGA_MAC_VER_28:
4099         case RTL_GIGA_MAC_VER_31:
4100                 rtl_udelay_loop_wait_low(tp, &rtl_npq_cond, 20, 42*42);
4101                 break;
4102         case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
4103         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
4104                 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
4105                 rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);
4106                 break;
4107         default:
4108                 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
4109                 udelay(100);
4110                 break;
4111         }
4112
4113         rtl_hw_reset(tp);
4114 }
4115
4116 static void rtl_set_tx_config_registers(struct rtl8169_private *tp)
4117 {
4118         u32 val = TX_DMA_BURST << TxDMAShift |
4119                   InterFrameGap << TxInterFrameGapShift;
4120
4121         if (rtl_is_8168evl_up(tp))
4122                 val |= TXCFG_AUTO_FIFO;
4123
4124         RTL_W32(tp, TxConfig, val);
4125 }
4126
4127 static void rtl_set_rx_max_size(struct rtl8169_private *tp)
4128 {
4129         /* Low hurts. Let's disable the filtering. */
4130         RTL_W16(tp, RxMaxSize, R8169_RX_BUF_SIZE + 1);
4131 }
4132
4133 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp)
4134 {
4135         /*
4136          * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
4137          * register to be written before TxDescAddrLow to work.
4138          * Switching from MMIO to I/O access fixes the issue as well.
4139          */
4140         RTL_W32(tp, TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
4141         RTL_W32(tp, TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
4142         RTL_W32(tp, RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
4143         RTL_W32(tp, RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
4144 }
4145
4146 static void rtl8169_set_magic_reg(struct rtl8169_private *tp, unsigned mac_version)
4147 {
4148         u32 val;
4149
4150         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
4151                 val = 0x000fff00;
4152         else if (tp->mac_version == RTL_GIGA_MAC_VER_06)
4153                 val = 0x00ffff00;
4154         else
4155                 return;
4156
4157         if (RTL_R8(tp, Config2) & PCI_Clock_66MHz)
4158                 val |= 0xff;
4159
4160         RTL_W32(tp, 0x7c, val);
4161 }
4162
4163 static void rtl_set_rx_mode(struct net_device *dev)
4164 {
4165         u32 rx_mode = AcceptBroadcast | AcceptMyPhys | AcceptMulticast;
4166         /* Multicast hash filter */
4167         u32 mc_filter[2] = { 0xffffffff, 0xffffffff };
4168         struct rtl8169_private *tp = netdev_priv(dev);
4169         u32 tmp;
4170
4171         if (dev->flags & IFF_PROMISC) {
4172                 /* Unconditionally log net taps. */
4173                 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
4174                 rx_mode |= AcceptAllPhys;
4175         } else if (netdev_mc_count(dev) > MC_FILTER_LIMIT ||
4176                    dev->flags & IFF_ALLMULTI ||
4177                    tp->mac_version == RTL_GIGA_MAC_VER_35) {
4178                 /* accept all multicasts */
4179         } else if (netdev_mc_empty(dev)) {
4180                 rx_mode &= ~AcceptMulticast;
4181         } else {
4182                 struct netdev_hw_addr *ha;
4183
4184                 mc_filter[1] = mc_filter[0] = 0;
4185                 netdev_for_each_mc_addr(ha, dev) {
4186                         u32 bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
4187                         mc_filter[bit_nr >> 5] |= BIT(bit_nr & 31);
4188                 }
4189
4190                 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
4191                         tmp = mc_filter[0];
4192                         mc_filter[0] = swab32(mc_filter[1]);
4193                         mc_filter[1] = swab32(tmp);
4194                 }
4195         }
4196
4197         if (dev->features & NETIF_F_RXALL)
4198                 rx_mode |= (AcceptErr | AcceptRunt);
4199
4200         RTL_W32(tp, MAR0 + 4, mc_filter[1]);
4201         RTL_W32(tp, MAR0 + 0, mc_filter[0]);
4202
4203         tmp = RTL_R32(tp, RxConfig);
4204         RTL_W32(tp, RxConfig, (tmp & ~RX_CONFIG_ACCEPT_MASK) | rx_mode);
4205 }
4206
4207 DECLARE_RTL_COND(rtl_csiar_cond)
4208 {
4209         return RTL_R32(tp, CSIAR) & CSIAR_FLAG;
4210 }
4211
4212 static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)
4213 {
4214         u32 func = PCI_FUNC(tp->pci_dev->devfn);
4215
4216         RTL_W32(tp, CSIDR, value);
4217         RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
4218                 CSIAR_BYTE_ENABLE | func << 16);
4219
4220         rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
4221 }
4222
4223 static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)
4224 {
4225         u32 func = PCI_FUNC(tp->pci_dev->devfn);
4226
4227         RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) | func << 16 |
4228                 CSIAR_BYTE_ENABLE);
4229
4230         return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
4231                 RTL_R32(tp, CSIDR) : ~0;
4232 }
4233
4234 static void rtl_csi_access_enable(struct rtl8169_private *tp, u8 val)
4235 {
4236         struct pci_dev *pdev = tp->pci_dev;
4237         u32 csi;
4238
4239         /* According to Realtek the value at config space address 0x070f
4240          * controls the L0s/L1 entrance latency. We try standard ECAM access
4241          * first and if it fails fall back to CSI.
4242          */
4243         if (pdev->cfg_size > 0x070f &&
4244             pci_write_config_byte(pdev, 0x070f, val) == PCIBIOS_SUCCESSFUL)
4245                 return;
4246
4247         netdev_notice_once(tp->dev,
4248                 "No native access to PCI extended config space, falling back to CSI\n");
4249         csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff;
4250         rtl_csi_write(tp, 0x070c, csi | val << 24);
4251 }
4252
4253 static void rtl_set_def_aspm_entry_latency(struct rtl8169_private *tp)
4254 {
4255         rtl_csi_access_enable(tp, 0x27);
4256 }
4257
4258 struct ephy_info {
4259         unsigned int offset;
4260         u16 mask;
4261         u16 bits;
4262 };
4263
4264 static void __rtl_ephy_init(struct rtl8169_private *tp,
4265                             const struct ephy_info *e, int len)
4266 {
4267         u16 w;
4268
4269         while (len-- > 0) {
4270                 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits;
4271                 rtl_ephy_write(tp, e->offset, w);
4272                 e++;
4273         }
4274 }
4275
4276 #define rtl_ephy_init(tp, a) __rtl_ephy_init(tp, a, ARRAY_SIZE(a))
4277
4278 static void rtl_disable_clock_request(struct rtl8169_private *tp)
4279 {
4280         pcie_capability_clear_word(tp->pci_dev, PCI_EXP_LNKCTL,
4281                                    PCI_EXP_LNKCTL_CLKREQ_EN);
4282 }
4283
4284 static void rtl_enable_clock_request(struct rtl8169_private *tp)
4285 {
4286         pcie_capability_set_word(tp->pci_dev, PCI_EXP_LNKCTL,
4287                                  PCI_EXP_LNKCTL_CLKREQ_EN);
4288 }
4289
4290 static void rtl_pcie_state_l2l3_disable(struct rtl8169_private *tp)
4291 {
4292         /* work around an issue when PCI reset occurs during L2/L3 state */
4293         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Rdy_to_L23);
4294 }
4295
4296 static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable)
4297 {
4298         /* Don't enable ASPM in the chip if OS can't control ASPM */
4299         if (enable && tp->aspm_manageable) {
4300                 RTL_W8(tp, Config5, RTL_R8(tp, Config5) | ASPM_en);
4301                 RTL_W8(tp, Config2, RTL_R8(tp, Config2) | ClkReqEn);
4302         } else {
4303                 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
4304                 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
4305         }
4306
4307         udelay(10);
4308 }
4309
4310 static void rtl_set_fifo_size(struct rtl8169_private *tp, u16 rx_stat,
4311                               u16 tx_stat, u16 rx_dyn, u16 tx_dyn)
4312 {
4313         /* Usage of dynamic vs. static FIFO is controlled by bit
4314          * TXCFG_AUTO_FIFO. Exact meaning of FIFO values isn't known.
4315          */
4316         rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, (rx_stat << 16) | rx_dyn);
4317         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, (tx_stat << 16) | tx_dyn);
4318 }
4319
4320 static void rtl8168g_set_pause_thresholds(struct rtl8169_private *tp,
4321                                           u8 low, u8 high)
4322 {
4323         /* FIFO thresholds for pause flow control */
4324         rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, low);
4325         rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, high);
4326 }
4327
4328 static void rtl_hw_start_8168bb(struct rtl8169_private *tp)
4329 {
4330         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4331
4332         if (tp->dev->mtu <= ETH_DATA_LEN) {
4333                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B |
4334                                          PCI_EXP_DEVCTL_NOSNOOP_EN);
4335         }
4336 }
4337
4338 static void rtl_hw_start_8168bef(struct rtl8169_private *tp)
4339 {
4340         rtl_hw_start_8168bb(tp);
4341
4342         RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0));
4343 }
4344
4345 static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)
4346 {
4347         RTL_W8(tp, Config1, RTL_R8(tp, Config1) | Speed_down);
4348
4349         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4350
4351         if (tp->dev->mtu <= ETH_DATA_LEN)
4352                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4353
4354         rtl_disable_clock_request(tp);
4355 }
4356
4357 static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp)
4358 {
4359         static const struct ephy_info e_info_8168cp[] = {
4360                 { 0x01, 0,      0x0001 },
4361                 { 0x02, 0x0800, 0x1000 },
4362                 { 0x03, 0,      0x0042 },
4363                 { 0x06, 0x0080, 0x0000 },
4364                 { 0x07, 0,      0x2000 }
4365         };
4366
4367         rtl_set_def_aspm_entry_latency(tp);
4368
4369         rtl_ephy_init(tp, e_info_8168cp);
4370
4371         __rtl_hw_start_8168cp(tp);
4372 }
4373
4374 static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)
4375 {
4376         rtl_set_def_aspm_entry_latency(tp);
4377
4378         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4379
4380         if (tp->dev->mtu <= ETH_DATA_LEN)
4381                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4382 }
4383
4384 static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)
4385 {
4386         rtl_set_def_aspm_entry_latency(tp);
4387
4388         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4389
4390         /* Magic. */
4391         RTL_W8(tp, DBG_REG, 0x20);
4392
4393         if (tp->dev->mtu <= ETH_DATA_LEN)
4394                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4395 }
4396
4397 static void rtl_hw_start_8168c_1(struct rtl8169_private *tp)
4398 {
4399         static const struct ephy_info e_info_8168c_1[] = {
4400                 { 0x02, 0x0800, 0x1000 },
4401                 { 0x03, 0,      0x0002 },
4402                 { 0x06, 0x0080, 0x0000 }
4403         };
4404
4405         rtl_set_def_aspm_entry_latency(tp);
4406
4407         RTL_W8(tp, DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
4408
4409         rtl_ephy_init(tp, e_info_8168c_1);
4410
4411         __rtl_hw_start_8168cp(tp);
4412 }
4413
4414 static void rtl_hw_start_8168c_2(struct rtl8169_private *tp)
4415 {
4416         static const struct ephy_info e_info_8168c_2[] = {
4417                 { 0x01, 0,      0x0001 },
4418                 { 0x03, 0x0400, 0x0220 }
4419         };
4420
4421         rtl_set_def_aspm_entry_latency(tp);
4422
4423         rtl_ephy_init(tp, e_info_8168c_2);
4424
4425         __rtl_hw_start_8168cp(tp);
4426 }
4427
4428 static void rtl_hw_start_8168c_3(struct rtl8169_private *tp)
4429 {
4430         rtl_hw_start_8168c_2(tp);
4431 }
4432
4433 static void rtl_hw_start_8168c_4(struct rtl8169_private *tp)
4434 {
4435         rtl_set_def_aspm_entry_latency(tp);
4436
4437         __rtl_hw_start_8168cp(tp);
4438 }
4439
4440 static void rtl_hw_start_8168d(struct rtl8169_private *tp)
4441 {
4442         rtl_set_def_aspm_entry_latency(tp);
4443
4444         rtl_disable_clock_request(tp);
4445
4446         if (tp->dev->mtu <= ETH_DATA_LEN)
4447                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4448 }
4449
4450 static void rtl_hw_start_8168dp(struct rtl8169_private *tp)
4451 {
4452         rtl_set_def_aspm_entry_latency(tp);
4453
4454         if (tp->dev->mtu <= ETH_DATA_LEN)
4455                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4456
4457         rtl_disable_clock_request(tp);
4458 }
4459
4460 static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
4461 {
4462         static const struct ephy_info e_info_8168d_4[] = {
4463                 { 0x0b, 0x0000, 0x0048 },
4464                 { 0x19, 0x0020, 0x0050 },
4465                 { 0x0c, 0x0100, 0x0020 }
4466         };
4467
4468         rtl_set_def_aspm_entry_latency(tp);
4469
4470         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4471
4472         rtl_ephy_init(tp, e_info_8168d_4);
4473
4474         rtl_enable_clock_request(tp);
4475 }
4476
4477 static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)
4478 {
4479         static const struct ephy_info e_info_8168e_1[] = {
4480                 { 0x00, 0x0200, 0x0100 },
4481                 { 0x00, 0x0000, 0x0004 },
4482                 { 0x06, 0x0002, 0x0001 },
4483                 { 0x06, 0x0000, 0x0030 },
4484                 { 0x07, 0x0000, 0x2000 },
4485                 { 0x00, 0x0000, 0x0020 },
4486                 { 0x03, 0x5800, 0x2000 },
4487                 { 0x03, 0x0000, 0x0001 },
4488                 { 0x01, 0x0800, 0x1000 },
4489                 { 0x07, 0x0000, 0x4000 },
4490                 { 0x1e, 0x0000, 0x2000 },
4491                 { 0x19, 0xffff, 0xfe6c },
4492                 { 0x0a, 0x0000, 0x0040 }
4493         };
4494
4495         rtl_set_def_aspm_entry_latency(tp);
4496
4497         rtl_ephy_init(tp, e_info_8168e_1);
4498
4499         if (tp->dev->mtu <= ETH_DATA_LEN)
4500                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4501
4502         rtl_disable_clock_request(tp);
4503
4504         /* Reset tx FIFO pointer */
4505         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | TXPLA_RST);
4506         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~TXPLA_RST);
4507
4508         RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
4509 }
4510
4511 static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
4512 {
4513         static const struct ephy_info e_info_8168e_2[] = {
4514                 { 0x09, 0x0000, 0x0080 },
4515                 { 0x19, 0x0000, 0x0224 }
4516         };
4517
4518         rtl_set_def_aspm_entry_latency(tp);
4519
4520         rtl_ephy_init(tp, e_info_8168e_2);
4521
4522         if (tp->dev->mtu <= ETH_DATA_LEN)
4523                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4524
4525         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
4526         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
4527         rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06);
4528         rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050);
4529         rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060);
4530         rtl_eri_set_bits(tp, 0x1b0, ERIAR_MASK_0001, BIT(4));
4531         rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00);
4532
4533         rtl_disable_clock_request(tp);
4534
4535         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
4536
4537         rtl8168_config_eee_mac(tp);
4538
4539         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
4540         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
4541         RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
4542
4543         rtl_hw_aspm_clkreq_enable(tp, true);
4544 }
4545
4546 static void rtl_hw_start_8168f(struct rtl8169_private *tp)
4547 {
4548         rtl_set_def_aspm_entry_latency(tp);
4549
4550         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4551
4552         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
4553         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
4554         rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06);
4555         rtl_reset_packet_filter(tp);
4556         rtl_eri_set_bits(tp, 0x1b0, ERIAR_MASK_0001, BIT(4));
4557         rtl_eri_set_bits(tp, 0x1d0, ERIAR_MASK_0001, BIT(4));
4558         rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050);
4559         rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060);
4560
4561         rtl_disable_clock_request(tp);
4562
4563         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
4564         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
4565         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
4566         RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
4567
4568         rtl8168_config_eee_mac(tp);
4569 }
4570
4571 static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
4572 {
4573         static const struct ephy_info e_info_8168f_1[] = {
4574                 { 0x06, 0x00c0, 0x0020 },
4575                 { 0x08, 0x0001, 0x0002 },
4576                 { 0x09, 0x0000, 0x0080 },
4577                 { 0x19, 0x0000, 0x0224 }
4578         };
4579
4580         rtl_hw_start_8168f(tp);
4581
4582         rtl_ephy_init(tp, e_info_8168f_1);
4583
4584         rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00);
4585 }
4586
4587 static void rtl_hw_start_8411(struct rtl8169_private *tp)
4588 {
4589         static const struct ephy_info e_info_8168f_1[] = {
4590                 { 0x06, 0x00c0, 0x0020 },
4591                 { 0x0f, 0xffff, 0x5200 },
4592                 { 0x1e, 0x0000, 0x4000 },
4593                 { 0x19, 0x0000, 0x0224 }
4594         };
4595
4596         rtl_hw_start_8168f(tp);
4597         rtl_pcie_state_l2l3_disable(tp);
4598
4599         rtl_ephy_init(tp, e_info_8168f_1);
4600
4601         rtl_eri_set_bits(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00);
4602 }
4603
4604 static void rtl_hw_start_8168g(struct rtl8169_private *tp)
4605 {
4606         rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
4607         rtl8168g_set_pause_thresholds(tp, 0x38, 0x48);
4608
4609         rtl_set_def_aspm_entry_latency(tp);
4610
4611         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4612
4613         rtl_reset_packet_filter(tp);
4614         rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f);
4615
4616         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
4617
4618         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
4619         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
4620
4621         rtl8168_config_eee_mac(tp);
4622
4623         rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06);
4624         rtl_eri_clear_bits(tp, 0x1b0, ERIAR_MASK_0011, BIT(12));
4625
4626         rtl_pcie_state_l2l3_disable(tp);
4627 }
4628
4629 static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
4630 {
4631         static const struct ephy_info e_info_8168g_1[] = {
4632                 { 0x00, 0x0000, 0x0008 },
4633                 { 0x0c, 0x37d0, 0x0820 },
4634                 { 0x1e, 0x0000, 0x0001 },
4635                 { 0x19, 0x8000, 0x0000 }
4636         };
4637
4638         rtl_hw_start_8168g(tp);
4639
4640         /* disable aspm and clock request before access ephy */
4641         rtl_hw_aspm_clkreq_enable(tp, false);
4642         rtl_ephy_init(tp, e_info_8168g_1);
4643         rtl_hw_aspm_clkreq_enable(tp, true);
4644 }
4645
4646 static void rtl_hw_start_8168g_2(struct rtl8169_private *tp)
4647 {
4648         static const struct ephy_info e_info_8168g_2[] = {
4649                 { 0x00, 0x0000, 0x0008 },
4650                 { 0x0c, 0x3df0, 0x0200 },
4651                 { 0x19, 0xffff, 0xfc00 },
4652                 { 0x1e, 0xffff, 0x20eb }
4653         };
4654
4655         rtl_hw_start_8168g(tp);
4656
4657         /* disable aspm and clock request before access ephy */
4658         RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
4659         RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
4660         rtl_ephy_init(tp, e_info_8168g_2);
4661 }
4662
4663 static void rtl_hw_start_8411_2(struct rtl8169_private *tp)
4664 {
4665         static const struct ephy_info e_info_8411_2[] = {
4666                 { 0x00, 0x0000, 0x0008 },
4667                 { 0x0c, 0x3df0, 0x0200 },
4668                 { 0x0f, 0xffff, 0x5200 },
4669                 { 0x19, 0x0020, 0x0000 },
4670                 { 0x1e, 0x0000, 0x2000 }
4671         };
4672
4673         rtl_hw_start_8168g(tp);
4674
4675         /* disable aspm and clock request before access ephy */
4676         rtl_hw_aspm_clkreq_enable(tp, false);
4677         rtl_ephy_init(tp, e_info_8411_2);
4678
4679         /* The following Realtek-provided magic fixes an issue with the RX unit
4680          * getting confused after the PHY having been powered-down.
4681          */
4682         r8168_mac_ocp_write(tp, 0xFC28, 0x0000);
4683         r8168_mac_ocp_write(tp, 0xFC2A, 0x0000);
4684         r8168_mac_ocp_write(tp, 0xFC2C, 0x0000);
4685         r8168_mac_ocp_write(tp, 0xFC2E, 0x0000);
4686         r8168_mac_ocp_write(tp, 0xFC30, 0x0000);
4687         r8168_mac_ocp_write(tp, 0xFC32, 0x0000);
4688         r8168_mac_ocp_write(tp, 0xFC34, 0x0000);
4689         r8168_mac_ocp_write(tp, 0xFC36, 0x0000);
4690         mdelay(3);
4691         r8168_mac_ocp_write(tp, 0xFC26, 0x0000);
4692
4693         r8168_mac_ocp_write(tp, 0xF800, 0xE008);
4694         r8168_mac_ocp_write(tp, 0xF802, 0xE00A);
4695         r8168_mac_ocp_write(tp, 0xF804, 0xE00C);
4696         r8168_mac_ocp_write(tp, 0xF806, 0xE00E);
4697         r8168_mac_ocp_write(tp, 0xF808, 0xE027);
4698         r8168_mac_ocp_write(tp, 0xF80A, 0xE04F);
4699         r8168_mac_ocp_write(tp, 0xF80C, 0xE05E);
4700         r8168_mac_ocp_write(tp, 0xF80E, 0xE065);
4701         r8168_mac_ocp_write(tp, 0xF810, 0xC602);
4702         r8168_mac_ocp_write(tp, 0xF812, 0xBE00);
4703         r8168_mac_ocp_write(tp, 0xF814, 0x0000);
4704         r8168_mac_ocp_write(tp, 0xF816, 0xC502);
4705         r8168_mac_ocp_write(tp, 0xF818, 0xBD00);
4706         r8168_mac_ocp_write(tp, 0xF81A, 0x074C);
4707         r8168_mac_ocp_write(tp, 0xF81C, 0xC302);
4708         r8168_mac_ocp_write(tp, 0xF81E, 0xBB00);
4709         r8168_mac_ocp_write(tp, 0xF820, 0x080A);
4710         r8168_mac_ocp_write(tp, 0xF822, 0x6420);
4711         r8168_mac_ocp_write(tp, 0xF824, 0x48C2);
4712         r8168_mac_ocp_write(tp, 0xF826, 0x8C20);
4713         r8168_mac_ocp_write(tp, 0xF828, 0xC516);
4714         r8168_mac_ocp_write(tp, 0xF82A, 0x64A4);
4715         r8168_mac_ocp_write(tp, 0xF82C, 0x49C0);
4716         r8168_mac_ocp_write(tp, 0xF82E, 0xF009);
4717         r8168_mac_ocp_write(tp, 0xF830, 0x74A2);
4718         r8168_mac_ocp_write(tp, 0xF832, 0x8CA5);
4719         r8168_mac_ocp_write(tp, 0xF834, 0x74A0);
4720         r8168_mac_ocp_write(tp, 0xF836, 0xC50E);
4721         r8168_mac_ocp_write(tp, 0xF838, 0x9CA2);
4722         r8168_mac_ocp_write(tp, 0xF83A, 0x1C11);
4723         r8168_mac_ocp_write(tp, 0xF83C, 0x9CA0);
4724         r8168_mac_ocp_write(tp, 0xF83E, 0xE006);
4725         r8168_mac_ocp_write(tp, 0xF840, 0x74F8);
4726         r8168_mac_ocp_write(tp, 0xF842, 0x48C4);
4727         r8168_mac_ocp_write(tp, 0xF844, 0x8CF8);
4728         r8168_mac_ocp_write(tp, 0xF846, 0xC404);
4729         r8168_mac_ocp_write(tp, 0xF848, 0xBC00);
4730         r8168_mac_ocp_write(tp, 0xF84A, 0xC403);
4731         r8168_mac_ocp_write(tp, 0xF84C, 0xBC00);
4732         r8168_mac_ocp_write(tp, 0xF84E, 0x0BF2);
4733         r8168_mac_ocp_write(tp, 0xF850, 0x0C0A);
4734         r8168_mac_ocp_write(tp, 0xF852, 0xE434);
4735         r8168_mac_ocp_write(tp, 0xF854, 0xD3C0);
4736         r8168_mac_ocp_write(tp, 0xF856, 0x49D9);
4737         r8168_mac_ocp_write(tp, 0xF858, 0xF01F);
4738         r8168_mac_ocp_write(tp, 0xF85A, 0xC526);
4739         r8168_mac_ocp_write(tp, 0xF85C, 0x64A5);
4740         r8168_mac_ocp_write(tp, 0xF85E, 0x1400);
4741         r8168_mac_ocp_write(tp, 0xF860, 0xF007);
4742         r8168_mac_ocp_write(tp, 0xF862, 0x0C01);
4743         r8168_mac_ocp_write(tp, 0xF864, 0x8CA5);
4744         r8168_mac_ocp_write(tp, 0xF866, 0x1C15);
4745         r8168_mac_ocp_write(tp, 0xF868, 0xC51B);
4746         r8168_mac_ocp_write(tp, 0xF86A, 0x9CA0);
4747         r8168_mac_ocp_write(tp, 0xF86C, 0xE013);
4748         r8168_mac_ocp_write(tp, 0xF86E, 0xC519);
4749         r8168_mac_ocp_write(tp, 0xF870, 0x74A0);
4750         r8168_mac_ocp_write(tp, 0xF872, 0x48C4);
4751         r8168_mac_ocp_write(tp, 0xF874, 0x8CA0);
4752         r8168_mac_ocp_write(tp, 0xF876, 0xC516);
4753         r8168_mac_ocp_write(tp, 0xF878, 0x74A4);
4754         r8168_mac_ocp_write(tp, 0xF87A, 0x48C8);
4755         r8168_mac_ocp_write(tp, 0xF87C, 0x48CA);
4756         r8168_mac_ocp_write(tp, 0xF87E, 0x9CA4);
4757         r8168_mac_ocp_write(tp, 0xF880, 0xC512);
4758         r8168_mac_ocp_write(tp, 0xF882, 0x1B00);
4759         r8168_mac_ocp_write(tp, 0xF884, 0x9BA0);
4760         r8168_mac_ocp_write(tp, 0xF886, 0x1B1C);
4761         r8168_mac_ocp_write(tp, 0xF888, 0x483F);
4762         r8168_mac_ocp_write(tp, 0xF88A, 0x9BA2);
4763         r8168_mac_ocp_write(tp, 0xF88C, 0x1B04);
4764         r8168_mac_ocp_write(tp, 0xF88E, 0xC508);
4765         r8168_mac_ocp_write(tp, 0xF890, 0x9BA0);
4766         r8168_mac_ocp_write(tp, 0xF892, 0xC505);
4767         r8168_mac_ocp_write(tp, 0xF894, 0xBD00);
4768         r8168_mac_ocp_write(tp, 0xF896, 0xC502);
4769         r8168_mac_ocp_write(tp, 0xF898, 0xBD00);
4770         r8168_mac_ocp_write(tp, 0xF89A, 0x0300);
4771         r8168_mac_ocp_write(tp, 0xF89C, 0x051E);
4772         r8168_mac_ocp_write(tp, 0xF89E, 0xE434);
4773         r8168_mac_ocp_write(tp, 0xF8A0, 0xE018);
4774         r8168_mac_ocp_write(tp, 0xF8A2, 0xE092);
4775         r8168_mac_ocp_write(tp, 0xF8A4, 0xDE20);
4776         r8168_mac_ocp_write(tp, 0xF8A6, 0xD3C0);
4777         r8168_mac_ocp_write(tp, 0xF8A8, 0xC50F);
4778         r8168_mac_ocp_write(tp, 0xF8AA, 0x76A4);
4779         r8168_mac_ocp_write(tp, 0xF8AC, 0x49E3);
4780         r8168_mac_ocp_write(tp, 0xF8AE, 0xF007);
4781         r8168_mac_ocp_write(tp, 0xF8B0, 0x49C0);
4782         r8168_mac_ocp_write(tp, 0xF8B2, 0xF103);
4783         r8168_mac_ocp_write(tp, 0xF8B4, 0xC607);
4784         r8168_mac_ocp_write(tp, 0xF8B6, 0xBE00);
4785         r8168_mac_ocp_write(tp, 0xF8B8, 0xC606);
4786         r8168_mac_ocp_write(tp, 0xF8BA, 0xBE00);
4787         r8168_mac_ocp_write(tp, 0xF8BC, 0xC602);
4788         r8168_mac_ocp_write(tp, 0xF8BE, 0xBE00);
4789         r8168_mac_ocp_write(tp, 0xF8C0, 0x0C4C);
4790         r8168_mac_ocp_write(tp, 0xF8C2, 0x0C28);
4791         r8168_mac_ocp_write(tp, 0xF8C4, 0x0C2C);
4792         r8168_mac_ocp_write(tp, 0xF8C6, 0xDC00);
4793         r8168_mac_ocp_write(tp, 0xF8C8, 0xC707);
4794         r8168_mac_ocp_write(tp, 0xF8CA, 0x1D00);
4795         r8168_mac_ocp_write(tp, 0xF8CC, 0x8DE2);
4796         r8168_mac_ocp_write(tp, 0xF8CE, 0x48C1);
4797         r8168_mac_ocp_write(tp, 0xF8D0, 0xC502);
4798         r8168_mac_ocp_write(tp, 0xF8D2, 0xBD00);
4799         r8168_mac_ocp_write(tp, 0xF8D4, 0x00AA);
4800         r8168_mac_ocp_write(tp, 0xF8D6, 0xE0C0);
4801         r8168_mac_ocp_write(tp, 0xF8D8, 0xC502);
4802         r8168_mac_ocp_write(tp, 0xF8DA, 0xBD00);
4803         r8168_mac_ocp_write(tp, 0xF8DC, 0x0132);
4804
4805         r8168_mac_ocp_write(tp, 0xFC26, 0x8000);
4806
4807         r8168_mac_ocp_write(tp, 0xFC2A, 0x0743);
4808         r8168_mac_ocp_write(tp, 0xFC2C, 0x0801);
4809         r8168_mac_ocp_write(tp, 0xFC2E, 0x0BE9);
4810         r8168_mac_ocp_write(tp, 0xFC30, 0x02FD);
4811         r8168_mac_ocp_write(tp, 0xFC32, 0x0C25);
4812         r8168_mac_ocp_write(tp, 0xFC34, 0x00A9);
4813         r8168_mac_ocp_write(tp, 0xFC36, 0x012D);
4814
4815         rtl_hw_aspm_clkreq_enable(tp, true);
4816 }
4817
4818 static void rtl_hw_start_8168h_1(struct rtl8169_private *tp)
4819 {
4820         static const struct ephy_info e_info_8168h_1[] = {
4821                 { 0x1e, 0x0800, 0x0001 },
4822                 { 0x1d, 0x0000, 0x0800 },
4823                 { 0x05, 0xffff, 0x2089 },
4824                 { 0x06, 0xffff, 0x5881 },
4825                 { 0x04, 0xffff, 0x154a },
4826                 { 0x01, 0xffff, 0x068b }
4827         };
4828         int rg_saw_cnt;
4829
4830         /* disable aspm and clock request before access ephy */
4831         rtl_hw_aspm_clkreq_enable(tp, false);
4832         rtl_ephy_init(tp, e_info_8168h_1);
4833
4834         rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
4835         rtl8168g_set_pause_thresholds(tp, 0x38, 0x48);
4836
4837         rtl_set_def_aspm_entry_latency(tp);
4838
4839         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4840
4841         rtl_reset_packet_filter(tp);
4842
4843         rtl_eri_set_bits(tp, 0xdc, ERIAR_MASK_1111, BIT(4));
4844
4845         rtl_eri_set_bits(tp, 0xd4, ERIAR_MASK_1111, 0x1f00);
4846
4847         rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);
4848
4849         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
4850
4851         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
4852         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
4853
4854         rtl8168_config_eee_mac(tp);
4855
4856         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
4857         RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
4858
4859         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
4860
4861         rtl_eri_clear_bits(tp, 0x1b0, ERIAR_MASK_0011, BIT(12));
4862
4863         rtl_pcie_state_l2l3_disable(tp);
4864
4865         rtl_writephy(tp, 0x1f, 0x0c42);
4866         rg_saw_cnt = (rtl_readphy(tp, 0x13) & 0x3fff);
4867         rtl_writephy(tp, 0x1f, 0x0000);
4868         if (rg_saw_cnt > 0) {
4869                 u16 sw_cnt_1ms_ini;
4870
4871                 sw_cnt_1ms_ini = 16000000/rg_saw_cnt;
4872                 sw_cnt_1ms_ini &= 0x0fff;
4873                 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini);
4874         }
4875
4876         r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070);
4877         r8168_mac_ocp_modify(tp, 0xe052, 0x6000, 0x8008);
4878         r8168_mac_ocp_modify(tp, 0xe0d6, 0x01ff, 0x017f);
4879         r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f);
4880
4881         r8168_mac_ocp_write(tp, 0xe63e, 0x0001);
4882         r8168_mac_ocp_write(tp, 0xe63e, 0x0000);
4883         r8168_mac_ocp_write(tp, 0xc094, 0x0000);
4884         r8168_mac_ocp_write(tp, 0xc09e, 0x0000);
4885
4886         rtl_hw_aspm_clkreq_enable(tp, true);
4887 }
4888
4889 static void rtl_hw_start_8168ep(struct rtl8169_private *tp)
4890 {
4891         rtl8168ep_stop_cmac(tp);
4892
4893         rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
4894         rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f);
4895
4896         rtl_set_def_aspm_entry_latency(tp);
4897
4898         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4899
4900         rtl_reset_packet_filter(tp);
4901
4902         rtl_eri_set_bits(tp, 0xd4, ERIAR_MASK_1111, 0x1f80);
4903
4904         rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);
4905
4906         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
4907
4908         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
4909         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
4910
4911         rtl8168_config_eee_mac(tp);
4912
4913         rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06);
4914
4915         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
4916
4917         rtl_pcie_state_l2l3_disable(tp);
4918 }
4919
4920 static void rtl_hw_start_8168ep_1(struct rtl8169_private *tp)
4921 {
4922         static const struct ephy_info e_info_8168ep_1[] = {
4923                 { 0x00, 0xffff, 0x10ab },
4924                 { 0x06, 0xffff, 0xf030 },
4925                 { 0x08, 0xffff, 0x2006 },
4926                 { 0x0d, 0xffff, 0x1666 },
4927                 { 0x0c, 0x3ff0, 0x0000 }
4928         };
4929
4930         /* disable aspm and clock request before access ephy */
4931         rtl_hw_aspm_clkreq_enable(tp, false);
4932         rtl_ephy_init(tp, e_info_8168ep_1);
4933
4934         rtl_hw_start_8168ep(tp);
4935
4936         rtl_hw_aspm_clkreq_enable(tp, true);
4937 }
4938
4939 static void rtl_hw_start_8168ep_2(struct rtl8169_private *tp)
4940 {
4941         static const struct ephy_info e_info_8168ep_2[] = {
4942                 { 0x00, 0xffff, 0x10a3 },
4943                 { 0x19, 0xffff, 0xfc00 },
4944                 { 0x1e, 0xffff, 0x20ea }
4945         };
4946
4947         /* disable aspm and clock request before access ephy */
4948         rtl_hw_aspm_clkreq_enable(tp, false);
4949         rtl_ephy_init(tp, e_info_8168ep_2);
4950
4951         rtl_hw_start_8168ep(tp);
4952
4953         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
4954         RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
4955
4956         rtl_hw_aspm_clkreq_enable(tp, true);
4957 }
4958
4959 static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp)
4960 {
4961         static const struct ephy_info e_info_8168ep_3[] = {
4962                 { 0x00, 0xffff, 0x10a3 },
4963                 { 0x19, 0xffff, 0x7c00 },
4964                 { 0x1e, 0xffff, 0x20eb },
4965                 { 0x0d, 0xffff, 0x1666 }
4966         };
4967
4968         /* disable aspm and clock request before access ephy */
4969         rtl_hw_aspm_clkreq_enable(tp, false);
4970         rtl_ephy_init(tp, e_info_8168ep_3);
4971
4972         rtl_hw_start_8168ep(tp);
4973
4974         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
4975         RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
4976
4977         r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x0271);
4978         r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000);
4979         r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080);
4980
4981         rtl_hw_aspm_clkreq_enable(tp, true);
4982 }
4983
4984 static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)
4985 {
4986         static const struct ephy_info e_info_8102e_1[] = {
4987                 { 0x01, 0, 0x6e65 },
4988                 { 0x02, 0, 0x091f },
4989                 { 0x03, 0, 0xc2f9 },
4990                 { 0x06, 0, 0xafb5 },
4991                 { 0x07, 0, 0x0e00 },
4992                 { 0x19, 0, 0xec80 },
4993                 { 0x01, 0, 0x2e65 },
4994                 { 0x01, 0, 0x6e65 }
4995         };
4996         u8 cfg1;
4997
4998         rtl_set_def_aspm_entry_latency(tp);
4999
5000         RTL_W8(tp, DBG_REG, FIX_NAK_1);
5001
5002         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5003
5004         RTL_W8(tp, Config1,
5005                LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
5006         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
5007
5008         cfg1 = RTL_R8(tp, Config1);
5009         if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
5010                 RTL_W8(tp, Config1, cfg1 & ~LEDS0);
5011
5012         rtl_ephy_init(tp, e_info_8102e_1);
5013 }
5014
5015 static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)
5016 {
5017         rtl_set_def_aspm_entry_latency(tp);
5018
5019         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5020
5021         RTL_W8(tp, Config1, MEMMAP | IOMAP | VPD | PMEnable);
5022         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
5023 }
5024
5025 static void rtl_hw_start_8102e_3(struct rtl8169_private *tp)
5026 {
5027         rtl_hw_start_8102e_2(tp);
5028
5029         rtl_ephy_write(tp, 0x03, 0xc2f9);
5030 }
5031
5032 static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)
5033 {
5034         static const struct ephy_info e_info_8105e_1[] = {
5035                 { 0x07, 0, 0x4000 },
5036                 { 0x19, 0, 0x0200 },
5037                 { 0x19, 0, 0x0020 },
5038                 { 0x1e, 0, 0x2000 },
5039                 { 0x03, 0, 0x0001 },
5040                 { 0x19, 0, 0x0100 },
5041                 { 0x19, 0, 0x0004 },
5042                 { 0x0a, 0, 0x0020 }
5043         };
5044
5045         /* Force LAN exit from ASPM if Rx/Tx are not idle */
5046         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
5047
5048         /* Disable Early Tally Counter */
5049         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) & ~0x010000);
5050
5051         RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
5052         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
5053
5054         rtl_ephy_init(tp, e_info_8105e_1);
5055
5056         rtl_pcie_state_l2l3_disable(tp);
5057 }
5058
5059 static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)
5060 {
5061         rtl_hw_start_8105e_1(tp);
5062         rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000);
5063 }
5064
5065 static void rtl_hw_start_8402(struct rtl8169_private *tp)
5066 {
5067         static const struct ephy_info e_info_8402[] = {
5068                 { 0x19, 0xffff, 0xff64 },
5069                 { 0x1e, 0, 0x4000 }
5070         };
5071
5072         rtl_set_def_aspm_entry_latency(tp);
5073
5074         /* Force LAN exit from ASPM if Rx/Tx are not idle */
5075         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
5076
5077         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
5078
5079         rtl_ephy_init(tp, e_info_8402);
5080
5081         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5082
5083         rtl_set_fifo_size(tp, 0x00, 0x00, 0x02, 0x06);
5084         rtl_reset_packet_filter(tp);
5085         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
5086         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
5087         rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0e00, 0xff00);
5088
5089         rtl_pcie_state_l2l3_disable(tp);
5090 }
5091
5092 static void rtl_hw_start_8106(struct rtl8169_private *tp)
5093 {
5094         rtl_hw_aspm_clkreq_enable(tp, false);
5095
5096         /* Force LAN exit from ASPM if Rx/Tx are not idle */
5097         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
5098
5099         RTL_W32(tp, MISC, (RTL_R32(tp, MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);
5100         RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
5101         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5102
5103         rtl_pcie_state_l2l3_disable(tp);
5104         rtl_hw_aspm_clkreq_enable(tp, true);
5105 }
5106
5107 static void rtl_hw_config(struct rtl8169_private *tp)
5108 {
5109         static const rtl_generic_fct hw_configs[] = {
5110                 [RTL_GIGA_MAC_VER_07] = rtl_hw_start_8102e_1,
5111                 [RTL_GIGA_MAC_VER_08] = rtl_hw_start_8102e_3,
5112                 [RTL_GIGA_MAC_VER_09] = rtl_hw_start_8102e_2,
5113                 [RTL_GIGA_MAC_VER_10] = NULL,
5114                 [RTL_GIGA_MAC_VER_11] = rtl_hw_start_8168bb,
5115                 [RTL_GIGA_MAC_VER_12] = rtl_hw_start_8168bef,
5116                 [RTL_GIGA_MAC_VER_13] = NULL,
5117                 [RTL_GIGA_MAC_VER_14] = NULL,
5118                 [RTL_GIGA_MAC_VER_15] = NULL,
5119                 [RTL_GIGA_MAC_VER_16] = NULL,
5120                 [RTL_GIGA_MAC_VER_17] = rtl_hw_start_8168bef,
5121                 [RTL_GIGA_MAC_VER_18] = rtl_hw_start_8168cp_1,
5122                 [RTL_GIGA_MAC_VER_19] = rtl_hw_start_8168c_1,
5123                 [RTL_GIGA_MAC_VER_20] = rtl_hw_start_8168c_2,
5124                 [RTL_GIGA_MAC_VER_21] = rtl_hw_start_8168c_3,
5125                 [RTL_GIGA_MAC_VER_22] = rtl_hw_start_8168c_4,
5126                 [RTL_GIGA_MAC_VER_23] = rtl_hw_start_8168cp_2,
5127                 [RTL_GIGA_MAC_VER_24] = rtl_hw_start_8168cp_3,
5128                 [RTL_GIGA_MAC_VER_25] = rtl_hw_start_8168d,
5129                 [RTL_GIGA_MAC_VER_26] = rtl_hw_start_8168d,
5130                 [RTL_GIGA_MAC_VER_27] = rtl_hw_start_8168d,
5131                 [RTL_GIGA_MAC_VER_28] = rtl_hw_start_8168d_4,
5132                 [RTL_GIGA_MAC_VER_29] = rtl_hw_start_8105e_1,
5133                 [RTL_GIGA_MAC_VER_30] = rtl_hw_start_8105e_2,
5134                 [RTL_GIGA_MAC_VER_31] = rtl_hw_start_8168dp,
5135                 [RTL_GIGA_MAC_VER_32] = rtl_hw_start_8168e_1,
5136                 [RTL_GIGA_MAC_VER_33] = rtl_hw_start_8168e_1,
5137                 [RTL_GIGA_MAC_VER_34] = rtl_hw_start_8168e_2,
5138                 [RTL_GIGA_MAC_VER_35] = rtl_hw_start_8168f_1,
5139                 [RTL_GIGA_MAC_VER_36] = rtl_hw_start_8168f_1,
5140                 [RTL_GIGA_MAC_VER_37] = rtl_hw_start_8402,
5141                 [RTL_GIGA_MAC_VER_38] = rtl_hw_start_8411,
5142                 [RTL_GIGA_MAC_VER_39] = rtl_hw_start_8106,
5143                 [RTL_GIGA_MAC_VER_40] = rtl_hw_start_8168g_1,
5144                 [RTL_GIGA_MAC_VER_41] = rtl_hw_start_8168g_1,
5145                 [RTL_GIGA_MAC_VER_42] = rtl_hw_start_8168g_2,
5146                 [RTL_GIGA_MAC_VER_43] = rtl_hw_start_8168g_2,
5147                 [RTL_GIGA_MAC_VER_44] = rtl_hw_start_8411_2,
5148                 [RTL_GIGA_MAC_VER_45] = rtl_hw_start_8168h_1,
5149                 [RTL_GIGA_MAC_VER_46] = rtl_hw_start_8168h_1,
5150                 [RTL_GIGA_MAC_VER_47] = rtl_hw_start_8168h_1,
5151                 [RTL_GIGA_MAC_VER_48] = rtl_hw_start_8168h_1,
5152                 [RTL_GIGA_MAC_VER_49] = rtl_hw_start_8168ep_1,
5153                 [RTL_GIGA_MAC_VER_50] = rtl_hw_start_8168ep_2,
5154                 [RTL_GIGA_MAC_VER_51] = rtl_hw_start_8168ep_3,
5155         };
5156
5157         if (hw_configs[tp->mac_version])
5158                 hw_configs[tp->mac_version](tp);
5159 }
5160
5161 static void rtl_hw_start_8168(struct rtl8169_private *tp)
5162 {
5163         if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
5164             tp->mac_version == RTL_GIGA_MAC_VER_16)
5165                 pcie_capability_set_word(tp->pci_dev, PCI_EXP_DEVCTL,
5166                                          PCI_EXP_DEVCTL_NOSNOOP_EN);
5167
5168         if (rtl_is_8168evl_up(tp))
5169                 RTL_W8(tp, MaxTxPacketSize, EarlySize);
5170         else
5171                 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
5172
5173         rtl_hw_config(tp);
5174 }
5175
5176 static void rtl_hw_start_8169(struct rtl8169_private *tp)
5177 {
5178         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
5179                 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
5180
5181         RTL_W8(tp, EarlyTxThres, NoEarlyTx);
5182
5183         tp->cp_cmd |= PCIMulRW;
5184
5185         if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
5186             tp->mac_version == RTL_GIGA_MAC_VER_03) {
5187                 netif_dbg(tp, drv, tp->dev,
5188                           "Set MAC Reg C+CR Offset 0xe0. Bit 3 and Bit 14 MUST be 1\n");
5189                 tp->cp_cmd |= (1 << 14);
5190         }
5191
5192         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
5193
5194         rtl8169_set_magic_reg(tp, tp->mac_version);
5195
5196         RTL_W32(tp, RxMissed, 0);
5197 }
5198
5199 static void rtl_hw_start(struct  rtl8169_private *tp)
5200 {
5201         rtl_unlock_config_regs(tp);
5202
5203         tp->cp_cmd &= CPCMD_MASK;
5204         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
5205
5206         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
5207                 rtl_hw_start_8169(tp);
5208         else
5209                 rtl_hw_start_8168(tp);
5210
5211         rtl_set_rx_max_size(tp);
5212         rtl_set_rx_tx_desc_registers(tp);
5213         rtl_lock_config_regs(tp);
5214
5215         /* disable interrupt coalescing */
5216         RTL_W16(tp, IntrMitigate, 0x0000);
5217         /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
5218         RTL_R8(tp, IntrMask);
5219         RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb);
5220         rtl_init_rxcfg(tp);
5221         rtl_set_tx_config_registers(tp);
5222         rtl_set_rx_mode(tp->dev);
5223         rtl_irq_enable(tp);
5224 }
5225
5226 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
5227 {
5228         struct rtl8169_private *tp = netdev_priv(dev);
5229
5230         if (new_mtu > ETH_DATA_LEN)
5231                 rtl_hw_jumbo_enable(tp);
5232         else
5233                 rtl_hw_jumbo_disable(tp);
5234
5235         dev->mtu = new_mtu;
5236         netdev_update_features(dev);
5237
5238         return 0;
5239 }
5240
5241 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
5242 {
5243         desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
5244         desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
5245 }
5246
5247 static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
5248                                      void **data_buff, struct RxDesc *desc)
5249 {
5250         dma_unmap_single(tp_to_dev(tp), le64_to_cpu(desc->addr),
5251                          R8169_RX_BUF_SIZE, DMA_FROM_DEVICE);
5252
5253         kfree(*data_buff);
5254         *data_buff = NULL;
5255         rtl8169_make_unusable_by_asic(desc);
5256 }
5257
5258 static inline void rtl8169_mark_to_asic(struct RxDesc *desc)
5259 {
5260         u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
5261
5262         /* Force memory writes to complete before releasing descriptor */
5263         dma_wmb();
5264
5265         desc->opts1 = cpu_to_le32(DescOwn | eor | R8169_RX_BUF_SIZE);
5266 }
5267
5268 static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
5269                                              struct RxDesc *desc)
5270 {
5271         void *data;
5272         dma_addr_t mapping;
5273         struct device *d = tp_to_dev(tp);
5274         int node = dev_to_node(d);
5275
5276         data = kmalloc_node(R8169_RX_BUF_SIZE, GFP_KERNEL, node);
5277         if (!data)
5278                 return NULL;
5279
5280         /* Memory should be properly aligned, but better check. */
5281         if (!IS_ALIGNED((unsigned long)data, 8)) {
5282                 netdev_err_once(tp->dev, "RX buffer not 8-byte-aligned\n");
5283                 goto err_out;
5284         }
5285
5286         mapping = dma_map_single(d, data, R8169_RX_BUF_SIZE, DMA_FROM_DEVICE);
5287         if (unlikely(dma_mapping_error(d, mapping))) {
5288                 if (net_ratelimit())
5289                         netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
5290                 goto err_out;
5291         }
5292
5293         desc->addr = cpu_to_le64(mapping);
5294         rtl8169_mark_to_asic(desc);
5295         return data;
5296
5297 err_out:
5298         kfree(data);
5299         return NULL;
5300 }
5301
5302 static void rtl8169_rx_clear(struct rtl8169_private *tp)
5303 {
5304         unsigned int i;
5305
5306         for (i = 0; i < NUM_RX_DESC; i++) {
5307                 if (tp->Rx_databuff[i]) {
5308                         rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
5309                                             tp->RxDescArray + i);
5310                 }
5311         }
5312 }
5313
5314 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
5315 {
5316         desc->opts1 |= cpu_to_le32(RingEnd);
5317 }
5318
5319 static int rtl8169_rx_fill(struct rtl8169_private *tp)
5320 {
5321         unsigned int i;
5322
5323         for (i = 0; i < NUM_RX_DESC; i++) {
5324                 void *data;
5325
5326                 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
5327                 if (!data) {
5328                         rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
5329                         goto err_out;
5330                 }
5331                 tp->Rx_databuff[i] = data;
5332         }
5333
5334         rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
5335         return 0;
5336
5337 err_out:
5338         rtl8169_rx_clear(tp);
5339         return -ENOMEM;
5340 }
5341
5342 static int rtl8169_init_ring(struct rtl8169_private *tp)
5343 {
5344         rtl8169_init_ring_indexes(tp);
5345
5346         memset(tp->tx_skb, 0, sizeof(tp->tx_skb));
5347         memset(tp->Rx_databuff, 0, sizeof(tp->Rx_databuff));
5348
5349         return rtl8169_rx_fill(tp);
5350 }
5351
5352 static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
5353                                  struct TxDesc *desc)
5354 {
5355         unsigned int len = tx_skb->len;
5356
5357         dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
5358
5359         desc->opts1 = 0x00;
5360         desc->opts2 = 0x00;
5361         desc->addr = 0x00;
5362         tx_skb->len = 0;
5363 }
5364
5365 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
5366                                    unsigned int n)
5367 {
5368         unsigned int i;
5369
5370         for (i = 0; i < n; i++) {
5371                 unsigned int entry = (start + i) % NUM_TX_DESC;
5372                 struct ring_info *tx_skb = tp->tx_skb + entry;
5373                 unsigned int len = tx_skb->len;
5374
5375                 if (len) {
5376                         struct sk_buff *skb = tx_skb->skb;
5377
5378                         rtl8169_unmap_tx_skb(tp_to_dev(tp), tx_skb,
5379                                              tp->TxDescArray + entry);
5380                         if (skb) {
5381                                 dev_consume_skb_any(skb);
5382                                 tx_skb->skb = NULL;
5383                         }
5384                 }
5385         }
5386 }
5387
5388 static void rtl8169_tx_clear(struct rtl8169_private *tp)
5389 {
5390         rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
5391         tp->cur_tx = tp->dirty_tx = 0;
5392         netdev_reset_queue(tp->dev);
5393 }
5394
5395 static void rtl_reset_work(struct rtl8169_private *tp)
5396 {
5397         struct net_device *dev = tp->dev;
5398         int i;
5399
5400         napi_disable(&tp->napi);
5401         netif_stop_queue(dev);
5402         synchronize_rcu();
5403
5404         rtl8169_hw_reset(tp);
5405
5406         for (i = 0; i < NUM_RX_DESC; i++)
5407                 rtl8169_mark_to_asic(tp->RxDescArray + i);
5408
5409         rtl8169_tx_clear(tp);
5410         rtl8169_init_ring_indexes(tp);
5411
5412         napi_enable(&tp->napi);
5413         rtl_hw_start(tp);
5414         netif_wake_queue(dev);
5415 }
5416
5417 static void rtl8169_tx_timeout(struct net_device *dev)
5418 {
5419         struct rtl8169_private *tp = netdev_priv(dev);
5420
5421         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
5422 }
5423
5424 static __le32 rtl8169_get_txd_opts1(u32 opts0, u32 len, unsigned int entry)
5425 {
5426         u32 status = opts0 | len;
5427
5428         if (entry == NUM_TX_DESC - 1)
5429                 status |= RingEnd;
5430
5431         return cpu_to_le32(status);
5432 }
5433
5434 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
5435                               u32 *opts)
5436 {
5437         struct skb_shared_info *info = skb_shinfo(skb);
5438         unsigned int cur_frag, entry;
5439         struct TxDesc *uninitialized_var(txd);
5440         struct device *d = tp_to_dev(tp);
5441
5442         entry = tp->cur_tx;
5443         for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
5444                 const skb_frag_t *frag = info->frags + cur_frag;
5445                 dma_addr_t mapping;
5446                 u32 len;
5447                 void *addr;
5448
5449                 entry = (entry + 1) % NUM_TX_DESC;
5450
5451                 txd = tp->TxDescArray + entry;
5452                 len = skb_frag_size(frag);
5453                 addr = skb_frag_address(frag);
5454                 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
5455                 if (unlikely(dma_mapping_error(d, mapping))) {
5456                         if (net_ratelimit())
5457                                 netif_err(tp, drv, tp->dev,
5458                                           "Failed to map TX fragments DMA!\n");
5459                         goto err_out;
5460                 }
5461
5462                 txd->opts1 = rtl8169_get_txd_opts1(opts[0], len, entry);
5463                 txd->opts2 = cpu_to_le32(opts[1]);
5464                 txd->addr = cpu_to_le64(mapping);
5465
5466                 tp->tx_skb[entry].len = len;
5467         }
5468
5469         if (cur_frag) {
5470                 tp->tx_skb[entry].skb = skb;
5471                 txd->opts1 |= cpu_to_le32(LastFrag);
5472         }
5473
5474         return cur_frag;
5475
5476 err_out:
5477         rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
5478         return -EIO;
5479 }
5480
5481 static bool rtl_test_hw_pad_bug(struct rtl8169_private *tp, struct sk_buff *skb)
5482 {
5483         return skb->len < ETH_ZLEN && tp->mac_version == RTL_GIGA_MAC_VER_34;
5484 }
5485
5486 /* msdn_giant_send_check()
5487  * According to the document of microsoft, the TCP Pseudo Header excludes the
5488  * packet length for IPv6 TCP large packets.
5489  */
5490 static int msdn_giant_send_check(struct sk_buff *skb)
5491 {
5492         const struct ipv6hdr *ipv6h;
5493         struct tcphdr *th;
5494         int ret;
5495
5496         ret = skb_cow_head(skb, 0);
5497         if (ret)
5498                 return ret;
5499
5500         ipv6h = ipv6_hdr(skb);
5501         th = tcp_hdr(skb);
5502
5503         th->check = 0;
5504         th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0);
5505
5506         return ret;
5507 }
5508
5509 static void rtl8169_tso_csum_v1(struct sk_buff *skb, u32 *opts)
5510 {
5511         u32 mss = skb_shinfo(skb)->gso_size;
5512
5513         if (mss) {
5514                 opts[0] |= TD_LSO;
5515                 opts[0] |= min(mss, TD_MSS_MAX) << TD0_MSS_SHIFT;
5516         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5517                 const struct iphdr *ip = ip_hdr(skb);
5518
5519                 if (ip->protocol == IPPROTO_TCP)
5520                         opts[0] |= TD0_IP_CS | TD0_TCP_CS;
5521                 else if (ip->protocol == IPPROTO_UDP)
5522                         opts[0] |= TD0_IP_CS | TD0_UDP_CS;
5523                 else
5524                         WARN_ON_ONCE(1);
5525         }
5526 }
5527
5528 static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp,
5529                                 struct sk_buff *skb, u32 *opts)
5530 {
5531         u32 transport_offset = (u32)skb_transport_offset(skb);
5532         u32 mss = skb_shinfo(skb)->gso_size;
5533
5534         if (mss) {
5535                 switch (vlan_get_protocol(skb)) {
5536                 case htons(ETH_P_IP):
5537                         opts[0] |= TD1_GTSENV4;
5538                         break;
5539
5540                 case htons(ETH_P_IPV6):
5541                         if (msdn_giant_send_check(skb))
5542                                 return false;
5543
5544                         opts[0] |= TD1_GTSENV6;
5545                         break;
5546
5547                 default:
5548                         WARN_ON_ONCE(1);
5549                         break;
5550                 }
5551
5552                 opts[0] |= transport_offset << GTTCPHO_SHIFT;
5553                 opts[1] |= min(mss, TD_MSS_MAX) << TD1_MSS_SHIFT;
5554         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5555                 u8 ip_protocol;
5556
5557                 switch (vlan_get_protocol(skb)) {
5558                 case htons(ETH_P_IP):
5559                         opts[1] |= TD1_IPv4_CS;
5560                         ip_protocol = ip_hdr(skb)->protocol;
5561                         break;
5562
5563                 case htons(ETH_P_IPV6):
5564                         opts[1] |= TD1_IPv6_CS;
5565                         ip_protocol = ipv6_hdr(skb)->nexthdr;
5566                         break;
5567
5568                 default:
5569                         ip_protocol = IPPROTO_RAW;
5570                         break;
5571                 }
5572
5573                 if (ip_protocol == IPPROTO_TCP)
5574                         opts[1] |= TD1_TCP_CS;
5575                 else if (ip_protocol == IPPROTO_UDP)
5576                         opts[1] |= TD1_UDP_CS;
5577                 else
5578                         WARN_ON_ONCE(1);
5579
5580                 opts[1] |= transport_offset << TCPHO_SHIFT;
5581         } else {
5582                 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
5583                         return !eth_skb_pad(skb);
5584         }
5585
5586         return true;
5587 }
5588
5589 static bool rtl_tx_slots_avail(struct rtl8169_private *tp,
5590                                unsigned int nr_frags)
5591 {
5592         unsigned int slots_avail = tp->dirty_tx + NUM_TX_DESC - tp->cur_tx;
5593
5594         /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
5595         return slots_avail > nr_frags;
5596 }
5597
5598 /* Versions RTL8102e and from RTL8168c onwards support csum_v2 */
5599 static bool rtl_chip_supports_csum_v2(struct rtl8169_private *tp)
5600 {
5601         switch (tp->mac_version) {
5602         case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
5603         case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
5604                 return false;
5605         default:
5606                 return true;
5607         }
5608 }
5609
5610 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
5611                                       struct net_device *dev)
5612 {
5613         struct rtl8169_private *tp = netdev_priv(dev);
5614         unsigned int entry = tp->cur_tx % NUM_TX_DESC;
5615         struct TxDesc *txd = tp->TxDescArray + entry;
5616         struct device *d = tp_to_dev(tp);
5617         dma_addr_t mapping;
5618         u32 opts[2], len;
5619         bool stop_queue;
5620         bool door_bell;
5621         int frags;
5622
5623         if (unlikely(!rtl_tx_slots_avail(tp, skb_shinfo(skb)->nr_frags))) {
5624                 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
5625                 goto err_stop_0;
5626         }
5627
5628         if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
5629                 goto err_stop_0;
5630
5631         opts[1] = rtl8169_tx_vlan_tag(skb);
5632         opts[0] = DescOwn;
5633
5634         if (rtl_chip_supports_csum_v2(tp)) {
5635                 if (!rtl8169_tso_csum_v2(tp, skb, opts))
5636                         goto err_dma_0;
5637         } else {
5638                 rtl8169_tso_csum_v1(skb, opts);
5639         }
5640
5641         len = skb_headlen(skb);
5642         mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
5643         if (unlikely(dma_mapping_error(d, mapping))) {
5644                 if (net_ratelimit())
5645                         netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
5646                 goto err_dma_0;
5647         }
5648
5649         tp->tx_skb[entry].len = len;
5650         txd->addr = cpu_to_le64(mapping);
5651
5652         frags = rtl8169_xmit_frags(tp, skb, opts);
5653         if (frags < 0)
5654                 goto err_dma_1;
5655         else if (frags)
5656                 opts[0] |= FirstFrag;
5657         else {
5658                 opts[0] |= FirstFrag | LastFrag;
5659                 tp->tx_skb[entry].skb = skb;
5660         }
5661
5662         txd->opts2 = cpu_to_le32(opts[1]);
5663
5664         skb_tx_timestamp(skb);
5665
5666         /* Force memory writes to complete before releasing descriptor */
5667         dma_wmb();
5668
5669         door_bell = __netdev_sent_queue(dev, skb->len, netdev_xmit_more());
5670
5671         txd->opts1 = rtl8169_get_txd_opts1(opts[0], len, entry);
5672
5673         /* Force all memory writes to complete before notifying device */
5674         wmb();
5675
5676         tp->cur_tx += frags + 1;
5677
5678         stop_queue = !rtl_tx_slots_avail(tp, MAX_SKB_FRAGS);
5679         if (unlikely(stop_queue)) {
5680                 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
5681                  * not miss a ring update when it notices a stopped queue.
5682                  */
5683                 smp_wmb();
5684                 netif_stop_queue(dev);
5685         }
5686
5687         if (door_bell)
5688                 RTL_W8(tp, TxPoll, NPQ);
5689
5690         if (unlikely(stop_queue)) {
5691                 /* Sync with rtl_tx:
5692                  * - publish queue status and cur_tx ring index (write barrier)
5693                  * - refresh dirty_tx ring index (read barrier).
5694                  * May the current thread have a pessimistic view of the ring
5695                  * status and forget to wake up queue, a racing rtl_tx thread
5696                  * can't.
5697                  */
5698                 smp_mb();
5699                 if (rtl_tx_slots_avail(tp, MAX_SKB_FRAGS))
5700                         netif_start_queue(dev);
5701         }
5702
5703         return NETDEV_TX_OK;
5704
5705 err_dma_1:
5706         rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
5707 err_dma_0:
5708         dev_kfree_skb_any(skb);
5709         dev->stats.tx_dropped++;
5710         return NETDEV_TX_OK;
5711
5712 err_stop_0:
5713         netif_stop_queue(dev);
5714         dev->stats.tx_dropped++;
5715         return NETDEV_TX_BUSY;
5716 }
5717
5718 static netdev_features_t rtl8169_features_check(struct sk_buff *skb,
5719                                                 struct net_device *dev,
5720                                                 netdev_features_t features)
5721 {
5722         int transport_offset = skb_transport_offset(skb);
5723         struct rtl8169_private *tp = netdev_priv(dev);
5724
5725         if (skb_is_gso(skb)) {
5726                 if (transport_offset > GTTCPHO_MAX &&
5727                     rtl_chip_supports_csum_v2(tp))
5728                         features &= ~NETIF_F_ALL_TSO;
5729         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5730                 if (skb->len < ETH_ZLEN) {
5731                         switch (tp->mac_version) {
5732                         case RTL_GIGA_MAC_VER_11:
5733                         case RTL_GIGA_MAC_VER_12:
5734                         case RTL_GIGA_MAC_VER_17:
5735                         case RTL_GIGA_MAC_VER_34:
5736                                 features &= ~NETIF_F_CSUM_MASK;
5737                                 break;
5738                         default:
5739                                 break;
5740                         }
5741                 }
5742
5743                 if (transport_offset > TCPHO_MAX &&
5744                     rtl_chip_supports_csum_v2(tp))
5745                         features &= ~NETIF_F_CSUM_MASK;
5746         }
5747
5748         return vlan_features_check(skb, features);
5749 }
5750
5751 static void rtl8169_pcierr_interrupt(struct net_device *dev)
5752 {
5753         struct rtl8169_private *tp = netdev_priv(dev);
5754         struct pci_dev *pdev = tp->pci_dev;
5755         u16 pci_status, pci_cmd;
5756
5757         pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
5758         pci_read_config_word(pdev, PCI_STATUS, &pci_status);
5759
5760         netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
5761                   pci_cmd, pci_status);
5762
5763         /*
5764          * The recovery sequence below admits a very elaborated explanation:
5765          * - it seems to work;
5766          * - I did not see what else could be done;
5767          * - it makes iop3xx happy.
5768          *
5769          * Feel free to adjust to your needs.
5770          */
5771         if (pdev->broken_parity_status)
5772                 pci_cmd &= ~PCI_COMMAND_PARITY;
5773         else
5774                 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
5775
5776         pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
5777
5778         pci_write_config_word(pdev, PCI_STATUS,
5779                 pci_status & (PCI_STATUS_DETECTED_PARITY |
5780                 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
5781                 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
5782
5783         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
5784 }
5785
5786 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp,
5787                    int budget)
5788 {
5789         unsigned int dirty_tx, tx_left, bytes_compl = 0, pkts_compl = 0;
5790
5791         dirty_tx = tp->dirty_tx;
5792         smp_rmb();
5793         tx_left = tp->cur_tx - dirty_tx;
5794
5795         while (tx_left > 0) {
5796                 unsigned int entry = dirty_tx % NUM_TX_DESC;
5797                 struct ring_info *tx_skb = tp->tx_skb + entry;
5798                 u32 status;
5799
5800                 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
5801                 if (status & DescOwn)
5802                         break;
5803
5804                 /* This barrier is needed to keep us from reading
5805                  * any other fields out of the Tx descriptor until
5806                  * we know the status of DescOwn
5807                  */
5808                 dma_rmb();
5809
5810                 rtl8169_unmap_tx_skb(tp_to_dev(tp), tx_skb,
5811                                      tp->TxDescArray + entry);
5812                 if (status & LastFrag) {
5813                         pkts_compl++;
5814                         bytes_compl += tx_skb->skb->len;
5815                         napi_consume_skb(tx_skb->skb, budget);
5816                         tx_skb->skb = NULL;
5817                 }
5818                 dirty_tx++;
5819                 tx_left--;
5820         }
5821
5822         if (tp->dirty_tx != dirty_tx) {
5823                 netdev_completed_queue(dev, pkts_compl, bytes_compl);
5824
5825                 u64_stats_update_begin(&tp->tx_stats.syncp);
5826                 tp->tx_stats.packets += pkts_compl;
5827                 tp->tx_stats.bytes += bytes_compl;
5828                 u64_stats_update_end(&tp->tx_stats.syncp);
5829
5830                 tp->dirty_tx = dirty_tx;
5831                 /* Sync with rtl8169_start_xmit:
5832                  * - publish dirty_tx ring index (write barrier)
5833                  * - refresh cur_tx ring index and queue status (read barrier)
5834                  * May the current thread miss the stopped queue condition,
5835                  * a racing xmit thread can only have a right view of the
5836                  * ring status.
5837                  */
5838                 smp_mb();
5839                 if (netif_queue_stopped(dev) &&
5840                     rtl_tx_slots_avail(tp, MAX_SKB_FRAGS)) {
5841                         netif_wake_queue(dev);
5842                 }
5843                 /*
5844                  * 8168 hack: TxPoll requests are lost when the Tx packets are
5845                  * too close. Let's kick an extra TxPoll request when a burst
5846                  * of start_xmit activity is detected (if it is not detected,
5847                  * it is slow enough). -- FR
5848                  */
5849                 if (tp->cur_tx != dirty_tx)
5850                         RTL_W8(tp, TxPoll, NPQ);
5851         }
5852 }
5853
5854 static inline int rtl8169_fragmented_frame(u32 status)
5855 {
5856         return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
5857 }
5858
5859 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
5860 {
5861         u32 status = opts1 & RxProtoMask;
5862
5863         if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
5864             ((status == RxProtoUDP) && !(opts1 & UDPFail)))
5865                 skb->ip_summed = CHECKSUM_UNNECESSARY;
5866         else
5867                 skb_checksum_none_assert(skb);
5868 }
5869
5870 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget)
5871 {
5872         unsigned int cur_rx, rx_left;
5873         unsigned int count;
5874
5875         cur_rx = tp->cur_rx;
5876
5877         for (rx_left = min(budget, NUM_RX_DESC); rx_left > 0; rx_left--, cur_rx++) {
5878                 unsigned int entry = cur_rx % NUM_RX_DESC;
5879                 struct RxDesc *desc = tp->RxDescArray + entry;
5880                 u32 status;
5881
5882                 status = le32_to_cpu(desc->opts1);
5883                 if (status & DescOwn)
5884                         break;
5885
5886                 /* This barrier is needed to keep us from reading
5887                  * any other fields out of the Rx descriptor until
5888                  * we know the status of DescOwn
5889                  */
5890                 dma_rmb();
5891
5892                 if (unlikely(status & RxRES)) {
5893                         netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
5894                                    status);
5895                         dev->stats.rx_errors++;
5896                         if (status & (RxRWT | RxRUNT))
5897                                 dev->stats.rx_length_errors++;
5898                         if (status & RxCRC)
5899                                 dev->stats.rx_crc_errors++;
5900                         if (status & (RxRUNT | RxCRC) && !(status & RxRWT) &&
5901                             dev->features & NETIF_F_RXALL) {
5902                                 goto process_pkt;
5903                         }
5904                 } else {
5905                         unsigned int pkt_size;
5906                         struct sk_buff *skb;
5907
5908 process_pkt:
5909                         pkt_size = status & GENMASK(13, 0);
5910                         if (likely(!(dev->features & NETIF_F_RXFCS)))
5911                                 pkt_size -= ETH_FCS_LEN;
5912                         /*
5913                          * The driver does not support incoming fragmented
5914                          * frames. They are seen as a symptom of over-mtu
5915                          * sized frames.
5916                          */
5917                         if (unlikely(rtl8169_fragmented_frame(status))) {
5918                                 dev->stats.rx_dropped++;
5919                                 dev->stats.rx_length_errors++;
5920                                 goto release_descriptor;
5921                         }
5922
5923                         dma_sync_single_for_cpu(tp_to_dev(tp),
5924                                                 le64_to_cpu(desc->addr),
5925                                                 pkt_size, DMA_FROM_DEVICE);
5926
5927                         skb = napi_alloc_skb(&tp->napi, pkt_size);
5928                         if (unlikely(!skb)) {
5929                                 dev->stats.rx_dropped++;
5930                                 goto release_descriptor;
5931                         }
5932
5933                         prefetch(tp->Rx_databuff[entry]);
5934                         skb_copy_to_linear_data(skb, tp->Rx_databuff[entry],
5935                                                 pkt_size);
5936                         skb->tail += pkt_size;
5937                         skb->len = pkt_size;
5938
5939                         rtl8169_rx_csum(skb, status);
5940                         skb->protocol = eth_type_trans(skb, dev);
5941
5942                         rtl8169_rx_vlan_tag(desc, skb);
5943
5944                         if (skb->pkt_type == PACKET_MULTICAST)
5945                                 dev->stats.multicast++;
5946
5947                         napi_gro_receive(&tp->napi, skb);
5948
5949                         u64_stats_update_begin(&tp->rx_stats.syncp);
5950                         tp->rx_stats.packets++;
5951                         tp->rx_stats.bytes += pkt_size;
5952                         u64_stats_update_end(&tp->rx_stats.syncp);
5953                 }
5954 release_descriptor:
5955                 desc->opts2 = 0;
5956                 rtl8169_mark_to_asic(desc);
5957         }
5958
5959         count = cur_rx - tp->cur_rx;
5960         tp->cur_rx = cur_rx;
5961
5962         return count;
5963 }
5964
5965 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
5966 {
5967         struct rtl8169_private *tp = dev_instance;
5968         u16 status = RTL_R16(tp, IntrStatus);
5969
5970         if (!tp->irq_enabled || status == 0xffff || !(status & tp->irq_mask))
5971                 return IRQ_NONE;
5972
5973         if (unlikely(status & SYSErr)) {
5974                 rtl8169_pcierr_interrupt(tp->dev);
5975                 goto out;
5976         }
5977
5978         if (status & LinkChg)
5979                 phy_mac_interrupt(tp->phydev);
5980
5981         if (unlikely(status & RxFIFOOver &&
5982             tp->mac_version == RTL_GIGA_MAC_VER_11)) {
5983                 netif_stop_queue(tp->dev);
5984                 /* XXX - Hack alert. See rtl_task(). */
5985                 set_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags);
5986         }
5987
5988         rtl_irq_disable(tp);
5989         napi_schedule_irqoff(&tp->napi);
5990 out:
5991         rtl_ack_events(tp, status);
5992
5993         return IRQ_HANDLED;
5994 }
5995
5996 static void rtl_task(struct work_struct *work)
5997 {
5998         static const struct {
5999                 int bitnr;
6000                 void (*action)(struct rtl8169_private *);
6001         } rtl_work[] = {
6002                 { RTL_FLAG_TASK_RESET_PENDING,  rtl_reset_work },
6003         };
6004         struct rtl8169_private *tp =
6005                 container_of(work, struct rtl8169_private, wk.work);
6006         struct net_device *dev = tp->dev;
6007         int i;
6008
6009         rtl_lock_work(tp);
6010
6011         if (!netif_running(dev) ||
6012             !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
6013                 goto out_unlock;
6014
6015         for (i = 0; i < ARRAY_SIZE(rtl_work); i++) {
6016                 bool pending;
6017
6018                 pending = test_and_clear_bit(rtl_work[i].bitnr, tp->wk.flags);
6019                 if (pending)
6020                         rtl_work[i].action(tp);
6021         }
6022
6023 out_unlock:
6024         rtl_unlock_work(tp);
6025 }
6026
6027 static int rtl8169_poll(struct napi_struct *napi, int budget)
6028 {
6029         struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
6030         struct net_device *dev = tp->dev;
6031         int work_done;
6032
6033         work_done = rtl_rx(dev, tp, (u32) budget);
6034
6035         rtl_tx(dev, tp, budget);
6036
6037         if (work_done < budget) {
6038                 napi_complete_done(napi, work_done);
6039                 rtl_irq_enable(tp);
6040         }
6041
6042         return work_done;
6043 }
6044
6045 static void rtl8169_rx_missed(struct net_device *dev)
6046 {
6047         struct rtl8169_private *tp = netdev_priv(dev);
6048
6049         if (tp->mac_version > RTL_GIGA_MAC_VER_06)
6050                 return;
6051
6052         dev->stats.rx_missed_errors += RTL_R32(tp, RxMissed) & 0xffffff;
6053         RTL_W32(tp, RxMissed, 0);
6054 }
6055
6056 static void r8169_phylink_handler(struct net_device *ndev)
6057 {
6058         struct rtl8169_private *tp = netdev_priv(ndev);
6059
6060         if (netif_carrier_ok(ndev)) {
6061                 rtl_link_chg_patch(tp);
6062                 pm_request_resume(&tp->pci_dev->dev);
6063         } else {
6064                 pm_runtime_idle(&tp->pci_dev->dev);
6065         }
6066
6067         if (net_ratelimit())
6068                 phy_print_status(tp->phydev);
6069 }
6070
6071 static int r8169_phy_connect(struct rtl8169_private *tp)
6072 {
6073         struct phy_device *phydev = tp->phydev;
6074         phy_interface_t phy_mode;
6075         int ret;
6076
6077         phy_mode = tp->supports_gmii ? PHY_INTERFACE_MODE_GMII :
6078                    PHY_INTERFACE_MODE_MII;
6079
6080         ret = phy_connect_direct(tp->dev, phydev, r8169_phylink_handler,
6081                                  phy_mode);
6082         if (ret)
6083                 return ret;
6084
6085         if (tp->supports_gmii)
6086                 phy_remove_link_mode(phydev,
6087                                      ETHTOOL_LINK_MODE_1000baseT_Half_BIT);
6088         else
6089                 phy_set_max_speed(phydev, SPEED_100);
6090
6091         phy_support_asym_pause(phydev);
6092
6093         phy_attached_info(phydev);
6094
6095         return 0;
6096 }
6097
6098 static void rtl8169_down(struct net_device *dev)
6099 {
6100         struct rtl8169_private *tp = netdev_priv(dev);
6101
6102         phy_stop(tp->phydev);
6103
6104         napi_disable(&tp->napi);
6105         netif_stop_queue(dev);
6106
6107         rtl8169_hw_reset(tp);
6108         /*
6109          * At this point device interrupts can not be enabled in any function,
6110          * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task)
6111          * and napi is disabled (rtl8169_poll).
6112          */
6113         rtl8169_rx_missed(dev);
6114
6115         /* Give a racing hard_start_xmit a few cycles to complete. */
6116         synchronize_rcu();
6117
6118         rtl8169_tx_clear(tp);
6119
6120         rtl8169_rx_clear(tp);
6121
6122         rtl_pll_power_down(tp);
6123 }
6124
6125 static int rtl8169_close(struct net_device *dev)
6126 {
6127         struct rtl8169_private *tp = netdev_priv(dev);
6128         struct pci_dev *pdev = tp->pci_dev;
6129
6130         pm_runtime_get_sync(&pdev->dev);
6131
6132         /* Update counters before going down */
6133         rtl8169_update_counters(tp);
6134
6135         rtl_lock_work(tp);
6136         /* Clear all task flags */
6137         bitmap_zero(tp->wk.flags, RTL_FLAG_MAX);
6138
6139         rtl8169_down(dev);
6140         rtl_unlock_work(tp);
6141
6142         cancel_work_sync(&tp->wk.work);
6143
6144         phy_disconnect(tp->phydev);
6145
6146         pci_free_irq(pdev, 0, tp);
6147
6148         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6149                           tp->RxPhyAddr);
6150         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6151                           tp->TxPhyAddr);
6152         tp->TxDescArray = NULL;
6153         tp->RxDescArray = NULL;
6154
6155         pm_runtime_put_sync(&pdev->dev);
6156
6157         return 0;
6158 }
6159
6160 #ifdef CONFIG_NET_POLL_CONTROLLER
6161 static void rtl8169_netpoll(struct net_device *dev)
6162 {
6163         struct rtl8169_private *tp = netdev_priv(dev);
6164
6165         rtl8169_interrupt(pci_irq_vector(tp->pci_dev, 0), tp);
6166 }
6167 #endif
6168
6169 static int rtl_open(struct net_device *dev)
6170 {
6171         struct rtl8169_private *tp = netdev_priv(dev);
6172         struct pci_dev *pdev = tp->pci_dev;
6173         int retval = -ENOMEM;
6174
6175         pm_runtime_get_sync(&pdev->dev);
6176
6177         /*
6178          * Rx and Tx descriptors needs 256 bytes alignment.
6179          * dma_alloc_coherent provides more.
6180          */
6181         tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
6182                                              &tp->TxPhyAddr, GFP_KERNEL);
6183         if (!tp->TxDescArray)
6184                 goto err_pm_runtime_put;
6185
6186         tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
6187                                              &tp->RxPhyAddr, GFP_KERNEL);
6188         if (!tp->RxDescArray)
6189                 goto err_free_tx_0;
6190
6191         retval = rtl8169_init_ring(tp);
6192         if (retval < 0)
6193                 goto err_free_rx_1;
6194
6195         rtl_request_firmware(tp);
6196
6197         retval = pci_request_irq(pdev, 0, rtl8169_interrupt, NULL, tp,
6198                                  dev->name);
6199         if (retval < 0)
6200                 goto err_release_fw_2;
6201
6202         retval = r8169_phy_connect(tp);
6203         if (retval)
6204                 goto err_free_irq;
6205
6206         rtl_lock_work(tp);
6207
6208         set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6209
6210         napi_enable(&tp->napi);
6211
6212         rtl8169_init_phy(dev, tp);
6213
6214         rtl_pll_power_up(tp);
6215
6216         rtl_hw_start(tp);
6217
6218         if (!rtl8169_init_counter_offsets(tp))
6219                 netif_warn(tp, hw, dev, "counter reset/update failed\n");
6220
6221         phy_start(tp->phydev);
6222         netif_start_queue(dev);
6223
6224         rtl_unlock_work(tp);
6225
6226         pm_runtime_put_sync(&pdev->dev);
6227 out:
6228         return retval;
6229
6230 err_free_irq:
6231         pci_free_irq(pdev, 0, tp);
6232 err_release_fw_2:
6233         rtl_release_firmware(tp);
6234         rtl8169_rx_clear(tp);
6235 err_free_rx_1:
6236         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6237                           tp->RxPhyAddr);
6238         tp->RxDescArray = NULL;
6239 err_free_tx_0:
6240         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6241                           tp->TxPhyAddr);
6242         tp->TxDescArray = NULL;
6243 err_pm_runtime_put:
6244         pm_runtime_put_noidle(&pdev->dev);
6245         goto out;
6246 }
6247
6248 static void
6249 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
6250 {
6251         struct rtl8169_private *tp = netdev_priv(dev);
6252         struct pci_dev *pdev = tp->pci_dev;
6253         struct rtl8169_counters *counters = tp->counters;
6254         unsigned int start;
6255
6256         pm_runtime_get_noresume(&pdev->dev);
6257
6258         if (netif_running(dev) && pm_runtime_active(&pdev->dev))
6259                 rtl8169_rx_missed(dev);
6260
6261         do {
6262                 start = u64_stats_fetch_begin_irq(&tp->rx_stats.syncp);
6263                 stats->rx_packets = tp->rx_stats.packets;
6264                 stats->rx_bytes = tp->rx_stats.bytes;
6265         } while (u64_stats_fetch_retry_irq(&tp->rx_stats.syncp, start));
6266
6267         do {
6268                 start = u64_stats_fetch_begin_irq(&tp->tx_stats.syncp);
6269                 stats->tx_packets = tp->tx_stats.packets;
6270                 stats->tx_bytes = tp->tx_stats.bytes;
6271         } while (u64_stats_fetch_retry_irq(&tp->tx_stats.syncp, start));
6272
6273         stats->rx_dropped       = dev->stats.rx_dropped;
6274         stats->tx_dropped       = dev->stats.tx_dropped;
6275         stats->rx_length_errors = dev->stats.rx_length_errors;
6276         stats->rx_errors        = dev->stats.rx_errors;
6277         stats->rx_crc_errors    = dev->stats.rx_crc_errors;
6278         stats->rx_fifo_errors   = dev->stats.rx_fifo_errors;
6279         stats->rx_missed_errors = dev->stats.rx_missed_errors;
6280         stats->multicast        = dev->stats.multicast;
6281
6282         /*
6283          * Fetch additional counter values missing in stats collected by driver
6284          * from tally counters.
6285          */
6286         if (pm_runtime_active(&pdev->dev))
6287                 rtl8169_update_counters(tp);
6288
6289         /*
6290          * Subtract values fetched during initalization.
6291          * See rtl8169_init_counter_offsets for a description why we do that.
6292          */
6293         stats->tx_errors = le64_to_cpu(counters->tx_errors) -
6294                 le64_to_cpu(tp->tc_offset.tx_errors);
6295         stats->collisions = le32_to_cpu(counters->tx_multi_collision) -
6296                 le32_to_cpu(tp->tc_offset.tx_multi_collision);
6297         stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) -
6298                 le16_to_cpu(tp->tc_offset.tx_aborted);
6299
6300         pm_runtime_put_noidle(&pdev->dev);
6301 }
6302
6303 static void rtl8169_net_suspend(struct net_device *dev)
6304 {
6305         struct rtl8169_private *tp = netdev_priv(dev);
6306
6307         if (!netif_running(dev))
6308                 return;
6309
6310         phy_stop(tp->phydev);
6311         netif_device_detach(dev);
6312
6313         rtl_lock_work(tp);
6314         napi_disable(&tp->napi);
6315         /* Clear all task flags */
6316         bitmap_zero(tp->wk.flags, RTL_FLAG_MAX);
6317
6318         rtl_unlock_work(tp);
6319
6320         rtl_pll_power_down(tp);
6321 }
6322
6323 #ifdef CONFIG_PM
6324
6325 static int rtl8169_suspend(struct device *device)
6326 {
6327         struct net_device *dev = dev_get_drvdata(device);
6328         struct rtl8169_private *tp = netdev_priv(dev);
6329
6330         rtl8169_net_suspend(dev);
6331         clk_disable_unprepare(tp->clk);
6332
6333         return 0;
6334 }
6335
6336 static void __rtl8169_resume(struct net_device *dev)
6337 {
6338         struct rtl8169_private *tp = netdev_priv(dev);
6339
6340         netif_device_attach(dev);
6341
6342         rtl_pll_power_up(tp);
6343         rtl8169_init_phy(dev, tp);
6344
6345         phy_start(tp->phydev);
6346
6347         rtl_lock_work(tp);
6348         napi_enable(&tp->napi);
6349         set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6350         rtl_reset_work(tp);
6351         rtl_unlock_work(tp);
6352 }
6353
6354 static int rtl8169_resume(struct device *device)
6355 {
6356         struct net_device *dev = dev_get_drvdata(device);
6357         struct rtl8169_private *tp = netdev_priv(dev);
6358
6359         rtl_rar_set(tp, dev->dev_addr);
6360
6361         clk_prepare_enable(tp->clk);
6362
6363         if (netif_running(dev))
6364                 __rtl8169_resume(dev);
6365
6366         return 0;
6367 }
6368
6369 static int rtl8169_runtime_suspend(struct device *device)
6370 {
6371         struct net_device *dev = dev_get_drvdata(device);
6372         struct rtl8169_private *tp = netdev_priv(dev);
6373
6374         if (!tp->TxDescArray)
6375                 return 0;
6376
6377         rtl_lock_work(tp);
6378         __rtl8169_set_wol(tp, WAKE_ANY);
6379         rtl_unlock_work(tp);
6380
6381         rtl8169_net_suspend(dev);
6382
6383         /* Update counters before going runtime suspend */
6384         rtl8169_rx_missed(dev);
6385         rtl8169_update_counters(tp);
6386
6387         return 0;
6388 }
6389
6390 static int rtl8169_runtime_resume(struct device *device)
6391 {
6392         struct net_device *dev = dev_get_drvdata(device);
6393         struct rtl8169_private *tp = netdev_priv(dev);
6394
6395         rtl_rar_set(tp, dev->dev_addr);
6396
6397         if (!tp->TxDescArray)
6398                 return 0;
6399
6400         rtl_lock_work(tp);
6401         __rtl8169_set_wol(tp, tp->saved_wolopts);
6402         rtl_unlock_work(tp);
6403
6404         __rtl8169_resume(dev);
6405
6406         return 0;
6407 }
6408
6409 static int rtl8169_runtime_idle(struct device *device)
6410 {
6411         struct net_device *dev = dev_get_drvdata(device);
6412
6413         if (!netif_running(dev) || !netif_carrier_ok(dev))
6414                 pm_schedule_suspend(device, 10000);
6415
6416         return -EBUSY;
6417 }
6418
6419 static const struct dev_pm_ops rtl8169_pm_ops = {
6420         .suspend                = rtl8169_suspend,
6421         .resume                 = rtl8169_resume,
6422         .freeze                 = rtl8169_suspend,
6423         .thaw                   = rtl8169_resume,
6424         .poweroff               = rtl8169_suspend,
6425         .restore                = rtl8169_resume,
6426         .runtime_suspend        = rtl8169_runtime_suspend,
6427         .runtime_resume         = rtl8169_runtime_resume,
6428         .runtime_idle           = rtl8169_runtime_idle,
6429 };
6430
6431 #define RTL8169_PM_OPS  (&rtl8169_pm_ops)
6432
6433 #else /* !CONFIG_PM */
6434
6435 #define RTL8169_PM_OPS  NULL
6436
6437 #endif /* !CONFIG_PM */
6438
6439 static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
6440 {
6441         /* WoL fails with 8168b when the receiver is disabled. */
6442         switch (tp->mac_version) {
6443         case RTL_GIGA_MAC_VER_11:
6444         case RTL_GIGA_MAC_VER_12:
6445         case RTL_GIGA_MAC_VER_17:
6446                 pci_clear_master(tp->pci_dev);
6447
6448                 RTL_W8(tp, ChipCmd, CmdRxEnb);
6449                 /* PCI commit */
6450                 RTL_R8(tp, ChipCmd);
6451                 break;
6452         default:
6453                 break;
6454         }
6455 }
6456
6457 static void rtl_shutdown(struct pci_dev *pdev)
6458 {
6459         struct net_device *dev = pci_get_drvdata(pdev);
6460         struct rtl8169_private *tp = netdev_priv(dev);
6461
6462         rtl8169_net_suspend(dev);
6463
6464         /* Restore original MAC address */
6465         rtl_rar_set(tp, dev->perm_addr);
6466
6467         rtl8169_hw_reset(tp);
6468
6469         if (system_state == SYSTEM_POWER_OFF) {
6470                 if (tp->saved_wolopts) {
6471                         rtl_wol_suspend_quirk(tp);
6472                         rtl_wol_shutdown_quirk(tp);
6473                 }
6474
6475                 pci_wake_from_d3(pdev, true);
6476                 pci_set_power_state(pdev, PCI_D3hot);
6477         }
6478 }
6479
6480 static void rtl_remove_one(struct pci_dev *pdev)
6481 {
6482         struct net_device *dev = pci_get_drvdata(pdev);
6483         struct rtl8169_private *tp = netdev_priv(dev);
6484
6485         if (r8168_check_dash(tp))
6486                 rtl8168_driver_stop(tp);
6487
6488         netif_napi_del(&tp->napi);
6489
6490         unregister_netdev(dev);
6491         mdiobus_unregister(tp->phydev->mdio.bus);
6492
6493         rtl_release_firmware(tp);
6494
6495         if (pci_dev_run_wake(pdev))
6496                 pm_runtime_get_noresume(&pdev->dev);
6497
6498         /* restore original MAC address */
6499         rtl_rar_set(tp, dev->perm_addr);
6500 }
6501
6502 static const struct net_device_ops rtl_netdev_ops = {
6503         .ndo_open               = rtl_open,
6504         .ndo_stop               = rtl8169_close,
6505         .ndo_get_stats64        = rtl8169_get_stats64,
6506         .ndo_start_xmit         = rtl8169_start_xmit,
6507         .ndo_features_check     = rtl8169_features_check,
6508         .ndo_tx_timeout         = rtl8169_tx_timeout,
6509         .ndo_validate_addr      = eth_validate_addr,
6510         .ndo_change_mtu         = rtl8169_change_mtu,
6511         .ndo_fix_features       = rtl8169_fix_features,
6512         .ndo_set_features       = rtl8169_set_features,
6513         .ndo_set_mac_address    = rtl_set_mac_address,
6514         .ndo_do_ioctl           = rtl8169_ioctl,
6515         .ndo_set_rx_mode        = rtl_set_rx_mode,
6516 #ifdef CONFIG_NET_POLL_CONTROLLER
6517         .ndo_poll_controller    = rtl8169_netpoll,
6518 #endif
6519
6520 };
6521
6522 static void rtl_set_irq_mask(struct rtl8169_private *tp)
6523 {
6524         tp->irq_mask = RTL_EVENT_NAPI | LinkChg;
6525
6526         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
6527                 tp->irq_mask |= SYSErr | RxOverflow | RxFIFOOver;
6528         else if (tp->mac_version == RTL_GIGA_MAC_VER_11)
6529                 /* special workaround needed */
6530                 tp->irq_mask |= RxFIFOOver;
6531         else
6532                 tp->irq_mask |= RxOverflow;
6533 }
6534
6535 static int rtl_alloc_irq(struct rtl8169_private *tp)
6536 {
6537         unsigned int flags;
6538
6539         if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
6540                 rtl_unlock_config_regs(tp);
6541                 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~MSIEnable);
6542                 rtl_lock_config_regs(tp);
6543                 flags = PCI_IRQ_LEGACY;
6544         } else {
6545                 flags = PCI_IRQ_ALL_TYPES;
6546         }
6547
6548         return pci_alloc_irq_vectors(tp->pci_dev, 1, 1, flags);
6549 }
6550
6551 static void rtl_read_mac_address(struct rtl8169_private *tp,
6552                                  u8 mac_addr[ETH_ALEN])
6553 {
6554         /* Get MAC address */
6555         if (rtl_is_8168evl_up(tp) && tp->mac_version != RTL_GIGA_MAC_VER_34) {
6556                 u32 value = rtl_eri_read(tp, 0xe0);
6557
6558                 mac_addr[0] = (value >>  0) & 0xff;
6559                 mac_addr[1] = (value >>  8) & 0xff;
6560                 mac_addr[2] = (value >> 16) & 0xff;
6561                 mac_addr[3] = (value >> 24) & 0xff;
6562
6563                 value = rtl_eri_read(tp, 0xe4);
6564                 mac_addr[4] = (value >>  0) & 0xff;
6565                 mac_addr[5] = (value >>  8) & 0xff;
6566         }
6567 }
6568
6569 DECLARE_RTL_COND(rtl_link_list_ready_cond)
6570 {
6571         return RTL_R8(tp, MCU) & LINK_LIST_RDY;
6572 }
6573
6574 DECLARE_RTL_COND(rtl_rxtx_empty_cond)
6575 {
6576         return (RTL_R8(tp, MCU) & RXTX_EMPTY) == RXTX_EMPTY;
6577 }
6578
6579 static int r8169_mdio_read_reg(struct mii_bus *mii_bus, int phyaddr, int phyreg)
6580 {
6581         struct rtl8169_private *tp = mii_bus->priv;
6582
6583         if (phyaddr > 0)
6584                 return -ENODEV;
6585
6586         return rtl_readphy(tp, phyreg);
6587 }
6588
6589 static int r8169_mdio_write_reg(struct mii_bus *mii_bus, int phyaddr,
6590                                 int phyreg, u16 val)
6591 {
6592         struct rtl8169_private *tp = mii_bus->priv;
6593
6594         if (phyaddr > 0)
6595                 return -ENODEV;
6596
6597         rtl_writephy(tp, phyreg, val);
6598
6599         return 0;
6600 }
6601
6602 static int r8169_mdio_register(struct rtl8169_private *tp)
6603 {
6604         struct pci_dev *pdev = tp->pci_dev;
6605         struct mii_bus *new_bus;
6606         int ret;
6607
6608         new_bus = devm_mdiobus_alloc(&pdev->dev);
6609         if (!new_bus)
6610                 return -ENOMEM;
6611
6612         new_bus->name = "r8169";
6613         new_bus->priv = tp;
6614         new_bus->parent = &pdev->dev;
6615         new_bus->irq[0] = PHY_IGNORE_INTERRUPT;
6616         snprintf(new_bus->id, MII_BUS_ID_SIZE, "r8169-%x", pci_dev_id(pdev));
6617
6618         new_bus->read = r8169_mdio_read_reg;
6619         new_bus->write = r8169_mdio_write_reg;
6620
6621         ret = mdiobus_register(new_bus);
6622         if (ret)
6623                 return ret;
6624
6625         tp->phydev = mdiobus_get_phy(new_bus, 0);
6626         if (!tp->phydev) {
6627                 mdiobus_unregister(new_bus);
6628                 return -ENODEV;
6629         }
6630
6631         /* PHY will be woken up in rtl_open() */
6632         phy_suspend(tp->phydev);
6633
6634         return 0;
6635 }
6636
6637 static void rtl_hw_init_8168g(struct rtl8169_private *tp)
6638 {
6639         tp->ocp_base = OCP_STD_PHY_BASE;
6640
6641         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN);
6642
6643         if (!rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42))
6644                 return;
6645
6646         if (!rtl_udelay_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42))
6647                 return;
6648
6649         RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
6650         msleep(1);
6651         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
6652
6653         r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0);
6654
6655         if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
6656                 return;
6657
6658         r8168_mac_ocp_modify(tp, 0xe8de, 0, BIT(15));
6659
6660         rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42);
6661 }
6662
6663 static void rtl_hw_initialize(struct rtl8169_private *tp)
6664 {
6665         switch (tp->mac_version) {
6666         case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_51:
6667                 rtl8168ep_stop_cmac(tp);
6668                 /* fall through */
6669         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_48:
6670                 rtl_hw_init_8168g(tp);
6671                 break;
6672         default:
6673                 break;
6674         }
6675 }
6676
6677 static int rtl_jumbo_max(struct rtl8169_private *tp)
6678 {
6679         /* Non-GBit versions don't support jumbo frames */
6680         if (!tp->supports_gmii)
6681                 return JUMBO_1K;
6682
6683         switch (tp->mac_version) {
6684         /* RTL8169 */
6685         case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
6686                 return JUMBO_7K;
6687         /* RTL8168b */
6688         case RTL_GIGA_MAC_VER_11:
6689         case RTL_GIGA_MAC_VER_12:
6690         case RTL_GIGA_MAC_VER_17:
6691                 return JUMBO_4K;
6692         /* RTL8168c */
6693         case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
6694                 return JUMBO_6K;
6695         default:
6696                 return JUMBO_9K;
6697         }
6698 }
6699
6700 static void rtl_disable_clk(void *data)
6701 {
6702         clk_disable_unprepare(data);
6703 }
6704
6705 static int rtl_get_ether_clk(struct rtl8169_private *tp)
6706 {
6707         struct device *d = tp_to_dev(tp);
6708         struct clk *clk;
6709         int rc;
6710
6711         clk = devm_clk_get(d, "ether_clk");
6712         if (IS_ERR(clk)) {
6713                 rc = PTR_ERR(clk);
6714                 if (rc == -ENOENT)
6715                         /* clk-core allows NULL (for suspend / resume) */
6716                         rc = 0;
6717                 else if (rc != -EPROBE_DEFER)
6718                         dev_err(d, "failed to get clk: %d\n", rc);
6719         } else {
6720                 tp->clk = clk;
6721                 rc = clk_prepare_enable(clk);
6722                 if (rc)
6723                         dev_err(d, "failed to enable clk: %d\n", rc);
6724                 else
6725                         rc = devm_add_action_or_reset(d, rtl_disable_clk, clk);
6726         }
6727
6728         return rc;
6729 }
6730
6731 static void rtl_init_mac_address(struct rtl8169_private *tp)
6732 {
6733         struct net_device *dev = tp->dev;
6734         u8 *mac_addr = dev->dev_addr;
6735         int rc, i;
6736
6737         rc = eth_platform_get_mac_address(tp_to_dev(tp), mac_addr);
6738         if (!rc)
6739                 goto done;
6740
6741         rtl_read_mac_address(tp, mac_addr);
6742         if (is_valid_ether_addr(mac_addr))
6743                 goto done;
6744
6745         for (i = 0; i < ETH_ALEN; i++)
6746                 mac_addr[i] = RTL_R8(tp, MAC0 + i);
6747         if (is_valid_ether_addr(mac_addr))
6748                 goto done;
6749
6750         eth_hw_addr_random(dev);
6751         dev_warn(tp_to_dev(tp), "can't read MAC address, setting random one\n");
6752 done:
6753         rtl_rar_set(tp, mac_addr);
6754 }
6755
6756 static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
6757 {
6758         struct rtl8169_private *tp;
6759         struct net_device *dev;
6760         int chipset, region;
6761         int jumbo_max, rc;
6762
6763         dev = devm_alloc_etherdev(&pdev->dev, sizeof (*tp));
6764         if (!dev)
6765                 return -ENOMEM;
6766
6767         SET_NETDEV_DEV(dev, &pdev->dev);
6768         dev->netdev_ops = &rtl_netdev_ops;
6769         tp = netdev_priv(dev);
6770         tp->dev = dev;
6771         tp->pci_dev = pdev;
6772         tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
6773         tp->supports_gmii = ent->driver_data == RTL_CFG_NO_GBIT ? 0 : 1;
6774
6775         /* Get the *optional* external "ether_clk" used on some boards */
6776         rc = rtl_get_ether_clk(tp);
6777         if (rc)
6778                 return rc;
6779
6780         /* Disable ASPM completely as that cause random device stop working
6781          * problems as well as full system hangs for some PCIe devices users.
6782          */
6783         rc = pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S |
6784                                           PCIE_LINK_STATE_L1);
6785         tp->aspm_manageable = !rc;
6786
6787         /* enable device (incl. PCI PM wakeup and hotplug setup) */
6788         rc = pcim_enable_device(pdev);
6789         if (rc < 0) {
6790                 dev_err(&pdev->dev, "enable failure\n");
6791                 return rc;
6792         }
6793
6794         if (pcim_set_mwi(pdev) < 0)
6795                 dev_info(&pdev->dev, "Mem-Wr-Inval unavailable\n");
6796
6797         /* use first MMIO region */
6798         region = ffs(pci_select_bars(pdev, IORESOURCE_MEM)) - 1;
6799         if (region < 0) {
6800                 dev_err(&pdev->dev, "no MMIO resource found\n");
6801                 return -ENODEV;
6802         }
6803
6804         /* check for weird/broken PCI region reporting */
6805         if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
6806                 dev_err(&pdev->dev, "Invalid PCI region size(s), aborting\n");
6807                 return -ENODEV;
6808         }
6809
6810         rc = pcim_iomap_regions(pdev, BIT(region), MODULENAME);
6811         if (rc < 0) {
6812                 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
6813                 return rc;
6814         }
6815
6816         tp->mmio_addr = pcim_iomap_table(pdev)[region];
6817
6818         /* Identify chip attached to board */
6819         rtl8169_get_mac_version(tp);
6820         if (tp->mac_version == RTL_GIGA_MAC_NONE)
6821                 return -ENODEV;
6822
6823         tp->cp_cmd = RTL_R16(tp, CPlusCmd);
6824
6825         if (sizeof(dma_addr_t) > 4 && tp->mac_version >= RTL_GIGA_MAC_VER_18 &&
6826             !dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)))
6827                 dev->features |= NETIF_F_HIGHDMA;
6828
6829         rtl_init_rxcfg(tp);
6830
6831         rtl8169_irq_mask_and_ack(tp);
6832
6833         rtl_hw_initialize(tp);
6834
6835         rtl_hw_reset(tp);
6836
6837         pci_set_master(pdev);
6838
6839         chipset = tp->mac_version;
6840
6841         rc = rtl_alloc_irq(tp);
6842         if (rc < 0) {
6843                 dev_err(&pdev->dev, "Can't allocate interrupt\n");
6844                 return rc;
6845         }
6846
6847         mutex_init(&tp->wk.mutex);
6848         INIT_WORK(&tp->wk.work, rtl_task);
6849         u64_stats_init(&tp->rx_stats.syncp);
6850         u64_stats_init(&tp->tx_stats.syncp);
6851
6852         rtl_init_mac_address(tp);
6853
6854         dev->ethtool_ops = &rtl8169_ethtool_ops;
6855
6856         netif_napi_add(dev, &tp->napi, rtl8169_poll, NAPI_POLL_WEIGHT);
6857
6858         dev->features |= NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
6859                 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_TX |
6860                 NETIF_F_HW_VLAN_CTAG_RX;
6861         dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
6862                 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_TX |
6863                 NETIF_F_HW_VLAN_CTAG_RX;
6864         dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
6865                 NETIF_F_HIGHDMA;
6866         dev->priv_flags |= IFF_LIVE_ADDR_CHANGE;
6867
6868         tp->cp_cmd |= RxChkSum | RxVlan;
6869
6870         /*
6871          * Pretend we are using VLANs; This bypasses a nasty bug where
6872          * Interrupts stop flowing on high load on 8110SCd controllers.
6873          */
6874         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
6875                 /* Disallow toggling */
6876                 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX;
6877
6878         if (rtl_chip_supports_csum_v2(tp)) {
6879                 dev->hw_features |= NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
6880                 dev->features |= NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
6881                 dev->gso_max_size = RTL_GSO_MAX_SIZE_V2;
6882                 dev->gso_max_segs = RTL_GSO_MAX_SEGS_V2;
6883         } else {
6884                 dev->gso_max_size = RTL_GSO_MAX_SIZE_V1;
6885                 dev->gso_max_segs = RTL_GSO_MAX_SEGS_V1;
6886         }
6887
6888         /* RTL8168e-vl has a HW issue with TSO */
6889         if (tp->mac_version == RTL_GIGA_MAC_VER_34) {
6890                 dev->vlan_features &= ~NETIF_F_ALL_TSO;
6891                 dev->hw_features &= ~NETIF_F_ALL_TSO;
6892                 dev->features &= ~NETIF_F_ALL_TSO;
6893         }
6894
6895         dev->hw_features |= NETIF_F_RXALL;
6896         dev->hw_features |= NETIF_F_RXFCS;
6897
6898         /* MTU range: 60 - hw-specific max */
6899         dev->min_mtu = ETH_ZLEN;
6900         jumbo_max = rtl_jumbo_max(tp);
6901         dev->max_mtu = jumbo_max;
6902
6903         rtl_set_irq_mask(tp);
6904
6905         tp->fw_name = rtl_chip_infos[chipset].fw_name;
6906
6907         tp->counters = dmam_alloc_coherent (&pdev->dev, sizeof(*tp->counters),
6908                                             &tp->counters_phys_addr,
6909                                             GFP_KERNEL);
6910         if (!tp->counters)
6911                 return -ENOMEM;
6912
6913         pci_set_drvdata(pdev, dev);
6914
6915         rc = r8169_mdio_register(tp);
6916         if (rc)
6917                 return rc;
6918
6919         /* chip gets powered up in rtl_open() */
6920         rtl_pll_power_down(tp);
6921
6922         rc = register_netdev(dev);
6923         if (rc)
6924                 goto err_mdio_unregister;
6925
6926         netif_info(tp, probe, dev, "%s, %pM, XID %03x, IRQ %d\n",
6927                    rtl_chip_infos[chipset].name, dev->dev_addr,
6928                    (RTL_R32(tp, TxConfig) >> 20) & 0xfcf,
6929                    pci_irq_vector(pdev, 0));
6930
6931         if (jumbo_max > JUMBO_1K)
6932                 netif_info(tp, probe, dev,
6933                            "jumbo features [frames: %d bytes, tx checksumming: %s]\n",
6934                            jumbo_max, tp->mac_version <= RTL_GIGA_MAC_VER_06 ?
6935                            "ok" : "ko");
6936
6937         if (r8168_check_dash(tp))
6938                 rtl8168_driver_start(tp);
6939
6940         if (pci_dev_run_wake(pdev))
6941                 pm_runtime_put_sync(&pdev->dev);
6942
6943         return 0;
6944
6945 err_mdio_unregister:
6946         mdiobus_unregister(tp->phydev->mdio.bus);
6947         return rc;
6948 }
6949
6950 static struct pci_driver rtl8169_pci_driver = {
6951         .name           = MODULENAME,
6952         .id_table       = rtl8169_pci_tbl,
6953         .probe          = rtl_init_one,
6954         .remove         = rtl_remove_one,
6955         .shutdown       = rtl_shutdown,
6956         .driver.pm      = RTL8169_PM_OPS,
6957 };
6958
6959 module_pci_driver(rtl8169_pci_driver);