drivers/net/ethernet/realtek/r8169_main.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * r8169.c: RealTek 8169/8168/8101 ethernet driver.
   4  *
   5  * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
   6  * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
   7  * Copyright (c) a lot of people too. Please respect their work.
   8  *
   9  * See MAINTAINERS file for support contact information.
  10  */
  11
  12 #include <linux/module.h>
  13 #include <linux/moduleparam.h>
  14 #include <linux/pci.h>
  15 #include <linux/netdevice.h>
  16 #include <linux/etherdevice.h>
  17 #include <linux/clk.h>
  18 #include <linux/delay.h>
  19 #include <linux/ethtool.h>
  20 #include <linux/phy.h>
  21 #include <linux/if_vlan.h>
  22 #include <linux/crc32.h>
  23 #include <linux/in.h>
  24 #include <linux/io.h>
  25 #include <linux/ip.h>
  26 #include <linux/tcp.h>
  27 #include <linux/interrupt.h>
  28 #include <linux/dma-mapping.h>
  29 #include <linux/pm_runtime.h>
  30 #include <linux/prefetch.h>
  31 #include <linux/pci-aspm.h>
  32 #include <linux/ipv6.h>
  33 #include <net/ip6_checksum.h>
  34
  35 #include "r8169_firmware.h"
  36
  37 #define MODULENAME "r8169"
  38
  39 #define FIRMWARE_8168D_1        "rtl_nic/rtl8168d-1.fw"
  40 #define FIRMWARE_8168D_2        "rtl_nic/rtl8168d-2.fw"
  41 #define FIRMWARE_8168E_1        "rtl_nic/rtl8168e-1.fw"
  42 #define FIRMWARE_8168E_2        "rtl_nic/rtl8168e-2.fw"
  43 #define FIRMWARE_8168E_3        "rtl_nic/rtl8168e-3.fw"
  44 #define FIRMWARE_8168F_1        "rtl_nic/rtl8168f-1.fw"
  45 #define FIRMWARE_8168F_2        "rtl_nic/rtl8168f-2.fw"
  46 #define FIRMWARE_8105E_1        "rtl_nic/rtl8105e-1.fw"
  47 #define FIRMWARE_8402_1         "rtl_nic/rtl8402-1.fw"
  48 #define FIRMWARE_8411_1         "rtl_nic/rtl8411-1.fw"
  49 #define FIRMWARE_8411_2         "rtl_nic/rtl8411-2.fw"
  50 #define FIRMWARE_8106E_1        "rtl_nic/rtl8106e-1.fw"
  51 #define FIRMWARE_8106E_2        "rtl_nic/rtl8106e-2.fw"
  52 #define FIRMWARE_8168G_2        "rtl_nic/rtl8168g-2.fw"
  53 #define FIRMWARE_8168G_3        "rtl_nic/rtl8168g-3.fw"
  54 #define FIRMWARE_8168H_1        "rtl_nic/rtl8168h-1.fw"
  55 #define FIRMWARE_8168H_2        "rtl_nic/rtl8168h-2.fw"
  56 #define FIRMWARE_8107E_1        "rtl_nic/rtl8107e-1.fw"
  57 #define FIRMWARE_8107E_2        "rtl_nic/rtl8107e-2.fw"
  58
  59 #define R8169_MSG_DEFAULT \
  60         (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
  61
  62 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
  63    The RTL chips use a 64 element hash table based on the Ethernet CRC. */
  64 #define MC_FILTER_LIMIT 32
  65
  66 #define TX_DMA_BURST    7       /* Maximum PCI burst, '7' is unlimited */
  67 #define InterFrameGap   0x03    /* 3 means InterFrameGap = the shortest one */
  68
  69 #define R8169_REGS_SIZE         256
  70 #define R8169_RX_BUF_SIZE       (SZ_16K - 1)
  71 #define NUM_TX_DESC     64      /* Number of Tx descriptor registers */
  72 #define NUM_RX_DESC     256U    /* Number of Rx descriptor registers */
  73 #define R8169_TX_RING_BYTES     (NUM_TX_DESC * sizeof(struct TxDesc))
  74 #define R8169_RX_RING_BYTES     (NUM_RX_DESC * sizeof(struct RxDesc))
  75
  76 #define RTL_CFG_NO_GBIT 1
  77
  78 /* write/read MMIO register */
  79 #define RTL_W8(tp, reg, val8)   writeb((val8), tp->mmio_addr + (reg))
  80 #define RTL_W16(tp, reg, val16) writew((val16), tp->mmio_addr + (reg))
  81 #define RTL_W32(tp, reg, val32) writel((val32), tp->mmio_addr + (reg))
  82 #define RTL_R8(tp, reg)         readb(tp->mmio_addr + (reg))
  83 #define RTL_R16(tp, reg)                readw(tp->mmio_addr + (reg))
  84 #define RTL_R32(tp, reg)                readl(tp->mmio_addr + (reg))
  85
  86 enum mac_version {
  87         /* support for ancient RTL_GIGA_MAC_VER_01 has been removed */
  88         RTL_GIGA_MAC_VER_02,
  89         RTL_GIGA_MAC_VER_03,
  90         RTL_GIGA_MAC_VER_04,
  91         RTL_GIGA_MAC_VER_05,
  92         RTL_GIGA_MAC_VER_06,
  93         RTL_GIGA_MAC_VER_07,
  94         RTL_GIGA_MAC_VER_08,
  95         RTL_GIGA_MAC_VER_09,
  96         RTL_GIGA_MAC_VER_10,
  97         RTL_GIGA_MAC_VER_11,
  98         RTL_GIGA_MAC_VER_12,
  99         RTL_GIGA_MAC_VER_13,
 100         RTL_GIGA_MAC_VER_14,
 101         RTL_GIGA_MAC_VER_15,
 102         RTL_GIGA_MAC_VER_16,
 103         RTL_GIGA_MAC_VER_17,
 104         RTL_GIGA_MAC_VER_18,
 105         RTL_GIGA_MAC_VER_19,
 106         RTL_GIGA_MAC_VER_20,
 107         RTL_GIGA_MAC_VER_21,
 108         RTL_GIGA_MAC_VER_22,
 109         RTL_GIGA_MAC_VER_23,
 110         RTL_GIGA_MAC_VER_24,
 111         RTL_GIGA_MAC_VER_25,
 112         RTL_GIGA_MAC_VER_26,
 113         RTL_GIGA_MAC_VER_27,
 114         RTL_GIGA_MAC_VER_28,
 115         RTL_GIGA_MAC_VER_29,
 116         RTL_GIGA_MAC_VER_30,
 117         RTL_GIGA_MAC_VER_31,
 118         RTL_GIGA_MAC_VER_32,
 119         RTL_GIGA_MAC_VER_33,
 120         RTL_GIGA_MAC_VER_34,
 121         RTL_GIGA_MAC_VER_35,
 122         RTL_GIGA_MAC_VER_36,
 123         RTL_GIGA_MAC_VER_37,
 124         RTL_GIGA_MAC_VER_38,
 125         RTL_GIGA_MAC_VER_39,
 126         RTL_GIGA_MAC_VER_40,
 127         RTL_GIGA_MAC_VER_41,
 128         RTL_GIGA_MAC_VER_42,
 129         RTL_GIGA_MAC_VER_43,
 130         RTL_GIGA_MAC_VER_44,
 131         RTL_GIGA_MAC_VER_45,
 132         RTL_GIGA_MAC_VER_46,
 133         RTL_GIGA_MAC_VER_47,
 134         RTL_GIGA_MAC_VER_48,
 135         RTL_GIGA_MAC_VER_49,
 136         RTL_GIGA_MAC_VER_50,
 137         RTL_GIGA_MAC_VER_51,
 138         RTL_GIGA_MAC_NONE
 139 };
 140
 141 #define JUMBO_1K        ETH_DATA_LEN
 142 #define JUMBO_4K        (4*1024 - ETH_HLEN - 2)
 143 #define JUMBO_6K        (6*1024 - ETH_HLEN - 2)
 144 #define JUMBO_7K        (7*1024 - ETH_HLEN - 2)
 145 #define JUMBO_9K        (9*1024 - ETH_HLEN - 2)
 146
 147 static const struct {
 148         const char *name;
 149         const char *fw_name;
 150 } rtl_chip_infos[] = {
 151         /* PCI devices. */
 152         [RTL_GIGA_MAC_VER_02] = {"RTL8169s"                             },
 153         [RTL_GIGA_MAC_VER_03] = {"RTL8110s"                             },
 154         [RTL_GIGA_MAC_VER_04] = {"RTL8169sb/8110sb"                     },
 155         [RTL_GIGA_MAC_VER_05] = {"RTL8169sc/8110sc"                     },
 156         [RTL_GIGA_MAC_VER_06] = {"RTL8169sc/8110sc"                     },
 157         /* PCI-E devices. */
 158         [RTL_GIGA_MAC_VER_07] = {"RTL8102e"                             },
 159         [RTL_GIGA_MAC_VER_08] = {"RTL8102e"                             },
 160         [RTL_GIGA_MAC_VER_09] = {"RTL8102e/RTL8103e"                    },
 161         [RTL_GIGA_MAC_VER_10] = {"RTL8101e"                             },
 162         [RTL_GIGA_MAC_VER_11] = {"RTL8168b/8111b"                       },
 163         [RTL_GIGA_MAC_VER_12] = {"RTL8168b/8111b"                       },
 164         [RTL_GIGA_MAC_VER_13] = {"RTL8101e"                             },
 165         [RTL_GIGA_MAC_VER_14] = {"RTL8100e"                             },
 166         [RTL_GIGA_MAC_VER_15] = {"RTL8100e"                             },
 167         [RTL_GIGA_MAC_VER_16] = {"RTL8101e"                             },
 168         [RTL_GIGA_MAC_VER_17] = {"RTL8168b/8111b"                       },
 169         [RTL_GIGA_MAC_VER_18] = {"RTL8168cp/8111cp"                     },
 170         [RTL_GIGA_MAC_VER_19] = {"RTL8168c/8111c"                       },
 171         [RTL_GIGA_MAC_VER_20] = {"RTL8168c/8111c"                       },
 172         [RTL_GIGA_MAC_VER_21] = {"RTL8168c/8111c"                       },
 173         [RTL_GIGA_MAC_VER_22] = {"RTL8168c/8111c"                       },
 174         [RTL_GIGA_MAC_VER_23] = {"RTL8168cp/8111cp"                     },
 175         [RTL_GIGA_MAC_VER_24] = {"RTL8168cp/8111cp"                     },
 176         [RTL_GIGA_MAC_VER_25] = {"RTL8168d/8111d",      FIRMWARE_8168D_1},
 177         [RTL_GIGA_MAC_VER_26] = {"RTL8168d/8111d",      FIRMWARE_8168D_2},
 178         [RTL_GIGA_MAC_VER_27] = {"RTL8168dp/8111dp"                     },
 179         [RTL_GIGA_MAC_VER_28] = {"RTL8168dp/8111dp"                     },
 180         [RTL_GIGA_MAC_VER_29] = {"RTL8105e",            FIRMWARE_8105E_1},
 181         [RTL_GIGA_MAC_VER_30] = {"RTL8105e",            FIRMWARE_8105E_1},
 182         [RTL_GIGA_MAC_VER_31] = {"RTL8168dp/8111dp"                     },
 183         [RTL_GIGA_MAC_VER_32] = {"RTL8168e/8111e",      FIRMWARE_8168E_1},
 184         [RTL_GIGA_MAC_VER_33] = {"RTL8168e/8111e",      FIRMWARE_8168E_2},
 185         [RTL_GIGA_MAC_VER_34] = {"RTL8168evl/8111evl",  FIRMWARE_8168E_3},
 186         [RTL_GIGA_MAC_VER_35] = {"RTL8168f/8111f",      FIRMWARE_8168F_1},
 187         [RTL_GIGA_MAC_VER_36] = {"RTL8168f/8111f",      FIRMWARE_8168F_2},
 188         [RTL_GIGA_MAC_VER_37] = {"RTL8402",             FIRMWARE_8402_1 },
 189         [RTL_GIGA_MAC_VER_38] = {"RTL8411",             FIRMWARE_8411_1 },
 190         [RTL_GIGA_MAC_VER_39] = {"RTL8106e",            FIRMWARE_8106E_1},
 191         [RTL_GIGA_MAC_VER_40] = {"RTL8168g/8111g",      FIRMWARE_8168G_2},
 192         [RTL_GIGA_MAC_VER_41] = {"RTL8168g/8111g"                       },
 193         [RTL_GIGA_MAC_VER_42] = {"RTL8168gu/8111gu",    FIRMWARE_8168G_3},
 194         [RTL_GIGA_MAC_VER_43] = {"RTL8106eus",          FIRMWARE_8106E_2},
 195         [RTL_GIGA_MAC_VER_44] = {"RTL8411b",            FIRMWARE_8411_2 },
 196         [RTL_GIGA_MAC_VER_45] = {"RTL8168h/8111h",      FIRMWARE_8168H_1},
 197         [RTL_GIGA_MAC_VER_46] = {"RTL8168h/8111h",      FIRMWARE_8168H_2},
 198         [RTL_GIGA_MAC_VER_47] = {"RTL8107e",            FIRMWARE_8107E_1},
 199         [RTL_GIGA_MAC_VER_48] = {"RTL8107e",            FIRMWARE_8107E_2},
 200         [RTL_GIGA_MAC_VER_49] = {"RTL8168ep/8111ep"                     },
 201         [RTL_GIGA_MAC_VER_50] = {"RTL8168ep/8111ep"                     },
 202         [RTL_GIGA_MAC_VER_51] = {"RTL8168ep/8111ep"                     },
 203 };
 204
 205 static const struct pci_device_id rtl8169_pci_tbl[] = {
 206         { PCI_VDEVICE(REALTEK,  0x2502) },
 207         { PCI_VDEVICE(REALTEK,  0x2600) },
 208         { PCI_VDEVICE(REALTEK,  0x8129) },
 209         { PCI_VDEVICE(REALTEK,  0x8136), RTL_CFG_NO_GBIT },
 210         { PCI_VDEVICE(REALTEK,  0x8161) },
 211         { PCI_VDEVICE(REALTEK,  0x8167) },
 212         { PCI_VDEVICE(REALTEK,  0x8168) },
 213         { PCI_VDEVICE(NCUBE,    0x8168) },
 214         { PCI_VDEVICE(REALTEK,  0x8169) },
 215         { PCI_VENDOR_ID_DLINK,  0x4300,
 216                 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0 },
 217         { PCI_VDEVICE(DLINK,    0x4300) },
 218         { PCI_VDEVICE(DLINK,    0x4302) },
 219         { PCI_VDEVICE(AT,       0xc107) },
 220         { PCI_VDEVICE(USR,      0x0116) },
 221         { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0024 },
 222         { 0x0001, 0x8168, PCI_ANY_ID, 0x2410 },
 223         {}
 224 };
 225
 226 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
 227
 228 static struct {
 229         u32 msg_enable;
 230 } debug = { -1 };
 231
 232 enum rtl_registers {
 233         MAC0            = 0,    /* Ethernet hardware address. */
 234         MAC4            = 4,
 235         MAR0            = 8,    /* Multicast filter. */
 236         CounterAddrLow          = 0x10,
 237         CounterAddrHigh         = 0x14,
 238         TxDescStartAddrLow      = 0x20,
 239         TxDescStartAddrHigh     = 0x24,
 240         TxHDescStartAddrLow     = 0x28,
 241         TxHDescStartAddrHigh    = 0x2c,
 242         FLASH           = 0x30,
 243         ERSR            = 0x36,
 244         ChipCmd         = 0x37,
 245         TxPoll          = 0x38,
 246         IntrMask        = 0x3c,
 247         IntrStatus      = 0x3e,
 248
 249         TxConfig        = 0x40,
 250 #define TXCFG_AUTO_FIFO                 (1 << 7)        /* 8111e-vl */
 251 #define TXCFG_EMPTY                     (1 << 11)       /* 8111e-vl */
 252
 253         RxConfig        = 0x44,
 254 #define RX128_INT_EN                    (1 << 15)       /* 8111c and later */
 255 #define RX_MULTI_EN                     (1 << 14)       /* 8111c only */
 256 #define RXCFG_FIFO_SHIFT                13
 257                                         /* No threshold before first PCI xfer */
 258 #define RX_FIFO_THRESH                  (7 << RXCFG_FIFO_SHIFT)
 259 #define RX_EARLY_OFF                    (1 << 11)
 260 #define RXCFG_DMA_SHIFT                 8
 261                                         /* Unlimited maximum PCI burst. */
 262 #define RX_DMA_BURST                    (7 << RXCFG_DMA_SHIFT)
 263
 264         RxMissed        = 0x4c,
 265         Cfg9346         = 0x50,
 266         Config0         = 0x51,
 267         Config1         = 0x52,
 268         Config2         = 0x53,
 269 #define PME_SIGNAL                      (1 << 5)        /* 8168c and later */
 270
 271         Config3         = 0x54,
 272         Config4         = 0x55,
 273         Config5         = 0x56,
 274         MultiIntr       = 0x5c,
 275         PHYAR           = 0x60,
 276         PHYstatus       = 0x6c,
 277         RxMaxSize       = 0xda,
 278         CPlusCmd        = 0xe0,
 279         IntrMitigate    = 0xe2,
 280
 281 #define RTL_COALESCE_MASK       0x0f
 282 #define RTL_COALESCE_SHIFT      4
 283 #define RTL_COALESCE_T_MAX      (RTL_COALESCE_MASK)
 284 #define RTL_COALESCE_FRAME_MAX  (RTL_COALESCE_MASK << 2)
 285
 286         RxDescAddrLow   = 0xe4,
 287         RxDescAddrHigh  = 0xe8,
 288         EarlyTxThres    = 0xec, /* 8169. Unit of 32 bytes. */
 289
 290 #define NoEarlyTx       0x3f    /* Max value : no early transmit. */
 291
 292         MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
 293
 294 #define TxPacketMax     (8064 >> 7)
 295 #define EarlySize       0x27
 296
 297         FuncEvent       = 0xf0,
 298         FuncEventMask   = 0xf4,
 299         FuncPresetState = 0xf8,
 300         IBCR0           = 0xf8,
 301         IBCR2           = 0xf9,
 302         IBIMR0          = 0xfa,
 303         IBISR0          = 0xfb,
 304         FuncForceEvent  = 0xfc,
 305 };
 306
 307 enum rtl8168_8101_registers {
 308         CSIDR                   = 0x64,
 309         CSIAR                   = 0x68,
 310 #define CSIAR_FLAG                      0x80000000
 311 #define CSIAR_WRITE_CMD                 0x80000000
 312 #define CSIAR_BYTE_ENABLE               0x0000f000
 313 #define CSIAR_ADDR_MASK                 0x00000fff
 314         PMCH                    = 0x6f,
 315         EPHYAR                  = 0x80,
 316 #define EPHYAR_FLAG                     0x80000000
 317 #define EPHYAR_WRITE_CMD                0x80000000
 318 #define EPHYAR_REG_MASK                 0x1f
 319 #define EPHYAR_REG_SHIFT                16
 320 #define EPHYAR_DATA_MASK                0xffff
 321         DLLPR                   = 0xd0,
 322 #define PFM_EN                          (1 << 6)
 323 #define TX_10M_PS_EN                    (1 << 7)
 324         DBG_REG                 = 0xd1,
 325 #define FIX_NAK_1                       (1 << 4)
 326 #define FIX_NAK_2                       (1 << 3)
 327         TWSI                    = 0xd2,
 328         MCU                     = 0xd3,
 329 #define NOW_IS_OOB                      (1 << 7)
 330 #define TX_EMPTY                        (1 << 5)
 331 #define RX_EMPTY                        (1 << 4)
 332 #define RXTX_EMPTY                      (TX_EMPTY | RX_EMPTY)
 333 #define EN_NDP                          (1 << 3)
 334 #define EN_OOB_RESET                    (1 << 2)
 335 #define LINK_LIST_RDY                   (1 << 1)
 336         EFUSEAR                 = 0xdc,
 337 #define EFUSEAR_FLAG                    0x80000000
 338 #define EFUSEAR_WRITE_CMD               0x80000000
 339 #define EFUSEAR_READ_CMD                0x00000000
 340 #define EFUSEAR_REG_MASK                0x03ff
 341 #define EFUSEAR_REG_SHIFT               8
 342 #define EFUSEAR_DATA_MASK               0xff
 343         MISC_1                  = 0xf2,
 344 #define PFM_D3COLD_EN                   (1 << 6)
 345 };
 346
 347 enum rtl8168_registers {
 348         LED_FREQ                = 0x1a,
 349         EEE_LED                 = 0x1b,
 350         ERIDR                   = 0x70,
 351         ERIAR                   = 0x74,
 352 #define ERIAR_FLAG                      0x80000000
 353 #define ERIAR_WRITE_CMD                 0x80000000
 354 #define ERIAR_READ_CMD                  0x00000000
 355 #define ERIAR_ADDR_BYTE_ALIGN           4
 356 #define ERIAR_TYPE_SHIFT                16
 357 #define ERIAR_EXGMAC                    (0x00 << ERIAR_TYPE_SHIFT)
 358 #define ERIAR_MSIX                      (0x01 << ERIAR_TYPE_SHIFT)
 359 #define ERIAR_ASF                       (0x02 << ERIAR_TYPE_SHIFT)
 360 #define ERIAR_OOB                       (0x02 << ERIAR_TYPE_SHIFT)
 361 #define ERIAR_MASK_SHIFT                12
 362 #define ERIAR_MASK_0001                 (0x1 << ERIAR_MASK_SHIFT)
 363 #define ERIAR_MASK_0011                 (0x3 << ERIAR_MASK_SHIFT)
 364 #define ERIAR_MASK_0100                 (0x4 << ERIAR_MASK_SHIFT)
 365 #define ERIAR_MASK_0101                 (0x5 << ERIAR_MASK_SHIFT)
 366 #define ERIAR_MASK_1111                 (0xf << ERIAR_MASK_SHIFT)
 367         EPHY_RXER_NUM           = 0x7c,
 368         OCPDR                   = 0xb0, /* OCP GPHY access */
 369 #define OCPDR_WRITE_CMD                 0x80000000
 370 #define OCPDR_READ_CMD                  0x00000000
 371 #define OCPDR_REG_MASK                  0x7f
 372 #define OCPDR_GPHY_REG_SHIFT            16
 373 #define OCPDR_DATA_MASK                 0xffff
 374         OCPAR                   = 0xb4,
 375 #define OCPAR_FLAG                      0x80000000
 376 #define OCPAR_GPHY_WRITE_CMD            0x8000f060
 377 #define OCPAR_GPHY_READ_CMD             0x0000f060
 378         GPHY_OCP                = 0xb8,
 379         RDSAR1                  = 0xd0, /* 8168c only. Undocumented on 8168dp */
 380         MISC                    = 0xf0, /* 8168e only. */
 381 #define TXPLA_RST                       (1 << 29)
 382 #define DISABLE_LAN_EN                  (1 << 23) /* Enable GPIO pin */
 383 #define PWM_EN                          (1 << 22)
 384 #define RXDV_GATED_EN                   (1 << 19)
 385 #define EARLY_TALLY_EN                  (1 << 16)
 386 };
 387
 388 enum rtl_register_content {
 389         /* InterruptStatusBits */
 390         SYSErr          = 0x8000,
 391         PCSTimeout      = 0x4000,
 392         SWInt           = 0x0100,
 393         TxDescUnavail   = 0x0080,
 394         RxFIFOOver      = 0x0040,
 395         LinkChg         = 0x0020,
 396         RxOverflow      = 0x0010,
 397         TxErr           = 0x0008,
 398         TxOK            = 0x0004,
 399         RxErr           = 0x0002,
 400         RxOK            = 0x0001,
 401
 402         /* RxStatusDesc */
 403         RxRWT   = (1 << 22),
 404         RxRES   = (1 << 21),
 405         RxRUNT  = (1 << 20),
 406         RxCRC   = (1 << 19),
 407
 408         /* ChipCmdBits */
 409         StopReq         = 0x80,
 410         CmdReset        = 0x10,
 411         CmdRxEnb        = 0x08,
 412         CmdTxEnb        = 0x04,
 413         RxBufEmpty      = 0x01,
 414
 415         /* TXPoll register p.5 */
 416         HPQ             = 0x80,         /* Poll cmd on the high prio queue */
 417         NPQ             = 0x40,         /* Poll cmd on the low prio queue */
 418         FSWInt          = 0x01,         /* Forced software interrupt */
 419
 420         /* Cfg9346Bits */
 421         Cfg9346_Lock    = 0x00,
 422         Cfg9346_Unlock  = 0xc0,
 423
 424         /* rx_mode_bits */
 425         AcceptErr       = 0x20,
 426         AcceptRunt      = 0x10,
 427         AcceptBroadcast = 0x08,
 428         AcceptMulticast = 0x04,
 429         AcceptMyPhys    = 0x02,
 430         AcceptAllPhys   = 0x01,
 431 #define RX_CONFIG_ACCEPT_MASK           0x3f
 432
 433         /* TxConfigBits */
 434         TxInterFrameGapShift = 24,
 435         TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
 436
 437         /* Config1 register p.24 */
 438         LEDS1           = (1 << 7),
 439         LEDS0           = (1 << 6),
 440         Speed_down      = (1 << 4),
 441         MEMMAP          = (1 << 3),
 442         IOMAP           = (1 << 2),
 443         VPD             = (1 << 1),
 444         PMEnable        = (1 << 0),     /* Power Management Enable */
 445
 446         /* Config2 register p. 25 */
 447         ClkReqEn        = (1 << 7),     /* Clock Request Enable */
 448         MSIEnable       = (1 << 5),     /* 8169 only. Reserved in the 8168. */
 449         PCI_Clock_66MHz = 0x01,
 450         PCI_Clock_33MHz = 0x00,
 451
 452         /* Config3 register p.25 */
 453         MagicPacket     = (1 << 5),     /* Wake up when receives a Magic Packet */
 454         LinkUp          = (1 << 4),     /* Wake up when the cable connection is re-established */
 455         Jumbo_En0       = (1 << 2),     /* 8168 only. Reserved in the 8168b */
 456         Rdy_to_L23      = (1 << 1),     /* L23 Enable */
 457         Beacon_en       = (1 << 0),     /* 8168 only. Reserved in the 8168b */
 458
 459         /* Config4 register */
 460         Jumbo_En1       = (1 << 1),     /* 8168 only. Reserved in the 8168b */
 461
 462         /* Config5 register p.27 */
 463         BWF             = (1 << 6),     /* Accept Broadcast wakeup frame */
 464         MWF             = (1 << 5),     /* Accept Multicast wakeup frame */
 465         UWF             = (1 << 4),     /* Accept Unicast wakeup frame */
 466         Spi_en          = (1 << 3),
 467         LanWake         = (1 << 1),     /* LanWake enable/disable */
 468         PMEStatus       = (1 << 0),     /* PME status can be reset by PCI RST# */
 469         ASPM_en         = (1 << 0),     /* ASPM enable */
 470
 471         /* CPlusCmd p.31 */
 472         EnableBist      = (1 << 15),    // 8168 8101
 473         Mac_dbgo_oe     = (1 << 14),    // 8168 8101
 474         Normal_mode     = (1 << 13),    // unused
 475         Force_half_dup  = (1 << 12),    // 8168 8101
 476         Force_rxflow_en = (1 << 11),    // 8168 8101
 477         Force_txflow_en = (1 << 10),    // 8168 8101
 478         Cxpl_dbg_sel    = (1 << 9),     // 8168 8101
 479         ASF             = (1 << 8),     // 8168 8101
 480         PktCntrDisable  = (1 << 7),     // 8168 8101
 481         Mac_dbgo_sel    = 0x001c,       // 8168
 482         RxVlan          = (1 << 6),
 483         RxChkSum        = (1 << 5),
 484         PCIDAC          = (1 << 4),
 485         PCIMulRW        = (1 << 3),
 486 #define INTT_MASK       GENMASK(1, 0)
 487 #define CPCMD_MASK      (Normal_mode | RxVlan | RxChkSum | INTT_MASK)
 488
 489         /* rtl8169_PHYstatus */
 490         TBI_Enable      = 0x80,
 491         TxFlowCtrl      = 0x40,
 492         RxFlowCtrl      = 0x20,
 493         _1000bpsF       = 0x10,
 494         _100bps         = 0x08,
 495         _10bps          = 0x04,
 496         LinkStatus      = 0x02,
 497         FullDup         = 0x01,
 498
 499         /* ResetCounterCommand */
 500         CounterReset    = 0x1,
 501
 502         /* DumpCounterCommand */
 503         CounterDump     = 0x8,
 504
 505         /* magic enable v2 */
 506         MagicPacket_v2  = (1 << 16),    /* Wake up when receives a Magic Packet */
 507 };
 508
 509 enum rtl_desc_bit {
 510         /* First doubleword. */
 511         DescOwn         = (1 << 31), /* Descriptor is owned by NIC */
 512         RingEnd         = (1 << 30), /* End of descriptor ring */
 513         FirstFrag       = (1 << 29), /* First segment of a packet */
 514         LastFrag        = (1 << 28), /* Final segment of a packet */
 515 };
 516
 517 /* Generic case. */
 518 enum rtl_tx_desc_bit {
 519         /* First doubleword. */
 520         TD_LSO          = (1 << 27),            /* Large Send Offload */
 521 #define TD_MSS_MAX                      0x07ffu /* MSS value */
 522
 523         /* Second doubleword. */
 524         TxVlanTag       = (1 << 17),            /* Add VLAN tag */
 525 };
 526
 527 /* 8169, 8168b and 810x except 8102e. */
 528 enum rtl_tx_desc_bit_0 {
 529         /* First doubleword. */
 530 #define TD0_MSS_SHIFT                   16      /* MSS position (11 bits) */
 531         TD0_TCP_CS      = (1 << 16),            /* Calculate TCP/IP checksum */
 532         TD0_UDP_CS      = (1 << 17),            /* Calculate UDP/IP checksum */
 533         TD0_IP_CS       = (1 << 18),            /* Calculate IP checksum */
 534 };
 535
 536 /* 8102e, 8168c and beyond. */
 537 enum rtl_tx_desc_bit_1 {
 538         /* First doubleword. */
 539         TD1_GTSENV4     = (1 << 26),            /* Giant Send for IPv4 */
 540         TD1_GTSENV6     = (1 << 25),            /* Giant Send for IPv6 */
 541 #define GTTCPHO_SHIFT                   18
 542 #define GTTCPHO_MAX                     0x7fU
 543
 544         /* Second doubleword. */
 545 #define TCPHO_SHIFT                     18
 546 #define TCPHO_MAX                       0x3ffU
 547 #define TD1_MSS_SHIFT                   18      /* MSS position (11 bits) */
 548         TD1_IPv6_CS     = (1 << 28),            /* Calculate IPv6 checksum */
 549         TD1_IPv4_CS     = (1 << 29),            /* Calculate IPv4 checksum */
 550         TD1_TCP_CS      = (1 << 30),            /* Calculate TCP/IP checksum */
 551         TD1_UDP_CS      = (1 << 31),            /* Calculate UDP/IP checksum */
 552 };
 553
 554 enum rtl_rx_desc_bit {
 555         /* Rx private */
 556         PID1            = (1 << 18), /* Protocol ID bit 1/2 */
 557         PID0            = (1 << 17), /* Protocol ID bit 0/2 */
 558
 559 #define RxProtoUDP      (PID1)
 560 #define RxProtoTCP      (PID0)
 561 #define RxProtoIP       (PID1 | PID0)
 562 #define RxProtoMask     RxProtoIP
 563
 564         IPFail          = (1 << 16), /* IP checksum failed */
 565         UDPFail         = (1 << 15), /* UDP/IP checksum failed */
 566         TCPFail         = (1 << 14), /* TCP/IP checksum failed */
 567         RxVlanTag       = (1 << 16), /* VLAN tag available */
 568 };
 569
 570 #define RsvdMask        0x3fffc000
 571
 572 struct TxDesc {
 573         __le32 opts1;
 574         __le32 opts2;
 575         __le64 addr;
 576 };
 577
 578 struct RxDesc {
 579         __le32 opts1;
 580         __le32 opts2;
 581         __le64 addr;
 582 };
 583
 584 struct ring_info {
 585         struct sk_buff  *skb;
 586         u32             len;
 587 };
 588
 589 struct rtl8169_counters {
 590         __le64  tx_packets;
 591         __le64  rx_packets;
 592         __le64  tx_errors;
 593         __le32  rx_errors;
 594         __le16  rx_missed;
 595         __le16  align_errors;
 596         __le32  tx_one_collision;
 597         __le32  tx_multi_collision;
 598         __le64  rx_unicast;
 599         __le64  rx_broadcast;
 600         __le32  rx_multicast;
 601         __le16  tx_aborted;
 602         __le16  tx_underun;
 603 };
 604
 605 struct rtl8169_tc_offsets {
 606         bool    inited;
 607         __le64  tx_errors;
 608         __le32  tx_multi_collision;
 609         __le16  tx_aborted;
 610 };
 611
 612 enum rtl_flag {
 613         RTL_FLAG_TASK_ENABLED = 0,
 614         RTL_FLAG_TASK_RESET_PENDING,
 615         RTL_FLAG_MAX
 616 };
 617
 618 struct rtl8169_stats {
 619         u64                     packets;
 620         u64                     bytes;
 621         struct u64_stats_sync   syncp;
 622 };
 623
 624 struct rtl8169_private {
 625         void __iomem *mmio_addr;        /* memory map physical address */
 626         struct pci_dev *pci_dev;
 627         struct net_device *dev;
 628         struct phy_device *phydev;
 629         struct napi_struct napi;
 630         u32 msg_enable;
 631         enum mac_version mac_version;
 632         u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
 633         u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
 634         u32 dirty_tx;
 635         struct rtl8169_stats rx_stats;
 636         struct rtl8169_stats tx_stats;
 637         struct TxDesc *TxDescArray;     /* 256-aligned Tx descriptor ring */
 638         struct RxDesc *RxDescArray;     /* 256-aligned Rx descriptor ring */
 639         dma_addr_t TxPhyAddr;
 640         dma_addr_t RxPhyAddr;
 641         void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
 642         struct ring_info tx_skb[NUM_TX_DESC];   /* Tx data buffers */
 643         u16 cp_cmd;
 644         u16 irq_mask;
 645         struct clk *clk;
 646
 647         struct {
 648                 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
 649                 struct mutex mutex;
 650                 struct work_struct work;
 651         } wk;
 652
 653         unsigned irq_enabled:1;
 654         unsigned supports_gmii:1;
 655         unsigned aspm_manageable:1;
 656         dma_addr_t counters_phys_addr;
 657         struct rtl8169_counters *counters;
 658         struct rtl8169_tc_offsets tc_offset;
 659         u32 saved_wolopts;
 660
 661         const char *fw_name;
 662         struct rtl_fw *rtl_fw;
 663
 664         u32 ocp_base;
 665 };
 666
 667 typedef void (*rtl_generic_fct)(struct rtl8169_private *tp);
 668
 669 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
 670 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
 671 module_param_named(debug, debug.msg_enable, int, 0);
 672 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
 673 MODULE_SOFTDEP("pre: realtek");
 674 MODULE_LICENSE("GPL");
 675 MODULE_FIRMWARE(FIRMWARE_8168D_1);
 676 MODULE_FIRMWARE(FIRMWARE_8168D_2);
 677 MODULE_FIRMWARE(FIRMWARE_8168E_1);
 678 MODULE_FIRMWARE(FIRMWARE_8168E_2);
 679 MODULE_FIRMWARE(FIRMWARE_8168E_3);
 680 MODULE_FIRMWARE(FIRMWARE_8105E_1);
 681 MODULE_FIRMWARE(FIRMWARE_8168F_1);
 682 MODULE_FIRMWARE(FIRMWARE_8168F_2);
 683 MODULE_FIRMWARE(FIRMWARE_8402_1);
 684 MODULE_FIRMWARE(FIRMWARE_8411_1);
 685 MODULE_FIRMWARE(FIRMWARE_8411_2);
 686 MODULE_FIRMWARE(FIRMWARE_8106E_1);
 687 MODULE_FIRMWARE(FIRMWARE_8106E_2);
 688 MODULE_FIRMWARE(FIRMWARE_8168G_2);
 689 MODULE_FIRMWARE(FIRMWARE_8168G_3);
 690 MODULE_FIRMWARE(FIRMWARE_8168H_1);
 691 MODULE_FIRMWARE(FIRMWARE_8168H_2);
 692 MODULE_FIRMWARE(FIRMWARE_8107E_1);
 693 MODULE_FIRMWARE(FIRMWARE_8107E_2);
 694
 695 static inline struct device *tp_to_dev(struct rtl8169_private *tp)
 696 {
 697         return &tp->pci_dev->dev;
 698 }
 699
 700 static void rtl_lock_work(struct rtl8169_private *tp)
 701 {
 702         mutex_lock(&tp->wk.mutex);
 703 }
 704
 705 static void rtl_unlock_work(struct rtl8169_private *tp)
 706 {
 707         mutex_unlock(&tp->wk.mutex);
 708 }
 709
 710 static void rtl_lock_config_regs(struct rtl8169_private *tp)
 711 {
 712         RTL_W8(tp, Cfg9346, Cfg9346_Lock);
 713 }
 714
 715 static void rtl_unlock_config_regs(struct rtl8169_private *tp)
 716 {
 717         RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
 718 }
 719
 720 static void rtl_tx_performance_tweak(struct rtl8169_private *tp, u16 force)
 721 {
 722         pcie_capability_clear_and_set_word(tp->pci_dev, PCI_EXP_DEVCTL,
 723                                            PCI_EXP_DEVCTL_READRQ, force);
 724 }
 725
 726 static bool rtl_is_8168evl_up(struct rtl8169_private *tp)
 727 {
 728         return tp->mac_version >= RTL_GIGA_MAC_VER_34 &&
 729                tp->mac_version != RTL_GIGA_MAC_VER_39;
 730 }
 731
 732 struct rtl_cond {
 733         bool (*check)(struct rtl8169_private *);
 734         const char *msg;
 735 };
 736
 737 static void rtl_udelay(unsigned int d)
 738 {
 739         udelay(d);
 740 }
 741
 742 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,
 743                           void (*delay)(unsigned int), unsigned int d, int n,
 744                           bool high)
 745 {
 746         int i;
 747
 748         for (i = 0; i < n; i++) {
 749                 if (c->check(tp) == high)
 750                         return true;
 751                 delay(d);
 752         }
 753         netif_err(tp, drv, tp->dev, "%s == %d (loop: %d, delay: %d).\n",
 754                   c->msg, !high, n, d);
 755         return false;
 756 }
 757
 758 static bool rtl_udelay_loop_wait_high(struct rtl8169_private *tp,
 759                                       const struct rtl_cond *c,
 760                                       unsigned int d, int n)
 761 {
 762         return rtl_loop_wait(tp, c, rtl_udelay, d, n, true);
 763 }
 764
 765 static bool rtl_udelay_loop_wait_low(struct rtl8169_private *tp,
 766                                      const struct rtl_cond *c,
 767                                      unsigned int d, int n)
 768 {
 769         return rtl_loop_wait(tp, c, rtl_udelay, d, n, false);
 770 }
 771
 772 static bool rtl_msleep_loop_wait_high(struct rtl8169_private *tp,
 773                                       const struct rtl_cond *c,
 774                                       unsigned int d, int n)
 775 {
 776         return rtl_loop_wait(tp, c, msleep, d, n, true);
 777 }
 778
 779 static bool rtl_msleep_loop_wait_low(struct rtl8169_private *tp,
 780                                      const struct rtl_cond *c,
 781                                      unsigned int d, int n)
 782 {
 783         return rtl_loop_wait(tp, c, msleep, d, n, false);
 784 }
 785
 786 #define DECLARE_RTL_COND(name)                          \
 787 static bool name ## _check(struct rtl8169_private *);   \
 788                                                         \
 789 static const struct rtl_cond name = {                   \
 790         .check  = name ## _check,                       \
 791         .msg    = #name                                 \
 792 };                                                      \
 793                                                         \
 794 static bool name ## _check(struct rtl8169_private *tp)
 795
 796 static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg)
 797 {
 798         if (reg & 0xffff0001) {
 799                 netif_err(tp, drv, tp->dev, "Invalid ocp reg %x!\n", reg);
 800                 return true;
 801         }
 802         return false;
 803 }
 804
 805 DECLARE_RTL_COND(rtl_ocp_gphy_cond)
 806 {
 807         return RTL_R32(tp, GPHY_OCP) & OCPAR_FLAG;
 808 }
 809
 810 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
 811 {
 812         if (rtl_ocp_reg_failure(tp, reg))
 813                 return;
 814
 815         RTL_W32(tp, GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);
 816
 817         rtl_udelay_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);
 818 }
 819
 820 static int r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
 821 {
 822         if (rtl_ocp_reg_failure(tp, reg))
 823                 return 0;
 824
 825         RTL_W32(tp, GPHY_OCP, reg << 15);
 826
 827         return rtl_udelay_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?
 828                 (RTL_R32(tp, GPHY_OCP) & 0xffff) : -ETIMEDOUT;
 829 }
 830
 831 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
 832 {
 833         if (rtl_ocp_reg_failure(tp, reg))
 834                 return;
 835
 836         RTL_W32(tp, OCPDR, OCPAR_FLAG | (reg << 15) | data);
 837 }
 838
 839 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
 840 {
 841         if (rtl_ocp_reg_failure(tp, reg))
 842                 return 0;
 843
 844         RTL_W32(tp, OCPDR, reg << 15);
 845
 846         return RTL_R32(tp, OCPDR);
 847 }
 848
 849 #define OCP_STD_PHY_BASE        0xa400
 850
 851 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)
 852 {
 853         if (reg == 0x1f) {
 854                 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;
 855                 return;
 856         }
 857
 858         if (tp->ocp_base != OCP_STD_PHY_BASE)
 859                 reg -= 0x10;
 860
 861         r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);
 862 }
 863
 864 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)
 865 {
 866         if (tp->ocp_base != OCP_STD_PHY_BASE)
 867                 reg -= 0x10;
 868
 869         return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);
 870 }
 871
 872 static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value)
 873 {
 874         if (reg == 0x1f) {
 875                 tp->ocp_base = value << 4;
 876                 return;
 877         }
 878
 879         r8168_mac_ocp_write(tp, tp->ocp_base + reg, value);
 880 }
 881
 882 static int mac_mcu_read(struct rtl8169_private *tp, int reg)
 883 {
 884         return r8168_mac_ocp_read(tp, tp->ocp_base + reg);
 885 }
 886
 887 DECLARE_RTL_COND(rtl_phyar_cond)
 888 {
 889         return RTL_R32(tp, PHYAR) & 0x80000000;
 890 }
 891
 892 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)
 893 {
 894         RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
 895
 896         rtl_udelay_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);
 897         /*
 898          * According to hardware specs a 20us delay is required after write
 899          * complete indication, but before sending next command.
 900          */
 901         udelay(20);
 902 }
 903
 904 static int r8169_mdio_read(struct rtl8169_private *tp, int reg)
 905 {
 906         int value;
 907
 908         RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16);
 909
 910         value = rtl_udelay_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?
 911                 RTL_R32(tp, PHYAR) & 0xffff : -ETIMEDOUT;
 912
 913         /*
 914          * According to hardware specs a 20us delay is required after read
 915          * complete indication, but before sending next command.
 916          */
 917         udelay(20);
 918
 919         return value;
 920 }
 921
 922 DECLARE_RTL_COND(rtl_ocpar_cond)
 923 {
 924         return RTL_R32(tp, OCPAR) & OCPAR_FLAG;
 925 }
 926
 927 static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data)
 928 {
 929         RTL_W32(tp, OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
 930         RTL_W32(tp, OCPAR, OCPAR_GPHY_WRITE_CMD);
 931         RTL_W32(tp, EPHY_RXER_NUM, 0);
 932
 933         rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100);
 934 }
 935
 936 static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value)
 937 {
 938         r8168dp_1_mdio_access(tp, reg,
 939                               OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK));
 940 }
 941
 942 static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg)
 943 {
 944         r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD);
 945
 946         mdelay(1);
 947         RTL_W32(tp, OCPAR, OCPAR_GPHY_READ_CMD);
 948         RTL_W32(tp, EPHY_RXER_NUM, 0);
 949
 950         return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ?
 951                 RTL_R32(tp, OCPDR) & OCPDR_DATA_MASK : -ETIMEDOUT;
 952 }
 953
 954 #define R8168DP_1_MDIO_ACCESS_BIT       0x00020000
 955
 956 static void r8168dp_2_mdio_start(struct rtl8169_private *tp)
 957 {
 958         RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
 959 }
 960
 961 static void r8168dp_2_mdio_stop(struct rtl8169_private *tp)
 962 {
 963         RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
 964 }
 965
 966 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)
 967 {
 968         r8168dp_2_mdio_start(tp);
 969
 970         r8169_mdio_write(tp, reg, value);
 971
 972         r8168dp_2_mdio_stop(tp);
 973 }
 974
 975 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)
 976 {
 977         int value;
 978
 979         r8168dp_2_mdio_start(tp);
 980
 981         value = r8169_mdio_read(tp, reg);
 982
 983         r8168dp_2_mdio_stop(tp);
 984
 985         return value;
 986 }
 987
 988 static void rtl_writephy(struct rtl8169_private *tp, int location, int val)
 989 {
 990         switch (tp->mac_version) {
 991         case RTL_GIGA_MAC_VER_27:
 992                 r8168dp_1_mdio_write(tp, location, val);
 993                 break;
 994         case RTL_GIGA_MAC_VER_28:
 995         case RTL_GIGA_MAC_VER_31:
 996                 r8168dp_2_mdio_write(tp, location, val);
 997                 break;
 998         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
 999                 r8168g_mdio_write(tp, location, val);
1000                 break;
1001         default:
1002                 r8169_mdio_write(tp, location, val);
1003                 break;
1004         }
1005 }
1006
1007 static int rtl_readphy(struct rtl8169_private *tp, int location)
1008 {
1009         switch (tp->mac_version) {
1010         case RTL_GIGA_MAC_VER_27:
1011                 return r8168dp_1_mdio_read(tp, location);
1012         case RTL_GIGA_MAC_VER_28:
1013         case RTL_GIGA_MAC_VER_31:
1014                 return r8168dp_2_mdio_read(tp, location);
1015         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
1016                 return r8168g_mdio_read(tp, location);
1017         default:
1018                 return r8169_mdio_read(tp, location);
1019         }
1020 }
1021
1022 static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
1023 {
1024         rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
1025 }
1026
1027 static void rtl_w0w1_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
1028 {
1029         int val;
1030
1031         val = rtl_readphy(tp, reg_addr);
1032         rtl_writephy(tp, reg_addr, (val & ~m) | p);
1033 }
1034
1035 DECLARE_RTL_COND(rtl_ephyar_cond)
1036 {
1037         return RTL_R32(tp, EPHYAR) & EPHYAR_FLAG;
1038 }
1039
1040 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)
1041 {
1042         RTL_W32(tp, EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1043                 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1044
1045         rtl_udelay_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);
1046
1047         udelay(10);
1048 }
1049
1050 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)
1051 {
1052         RTL_W32(tp, EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1053
1054         return rtl_udelay_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?
1055                 RTL_R32(tp, EPHYAR) & EPHYAR_DATA_MASK : ~0;
1056 }
1057
1058 DECLARE_RTL_COND(rtl_eriar_cond)
1059 {
1060         return RTL_R32(tp, ERIAR) & ERIAR_FLAG;
1061 }
1062
1063 static void _rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1064                            u32 val, int type)
1065 {
1066         BUG_ON((addr & 3) || (mask == 0));
1067         RTL_W32(tp, ERIDR, val);
1068         RTL_W32(tp, ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
1069
1070         rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);
1071 }
1072
1073 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1074                           u32 val)
1075 {
1076         _rtl_eri_write(tp, addr, mask, val, ERIAR_EXGMAC);
1077 }
1078
1079 static u32 _rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
1080 {
1081         RTL_W32(tp, ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
1082
1083         return rtl_udelay_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?
1084                 RTL_R32(tp, ERIDR) : ~0;
1085 }
1086
1087 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr)
1088 {
1089         return _rtl_eri_read(tp, addr, ERIAR_EXGMAC);
1090 }
1091
1092 static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 mask, u32 p,
1093                          u32 m)
1094 {
1095         u32 val;
1096
1097         val = rtl_eri_read(tp, addr);
1098         rtl_eri_write(tp, addr, mask, (val & ~m) | p);
1099 }
1100
1101 static void rtl_eri_set_bits(struct rtl8169_private *tp, int addr, u32 mask,
1102                              u32 p)
1103 {
1104         rtl_w0w1_eri(tp, addr, mask, p, 0);
1105 }
1106
1107 static void rtl_eri_clear_bits(struct rtl8169_private *tp, int addr, u32 mask,
1108                                u32 m)
1109 {
1110         rtl_w0w1_eri(tp, addr, mask, 0, m);
1111 }
1112
1113 static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1114 {
1115         RTL_W32(tp, OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1116         return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?
1117                 RTL_R32(tp, OCPDR) : ~0;
1118 }
1119
1120 static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1121 {
1122         return _rtl_eri_read(tp, reg, ERIAR_OOB);
1123 }
1124
1125 static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1126                               u32 data)
1127 {
1128         RTL_W32(tp, OCPDR, data);
1129         RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1130         rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);
1131 }
1132
1133 static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1134                               u32 data)
1135 {
1136         _rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT,
1137                        data, ERIAR_OOB);
1138 }
1139
1140 static void r8168dp_oob_notify(struct rtl8169_private *tp, u8 cmd)
1141 {
1142         rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd);
1143
1144         r8168dp_ocp_write(tp, 0x1, 0x30, 0x00000001);
1145 }
1146
1147 #define OOB_CMD_RESET           0x00
1148 #define OOB_CMD_DRIVER_START    0x05
1149 #define OOB_CMD_DRIVER_STOP     0x06
1150
1151 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
1152 {
1153         return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
1154 }
1155
1156 DECLARE_RTL_COND(rtl_dp_ocp_read_cond)
1157 {
1158         u16 reg;
1159
1160         reg = rtl8168_get_ocp_reg(tp);
1161
1162         return r8168dp_ocp_read(tp, 0x0f, reg) & 0x00000800;
1163 }
1164
1165 DECLARE_RTL_COND(rtl_ep_ocp_read_cond)
1166 {
1167         return r8168ep_ocp_read(tp, 0x0f, 0x124) & 0x00000001;
1168 }
1169
1170 DECLARE_RTL_COND(rtl_ocp_tx_cond)
1171 {
1172         return RTL_R8(tp, IBISR0) & 0x20;
1173 }
1174
1175 static void rtl8168ep_stop_cmac(struct rtl8169_private *tp)
1176 {
1177         RTL_W8(tp, IBCR2, RTL_R8(tp, IBCR2) & ~0x01);
1178         rtl_msleep_loop_wait_high(tp, &rtl_ocp_tx_cond, 50, 2000);
1179         RTL_W8(tp, IBISR0, RTL_R8(tp, IBISR0) | 0x20);
1180         RTL_W8(tp, IBCR0, RTL_R8(tp, IBCR0) & ~0x01);
1181 }
1182
1183 static void rtl8168dp_driver_start(struct rtl8169_private *tp)
1184 {
1185         r8168dp_oob_notify(tp, OOB_CMD_DRIVER_START);
1186         rtl_msleep_loop_wait_high(tp, &rtl_dp_ocp_read_cond, 10, 10);
1187 }
1188
1189 static void rtl8168ep_driver_start(struct rtl8169_private *tp)
1190 {
1191         r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START);
1192         r8168ep_ocp_write(tp, 0x01, 0x30,
1193                           r8168ep_ocp_read(tp, 0x01, 0x30) | 0x01);
1194         rtl_msleep_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10, 10);
1195 }
1196
1197 static void rtl8168_driver_start(struct rtl8169_private *tp)
1198 {
1199         switch (tp->mac_version) {
1200         case RTL_GIGA_MAC_VER_27:
1201         case RTL_GIGA_MAC_VER_28:
1202         case RTL_GIGA_MAC_VER_31:
1203                 rtl8168dp_driver_start(tp);
1204                 break;
1205         case RTL_GIGA_MAC_VER_49:
1206         case RTL_GIGA_MAC_VER_50:
1207         case RTL_GIGA_MAC_VER_51:
1208                 rtl8168ep_driver_start(tp);
1209                 break;
1210         default:
1211                 BUG();
1212                 break;
1213         }
1214 }
1215
1216 static void rtl8168dp_driver_stop(struct rtl8169_private *tp)
1217 {
1218         r8168dp_oob_notify(tp, OOB_CMD_DRIVER_STOP);
1219         rtl_msleep_loop_wait_low(tp, &rtl_dp_ocp_read_cond, 10, 10);
1220 }
1221
1222 static void rtl8168ep_driver_stop(struct rtl8169_private *tp)
1223 {
1224         rtl8168ep_stop_cmac(tp);
1225         r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP);
1226         r8168ep_ocp_write(tp, 0x01, 0x30,
1227                           r8168ep_ocp_read(tp, 0x01, 0x30) | 0x01);
1228         rtl_msleep_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10, 10);
1229 }
1230
1231 static void rtl8168_driver_stop(struct rtl8169_private *tp)
1232 {
1233         switch (tp->mac_version) {
1234         case RTL_GIGA_MAC_VER_27:
1235         case RTL_GIGA_MAC_VER_28:
1236         case RTL_GIGA_MAC_VER_31:
1237                 rtl8168dp_driver_stop(tp);
1238                 break;
1239         case RTL_GIGA_MAC_VER_49:
1240         case RTL_GIGA_MAC_VER_50:
1241         case RTL_GIGA_MAC_VER_51:
1242                 rtl8168ep_driver_stop(tp);
1243                 break;
1244         default:
1245                 BUG();
1246                 break;
1247         }
1248 }
1249
1250 static bool r8168dp_check_dash(struct rtl8169_private *tp)
1251 {
1252         u16 reg = rtl8168_get_ocp_reg(tp);
1253
1254         return !!(r8168dp_ocp_read(tp, 0x0f, reg) & 0x00008000);
1255 }
1256
1257 static bool r8168ep_check_dash(struct rtl8169_private *tp)
1258 {
1259         return !!(r8168ep_ocp_read(tp, 0x0f, 0x128) & 0x00000001);
1260 }
1261
1262 static bool r8168_check_dash(struct rtl8169_private *tp)
1263 {
1264         switch (tp->mac_version) {
1265         case RTL_GIGA_MAC_VER_27:
1266         case RTL_GIGA_MAC_VER_28:
1267         case RTL_GIGA_MAC_VER_31:
1268                 return r8168dp_check_dash(tp);
1269         case RTL_GIGA_MAC_VER_49:
1270         case RTL_GIGA_MAC_VER_50:
1271         case RTL_GIGA_MAC_VER_51:
1272                 return r8168ep_check_dash(tp);
1273         default:
1274                 return false;
1275         }
1276 }
1277
1278 static void rtl_reset_packet_filter(struct rtl8169_private *tp)
1279 {
1280         rtl_eri_clear_bits(tp, 0xdc, ERIAR_MASK_0001, BIT(0));
1281         rtl_eri_set_bits(tp, 0xdc, ERIAR_MASK_0001, BIT(0));
1282 }
1283
1284 DECLARE_RTL_COND(rtl_efusear_cond)
1285 {
1286         return RTL_R32(tp, EFUSEAR) & EFUSEAR_FLAG;
1287 }
1288
1289 static u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)
1290 {
1291         RTL_W32(tp, EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1292
1293         return rtl_udelay_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?
1294                 RTL_R32(tp, EFUSEAR) & EFUSEAR_DATA_MASK : ~0;
1295 }
1296
1297 static void rtl_ack_events(struct rtl8169_private *tp, u16 bits)
1298 {
1299         RTL_W16(tp, IntrStatus, bits);
1300 }
1301
1302 static void rtl_irq_disable(struct rtl8169_private *tp)
1303 {
1304         RTL_W16(tp, IntrMask, 0);
1305         tp->irq_enabled = 0;
1306 }
1307
1308 #define RTL_EVENT_NAPI_RX       (RxOK | RxErr)
1309 #define RTL_EVENT_NAPI_TX       (TxOK | TxErr)
1310 #define RTL_EVENT_NAPI          (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX)
1311
1312 static void rtl_irq_enable(struct rtl8169_private *tp)
1313 {
1314         tp->irq_enabled = 1;
1315         RTL_W16(tp, IntrMask, tp->irq_mask);
1316 }
1317
1318 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1319 {
1320         rtl_irq_disable(tp);
1321         rtl_ack_events(tp, 0xffff);
1322         /* PCI commit */
1323         RTL_R8(tp, ChipCmd);
1324 }
1325
1326 static void rtl_link_chg_patch(struct rtl8169_private *tp)
1327 {
1328         struct net_device *dev = tp->dev;
1329         struct phy_device *phydev = tp->phydev;
1330
1331         if (!netif_running(dev))
1332                 return;
1333
1334         if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
1335             tp->mac_version == RTL_GIGA_MAC_VER_38) {
1336                 if (phydev->speed == SPEED_1000) {
1337                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011);
1338                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
1339                 } else if (phydev->speed == SPEED_100) {
1340                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1341                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
1342                 } else {
1343                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1344                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f);
1345                 }
1346                 rtl_reset_packet_filter(tp);
1347         } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1348                    tp->mac_version == RTL_GIGA_MAC_VER_36) {
1349                 if (phydev->speed == SPEED_1000) {
1350                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011);
1351                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
1352                 } else {
1353                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1354                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f);
1355                 }
1356         } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
1357                 if (phydev->speed == SPEED_10) {
1358                         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02);
1359                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060a);
1360                 } else {
1361                         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000);
1362                 }
1363         }
1364 }
1365
1366 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1367
1368 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1369 {
1370         struct rtl8169_private *tp = netdev_priv(dev);
1371
1372         rtl_lock_work(tp);
1373         wol->supported = WAKE_ANY;
1374         wol->wolopts = tp->saved_wolopts;
1375         rtl_unlock_work(tp);
1376 }
1377
1378 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1379 {
1380         unsigned int i, tmp;
1381         static const struct {
1382                 u32 opt;
1383                 u16 reg;
1384                 u8  mask;
1385         } cfg[] = {
1386                 { WAKE_PHY,   Config3, LinkUp },
1387                 { WAKE_UCAST, Config5, UWF },
1388                 { WAKE_BCAST, Config5, BWF },
1389                 { WAKE_MCAST, Config5, MWF },
1390                 { WAKE_ANY,   Config5, LanWake },
1391                 { WAKE_MAGIC, Config3, MagicPacket }
1392         };
1393         u8 options;
1394
1395         rtl_unlock_config_regs(tp);
1396
1397         if (rtl_is_8168evl_up(tp)) {
1398                 tmp = ARRAY_SIZE(cfg) - 1;
1399                 if (wolopts & WAKE_MAGIC)
1400                         rtl_eri_set_bits(tp, 0x0dc, ERIAR_MASK_0100,
1401                                          MagicPacket_v2);
1402                 else
1403                         rtl_eri_clear_bits(tp, 0x0dc, ERIAR_MASK_0100,
1404                                            MagicPacket_v2);
1405         } else {
1406                 tmp = ARRAY_SIZE(cfg);
1407         }
1408
1409         for (i = 0; i < tmp; i++) {
1410                 options = RTL_R8(tp, cfg[i].reg) & ~cfg[i].mask;
1411                 if (wolopts & cfg[i].opt)
1412                         options |= cfg[i].mask;
1413                 RTL_W8(tp, cfg[i].reg, options);
1414         }
1415
1416         switch (tp->mac_version) {
1417         case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
1418                 options = RTL_R8(tp, Config1) & ~PMEnable;
1419                 if (wolopts)
1420                         options |= PMEnable;
1421                 RTL_W8(tp, Config1, options);
1422                 break;
1423         case RTL_GIGA_MAC_VER_34:
1424         case RTL_GIGA_MAC_VER_37:
1425         case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_51:
1426                 options = RTL_R8(tp, Config2) & ~PME_SIGNAL;
1427                 if (wolopts)
1428                         options |= PME_SIGNAL;
1429                 RTL_W8(tp, Config2, options);
1430                 break;
1431         default:
1432                 break;
1433         }
1434
1435         rtl_lock_config_regs(tp);
1436
1437         device_set_wakeup_enable(tp_to_dev(tp), wolopts);
1438 }
1439
1440 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1441 {
1442         struct rtl8169_private *tp = netdev_priv(dev);
1443         struct device *d = tp_to_dev(tp);
1444
1445         if (wol->wolopts & ~WAKE_ANY)
1446                 return -EINVAL;
1447
1448         pm_runtime_get_noresume(d);
1449
1450         rtl_lock_work(tp);
1451
1452         tp->saved_wolopts = wol->wolopts;
1453
1454         if (pm_runtime_active(d))
1455                 __rtl8169_set_wol(tp, tp->saved_wolopts);
1456
1457         rtl_unlock_work(tp);
1458
1459         pm_runtime_put_noidle(d);
1460
1461         return 0;
1462 }
1463
1464 static void rtl8169_get_drvinfo(struct net_device *dev,
1465                                 struct ethtool_drvinfo *info)
1466 {
1467         struct rtl8169_private *tp = netdev_priv(dev);
1468         struct rtl_fw *rtl_fw = tp->rtl_fw;
1469
1470         strlcpy(info->driver, MODULENAME, sizeof(info->driver));
1471         strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1472         BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
1473         if (rtl_fw)
1474                 strlcpy(info->fw_version, rtl_fw->version,
1475                         sizeof(info->fw_version));
1476 }
1477
1478 static int rtl8169_get_regs_len(struct net_device *dev)
1479 {
1480         return R8169_REGS_SIZE;
1481 }
1482
1483 static netdev_features_t rtl8169_fix_features(struct net_device *dev,
1484         netdev_features_t features)
1485 {
1486         struct rtl8169_private *tp = netdev_priv(dev);
1487
1488         if (dev->mtu > TD_MSS_MAX)
1489                 features &= ~NETIF_F_ALL_TSO;
1490
1491         if (dev->mtu > JUMBO_1K &&
1492             tp->mac_version > RTL_GIGA_MAC_VER_06)
1493                 features &= ~NETIF_F_IP_CSUM;
1494
1495         return features;
1496 }
1497
1498 static int rtl8169_set_features(struct net_device *dev,
1499                                 netdev_features_t features)
1500 {
1501         struct rtl8169_private *tp = netdev_priv(dev);
1502         u32 rx_config;
1503
1504         rtl_lock_work(tp);
1505
1506         rx_config = RTL_R32(tp, RxConfig);
1507         if (features & NETIF_F_RXALL)
1508                 rx_config |= (AcceptErr | AcceptRunt);
1509         else
1510                 rx_config &= ~(AcceptErr | AcceptRunt);
1511
1512         RTL_W32(tp, RxConfig, rx_config);
1513
1514         if (features & NETIF_F_RXCSUM)
1515                 tp->cp_cmd |= RxChkSum;
1516         else
1517                 tp->cp_cmd &= ~RxChkSum;
1518
1519         if (features & NETIF_F_HW_VLAN_CTAG_RX)
1520                 tp->cp_cmd |= RxVlan;
1521         else
1522                 tp->cp_cmd &= ~RxVlan;
1523
1524         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1525         RTL_R16(tp, CPlusCmd);
1526
1527         rtl_unlock_work(tp);
1528
1529         return 0;
1530 }
1531
1532 static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb)
1533 {
1534         return (skb_vlan_tag_present(skb)) ?
1535                 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00;
1536 }
1537
1538 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1539 {
1540         u32 opts2 = le32_to_cpu(desc->opts2);
1541
1542         if (opts2 & RxVlanTag)
1543                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff));
1544 }
1545
1546 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1547                              void *p)
1548 {
1549         struct rtl8169_private *tp = netdev_priv(dev);
1550         u32 __iomem *data = tp->mmio_addr;
1551         u32 *dw = p;
1552         int i;
1553
1554         rtl_lock_work(tp);
1555         for (i = 0; i < R8169_REGS_SIZE; i += 4)
1556                 memcpy_fromio(dw++, data++, 4);
1557         rtl_unlock_work(tp);
1558 }
1559
1560 static u32 rtl8169_get_msglevel(struct net_device *dev)
1561 {
1562         struct rtl8169_private *tp = netdev_priv(dev);
1563
1564         return tp->msg_enable;
1565 }
1566
1567 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1568 {
1569         struct rtl8169_private *tp = netdev_priv(dev);
1570
1571         tp->msg_enable = value;
1572 }
1573
1574 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1575         "tx_packets",
1576         "rx_packets",
1577         "tx_errors",
1578         "rx_errors",
1579         "rx_missed",
1580         "align_errors",
1581         "tx_single_collisions",
1582         "tx_multi_collisions",
1583         "unicast",
1584         "broadcast",
1585         "multicast",
1586         "tx_aborted",
1587         "tx_underrun",
1588 };
1589
1590 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1591 {
1592         switch (sset) {
1593         case ETH_SS_STATS:
1594                 return ARRAY_SIZE(rtl8169_gstrings);
1595         default:
1596                 return -EOPNOTSUPP;
1597         }
1598 }
1599
1600 DECLARE_RTL_COND(rtl_counters_cond)
1601 {
1602         return RTL_R32(tp, CounterAddrLow) & (CounterReset | CounterDump);
1603 }
1604
1605 static bool rtl8169_do_counters(struct rtl8169_private *tp, u32 counter_cmd)
1606 {
1607         dma_addr_t paddr = tp->counters_phys_addr;
1608         u32 cmd;
1609
1610         RTL_W32(tp, CounterAddrHigh, (u64)paddr >> 32);
1611         RTL_R32(tp, CounterAddrHigh);
1612         cmd = (u64)paddr & DMA_BIT_MASK(32);
1613         RTL_W32(tp, CounterAddrLow, cmd);
1614         RTL_W32(tp, CounterAddrLow, cmd | counter_cmd);
1615
1616         return rtl_udelay_loop_wait_low(tp, &rtl_counters_cond, 10, 1000);
1617 }
1618
1619 static bool rtl8169_reset_counters(struct rtl8169_private *tp)
1620 {
1621         /*
1622          * Versions prior to RTL_GIGA_MAC_VER_19 don't support resetting the
1623          * tally counters.
1624          */
1625         if (tp->mac_version < RTL_GIGA_MAC_VER_19)
1626                 return true;
1627
1628         return rtl8169_do_counters(tp, CounterReset);
1629 }
1630
1631 static bool rtl8169_update_counters(struct rtl8169_private *tp)
1632 {
1633         u8 val = RTL_R8(tp, ChipCmd);
1634
1635         /*
1636          * Some chips are unable to dump tally counters when the receiver
1637          * is disabled. If 0xff chip may be in a PCI power-save state.
1638          */
1639         if (!(val & CmdRxEnb) || val == 0xff)
1640                 return true;
1641
1642         return rtl8169_do_counters(tp, CounterDump);
1643 }
1644
1645 static bool rtl8169_init_counter_offsets(struct rtl8169_private *tp)
1646 {
1647         struct rtl8169_counters *counters = tp->counters;
1648         bool ret = false;
1649
1650         /*
1651          * rtl8169_init_counter_offsets is called from rtl_open.  On chip
1652          * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only
1653          * reset by a power cycle, while the counter values collected by the
1654          * driver are reset at every driver unload/load cycle.
1655          *
1656          * To make sure the HW values returned by @get_stats64 match the SW
1657          * values, we collect the initial values at first open(*) and use them
1658          * as offsets to normalize the values returned by @get_stats64.
1659          *
1660          * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one
1661          * for the reason stated in rtl8169_update_counters; CmdRxEnb is only
1662          * set at open time by rtl_hw_start.
1663          */
1664
1665         if (tp->tc_offset.inited)
1666                 return true;
1667
1668         /* If both, reset and update fail, propagate to caller. */
1669         if (rtl8169_reset_counters(tp))
1670                 ret = true;
1671
1672         if (rtl8169_update_counters(tp))
1673                 ret = true;
1674
1675         tp->tc_offset.tx_errors = counters->tx_errors;
1676         tp->tc_offset.tx_multi_collision = counters->tx_multi_collision;
1677         tp->tc_offset.tx_aborted = counters->tx_aborted;
1678         tp->tc_offset.inited = true;
1679
1680         return ret;
1681 }
1682
1683 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1684                                       struct ethtool_stats *stats, u64 *data)
1685 {
1686         struct rtl8169_private *tp = netdev_priv(dev);
1687         struct device *d = tp_to_dev(tp);
1688         struct rtl8169_counters *counters = tp->counters;
1689
1690         ASSERT_RTNL();
1691
1692         pm_runtime_get_noresume(d);
1693
1694         if (pm_runtime_active(d))
1695                 rtl8169_update_counters(tp);
1696
1697         pm_runtime_put_noidle(d);
1698
1699         data[0] = le64_to_cpu(counters->tx_packets);
1700         data[1] = le64_to_cpu(counters->rx_packets);
1701         data[2] = le64_to_cpu(counters->tx_errors);
1702         data[3] = le32_to_cpu(counters->rx_errors);
1703         data[4] = le16_to_cpu(counters->rx_missed);
1704         data[5] = le16_to_cpu(counters->align_errors);
1705         data[6] = le32_to_cpu(counters->tx_one_collision);
1706         data[7] = le32_to_cpu(counters->tx_multi_collision);
1707         data[8] = le64_to_cpu(counters->rx_unicast);
1708         data[9] = le64_to_cpu(counters->rx_broadcast);
1709         data[10] = le32_to_cpu(counters->rx_multicast);
1710         data[11] = le16_to_cpu(counters->tx_aborted);
1711         data[12] = le16_to_cpu(counters->tx_underun);
1712 }
1713
1714 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1715 {
1716         switch(stringset) {
1717         case ETH_SS_STATS:
1718                 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1719                 break;
1720         }
1721 }
1722
1723 /*
1724  * Interrupt coalescing
1725  *
1726  * > 1 - the availability of the IntrMitigate (0xe2) register through the
1727  * >     8169, 8168 and 810x line of chipsets
1728  *
1729  * 8169, 8168, and 8136(810x) serial chipsets support it.
1730  *
1731  * > 2 - the Tx timer unit at gigabit speed
1732  *
1733  * The unit of the timer depends on both the speed and the setting of CPlusCmd
1734  * (0xe0) bit 1 and bit 0.
1735  *
1736  * For 8169
1737  * bit[1:0] \ speed        1000M           100M            10M
1738  * 0 0                     320ns           2.56us          40.96us
1739  * 0 1                     2.56us          20.48us         327.7us
1740  * 1 0                     5.12us          40.96us         655.4us
1741  * 1 1                     10.24us         81.92us         1.31ms
1742  *
1743  * For the other
1744  * bit[1:0] \ speed        1000M           100M            10M
1745  * 0 0                     5us             2.56us          40.96us
1746  * 0 1                     40us            20.48us         327.7us
1747  * 1 0                     80us            40.96us         655.4us
1748  * 1 1                     160us           81.92us         1.31ms
1749  */
1750
1751 /* rx/tx scale factors for one particular CPlusCmd[0:1] value */
1752 struct rtl_coalesce_scale {
1753         /* Rx / Tx */
1754         u32 nsecs[2];
1755 };
1756
1757 /* rx/tx scale factors for all CPlusCmd[0:1] cases */
1758 struct rtl_coalesce_info {
1759         u32 speed;
1760         struct rtl_coalesce_scale scalev[4];    /* each CPlusCmd[0:1] case */
1761 };
1762
1763 /* produce (r,t) pairs with each being in series of *1, *8, *8*2, *8*2*2 */
1764 #define rxtx_x1822(r, t) {              \
1765         {{(r),          (t)}},          \
1766         {{(r)*8,        (t)*8}},        \
1767         {{(r)*8*2,      (t)*8*2}},      \
1768         {{(r)*8*2*2,    (t)*8*2*2}},    \
1769 }
1770 static const struct rtl_coalesce_info rtl_coalesce_info_8169[] = {
1771         /* speed        delays:     rx00   tx00 */
1772         { SPEED_10,     rxtx_x1822(40960, 40960)        },
1773         { SPEED_100,    rxtx_x1822( 2560,  2560)        },
1774         { SPEED_1000,   rxtx_x1822(  320,   320)        },
1775         { 0 },
1776 };
1777
1778 static const struct rtl_coalesce_info rtl_coalesce_info_8168_8136[] = {
1779         /* speed        delays:     rx00   tx00 */
1780         { SPEED_10,     rxtx_x1822(40960, 40960)        },
1781         { SPEED_100,    rxtx_x1822( 2560,  2560)        },
1782         { SPEED_1000,   rxtx_x1822( 5000,  5000)        },
1783         { 0 },
1784 };
1785 #undef rxtx_x1822
1786
1787 /* get rx/tx scale vector corresponding to current speed */
1788 static const struct rtl_coalesce_info *rtl_coalesce_info(struct net_device *dev)
1789 {
1790         struct rtl8169_private *tp = netdev_priv(dev);
1791         const struct rtl_coalesce_info *ci;
1792
1793         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
1794                 ci = rtl_coalesce_info_8169;
1795         else
1796                 ci = rtl_coalesce_info_8168_8136;
1797
1798         for (; ci->speed; ci++) {
1799                 if (tp->phydev->speed == ci->speed)
1800                         return ci;
1801         }
1802
1803         return ERR_PTR(-ELNRNG);
1804 }
1805
1806 static int rtl_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1807 {
1808         struct rtl8169_private *tp = netdev_priv(dev);
1809         const struct rtl_coalesce_info *ci;
1810         const struct rtl_coalesce_scale *scale;
1811         struct {
1812                 u32 *max_frames;
1813                 u32 *usecs;
1814         } coal_settings [] = {
1815                 { &ec->rx_max_coalesced_frames, &ec->rx_coalesce_usecs },
1816                 { &ec->tx_max_coalesced_frames, &ec->tx_coalesce_usecs }
1817         }, *p = coal_settings;
1818         int i;
1819         u16 w;
1820
1821         memset(ec, 0, sizeof(*ec));
1822
1823         /* get rx/tx scale corresponding to current speed and CPlusCmd[0:1] */
1824         ci = rtl_coalesce_info(dev);
1825         if (IS_ERR(ci))
1826                 return PTR_ERR(ci);
1827
1828         scale = &ci->scalev[tp->cp_cmd & INTT_MASK];
1829
1830         /* read IntrMitigate and adjust according to scale */
1831         for (w = RTL_R16(tp, IntrMitigate); w; w >>= RTL_COALESCE_SHIFT, p++) {
1832                 *p->max_frames = (w & RTL_COALESCE_MASK) << 2;
1833                 w >>= RTL_COALESCE_SHIFT;
1834                 *p->usecs = w & RTL_COALESCE_MASK;
1835         }
1836
1837         for (i = 0; i < 2; i++) {
1838                 p = coal_settings + i;
1839                 *p->usecs = (*p->usecs * scale->nsecs[i]) / 1000;
1840
1841                 /*
1842                  * ethtool_coalesce says it is illegal to set both usecs and
1843                  * max_frames to 0.
1844                  */
1845                 if (!*p->usecs && !*p->max_frames)
1846                         *p->max_frames = 1;
1847         }
1848
1849         return 0;
1850 }
1851
1852 /* choose appropriate scale factor and CPlusCmd[0:1] for (speed, nsec) */
1853 static const struct rtl_coalesce_scale *rtl_coalesce_choose_scale(
1854                         struct net_device *dev, u32 nsec, u16 *cp01)
1855 {
1856         const struct rtl_coalesce_info *ci;
1857         u16 i;
1858
1859         ci = rtl_coalesce_info(dev);
1860         if (IS_ERR(ci))
1861                 return ERR_CAST(ci);
1862
1863         for (i = 0; i < 4; i++) {
1864                 u32 rxtx_maxscale = max(ci->scalev[i].nsecs[0],
1865                                         ci->scalev[i].nsecs[1]);
1866                 if (nsec <= rxtx_maxscale * RTL_COALESCE_T_MAX) {
1867                         *cp01 = i;
1868                         return &ci->scalev[i];
1869                 }
1870         }
1871
1872         return ERR_PTR(-EINVAL);
1873 }
1874
1875 static int rtl_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1876 {
1877         struct rtl8169_private *tp = netdev_priv(dev);
1878         const struct rtl_coalesce_scale *scale;
1879         struct {
1880                 u32 frames;
1881                 u32 usecs;
1882         } coal_settings [] = {
1883                 { ec->rx_max_coalesced_frames, ec->rx_coalesce_usecs },
1884                 { ec->tx_max_coalesced_frames, ec->tx_coalesce_usecs }
1885         }, *p = coal_settings;
1886         u16 w = 0, cp01;
1887         int i;
1888
1889         scale = rtl_coalesce_choose_scale(dev,
1890                         max(p[0].usecs, p[1].usecs) * 1000, &cp01);
1891         if (IS_ERR(scale))
1892                 return PTR_ERR(scale);
1893
1894         for (i = 0; i < 2; i++, p++) {
1895                 u32 units;
1896
1897                 /*
1898                  * accept max_frames=1 we returned in rtl_get_coalesce.
1899                  * accept it not only when usecs=0 because of e.g. the following scenario:
1900                  *
1901                  * - both rx_usecs=0 & rx_frames=0 in hardware (no delay on RX)
1902                  * - rtl_get_coalesce returns rx_usecs=0, rx_frames=1
1903                  * - then user does `ethtool -C eth0 rx-usecs 100`
1904                  *
1905                  * since ethtool sends to kernel whole ethtool_coalesce
1906                  * settings, if we do not handle rx_usecs=!0, rx_frames=1
1907                  * we'll reject it below in `frames % 4 != 0`.
1908                  */
1909                 if (p->frames == 1) {
1910                         p->frames = 0;
1911                 }
1912
1913                 units = p->usecs * 1000 / scale->nsecs[i];
1914                 if (p->frames > RTL_COALESCE_FRAME_MAX || p->frames % 4)
1915                         return -EINVAL;
1916
1917                 w <<= RTL_COALESCE_SHIFT;
1918                 w |= units;
1919                 w <<= RTL_COALESCE_SHIFT;
1920                 w |= p->frames >> 2;
1921         }
1922
1923         rtl_lock_work(tp);
1924
1925         RTL_W16(tp, IntrMitigate, swab16(w));
1926
1927         tp->cp_cmd = (tp->cp_cmd & ~INTT_MASK) | cp01;
1928         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1929         RTL_R16(tp, CPlusCmd);
1930
1931         rtl_unlock_work(tp);
1932
1933         return 0;
1934 }
1935
1936 static int rtl_get_eee_supp(struct rtl8169_private *tp)
1937 {
1938         struct phy_device *phydev = tp->phydev;
1939         int ret;
1940
1941         switch (tp->mac_version) {
1942         case RTL_GIGA_MAC_VER_34:
1943         case RTL_GIGA_MAC_VER_35:
1944         case RTL_GIGA_MAC_VER_36:
1945         case RTL_GIGA_MAC_VER_38:
1946                 ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE);
1947                 break;
1948         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
1949                 ret = phy_read_paged(phydev, 0x0a5c, 0x12);
1950                 break;
1951         default:
1952                 ret = -EPROTONOSUPPORT;
1953                 break;
1954         }
1955
1956         return ret;
1957 }
1958
1959 static int rtl_get_eee_lpadv(struct rtl8169_private *tp)
1960 {
1961         struct phy_device *phydev = tp->phydev;
1962         int ret;
1963
1964         switch (tp->mac_version) {
1965         case RTL_GIGA_MAC_VER_34:
1966         case RTL_GIGA_MAC_VER_35:
1967         case RTL_GIGA_MAC_VER_36:
1968         case RTL_GIGA_MAC_VER_38:
1969                 ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE);
1970                 break;
1971         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
1972                 ret = phy_read_paged(phydev, 0x0a5d, 0x11);
1973                 break;
1974         default:
1975                 ret = -EPROTONOSUPPORT;
1976                 break;
1977         }
1978
1979         return ret;
1980 }
1981
1982 static int rtl_get_eee_adv(struct rtl8169_private *tp)
1983 {
1984         struct phy_device *phydev = tp->phydev;
1985         int ret;
1986
1987         switch (tp->mac_version) {
1988         case RTL_GIGA_MAC_VER_34:
1989         case RTL_GIGA_MAC_VER_35:
1990         case RTL_GIGA_MAC_VER_36:
1991         case RTL_GIGA_MAC_VER_38:
1992                 ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV);
1993                 break;
1994         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
1995                 ret = phy_read_paged(phydev, 0x0a5d, 0x10);
1996                 break;
1997         default:
1998                 ret = -EPROTONOSUPPORT;
1999                 break;
2000         }
2001
2002         return ret;
2003 }
2004
2005 static int rtl_set_eee_adv(struct rtl8169_private *tp, int val)
2006 {
2007         struct phy_device *phydev = tp->phydev;
2008         int ret = 0;
2009
2010         switch (tp->mac_version) {
2011         case RTL_GIGA_MAC_VER_34:
2012         case RTL_GIGA_MAC_VER_35:
2013         case RTL_GIGA_MAC_VER_36:
2014         case RTL_GIGA_MAC_VER_38:
2015                 ret = phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);
2016                 break;
2017         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
2018                 phy_write_paged(phydev, 0x0a5d, 0x10, val);
2019                 break;
2020         default:
2021                 ret = -EPROTONOSUPPORT;
2022                 break;
2023         }
2024
2025         return ret;
2026 }
2027
2028 static int rtl8169_get_eee(struct net_device *dev, struct ethtool_eee *data)
2029 {
2030         struct rtl8169_private *tp = netdev_priv(dev);
2031         struct device *d = tp_to_dev(tp);
2032         int ret;
2033
2034         pm_runtime_get_noresume(d);
2035
2036         if (!pm_runtime_active(d)) {
2037                 ret = -EOPNOTSUPP;
2038                 goto out;
2039         }
2040
2041         /* Get Supported EEE */
2042         ret = rtl_get_eee_supp(tp);
2043         if (ret < 0)
2044                 goto out;
2045         data->supported = mmd_eee_cap_to_ethtool_sup_t(ret);
2046
2047         /* Get advertisement EEE */
2048         ret = rtl_get_eee_adv(tp);
2049         if (ret < 0)
2050                 goto out;
2051         data->advertised = mmd_eee_adv_to_ethtool_adv_t(ret);
2052         data->eee_enabled = !!data->advertised;
2053
2054         /* Get LP advertisement EEE */
2055         ret = rtl_get_eee_lpadv(tp);
2056         if (ret < 0)
2057                 goto out;
2058         data->lp_advertised = mmd_eee_adv_to_ethtool_adv_t(ret);
2059         data->eee_active = !!(data->advertised & data->lp_advertised);
2060 out:
2061         pm_runtime_put_noidle(d);
2062         return ret < 0 ? ret : 0;
2063 }
2064
2065 static int rtl8169_set_eee(struct net_device *dev, struct ethtool_eee *data)
2066 {
2067         struct rtl8169_private *tp = netdev_priv(dev);
2068         struct device *d = tp_to_dev(tp);
2069         int old_adv, adv = 0, cap, ret;
2070
2071         pm_runtime_get_noresume(d);
2072
2073         if (!dev->phydev || !pm_runtime_active(d)) {
2074                 ret = -EOPNOTSUPP;
2075                 goto out;
2076         }
2077
2078         if (dev->phydev->autoneg == AUTONEG_DISABLE ||
2079             dev->phydev->duplex != DUPLEX_FULL) {
2080                 ret = -EPROTONOSUPPORT;
2081                 goto out;
2082         }
2083
2084         /* Get Supported EEE */
2085         ret = rtl_get_eee_supp(tp);
2086         if (ret < 0)
2087                 goto out;
2088         cap = ret;
2089
2090         ret = rtl_get_eee_adv(tp);
2091         if (ret < 0)
2092                 goto out;
2093         old_adv = ret;
2094
2095         if (data->eee_enabled) {
2096                 adv = !data->advertised ? cap :
2097                       ethtool_adv_to_mmd_eee_adv_t(data->advertised) & cap;
2098                 /* Mask prohibited EEE modes */
2099                 adv &= ~dev->phydev->eee_broken_modes;
2100         }
2101
2102         if (old_adv != adv) {
2103                 ret = rtl_set_eee_adv(tp, adv);
2104                 if (ret < 0)
2105                         goto out;
2106
2107                 /* Restart autonegotiation so the new modes get sent to the
2108                  * link partner.
2109                  */
2110                 ret = phy_restart_aneg(dev->phydev);
2111         }
2112
2113 out:
2114         pm_runtime_put_noidle(d);
2115         return ret < 0 ? ret : 0;
2116 }
2117
2118 static const struct ethtool_ops rtl8169_ethtool_ops = {
2119         .get_drvinfo            = rtl8169_get_drvinfo,
2120         .get_regs_len           = rtl8169_get_regs_len,
2121         .get_link               = ethtool_op_get_link,
2122         .get_coalesce           = rtl_get_coalesce,
2123         .set_coalesce           = rtl_set_coalesce,
2124         .get_msglevel           = rtl8169_get_msglevel,
2125         .set_msglevel           = rtl8169_set_msglevel,
2126         .get_regs               = rtl8169_get_regs,
2127         .get_wol                = rtl8169_get_wol,
2128         .set_wol                = rtl8169_set_wol,
2129         .get_strings            = rtl8169_get_strings,
2130         .get_sset_count         = rtl8169_get_sset_count,
2131         .get_ethtool_stats      = rtl8169_get_ethtool_stats,
2132         .get_ts_info            = ethtool_op_get_ts_info,
2133         .nway_reset             = phy_ethtool_nway_reset,
2134         .get_eee                = rtl8169_get_eee,
2135         .set_eee                = rtl8169_set_eee,
2136         .get_link_ksettings     = phy_ethtool_get_link_ksettings,
2137         .set_link_ksettings     = phy_ethtool_set_link_ksettings,
2138 };
2139
2140 static void rtl_enable_eee(struct rtl8169_private *tp)
2141 {
2142         int supported = rtl_get_eee_supp(tp);
2143
2144         if (supported > 0)
2145                 rtl_set_eee_adv(tp, supported);
2146 }
2147
2148 static void rtl8169_get_mac_version(struct rtl8169_private *tp)
2149 {
2150         /*
2151          * The driver currently handles the 8168Bf and the 8168Be identically
2152          * but they can be identified more specifically through the test below
2153          * if needed:
2154          *
2155          * (RTL_R32(tp, TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
2156          *
2157          * Same thing for the 8101Eb and the 8101Ec:
2158          *
2159          * (RTL_R32(tp, TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
2160          */
2161         static const struct rtl_mac_info {
2162                 u16 mask;
2163                 u16 val;
2164                 u16 mac_version;
2165         } mac_info[] = {
2166                 /* 8168EP family. */
2167                 { 0x7cf, 0x502, RTL_GIGA_MAC_VER_51 },
2168                 { 0x7cf, 0x501, RTL_GIGA_MAC_VER_50 },
2169                 { 0x7cf, 0x500, RTL_GIGA_MAC_VER_49 },
2170
2171                 /* 8168H family. */
2172                 { 0x7cf, 0x541, RTL_GIGA_MAC_VER_46 },
2173                 { 0x7cf, 0x540, RTL_GIGA_MAC_VER_45 },
2174
2175                 /* 8168G family. */
2176                 { 0x7cf, 0x5c8, RTL_GIGA_MAC_VER_44 },
2177                 { 0x7cf, 0x509, RTL_GIGA_MAC_VER_42 },
2178                 { 0x7cf, 0x4c1, RTL_GIGA_MAC_VER_41 },
2179                 { 0x7cf, 0x4c0, RTL_GIGA_MAC_VER_40 },
2180
2181                 /* 8168F family. */
2182                 { 0x7c8, 0x488, RTL_GIGA_MAC_VER_38 },
2183                 { 0x7cf, 0x481, RTL_GIGA_MAC_VER_36 },
2184                 { 0x7cf, 0x480, RTL_GIGA_MAC_VER_35 },
2185
2186                 /* 8168E family. */
2187                 { 0x7c8, 0x2c8, RTL_GIGA_MAC_VER_34 },
2188                 { 0x7cf, 0x2c1, RTL_GIGA_MAC_VER_32 },
2189                 { 0x7c8, 0x2c0, RTL_GIGA_MAC_VER_33 },
2190
2191                 /* 8168D family. */
2192                 { 0x7cf, 0x281, RTL_GIGA_MAC_VER_25 },
2193                 { 0x7c8, 0x280, RTL_GIGA_MAC_VER_26 },
2194
2195                 /* 8168DP family. */
2196                 { 0x7cf, 0x288, RTL_GIGA_MAC_VER_27 },
2197                 { 0x7cf, 0x28a, RTL_GIGA_MAC_VER_28 },
2198                 { 0x7cf, 0x28b, RTL_GIGA_MAC_VER_31 },
2199
2200                 /* 8168C family. */
2201                 { 0x7cf, 0x3c9, RTL_GIGA_MAC_VER_23 },
2202                 { 0x7cf, 0x3c8, RTL_GIGA_MAC_VER_18 },
2203                 { 0x7c8, 0x3c8, RTL_GIGA_MAC_VER_24 },
2204                 { 0x7cf, 0x3c0, RTL_GIGA_MAC_VER_19 },
2205                 { 0x7cf, 0x3c2, RTL_GIGA_MAC_VER_20 },
2206                 { 0x7cf, 0x3c3, RTL_GIGA_MAC_VER_21 },
2207                 { 0x7c8, 0x3c0, RTL_GIGA_MAC_VER_22 },
2208
2209                 /* 8168B family. */
2210                 { 0x7cf, 0x380, RTL_GIGA_MAC_VER_12 },
2211                 { 0x7c8, 0x380, RTL_GIGA_MAC_VER_17 },
2212                 { 0x7c8, 0x300, RTL_GIGA_MAC_VER_11 },
2213
2214                 /* 8101 family. */
2215                 { 0x7c8, 0x448, RTL_GIGA_MAC_VER_39 },
2216                 { 0x7c8, 0x440, RTL_GIGA_MAC_VER_37 },
2217                 { 0x7cf, 0x409, RTL_GIGA_MAC_VER_29 },
2218                 { 0x7c8, 0x408, RTL_GIGA_MAC_VER_30 },
2219                 { 0x7cf, 0x349, RTL_GIGA_MAC_VER_08 },
2220                 { 0x7cf, 0x249, RTL_GIGA_MAC_VER_08 },
2221                 { 0x7cf, 0x348, RTL_GIGA_MAC_VER_07 },
2222                 { 0x7cf, 0x248, RTL_GIGA_MAC_VER_07 },
2223                 { 0x7cf, 0x340, RTL_GIGA_MAC_VER_13 },
2224                 { 0x7cf, 0x343, RTL_GIGA_MAC_VER_10 },
2225                 { 0x7cf, 0x342, RTL_GIGA_MAC_VER_16 },
2226                 { 0x7c8, 0x348, RTL_GIGA_MAC_VER_09 },
2227                 { 0x7c8, 0x248, RTL_GIGA_MAC_VER_09 },
2228                 { 0x7c8, 0x340, RTL_GIGA_MAC_VER_16 },
2229                 /* FIXME: where did these entries come from ? -- FR */
2230                 { 0xfc8, 0x388, RTL_GIGA_MAC_VER_15 },
2231                 { 0xfc8, 0x308, RTL_GIGA_MAC_VER_14 },
2232
2233                 /* 8110 family. */
2234                 { 0xfc8, 0x980, RTL_GIGA_MAC_VER_06 },
2235                 { 0xfc8, 0x180, RTL_GIGA_MAC_VER_05 },
2236                 { 0xfc8, 0x100, RTL_GIGA_MAC_VER_04 },
2237                 { 0xfc8, 0x040, RTL_GIGA_MAC_VER_03 },
2238                 { 0xfc8, 0x008, RTL_GIGA_MAC_VER_02 },
2239
2240                 /* Catch-all */
2241                 { 0x000, 0x000, RTL_GIGA_MAC_NONE   }
2242         };
2243         const struct rtl_mac_info *p = mac_info;
2244         u16 reg = RTL_R32(tp, TxConfig) >> 20;
2245
2246         while ((reg & p->mask) != p->val)
2247                 p++;
2248         tp->mac_version = p->mac_version;
2249
2250         if (tp->mac_version == RTL_GIGA_MAC_NONE) {
2251                 dev_err(tp_to_dev(tp), "unknown chip XID %03x\n", reg & 0xfcf);
2252         } else if (!tp->supports_gmii) {
2253                 if (tp->mac_version == RTL_GIGA_MAC_VER_42)
2254                         tp->mac_version = RTL_GIGA_MAC_VER_43;
2255                 else if (tp->mac_version == RTL_GIGA_MAC_VER_45)
2256                         tp->mac_version = RTL_GIGA_MAC_VER_47;
2257                 else if (tp->mac_version == RTL_GIGA_MAC_VER_46)
2258                         tp->mac_version = RTL_GIGA_MAC_VER_48;
2259         }
2260 }
2261
2262 struct phy_reg {
2263         u16 reg;
2264         u16 val;
2265 };
2266
2267 static void __rtl_writephy_batch(struct rtl8169_private *tp,
2268                                  const struct phy_reg *regs, int len)
2269 {
2270         while (len-- > 0) {
2271                 rtl_writephy(tp, regs->reg, regs->val);
2272                 regs++;
2273         }
2274 }
2275
2276 #define rtl_writephy_batch(tp, a) __rtl_writephy_batch(tp, a, ARRAY_SIZE(a))
2277
2278 static void rtl_release_firmware(struct rtl8169_private *tp)
2279 {
2280         if (tp->rtl_fw) {
2281                 rtl_fw_release_firmware(tp->rtl_fw);
2282                 kfree(tp->rtl_fw);
2283                 tp->rtl_fw = NULL;
2284         }
2285 }
2286
2287 static void rtl_apply_firmware(struct rtl8169_private *tp)
2288 {
2289         /* TODO: release firmware if rtl_fw_write_firmware signals failure. */
2290         if (tp->rtl_fw)
2291                 rtl_fw_write_firmware(tp, tp->rtl_fw);
2292 }
2293
2294 static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
2295 {
2296         if (rtl_readphy(tp, reg) != val)
2297                 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
2298         else
2299                 rtl_apply_firmware(tp);
2300 }
2301
2302 static void rtl8168_config_eee_mac(struct rtl8169_private *tp)
2303 {
2304         /* Adjust EEE LED frequency */
2305         if (tp->mac_version != RTL_GIGA_MAC_VER_38)
2306                 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
2307
2308         rtl_eri_set_bits(tp, 0x1b0, ERIAR_MASK_1111, 0x0003);
2309 }
2310
2311 static void rtl8168f_config_eee_phy(struct rtl8169_private *tp)
2312 {
2313         struct phy_device *phydev = tp->phydev;
2314
2315         phy_write(phydev, 0x1f, 0x0007);
2316         phy_write(phydev, 0x1e, 0x0020);
2317         phy_set_bits(phydev, 0x15, BIT(8));
2318
2319         phy_write(phydev, 0x1f, 0x0005);
2320         phy_write(phydev, 0x05, 0x8b85);
2321         phy_set_bits(phydev, 0x06, BIT(13));
2322
2323         phy_write(phydev, 0x1f, 0x0000);
2324 }
2325
2326 static void rtl8168g_config_eee_phy(struct rtl8169_private *tp)
2327 {
2328         phy_modify_paged(tp->phydev, 0x0a43, 0x11, 0, BIT(4));
2329 }
2330
2331 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
2332 {
2333         static const struct phy_reg phy_reg_init[] = {
2334                 { 0x1f, 0x0001 },
2335                 { 0x06, 0x006e },
2336                 { 0x08, 0x0708 },
2337                 { 0x15, 0x4000 },
2338                 { 0x18, 0x65c7 },
2339
2340                 { 0x1f, 0x0001 },
2341                 { 0x03, 0x00a1 },
2342                 { 0x02, 0x0008 },
2343                 { 0x01, 0x0120 },
2344                 { 0x00, 0x1000 },
2345                 { 0x04, 0x0800 },
2346                 { 0x04, 0x0000 },
2347
2348                 { 0x03, 0xff41 },
2349                 { 0x02, 0xdf60 },
2350                 { 0x01, 0x0140 },
2351                 { 0x00, 0x0077 },
2352                 { 0x04, 0x7800 },
2353                 { 0x04, 0x7000 },
2354
2355                 { 0x03, 0x802f },
2356                 { 0x02, 0x4f02 },
2357                 { 0x01, 0x0409 },
2358                 { 0x00, 0xf0f9 },
2359                 { 0x04, 0x9800 },
2360                 { 0x04, 0x9000 },
2361
2362                 { 0x03, 0xdf01 },
2363                 { 0x02, 0xdf20 },
2364                 { 0x01, 0xff95 },
2365                 { 0x00, 0xba00 },
2366                 { 0x04, 0xa800 },
2367                 { 0x04, 0xa000 },
2368
2369                 { 0x03, 0xff41 },
2370                 { 0x02, 0xdf20 },
2371                 { 0x01, 0x0140 },
2372                 { 0x00, 0x00bb },
2373                 { 0x04, 0xb800 },
2374                 { 0x04, 0xb000 },
2375
2376                 { 0x03, 0xdf41 },
2377                 { 0x02, 0xdc60 },
2378                 { 0x01, 0x6340 },
2379                 { 0x00, 0x007d },
2380                 { 0x04, 0xd800 },
2381                 { 0x04, 0xd000 },
2382
2383                 { 0x03, 0xdf01 },
2384                 { 0x02, 0xdf20 },
2385                 { 0x01, 0x100a },
2386                 { 0x00, 0xa0ff },
2387                 { 0x04, 0xf800 },
2388                 { 0x04, 0xf000 },
2389
2390                 { 0x1f, 0x0000 },
2391                 { 0x0b, 0x0000 },
2392                 { 0x00, 0x9200 }
2393         };
2394
2395         rtl_writephy_batch(tp, phy_reg_init);
2396 }
2397
2398 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
2399 {
2400         static const struct phy_reg phy_reg_init[] = {
2401                 { 0x1f, 0x0002 },
2402                 { 0x01, 0x90d0 },
2403                 { 0x1f, 0x0000 }
2404         };
2405
2406         rtl_writephy_batch(tp, phy_reg_init);
2407 }
2408
2409 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2410 {
2411         struct pci_dev *pdev = tp->pci_dev;
2412
2413         if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
2414             (pdev->subsystem_device != 0xe000))
2415                 return;
2416
2417         rtl_writephy(tp, 0x1f, 0x0001);
2418         rtl_writephy(tp, 0x10, 0xf01b);
2419         rtl_writephy(tp, 0x1f, 0x0000);
2420 }
2421
2422 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2423 {
2424         static const struct phy_reg phy_reg_init[] = {
2425                 { 0x1f, 0x0001 },
2426                 { 0x04, 0x0000 },
2427                 { 0x03, 0x00a1 },
2428                 { 0x02, 0x0008 },
2429                 { 0x01, 0x0120 },
2430                 { 0x00, 0x1000 },
2431                 { 0x04, 0x0800 },
2432                 { 0x04, 0x9000 },
2433                 { 0x03, 0x802f },
2434                 { 0x02, 0x4f02 },
2435                 { 0x01, 0x0409 },
2436                 { 0x00, 0xf099 },
2437                 { 0x04, 0x9800 },
2438                 { 0x04, 0xa000 },
2439                 { 0x03, 0xdf01 },
2440                 { 0x02, 0xdf20 },
2441                 { 0x01, 0xff95 },
2442                 { 0x00, 0xba00 },
2443                 { 0x04, 0xa800 },
2444                 { 0x04, 0xf000 },
2445                 { 0x03, 0xdf01 },
2446                 { 0x02, 0xdf20 },
2447                 { 0x01, 0x101a },
2448                 { 0x00, 0xa0ff },
2449                 { 0x04, 0xf800 },
2450                 { 0x04, 0x0000 },
2451                 { 0x1f, 0x0000 },
2452
2453                 { 0x1f, 0x0001 },
2454                 { 0x10, 0xf41b },
2455                 { 0x14, 0xfb54 },
2456                 { 0x18, 0xf5c7 },
2457                 { 0x1f, 0x0000 },
2458
2459                 { 0x1f, 0x0001 },
2460                 { 0x17, 0x0cc0 },
2461                 { 0x1f, 0x0000 }
2462         };
2463
2464         rtl_writephy_batch(tp, phy_reg_init);
2465
2466         rtl8169scd_hw_phy_config_quirk(tp);
2467 }
2468
2469 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
2470 {
2471         static const struct phy_reg phy_reg_init[] = {
2472                 { 0x1f, 0x0001 },
2473                 { 0x04, 0x0000 },
2474                 { 0x03, 0x00a1 },
2475                 { 0x02, 0x0008 },
2476                 { 0x01, 0x0120 },
2477                 { 0x00, 0x1000 },
2478                 { 0x04, 0x0800 },
2479                 { 0x04, 0x9000 },
2480                 { 0x03, 0x802f },
2481                 { 0x02, 0x4f02 },
2482                 { 0x01, 0x0409 },
2483                 { 0x00, 0xf099 },
2484                 { 0x04, 0x9800 },
2485                 { 0x04, 0xa000 },
2486                 { 0x03, 0xdf01 },
2487                 { 0x02, 0xdf20 },
2488                 { 0x01, 0xff95 },
2489                 { 0x00, 0xba00 },
2490                 { 0x04, 0xa800 },
2491                 { 0x04, 0xf000 },
2492                 { 0x03, 0xdf01 },
2493                 { 0x02, 0xdf20 },
2494                 { 0x01, 0x101a },
2495                 { 0x00, 0xa0ff },
2496                 { 0x04, 0xf800 },
2497                 { 0x04, 0x0000 },
2498                 { 0x1f, 0x0000 },
2499
2500                 { 0x1f, 0x0001 },
2501                 { 0x0b, 0x8480 },
2502                 { 0x1f, 0x0000 },
2503
2504                 { 0x1f, 0x0001 },
2505                 { 0x18, 0x67c7 },
2506                 { 0x04, 0x2000 },
2507                 { 0x03, 0x002f },
2508                 { 0x02, 0x4360 },
2509                 { 0x01, 0x0109 },
2510                 { 0x00, 0x3022 },
2511                 { 0x04, 0x2800 },
2512                 { 0x1f, 0x0000 },
2513
2514                 { 0x1f, 0x0001 },
2515                 { 0x17, 0x0cc0 },
2516                 { 0x1f, 0x0000 }
2517         };
2518
2519         rtl_writephy_batch(tp, phy_reg_init);
2520 }
2521
2522 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
2523 {
2524         static const struct phy_reg phy_reg_init[] = {
2525                 { 0x10, 0xf41b },
2526                 { 0x1f, 0x0000 }
2527         };
2528
2529         rtl_writephy(tp, 0x1f, 0x0001);
2530         rtl_patchphy(tp, 0x16, 1 << 0);
2531
2532         rtl_writephy_batch(tp, phy_reg_init);
2533 }
2534
2535 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
2536 {
2537         static const struct phy_reg phy_reg_init[] = {
2538                 { 0x1f, 0x0001 },
2539                 { 0x10, 0xf41b },
2540                 { 0x1f, 0x0000 }
2541         };
2542
2543         rtl_writephy_batch(tp, phy_reg_init);
2544 }
2545
2546 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
2547 {
2548         static const struct phy_reg phy_reg_init[] = {
2549                 { 0x1f, 0x0000 },
2550                 { 0x1d, 0x0f00 },
2551                 { 0x1f, 0x0002 },
2552                 { 0x0c, 0x1ec8 },
2553                 { 0x1f, 0x0000 }
2554         };
2555
2556         rtl_writephy_batch(tp, phy_reg_init);
2557 }
2558
2559 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
2560 {
2561         static const struct phy_reg phy_reg_init[] = {
2562                 { 0x1f, 0x0001 },
2563                 { 0x1d, 0x3d98 },
2564                 { 0x1f, 0x0000 }
2565         };
2566
2567         rtl_writephy(tp, 0x1f, 0x0000);
2568         rtl_patchphy(tp, 0x14, 1 << 5);
2569         rtl_patchphy(tp, 0x0d, 1 << 5);
2570
2571         rtl_writephy_batch(tp, phy_reg_init);
2572 }
2573
2574 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
2575 {
2576         static const struct phy_reg phy_reg_init[] = {
2577                 { 0x1f, 0x0001 },
2578                 { 0x12, 0x2300 },
2579                 { 0x1f, 0x0002 },
2580                 { 0x00, 0x88d4 },
2581                 { 0x01, 0x82b1 },
2582                 { 0x03, 0x7002 },
2583                 { 0x08, 0x9e30 },
2584                 { 0x09, 0x01f0 },
2585                 { 0x0a, 0x5500 },
2586                 { 0x0c, 0x00c8 },
2587                 { 0x1f, 0x0003 },
2588                 { 0x12, 0xc096 },
2589                 { 0x16, 0x000a },
2590                 { 0x1f, 0x0000 },
2591                 { 0x1f, 0x0000 },
2592                 { 0x09, 0x2000 },
2593                 { 0x09, 0x0000 }
2594         };
2595
2596         rtl_writephy_batch(tp, phy_reg_init);
2597
2598         rtl_patchphy(tp, 0x14, 1 << 5);
2599         rtl_patchphy(tp, 0x0d, 1 << 5);
2600         rtl_writephy(tp, 0x1f, 0x0000);
2601 }
2602
2603 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
2604 {
2605         static const struct phy_reg phy_reg_init[] = {
2606                 { 0x1f, 0x0001 },
2607                 { 0x12, 0x2300 },
2608                 { 0x03, 0x802f },
2609                 { 0x02, 0x4f02 },
2610                 { 0x01, 0x0409 },
2611                 { 0x00, 0xf099 },
2612                 { 0x04, 0x9800 },
2613                 { 0x04, 0x9000 },
2614                 { 0x1d, 0x3d98 },
2615                 { 0x1f, 0x0002 },
2616                 { 0x0c, 0x7eb8 },
2617                 { 0x06, 0x0761 },
2618                 { 0x1f, 0x0003 },
2619                 { 0x16, 0x0f0a },
2620                 { 0x1f, 0x0000 }
2621         };
2622
2623         rtl_writephy_batch(tp, phy_reg_init);
2624
2625         rtl_patchphy(tp, 0x16, 1 << 0);
2626         rtl_patchphy(tp, 0x14, 1 << 5);
2627         rtl_patchphy(tp, 0x0d, 1 << 5);
2628         rtl_writephy(tp, 0x1f, 0x0000);
2629 }
2630
2631 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
2632 {
2633         static const struct phy_reg phy_reg_init[] = {
2634                 { 0x1f, 0x0001 },
2635                 { 0x12, 0x2300 },
2636                 { 0x1d, 0x3d98 },
2637                 { 0x1f, 0x0002 },
2638                 { 0x0c, 0x7eb8 },
2639                 { 0x06, 0x5461 },
2640                 { 0x1f, 0x0003 },
2641                 { 0x16, 0x0f0a },
2642                 { 0x1f, 0x0000 }
2643         };
2644
2645         rtl_writephy_batch(tp, phy_reg_init);
2646
2647         rtl_patchphy(tp, 0x16, 1 << 0);
2648         rtl_patchphy(tp, 0x14, 1 << 5);
2649         rtl_patchphy(tp, 0x0d, 1 << 5);
2650         rtl_writephy(tp, 0x1f, 0x0000);
2651 }
2652
2653 static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
2654 {
2655         rtl8168c_3_hw_phy_config(tp);
2656 }
2657
2658 static const struct phy_reg rtl8168d_1_phy_reg_init_0[] = {
2659         /* Channel Estimation */
2660         { 0x1f, 0x0001 },
2661         { 0x06, 0x4064 },
2662         { 0x07, 0x2863 },
2663         { 0x08, 0x059c },
2664         { 0x09, 0x26b4 },
2665         { 0x0a, 0x6a19 },
2666         { 0x0b, 0xdcc8 },
2667         { 0x10, 0xf06d },
2668         { 0x14, 0x7f68 },
2669         { 0x18, 0x7fd9 },
2670         { 0x1c, 0xf0ff },
2671         { 0x1d, 0x3d9c },
2672         { 0x1f, 0x0003 },
2673         { 0x12, 0xf49f },
2674         { 0x13, 0x070b },
2675         { 0x1a, 0x05ad },
2676         { 0x14, 0x94c0 },
2677
2678         /*
2679          * Tx Error Issue
2680          * Enhance line driver power
2681          */
2682         { 0x1f, 0x0002 },
2683         { 0x06, 0x5561 },
2684         { 0x1f, 0x0005 },
2685         { 0x05, 0x8332 },
2686         { 0x06, 0x5561 },
2687
2688         /*
2689          * Can not link to 1Gbps with bad cable
2690          * Decrease SNR threshold form 21.07dB to 19.04dB
2691          */
2692         { 0x1f, 0x0001 },
2693         { 0x17, 0x0cc0 },
2694
2695         { 0x1f, 0x0000 },
2696         { 0x0d, 0xf880 }
2697 };
2698
2699 static const struct phy_reg rtl8168d_1_phy_reg_init_1[] = {
2700         { 0x1f, 0x0002 },
2701         { 0x05, 0x669a },
2702         { 0x1f, 0x0005 },
2703         { 0x05, 0x8330 },
2704         { 0x06, 0x669a },
2705         { 0x1f, 0x0002 }
2706 };
2707
2708 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
2709 {
2710         rtl_writephy_batch(tp, rtl8168d_1_phy_reg_init_0);
2711
2712         /*
2713          * Rx Error Issue
2714          * Fine Tune Switching regulator parameter
2715          */
2716         rtl_writephy(tp, 0x1f, 0x0002);
2717         rtl_w0w1_phy(tp, 0x0b, 0x0010, 0x00ef);
2718         rtl_w0w1_phy(tp, 0x0c, 0xa200, 0x5d00);
2719
2720         if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
2721                 int val;
2722
2723                 rtl_writephy_batch(tp, rtl8168d_1_phy_reg_init_1);
2724
2725                 val = rtl_readphy(tp, 0x0d);
2726
2727                 if ((val & 0x00ff) != 0x006c) {
2728                         static const u32 set[] = {
2729                                 0x0065, 0x0066, 0x0067, 0x0068,
2730                                 0x0069, 0x006a, 0x006b, 0x006c
2731                         };
2732                         int i;
2733
2734                         rtl_writephy(tp, 0x1f, 0x0002);
2735
2736                         val &= 0xff00;
2737                         for (i = 0; i < ARRAY_SIZE(set); i++)
2738                                 rtl_writephy(tp, 0x0d, val | set[i]);
2739                 }
2740         } else {
2741                 static const struct phy_reg phy_reg_init[] = {
2742                         { 0x1f, 0x0002 },
2743                         { 0x05, 0x6662 },
2744                         { 0x1f, 0x0005 },
2745                         { 0x05, 0x8330 },
2746                         { 0x06, 0x6662 }
2747                 };
2748
2749                 rtl_writephy_batch(tp, phy_reg_init);
2750         }
2751
2752         /* RSET couple improve */
2753         rtl_writephy(tp, 0x1f, 0x0002);
2754         rtl_patchphy(tp, 0x0d, 0x0300);
2755         rtl_patchphy(tp, 0x0f, 0x0010);
2756
2757         /* Fine tune PLL performance */
2758         rtl_writephy(tp, 0x1f, 0x0002);
2759         rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
2760         rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
2761
2762         rtl_writephy(tp, 0x1f, 0x0005);
2763         rtl_writephy(tp, 0x05, 0x001b);
2764
2765         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
2766
2767         rtl_writephy(tp, 0x1f, 0x0000);
2768 }
2769
2770 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
2771 {
2772         rtl_writephy_batch(tp, rtl8168d_1_phy_reg_init_0);
2773
2774         if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
2775                 int val;
2776
2777                 rtl_writephy_batch(tp, rtl8168d_1_phy_reg_init_1);
2778
2779                 val = rtl_readphy(tp, 0x0d);
2780                 if ((val & 0x00ff) != 0x006c) {
2781                         static const u32 set[] = {
2782                                 0x0065, 0x0066, 0x0067, 0x0068,
2783                                 0x0069, 0x006a, 0x006b, 0x006c
2784                         };
2785                         int i;
2786
2787                         rtl_writephy(tp, 0x1f, 0x0002);
2788
2789                         val &= 0xff00;
2790                         for (i = 0; i < ARRAY_SIZE(set); i++)
2791                                 rtl_writephy(tp, 0x0d, val | set[i]);
2792                 }
2793         } else {
2794                 static const struct phy_reg phy_reg_init[] = {
2795                         { 0x1f, 0x0002 },
2796                         { 0x05, 0x2642 },
2797                         { 0x1f, 0x0005 },
2798                         { 0x05, 0x8330 },
2799                         { 0x06, 0x2642 }
2800                 };
2801
2802                 rtl_writephy_batch(tp, phy_reg_init);
2803         }
2804
2805         /* Fine tune PLL performance */
2806         rtl_writephy(tp, 0x1f, 0x0002);
2807         rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
2808         rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
2809
2810         /* Switching regulator Slew rate */
2811         rtl_writephy(tp, 0x1f, 0x0002);
2812         rtl_patchphy(tp, 0x0f, 0x0017);
2813
2814         rtl_writephy(tp, 0x1f, 0x0005);
2815         rtl_writephy(tp, 0x05, 0x001b);
2816
2817         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
2818
2819         rtl_writephy(tp, 0x1f, 0x0000);
2820 }
2821
2822 static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
2823 {
2824         static const struct phy_reg phy_reg_init[] = {
2825                 { 0x1f, 0x0002 },
2826                 { 0x10, 0x0008 },
2827                 { 0x0d, 0x006c },
2828
2829                 { 0x1f, 0x0000 },
2830                 { 0x0d, 0xf880 },
2831
2832                 { 0x1f, 0x0001 },
2833                 { 0x17, 0x0cc0 },
2834
2835                 { 0x1f, 0x0001 },
2836                 { 0x0b, 0xa4d8 },
2837                 { 0x09, 0x281c },
2838                 { 0x07, 0x2883 },
2839                 { 0x0a, 0x6b35 },
2840                 { 0x1d, 0x3da4 },
2841                 { 0x1c, 0xeffd },
2842                 { 0x14, 0x7f52 },
2843                 { 0x18, 0x7fc6 },
2844                 { 0x08, 0x0601 },
2845                 { 0x06, 0x4063 },
2846                 { 0x10, 0xf074 },
2847                 { 0x1f, 0x0003 },
2848                 { 0x13, 0x0789 },
2849                 { 0x12, 0xf4bd },
2850                 { 0x1a, 0x04fd },
2851                 { 0x14, 0x84b0 },
2852                 { 0x1f, 0x0000 },
2853                 { 0x00, 0x9200 },
2854
2855                 { 0x1f, 0x0005 },
2856                 { 0x01, 0x0340 },
2857                 { 0x1f, 0x0001 },
2858                 { 0x04, 0x4000 },
2859                 { 0x03, 0x1d21 },
2860                 { 0x02, 0x0c32 },
2861                 { 0x01, 0x0200 },
2862                 { 0x00, 0x5554 },
2863                 { 0x04, 0x4800 },
2864                 { 0x04, 0x4000 },
2865                 { 0x04, 0xf000 },
2866                 { 0x03, 0xdf01 },
2867                 { 0x02, 0xdf20 },
2868                 { 0x01, 0x101a },
2869                 { 0x00, 0xa0ff },
2870                 { 0x04, 0xf800 },
2871                 { 0x04, 0xf000 },
2872                 { 0x1f, 0x0000 },
2873
2874                 { 0x1f, 0x0007 },
2875                 { 0x1e, 0x0023 },
2876                 { 0x16, 0x0000 },
2877                 { 0x1f, 0x0000 }
2878         };
2879
2880         rtl_writephy_batch(tp, phy_reg_init);
2881 }
2882
2883 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
2884 {
2885         static const struct phy_reg phy_reg_init[] = {
2886                 { 0x1f, 0x0001 },
2887                 { 0x17, 0x0cc0 },
2888
2889                 { 0x1f, 0x0007 },
2890                 { 0x1e, 0x002d },
2891                 { 0x18, 0x0040 },
2892                 { 0x1f, 0x0000 }
2893         };
2894
2895         rtl_writephy_batch(tp, phy_reg_init);
2896         rtl_patchphy(tp, 0x0d, 1 << 5);
2897 }
2898
2899 static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
2900 {
2901         static const struct phy_reg phy_reg_init[] = {
2902                 /* Enable Delay cap */
2903                 { 0x1f, 0x0005 },
2904                 { 0x05, 0x8b80 },
2905                 { 0x06, 0xc896 },
2906                 { 0x1f, 0x0000 },
2907
2908                 /* Channel estimation fine tune */
2909                 { 0x1f, 0x0001 },
2910                 { 0x0b, 0x6c20 },
2911                 { 0x07, 0x2872 },
2912                 { 0x1c, 0xefff },
2913                 { 0x1f, 0x0003 },
2914                 { 0x14, 0x6420 },
2915                 { 0x1f, 0x0000 },
2916
2917                 /* Update PFM & 10M TX idle timer */
2918                 { 0x1f, 0x0007 },
2919                 { 0x1e, 0x002f },
2920                 { 0x15, 0x1919 },
2921                 { 0x1f, 0x0000 },
2922
2923                 { 0x1f, 0x0007 },
2924                 { 0x1e, 0x00ac },
2925                 { 0x18, 0x0006 },
2926                 { 0x1f, 0x0000 }
2927         };
2928
2929         rtl_apply_firmware(tp);
2930
2931         rtl_writephy_batch(tp, phy_reg_init);
2932
2933         /* DCO enable for 10M IDLE Power */
2934         rtl_writephy(tp, 0x1f, 0x0007);
2935         rtl_writephy(tp, 0x1e, 0x0023);
2936         rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
2937         rtl_writephy(tp, 0x1f, 0x0000);
2938
2939         /* For impedance matching */
2940         rtl_writephy(tp, 0x1f, 0x0002);
2941         rtl_w0w1_phy(tp, 0x08, 0x8000, 0x7f00);
2942         rtl_writephy(tp, 0x1f, 0x0000);
2943
2944         /* PHY auto speed down */
2945         rtl_writephy(tp, 0x1f, 0x0007);
2946         rtl_writephy(tp, 0x1e, 0x002d);
2947         rtl_w0w1_phy(tp, 0x18, 0x0050, 0x0000);
2948         rtl_writephy(tp, 0x1f, 0x0000);
2949         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
2950
2951         rtl_writephy(tp, 0x1f, 0x0005);
2952         rtl_writephy(tp, 0x05, 0x8b86);
2953         rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
2954         rtl_writephy(tp, 0x1f, 0x0000);
2955
2956         rtl_writephy(tp, 0x1f, 0x0005);
2957         rtl_writephy(tp, 0x05, 0x8b85);
2958         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
2959         rtl_writephy(tp, 0x1f, 0x0007);
2960         rtl_writephy(tp, 0x1e, 0x0020);
2961         rtl_w0w1_phy(tp, 0x15, 0x0000, 0x1100);
2962         rtl_writephy(tp, 0x1f, 0x0006);
2963         rtl_writephy(tp, 0x00, 0x5a00);
2964         rtl_writephy(tp, 0x1f, 0x0000);
2965         rtl_writephy(tp, 0x0d, 0x0007);
2966         rtl_writephy(tp, 0x0e, 0x003c);
2967         rtl_writephy(tp, 0x0d, 0x4007);
2968         rtl_writephy(tp, 0x0e, 0x0000);
2969         rtl_writephy(tp, 0x0d, 0x0000);
2970 }
2971
2972 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, u8 *addr)
2973 {
2974         const u16 w[] = {
2975                 addr[0] | (addr[1] << 8),
2976                 addr[2] | (addr[3] << 8),
2977                 addr[4] | (addr[5] << 8)
2978         };
2979
2980         rtl_eri_write(tp, 0xe0, ERIAR_MASK_1111, w[0] | (w[1] << 16));
2981         rtl_eri_write(tp, 0xe4, ERIAR_MASK_1111, w[2]);
2982         rtl_eri_write(tp, 0xf0, ERIAR_MASK_1111, w[0] << 16);
2983         rtl_eri_write(tp, 0xf4, ERIAR_MASK_1111, w[1] | (w[2] << 16));
2984 }
2985
2986 static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
2987 {
2988         static const struct phy_reg phy_reg_init[] = {
2989                 /* Enable Delay cap */
2990                 { 0x1f, 0x0004 },
2991                 { 0x1f, 0x0007 },
2992                 { 0x1e, 0x00ac },
2993                 { 0x18, 0x0006 },
2994                 { 0x1f, 0x0002 },
2995                 { 0x1f, 0x0000 },
2996                 { 0x1f, 0x0000 },
2997
2998                 /* Channel estimation fine tune */
2999                 { 0x1f, 0x0003 },
3000                 { 0x09, 0xa20f },
3001                 { 0x1f, 0x0000 },
3002                 { 0x1f, 0x0000 },
3003
3004                 /* Green Setting */
3005                 { 0x1f, 0x0005 },
3006                 { 0x05, 0x8b5b },
3007                 { 0x06, 0x9222 },
3008                 { 0x05, 0x8b6d },
3009                 { 0x06, 0x8000 },
3010                 { 0x05, 0x8b76 },
3011                 { 0x06, 0x8000 },
3012                 { 0x1f, 0x0000 }
3013         };
3014
3015         rtl_apply_firmware(tp);
3016
3017         rtl_writephy_batch(tp, phy_reg_init);
3018
3019         /* For 4-corner performance improve */
3020         rtl_writephy(tp, 0x1f, 0x0005);
3021         rtl_writephy(tp, 0x05, 0x8b80);
3022         rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
3023         rtl_writephy(tp, 0x1f, 0x0000);
3024
3025         /* PHY auto speed down */
3026         rtl_writephy(tp, 0x1f, 0x0004);
3027         rtl_writephy(tp, 0x1f, 0x0007);
3028         rtl_writephy(tp, 0x1e, 0x002d);
3029         rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
3030         rtl_writephy(tp, 0x1f, 0x0002);
3031         rtl_writephy(tp, 0x1f, 0x0000);
3032         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3033
3034         /* improve 10M EEE waveform */
3035         rtl_writephy(tp, 0x1f, 0x0005);
3036         rtl_writephy(tp, 0x05, 0x8b86);
3037         rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3038         rtl_writephy(tp, 0x1f, 0x0000);
3039
3040         /* Improve 2-pair detection performance */
3041         rtl_writephy(tp, 0x1f, 0x0005);
3042         rtl_writephy(tp, 0x05, 0x8b85);
3043         rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3044         rtl_writephy(tp, 0x1f, 0x0000);
3045
3046         rtl8168f_config_eee_phy(tp);
3047         rtl_enable_eee(tp);
3048
3049         /* Green feature */
3050         rtl_writephy(tp, 0x1f, 0x0003);
3051         rtl_w0w1_phy(tp, 0x19, 0x0001, 0x0000);
3052         rtl_w0w1_phy(tp, 0x10, 0x0400, 0x0000);
3053         rtl_writephy(tp, 0x1f, 0x0000);
3054         rtl_writephy(tp, 0x1f, 0x0005);
3055         rtl_w0w1_phy(tp, 0x01, 0x0100, 0x0000);
3056         rtl_writephy(tp, 0x1f, 0x0000);
3057
3058         /* Broken BIOS workaround: feed GigaMAC registers with MAC address. */
3059         rtl_rar_exgmac_set(tp, tp->dev->dev_addr);
3060 }
3061
3062 static void rtl8168f_hw_phy_config(struct rtl8169_private *tp)
3063 {
3064         /* For 4-corner performance improve */
3065         rtl_writephy(tp, 0x1f, 0x0005);
3066         rtl_writephy(tp, 0x05, 0x8b80);
3067         rtl_w0w1_phy(tp, 0x06, 0x0006, 0x0000);
3068         rtl_writephy(tp, 0x1f, 0x0000);
3069
3070         /* PHY auto speed down */
3071         rtl_writephy(tp, 0x1f, 0x0007);
3072         rtl_writephy(tp, 0x1e, 0x002d);
3073         rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
3074         rtl_writephy(tp, 0x1f, 0x0000);
3075         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3076
3077         /* Improve 10M EEE waveform */
3078         rtl_writephy(tp, 0x1f, 0x0005);
3079         rtl_writephy(tp, 0x05, 0x8b86);
3080         rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3081         rtl_writephy(tp, 0x1f, 0x0000);
3082
3083         rtl8168f_config_eee_phy(tp);
3084         rtl_enable_eee(tp);
3085 }
3086
3087 static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp)
3088 {
3089         static const struct phy_reg phy_reg_init[] = {
3090                 /* Channel estimation fine tune */
3091                 { 0x1f, 0x0003 },
3092                 { 0x09, 0xa20f },
3093                 { 0x1f, 0x0000 },
3094
3095                 /* Modify green table for giga & fnet */
3096                 { 0x1f, 0x0005 },
3097                 { 0x05, 0x8b55 },
3098                 { 0x06, 0x0000 },
3099                 { 0x05, 0x8b5e },
3100                 { 0x06, 0x0000 },
3101                 { 0x05, 0x8b67 },
3102                 { 0x06, 0x0000 },
3103                 { 0x05, 0x8b70 },
3104                 { 0x06, 0x0000 },
3105                 { 0x1f, 0x0000 },
3106                 { 0x1f, 0x0007 },
3107                 { 0x1e, 0x0078 },
3108                 { 0x17, 0x0000 },
3109                 { 0x19, 0x00fb },
3110                 { 0x1f, 0x0000 },
3111
3112                 /* Modify green table for 10M */
3113                 { 0x1f, 0x0005 },
3114                 { 0x05, 0x8b79 },
3115                 { 0x06, 0xaa00 },
3116                 { 0x1f, 0x0000 },
3117
3118                 /* Disable hiimpedance detection (RTCT) */
3119                 { 0x1f, 0x0003 },
3120                 { 0x01, 0x328a },
3121                 { 0x1f, 0x0000 }
3122         };
3123
3124         rtl_apply_firmware(tp);
3125
3126         rtl_writephy_batch(tp, phy_reg_init);
3127
3128         rtl8168f_hw_phy_config(tp);
3129
3130         /* Improve 2-pair detection performance */
3131         rtl_writephy(tp, 0x1f, 0x0005);
3132         rtl_writephy(tp, 0x05, 0x8b85);
3133         rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3134         rtl_writephy(tp, 0x1f, 0x0000);
3135 }
3136
3137 static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp)
3138 {
3139         rtl_apply_firmware(tp);
3140
3141         rtl8168f_hw_phy_config(tp);
3142 }
3143
3144 static void rtl8411_hw_phy_config(struct rtl8169_private *tp)
3145 {
3146         static const struct phy_reg phy_reg_init[] = {
3147                 /* Channel estimation fine tune */
3148                 { 0x1f, 0x0003 },
3149                 { 0x09, 0xa20f },
3150                 { 0x1f, 0x0000 },
3151
3152                 /* Modify green table for giga & fnet */
3153                 { 0x1f, 0x0005 },
3154                 { 0x05, 0x8b55 },
3155                 { 0x06, 0x0000 },
3156                 { 0x05, 0x8b5e },
3157                 { 0x06, 0x0000 },
3158                 { 0x05, 0x8b67 },
3159                 { 0x06, 0x0000 },
3160                 { 0x05, 0x8b70 },
3161                 { 0x06, 0x0000 },
3162                 { 0x1f, 0x0000 },
3163                 { 0x1f, 0x0007 },
3164                 { 0x1e, 0x0078 },
3165                 { 0x17, 0x0000 },
3166                 { 0x19, 0x00aa },
3167                 { 0x1f, 0x0000 },
3168
3169                 /* Modify green table for 10M */
3170                 { 0x1f, 0x0005 },
3171                 { 0x05, 0x8b79 },
3172                 { 0x06, 0xaa00 },
3173                 { 0x1f, 0x0000 },
3174
3175                 /* Disable hiimpedance detection (RTCT) */
3176                 { 0x1f, 0x0003 },
3177                 { 0x01, 0x328a },
3178                 { 0x1f, 0x0000 }
3179         };
3180
3181
3182         rtl_apply_firmware(tp);
3183
3184         rtl8168f_hw_phy_config(tp);
3185
3186         /* Improve 2-pair detection performance */
3187         rtl_writephy(tp, 0x1f, 0x0005);
3188         rtl_writephy(tp, 0x05, 0x8b85);
3189         rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3190         rtl_writephy(tp, 0x1f, 0x0000);
3191
3192         rtl_writephy_batch(tp, phy_reg_init);
3193
3194         /* Modify green table for giga */
3195         rtl_writephy(tp, 0x1f, 0x0005);
3196         rtl_writephy(tp, 0x05, 0x8b54);
3197         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
3198         rtl_writephy(tp, 0x05, 0x8b5d);
3199         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
3200         rtl_writephy(tp, 0x05, 0x8a7c);
3201         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3202         rtl_writephy(tp, 0x05, 0x8a7f);
3203         rtl_w0w1_phy(tp, 0x06, 0x0100, 0x0000);
3204         rtl_writephy(tp, 0x05, 0x8a82);
3205         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3206         rtl_writephy(tp, 0x05, 0x8a85);
3207         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3208         rtl_writephy(tp, 0x05, 0x8a88);
3209         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3210         rtl_writephy(tp, 0x1f, 0x0000);
3211
3212         /* uc same-seed solution */
3213         rtl_writephy(tp, 0x1f, 0x0005);
3214         rtl_writephy(tp, 0x05, 0x8b85);
3215         rtl_w0w1_phy(tp, 0x06, 0x8000, 0x0000);
3216         rtl_writephy(tp, 0x1f, 0x0000);
3217
3218         /* Green feature */
3219         rtl_writephy(tp, 0x1f, 0x0003);
3220         rtl_w0w1_phy(tp, 0x19, 0x0000, 0x0001);
3221         rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0400);
3222         rtl_writephy(tp, 0x1f, 0x0000);
3223 }
3224
3225 static void rtl8168g_disable_aldps(struct rtl8169_private *tp)
3226 {
3227         phy_modify_paged(tp->phydev, 0x0a43, 0x10, BIT(2), 0);
3228 }
3229
3230 static void rtl8168g_phy_adjust_10m_aldps(struct rtl8169_private *tp)
3231 {
3232         struct phy_device *phydev = tp->phydev;
3233
3234         phy_modify_paged(phydev, 0x0bcc, 0x14, BIT(8), 0);
3235         phy_modify_paged(phydev, 0x0a44, 0x11, 0, BIT(7) | BIT(6));
3236         phy_write(phydev, 0x1f, 0x0a43);
3237         phy_write(phydev, 0x13, 0x8084);
3238         phy_clear_bits(phydev, 0x14, BIT(14) | BIT(13));
3239         phy_set_bits(phydev, 0x10, BIT(12) | BIT(1) | BIT(0));
3240
3241         phy_write(phydev, 0x1f, 0x0000);
3242 }
3243
3244 static void rtl8168g_1_hw_phy_config(struct rtl8169_private *tp)
3245 {
3246         int ret;
3247
3248         rtl_apply_firmware(tp);
3249
3250         ret = phy_read_paged(tp->phydev, 0x0a46, 0x10);
3251         if (ret & BIT(8))
3252                 phy_modify_paged(tp->phydev, 0x0bcc, 0x12, BIT(15), 0);
3253         else
3254                 phy_modify_paged(tp->phydev, 0x0bcc, 0x12, 0, BIT(15));
3255
3256         ret = phy_read_paged(tp->phydev, 0x0a46, 0x13);
3257         if (ret & BIT(8))
3258                 phy_modify_paged(tp->phydev, 0x0c41, 0x15, 0, BIT(1));
3259         else
3260                 phy_modify_paged(tp->phydev, 0x0c41, 0x15, BIT(1), 0);
3261
3262         /* Enable PHY auto speed down */
3263         phy_modify_paged(tp->phydev, 0x0a44, 0x11, 0, BIT(3) | BIT(2));
3264
3265         rtl8168g_phy_adjust_10m_aldps(tp);
3266
3267         /* EEE auto-fallback function */
3268         phy_modify_paged(tp->phydev, 0x0a4b, 0x11, 0, BIT(2));
3269
3270         /* Enable UC LPF tune function */
3271         rtl_writephy(tp, 0x1f, 0x0a43);
3272         rtl_writephy(tp, 0x13, 0x8012);
3273         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3274
3275         phy_modify_paged(tp->phydev, 0x0c42, 0x11, BIT(13), BIT(14));
3276
3277         /* Improve SWR Efficiency */
3278         rtl_writephy(tp, 0x1f, 0x0bcd);
3279         rtl_writephy(tp, 0x14, 0x5065);
3280         rtl_writephy(tp, 0x14, 0xd065);
3281         rtl_writephy(tp, 0x1f, 0x0bc8);
3282         rtl_writephy(tp, 0x11, 0x5655);
3283         rtl_writephy(tp, 0x1f, 0x0bcd);
3284         rtl_writephy(tp, 0x14, 0x1065);
3285         rtl_writephy(tp, 0x14, 0x9065);
3286         rtl_writephy(tp, 0x14, 0x1065);
3287         rtl_writephy(tp, 0x1f, 0x0000);
3288
3289         rtl8168g_disable_aldps(tp);
3290         rtl8168g_config_eee_phy(tp);
3291         rtl_enable_eee(tp);
3292 }
3293
3294 static void rtl8168g_2_hw_phy_config(struct rtl8169_private *tp)
3295 {
3296         rtl_apply_firmware(tp);
3297         rtl8168g_config_eee_phy(tp);
3298         rtl_enable_eee(tp);
3299 }
3300
3301 static void rtl8168h_1_hw_phy_config(struct rtl8169_private *tp)
3302 {
3303         u16 dout_tapbin;
3304         u32 data;
3305
3306         rtl_apply_firmware(tp);
3307
3308         /* CHN EST parameters adjust - giga master */
3309         rtl_writephy(tp, 0x1f, 0x0a43);
3310         rtl_writephy(tp, 0x13, 0x809b);
3311         rtl_w0w1_phy(tp, 0x14, 0x8000, 0xf800);
3312         rtl_writephy(tp, 0x13, 0x80a2);
3313         rtl_w0w1_phy(tp, 0x14, 0x8000, 0xff00);
3314         rtl_writephy(tp, 0x13, 0x80a4);
3315         rtl_w0w1_phy(tp, 0x14, 0x8500, 0xff00);
3316         rtl_writephy(tp, 0x13, 0x809c);
3317         rtl_w0w1_phy(tp, 0x14, 0xbd00, 0xff00);
3318         rtl_writephy(tp, 0x1f, 0x0000);
3319
3320         /* CHN EST parameters adjust - giga slave */
3321         rtl_writephy(tp, 0x1f, 0x0a43);
3322         rtl_writephy(tp, 0x13, 0x80ad);
3323         rtl_w0w1_phy(tp, 0x14, 0x7000, 0xf800);
3324         rtl_writephy(tp, 0x13, 0x80b4);
3325         rtl_w0w1_phy(tp, 0x14, 0x5000, 0xff00);
3326         rtl_writephy(tp, 0x13, 0x80ac);
3327         rtl_w0w1_phy(tp, 0x14, 0x4000, 0xff00);
3328         rtl_writephy(tp, 0x1f, 0x0000);
3329
3330         /* CHN EST parameters adjust - fnet */
3331         rtl_writephy(tp, 0x1f, 0x0a43);
3332         rtl_writephy(tp, 0x13, 0x808e);
3333         rtl_w0w1_phy(tp, 0x14, 0x1200, 0xff00);
3334         rtl_writephy(tp, 0x13, 0x8090);
3335         rtl_w0w1_phy(tp, 0x14, 0xe500, 0xff00);
3336         rtl_writephy(tp, 0x13, 0x8092);
3337         rtl_w0w1_phy(tp, 0x14, 0x9f00, 0xff00);
3338         rtl_writephy(tp, 0x1f, 0x0000);
3339
3340         /* enable R-tune & PGA-retune function */
3341         dout_tapbin = 0;
3342         rtl_writephy(tp, 0x1f, 0x0a46);
3343         data = rtl_readphy(tp, 0x13);
3344         data &= 3;
3345         data <<= 2;
3346         dout_tapbin |= data;
3347         data = rtl_readphy(tp, 0x12);
3348         data &= 0xc000;
3349         data >>= 14;
3350         dout_tapbin |= data;
3351         dout_tapbin = ~(dout_tapbin^0x08);
3352         dout_tapbin <<= 12;
3353         dout_tapbin &= 0xf000;
3354         rtl_writephy(tp, 0x1f, 0x0a43);
3355         rtl_writephy(tp, 0x13, 0x827a);
3356         rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3357         rtl_writephy(tp, 0x13, 0x827b);
3358         rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3359         rtl_writephy(tp, 0x13, 0x827c);
3360         rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3361         rtl_writephy(tp, 0x13, 0x827d);
3362         rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3363
3364         rtl_writephy(tp, 0x1f, 0x0a43);
3365         rtl_writephy(tp, 0x13, 0x0811);
3366         rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
3367         rtl_writephy(tp, 0x1f, 0x0a42);
3368         rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
3369         rtl_writephy(tp, 0x1f, 0x0000);
3370
3371         /* enable GPHY 10M */
3372         phy_modify_paged(tp->phydev, 0x0a44, 0x11, 0, BIT(11));
3373
3374         /* SAR ADC performance */
3375         phy_modify_paged(tp->phydev, 0x0bca, 0x17, BIT(12) | BIT(13), BIT(14));
3376
3377         rtl_writephy(tp, 0x1f, 0x0a43);
3378         rtl_writephy(tp, 0x13, 0x803f);
3379         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3380         rtl_writephy(tp, 0x13, 0x8047);
3381         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3382         rtl_writephy(tp, 0x13, 0x804f);
3383         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3384         rtl_writephy(tp, 0x13, 0x8057);
3385         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3386         rtl_writephy(tp, 0x13, 0x805f);
3387         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3388         rtl_writephy(tp, 0x13, 0x8067);
3389         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3390         rtl_writephy(tp, 0x13, 0x806f);
3391         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3392         rtl_writephy(tp, 0x1f, 0x0000);
3393
3394         /* disable phy pfm mode */
3395         phy_modify_paged(tp->phydev, 0x0a44, 0x11, BIT(7), 0);
3396
3397         rtl8168g_disable_aldps(tp);
3398         rtl8168g_config_eee_phy(tp);
3399         rtl_enable_eee(tp);
3400 }
3401
3402 static void rtl8168h_2_hw_phy_config(struct rtl8169_private *tp)
3403 {
3404         u16 ioffset_p3, ioffset_p2, ioffset_p1, ioffset_p0;
3405         u16 rlen;
3406         u32 data;
3407
3408         rtl_apply_firmware(tp);
3409
3410         /* CHIN EST parameter update */
3411         rtl_writephy(tp, 0x1f, 0x0a43);
3412         rtl_writephy(tp, 0x13, 0x808a);
3413         rtl_w0w1_phy(tp, 0x14, 0x000a, 0x003f);
3414         rtl_writephy(tp, 0x1f, 0x0000);
3415
3416         /* enable R-tune & PGA-retune function */
3417         rtl_writephy(tp, 0x1f, 0x0a43);
3418         rtl_writephy(tp, 0x13, 0x0811);
3419         rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
3420         rtl_writephy(tp, 0x1f, 0x0a42);
3421         rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
3422         rtl_writephy(tp, 0x1f, 0x0000);
3423
3424         /* enable GPHY 10M */
3425         phy_modify_paged(tp->phydev, 0x0a44, 0x11, 0, BIT(11));
3426
3427         r8168_mac_ocp_write(tp, 0xdd02, 0x807d);
3428         data = r8168_mac_ocp_read(tp, 0xdd02);
3429         ioffset_p3 = ((data & 0x80)>>7);
3430         ioffset_p3 <<= 3;
3431
3432         data = r8168_mac_ocp_read(tp, 0xdd00);
3433         ioffset_p3 |= ((data & (0xe000))>>13);
3434         ioffset_p2 = ((data & (0x1e00))>>9);
3435         ioffset_p1 = ((data & (0x01e0))>>5);
3436         ioffset_p0 = ((data & 0x0010)>>4);
3437         ioffset_p0 <<= 3;
3438         ioffset_p0 |= (data & (0x07));
3439         data = (ioffset_p3<<12)|(ioffset_p2<<8)|(ioffset_p1<<4)|(ioffset_p0);
3440
3441         if ((ioffset_p3 != 0x0f) || (ioffset_p2 != 0x0f) ||
3442             (ioffset_p1 != 0x0f) || (ioffset_p0 != 0x0f)) {
3443                 rtl_writephy(tp, 0x1f, 0x0bcf);
3444                 rtl_writephy(tp, 0x16, data);
3445                 rtl_writephy(tp, 0x1f, 0x0000);
3446         }
3447
3448         /* Modify rlen (TX LPF corner frequency) level */
3449         rtl_writephy(tp, 0x1f, 0x0bcd);
3450         data = rtl_readphy(tp, 0x16);
3451         data &= 0x000f;
3452         rlen = 0;
3453         if (data > 3)
3454                 rlen = data - 3;
3455         data = rlen | (rlen<<4) | (rlen<<8) | (rlen<<12);
3456         rtl_writephy(tp, 0x17, data);
3457         rtl_writephy(tp, 0x1f, 0x0bcd);
3458         rtl_writephy(tp, 0x1f, 0x0000);
3459
3460         /* disable phy pfm mode */
3461         phy_modify_paged(tp->phydev, 0x0a44, 0x11, BIT(7), 0);
3462
3463         rtl8168g_disable_aldps(tp);
3464         rtl8168g_config_eee_phy(tp);
3465         rtl_enable_eee(tp);
3466 }
3467
3468 static void rtl8168ep_1_hw_phy_config(struct rtl8169_private *tp)
3469 {
3470         /* Enable PHY auto speed down */
3471         phy_modify_paged(tp->phydev, 0x0a44, 0x11, 0, BIT(3) | BIT(2));
3472
3473         rtl8168g_phy_adjust_10m_aldps(tp);
3474
3475         /* Enable EEE auto-fallback function */
3476         phy_modify_paged(tp->phydev, 0x0a4b, 0x11, 0, BIT(2));
3477
3478         /* Enable UC LPF tune function */
3479         rtl_writephy(tp, 0x1f, 0x0a43);
3480         rtl_writephy(tp, 0x13, 0x8012);
3481         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3482         rtl_writephy(tp, 0x1f, 0x0000);
3483
3484         /* set rg_sel_sdm_rate */
3485         phy_modify_paged(tp->phydev, 0x0c42, 0x11, BIT(13), BIT(14));
3486
3487         rtl8168g_disable_aldps(tp);
3488         rtl8168g_config_eee_phy(tp);
3489         rtl_enable_eee(tp);
3490 }
3491
3492 static void rtl8168ep_2_hw_phy_config(struct rtl8169_private *tp)
3493 {
3494         rtl8168g_phy_adjust_10m_aldps(tp);
3495
3496         /* Enable UC LPF tune function */
3497         rtl_writephy(tp, 0x1f, 0x0a43);
3498         rtl_writephy(tp, 0x13, 0x8012);
3499         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3500         rtl_writephy(tp, 0x1f, 0x0000);
3501
3502         /* Set rg_sel_sdm_rate */
3503         phy_modify_paged(tp->phydev, 0x0c42, 0x11, BIT(13), BIT(14));
3504
3505         /* Channel estimation parameters */
3506         rtl_writephy(tp, 0x1f, 0x0a43);
3507         rtl_writephy(tp, 0x13, 0x80f3);
3508         rtl_w0w1_phy(tp, 0x14, 0x8b00, ~0x8bff);
3509         rtl_writephy(tp, 0x13, 0x80f0);
3510         rtl_w0w1_phy(tp, 0x14, 0x3a00, ~0x3aff);
3511         rtl_writephy(tp, 0x13, 0x80ef);
3512         rtl_w0w1_phy(tp, 0x14, 0x0500, ~0x05ff);
3513         rtl_writephy(tp, 0x13, 0x80f6);
3514         rtl_w0w1_phy(tp, 0x14, 0x6e00, ~0x6eff);
3515         rtl_writephy(tp, 0x13, 0x80ec);
3516         rtl_w0w1_phy(tp, 0x14, 0x6800, ~0x68ff);
3517         rtl_writephy(tp, 0x13, 0x80ed);
3518         rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
3519         rtl_writephy(tp, 0x13, 0x80f2);
3520         rtl_w0w1_phy(tp, 0x14, 0xf400, ~0xf4ff);
3521         rtl_writephy(tp, 0x13, 0x80f4);
3522         rtl_w0w1_phy(tp, 0x14, 0x8500, ~0x85ff);
3523         rtl_writephy(tp, 0x1f, 0x0a43);
3524         rtl_writephy(tp, 0x13, 0x8110);
3525         rtl_w0w1_phy(tp, 0x14, 0xa800, ~0xa8ff);
3526         rtl_writephy(tp, 0x13, 0x810f);
3527         rtl_w0w1_phy(tp, 0x14, 0x1d00, ~0x1dff);
3528         rtl_writephy(tp, 0x13, 0x8111);
3529         rtl_w0w1_phy(tp, 0x14, 0xf500, ~0xf5ff);
3530         rtl_writephy(tp, 0x13, 0x8113);
3531         rtl_w0w1_phy(tp, 0x14, 0x6100, ~0x61ff);
3532         rtl_writephy(tp, 0x13, 0x8115);
3533         rtl_w0w1_phy(tp, 0x14, 0x9200, ~0x92ff);
3534         rtl_writephy(tp, 0x13, 0x810e);
3535         rtl_w0w1_phy(tp, 0x14, 0x0400, ~0x04ff);
3536         rtl_writephy(tp, 0x13, 0x810c);
3537         rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
3538         rtl_writephy(tp, 0x13, 0x810b);
3539         rtl_w0w1_phy(tp, 0x14, 0x5a00, ~0x5aff);
3540         rtl_writephy(tp, 0x1f, 0x0a43);
3541         rtl_writephy(tp, 0x13, 0x80d1);
3542         rtl_w0w1_phy(tp, 0x14, 0xff00, ~0xffff);
3543         rtl_writephy(tp, 0x13, 0x80cd);
3544         rtl_w0w1_phy(tp, 0x14, 0x9e00, ~0x9eff);
3545         rtl_writephy(tp, 0x13, 0x80d3);
3546         rtl_w0w1_phy(tp, 0x14, 0x0e00, ~0x0eff);
3547         rtl_writephy(tp, 0x13, 0x80d5);
3548         rtl_w0w1_phy(tp, 0x14, 0xca00, ~0xcaff);
3549         rtl_writephy(tp, 0x13, 0x80d7);
3550         rtl_w0w1_phy(tp, 0x14, 0x8400, ~0x84ff);
3551
3552         /* Force PWM-mode */
3553         rtl_writephy(tp, 0x1f, 0x0bcd);
3554         rtl_writephy(tp, 0x14, 0x5065);
3555         rtl_writephy(tp, 0x14, 0xd065);
3556         rtl_writephy(tp, 0x1f, 0x0bc8);
3557         rtl_writephy(tp, 0x12, 0x00ed);
3558         rtl_writephy(tp, 0x1f, 0x0bcd);
3559         rtl_writephy(tp, 0x14, 0x1065);
3560         rtl_writephy(tp, 0x14, 0x9065);
3561         rtl_writephy(tp, 0x14, 0x1065);
3562         rtl_writephy(tp, 0x1f, 0x0000);
3563
3564         rtl8168g_disable_aldps(tp);
3565         rtl8168g_config_eee_phy(tp);
3566         rtl_enable_eee(tp);
3567 }
3568
3569 static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
3570 {
3571         static const struct phy_reg phy_reg_init[] = {
3572                 { 0x1f, 0x0003 },
3573                 { 0x08, 0x441d },
3574                 { 0x01, 0x9100 },
3575                 { 0x1f, 0x0000 }
3576         };
3577
3578         rtl_writephy(tp, 0x1f, 0x0000);
3579         rtl_patchphy(tp, 0x11, 1 << 12);
3580         rtl_patchphy(tp, 0x19, 1 << 13);
3581         rtl_patchphy(tp, 0x10, 1 << 15);
3582
3583         rtl_writephy_batch(tp, phy_reg_init);
3584 }
3585
3586 static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
3587 {
3588         static const struct phy_reg phy_reg_init[] = {
3589                 { 0x1f, 0x0005 },
3590                 { 0x1a, 0x0000 },
3591                 { 0x1f, 0x0000 },
3592
3593                 { 0x1f, 0x0004 },
3594                 { 0x1c, 0x0000 },
3595                 { 0x1f, 0x0000 },
3596
3597                 { 0x1f, 0x0001 },
3598                 { 0x15, 0x7701 },
3599                 { 0x1f, 0x0000 }
3600         };
3601
3602         /* Disable ALDPS before ram code */
3603         rtl_writephy(tp, 0x1f, 0x0000);
3604         rtl_writephy(tp, 0x18, 0x0310);
3605         msleep(100);
3606
3607         rtl_apply_firmware(tp);
3608
3609         rtl_writephy_batch(tp, phy_reg_init);
3610 }
3611
3612 static void rtl8402_hw_phy_config(struct rtl8169_private *tp)
3613 {
3614         /* Disable ALDPS before setting firmware */
3615         rtl_writephy(tp, 0x1f, 0x0000);
3616         rtl_writephy(tp, 0x18, 0x0310);
3617         msleep(20);
3618
3619         rtl_apply_firmware(tp);
3620
3621         /* EEE setting */
3622         rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000);
3623         rtl_writephy(tp, 0x1f, 0x0004);
3624         rtl_writephy(tp, 0x10, 0x401f);
3625         rtl_writephy(tp, 0x19, 0x7030);
3626         rtl_writephy(tp, 0x1f, 0x0000);
3627 }
3628
3629 static void rtl8106e_hw_phy_config(struct rtl8169_private *tp)
3630 {
3631         static const struct phy_reg phy_reg_init[] = {
3632                 { 0x1f, 0x0004 },
3633                 { 0x10, 0xc07f },
3634                 { 0x19, 0x7030 },
3635                 { 0x1f, 0x0000 }
3636         };
3637
3638         /* Disable ALDPS before ram code */
3639         rtl_writephy(tp, 0x1f, 0x0000);
3640         rtl_writephy(tp, 0x18, 0x0310);
3641         msleep(100);
3642
3643         rtl_apply_firmware(tp);
3644
3645         rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000);
3646         rtl_writephy_batch(tp, phy_reg_init);
3647
3648         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000);
3649 }
3650
3651 static void rtl_hw_phy_config(struct net_device *dev)
3652 {
3653         static const rtl_generic_fct phy_configs[] = {
3654                 /* PCI devices. */
3655                 [RTL_GIGA_MAC_VER_02] = rtl8169s_hw_phy_config,
3656                 [RTL_GIGA_MAC_VER_03] = rtl8169s_hw_phy_config,
3657                 [RTL_GIGA_MAC_VER_04] = rtl8169sb_hw_phy_config,
3658                 [RTL_GIGA_MAC_VER_05] = rtl8169scd_hw_phy_config,
3659                 [RTL_GIGA_MAC_VER_06] = rtl8169sce_hw_phy_config,
3660                 /* PCI-E devices. */
3661                 [RTL_GIGA_MAC_VER_07] = rtl8102e_hw_phy_config,
3662                 [RTL_GIGA_MAC_VER_08] = rtl8102e_hw_phy_config,
3663                 [RTL_GIGA_MAC_VER_09] = rtl8102e_hw_phy_config,
3664                 [RTL_GIGA_MAC_VER_10] = NULL,
3665                 [RTL_GIGA_MAC_VER_11] = rtl8168bb_hw_phy_config,
3666                 [RTL_GIGA_MAC_VER_12] = rtl8168bef_hw_phy_config,
3667                 [RTL_GIGA_MAC_VER_13] = NULL,
3668                 [RTL_GIGA_MAC_VER_14] = NULL,
3669                 [RTL_GIGA_MAC_VER_15] = NULL,
3670                 [RTL_GIGA_MAC_VER_16] = NULL,
3671                 [RTL_GIGA_MAC_VER_17] = rtl8168bef_hw_phy_config,
3672                 [RTL_GIGA_MAC_VER_18] = rtl8168cp_1_hw_phy_config,
3673                 [RTL_GIGA_MAC_VER_19] = rtl8168c_1_hw_phy_config,
3674                 [RTL_GIGA_MAC_VER_20] = rtl8168c_2_hw_phy_config,
3675                 [RTL_GIGA_MAC_VER_21] = rtl8168c_3_hw_phy_config,
3676                 [RTL_GIGA_MAC_VER_22] = rtl8168c_4_hw_phy_config,
3677                 [RTL_GIGA_MAC_VER_23] = rtl8168cp_2_hw_phy_config,
3678                 [RTL_GIGA_MAC_VER_24] = rtl8168cp_2_hw_phy_config,
3679                 [RTL_GIGA_MAC_VER_25] = rtl8168d_1_hw_phy_config,
3680                 [RTL_GIGA_MAC_VER_26] = rtl8168d_2_hw_phy_config,
3681                 [RTL_GIGA_MAC_VER_27] = rtl8168d_3_hw_phy_config,
3682                 [RTL_GIGA_MAC_VER_28] = rtl8168d_4_hw_phy_config,
3683                 [RTL_GIGA_MAC_VER_29] = rtl8105e_hw_phy_config,
3684                 [RTL_GIGA_MAC_VER_30] = rtl8105e_hw_phy_config,
3685                 [RTL_GIGA_MAC_VER_31] = NULL,
3686                 [RTL_GIGA_MAC_VER_32] = rtl8168e_1_hw_phy_config,
3687                 [RTL_GIGA_MAC_VER_33] = rtl8168e_1_hw_phy_config,
3688                 [RTL_GIGA_MAC_VER_34] = rtl8168e_2_hw_phy_config,
3689                 [RTL_GIGA_MAC_VER_35] = rtl8168f_1_hw_phy_config,
3690                 [RTL_GIGA_MAC_VER_36] = rtl8168f_2_hw_phy_config,
3691                 [RTL_GIGA_MAC_VER_37] = rtl8402_hw_phy_config,
3692                 [RTL_GIGA_MAC_VER_38] = rtl8411_hw_phy_config,
3693                 [RTL_GIGA_MAC_VER_39] = rtl8106e_hw_phy_config,
3694                 [RTL_GIGA_MAC_VER_40] = rtl8168g_1_hw_phy_config,
3695                 [RTL_GIGA_MAC_VER_41] = NULL,
3696                 [RTL_GIGA_MAC_VER_42] = rtl8168g_2_hw_phy_config,
3697                 [RTL_GIGA_MAC_VER_43] = rtl8168g_2_hw_phy_config,
3698                 [RTL_GIGA_MAC_VER_44] = rtl8168g_2_hw_phy_config,
3699                 [RTL_GIGA_MAC_VER_45] = rtl8168h_1_hw_phy_config,
3700                 [RTL_GIGA_MAC_VER_46] = rtl8168h_2_hw_phy_config,
3701                 [RTL_GIGA_MAC_VER_47] = rtl8168h_1_hw_phy_config,
3702                 [RTL_GIGA_MAC_VER_48] = rtl8168h_2_hw_phy_config,
3703                 [RTL_GIGA_MAC_VER_49] = rtl8168ep_1_hw_phy_config,
3704                 [RTL_GIGA_MAC_VER_50] = rtl8168ep_2_hw_phy_config,
3705                 [RTL_GIGA_MAC_VER_51] = rtl8168ep_2_hw_phy_config,
3706         };
3707         struct rtl8169_private *tp = netdev_priv(dev);
3708
3709         if (phy_configs[tp->mac_version])
3710                 phy_configs[tp->mac_version](tp);
3711 }
3712
3713 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
3714 {
3715         if (!test_and_set_bit(flag, tp->wk.flags))
3716                 schedule_work(&tp->wk.work);
3717 }
3718
3719 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
3720 {
3721         rtl_hw_phy_config(dev);
3722
3723         if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
3724                 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
3725                 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
3726                 netif_dbg(tp, drv, dev,
3727                           "Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3728                 RTL_W8(tp, 0x82, 0x01);
3729         }
3730
3731         /* We may have called phy_speed_down before */
3732         phy_speed_up(tp->phydev);
3733
3734         genphy_soft_reset(tp->phydev);
3735 }
3736
3737 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
3738 {
3739         rtl_lock_work(tp);
3740
3741         rtl_unlock_config_regs(tp);
3742
3743         RTL_W32(tp, MAC4, addr[4] | addr[5] << 8);
3744         RTL_R32(tp, MAC4);
3745
3746         RTL_W32(tp, MAC0, addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24);
3747         RTL_R32(tp, MAC0);
3748
3749         if (tp->mac_version == RTL_GIGA_MAC_VER_34)
3750                 rtl_rar_exgmac_set(tp, addr);
3751
3752         rtl_lock_config_regs(tp);
3753
3754         rtl_unlock_work(tp);
3755 }
3756
3757 static int rtl_set_mac_address(struct net_device *dev, void *p)
3758 {
3759         struct rtl8169_private *tp = netdev_priv(dev);
3760         struct device *d = tp_to_dev(tp);
3761         int ret;
3762
3763         ret = eth_mac_addr(dev, p);
3764         if (ret)
3765                 return ret;
3766
3767         pm_runtime_get_noresume(d);
3768
3769         if (pm_runtime_active(d))
3770                 rtl_rar_set(tp, dev->dev_addr);
3771
3772         pm_runtime_put_noidle(d);
3773
3774         return 0;
3775 }
3776
3777 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
3778 {
3779         struct rtl8169_private *tp = netdev_priv(dev);
3780
3781         if (!netif_running(dev))
3782                 return -ENODEV;
3783
3784         return phy_mii_ioctl(tp->phydev, ifr, cmd);
3785 }
3786
3787 static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
3788 {
3789         switch (tp->mac_version) {
3790         case RTL_GIGA_MAC_VER_25:
3791         case RTL_GIGA_MAC_VER_26:
3792         case RTL_GIGA_MAC_VER_29:
3793         case RTL_GIGA_MAC_VER_30:
3794         case RTL_GIGA_MAC_VER_32:
3795         case RTL_GIGA_MAC_VER_33:
3796         case RTL_GIGA_MAC_VER_34:
3797         case RTL_GIGA_MAC_VER_37 ... RTL_GIGA_MAC_VER_51:
3798                 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) |
3799                         AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
3800                 break;
3801         default:
3802                 break;
3803         }
3804 }
3805
3806 static void rtl_pll_power_down(struct rtl8169_private *tp)
3807 {
3808         if (r8168_check_dash(tp))
3809                 return;
3810
3811         if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
3812             tp->mac_version == RTL_GIGA_MAC_VER_33)
3813                 rtl_ephy_write(tp, 0x19, 0xff64);
3814
3815         if (device_may_wakeup(tp_to_dev(tp))) {
3816                 phy_speed_down(tp->phydev, false);
3817                 rtl_wol_suspend_quirk(tp);
3818                 return;
3819         }
3820
3821         switch (tp->mac_version) {
3822         case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_33:
3823         case RTL_GIGA_MAC_VER_37:
3824         case RTL_GIGA_MAC_VER_39:
3825         case RTL_GIGA_MAC_VER_43:
3826         case RTL_GIGA_MAC_VER_44:
3827         case RTL_GIGA_MAC_VER_45:
3828         case RTL_GIGA_MAC_VER_46:
3829         case RTL_GIGA_MAC_VER_47:
3830         case RTL_GIGA_MAC_VER_48:
3831         case RTL_GIGA_MAC_VER_50:
3832         case RTL_GIGA_MAC_VER_51:
3833                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80);
3834                 break;
3835         case RTL_GIGA_MAC_VER_40:
3836         case RTL_GIGA_MAC_VER_41:
3837         case RTL_GIGA_MAC_VER_49:
3838                 rtl_eri_clear_bits(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000);
3839                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80);
3840                 break;
3841         default:
3842                 break;
3843         }
3844 }
3845
3846 static void rtl_pll_power_up(struct rtl8169_private *tp)
3847 {
3848         switch (tp->mac_version) {
3849         case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_33:
3850         case RTL_GIGA_MAC_VER_37:
3851         case RTL_GIGA_MAC_VER_39:
3852         case RTL_GIGA_MAC_VER_43:
3853                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0x80);
3854                 break;
3855         case RTL_GIGA_MAC_VER_44:
3856         case RTL_GIGA_MAC_VER_45:
3857         case RTL_GIGA_MAC_VER_46:
3858         case RTL_GIGA_MAC_VER_47:
3859         case RTL_GIGA_MAC_VER_48:
3860         case RTL_GIGA_MAC_VER_50:
3861         case RTL_GIGA_MAC_VER_51:
3862                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0);
3863                 break;
3864         case RTL_GIGA_MAC_VER_40:
3865         case RTL_GIGA_MAC_VER_41:
3866         case RTL_GIGA_MAC_VER_49:
3867                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0);
3868                 rtl_eri_set_bits(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000);
3869                 break;
3870         default:
3871                 break;
3872         }
3873
3874         phy_resume(tp->phydev);
3875         /* give MAC/PHY some time to resume */
3876         msleep(20);
3877 }
3878
3879 static void rtl_init_rxcfg(struct rtl8169_private *tp)
3880 {
3881         switch (tp->mac_version) {
3882         case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
3883         case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
3884                 RTL_W32(tp, RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
3885                 break;
3886         case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
3887         case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36:
3888         case RTL_GIGA_MAC_VER_38:
3889                 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
3890                 break;
3891         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
3892                 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF);
3893                 break;
3894         default:
3895                 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_DMA_BURST);
3896                 break;
3897         }
3898 }
3899
3900 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
3901 {
3902         tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0;
3903 }
3904
3905 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
3906 {
3907         RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
3908         RTL_W8(tp, Config4, RTL_R8(tp, Config4) | Jumbo_En1);
3909         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_512B);
3910 }
3911
3912 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
3913 {
3914         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
3915         RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~Jumbo_En1);
3916         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
3917 }
3918
3919 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
3920 {
3921         RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
3922 }
3923
3924 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
3925 {
3926         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
3927 }
3928
3929 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
3930 {
3931         RTL_W8(tp, MaxTxPacketSize, 0x3f);
3932         RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
3933         RTL_W8(tp, Config4, RTL_R8(tp, Config4) | 0x01);
3934         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_512B);
3935 }
3936
3937 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
3938 {
3939         RTL_W8(tp, MaxTxPacketSize, 0x0c);
3940         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
3941         RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~0x01);
3942         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
3943 }
3944
3945 static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp)
3946 {
3947         rtl_tx_performance_tweak(tp,
3948                 PCI_EXP_DEVCTL_READRQ_512B | PCI_EXP_DEVCTL_NOSNOOP_EN);
3949 }
3950
3951 static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp)
3952 {
3953         rtl_tx_performance_tweak(tp,
3954                 PCI_EXP_DEVCTL_READRQ_4096B | PCI_EXP_DEVCTL_NOSNOOP_EN);
3955 }
3956
3957 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
3958 {
3959         r8168b_0_hw_jumbo_enable(tp);
3960
3961         RTL_W8(tp, Config4, RTL_R8(tp, Config4) | (1 << 0));
3962 }
3963
3964 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
3965 {
3966         r8168b_0_hw_jumbo_disable(tp);
3967
3968         RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0));
3969 }
3970
3971 static void rtl_hw_jumbo_enable(struct rtl8169_private *tp)
3972 {
3973         rtl_unlock_config_regs(tp);
3974         switch (tp->mac_version) {
3975         case RTL_GIGA_MAC_VER_11:
3976                 r8168b_0_hw_jumbo_enable(tp);
3977                 break;
3978         case RTL_GIGA_MAC_VER_12:
3979         case RTL_GIGA_MAC_VER_17:
3980                 r8168b_1_hw_jumbo_enable(tp);
3981                 break;
3982         case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_26:
3983                 r8168c_hw_jumbo_enable(tp);
3984                 break;
3985         case RTL_GIGA_MAC_VER_27 ... RTL_GIGA_MAC_VER_28:
3986                 r8168dp_hw_jumbo_enable(tp);
3987                 break;
3988         case RTL_GIGA_MAC_VER_31 ... RTL_GIGA_MAC_VER_34:
3989                 r8168e_hw_jumbo_enable(tp);
3990                 break;
3991         default:
3992                 break;
3993         }
3994         rtl_lock_config_regs(tp);
3995 }
3996
3997 static void rtl_hw_jumbo_disable(struct rtl8169_private *tp)
3998 {
3999         rtl_unlock_config_regs(tp);
4000         switch (tp->mac_version) {
4001         case RTL_GIGA_MAC_VER_11:
4002                 r8168b_0_hw_jumbo_disable(tp);
4003                 break;
4004         case RTL_GIGA_MAC_VER_12:
4005         case RTL_GIGA_MAC_VER_17:
4006                 r8168b_1_hw_jumbo_disable(tp);
4007                 break;
4008         case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_26:
4009                 r8168c_hw_jumbo_disable(tp);
4010                 break;
4011         case RTL_GIGA_MAC_VER_27 ... RTL_GIGA_MAC_VER_28:
4012                 r8168dp_hw_jumbo_disable(tp);
4013                 break;
4014         case RTL_GIGA_MAC_VER_31 ... RTL_GIGA_MAC_VER_34:
4015                 r8168e_hw_jumbo_disable(tp);
4016                 break;
4017         default:
4018                 break;
4019         }
4020         rtl_lock_config_regs(tp);
4021 }
4022
4023 DECLARE_RTL_COND(rtl_chipcmd_cond)
4024 {
4025         return RTL_R8(tp, ChipCmd) & CmdReset;
4026 }
4027
4028 static void rtl_hw_reset(struct rtl8169_private *tp)
4029 {
4030         RTL_W8(tp, ChipCmd, CmdReset);
4031
4032         rtl_udelay_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100);
4033 }
4034
4035 static void rtl_request_firmware(struct rtl8169_private *tp)
4036 {
4037         struct rtl_fw *rtl_fw;
4038
4039         /* firmware loaded already or no firmware available */
4040         if (tp->rtl_fw || !tp->fw_name)
4041                 return;
4042
4043         rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
4044         if (!rtl_fw) {
4045                 netif_warn(tp, ifup, tp->dev, "Unable to load firmware, out of memory\n");
4046                 return;
4047         }
4048
4049         rtl_fw->phy_write = rtl_writephy;
4050         rtl_fw->phy_read = rtl_readphy;
4051         rtl_fw->mac_mcu_write = mac_mcu_write;
4052         rtl_fw->mac_mcu_read = mac_mcu_read;
4053         rtl_fw->fw_name = tp->fw_name;
4054         rtl_fw->dev = tp_to_dev(tp);
4055
4056         if (rtl_fw_request_firmware(rtl_fw))
4057                 kfree(rtl_fw);
4058         else
4059                 tp->rtl_fw = rtl_fw;
4060 }
4061
4062 static void rtl_rx_close(struct rtl8169_private *tp)
4063 {
4064         RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
4065 }
4066
4067 DECLARE_RTL_COND(rtl_npq_cond)
4068 {
4069         return RTL_R8(tp, TxPoll) & NPQ;
4070 }
4071
4072 DECLARE_RTL_COND(rtl_txcfg_empty_cond)
4073 {
4074         return RTL_R32(tp, TxConfig) & TXCFG_EMPTY;
4075 }
4076
4077 static void rtl8169_hw_reset(struct rtl8169_private *tp)
4078 {
4079         /* Disable interrupts */
4080         rtl8169_irq_mask_and_ack(tp);
4081
4082         rtl_rx_close(tp);
4083
4084         switch (tp->mac_version) {
4085         case RTL_GIGA_MAC_VER_27:
4086         case RTL_GIGA_MAC_VER_28:
4087         case RTL_GIGA_MAC_VER_31:
4088                 rtl_udelay_loop_wait_low(tp, &rtl_npq_cond, 20, 42*42);
4089                 break;
4090         case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
4091         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
4092                 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
4093                 rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);
4094                 break;
4095         default:
4096                 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
4097                 udelay(100);
4098                 break;
4099         }
4100
4101         rtl_hw_reset(tp);
4102 }
4103
4104 static void rtl_set_tx_config_registers(struct rtl8169_private *tp)
4105 {
4106         u32 val = TX_DMA_BURST << TxDMAShift |
4107                   InterFrameGap << TxInterFrameGapShift;
4108
4109         if (rtl_is_8168evl_up(tp))
4110                 val |= TXCFG_AUTO_FIFO;
4111
4112         RTL_W32(tp, TxConfig, val);
4113 }
4114
4115 static void rtl_set_rx_max_size(struct rtl8169_private *tp)
4116 {
4117         /* Low hurts. Let's disable the filtering. */
4118         RTL_W16(tp, RxMaxSize, R8169_RX_BUF_SIZE + 1);
4119 }
4120
4121 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp)
4122 {
4123         /*
4124          * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
4125          * register to be written before TxDescAddrLow to work.
4126          * Switching from MMIO to I/O access fixes the issue as well.
4127          */
4128         RTL_W32(tp, TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
4129         RTL_W32(tp, TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
4130         RTL_W32(tp, RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
4131         RTL_W32(tp, RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
4132 }
4133
4134 static void rtl8169_set_magic_reg(struct rtl8169_private *tp, unsigned mac_version)
4135 {
4136         u32 val;
4137
4138         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
4139                 val = 0x000fff00;
4140         else if (tp->mac_version == RTL_GIGA_MAC_VER_06)
4141                 val = 0x00ffff00;
4142         else
4143                 return;
4144
4145         if (RTL_R8(tp, Config2) & PCI_Clock_66MHz)
4146                 val |= 0xff;
4147
4148         RTL_W32(tp, 0x7c, val);
4149 }
4150
4151 static void rtl_set_rx_mode(struct net_device *dev)
4152 {
4153         u32 rx_mode = AcceptBroadcast | AcceptMyPhys | AcceptMulticast;
4154         /* Multicast hash filter */
4155         u32 mc_filter[2] = { 0xffffffff, 0xffffffff };
4156         struct rtl8169_private *tp = netdev_priv(dev);
4157         u32 tmp;
4158
4159         if (dev->flags & IFF_PROMISC) {
4160                 /* Unconditionally log net taps. */
4161                 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
4162                 rx_mode |= AcceptAllPhys;
4163         } else if (netdev_mc_count(dev) > MC_FILTER_LIMIT ||
4164                    dev->flags & IFF_ALLMULTI ||
4165                    tp->mac_version == RTL_GIGA_MAC_VER_35) {
4166                 /* accept all multicasts */
4167         } else if (netdev_mc_empty(dev)) {
4168                 rx_mode &= ~AcceptMulticast;
4169         } else {
4170                 struct netdev_hw_addr *ha;
4171
4172                 mc_filter[1] = mc_filter[0] = 0;
4173                 netdev_for_each_mc_addr(ha, dev) {
4174                         u32 bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
4175                         mc_filter[bit_nr >> 5] |= BIT(bit_nr & 31);
4176                 }
4177
4178                 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
4179                         tmp = mc_filter[0];
4180                         mc_filter[0] = swab32(mc_filter[1]);
4181                         mc_filter[1] = swab32(tmp);
4182                 }
4183         }
4184
4185         if (dev->features & NETIF_F_RXALL)
4186                 rx_mode |= (AcceptErr | AcceptRunt);
4187
4188         RTL_W32(tp, MAR0 + 4, mc_filter[1]);
4189         RTL_W32(tp, MAR0 + 0, mc_filter[0]);
4190
4191         tmp = RTL_R32(tp, RxConfig);
4192         RTL_W32(tp, RxConfig, (tmp & ~RX_CONFIG_ACCEPT_MASK) | rx_mode);
4193 }
4194
4195 DECLARE_RTL_COND(rtl_csiar_cond)
4196 {
4197         return RTL_R32(tp, CSIAR) & CSIAR_FLAG;
4198 }
4199
4200 static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)
4201 {
4202         u32 func = PCI_FUNC(tp->pci_dev->devfn);
4203
4204         RTL_W32(tp, CSIDR, value);
4205         RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
4206                 CSIAR_BYTE_ENABLE | func << 16);
4207
4208         rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
4209 }
4210
4211 static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)
4212 {
4213         u32 func = PCI_FUNC(tp->pci_dev->devfn);
4214
4215         RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) | func << 16 |
4216                 CSIAR_BYTE_ENABLE);
4217
4218         return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
4219                 RTL_R32(tp, CSIDR) : ~0;
4220 }
4221
4222 static void rtl_csi_access_enable(struct rtl8169_private *tp, u8 val)
4223 {
4224         struct pci_dev *pdev = tp->pci_dev;
4225         u32 csi;
4226
4227         /* According to Realtek the value at config space address 0x070f
4228          * controls the L0s/L1 entrance latency. We try standard ECAM access
4229          * first and if it fails fall back to CSI.
4230          */
4231         if (pdev->cfg_size > 0x070f &&
4232             pci_write_config_byte(pdev, 0x070f, val) == PCIBIOS_SUCCESSFUL)
4233                 return;
4234
4235         netdev_notice_once(tp->dev,
4236                 "No native access to PCI extended config space, falling back to CSI\n");
4237         csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff;
4238         rtl_csi_write(tp, 0x070c, csi | val << 24);
4239 }
4240
4241 static void rtl_set_def_aspm_entry_latency(struct rtl8169_private *tp)
4242 {
4243         rtl_csi_access_enable(tp, 0x27);
4244 }
4245
4246 struct ephy_info {
4247         unsigned int offset;
4248         u16 mask;
4249         u16 bits;
4250 };
4251
4252 static void __rtl_ephy_init(struct rtl8169_private *tp,
4253                             const struct ephy_info *e, int len)
4254 {
4255         u16 w;
4256
4257         while (len-- > 0) {
4258                 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits;
4259                 rtl_ephy_write(tp, e->offset, w);
4260                 e++;
4261         }
4262 }
4263
4264 #define rtl_ephy_init(tp, a) __rtl_ephy_init(tp, a, ARRAY_SIZE(a))
4265
4266 static void rtl_disable_clock_request(struct rtl8169_private *tp)
4267 {
4268         pcie_capability_clear_word(tp->pci_dev, PCI_EXP_LNKCTL,
4269                                    PCI_EXP_LNKCTL_CLKREQ_EN);
4270 }
4271
4272 static void rtl_enable_clock_request(struct rtl8169_private *tp)
4273 {
4274         pcie_capability_set_word(tp->pci_dev, PCI_EXP_LNKCTL,
4275                                  PCI_EXP_LNKCTL_CLKREQ_EN);
4276 }
4277
4278 static void rtl_pcie_state_l2l3_disable(struct rtl8169_private *tp)
4279 {
4280         /* work around an issue when PCI reset occurs during L2/L3 state */
4281         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Rdy_to_L23);
4282 }
4283
4284 static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable)
4285 {
4286         /* Don't enable ASPM in the chip if OS can't control ASPM */
4287         if (enable && tp->aspm_manageable) {
4288                 RTL_W8(tp, Config5, RTL_R8(tp, Config5) | ASPM_en);
4289                 RTL_W8(tp, Config2, RTL_R8(tp, Config2) | ClkReqEn);
4290         } else {
4291                 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
4292                 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
4293         }
4294
4295         udelay(10);
4296 }
4297
4298 static void rtl_set_fifo_size(struct rtl8169_private *tp, u16 rx_stat,
4299                               u16 tx_stat, u16 rx_dyn, u16 tx_dyn)
4300 {
4301         /* Usage of dynamic vs. static FIFO is controlled by bit
4302          * TXCFG_AUTO_FIFO. Exact meaning of FIFO values isn't known.
4303          */
4304         rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, (rx_stat << 16) | rx_dyn);
4305         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, (tx_stat << 16) | tx_dyn);
4306 }
4307
4308 static void rtl8168g_set_pause_thresholds(struct rtl8169_private *tp,
4309                                           u8 low, u8 high)
4310 {
4311         /* FIFO thresholds for pause flow control */
4312         rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, low);
4313         rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, high);
4314 }
4315
4316 static void rtl_hw_start_8168bb(struct rtl8169_private *tp)
4317 {
4318         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4319
4320         if (tp->dev->mtu <= ETH_DATA_LEN) {
4321                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B |
4322                                          PCI_EXP_DEVCTL_NOSNOOP_EN);
4323         }
4324 }
4325
4326 static void rtl_hw_start_8168bef(struct rtl8169_private *tp)
4327 {
4328         rtl_hw_start_8168bb(tp);
4329
4330         RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0));
4331 }
4332
4333 static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)
4334 {
4335         RTL_W8(tp, Config1, RTL_R8(tp, Config1) | Speed_down);
4336
4337         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4338
4339         if (tp->dev->mtu <= ETH_DATA_LEN)
4340                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4341
4342         rtl_disable_clock_request(tp);
4343 }
4344
4345 static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp)
4346 {
4347         static const struct ephy_info e_info_8168cp[] = {
4348                 { 0x01, 0,      0x0001 },
4349                 { 0x02, 0x0800, 0x1000 },
4350                 { 0x03, 0,      0x0042 },
4351                 { 0x06, 0x0080, 0x0000 },
4352                 { 0x07, 0,      0x2000 }
4353         };
4354
4355         rtl_set_def_aspm_entry_latency(tp);
4356
4357         rtl_ephy_init(tp, e_info_8168cp);
4358
4359         __rtl_hw_start_8168cp(tp);
4360 }
4361
4362 static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)
4363 {
4364         rtl_set_def_aspm_entry_latency(tp);
4365
4366         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4367
4368         if (tp->dev->mtu <= ETH_DATA_LEN)
4369                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4370 }
4371
4372 static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)
4373 {
4374         rtl_set_def_aspm_entry_latency(tp);
4375
4376         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4377
4378         /* Magic. */
4379         RTL_W8(tp, DBG_REG, 0x20);
4380
4381         if (tp->dev->mtu <= ETH_DATA_LEN)
4382                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4383 }
4384
4385 static void rtl_hw_start_8168c_1(struct rtl8169_private *tp)
4386 {
4387         static const struct ephy_info e_info_8168c_1[] = {
4388                 { 0x02, 0x0800, 0x1000 },
4389                 { 0x03, 0,      0x0002 },
4390                 { 0x06, 0x0080, 0x0000 }
4391         };
4392
4393         rtl_set_def_aspm_entry_latency(tp);
4394
4395         RTL_W8(tp, DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
4396
4397         rtl_ephy_init(tp, e_info_8168c_1);
4398
4399         __rtl_hw_start_8168cp(tp);
4400 }
4401
4402 static void rtl_hw_start_8168c_2(struct rtl8169_private *tp)
4403 {
4404         static const struct ephy_info e_info_8168c_2[] = {
4405                 { 0x01, 0,      0x0001 },
4406                 { 0x03, 0x0400, 0x0220 }
4407         };
4408
4409         rtl_set_def_aspm_entry_latency(tp);
4410
4411         rtl_ephy_init(tp, e_info_8168c_2);
4412
4413         __rtl_hw_start_8168cp(tp);
4414 }
4415
4416 static void rtl_hw_start_8168c_3(struct rtl8169_private *tp)
4417 {
4418         rtl_hw_start_8168c_2(tp);
4419 }
4420
4421 static void rtl_hw_start_8168c_4(struct rtl8169_private *tp)
4422 {
4423         rtl_set_def_aspm_entry_latency(tp);
4424
4425         __rtl_hw_start_8168cp(tp);
4426 }
4427
4428 static void rtl_hw_start_8168d(struct rtl8169_private *tp)
4429 {
4430         rtl_set_def_aspm_entry_latency(tp);
4431
4432         rtl_disable_clock_request(tp);
4433
4434         if (tp->dev->mtu <= ETH_DATA_LEN)
4435                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4436 }
4437
4438 static void rtl_hw_start_8168dp(struct rtl8169_private *tp)
4439 {
4440         rtl_set_def_aspm_entry_latency(tp);
4441
4442         if (tp->dev->mtu <= ETH_DATA_LEN)
4443                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4444
4445         rtl_disable_clock_request(tp);
4446 }
4447
4448 static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
4449 {
4450         static const struct ephy_info e_info_8168d_4[] = {
4451                 { 0x0b, 0x0000, 0x0048 },
4452                 { 0x19, 0x0020, 0x0050 },
4453                 { 0x0c, 0x0100, 0x0020 }
4454         };
4455
4456         rtl_set_def_aspm_entry_latency(tp);
4457
4458         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4459
4460         rtl_ephy_init(tp, e_info_8168d_4);
4461
4462         rtl_enable_clock_request(tp);
4463 }
4464
4465 static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)
4466 {
4467         static const struct ephy_info e_info_8168e_1[] = {
4468                 { 0x00, 0x0200, 0x0100 },
4469                 { 0x00, 0x0000, 0x0004 },
4470                 { 0x06, 0x0002, 0x0001 },
4471                 { 0x06, 0x0000, 0x0030 },
4472                 { 0x07, 0x0000, 0x2000 },
4473                 { 0x00, 0x0000, 0x0020 },
4474                 { 0x03, 0x5800, 0x2000 },
4475                 { 0x03, 0x0000, 0x0001 },
4476                 { 0x01, 0x0800, 0x1000 },
4477                 { 0x07, 0x0000, 0x4000 },
4478                 { 0x1e, 0x0000, 0x2000 },
4479                 { 0x19, 0xffff, 0xfe6c },
4480                 { 0x0a, 0x0000, 0x0040 }
4481         };
4482
4483         rtl_set_def_aspm_entry_latency(tp);
4484
4485         rtl_ephy_init(tp, e_info_8168e_1);
4486
4487         if (tp->dev->mtu <= ETH_DATA_LEN)
4488                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4489
4490         rtl_disable_clock_request(tp);
4491
4492         /* Reset tx FIFO pointer */
4493         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | TXPLA_RST);
4494         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~TXPLA_RST);
4495
4496         RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
4497 }
4498
4499 static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
4500 {
4501         static const struct ephy_info e_info_8168e_2[] = {
4502                 { 0x09, 0x0000, 0x0080 },
4503                 { 0x19, 0x0000, 0x0224 }
4504         };
4505
4506         rtl_set_def_aspm_entry_latency(tp);
4507
4508         rtl_ephy_init(tp, e_info_8168e_2);
4509
4510         if (tp->dev->mtu <= ETH_DATA_LEN)
4511                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4512
4513         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
4514         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
4515         rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06);
4516         rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050);
4517         rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060);
4518         rtl_eri_set_bits(tp, 0x1b0, ERIAR_MASK_0001, BIT(4));
4519         rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00);
4520
4521         rtl_disable_clock_request(tp);
4522
4523         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
4524
4525         rtl8168_config_eee_mac(tp);
4526
4527         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
4528         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
4529         RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
4530
4531         rtl_hw_aspm_clkreq_enable(tp, true);
4532 }
4533
4534 static void rtl_hw_start_8168f(struct rtl8169_private *tp)
4535 {
4536         rtl_set_def_aspm_entry_latency(tp);
4537
4538         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4539
4540         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
4541         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
4542         rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06);
4543         rtl_reset_packet_filter(tp);
4544         rtl_eri_set_bits(tp, 0x1b0, ERIAR_MASK_0001, BIT(4));
4545         rtl_eri_set_bits(tp, 0x1d0, ERIAR_MASK_0001, BIT(4));
4546         rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050);
4547         rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060);
4548
4549         rtl_disable_clock_request(tp);
4550
4551         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
4552         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
4553         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
4554         RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
4555
4556         rtl8168_config_eee_mac(tp);
4557 }
4558
4559 static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
4560 {
4561         static const struct ephy_info e_info_8168f_1[] = {
4562                 { 0x06, 0x00c0, 0x0020 },
4563                 { 0x08, 0x0001, 0x0002 },
4564                 { 0x09, 0x0000, 0x0080 },
4565                 { 0x19, 0x0000, 0x0224 }
4566         };
4567
4568         rtl_hw_start_8168f(tp);
4569
4570         rtl_ephy_init(tp, e_info_8168f_1);
4571
4572         rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00);
4573 }
4574
4575 static void rtl_hw_start_8411(struct rtl8169_private *tp)
4576 {
4577         static const struct ephy_info e_info_8168f_1[] = {
4578                 { 0x06, 0x00c0, 0x0020 },
4579                 { 0x0f, 0xffff, 0x5200 },
4580                 { 0x1e, 0x0000, 0x4000 },
4581                 { 0x19, 0x0000, 0x0224 }
4582         };
4583
4584         rtl_hw_start_8168f(tp);
4585         rtl_pcie_state_l2l3_disable(tp);
4586
4587         rtl_ephy_init(tp, e_info_8168f_1);
4588
4589         rtl_eri_set_bits(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00);
4590 }
4591
4592 static void rtl_hw_start_8168g(struct rtl8169_private *tp)
4593 {
4594         rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
4595         rtl8168g_set_pause_thresholds(tp, 0x38, 0x48);
4596
4597         rtl_set_def_aspm_entry_latency(tp);
4598
4599         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4600
4601         rtl_reset_packet_filter(tp);
4602         rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f);
4603
4604         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
4605
4606         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
4607         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
4608
4609         rtl8168_config_eee_mac(tp);
4610
4611         rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06);
4612         rtl_eri_clear_bits(tp, 0x1b0, ERIAR_MASK_0011, BIT(12));
4613
4614         rtl_pcie_state_l2l3_disable(tp);
4615 }
4616
4617 static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
4618 {
4619         static const struct ephy_info e_info_8168g_1[] = {
4620                 { 0x00, 0x0000, 0x0008 },
4621                 { 0x0c, 0x37d0, 0x0820 },
4622                 { 0x1e, 0x0000, 0x0001 },
4623                 { 0x19, 0x8000, 0x0000 }
4624         };
4625
4626         rtl_hw_start_8168g(tp);
4627
4628         /* disable aspm and clock request before access ephy */
4629         rtl_hw_aspm_clkreq_enable(tp, false);
4630         rtl_ephy_init(tp, e_info_8168g_1);
4631         rtl_hw_aspm_clkreq_enable(tp, true);
4632 }
4633
4634 static void rtl_hw_start_8168g_2(struct rtl8169_private *tp)
4635 {
4636         static const struct ephy_info e_info_8168g_2[] = {
4637                 { 0x00, 0x0000, 0x0008 },
4638                 { 0x0c, 0x3df0, 0x0200 },
4639                 { 0x19, 0xffff, 0xfc00 },
4640                 { 0x1e, 0xffff, 0x20eb }
4641         };
4642
4643         rtl_hw_start_8168g(tp);
4644
4645         /* disable aspm and clock request before access ephy */
4646         RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
4647         RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
4648         rtl_ephy_init(tp, e_info_8168g_2);
4649 }
4650
4651 static void rtl_hw_start_8411_2(struct rtl8169_private *tp)
4652 {
4653         static const struct ephy_info e_info_8411_2[] = {
4654                 { 0x00, 0x0000, 0x0008 },
4655                 { 0x0c, 0x3df0, 0x0200 },
4656                 { 0x0f, 0xffff, 0x5200 },
4657                 { 0x19, 0x0020, 0x0000 },
4658                 { 0x1e, 0x0000, 0x2000 }
4659         };
4660
4661         rtl_hw_start_8168g(tp);
4662
4663         /* disable aspm and clock request before access ephy */
4664         rtl_hw_aspm_clkreq_enable(tp, false);
4665         rtl_ephy_init(tp, e_info_8411_2);
4666
4667         /* The following Realtek-provided magic fixes an issue with the RX unit
4668          * getting confused after the PHY having been powered-down.
4669          */
4670         r8168_mac_ocp_write(tp, 0xFC28, 0x0000);
4671         r8168_mac_ocp_write(tp, 0xFC2A, 0x0000);
4672         r8168_mac_ocp_write(tp, 0xFC2C, 0x0000);
4673         r8168_mac_ocp_write(tp, 0xFC2E, 0x0000);
4674         r8168_mac_ocp_write(tp, 0xFC30, 0x0000);
4675         r8168_mac_ocp_write(tp, 0xFC32, 0x0000);
4676         r8168_mac_ocp_write(tp, 0xFC34, 0x0000);
4677         r8168_mac_ocp_write(tp, 0xFC36, 0x0000);
4678         mdelay(3);
4679         r8168_mac_ocp_write(tp, 0xFC26, 0x0000);
4680
4681         r8168_mac_ocp_write(tp, 0xF800, 0xE008);
4682         r8168_mac_ocp_write(tp, 0xF802, 0xE00A);
4683         r8168_mac_ocp_write(tp, 0xF804, 0xE00C);
4684         r8168_mac_ocp_write(tp, 0xF806, 0xE00E);
4685         r8168_mac_ocp_write(tp, 0xF808, 0xE027);
4686         r8168_mac_ocp_write(tp, 0xF80A, 0xE04F);
4687         r8168_mac_ocp_write(tp, 0xF80C, 0xE05E);
4688         r8168_mac_ocp_write(tp, 0xF80E, 0xE065);
4689         r8168_mac_ocp_write(tp, 0xF810, 0xC602);
4690         r8168_mac_ocp_write(tp, 0xF812, 0xBE00);
4691         r8168_mac_ocp_write(tp, 0xF814, 0x0000);
4692         r8168_mac_ocp_write(tp, 0xF816, 0xC502);
4693         r8168_mac_ocp_write(tp, 0xF818, 0xBD00);
4694         r8168_mac_ocp_write(tp, 0xF81A, 0x074C);
4695         r8168_mac_ocp_write(tp, 0xF81C, 0xC302);
4696         r8168_mac_ocp_write(tp, 0xF81E, 0xBB00);
4697         r8168_mac_ocp_write(tp, 0xF820, 0x080A);
4698         r8168_mac_ocp_write(tp, 0xF822, 0x6420);
4699         r8168_mac_ocp_write(tp, 0xF824, 0x48C2);
4700         r8168_mac_ocp_write(tp, 0xF826, 0x8C20);
4701         r8168_mac_ocp_write(tp, 0xF828, 0xC516);
4702         r8168_mac_ocp_write(tp, 0xF82A, 0x64A4);
4703         r8168_mac_ocp_write(tp, 0xF82C, 0x49C0);
4704         r8168_mac_ocp_write(tp, 0xF82E, 0xF009);
4705         r8168_mac_ocp_write(tp, 0xF830, 0x74A2);
4706         r8168_mac_ocp_write(tp, 0xF832, 0x8CA5);
4707         r8168_mac_ocp_write(tp, 0xF834, 0x74A0);
4708         r8168_mac_ocp_write(tp, 0xF836, 0xC50E);
4709         r8168_mac_ocp_write(tp, 0xF838, 0x9CA2);
4710         r8168_mac_ocp_write(tp, 0xF83A, 0x1C11);
4711         r8168_mac_ocp_write(tp, 0xF83C, 0x9CA0);
4712         r8168_mac_ocp_write(tp, 0xF83E, 0xE006);
4713         r8168_mac_ocp_write(tp, 0xF840, 0x74F8);
4714         r8168_mac_ocp_write(tp, 0xF842, 0x48C4);
4715         r8168_mac_ocp_write(tp, 0xF844, 0x8CF8);
4716         r8168_mac_ocp_write(tp, 0xF846, 0xC404);
4717         r8168_mac_ocp_write(tp, 0xF848, 0xBC00);
4718         r8168_mac_ocp_write(tp, 0xF84A, 0xC403);
4719         r8168_mac_ocp_write(tp, 0xF84C, 0xBC00);
4720         r8168_mac_ocp_write(tp, 0xF84E, 0x0BF2);
4721         r8168_mac_ocp_write(tp, 0xF850, 0x0C0A);
4722         r8168_mac_ocp_write(tp, 0xF852, 0xE434);
4723         r8168_mac_ocp_write(tp, 0xF854, 0xD3C0);
4724         r8168_mac_ocp_write(tp, 0xF856, 0x49D9);
4725         r8168_mac_ocp_write(tp, 0xF858, 0xF01F);
4726         r8168_mac_ocp_write(tp, 0xF85A, 0xC526);
4727         r8168_mac_ocp_write(tp, 0xF85C, 0x64A5);
4728         r8168_mac_ocp_write(tp, 0xF85E, 0x1400);
4729         r8168_mac_ocp_write(tp, 0xF860, 0xF007);
4730         r8168_mac_ocp_write(tp, 0xF862, 0x0C01);
4731         r8168_mac_ocp_write(tp, 0xF864, 0x8CA5);
4732         r8168_mac_ocp_write(tp, 0xF866, 0x1C15);
4733         r8168_mac_ocp_write(tp, 0xF868, 0xC51B);
4734         r8168_mac_ocp_write(tp, 0xF86A, 0x9CA0);
4735         r8168_mac_ocp_write(tp, 0xF86C, 0xE013);
4736         r8168_mac_ocp_write(tp, 0xF86E, 0xC519);
4737         r8168_mac_ocp_write(tp, 0xF870, 0x74A0);
4738         r8168_mac_ocp_write(tp, 0xF872, 0x48C4);
4739         r8168_mac_ocp_write(tp, 0xF874, 0x8CA0);
4740         r8168_mac_ocp_write(tp, 0xF876, 0xC516);
4741         r8168_mac_ocp_write(tp, 0xF878, 0x74A4);
4742         r8168_mac_ocp_write(tp, 0xF87A, 0x48C8);
4743         r8168_mac_ocp_write(tp, 0xF87C, 0x48CA);
4744         r8168_mac_ocp_write(tp, 0xF87E, 0x9CA4);
4745         r8168_mac_ocp_write(tp, 0xF880, 0xC512);
4746         r8168_mac_ocp_write(tp, 0xF882, 0x1B00);
4747         r8168_mac_ocp_write(tp, 0xF884, 0x9BA0);
4748         r8168_mac_ocp_write(tp, 0xF886, 0x1B1C);
4749         r8168_mac_ocp_write(tp, 0xF888, 0x483F);
4750         r8168_mac_ocp_write(tp, 0xF88A, 0x9BA2);
4751         r8168_mac_ocp_write(tp, 0xF88C, 0x1B04);
4752         r8168_mac_ocp_write(tp, 0xF88E, 0xC508);
4753         r8168_mac_ocp_write(tp, 0xF890, 0x9BA0);
4754         r8168_mac_ocp_write(tp, 0xF892, 0xC505);
4755         r8168_mac_ocp_write(tp, 0xF894, 0xBD00);
4756         r8168_mac_ocp_write(tp, 0xF896, 0xC502);
4757         r8168_mac_ocp_write(tp, 0xF898, 0xBD00);
4758         r8168_mac_ocp_write(tp, 0xF89A, 0x0300);
4759         r8168_mac_ocp_write(tp, 0xF89C, 0x051E);
4760         r8168_mac_ocp_write(tp, 0xF89E, 0xE434);
4761         r8168_mac_ocp_write(tp, 0xF8A0, 0xE018);
4762         r8168_mac_ocp_write(tp, 0xF8A2, 0xE092);
4763         r8168_mac_ocp_write(tp, 0xF8A4, 0xDE20);
4764         r8168_mac_ocp_write(tp, 0xF8A6, 0xD3C0);
4765         r8168_mac_ocp_write(tp, 0xF8A8, 0xC50F);
4766         r8168_mac_ocp_write(tp, 0xF8AA, 0x76A4);
4767         r8168_mac_ocp_write(tp, 0xF8AC, 0x49E3);
4768         r8168_mac_ocp_write(tp, 0xF8AE, 0xF007);
4769         r8168_mac_ocp_write(tp, 0xF8B0, 0x49C0);
4770         r8168_mac_ocp_write(tp, 0xF8B2, 0xF103);
4771         r8168_mac_ocp_write(tp, 0xF8B4, 0xC607);
4772         r8168_mac_ocp_write(tp, 0xF8B6, 0xBE00);
4773         r8168_mac_ocp_write(tp, 0xF8B8, 0xC606);
4774         r8168_mac_ocp_write(tp, 0xF8BA, 0xBE00);
4775         r8168_mac_ocp_write(tp, 0xF8BC, 0xC602);
4776         r8168_mac_ocp_write(tp, 0xF8BE, 0xBE00);
4777         r8168_mac_ocp_write(tp, 0xF8C0, 0x0C4C);
4778         r8168_mac_ocp_write(tp, 0xF8C2, 0x0C28);
4779         r8168_mac_ocp_write(tp, 0xF8C4, 0x0C2C);
4780         r8168_mac_ocp_write(tp, 0xF8C6, 0xDC00);
4781         r8168_mac_ocp_write(tp, 0xF8C8, 0xC707);
4782         r8168_mac_ocp_write(tp, 0xF8CA, 0x1D00);
4783         r8168_mac_ocp_write(tp, 0xF8CC, 0x8DE2);
4784         r8168_mac_ocp_write(tp, 0xF8CE, 0x48C1);
4785         r8168_mac_ocp_write(tp, 0xF8D0, 0xC502);
4786         r8168_mac_ocp_write(tp, 0xF8D2, 0xBD00);
4787         r8168_mac_ocp_write(tp, 0xF8D4, 0x00AA);
4788         r8168_mac_ocp_write(tp, 0xF8D6, 0xE0C0);
4789         r8168_mac_ocp_write(tp, 0xF8D8, 0xC502);
4790         r8168_mac_ocp_write(tp, 0xF8DA, 0xBD00);
4791         r8168_mac_ocp_write(tp, 0xF8DC, 0x0132);
4792
4793         r8168_mac_ocp_write(tp, 0xFC26, 0x8000);
4794
4795         r8168_mac_ocp_write(tp, 0xFC2A, 0x0743);
4796         r8168_mac_ocp_write(tp, 0xFC2C, 0x0801);
4797         r8168_mac_ocp_write(tp, 0xFC2E, 0x0BE9);
4798         r8168_mac_ocp_write(tp, 0xFC30, 0x02FD);
4799         r8168_mac_ocp_write(tp, 0xFC32, 0x0C25);
4800         r8168_mac_ocp_write(tp, 0xFC34, 0x00A9);
4801         r8168_mac_ocp_write(tp, 0xFC36, 0x012D);
4802
4803         rtl_hw_aspm_clkreq_enable(tp, true);
4804 }
4805
4806 static void rtl_hw_start_8168h_1(struct rtl8169_private *tp)
4807 {
4808         int rg_saw_cnt;
4809         u32 data;
4810         static const struct ephy_info e_info_8168h_1[] = {
4811                 { 0x1e, 0x0800, 0x0001 },
4812                 { 0x1d, 0x0000, 0x0800 },
4813                 { 0x05, 0xffff, 0x2089 },
4814                 { 0x06, 0xffff, 0x5881 },
4815                 { 0x04, 0xffff, 0x154a },
4816                 { 0x01, 0xffff, 0x068b }
4817         };
4818
4819         /* disable aspm and clock request before access ephy */
4820         rtl_hw_aspm_clkreq_enable(tp, false);
4821         rtl_ephy_init(tp, e_info_8168h_1);
4822
4823         rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
4824         rtl8168g_set_pause_thresholds(tp, 0x38, 0x48);
4825
4826         rtl_set_def_aspm_entry_latency(tp);
4827
4828         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4829
4830         rtl_reset_packet_filter(tp);
4831
4832         rtl_eri_set_bits(tp, 0xdc, ERIAR_MASK_1111, BIT(4));
4833
4834         rtl_eri_set_bits(tp, 0xd4, ERIAR_MASK_1111, 0x1f00);
4835
4836         rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);
4837
4838         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
4839
4840         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
4841         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
4842
4843         rtl8168_config_eee_mac(tp);
4844
4845         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
4846         RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
4847
4848         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
4849
4850         rtl_eri_clear_bits(tp, 0x1b0, ERIAR_MASK_0011, BIT(12));
4851
4852         rtl_pcie_state_l2l3_disable(tp);
4853
4854         rtl_writephy(tp, 0x1f, 0x0c42);
4855         rg_saw_cnt = (rtl_readphy(tp, 0x13) & 0x3fff);
4856         rtl_writephy(tp, 0x1f, 0x0000);
4857         if (rg_saw_cnt > 0) {
4858                 u16 sw_cnt_1ms_ini;
4859
4860                 sw_cnt_1ms_ini = 16000000/rg_saw_cnt;
4861                 sw_cnt_1ms_ini &= 0x0fff;
4862                 data = r8168_mac_ocp_read(tp, 0xd412);
4863                 data &= ~0x0fff;
4864                 data |= sw_cnt_1ms_ini;
4865                 r8168_mac_ocp_write(tp, 0xd412, data);
4866         }
4867
4868         data = r8168_mac_ocp_read(tp, 0xe056);
4869         data &= ~0xf0;
4870         data |= 0x70;
4871         r8168_mac_ocp_write(tp, 0xe056, data);
4872
4873         data = r8168_mac_ocp_read(tp, 0xe052);
4874         data &= ~0x6000;
4875         data |= 0x8008;
4876         r8168_mac_ocp_write(tp, 0xe052, data);
4877
4878         data = r8168_mac_ocp_read(tp, 0xe0d6);
4879         data &= ~0x01ff;
4880         data |= 0x017f;
4881         r8168_mac_ocp_write(tp, 0xe0d6, data);
4882
4883         data = r8168_mac_ocp_read(tp, 0xd420);
4884         data &= ~0x0fff;
4885         data |= 0x047f;
4886         r8168_mac_ocp_write(tp, 0xd420, data);
4887
4888         r8168_mac_ocp_write(tp, 0xe63e, 0x0001);
4889         r8168_mac_ocp_write(tp, 0xe63e, 0x0000);
4890         r8168_mac_ocp_write(tp, 0xc094, 0x0000);
4891         r8168_mac_ocp_write(tp, 0xc09e, 0x0000);
4892
4893         rtl_hw_aspm_clkreq_enable(tp, true);
4894 }
4895
4896 static void rtl_hw_start_8168ep(struct rtl8169_private *tp)
4897 {
4898         rtl8168ep_stop_cmac(tp);
4899
4900         rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
4901         rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f);
4902
4903         rtl_set_def_aspm_entry_latency(tp);
4904
4905         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4906
4907         rtl_reset_packet_filter(tp);
4908
4909         rtl_eri_set_bits(tp, 0xd4, ERIAR_MASK_1111, 0x1f80);
4910
4911         rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);
4912
4913         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
4914
4915         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
4916         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
4917
4918         rtl8168_config_eee_mac(tp);
4919
4920         rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06);
4921
4922         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
4923
4924         rtl_pcie_state_l2l3_disable(tp);
4925 }
4926
4927 static void rtl_hw_start_8168ep_1(struct rtl8169_private *tp)
4928 {
4929         static const struct ephy_info e_info_8168ep_1[] = {
4930                 { 0x00, 0xffff, 0x10ab },
4931                 { 0x06, 0xffff, 0xf030 },
4932                 { 0x08, 0xffff, 0x2006 },
4933                 { 0x0d, 0xffff, 0x1666 },
4934                 { 0x0c, 0x3ff0, 0x0000 }
4935         };
4936
4937         /* disable aspm and clock request before access ephy */
4938         rtl_hw_aspm_clkreq_enable(tp, false);
4939         rtl_ephy_init(tp, e_info_8168ep_1);
4940
4941         rtl_hw_start_8168ep(tp);
4942
4943         rtl_hw_aspm_clkreq_enable(tp, true);
4944 }
4945
4946 static void rtl_hw_start_8168ep_2(struct rtl8169_private *tp)
4947 {
4948         static const struct ephy_info e_info_8168ep_2[] = {
4949                 { 0x00, 0xffff, 0x10a3 },
4950                 { 0x19, 0xffff, 0xfc00 },
4951                 { 0x1e, 0xffff, 0x20ea }
4952         };
4953
4954         /* disable aspm and clock request before access ephy */
4955         rtl_hw_aspm_clkreq_enable(tp, false);
4956         rtl_ephy_init(tp, e_info_8168ep_2);
4957
4958         rtl_hw_start_8168ep(tp);
4959
4960         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
4961         RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
4962
4963         rtl_hw_aspm_clkreq_enable(tp, true);
4964 }
4965
4966 static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp)
4967 {
4968         u32 data;
4969         static const struct ephy_info e_info_8168ep_3[] = {
4970                 { 0x00, 0xffff, 0x10a3 },
4971                 { 0x19, 0xffff, 0x7c00 },
4972                 { 0x1e, 0xffff, 0x20eb },
4973                 { 0x0d, 0xffff, 0x1666 }
4974         };
4975
4976         /* disable aspm and clock request before access ephy */
4977         rtl_hw_aspm_clkreq_enable(tp, false);
4978         rtl_ephy_init(tp, e_info_8168ep_3);
4979
4980         rtl_hw_start_8168ep(tp);
4981
4982         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
4983         RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
4984
4985         data = r8168_mac_ocp_read(tp, 0xd3e2);
4986         data &= 0xf000;
4987         data |= 0x0271;
4988         r8168_mac_ocp_write(tp, 0xd3e2, data);
4989
4990         data = r8168_mac_ocp_read(tp, 0xd3e4);
4991         data &= 0xff00;
4992         r8168_mac_ocp_write(tp, 0xd3e4, data);
4993
4994         data = r8168_mac_ocp_read(tp, 0xe860);
4995         data |= 0x0080;
4996         r8168_mac_ocp_write(tp, 0xe860, data);
4997
4998         rtl_hw_aspm_clkreq_enable(tp, true);
4999 }
5000
5001 static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)
5002 {
5003         static const struct ephy_info e_info_8102e_1[] = {
5004                 { 0x01, 0, 0x6e65 },
5005                 { 0x02, 0, 0x091f },
5006                 { 0x03, 0, 0xc2f9 },
5007                 { 0x06, 0, 0xafb5 },
5008                 { 0x07, 0, 0x0e00 },
5009                 { 0x19, 0, 0xec80 },
5010                 { 0x01, 0, 0x2e65 },
5011                 { 0x01, 0, 0x6e65 }
5012         };
5013         u8 cfg1;
5014
5015         rtl_set_def_aspm_entry_latency(tp);
5016
5017         RTL_W8(tp, DBG_REG, FIX_NAK_1);
5018
5019         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5020
5021         RTL_W8(tp, Config1,
5022                LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
5023         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
5024
5025         cfg1 = RTL_R8(tp, Config1);
5026         if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
5027                 RTL_W8(tp, Config1, cfg1 & ~LEDS0);
5028
5029         rtl_ephy_init(tp, e_info_8102e_1);
5030 }
5031
5032 static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)
5033 {
5034         rtl_set_def_aspm_entry_latency(tp);
5035
5036         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5037
5038         RTL_W8(tp, Config1, MEMMAP | IOMAP | VPD | PMEnable);
5039         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
5040 }
5041
5042 static void rtl_hw_start_8102e_3(struct rtl8169_private *tp)
5043 {
5044         rtl_hw_start_8102e_2(tp);
5045
5046         rtl_ephy_write(tp, 0x03, 0xc2f9);
5047 }
5048
5049 static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)
5050 {
5051         static const struct ephy_info e_info_8105e_1[] = {
5052                 { 0x07, 0, 0x4000 },
5053                 { 0x19, 0, 0x0200 },
5054                 { 0x19, 0, 0x0020 },
5055                 { 0x1e, 0, 0x2000 },
5056                 { 0x03, 0, 0x0001 },
5057                 { 0x19, 0, 0x0100 },
5058                 { 0x19, 0, 0x0004 },
5059                 { 0x0a, 0, 0x0020 }
5060         };
5061
5062         /* Force LAN exit from ASPM if Rx/Tx are not idle */
5063         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
5064
5065         /* Disable Early Tally Counter */
5066         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) & ~0x010000);
5067
5068         RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
5069         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
5070
5071         rtl_ephy_init(tp, e_info_8105e_1);
5072
5073         rtl_pcie_state_l2l3_disable(tp);
5074 }
5075
5076 static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)
5077 {
5078         rtl_hw_start_8105e_1(tp);
5079         rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000);
5080 }
5081
5082 static void rtl_hw_start_8402(struct rtl8169_private *tp)
5083 {
5084         static const struct ephy_info e_info_8402[] = {
5085                 { 0x19, 0xffff, 0xff64 },
5086                 { 0x1e, 0, 0x4000 }
5087         };
5088
5089         rtl_set_def_aspm_entry_latency(tp);
5090
5091         /* Force LAN exit from ASPM if Rx/Tx are not idle */
5092         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
5093
5094         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
5095
5096         rtl_ephy_init(tp, e_info_8402);
5097
5098         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5099
5100         rtl_set_fifo_size(tp, 0x00, 0x00, 0x02, 0x06);
5101         rtl_reset_packet_filter(tp);
5102         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
5103         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
5104         rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0e00, 0xff00);
5105
5106         rtl_pcie_state_l2l3_disable(tp);
5107 }
5108
5109 static void rtl_hw_start_8106(struct rtl8169_private *tp)
5110 {
5111         rtl_hw_aspm_clkreq_enable(tp, false);
5112
5113         /* Force LAN exit from ASPM if Rx/Tx are not idle */
5114         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
5115
5116         RTL_W32(tp, MISC, (RTL_R32(tp, MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);
5117         RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
5118         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5119
5120         rtl_pcie_state_l2l3_disable(tp);
5121         rtl_hw_aspm_clkreq_enable(tp, true);
5122 }
5123
5124 static void rtl_hw_config(struct rtl8169_private *tp)
5125 {
5126         static const rtl_generic_fct hw_configs[] = {
5127                 [RTL_GIGA_MAC_VER_07] = rtl_hw_start_8102e_1,
5128                 [RTL_GIGA_MAC_VER_08] = rtl_hw_start_8102e_3,
5129                 [RTL_GIGA_MAC_VER_09] = rtl_hw_start_8102e_2,
5130                 [RTL_GIGA_MAC_VER_10] = NULL,
5131                 [RTL_GIGA_MAC_VER_11] = rtl_hw_start_8168bb,
5132                 [RTL_GIGA_MAC_VER_12] = rtl_hw_start_8168bef,
5133                 [RTL_GIGA_MAC_VER_13] = NULL,
5134                 [RTL_GIGA_MAC_VER_14] = NULL,
5135                 [RTL_GIGA_MAC_VER_15] = NULL,
5136                 [RTL_GIGA_MAC_VER_16] = NULL,
5137                 [RTL_GIGA_MAC_VER_17] = rtl_hw_start_8168bef,
5138                 [RTL_GIGA_MAC_VER_18] = rtl_hw_start_8168cp_1,
5139                 [RTL_GIGA_MAC_VER_19] = rtl_hw_start_8168c_1,
5140                 [RTL_GIGA_MAC_VER_20] = rtl_hw_start_8168c_2,
5141                 [RTL_GIGA_MAC_VER_21] = rtl_hw_start_8168c_3,
5142                 [RTL_GIGA_MAC_VER_22] = rtl_hw_start_8168c_4,
5143                 [RTL_GIGA_MAC_VER_23] = rtl_hw_start_8168cp_2,
5144                 [RTL_GIGA_MAC_VER_24] = rtl_hw_start_8168cp_3,
5145                 [RTL_GIGA_MAC_VER_25] = rtl_hw_start_8168d,
5146                 [RTL_GIGA_MAC_VER_26] = rtl_hw_start_8168d,
5147                 [RTL_GIGA_MAC_VER_27] = rtl_hw_start_8168d,
5148                 [RTL_GIGA_MAC_VER_28] = rtl_hw_start_8168d_4,
5149                 [RTL_GIGA_MAC_VER_29] = rtl_hw_start_8105e_1,
5150                 [RTL_GIGA_MAC_VER_30] = rtl_hw_start_8105e_2,
5151                 [RTL_GIGA_MAC_VER_31] = rtl_hw_start_8168dp,
5152                 [RTL_GIGA_MAC_VER_32] = rtl_hw_start_8168e_1,
5153                 [RTL_GIGA_MAC_VER_33] = rtl_hw_start_8168e_1,
5154                 [RTL_GIGA_MAC_VER_34] = rtl_hw_start_8168e_2,
5155                 [RTL_GIGA_MAC_VER_35] = rtl_hw_start_8168f_1,
5156                 [RTL_GIGA_MAC_VER_36] = rtl_hw_start_8168f_1,
5157                 [RTL_GIGA_MAC_VER_37] = rtl_hw_start_8402,
5158                 [RTL_GIGA_MAC_VER_38] = rtl_hw_start_8411,
5159                 [RTL_GIGA_MAC_VER_39] = rtl_hw_start_8106,
5160                 [RTL_GIGA_MAC_VER_40] = rtl_hw_start_8168g_1,
5161                 [RTL_GIGA_MAC_VER_41] = rtl_hw_start_8168g_1,
5162                 [RTL_GIGA_MAC_VER_42] = rtl_hw_start_8168g_2,
5163                 [RTL_GIGA_MAC_VER_43] = rtl_hw_start_8168g_2,
5164                 [RTL_GIGA_MAC_VER_44] = rtl_hw_start_8411_2,
5165                 [RTL_GIGA_MAC_VER_45] = rtl_hw_start_8168h_1,
5166                 [RTL_GIGA_MAC_VER_46] = rtl_hw_start_8168h_1,
5167                 [RTL_GIGA_MAC_VER_47] = rtl_hw_start_8168h_1,
5168                 [RTL_GIGA_MAC_VER_48] = rtl_hw_start_8168h_1,
5169                 [RTL_GIGA_MAC_VER_49] = rtl_hw_start_8168ep_1,
5170                 [RTL_GIGA_MAC_VER_50] = rtl_hw_start_8168ep_2,
5171                 [RTL_GIGA_MAC_VER_51] = rtl_hw_start_8168ep_3,
5172         };
5173
5174         if (hw_configs[tp->mac_version])
5175                 hw_configs[tp->mac_version](tp);
5176 }
5177
5178 static void rtl_hw_start_8168(struct rtl8169_private *tp)
5179 {
5180         if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
5181             tp->mac_version == RTL_GIGA_MAC_VER_16)
5182                 pcie_capability_set_word(tp->pci_dev, PCI_EXP_DEVCTL,
5183                                          PCI_EXP_DEVCTL_NOSNOOP_EN);
5184
5185         if (rtl_is_8168evl_up(tp))
5186                 RTL_W8(tp, MaxTxPacketSize, EarlySize);
5187         else
5188                 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
5189
5190         rtl_hw_config(tp);
5191 }
5192
5193 static void rtl_hw_start_8169(struct rtl8169_private *tp)
5194 {
5195         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
5196                 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
5197
5198         RTL_W8(tp, EarlyTxThres, NoEarlyTx);
5199
5200         tp->cp_cmd |= PCIMulRW;
5201
5202         if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
5203             tp->mac_version == RTL_GIGA_MAC_VER_03) {
5204                 netif_dbg(tp, drv, tp->dev,
5205                           "Set MAC Reg C+CR Offset 0xe0. Bit 3 and Bit 14 MUST be 1\n");
5206                 tp->cp_cmd |= (1 << 14);
5207         }
5208
5209         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
5210
5211         rtl8169_set_magic_reg(tp, tp->mac_version);
5212
5213         RTL_W32(tp, RxMissed, 0);
5214 }
5215
5216 static void rtl_hw_start(struct  rtl8169_private *tp)
5217 {
5218         rtl_unlock_config_regs(tp);
5219
5220         tp->cp_cmd &= CPCMD_MASK;
5221         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
5222
5223         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
5224                 rtl_hw_start_8169(tp);
5225         else
5226                 rtl_hw_start_8168(tp);
5227
5228         rtl_set_rx_max_size(tp);
5229         rtl_set_rx_tx_desc_registers(tp);
5230         rtl_lock_config_regs(tp);
5231
5232         /* disable interrupt coalescing */
5233         RTL_W16(tp, IntrMitigate, 0x0000);
5234         /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
5235         RTL_R8(tp, IntrMask);
5236         RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb);
5237         rtl_init_rxcfg(tp);
5238         rtl_set_tx_config_registers(tp);
5239
5240         rtl_set_rx_mode(tp->dev);
5241         /* no early-rx interrupts */
5242         RTL_W16(tp, MultiIntr, RTL_R16(tp, MultiIntr) & 0xf000);
5243         rtl_irq_enable(tp);
5244 }
5245
5246 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
5247 {
5248         struct rtl8169_private *tp = netdev_priv(dev);
5249
5250         if (new_mtu > ETH_DATA_LEN)
5251                 rtl_hw_jumbo_enable(tp);
5252         else
5253                 rtl_hw_jumbo_disable(tp);
5254
5255         dev->mtu = new_mtu;
5256         netdev_update_features(dev);
5257
5258         return 0;
5259 }
5260
5261 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
5262 {
5263         desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
5264         desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
5265 }
5266
5267 static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
5268                                      void **data_buff, struct RxDesc *desc)
5269 {
5270         dma_unmap_single(tp_to_dev(tp), le64_to_cpu(desc->addr),
5271                          R8169_RX_BUF_SIZE, DMA_FROM_DEVICE);
5272
5273         kfree(*data_buff);
5274         *data_buff = NULL;
5275         rtl8169_make_unusable_by_asic(desc);
5276 }
5277
5278 static inline void rtl8169_mark_to_asic(struct RxDesc *desc)
5279 {
5280         u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
5281
5282         /* Force memory writes to complete before releasing descriptor */
5283         dma_wmb();
5284
5285         desc->opts1 = cpu_to_le32(DescOwn | eor | R8169_RX_BUF_SIZE);
5286 }
5287
5288 static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
5289                                              struct RxDesc *desc)
5290 {
5291         void *data;
5292         dma_addr_t mapping;
5293         struct device *d = tp_to_dev(tp);
5294         int node = dev_to_node(d);
5295
5296         data = kmalloc_node(R8169_RX_BUF_SIZE, GFP_KERNEL, node);
5297         if (!data)
5298                 return NULL;
5299
5300         /* Memory should be properly aligned, but better check. */
5301         if (!IS_ALIGNED((unsigned long)data, 8)) {
5302                 netdev_err_once(tp->dev, "RX buffer not 8-byte-aligned\n");
5303                 goto err_out;
5304         }
5305
5306         mapping = dma_map_single(d, data, R8169_RX_BUF_SIZE, DMA_FROM_DEVICE);
5307         if (unlikely(dma_mapping_error(d, mapping))) {
5308                 if (net_ratelimit())
5309                         netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
5310                 goto err_out;
5311         }
5312
5313         desc->addr = cpu_to_le64(mapping);
5314         rtl8169_mark_to_asic(desc);
5315         return data;
5316
5317 err_out:
5318         kfree(data);
5319         return NULL;
5320 }
5321
5322 static void rtl8169_rx_clear(struct rtl8169_private *tp)
5323 {
5324         unsigned int i;
5325
5326         for (i = 0; i < NUM_RX_DESC; i++) {
5327                 if (tp->Rx_databuff[i]) {
5328                         rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
5329                                             tp->RxDescArray + i);
5330                 }
5331         }
5332 }
5333
5334 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
5335 {
5336         desc->opts1 |= cpu_to_le32(RingEnd);
5337 }
5338
5339 static int rtl8169_rx_fill(struct rtl8169_private *tp)
5340 {
5341         unsigned int i;
5342
5343         for (i = 0; i < NUM_RX_DESC; i++) {
5344                 void *data;
5345
5346                 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
5347                 if (!data) {
5348                         rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
5349                         goto err_out;
5350                 }
5351                 tp->Rx_databuff[i] = data;
5352         }
5353
5354         rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
5355         return 0;
5356
5357 err_out:
5358         rtl8169_rx_clear(tp);
5359         return -ENOMEM;
5360 }
5361
5362 static int rtl8169_init_ring(struct rtl8169_private *tp)
5363 {
5364         rtl8169_init_ring_indexes(tp);
5365
5366         memset(tp->tx_skb, 0, sizeof(tp->tx_skb));
5367         memset(tp->Rx_databuff, 0, sizeof(tp->Rx_databuff));
5368
5369         return rtl8169_rx_fill(tp);
5370 }
5371
5372 static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
5373                                  struct TxDesc *desc)
5374 {
5375         unsigned int len = tx_skb->len;
5376
5377         dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
5378
5379         desc->opts1 = 0x00;
5380         desc->opts2 = 0x00;
5381         desc->addr = 0x00;
5382         tx_skb->len = 0;
5383 }
5384
5385 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
5386                                    unsigned int n)
5387 {
5388         unsigned int i;
5389
5390         for (i = 0; i < n; i++) {
5391                 unsigned int entry = (start + i) % NUM_TX_DESC;
5392                 struct ring_info *tx_skb = tp->tx_skb + entry;
5393                 unsigned int len = tx_skb->len;
5394
5395                 if (len) {
5396                         struct sk_buff *skb = tx_skb->skb;
5397
5398                         rtl8169_unmap_tx_skb(tp_to_dev(tp), tx_skb,
5399                                              tp->TxDescArray + entry);
5400                         if (skb) {
5401                                 dev_consume_skb_any(skb);
5402                                 tx_skb->skb = NULL;
5403                         }
5404                 }
5405         }
5406 }
5407
5408 static void rtl8169_tx_clear(struct rtl8169_private *tp)
5409 {
5410         rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
5411         tp->cur_tx = tp->dirty_tx = 0;
5412         netdev_reset_queue(tp->dev);
5413 }
5414
5415 static void rtl_reset_work(struct rtl8169_private *tp)
5416 {
5417         struct net_device *dev = tp->dev;
5418         int i;
5419
5420         napi_disable(&tp->napi);
5421         netif_stop_queue(dev);
5422         synchronize_rcu();
5423
5424         rtl8169_hw_reset(tp);
5425
5426         for (i = 0; i < NUM_RX_DESC; i++)
5427                 rtl8169_mark_to_asic(tp->RxDescArray + i);
5428
5429         rtl8169_tx_clear(tp);
5430         rtl8169_init_ring_indexes(tp);
5431
5432         napi_enable(&tp->napi);
5433         rtl_hw_start(tp);
5434         netif_wake_queue(dev);
5435 }
5436
5437 static void rtl8169_tx_timeout(struct net_device *dev)
5438 {
5439         struct rtl8169_private *tp = netdev_priv(dev);
5440
5441         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
5442 }
5443
5444 static __le32 rtl8169_get_txd_opts1(u32 opts0, u32 len, unsigned int entry)
5445 {
5446         u32 status = opts0 | len;
5447
5448         if (entry == NUM_TX_DESC - 1)
5449                 status |= RingEnd;
5450
5451         return cpu_to_le32(status);
5452 }
5453
5454 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
5455                               u32 *opts)
5456 {
5457         struct skb_shared_info *info = skb_shinfo(skb);
5458         unsigned int cur_frag, entry;
5459         struct TxDesc *uninitialized_var(txd);
5460         struct device *d = tp_to_dev(tp);
5461
5462         entry = tp->cur_tx;
5463         for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
5464                 const skb_frag_t *frag = info->frags + cur_frag;
5465                 dma_addr_t mapping;
5466                 u32 len;
5467                 void *addr;
5468
5469                 entry = (entry + 1) % NUM_TX_DESC;
5470
5471                 txd = tp->TxDescArray + entry;
5472                 len = skb_frag_size(frag);
5473                 addr = skb_frag_address(frag);
5474                 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
5475                 if (unlikely(dma_mapping_error(d, mapping))) {
5476                         if (net_ratelimit())
5477                                 netif_err(tp, drv, tp->dev,
5478                                           "Failed to map TX fragments DMA!\n");
5479                         goto err_out;
5480                 }
5481
5482                 txd->opts1 = rtl8169_get_txd_opts1(opts[0], len, entry);
5483                 txd->opts2 = cpu_to_le32(opts[1]);
5484                 txd->addr = cpu_to_le64(mapping);
5485
5486                 tp->tx_skb[entry].len = len;
5487         }
5488
5489         if (cur_frag) {
5490                 tp->tx_skb[entry].skb = skb;
5491                 txd->opts1 |= cpu_to_le32(LastFrag);
5492         }
5493
5494         return cur_frag;
5495
5496 err_out:
5497         rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
5498         return -EIO;
5499 }
5500
5501 static bool rtl_test_hw_pad_bug(struct rtl8169_private *tp, struct sk_buff *skb)
5502 {
5503         return skb->len < ETH_ZLEN && tp->mac_version == RTL_GIGA_MAC_VER_34;
5504 }
5505
5506 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
5507                                       struct net_device *dev);
5508 /* r8169_csum_workaround()
5509  * The hw limites the value the transport offset. When the offset is out of the
5510  * range, calculate the checksum by sw.
5511  */
5512 static void r8169_csum_workaround(struct rtl8169_private *tp,
5513                                   struct sk_buff *skb)
5514 {
5515         if (skb_is_gso(skb)) {
5516                 netdev_features_t features = tp->dev->features;
5517                 struct sk_buff *segs, *nskb;
5518
5519                 features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
5520                 segs = skb_gso_segment(skb, features);
5521                 if (IS_ERR(segs) || !segs)
5522                         goto drop;
5523
5524                 do {
5525                         nskb = segs;
5526                         segs = segs->next;
5527                         nskb->next = NULL;
5528                         rtl8169_start_xmit(nskb, tp->dev);
5529                 } while (segs);
5530
5531                 dev_consume_skb_any(skb);
5532         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5533                 if (skb_checksum_help(skb) < 0)
5534                         goto drop;
5535
5536                 rtl8169_start_xmit(skb, tp->dev);
5537         } else {
5538 drop:
5539                 tp->dev->stats.tx_dropped++;
5540                 dev_kfree_skb_any(skb);
5541         }
5542 }
5543
5544 /* msdn_giant_send_check()
5545  * According to the document of microsoft, the TCP Pseudo Header excludes the
5546  * packet length for IPv6 TCP large packets.
5547  */
5548 static int msdn_giant_send_check(struct sk_buff *skb)
5549 {
5550         const struct ipv6hdr *ipv6h;
5551         struct tcphdr *th;
5552         int ret;
5553
5554         ret = skb_cow_head(skb, 0);
5555         if (ret)
5556                 return ret;
5557
5558         ipv6h = ipv6_hdr(skb);
5559         th = tcp_hdr(skb);
5560
5561         th->check = 0;
5562         th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0);
5563
5564         return ret;
5565 }
5566
5567 static void rtl8169_tso_csum_v1(struct sk_buff *skb, u32 *opts)
5568 {
5569         u32 mss = skb_shinfo(skb)->gso_size;
5570
5571         if (mss) {
5572                 opts[0] |= TD_LSO;
5573                 opts[0] |= min(mss, TD_MSS_MAX) << TD0_MSS_SHIFT;
5574         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5575                 const struct iphdr *ip = ip_hdr(skb);
5576
5577                 if (ip->protocol == IPPROTO_TCP)
5578                         opts[0] |= TD0_IP_CS | TD0_TCP_CS;
5579                 else if (ip->protocol == IPPROTO_UDP)
5580                         opts[0] |= TD0_IP_CS | TD0_UDP_CS;
5581                 else
5582                         WARN_ON_ONCE(1);
5583         }
5584 }
5585
5586 static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp,
5587                                 struct sk_buff *skb, u32 *opts)
5588 {
5589         u32 transport_offset = (u32)skb_transport_offset(skb);
5590         u32 mss = skb_shinfo(skb)->gso_size;
5591
5592         if (mss) {
5593                 if (transport_offset > GTTCPHO_MAX) {
5594                         netif_warn(tp, tx_err, tp->dev,
5595                                    "Invalid transport offset 0x%x for TSO\n",
5596                                    transport_offset);
5597                         return false;
5598                 }
5599
5600                 switch (vlan_get_protocol(skb)) {
5601                 case htons(ETH_P_IP):
5602                         opts[0] |= TD1_GTSENV4;
5603                         break;
5604
5605                 case htons(ETH_P_IPV6):
5606                         if (msdn_giant_send_check(skb))
5607                                 return false;
5608
5609                         opts[0] |= TD1_GTSENV6;
5610                         break;
5611
5612                 default:
5613                         WARN_ON_ONCE(1);
5614                         break;
5615                 }
5616
5617                 opts[0] |= transport_offset << GTTCPHO_SHIFT;
5618                 opts[1] |= min(mss, TD_MSS_MAX) << TD1_MSS_SHIFT;
5619         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5620                 u8 ip_protocol;
5621
5622                 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
5623                         return !(skb_checksum_help(skb) || eth_skb_pad(skb));
5624
5625                 if (transport_offset > TCPHO_MAX) {
5626                         netif_warn(tp, tx_err, tp->dev,
5627                                    "Invalid transport offset 0x%x\n",
5628                                    transport_offset);
5629                         return false;
5630                 }
5631
5632                 switch (vlan_get_protocol(skb)) {
5633                 case htons(ETH_P_IP):
5634                         opts[1] |= TD1_IPv4_CS;
5635                         ip_protocol = ip_hdr(skb)->protocol;
5636                         break;
5637
5638                 case htons(ETH_P_IPV6):
5639                         opts[1] |= TD1_IPv6_CS;
5640                         ip_protocol = ipv6_hdr(skb)->nexthdr;
5641                         break;
5642
5643                 default:
5644                         ip_protocol = IPPROTO_RAW;
5645                         break;
5646                 }
5647
5648                 if (ip_protocol == IPPROTO_TCP)
5649                         opts[1] |= TD1_TCP_CS;
5650                 else if (ip_protocol == IPPROTO_UDP)
5651                         opts[1] |= TD1_UDP_CS;
5652                 else
5653                         WARN_ON_ONCE(1);
5654
5655                 opts[1] |= transport_offset << TCPHO_SHIFT;
5656         } else {
5657                 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
5658                         return !eth_skb_pad(skb);
5659         }
5660
5661         return true;
5662 }
5663
5664 static bool rtl_tx_slots_avail(struct rtl8169_private *tp,
5665                                unsigned int nr_frags)
5666 {
5667         unsigned int slots_avail = tp->dirty_tx + NUM_TX_DESC - tp->cur_tx;
5668
5669         /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
5670         return slots_avail > nr_frags;
5671 }
5672
5673 /* Versions RTL8102e and from RTL8168c onwards support csum_v2 */
5674 static bool rtl_chip_supports_csum_v2(struct rtl8169_private *tp)
5675 {
5676         switch (tp->mac_version) {
5677         case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
5678         case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
5679                 return false;
5680         default:
5681                 return true;
5682         }
5683 }
5684
5685 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
5686                                       struct net_device *dev)
5687 {
5688         struct rtl8169_private *tp = netdev_priv(dev);
5689         unsigned int entry = tp->cur_tx % NUM_TX_DESC;
5690         struct TxDesc *txd = tp->TxDescArray + entry;
5691         struct device *d = tp_to_dev(tp);
5692         dma_addr_t mapping;
5693         u32 opts[2], len;
5694         int frags;
5695
5696         if (unlikely(!rtl_tx_slots_avail(tp, skb_shinfo(skb)->nr_frags))) {
5697                 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
5698                 goto err_stop_0;
5699         }
5700
5701         if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
5702                 goto err_stop_0;
5703
5704         opts[1] = rtl8169_tx_vlan_tag(skb);
5705         opts[0] = DescOwn;
5706
5707         if (rtl_chip_supports_csum_v2(tp)) {
5708                 if (!rtl8169_tso_csum_v2(tp, skb, opts)) {
5709                         r8169_csum_workaround(tp, skb);
5710                         return NETDEV_TX_OK;
5711                 }
5712         } else {
5713                 rtl8169_tso_csum_v1(skb, opts);
5714         }
5715
5716         len = skb_headlen(skb);
5717         mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
5718         if (unlikely(dma_mapping_error(d, mapping))) {
5719                 if (net_ratelimit())
5720                         netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
5721                 goto err_dma_0;
5722         }
5723
5724         tp->tx_skb[entry].len = len;
5725         txd->addr = cpu_to_le64(mapping);
5726
5727         frags = rtl8169_xmit_frags(tp, skb, opts);
5728         if (frags < 0)
5729                 goto err_dma_1;
5730         else if (frags)
5731                 opts[0] |= FirstFrag;
5732         else {
5733                 opts[0] |= FirstFrag | LastFrag;
5734                 tp->tx_skb[entry].skb = skb;
5735         }
5736
5737         txd->opts2 = cpu_to_le32(opts[1]);
5738
5739         netdev_sent_queue(dev, skb->len);
5740
5741         skb_tx_timestamp(skb);
5742
5743         /* Force memory writes to complete before releasing descriptor */
5744         dma_wmb();
5745
5746         txd->opts1 = rtl8169_get_txd_opts1(opts[0], len, entry);
5747
5748         /* Force all memory writes to complete before notifying device */
5749         wmb();
5750
5751         tp->cur_tx += frags + 1;
5752
5753         RTL_W8(tp, TxPoll, NPQ);
5754
5755         if (!rtl_tx_slots_avail(tp, MAX_SKB_FRAGS)) {
5756                 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
5757                  * not miss a ring update when it notices a stopped queue.
5758                  */
5759                 smp_wmb();
5760                 netif_stop_queue(dev);
5761                 /* Sync with rtl_tx:
5762                  * - publish queue status and cur_tx ring index (write barrier)
5763                  * - refresh dirty_tx ring index (read barrier).
5764                  * May the current thread have a pessimistic view of the ring
5765                  * status and forget to wake up queue, a racing rtl_tx thread
5766                  * can't.
5767                  */
5768                 smp_mb();
5769                 if (rtl_tx_slots_avail(tp, MAX_SKB_FRAGS))
5770                         netif_start_queue(dev);
5771         }
5772
5773         return NETDEV_TX_OK;
5774
5775 err_dma_1:
5776         rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
5777 err_dma_0:
5778         dev_kfree_skb_any(skb);
5779         dev->stats.tx_dropped++;
5780         return NETDEV_TX_OK;
5781
5782 err_stop_0:
5783         netif_stop_queue(dev);
5784         dev->stats.tx_dropped++;
5785         return NETDEV_TX_BUSY;
5786 }
5787
5788 static void rtl8169_pcierr_interrupt(struct net_device *dev)
5789 {
5790         struct rtl8169_private *tp = netdev_priv(dev);
5791         struct pci_dev *pdev = tp->pci_dev;
5792         u16 pci_status, pci_cmd;
5793
5794         pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
5795         pci_read_config_word(pdev, PCI_STATUS, &pci_status);
5796
5797         netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
5798                   pci_cmd, pci_status);
5799
5800         /*
5801          * The recovery sequence below admits a very elaborated explanation:
5802          * - it seems to work;
5803          * - I did not see what else could be done;
5804          * - it makes iop3xx happy.
5805          *
5806          * Feel free to adjust to your needs.
5807          */
5808         if (pdev->broken_parity_status)
5809                 pci_cmd &= ~PCI_COMMAND_PARITY;
5810         else
5811                 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
5812
5813         pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
5814
5815         pci_write_config_word(pdev, PCI_STATUS,
5816                 pci_status & (PCI_STATUS_DETECTED_PARITY |
5817                 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
5818                 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
5819
5820         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
5821 }
5822
5823 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp,
5824                    int budget)
5825 {
5826         unsigned int dirty_tx, tx_left, bytes_compl = 0, pkts_compl = 0;
5827
5828         dirty_tx = tp->dirty_tx;
5829         smp_rmb();
5830         tx_left = tp->cur_tx - dirty_tx;
5831
5832         while (tx_left > 0) {
5833                 unsigned int entry = dirty_tx % NUM_TX_DESC;
5834                 struct ring_info *tx_skb = tp->tx_skb + entry;
5835                 u32 status;
5836
5837                 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
5838                 if (status & DescOwn)
5839                         break;
5840
5841                 /* This barrier is needed to keep us from reading
5842                  * any other fields out of the Tx descriptor until
5843                  * we know the status of DescOwn
5844                  */
5845                 dma_rmb();
5846
5847                 rtl8169_unmap_tx_skb(tp_to_dev(tp), tx_skb,
5848                                      tp->TxDescArray + entry);
5849                 if (status & LastFrag) {
5850                         pkts_compl++;
5851                         bytes_compl += tx_skb->skb->len;
5852                         napi_consume_skb(tx_skb->skb, budget);
5853                         tx_skb->skb = NULL;
5854                 }
5855                 dirty_tx++;
5856                 tx_left--;
5857         }
5858
5859         if (tp->dirty_tx != dirty_tx) {
5860                 netdev_completed_queue(dev, pkts_compl, bytes_compl);
5861
5862                 u64_stats_update_begin(&tp->tx_stats.syncp);
5863                 tp->tx_stats.packets += pkts_compl;
5864                 tp->tx_stats.bytes += bytes_compl;
5865                 u64_stats_update_end(&tp->tx_stats.syncp);
5866
5867                 tp->dirty_tx = dirty_tx;
5868                 /* Sync with rtl8169_start_xmit:
5869                  * - publish dirty_tx ring index (write barrier)
5870                  * - refresh cur_tx ring index and queue status (read barrier)
5871                  * May the current thread miss the stopped queue condition,
5872                  * a racing xmit thread can only have a right view of the
5873                  * ring status.
5874                  */
5875                 smp_mb();
5876                 if (netif_queue_stopped(dev) &&
5877                     rtl_tx_slots_avail(tp, MAX_SKB_FRAGS)) {
5878                         netif_wake_queue(dev);
5879                 }
5880                 /*
5881                  * 8168 hack: TxPoll requests are lost when the Tx packets are
5882                  * too close. Let's kick an extra TxPoll request when a burst
5883                  * of start_xmit activity is detected (if it is not detected,
5884                  * it is slow enough). -- FR
5885                  */
5886                 if (tp->cur_tx != dirty_tx)
5887                         RTL_W8(tp, TxPoll, NPQ);
5888         }
5889 }
5890
5891 static inline int rtl8169_fragmented_frame(u32 status)
5892 {
5893         return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
5894 }
5895
5896 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
5897 {
5898         u32 status = opts1 & RxProtoMask;
5899
5900         if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
5901             ((status == RxProtoUDP) && !(opts1 & UDPFail)))
5902                 skb->ip_summed = CHECKSUM_UNNECESSARY;
5903         else
5904                 skb_checksum_none_assert(skb);
5905 }
5906
5907 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget)
5908 {
5909         unsigned int cur_rx, rx_left;
5910         unsigned int count;
5911
5912         cur_rx = tp->cur_rx;
5913
5914         for (rx_left = min(budget, NUM_RX_DESC); rx_left > 0; rx_left--, cur_rx++) {
5915                 unsigned int entry = cur_rx % NUM_RX_DESC;
5916                 struct RxDesc *desc = tp->RxDescArray + entry;
5917                 u32 status;
5918
5919                 status = le32_to_cpu(desc->opts1);
5920                 if (status & DescOwn)
5921                         break;
5922
5923                 /* This barrier is needed to keep us from reading
5924                  * any other fields out of the Rx descriptor until
5925                  * we know the status of DescOwn
5926                  */
5927                 dma_rmb();
5928
5929                 if (unlikely(status & RxRES)) {
5930                         netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
5931                                    status);
5932                         dev->stats.rx_errors++;
5933                         if (status & (RxRWT | RxRUNT))
5934                                 dev->stats.rx_length_errors++;
5935                         if (status & RxCRC)
5936                                 dev->stats.rx_crc_errors++;
5937                         if (status & (RxRUNT | RxCRC) && !(status & RxRWT) &&
5938                             dev->features & NETIF_F_RXALL) {
5939                                 goto process_pkt;
5940                         }
5941                 } else {
5942                         unsigned int pkt_size;
5943                         struct sk_buff *skb;
5944
5945 process_pkt:
5946                         pkt_size = status & GENMASK(13, 0);
5947                         if (likely(!(dev->features & NETIF_F_RXFCS)))
5948                                 pkt_size -= ETH_FCS_LEN;
5949                         /*
5950                          * The driver does not support incoming fragmented
5951                          * frames. They are seen as a symptom of over-mtu
5952                          * sized frames.
5953                          */
5954                         if (unlikely(rtl8169_fragmented_frame(status))) {
5955                                 dev->stats.rx_dropped++;
5956                                 dev->stats.rx_length_errors++;
5957                                 goto release_descriptor;
5958                         }
5959
5960                         dma_sync_single_for_cpu(tp_to_dev(tp),
5961                                                 le64_to_cpu(desc->addr),
5962                                                 pkt_size, DMA_FROM_DEVICE);
5963
5964                         skb = napi_alloc_skb(&tp->napi, pkt_size);
5965                         if (unlikely(!skb)) {
5966                                 dev->stats.rx_dropped++;
5967                                 goto release_descriptor;
5968                         }
5969
5970                         prefetch(tp->Rx_databuff[entry]);
5971                         skb_copy_to_linear_data(skb, tp->Rx_databuff[entry],
5972                                                 pkt_size);
5973                         skb->tail += pkt_size;
5974                         skb->len = pkt_size;
5975
5976                         rtl8169_rx_csum(skb, status);
5977                         skb->protocol = eth_type_trans(skb, dev);
5978
5979                         rtl8169_rx_vlan_tag(desc, skb);
5980
5981                         if (skb->pkt_type == PACKET_MULTICAST)
5982                                 dev->stats.multicast++;
5983
5984                         napi_gro_receive(&tp->napi, skb);
5985
5986                         u64_stats_update_begin(&tp->rx_stats.syncp);
5987                         tp->rx_stats.packets++;
5988                         tp->rx_stats.bytes += pkt_size;
5989                         u64_stats_update_end(&tp->rx_stats.syncp);
5990                 }
5991 release_descriptor:
5992                 desc->opts2 = 0;
5993                 rtl8169_mark_to_asic(desc);
5994         }
5995
5996         count = cur_rx - tp->cur_rx;
5997         tp->cur_rx = cur_rx;
5998
5999         return count;
6000 }
6001
6002 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
6003 {
6004         struct rtl8169_private *tp = dev_instance;
6005         u16 status = RTL_R16(tp, IntrStatus);
6006
6007         if (!tp->irq_enabled || status == 0xffff || !(status & tp->irq_mask))
6008                 return IRQ_NONE;
6009
6010         if (unlikely(status & SYSErr)) {
6011                 rtl8169_pcierr_interrupt(tp->dev);
6012                 goto out;
6013         }
6014
6015         if (status & LinkChg)
6016                 phy_mac_interrupt(tp->phydev);
6017
6018         if (unlikely(status & RxFIFOOver &&
6019             tp->mac_version == RTL_GIGA_MAC_VER_11)) {
6020                 netif_stop_queue(tp->dev);
6021                 /* XXX - Hack alert. See rtl_task(). */
6022                 set_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags);
6023         }
6024
6025         rtl_irq_disable(tp);
6026         napi_schedule_irqoff(&tp->napi);
6027 out:
6028         rtl_ack_events(tp, status);
6029
6030         return IRQ_HANDLED;
6031 }
6032
6033 static void rtl_task(struct work_struct *work)
6034 {
6035         static const struct {
6036                 int bitnr;
6037                 void (*action)(struct rtl8169_private *);
6038         } rtl_work[] = {
6039                 { RTL_FLAG_TASK_RESET_PENDING,  rtl_reset_work },
6040         };
6041         struct rtl8169_private *tp =
6042                 container_of(work, struct rtl8169_private, wk.work);
6043         struct net_device *dev = tp->dev;
6044         int i;
6045
6046         rtl_lock_work(tp);
6047
6048         if (!netif_running(dev) ||
6049             !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
6050                 goto out_unlock;
6051
6052         for (i = 0; i < ARRAY_SIZE(rtl_work); i++) {
6053                 bool pending;
6054
6055                 pending = test_and_clear_bit(rtl_work[i].bitnr, tp->wk.flags);
6056                 if (pending)
6057                         rtl_work[i].action(tp);
6058         }
6059
6060 out_unlock:
6061         rtl_unlock_work(tp);
6062 }
6063
6064 static int rtl8169_poll(struct napi_struct *napi, int budget)
6065 {
6066         struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
6067         struct net_device *dev = tp->dev;
6068         int work_done;
6069
6070         work_done = rtl_rx(dev, tp, (u32) budget);
6071
6072         rtl_tx(dev, tp, budget);
6073
6074         if (work_done < budget) {
6075                 napi_complete_done(napi, work_done);
6076                 rtl_irq_enable(tp);
6077         }
6078
6079         return work_done;
6080 }
6081
6082 static void rtl8169_rx_missed(struct net_device *dev)
6083 {
6084         struct rtl8169_private *tp = netdev_priv(dev);
6085
6086         if (tp->mac_version > RTL_GIGA_MAC_VER_06)
6087                 return;
6088
6089         dev->stats.rx_missed_errors += RTL_R32(tp, RxMissed) & 0xffffff;
6090         RTL_W32(tp, RxMissed, 0);
6091 }
6092
6093 static void r8169_phylink_handler(struct net_device *ndev)
6094 {
6095         struct rtl8169_private *tp = netdev_priv(ndev);
6096
6097         if (netif_carrier_ok(ndev)) {
6098                 rtl_link_chg_patch(tp);
6099                 pm_request_resume(&tp->pci_dev->dev);
6100         } else {
6101                 pm_runtime_idle(&tp->pci_dev->dev);
6102         }
6103
6104         if (net_ratelimit())
6105                 phy_print_status(tp->phydev);
6106 }
6107
6108 static int r8169_phy_connect(struct rtl8169_private *tp)
6109 {
6110         struct phy_device *phydev = tp->phydev;
6111         phy_interface_t phy_mode;
6112         int ret;
6113
6114         phy_mode = tp->supports_gmii ? PHY_INTERFACE_MODE_GMII :
6115                    PHY_INTERFACE_MODE_MII;
6116
6117         ret = phy_connect_direct(tp->dev, phydev, r8169_phylink_handler,
6118                                  phy_mode);
6119         if (ret)
6120                 return ret;
6121
6122         if (tp->supports_gmii)
6123                 phy_remove_link_mode(phydev,
6124                                      ETHTOOL_LINK_MODE_1000baseT_Half_BIT);
6125         else
6126                 phy_set_max_speed(phydev, SPEED_100);
6127
6128         phy_support_asym_pause(phydev);
6129
6130         phy_attached_info(phydev);
6131
6132         return 0;
6133 }
6134
6135 static void rtl8169_down(struct net_device *dev)
6136 {
6137         struct rtl8169_private *tp = netdev_priv(dev);
6138
6139         phy_stop(tp->phydev);
6140
6141         napi_disable(&tp->napi);
6142         netif_stop_queue(dev);
6143
6144         rtl8169_hw_reset(tp);
6145         /*
6146          * At this point device interrupts can not be enabled in any function,
6147          * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task)
6148          * and napi is disabled (rtl8169_poll).
6149          */
6150         rtl8169_rx_missed(dev);
6151
6152         /* Give a racing hard_start_xmit a few cycles to complete. */
6153         synchronize_rcu();
6154
6155         rtl8169_tx_clear(tp);
6156
6157         rtl8169_rx_clear(tp);
6158
6159         rtl_pll_power_down(tp);
6160 }
6161
6162 static int rtl8169_close(struct net_device *dev)
6163 {
6164         struct rtl8169_private *tp = netdev_priv(dev);
6165         struct pci_dev *pdev = tp->pci_dev;
6166
6167         pm_runtime_get_sync(&pdev->dev);
6168
6169         /* Update counters before going down */
6170         rtl8169_update_counters(tp);
6171
6172         rtl_lock_work(tp);
6173         /* Clear all task flags */
6174         bitmap_zero(tp->wk.flags, RTL_FLAG_MAX);
6175
6176         rtl8169_down(dev);
6177         rtl_unlock_work(tp);
6178
6179         cancel_work_sync(&tp->wk.work);
6180
6181         phy_disconnect(tp->phydev);
6182
6183         pci_free_irq(pdev, 0, tp);
6184
6185         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6186                           tp->RxPhyAddr);
6187         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6188                           tp->TxPhyAddr);
6189         tp->TxDescArray = NULL;
6190         tp->RxDescArray = NULL;
6191
6192         pm_runtime_put_sync(&pdev->dev);
6193
6194         return 0;
6195 }
6196
6197 #ifdef CONFIG_NET_POLL_CONTROLLER
6198 static void rtl8169_netpoll(struct net_device *dev)
6199 {
6200         struct rtl8169_private *tp = netdev_priv(dev);
6201
6202         rtl8169_interrupt(pci_irq_vector(tp->pci_dev, 0), tp);
6203 }
6204 #endif
6205
6206 static int rtl_open(struct net_device *dev)
6207 {
6208         struct rtl8169_private *tp = netdev_priv(dev);
6209         struct pci_dev *pdev = tp->pci_dev;
6210         int retval = -ENOMEM;
6211
6212         pm_runtime_get_sync(&pdev->dev);
6213
6214         /*
6215          * Rx and Tx descriptors needs 256 bytes alignment.
6216          * dma_alloc_coherent provides more.
6217          */
6218         tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
6219                                              &tp->TxPhyAddr, GFP_KERNEL);
6220         if (!tp->TxDescArray)
6221                 goto err_pm_runtime_put;
6222
6223         tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
6224                                              &tp->RxPhyAddr, GFP_KERNEL);
6225         if (!tp->RxDescArray)
6226                 goto err_free_tx_0;
6227
6228         retval = rtl8169_init_ring(tp);
6229         if (retval < 0)
6230                 goto err_free_rx_1;
6231
6232         rtl_request_firmware(tp);
6233
6234         retval = pci_request_irq(pdev, 0, rtl8169_interrupt, NULL, tp,
6235                                  dev->name);
6236         if (retval < 0)
6237                 goto err_release_fw_2;
6238
6239         retval = r8169_phy_connect(tp);
6240         if (retval)
6241                 goto err_free_irq;
6242
6243         rtl_lock_work(tp);
6244
6245         set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6246
6247         napi_enable(&tp->napi);
6248
6249         rtl8169_init_phy(dev, tp);
6250
6251         rtl_pll_power_up(tp);
6252
6253         rtl_hw_start(tp);
6254
6255         if (!rtl8169_init_counter_offsets(tp))
6256                 netif_warn(tp, hw, dev, "counter reset/update failed\n");
6257
6258         phy_start(tp->phydev);
6259         netif_start_queue(dev);
6260
6261         rtl_unlock_work(tp);
6262
6263         pm_runtime_put_sync(&pdev->dev);
6264 out:
6265         return retval;
6266
6267 err_free_irq:
6268         pci_free_irq(pdev, 0, tp);
6269 err_release_fw_2:
6270         rtl_release_firmware(tp);
6271         rtl8169_rx_clear(tp);
6272 err_free_rx_1:
6273         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6274                           tp->RxPhyAddr);
6275         tp->RxDescArray = NULL;
6276 err_free_tx_0:
6277         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6278                           tp->TxPhyAddr);
6279         tp->TxDescArray = NULL;
6280 err_pm_runtime_put:
6281         pm_runtime_put_noidle(&pdev->dev);
6282         goto out;
6283 }
6284
6285 static void
6286 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
6287 {
6288         struct rtl8169_private *tp = netdev_priv(dev);
6289         struct pci_dev *pdev = tp->pci_dev;
6290         struct rtl8169_counters *counters = tp->counters;
6291         unsigned int start;
6292
6293         pm_runtime_get_noresume(&pdev->dev);
6294
6295         if (netif_running(dev) && pm_runtime_active(&pdev->dev))
6296                 rtl8169_rx_missed(dev);
6297
6298         do {
6299                 start = u64_stats_fetch_begin_irq(&tp->rx_stats.syncp);
6300                 stats->rx_packets = tp->rx_stats.packets;
6301                 stats->rx_bytes = tp->rx_stats.bytes;
6302         } while (u64_stats_fetch_retry_irq(&tp->rx_stats.syncp, start));
6303
6304         do {
6305                 start = u64_stats_fetch_begin_irq(&tp->tx_stats.syncp);
6306                 stats->tx_packets = tp->tx_stats.packets;
6307                 stats->tx_bytes = tp->tx_stats.bytes;
6308         } while (u64_stats_fetch_retry_irq(&tp->tx_stats.syncp, start));
6309
6310         stats->rx_dropped       = dev->stats.rx_dropped;
6311         stats->tx_dropped       = dev->stats.tx_dropped;
6312         stats->rx_length_errors = dev->stats.rx_length_errors;
6313         stats->rx_errors        = dev->stats.rx_errors;
6314         stats->rx_crc_errors    = dev->stats.rx_crc_errors;
6315         stats->rx_fifo_errors   = dev->stats.rx_fifo_errors;
6316         stats->rx_missed_errors = dev->stats.rx_missed_errors;
6317         stats->multicast        = dev->stats.multicast;
6318
6319         /*
6320          * Fetch additional counter values missing in stats collected by driver
6321          * from tally counters.
6322          */
6323         if (pm_runtime_active(&pdev->dev))
6324                 rtl8169_update_counters(tp);
6325
6326         /*
6327          * Subtract values fetched during initalization.
6328          * See rtl8169_init_counter_offsets for a description why we do that.
6329          */
6330         stats->tx_errors = le64_to_cpu(counters->tx_errors) -
6331                 le64_to_cpu(tp->tc_offset.tx_errors);
6332         stats->collisions = le32_to_cpu(counters->tx_multi_collision) -
6333                 le32_to_cpu(tp->tc_offset.tx_multi_collision);
6334         stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) -
6335                 le16_to_cpu(tp->tc_offset.tx_aborted);
6336
6337         pm_runtime_put_noidle(&pdev->dev);
6338 }
6339
6340 static void rtl8169_net_suspend(struct net_device *dev)
6341 {
6342         struct rtl8169_private *tp = netdev_priv(dev);
6343
6344         if (!netif_running(dev))
6345                 return;
6346
6347         phy_stop(tp->phydev);
6348         netif_device_detach(dev);
6349
6350         rtl_lock_work(tp);
6351         napi_disable(&tp->napi);
6352         /* Clear all task flags */
6353         bitmap_zero(tp->wk.flags, RTL_FLAG_MAX);
6354
6355         rtl_unlock_work(tp);
6356
6357         rtl_pll_power_down(tp);
6358 }
6359
6360 #ifdef CONFIG_PM
6361
6362 static int rtl8169_suspend(struct device *device)
6363 {
6364         struct net_device *dev = dev_get_drvdata(device);
6365         struct rtl8169_private *tp = netdev_priv(dev);
6366
6367         rtl8169_net_suspend(dev);
6368         clk_disable_unprepare(tp->clk);
6369
6370         return 0;
6371 }
6372
6373 static void __rtl8169_resume(struct net_device *dev)
6374 {
6375         struct rtl8169_private *tp = netdev_priv(dev);
6376
6377         netif_device_attach(dev);
6378
6379         rtl_pll_power_up(tp);
6380         rtl8169_init_phy(dev, tp);
6381
6382         phy_start(tp->phydev);
6383
6384         rtl_lock_work(tp);
6385         napi_enable(&tp->napi);
6386         set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6387         rtl_reset_work(tp);
6388         rtl_unlock_work(tp);
6389 }
6390
6391 static int rtl8169_resume(struct device *device)
6392 {
6393         struct net_device *dev = dev_get_drvdata(device);
6394         struct rtl8169_private *tp = netdev_priv(dev);
6395
6396         rtl_rar_set(tp, dev->dev_addr);
6397
6398         clk_prepare_enable(tp->clk);
6399
6400         if (netif_running(dev))
6401                 __rtl8169_resume(dev);
6402
6403         return 0;
6404 }
6405
6406 static int rtl8169_runtime_suspend(struct device *device)
6407 {
6408         struct net_device *dev = dev_get_drvdata(device);
6409         struct rtl8169_private *tp = netdev_priv(dev);
6410
6411         if (!tp->TxDescArray)
6412                 return 0;
6413
6414         rtl_lock_work(tp);
6415         __rtl8169_set_wol(tp, WAKE_ANY);
6416         rtl_unlock_work(tp);
6417
6418         rtl8169_net_suspend(dev);
6419
6420         /* Update counters before going runtime suspend */
6421         rtl8169_rx_missed(dev);
6422         rtl8169_update_counters(tp);
6423
6424         return 0;
6425 }
6426
6427 static int rtl8169_runtime_resume(struct device *device)
6428 {
6429         struct net_device *dev = dev_get_drvdata(device);
6430         struct rtl8169_private *tp = netdev_priv(dev);
6431
6432         rtl_rar_set(tp, dev->dev_addr);
6433
6434         if (!tp->TxDescArray)
6435                 return 0;
6436
6437         rtl_lock_work(tp);
6438         __rtl8169_set_wol(tp, tp->saved_wolopts);
6439         rtl_unlock_work(tp);
6440
6441         __rtl8169_resume(dev);
6442
6443         return 0;
6444 }
6445
6446 static int rtl8169_runtime_idle(struct device *device)
6447 {
6448         struct net_device *dev = dev_get_drvdata(device);
6449
6450         if (!netif_running(dev) || !netif_carrier_ok(dev))
6451                 pm_schedule_suspend(device, 10000);
6452
6453         return -EBUSY;
6454 }
6455
6456 static const struct dev_pm_ops rtl8169_pm_ops = {
6457         .suspend                = rtl8169_suspend,
6458         .resume                 = rtl8169_resume,
6459         .freeze                 = rtl8169_suspend,
6460         .thaw                   = rtl8169_resume,
6461         .poweroff               = rtl8169_suspend,
6462         .restore                = rtl8169_resume,
6463         .runtime_suspend        = rtl8169_runtime_suspend,
6464         .runtime_resume         = rtl8169_runtime_resume,
6465         .runtime_idle           = rtl8169_runtime_idle,
6466 };
6467
6468 #define RTL8169_PM_OPS  (&rtl8169_pm_ops)
6469
6470 #else /* !CONFIG_PM */
6471
6472 #define RTL8169_PM_OPS  NULL
6473
6474 #endif /* !CONFIG_PM */
6475
6476 static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
6477 {
6478         /* WoL fails with 8168b when the receiver is disabled. */
6479         switch (tp->mac_version) {
6480         case RTL_GIGA_MAC_VER_11:
6481         case RTL_GIGA_MAC_VER_12:
6482         case RTL_GIGA_MAC_VER_17:
6483                 pci_clear_master(tp->pci_dev);
6484
6485                 RTL_W8(tp, ChipCmd, CmdRxEnb);
6486                 /* PCI commit */
6487                 RTL_R8(tp, ChipCmd);
6488                 break;
6489         default:
6490                 break;
6491         }
6492 }
6493
6494 static void rtl_shutdown(struct pci_dev *pdev)
6495 {
6496         struct net_device *dev = pci_get_drvdata(pdev);
6497         struct rtl8169_private *tp = netdev_priv(dev);
6498
6499         rtl8169_net_suspend(dev);
6500
6501         /* Restore original MAC address */
6502         rtl_rar_set(tp, dev->perm_addr);
6503
6504         rtl8169_hw_reset(tp);
6505
6506         if (system_state == SYSTEM_POWER_OFF) {
6507                 if (tp->saved_wolopts) {
6508                         rtl_wol_suspend_quirk(tp);
6509                         rtl_wol_shutdown_quirk(tp);
6510                 }
6511
6512                 pci_wake_from_d3(pdev, true);
6513                 pci_set_power_state(pdev, PCI_D3hot);
6514         }
6515 }
6516
6517 static void rtl_remove_one(struct pci_dev *pdev)
6518 {
6519         struct net_device *dev = pci_get_drvdata(pdev);
6520         struct rtl8169_private *tp = netdev_priv(dev);
6521
6522         if (r8168_check_dash(tp))
6523                 rtl8168_driver_stop(tp);
6524
6525         netif_napi_del(&tp->napi);
6526
6527         unregister_netdev(dev);
6528         mdiobus_unregister(tp->phydev->mdio.bus);
6529
6530         rtl_release_firmware(tp);
6531
6532         if (pci_dev_run_wake(pdev))
6533                 pm_runtime_get_noresume(&pdev->dev);
6534
6535         /* restore original MAC address */
6536         rtl_rar_set(tp, dev->perm_addr);
6537 }
6538
6539 static const struct net_device_ops rtl_netdev_ops = {
6540         .ndo_open               = rtl_open,
6541         .ndo_stop               = rtl8169_close,
6542         .ndo_get_stats64        = rtl8169_get_stats64,
6543         .ndo_start_xmit         = rtl8169_start_xmit,
6544         .ndo_tx_timeout         = rtl8169_tx_timeout,
6545         .ndo_validate_addr      = eth_validate_addr,
6546         .ndo_change_mtu         = rtl8169_change_mtu,
6547         .ndo_fix_features       = rtl8169_fix_features,
6548         .ndo_set_features       = rtl8169_set_features,
6549         .ndo_set_mac_address    = rtl_set_mac_address,
6550         .ndo_do_ioctl           = rtl8169_ioctl,
6551         .ndo_set_rx_mode        = rtl_set_rx_mode,
6552 #ifdef CONFIG_NET_POLL_CONTROLLER
6553         .ndo_poll_controller    = rtl8169_netpoll,
6554 #endif
6555
6556 };
6557
6558 static void rtl_set_irq_mask(struct rtl8169_private *tp)
6559 {
6560         tp->irq_mask = RTL_EVENT_NAPI | LinkChg;
6561
6562         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
6563                 tp->irq_mask |= SYSErr | RxOverflow | RxFIFOOver;
6564         else if (tp->mac_version == RTL_GIGA_MAC_VER_11)
6565                 /* special workaround needed */
6566                 tp->irq_mask |= RxFIFOOver;
6567         else
6568                 tp->irq_mask |= RxOverflow;
6569 }
6570
6571 static int rtl_alloc_irq(struct rtl8169_private *tp)
6572 {
6573         unsigned int flags;
6574
6575         if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
6576                 rtl_unlock_config_regs(tp);
6577                 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~MSIEnable);
6578                 rtl_lock_config_regs(tp);
6579                 flags = PCI_IRQ_LEGACY;
6580         } else {
6581                 flags = PCI_IRQ_ALL_TYPES;
6582         }
6583
6584         return pci_alloc_irq_vectors(tp->pci_dev, 1, 1, flags);
6585 }
6586
6587 static void rtl_read_mac_address(struct rtl8169_private *tp,
6588                                  u8 mac_addr[ETH_ALEN])
6589 {
6590         /* Get MAC address */
6591         if (rtl_is_8168evl_up(tp) && tp->mac_version != RTL_GIGA_MAC_VER_34) {
6592                 u32 value = rtl_eri_read(tp, 0xe0);
6593
6594                 mac_addr[0] = (value >>  0) & 0xff;
6595                 mac_addr[1] = (value >>  8) & 0xff;
6596                 mac_addr[2] = (value >> 16) & 0xff;
6597                 mac_addr[3] = (value >> 24) & 0xff;
6598
6599                 value = rtl_eri_read(tp, 0xe4);
6600                 mac_addr[4] = (value >>  0) & 0xff;
6601                 mac_addr[5] = (value >>  8) & 0xff;
6602         }
6603 }
6604
6605 DECLARE_RTL_COND(rtl_link_list_ready_cond)
6606 {
6607         return RTL_R8(tp, MCU) & LINK_LIST_RDY;
6608 }
6609
6610 DECLARE_RTL_COND(rtl_rxtx_empty_cond)
6611 {
6612         return (RTL_R8(tp, MCU) & RXTX_EMPTY) == RXTX_EMPTY;
6613 }
6614
6615 static int r8169_mdio_read_reg(struct mii_bus *mii_bus, int phyaddr, int phyreg)
6616 {
6617         struct rtl8169_private *tp = mii_bus->priv;
6618
6619         if (phyaddr > 0)
6620                 return -ENODEV;
6621
6622         return rtl_readphy(tp, phyreg);
6623 }
6624
6625 static int r8169_mdio_write_reg(struct mii_bus *mii_bus, int phyaddr,
6626                                 int phyreg, u16 val)
6627 {
6628         struct rtl8169_private *tp = mii_bus->priv;
6629
6630         if (phyaddr > 0)
6631                 return -ENODEV;
6632
6633         rtl_writephy(tp, phyreg, val);
6634
6635         return 0;
6636 }
6637
6638 static int r8169_mdio_register(struct rtl8169_private *tp)
6639 {
6640         struct pci_dev *pdev = tp->pci_dev;
6641         struct mii_bus *new_bus;
6642         int ret;
6643
6644         new_bus = devm_mdiobus_alloc(&pdev->dev);
6645         if (!new_bus)
6646                 return -ENOMEM;
6647
6648         new_bus->name = "r8169";
6649         new_bus->priv = tp;
6650         new_bus->parent = &pdev->dev;
6651         new_bus->irq[0] = PHY_IGNORE_INTERRUPT;
6652         snprintf(new_bus->id, MII_BUS_ID_SIZE, "r8169-%x", pci_dev_id(pdev));
6653
6654         new_bus->read = r8169_mdio_read_reg;
6655         new_bus->write = r8169_mdio_write_reg;
6656
6657         ret = mdiobus_register(new_bus);
6658         if (ret)
6659                 return ret;
6660
6661         tp->phydev = mdiobus_get_phy(new_bus, 0);
6662         if (!tp->phydev) {
6663                 mdiobus_unregister(new_bus);
6664                 return -ENODEV;
6665         }
6666
6667         /* PHY will be woken up in rtl_open() */
6668         phy_suspend(tp->phydev);
6669
6670         return 0;
6671 }
6672
6673 static void rtl_hw_init_8168g(struct rtl8169_private *tp)
6674 {
6675         u32 data;
6676
6677         tp->ocp_base = OCP_STD_PHY_BASE;
6678
6679         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN);
6680
6681         if (!rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42))
6682                 return;
6683
6684         if (!rtl_udelay_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42))
6685                 return;
6686
6687         RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
6688         msleep(1);
6689         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
6690
6691         data = r8168_mac_ocp_read(tp, 0xe8de);
6692         data &= ~(1 << 14);
6693         r8168_mac_ocp_write(tp, 0xe8de, data);
6694
6695         if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
6696                 return;
6697
6698         data = r8168_mac_ocp_read(tp, 0xe8de);
6699         data |= (1 << 15);
6700         r8168_mac_ocp_write(tp, 0xe8de, data);
6701
6702         rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42);
6703 }
6704
6705 static void rtl_hw_initialize(struct rtl8169_private *tp)
6706 {
6707         switch (tp->mac_version) {
6708         case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_51:
6709                 rtl8168ep_stop_cmac(tp);
6710                 /* fall through */
6711         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_48:
6712                 rtl_hw_init_8168g(tp);
6713                 break;
6714         default:
6715                 break;
6716         }
6717 }
6718
6719 static int rtl_jumbo_max(struct rtl8169_private *tp)
6720 {
6721         /* Non-GBit versions don't support jumbo frames */
6722         if (!tp->supports_gmii)
6723                 return JUMBO_1K;
6724
6725         switch (tp->mac_version) {
6726         /* RTL8169 */
6727         case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
6728                 return JUMBO_7K;
6729         /* RTL8168b */
6730         case RTL_GIGA_MAC_VER_11:
6731         case RTL_GIGA_MAC_VER_12:
6732         case RTL_GIGA_MAC_VER_17:
6733                 return JUMBO_4K;
6734         /* RTL8168c */
6735         case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
6736                 return JUMBO_6K;
6737         default:
6738                 return JUMBO_9K;
6739         }
6740 }
6741
6742 static void rtl_disable_clk(void *data)
6743 {
6744         clk_disable_unprepare(data);
6745 }
6746
6747 static int rtl_get_ether_clk(struct rtl8169_private *tp)
6748 {
6749         struct device *d = tp_to_dev(tp);
6750         struct clk *clk;
6751         int rc;
6752
6753         clk = devm_clk_get(d, "ether_clk");
6754         if (IS_ERR(clk)) {
6755                 rc = PTR_ERR(clk);
6756                 if (rc == -ENOENT)
6757                         /* clk-core allows NULL (for suspend / resume) */
6758                         rc = 0;
6759                 else if (rc != -EPROBE_DEFER)
6760                         dev_err(d, "failed to get clk: %d\n", rc);
6761         } else {
6762                 tp->clk = clk;
6763                 rc = clk_prepare_enable(clk);
6764                 if (rc)
6765                         dev_err(d, "failed to enable clk: %d\n", rc);
6766                 else
6767                         rc = devm_add_action_or_reset(d, rtl_disable_clk, clk);
6768         }
6769
6770         return rc;
6771 }
6772
6773 static void rtl_init_mac_address(struct rtl8169_private *tp)
6774 {
6775         struct net_device *dev = tp->dev;
6776         u8 *mac_addr = dev->dev_addr;
6777         int rc, i;
6778
6779         rc = eth_platform_get_mac_address(tp_to_dev(tp), mac_addr);
6780         if (!rc)
6781                 goto done;
6782
6783         rtl_read_mac_address(tp, mac_addr);
6784         if (is_valid_ether_addr(mac_addr))
6785                 goto done;
6786
6787         for (i = 0; i < ETH_ALEN; i++)
6788                 mac_addr[i] = RTL_R8(tp, MAC0 + i);
6789         if (is_valid_ether_addr(mac_addr))
6790                 goto done;
6791
6792         eth_hw_addr_random(dev);
6793         dev_warn(tp_to_dev(tp), "can't read MAC address, setting random one\n");
6794 done:
6795         rtl_rar_set(tp, mac_addr);
6796 }
6797
6798 static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
6799 {
6800         struct rtl8169_private *tp;
6801         struct net_device *dev;
6802         int chipset, region;
6803         int jumbo_max, rc;
6804
6805         dev = devm_alloc_etherdev(&pdev->dev, sizeof (*tp));
6806         if (!dev)
6807                 return -ENOMEM;
6808
6809         SET_NETDEV_DEV(dev, &pdev->dev);
6810         dev->netdev_ops = &rtl_netdev_ops;
6811         tp = netdev_priv(dev);
6812         tp->dev = dev;
6813         tp->pci_dev = pdev;
6814         tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
6815         tp->supports_gmii = ent->driver_data == RTL_CFG_NO_GBIT ? 0 : 1;
6816
6817         /* Get the *optional* external "ether_clk" used on some boards */
6818         rc = rtl_get_ether_clk(tp);
6819         if (rc)
6820                 return rc;
6821
6822         /* Disable ASPM completely as that cause random device stop working
6823          * problems as well as full system hangs for some PCIe devices users.
6824          */
6825         rc = pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S |
6826                                           PCIE_LINK_STATE_L1);
6827         tp->aspm_manageable = !rc;
6828
6829         /* enable device (incl. PCI PM wakeup and hotplug setup) */
6830         rc = pcim_enable_device(pdev);
6831         if (rc < 0) {
6832                 dev_err(&pdev->dev, "enable failure\n");
6833                 return rc;
6834         }
6835
6836         if (pcim_set_mwi(pdev) < 0)
6837                 dev_info(&pdev->dev, "Mem-Wr-Inval unavailable\n");
6838
6839         /* use first MMIO region */
6840         region = ffs(pci_select_bars(pdev, IORESOURCE_MEM)) - 1;
6841         if (region < 0) {
6842                 dev_err(&pdev->dev, "no MMIO resource found\n");
6843                 return -ENODEV;
6844         }
6845
6846         /* check for weird/broken PCI region reporting */
6847         if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
6848                 dev_err(&pdev->dev, "Invalid PCI region size(s), aborting\n");
6849                 return -ENODEV;
6850         }
6851
6852         rc = pcim_iomap_regions(pdev, BIT(region), MODULENAME);
6853         if (rc < 0) {
6854                 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
6855                 return rc;
6856         }
6857
6858         tp->mmio_addr = pcim_iomap_table(pdev)[region];
6859
6860         /* Identify chip attached to board */
6861         rtl8169_get_mac_version(tp);
6862         if (tp->mac_version == RTL_GIGA_MAC_NONE)
6863                 return -ENODEV;
6864
6865         tp->cp_cmd = RTL_R16(tp, CPlusCmd);
6866
6867         if (sizeof(dma_addr_t) > 4 && tp->mac_version >= RTL_GIGA_MAC_VER_18 &&
6868             !dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)))
6869                 dev->features |= NETIF_F_HIGHDMA;
6870
6871         rtl_init_rxcfg(tp);
6872
6873         rtl8169_irq_mask_and_ack(tp);
6874
6875         rtl_hw_initialize(tp);
6876
6877         rtl_hw_reset(tp);
6878
6879         pci_set_master(pdev);
6880
6881         chipset = tp->mac_version;
6882
6883         rc = rtl_alloc_irq(tp);
6884         if (rc < 0) {
6885                 dev_err(&pdev->dev, "Can't allocate interrupt\n");
6886                 return rc;
6887         }
6888
6889         mutex_init(&tp->wk.mutex);
6890         INIT_WORK(&tp->wk.work, rtl_task);
6891         u64_stats_init(&tp->rx_stats.syncp);
6892         u64_stats_init(&tp->tx_stats.syncp);
6893
6894         rtl_init_mac_address(tp);
6895
6896         dev->ethtool_ops = &rtl8169_ethtool_ops;
6897
6898         netif_napi_add(dev, &tp->napi, rtl8169_poll, NAPI_POLL_WEIGHT);
6899
6900         /* don't enable SG, IP_CSUM and TSO by default - it might not work
6901          * properly for all devices */
6902         dev->features |= NETIF_F_RXCSUM |
6903                 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
6904
6905         dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
6906                 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_TX |
6907                 NETIF_F_HW_VLAN_CTAG_RX;
6908         dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
6909                 NETIF_F_HIGHDMA;
6910         dev->priv_flags |= IFF_LIVE_ADDR_CHANGE;
6911
6912         tp->cp_cmd |= RxChkSum | RxVlan;
6913
6914         /*
6915          * Pretend we are using VLANs; This bypasses a nasty bug where
6916          * Interrupts stop flowing on high load on 8110SCd controllers.
6917          */
6918         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
6919                 /* Disallow toggling */
6920                 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX;
6921
6922         if (rtl_chip_supports_csum_v2(tp))
6923                 dev->hw_features |= NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
6924
6925         dev->hw_features |= NETIF_F_RXALL;
6926         dev->hw_features |= NETIF_F_RXFCS;
6927
6928         /* MTU range: 60 - hw-specific max */
6929         dev->min_mtu = ETH_ZLEN;
6930         jumbo_max = rtl_jumbo_max(tp);
6931         dev->max_mtu = jumbo_max;
6932
6933         rtl_set_irq_mask(tp);
6934
6935         tp->fw_name = rtl_chip_infos[chipset].fw_name;
6936
6937         tp->counters = dmam_alloc_coherent (&pdev->dev, sizeof(*tp->counters),
6938                                             &tp->counters_phys_addr,
6939                                             GFP_KERNEL);
6940         if (!tp->counters)
6941                 return -ENOMEM;
6942
6943         pci_set_drvdata(pdev, dev);
6944
6945         rc = r8169_mdio_register(tp);
6946         if (rc)
6947                 return rc;
6948
6949         /* chip gets powered up in rtl_open() */
6950         rtl_pll_power_down(tp);
6951
6952         rc = register_netdev(dev);
6953         if (rc)
6954                 goto err_mdio_unregister;
6955
6956         netif_info(tp, probe, dev, "%s, %pM, XID %03x, IRQ %d\n",
6957                    rtl_chip_infos[chipset].name, dev->dev_addr,
6958                    (RTL_R32(tp, TxConfig) >> 20) & 0xfcf,
6959                    pci_irq_vector(pdev, 0));
6960
6961         if (jumbo_max > JUMBO_1K)
6962                 netif_info(tp, probe, dev,
6963                            "jumbo features [frames: %d bytes, tx checksumming: %s]\n",
6964                            jumbo_max, tp->mac_version <= RTL_GIGA_MAC_VER_06 ?
6965                            "ok" : "ko");
6966
6967         if (r8168_check_dash(tp))
6968                 rtl8168_driver_start(tp);
6969
6970         if (pci_dev_run_wake(pdev))
6971                 pm_runtime_put_sync(&pdev->dev);
6972
6973         return 0;
6974
6975 err_mdio_unregister:
6976         mdiobus_unregister(tp->phydev->mdio.bus);
6977         return rc;
6978 }
6979
6980 static struct pci_driver rtl8169_pci_driver = {
6981         .name           = MODULENAME,
6982         .id_table       = rtl8169_pci_tbl,
6983         .probe          = rtl_init_one,
6984         .remove         = rtl_remove_one,
6985         .shutdown       = rtl_shutdown,
6986         .driver.pm      = RTL8169_PM_OPS,
6987 };
6988
6989 module_pci_driver(rtl8169_pci_driver);