1 // SPDX-License-Identifier: GPL-2.0-only
3 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
5 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
6 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
7 * Copyright (c) a lot of people too. Please respect their work.
9 * See MAINTAINERS file for support contact information.
12 #include <linux/module.h>
13 #include <linux/moduleparam.h>
14 #include <linux/pci.h>
15 #include <linux/netdevice.h>
16 #include <linux/etherdevice.h>
17 #include <linux/clk.h>
18 #include <linux/delay.h>
19 #include <linux/ethtool.h>
20 #include <linux/phy.h>
21 #include <linux/if_vlan.h>
22 #include <linux/crc32.h>
26 #include <linux/tcp.h>
27 #include <linux/interrupt.h>
28 #include <linux/dma-mapping.h>
29 #include <linux/pm_runtime.h>
30 #include <linux/firmware.h>
31 #include <linux/prefetch.h>
32 #include <linux/pci-aspm.h>
33 #include <linux/ipv6.h>
34 #include <net/ip6_checksum.h>
36 #define MODULENAME "r8169"
38 #define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
39 #define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
40 #define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw"
41 #define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw"
42 #define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw"
43 #define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw"
44 #define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw"
45 #define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw"
46 #define FIRMWARE_8402_1 "rtl_nic/rtl8402-1.fw"
47 #define FIRMWARE_8411_1 "rtl_nic/rtl8411-1.fw"
48 #define FIRMWARE_8411_2 "rtl_nic/rtl8411-2.fw"
49 #define FIRMWARE_8106E_1 "rtl_nic/rtl8106e-1.fw"
50 #define FIRMWARE_8106E_2 "rtl_nic/rtl8106e-2.fw"
51 #define FIRMWARE_8168G_2 "rtl_nic/rtl8168g-2.fw"
52 #define FIRMWARE_8168G_3 "rtl_nic/rtl8168g-3.fw"
53 #define FIRMWARE_8168H_1 "rtl_nic/rtl8168h-1.fw"
54 #define FIRMWARE_8168H_2 "rtl_nic/rtl8168h-2.fw"
55 #define FIRMWARE_8107E_1 "rtl_nic/rtl8107e-1.fw"
56 #define FIRMWARE_8107E_2 "rtl_nic/rtl8107e-2.fw"
58 #define R8169_MSG_DEFAULT \
59 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
61 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
62 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
63 static const int multicast_filter_limit = 32;
65 #define TX_DMA_BURST 7 /* Maximum PCI burst, '7' is unlimited */
66 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
68 #define R8169_REGS_SIZE 256
69 #define R8169_RX_BUF_SIZE (SZ_16K - 1)
70 #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
71 #define NUM_RX_DESC 256U /* Number of Rx descriptor registers */
72 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
73 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
75 /* write/read MMIO register */
76 #define RTL_W8(tp, reg, val8) writeb((val8), tp->mmio_addr + (reg))
77 #define RTL_W16(tp, reg, val16) writew((val16), tp->mmio_addr + (reg))
78 #define RTL_W32(tp, reg, val32) writel((val32), tp->mmio_addr + (reg))
79 #define RTL_R8(tp, reg) readb(tp->mmio_addr + (reg))
80 #define RTL_R16(tp, reg) readw(tp->mmio_addr + (reg))
81 #define RTL_R32(tp, reg) readl(tp->mmio_addr + (reg))
84 /* support for ancient RTL_GIGA_MAC_VER_01 has been removed */
138 #define JUMBO_1K ETH_DATA_LEN
139 #define JUMBO_4K (4*1024 - ETH_HLEN - 2)
140 #define JUMBO_6K (6*1024 - ETH_HLEN - 2)
141 #define JUMBO_7K (7*1024 - ETH_HLEN - 2)
142 #define JUMBO_9K (9*1024 - ETH_HLEN - 2)
144 static const struct {
147 } rtl_chip_infos[] = {
149 [RTL_GIGA_MAC_VER_02] = {"RTL8169s" },
150 [RTL_GIGA_MAC_VER_03] = {"RTL8110s" },
151 [RTL_GIGA_MAC_VER_04] = {"RTL8169sb/8110sb" },
152 [RTL_GIGA_MAC_VER_05] = {"RTL8169sc/8110sc" },
153 [RTL_GIGA_MAC_VER_06] = {"RTL8169sc/8110sc" },
155 [RTL_GIGA_MAC_VER_07] = {"RTL8102e" },
156 [RTL_GIGA_MAC_VER_08] = {"RTL8102e" },
157 [RTL_GIGA_MAC_VER_09] = {"RTL8102e" },
158 [RTL_GIGA_MAC_VER_10] = {"RTL8101e" },
159 [RTL_GIGA_MAC_VER_11] = {"RTL8168b/8111b" },
160 [RTL_GIGA_MAC_VER_12] = {"RTL8168b/8111b" },
161 [RTL_GIGA_MAC_VER_13] = {"RTL8101e" },
162 [RTL_GIGA_MAC_VER_14] = {"RTL8100e" },
163 [RTL_GIGA_MAC_VER_15] = {"RTL8100e" },
164 [RTL_GIGA_MAC_VER_16] = {"RTL8101e" },
165 [RTL_GIGA_MAC_VER_17] = {"RTL8168b/8111b" },
166 [RTL_GIGA_MAC_VER_18] = {"RTL8168cp/8111cp" },
167 [RTL_GIGA_MAC_VER_19] = {"RTL8168c/8111c" },
168 [RTL_GIGA_MAC_VER_20] = {"RTL8168c/8111c" },
169 [RTL_GIGA_MAC_VER_21] = {"RTL8168c/8111c" },
170 [RTL_GIGA_MAC_VER_22] = {"RTL8168c/8111c" },
171 [RTL_GIGA_MAC_VER_23] = {"RTL8168cp/8111cp" },
172 [RTL_GIGA_MAC_VER_24] = {"RTL8168cp/8111cp" },
173 [RTL_GIGA_MAC_VER_25] = {"RTL8168d/8111d", FIRMWARE_8168D_1},
174 [RTL_GIGA_MAC_VER_26] = {"RTL8168d/8111d", FIRMWARE_8168D_2},
175 [RTL_GIGA_MAC_VER_27] = {"RTL8168dp/8111dp" },
176 [RTL_GIGA_MAC_VER_28] = {"RTL8168dp/8111dp" },
177 [RTL_GIGA_MAC_VER_29] = {"RTL8105e", FIRMWARE_8105E_1},
178 [RTL_GIGA_MAC_VER_30] = {"RTL8105e", FIRMWARE_8105E_1},
179 [RTL_GIGA_MAC_VER_31] = {"RTL8168dp/8111dp" },
180 [RTL_GIGA_MAC_VER_32] = {"RTL8168e/8111e", FIRMWARE_8168E_1},
181 [RTL_GIGA_MAC_VER_33] = {"RTL8168e/8111e", FIRMWARE_8168E_2},
182 [RTL_GIGA_MAC_VER_34] = {"RTL8168evl/8111evl", FIRMWARE_8168E_3},
183 [RTL_GIGA_MAC_VER_35] = {"RTL8168f/8111f", FIRMWARE_8168F_1},
184 [RTL_GIGA_MAC_VER_36] = {"RTL8168f/8111f", FIRMWARE_8168F_2},
185 [RTL_GIGA_MAC_VER_37] = {"RTL8402", FIRMWARE_8402_1 },
186 [RTL_GIGA_MAC_VER_38] = {"RTL8411", FIRMWARE_8411_1 },
187 [RTL_GIGA_MAC_VER_39] = {"RTL8106e", FIRMWARE_8106E_1},
188 [RTL_GIGA_MAC_VER_40] = {"RTL8168g/8111g", FIRMWARE_8168G_2},
189 [RTL_GIGA_MAC_VER_41] = {"RTL8168g/8111g" },
190 [RTL_GIGA_MAC_VER_42] = {"RTL8168g/8111g", FIRMWARE_8168G_3},
191 [RTL_GIGA_MAC_VER_43] = {"RTL8106e", FIRMWARE_8106E_2},
192 [RTL_GIGA_MAC_VER_44] = {"RTL8411", FIRMWARE_8411_2 },
193 [RTL_GIGA_MAC_VER_45] = {"RTL8168h/8111h", FIRMWARE_8168H_1},
194 [RTL_GIGA_MAC_VER_46] = {"RTL8168h/8111h", FIRMWARE_8168H_2},
195 [RTL_GIGA_MAC_VER_47] = {"RTL8107e", FIRMWARE_8107E_1},
196 [RTL_GIGA_MAC_VER_48] = {"RTL8107e", FIRMWARE_8107E_2},
197 [RTL_GIGA_MAC_VER_49] = {"RTL8168ep/8111ep" },
198 [RTL_GIGA_MAC_VER_50] = {"RTL8168ep/8111ep" },
199 [RTL_GIGA_MAC_VER_51] = {"RTL8168ep/8111ep" },
208 static const struct pci_device_id rtl8169_pci_tbl[] = {
209 { PCI_VDEVICE(REALTEK, 0x2502), RTL_CFG_1 },
210 { PCI_VDEVICE(REALTEK, 0x2600), RTL_CFG_1 },
211 { PCI_VDEVICE(REALTEK, 0x8129), RTL_CFG_0 },
212 { PCI_VDEVICE(REALTEK, 0x8136), RTL_CFG_2 },
213 { PCI_VDEVICE(REALTEK, 0x8161), RTL_CFG_1 },
214 { PCI_VDEVICE(REALTEK, 0x8167), RTL_CFG_0 },
215 { PCI_VDEVICE(REALTEK, 0x8168), RTL_CFG_1 },
216 { PCI_VDEVICE(NCUBE, 0x8168), RTL_CFG_1 },
217 { PCI_VDEVICE(REALTEK, 0x8169), RTL_CFG_0 },
218 { PCI_VENDOR_ID_DLINK, 0x4300,
219 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0, RTL_CFG_1 },
220 { PCI_VDEVICE(DLINK, 0x4300), RTL_CFG_0 },
221 { PCI_VDEVICE(DLINK, 0x4302), RTL_CFG_0 },
222 { PCI_VDEVICE(AT, 0xc107), RTL_CFG_0 },
223 { PCI_VDEVICE(USR, 0x0116), RTL_CFG_0 },
224 { PCI_VENDOR_ID_LINKSYS, 0x1032,
225 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
227 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
231 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
238 MAC0 = 0, /* Ethernet hardware address. */
240 MAR0 = 8, /* Multicast filter. */
241 CounterAddrLow = 0x10,
242 CounterAddrHigh = 0x14,
243 TxDescStartAddrLow = 0x20,
244 TxDescStartAddrHigh = 0x24,
245 TxHDescStartAddrLow = 0x28,
246 TxHDescStartAddrHigh = 0x2c,
255 #define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */
256 #define TXCFG_EMPTY (1 << 11) /* 8111e-vl */
259 #define RX128_INT_EN (1 << 15) /* 8111c and later */
260 #define RX_MULTI_EN (1 << 14) /* 8111c only */
261 #define RXCFG_FIFO_SHIFT 13
262 /* No threshold before first PCI xfer */
263 #define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT)
264 #define RX_EARLY_OFF (1 << 11)
265 #define RXCFG_DMA_SHIFT 8
266 /* Unlimited maximum PCI burst. */
267 #define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT)
274 #define PME_SIGNAL (1 << 5) /* 8168c and later */
286 #define RTL_COALESCE_MASK 0x0f
287 #define RTL_COALESCE_SHIFT 4
288 #define RTL_COALESCE_T_MAX (RTL_COALESCE_MASK)
289 #define RTL_COALESCE_FRAME_MAX (RTL_COALESCE_MASK << 2)
291 RxDescAddrLow = 0xe4,
292 RxDescAddrHigh = 0xe8,
293 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */
295 #define NoEarlyTx 0x3f /* Max value : no early transmit. */
297 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
299 #define TxPacketMax (8064 >> 7)
300 #define EarlySize 0x27
303 FuncEventMask = 0xf4,
304 FuncPresetState = 0xf8,
309 FuncForceEvent = 0xfc,
312 enum rtl8168_8101_registers {
315 #define CSIAR_FLAG 0x80000000
316 #define CSIAR_WRITE_CMD 0x80000000
317 #define CSIAR_BYTE_ENABLE 0x0000f000
318 #define CSIAR_ADDR_MASK 0x00000fff
321 #define EPHYAR_FLAG 0x80000000
322 #define EPHYAR_WRITE_CMD 0x80000000
323 #define EPHYAR_REG_MASK 0x1f
324 #define EPHYAR_REG_SHIFT 16
325 #define EPHYAR_DATA_MASK 0xffff
327 #define PFM_EN (1 << 6)
328 #define TX_10M_PS_EN (1 << 7)
330 #define FIX_NAK_1 (1 << 4)
331 #define FIX_NAK_2 (1 << 3)
334 #define NOW_IS_OOB (1 << 7)
335 #define TX_EMPTY (1 << 5)
336 #define RX_EMPTY (1 << 4)
337 #define RXTX_EMPTY (TX_EMPTY | RX_EMPTY)
338 #define EN_NDP (1 << 3)
339 #define EN_OOB_RESET (1 << 2)
340 #define LINK_LIST_RDY (1 << 1)
342 #define EFUSEAR_FLAG 0x80000000
343 #define EFUSEAR_WRITE_CMD 0x80000000
344 #define EFUSEAR_READ_CMD 0x00000000
345 #define EFUSEAR_REG_MASK 0x03ff
346 #define EFUSEAR_REG_SHIFT 8
347 #define EFUSEAR_DATA_MASK 0xff
349 #define PFM_D3COLD_EN (1 << 6)
352 enum rtl8168_registers {
357 #define ERIAR_FLAG 0x80000000
358 #define ERIAR_WRITE_CMD 0x80000000
359 #define ERIAR_READ_CMD 0x00000000
360 #define ERIAR_ADDR_BYTE_ALIGN 4
361 #define ERIAR_TYPE_SHIFT 16
362 #define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT)
363 #define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT)
364 #define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT)
365 #define ERIAR_OOB (0x02 << ERIAR_TYPE_SHIFT)
366 #define ERIAR_MASK_SHIFT 12
367 #define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT)
368 #define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT)
369 #define ERIAR_MASK_0100 (0x4 << ERIAR_MASK_SHIFT)
370 #define ERIAR_MASK_0101 (0x5 << ERIAR_MASK_SHIFT)
371 #define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT)
372 EPHY_RXER_NUM = 0x7c,
373 OCPDR = 0xb0, /* OCP GPHY access */
374 #define OCPDR_WRITE_CMD 0x80000000
375 #define OCPDR_READ_CMD 0x00000000
376 #define OCPDR_REG_MASK 0x7f
377 #define OCPDR_GPHY_REG_SHIFT 16
378 #define OCPDR_DATA_MASK 0xffff
380 #define OCPAR_FLAG 0x80000000
381 #define OCPAR_GPHY_WRITE_CMD 0x8000f060
382 #define OCPAR_GPHY_READ_CMD 0x0000f060
384 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */
385 MISC = 0xf0, /* 8168e only. */
386 #define TXPLA_RST (1 << 29)
387 #define DISABLE_LAN_EN (1 << 23) /* Enable GPIO pin */
388 #define PWM_EN (1 << 22)
389 #define RXDV_GATED_EN (1 << 19)
390 #define EARLY_TALLY_EN (1 << 16)
393 enum rtl_register_content {
394 /* InterruptStatusBits */
398 TxDescUnavail = 0x0080,
420 /* TXPoll register p.5 */
421 HPQ = 0x80, /* Poll cmd on the high prio queue */
422 NPQ = 0x40, /* Poll cmd on the low prio queue */
423 FSWInt = 0x01, /* Forced software interrupt */
427 Cfg9346_Unlock = 0xc0,
432 AcceptBroadcast = 0x08,
433 AcceptMulticast = 0x04,
435 AcceptAllPhys = 0x01,
436 #define RX_CONFIG_ACCEPT_MASK 0x3f
439 TxInterFrameGapShift = 24,
440 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
442 /* Config1 register p.24 */
445 Speed_down = (1 << 4),
449 PMEnable = (1 << 0), /* Power Management Enable */
451 /* Config2 register p. 25 */
452 ClkReqEn = (1 << 7), /* Clock Request Enable */
453 MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */
454 PCI_Clock_66MHz = 0x01,
455 PCI_Clock_33MHz = 0x00,
457 /* Config3 register p.25 */
458 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
459 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
460 Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */
461 Rdy_to_L23 = (1 << 1), /* L23 Enable */
462 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
464 /* Config4 register */
465 Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */
467 /* Config5 register p.27 */
468 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
469 MWF = (1 << 5), /* Accept Multicast wakeup frame */
470 UWF = (1 << 4), /* Accept Unicast wakeup frame */
472 LanWake = (1 << 1), /* LanWake enable/disable */
473 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
474 ASPM_en = (1 << 0), /* ASPM enable */
477 EnableBist = (1 << 15), // 8168 8101
478 Mac_dbgo_oe = (1 << 14), // 8168 8101
479 Normal_mode = (1 << 13), // unused
480 Force_half_dup = (1 << 12), // 8168 8101
481 Force_rxflow_en = (1 << 11), // 8168 8101
482 Force_txflow_en = (1 << 10), // 8168 8101
483 Cxpl_dbg_sel = (1 << 9), // 8168 8101
484 ASF = (1 << 8), // 8168 8101
485 PktCntrDisable = (1 << 7), // 8168 8101
486 Mac_dbgo_sel = 0x001c, // 8168
491 #define INTT_MASK GENMASK(1, 0)
493 /* rtl8169_PHYstatus */
503 /* ResetCounterCommand */
506 /* DumpCounterCommand */
509 /* magic enable v2 */
510 MagicPacket_v2 = (1 << 16), /* Wake up when receives a Magic Packet */
514 /* First doubleword. */
515 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
516 RingEnd = (1 << 30), /* End of descriptor ring */
517 FirstFrag = (1 << 29), /* First segment of a packet */
518 LastFrag = (1 << 28), /* Final segment of a packet */
522 enum rtl_tx_desc_bit {
523 /* First doubleword. */
524 TD_LSO = (1 << 27), /* Large Send Offload */
525 #define TD_MSS_MAX 0x07ffu /* MSS value */
527 /* Second doubleword. */
528 TxVlanTag = (1 << 17), /* Add VLAN tag */
531 /* 8169, 8168b and 810x except 8102e. */
532 enum rtl_tx_desc_bit_0 {
533 /* First doubleword. */
534 #define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */
535 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */
536 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */
537 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */
540 /* 8102e, 8168c and beyond. */
541 enum rtl_tx_desc_bit_1 {
542 /* First doubleword. */
543 TD1_GTSENV4 = (1 << 26), /* Giant Send for IPv4 */
544 TD1_GTSENV6 = (1 << 25), /* Giant Send for IPv6 */
545 #define GTTCPHO_SHIFT 18
546 #define GTTCPHO_MAX 0x7fU
548 /* Second doubleword. */
549 #define TCPHO_SHIFT 18
550 #define TCPHO_MAX 0x3ffU
551 #define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */
552 TD1_IPv6_CS = (1 << 28), /* Calculate IPv6 checksum */
553 TD1_IPv4_CS = (1 << 29), /* Calculate IPv4 checksum */
554 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */
555 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */
558 enum rtl_rx_desc_bit {
560 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
561 PID0 = (1 << 17), /* Protocol ID bit 0/2 */
563 #define RxProtoUDP (PID1)
564 #define RxProtoTCP (PID0)
565 #define RxProtoIP (PID1 | PID0)
566 #define RxProtoMask RxProtoIP
568 IPFail = (1 << 16), /* IP checksum failed */
569 UDPFail = (1 << 15), /* UDP/IP checksum failed */
570 TCPFail = (1 << 14), /* TCP/IP checksum failed */
571 RxVlanTag = (1 << 16), /* VLAN tag available */
574 #define RsvdMask 0x3fffc000
575 #define CPCMD_QUIRK_MASK (Normal_mode | RxVlan | RxChkSum | INTT_MASK)
594 struct rtl8169_counters {
601 __le32 tx_one_collision;
602 __le32 tx_multi_collision;
610 struct rtl8169_tc_offsets {
613 __le32 tx_multi_collision;
618 RTL_FLAG_TASK_ENABLED = 0,
619 RTL_FLAG_TASK_RESET_PENDING,
623 struct rtl8169_stats {
626 struct u64_stats_sync syncp;
629 struct rtl8169_private;
630 typedef void (*rtl_fw_write_t)(struct rtl8169_private *tp, int reg, int val);
631 typedef int (*rtl_fw_read_t)(struct rtl8169_private *tp, int reg);
633 struct rtl8169_private {
634 void __iomem *mmio_addr; /* memory map physical address */
635 struct pci_dev *pci_dev;
636 struct net_device *dev;
637 struct phy_device *phydev;
638 struct napi_struct napi;
640 enum mac_version mac_version;
641 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
642 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
644 struct rtl8169_stats rx_stats;
645 struct rtl8169_stats tx_stats;
646 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
647 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
648 dma_addr_t TxPhyAddr;
649 dma_addr_t RxPhyAddr;
650 void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
651 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
655 const struct rtl_coalesce_info *coalesce_info;
658 void (*hw_start)(struct rtl8169_private *tp);
661 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
663 struct work_struct work;
666 unsigned irq_enabled:1;
667 unsigned supports_gmii:1;
668 dma_addr_t counters_phys_addr;
669 struct rtl8169_counters *counters;
670 struct rtl8169_tc_offsets tc_offset;
675 rtl_fw_write_t phy_write;
676 rtl_fw_read_t phy_read;
677 rtl_fw_write_t mac_mcu_write;
678 rtl_fw_read_t mac_mcu_read;
679 const struct firmware *fw;
683 #define RTL_VER_SIZE 32
685 char version[RTL_VER_SIZE];
687 struct rtl_fw_phy_action {
696 typedef void (*rtl_generic_fct)(struct rtl8169_private *tp);
698 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
699 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
700 module_param_named(debug, debug.msg_enable, int, 0);
701 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
702 MODULE_SOFTDEP("pre: realtek");
703 MODULE_LICENSE("GPL");
704 MODULE_FIRMWARE(FIRMWARE_8168D_1);
705 MODULE_FIRMWARE(FIRMWARE_8168D_2);
706 MODULE_FIRMWARE(FIRMWARE_8168E_1);
707 MODULE_FIRMWARE(FIRMWARE_8168E_2);
708 MODULE_FIRMWARE(FIRMWARE_8168E_3);
709 MODULE_FIRMWARE(FIRMWARE_8105E_1);
710 MODULE_FIRMWARE(FIRMWARE_8168F_1);
711 MODULE_FIRMWARE(FIRMWARE_8168F_2);
712 MODULE_FIRMWARE(FIRMWARE_8402_1);
713 MODULE_FIRMWARE(FIRMWARE_8411_1);
714 MODULE_FIRMWARE(FIRMWARE_8411_2);
715 MODULE_FIRMWARE(FIRMWARE_8106E_1);
716 MODULE_FIRMWARE(FIRMWARE_8106E_2);
717 MODULE_FIRMWARE(FIRMWARE_8168G_2);
718 MODULE_FIRMWARE(FIRMWARE_8168G_3);
719 MODULE_FIRMWARE(FIRMWARE_8168H_1);
720 MODULE_FIRMWARE(FIRMWARE_8168H_2);
721 MODULE_FIRMWARE(FIRMWARE_8107E_1);
722 MODULE_FIRMWARE(FIRMWARE_8107E_2);
724 static inline struct device *tp_to_dev(struct rtl8169_private *tp)
726 return &tp->pci_dev->dev;
729 static void rtl_lock_work(struct rtl8169_private *tp)
731 mutex_lock(&tp->wk.mutex);
734 static void rtl_unlock_work(struct rtl8169_private *tp)
736 mutex_unlock(&tp->wk.mutex);
739 static void rtl_lock_config_regs(struct rtl8169_private *tp)
741 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
744 static void rtl_unlock_config_regs(struct rtl8169_private *tp)
746 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
749 static void rtl_tx_performance_tweak(struct rtl8169_private *tp, u16 force)
751 pcie_capability_clear_and_set_word(tp->pci_dev, PCI_EXP_DEVCTL,
752 PCI_EXP_DEVCTL_READRQ, force);
756 bool (*check)(struct rtl8169_private *);
760 static void rtl_udelay(unsigned int d)
765 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,
766 void (*delay)(unsigned int), unsigned int d, int n,
771 for (i = 0; i < n; i++) {
772 if (c->check(tp) == high)
776 netif_err(tp, drv, tp->dev, "%s == %d (loop: %d, delay: %d).\n",
777 c->msg, !high, n, d);
781 static bool rtl_udelay_loop_wait_high(struct rtl8169_private *tp,
782 const struct rtl_cond *c,
783 unsigned int d, int n)
785 return rtl_loop_wait(tp, c, rtl_udelay, d, n, true);
788 static bool rtl_udelay_loop_wait_low(struct rtl8169_private *tp,
789 const struct rtl_cond *c,
790 unsigned int d, int n)
792 return rtl_loop_wait(tp, c, rtl_udelay, d, n, false);
795 static bool rtl_msleep_loop_wait_high(struct rtl8169_private *tp,
796 const struct rtl_cond *c,
797 unsigned int d, int n)
799 return rtl_loop_wait(tp, c, msleep, d, n, true);
802 static bool rtl_msleep_loop_wait_low(struct rtl8169_private *tp,
803 const struct rtl_cond *c,
804 unsigned int d, int n)
806 return rtl_loop_wait(tp, c, msleep, d, n, false);
809 #define DECLARE_RTL_COND(name) \
810 static bool name ## _check(struct rtl8169_private *); \
812 static const struct rtl_cond name = { \
813 .check = name ## _check, \
817 static bool name ## _check(struct rtl8169_private *tp)
819 static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg)
821 if (reg & 0xffff0001) {
822 netif_err(tp, drv, tp->dev, "Invalid ocp reg %x!\n", reg);
828 DECLARE_RTL_COND(rtl_ocp_gphy_cond)
830 return RTL_R32(tp, GPHY_OCP) & OCPAR_FLAG;
833 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
835 if (rtl_ocp_reg_failure(tp, reg))
838 RTL_W32(tp, GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);
840 rtl_udelay_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);
843 static u16 r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
845 if (rtl_ocp_reg_failure(tp, reg))
848 RTL_W32(tp, GPHY_OCP, reg << 15);
850 return rtl_udelay_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?
851 (RTL_R32(tp, GPHY_OCP) & 0xffff) : ~0;
854 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
856 if (rtl_ocp_reg_failure(tp, reg))
859 RTL_W32(tp, OCPDR, OCPAR_FLAG | (reg << 15) | data);
862 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
864 if (rtl_ocp_reg_failure(tp, reg))
867 RTL_W32(tp, OCPDR, reg << 15);
869 return RTL_R32(tp, OCPDR);
872 #define OCP_STD_PHY_BASE 0xa400
874 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)
877 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;
881 if (tp->ocp_base != OCP_STD_PHY_BASE)
884 r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);
887 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)
889 if (tp->ocp_base != OCP_STD_PHY_BASE)
892 return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);
895 static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value)
898 tp->ocp_base = value << 4;
902 r8168_mac_ocp_write(tp, tp->ocp_base + reg, value);
905 static int mac_mcu_read(struct rtl8169_private *tp, int reg)
907 return r8168_mac_ocp_read(tp, tp->ocp_base + reg);
910 DECLARE_RTL_COND(rtl_phyar_cond)
912 return RTL_R32(tp, PHYAR) & 0x80000000;
915 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)
917 RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
919 rtl_udelay_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);
921 * According to hardware specs a 20us delay is required after write
922 * complete indication, but before sending next command.
927 static int r8169_mdio_read(struct rtl8169_private *tp, int reg)
931 RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16);
933 value = rtl_udelay_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?
934 RTL_R32(tp, PHYAR) & 0xffff : ~0;
937 * According to hardware specs a 20us delay is required after read
938 * complete indication, but before sending next command.
945 DECLARE_RTL_COND(rtl_ocpar_cond)
947 return RTL_R32(tp, OCPAR) & OCPAR_FLAG;
950 static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data)
952 RTL_W32(tp, OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
953 RTL_W32(tp, OCPAR, OCPAR_GPHY_WRITE_CMD);
954 RTL_W32(tp, EPHY_RXER_NUM, 0);
956 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100);
959 static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value)
961 r8168dp_1_mdio_access(tp, reg,
962 OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK));
965 static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg)
967 r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD);
970 RTL_W32(tp, OCPAR, OCPAR_GPHY_READ_CMD);
971 RTL_W32(tp, EPHY_RXER_NUM, 0);
973 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ?
974 RTL_R32(tp, OCPDR) & OCPDR_DATA_MASK : ~0;
977 #define R8168DP_1_MDIO_ACCESS_BIT 0x00020000
979 static void r8168dp_2_mdio_start(struct rtl8169_private *tp)
981 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
984 static void r8168dp_2_mdio_stop(struct rtl8169_private *tp)
986 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
989 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)
991 r8168dp_2_mdio_start(tp);
993 r8169_mdio_write(tp, reg, value);
995 r8168dp_2_mdio_stop(tp);
998 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)
1002 r8168dp_2_mdio_start(tp);
1004 value = r8169_mdio_read(tp, reg);
1006 r8168dp_2_mdio_stop(tp);
1011 static void rtl_writephy(struct rtl8169_private *tp, int location, int val)
1013 switch (tp->mac_version) {
1014 case RTL_GIGA_MAC_VER_27:
1015 r8168dp_1_mdio_write(tp, location, val);
1017 case RTL_GIGA_MAC_VER_28:
1018 case RTL_GIGA_MAC_VER_31:
1019 r8168dp_2_mdio_write(tp, location, val);
1021 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
1022 r8168g_mdio_write(tp, location, val);
1025 r8169_mdio_write(tp, location, val);
1030 static int rtl_readphy(struct rtl8169_private *tp, int location)
1032 switch (tp->mac_version) {
1033 case RTL_GIGA_MAC_VER_27:
1034 return r8168dp_1_mdio_read(tp, location);
1035 case RTL_GIGA_MAC_VER_28:
1036 case RTL_GIGA_MAC_VER_31:
1037 return r8168dp_2_mdio_read(tp, location);
1038 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
1039 return r8168g_mdio_read(tp, location);
1041 return r8169_mdio_read(tp, location);
1045 static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
1047 rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
1050 static void rtl_w0w1_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
1054 val = rtl_readphy(tp, reg_addr);
1055 rtl_writephy(tp, reg_addr, (val & ~m) | p);
1058 DECLARE_RTL_COND(rtl_ephyar_cond)
1060 return RTL_R32(tp, EPHYAR) & EPHYAR_FLAG;
1063 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)
1065 RTL_W32(tp, EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1066 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1068 rtl_udelay_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);
1073 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)
1075 RTL_W32(tp, EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1077 return rtl_udelay_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?
1078 RTL_R32(tp, EPHYAR) & EPHYAR_DATA_MASK : ~0;
1081 DECLARE_RTL_COND(rtl_eriar_cond)
1083 return RTL_R32(tp, ERIAR) & ERIAR_FLAG;
1086 static void _rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1089 BUG_ON((addr & 3) || (mask == 0));
1090 RTL_W32(tp, ERIDR, val);
1091 RTL_W32(tp, ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
1093 rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);
1096 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1099 _rtl_eri_write(tp, addr, mask, val, ERIAR_EXGMAC);
1102 static u32 _rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
1104 RTL_W32(tp, ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
1106 return rtl_udelay_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?
1107 RTL_R32(tp, ERIDR) : ~0;
1110 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr)
1112 return _rtl_eri_read(tp, addr, ERIAR_EXGMAC);
1115 static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 mask, u32 p,
1120 val = rtl_eri_read(tp, addr);
1121 rtl_eri_write(tp, addr, mask, (val & ~m) | p);
1124 static void rtl_eri_set_bits(struct rtl8169_private *tp, int addr, u32 mask,
1127 rtl_w0w1_eri(tp, addr, mask, p, 0);
1130 static void rtl_eri_clear_bits(struct rtl8169_private *tp, int addr, u32 mask,
1133 rtl_w0w1_eri(tp, addr, mask, 0, m);
1136 static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1138 RTL_W32(tp, OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1139 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?
1140 RTL_R32(tp, OCPDR) : ~0;
1143 static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1145 return _rtl_eri_read(tp, reg, ERIAR_OOB);
1148 static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1151 RTL_W32(tp, OCPDR, data);
1152 RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1153 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);
1156 static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1159 _rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT,
1163 static void r8168dp_oob_notify(struct rtl8169_private *tp, u8 cmd)
1165 rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd);
1167 r8168dp_ocp_write(tp, 0x1, 0x30, 0x00000001);
1170 #define OOB_CMD_RESET 0x00
1171 #define OOB_CMD_DRIVER_START 0x05
1172 #define OOB_CMD_DRIVER_STOP 0x06
1174 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
1176 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
1179 DECLARE_RTL_COND(rtl_dp_ocp_read_cond)
1183 reg = rtl8168_get_ocp_reg(tp);
1185 return r8168dp_ocp_read(tp, 0x0f, reg) & 0x00000800;
1188 DECLARE_RTL_COND(rtl_ep_ocp_read_cond)
1190 return r8168ep_ocp_read(tp, 0x0f, 0x124) & 0x00000001;
1193 DECLARE_RTL_COND(rtl_ocp_tx_cond)
1195 return RTL_R8(tp, IBISR0) & 0x20;
1198 static void rtl8168ep_stop_cmac(struct rtl8169_private *tp)
1200 RTL_W8(tp, IBCR2, RTL_R8(tp, IBCR2) & ~0x01);
1201 rtl_msleep_loop_wait_high(tp, &rtl_ocp_tx_cond, 50, 2000);
1202 RTL_W8(tp, IBISR0, RTL_R8(tp, IBISR0) | 0x20);
1203 RTL_W8(tp, IBCR0, RTL_R8(tp, IBCR0) & ~0x01);
1206 static void rtl8168dp_driver_start(struct rtl8169_private *tp)
1208 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_START);
1209 rtl_msleep_loop_wait_high(tp, &rtl_dp_ocp_read_cond, 10, 10);
1212 static void rtl8168ep_driver_start(struct rtl8169_private *tp)
1214 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START);
1215 r8168ep_ocp_write(tp, 0x01, 0x30,
1216 r8168ep_ocp_read(tp, 0x01, 0x30) | 0x01);
1217 rtl_msleep_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10, 10);
1220 static void rtl8168_driver_start(struct rtl8169_private *tp)
1222 switch (tp->mac_version) {
1223 case RTL_GIGA_MAC_VER_27:
1224 case RTL_GIGA_MAC_VER_28:
1225 case RTL_GIGA_MAC_VER_31:
1226 rtl8168dp_driver_start(tp);
1228 case RTL_GIGA_MAC_VER_49:
1229 case RTL_GIGA_MAC_VER_50:
1230 case RTL_GIGA_MAC_VER_51:
1231 rtl8168ep_driver_start(tp);
1239 static void rtl8168dp_driver_stop(struct rtl8169_private *tp)
1241 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_STOP);
1242 rtl_msleep_loop_wait_low(tp, &rtl_dp_ocp_read_cond, 10, 10);
1245 static void rtl8168ep_driver_stop(struct rtl8169_private *tp)
1247 rtl8168ep_stop_cmac(tp);
1248 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP);
1249 r8168ep_ocp_write(tp, 0x01, 0x30,
1250 r8168ep_ocp_read(tp, 0x01, 0x30) | 0x01);
1251 rtl_msleep_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10, 10);
1254 static void rtl8168_driver_stop(struct rtl8169_private *tp)
1256 switch (tp->mac_version) {
1257 case RTL_GIGA_MAC_VER_27:
1258 case RTL_GIGA_MAC_VER_28:
1259 case RTL_GIGA_MAC_VER_31:
1260 rtl8168dp_driver_stop(tp);
1262 case RTL_GIGA_MAC_VER_49:
1263 case RTL_GIGA_MAC_VER_50:
1264 case RTL_GIGA_MAC_VER_51:
1265 rtl8168ep_driver_stop(tp);
1273 static bool r8168dp_check_dash(struct rtl8169_private *tp)
1275 u16 reg = rtl8168_get_ocp_reg(tp);
1277 return !!(r8168dp_ocp_read(tp, 0x0f, reg) & 0x00008000);
1280 static bool r8168ep_check_dash(struct rtl8169_private *tp)
1282 return !!(r8168ep_ocp_read(tp, 0x0f, 0x128) & 0x00000001);
1285 static bool r8168_check_dash(struct rtl8169_private *tp)
1287 switch (tp->mac_version) {
1288 case RTL_GIGA_MAC_VER_27:
1289 case RTL_GIGA_MAC_VER_28:
1290 case RTL_GIGA_MAC_VER_31:
1291 return r8168dp_check_dash(tp);
1292 case RTL_GIGA_MAC_VER_49:
1293 case RTL_GIGA_MAC_VER_50:
1294 case RTL_GIGA_MAC_VER_51:
1295 return r8168ep_check_dash(tp);
1301 static void rtl_reset_packet_filter(struct rtl8169_private *tp)
1303 rtl_eri_clear_bits(tp, 0xdc, ERIAR_MASK_0001, BIT(0));
1304 rtl_eri_set_bits(tp, 0xdc, ERIAR_MASK_0001, BIT(0));
1307 DECLARE_RTL_COND(rtl_efusear_cond)
1309 return RTL_R32(tp, EFUSEAR) & EFUSEAR_FLAG;
1312 static u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)
1314 RTL_W32(tp, EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1316 return rtl_udelay_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?
1317 RTL_R32(tp, EFUSEAR) & EFUSEAR_DATA_MASK : ~0;
1320 static void rtl_ack_events(struct rtl8169_private *tp, u16 bits)
1322 RTL_W16(tp, IntrStatus, bits);
1325 static void rtl_irq_disable(struct rtl8169_private *tp)
1327 RTL_W16(tp, IntrMask, 0);
1328 tp->irq_enabled = 0;
1331 #define RTL_EVENT_NAPI_RX (RxOK | RxErr)
1332 #define RTL_EVENT_NAPI_TX (TxOK | TxErr)
1333 #define RTL_EVENT_NAPI (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX)
1335 static void rtl_irq_enable(struct rtl8169_private *tp)
1337 tp->irq_enabled = 1;
1338 RTL_W16(tp, IntrMask, tp->irq_mask);
1341 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1343 rtl_irq_disable(tp);
1344 rtl_ack_events(tp, 0xffff);
1346 RTL_R8(tp, ChipCmd);
1349 static void rtl_link_chg_patch(struct rtl8169_private *tp)
1351 struct net_device *dev = tp->dev;
1352 struct phy_device *phydev = tp->phydev;
1354 if (!netif_running(dev))
1357 if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
1358 tp->mac_version == RTL_GIGA_MAC_VER_38) {
1359 if (phydev->speed == SPEED_1000) {
1360 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011);
1361 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
1362 } else if (phydev->speed == SPEED_100) {
1363 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1364 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
1366 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1367 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f);
1369 rtl_reset_packet_filter(tp);
1370 } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1371 tp->mac_version == RTL_GIGA_MAC_VER_36) {
1372 if (phydev->speed == SPEED_1000) {
1373 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011);
1374 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
1376 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1377 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f);
1379 } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
1380 if (phydev->speed == SPEED_10) {
1381 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02);
1382 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060a);
1384 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000);
1389 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1391 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1393 struct rtl8169_private *tp = netdev_priv(dev);
1396 wol->supported = WAKE_ANY;
1397 wol->wolopts = tp->saved_wolopts;
1398 rtl_unlock_work(tp);
1401 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1403 unsigned int i, tmp;
1404 static const struct {
1409 { WAKE_PHY, Config3, LinkUp },
1410 { WAKE_UCAST, Config5, UWF },
1411 { WAKE_BCAST, Config5, BWF },
1412 { WAKE_MCAST, Config5, MWF },
1413 { WAKE_ANY, Config5, LanWake },
1414 { WAKE_MAGIC, Config3, MagicPacket }
1418 rtl_unlock_config_regs(tp);
1420 switch (tp->mac_version) {
1421 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
1422 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
1423 tmp = ARRAY_SIZE(cfg) - 1;
1424 if (wolopts & WAKE_MAGIC)
1425 rtl_eri_set_bits(tp, 0x0dc, ERIAR_MASK_0100,
1428 rtl_eri_clear_bits(tp, 0x0dc, ERIAR_MASK_0100,
1432 tmp = ARRAY_SIZE(cfg);
1436 for (i = 0; i < tmp; i++) {
1437 options = RTL_R8(tp, cfg[i].reg) & ~cfg[i].mask;
1438 if (wolopts & cfg[i].opt)
1439 options |= cfg[i].mask;
1440 RTL_W8(tp, cfg[i].reg, options);
1443 switch (tp->mac_version) {
1444 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_17:
1445 options = RTL_R8(tp, Config1) & ~PMEnable;
1447 options |= PMEnable;
1448 RTL_W8(tp, Config1, options);
1451 options = RTL_R8(tp, Config2) & ~PME_SIGNAL;
1453 options |= PME_SIGNAL;
1454 RTL_W8(tp, Config2, options);
1458 rtl_lock_config_regs(tp);
1460 device_set_wakeup_enable(tp_to_dev(tp), wolopts);
1463 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1465 struct rtl8169_private *tp = netdev_priv(dev);
1466 struct device *d = tp_to_dev(tp);
1468 if (wol->wolopts & ~WAKE_ANY)
1471 pm_runtime_get_noresume(d);
1475 tp->saved_wolopts = wol->wolopts;
1477 if (pm_runtime_active(d))
1478 __rtl8169_set_wol(tp, tp->saved_wolopts);
1480 rtl_unlock_work(tp);
1482 pm_runtime_put_noidle(d);
1487 static void rtl8169_get_drvinfo(struct net_device *dev,
1488 struct ethtool_drvinfo *info)
1490 struct rtl8169_private *tp = netdev_priv(dev);
1491 struct rtl_fw *rtl_fw = tp->rtl_fw;
1493 strlcpy(info->driver, MODULENAME, sizeof(info->driver));
1494 strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1495 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
1497 strlcpy(info->fw_version, rtl_fw->version,
1498 sizeof(info->fw_version));
1501 static int rtl8169_get_regs_len(struct net_device *dev)
1503 return R8169_REGS_SIZE;
1506 static netdev_features_t rtl8169_fix_features(struct net_device *dev,
1507 netdev_features_t features)
1509 struct rtl8169_private *tp = netdev_priv(dev);
1511 if (dev->mtu > TD_MSS_MAX)
1512 features &= ~NETIF_F_ALL_TSO;
1514 if (dev->mtu > JUMBO_1K &&
1515 tp->mac_version > RTL_GIGA_MAC_VER_06)
1516 features &= ~NETIF_F_IP_CSUM;
1521 static int rtl8169_set_features(struct net_device *dev,
1522 netdev_features_t features)
1524 struct rtl8169_private *tp = netdev_priv(dev);
1529 rx_config = RTL_R32(tp, RxConfig);
1530 if (features & NETIF_F_RXALL)
1531 rx_config |= (AcceptErr | AcceptRunt);
1533 rx_config &= ~(AcceptErr | AcceptRunt);
1535 RTL_W32(tp, RxConfig, rx_config);
1537 if (features & NETIF_F_RXCSUM)
1538 tp->cp_cmd |= RxChkSum;
1540 tp->cp_cmd &= ~RxChkSum;
1542 if (features & NETIF_F_HW_VLAN_CTAG_RX)
1543 tp->cp_cmd |= RxVlan;
1545 tp->cp_cmd &= ~RxVlan;
1547 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1548 RTL_R16(tp, CPlusCmd);
1550 rtl_unlock_work(tp);
1555 static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb)
1557 return (skb_vlan_tag_present(skb)) ?
1558 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00;
1561 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1563 u32 opts2 = le32_to_cpu(desc->opts2);
1565 if (opts2 & RxVlanTag)
1566 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff));
1569 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1572 struct rtl8169_private *tp = netdev_priv(dev);
1573 u32 __iomem *data = tp->mmio_addr;
1578 for (i = 0; i < R8169_REGS_SIZE; i += 4)
1579 memcpy_fromio(dw++, data++, 4);
1580 rtl_unlock_work(tp);
1583 static u32 rtl8169_get_msglevel(struct net_device *dev)
1585 struct rtl8169_private *tp = netdev_priv(dev);
1587 return tp->msg_enable;
1590 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1592 struct rtl8169_private *tp = netdev_priv(dev);
1594 tp->msg_enable = value;
1597 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1604 "tx_single_collisions",
1605 "tx_multi_collisions",
1613 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1617 return ARRAY_SIZE(rtl8169_gstrings);
1623 DECLARE_RTL_COND(rtl_counters_cond)
1625 return RTL_R32(tp, CounterAddrLow) & (CounterReset | CounterDump);
1628 static bool rtl8169_do_counters(struct rtl8169_private *tp, u32 counter_cmd)
1630 dma_addr_t paddr = tp->counters_phys_addr;
1633 RTL_W32(tp, CounterAddrHigh, (u64)paddr >> 32);
1634 RTL_R32(tp, CounterAddrHigh);
1635 cmd = (u64)paddr & DMA_BIT_MASK(32);
1636 RTL_W32(tp, CounterAddrLow, cmd);
1637 RTL_W32(tp, CounterAddrLow, cmd | counter_cmd);
1639 return rtl_udelay_loop_wait_low(tp, &rtl_counters_cond, 10, 1000);
1642 static bool rtl8169_reset_counters(struct rtl8169_private *tp)
1645 * Versions prior to RTL_GIGA_MAC_VER_19 don't support resetting the
1648 if (tp->mac_version < RTL_GIGA_MAC_VER_19)
1651 return rtl8169_do_counters(tp, CounterReset);
1654 static bool rtl8169_update_counters(struct rtl8169_private *tp)
1656 u8 val = RTL_R8(tp, ChipCmd);
1659 * Some chips are unable to dump tally counters when the receiver
1660 * is disabled. If 0xff chip may be in a PCI power-save state.
1662 if (!(val & CmdRxEnb) || val == 0xff)
1665 return rtl8169_do_counters(tp, CounterDump);
1668 static bool rtl8169_init_counter_offsets(struct rtl8169_private *tp)
1670 struct rtl8169_counters *counters = tp->counters;
1674 * rtl8169_init_counter_offsets is called from rtl_open. On chip
1675 * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only
1676 * reset by a power cycle, while the counter values collected by the
1677 * driver are reset at every driver unload/load cycle.
1679 * To make sure the HW values returned by @get_stats64 match the SW
1680 * values, we collect the initial values at first open(*) and use them
1681 * as offsets to normalize the values returned by @get_stats64.
1683 * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one
1684 * for the reason stated in rtl8169_update_counters; CmdRxEnb is only
1685 * set at open time by rtl_hw_start.
1688 if (tp->tc_offset.inited)
1691 /* If both, reset and update fail, propagate to caller. */
1692 if (rtl8169_reset_counters(tp))
1695 if (rtl8169_update_counters(tp))
1698 tp->tc_offset.tx_errors = counters->tx_errors;
1699 tp->tc_offset.tx_multi_collision = counters->tx_multi_collision;
1700 tp->tc_offset.tx_aborted = counters->tx_aborted;
1701 tp->tc_offset.inited = true;
1706 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1707 struct ethtool_stats *stats, u64 *data)
1709 struct rtl8169_private *tp = netdev_priv(dev);
1710 struct device *d = tp_to_dev(tp);
1711 struct rtl8169_counters *counters = tp->counters;
1715 pm_runtime_get_noresume(d);
1717 if (pm_runtime_active(d))
1718 rtl8169_update_counters(tp);
1720 pm_runtime_put_noidle(d);
1722 data[0] = le64_to_cpu(counters->tx_packets);
1723 data[1] = le64_to_cpu(counters->rx_packets);
1724 data[2] = le64_to_cpu(counters->tx_errors);
1725 data[3] = le32_to_cpu(counters->rx_errors);
1726 data[4] = le16_to_cpu(counters->rx_missed);
1727 data[5] = le16_to_cpu(counters->align_errors);
1728 data[6] = le32_to_cpu(counters->tx_one_collision);
1729 data[7] = le32_to_cpu(counters->tx_multi_collision);
1730 data[8] = le64_to_cpu(counters->rx_unicast);
1731 data[9] = le64_to_cpu(counters->rx_broadcast);
1732 data[10] = le32_to_cpu(counters->rx_multicast);
1733 data[11] = le16_to_cpu(counters->tx_aborted);
1734 data[12] = le16_to_cpu(counters->tx_underun);
1737 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1741 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1747 * Interrupt coalescing
1749 * > 1 - the availability of the IntrMitigate (0xe2) register through the
1750 * > 8169, 8168 and 810x line of chipsets
1752 * 8169, 8168, and 8136(810x) serial chipsets support it.
1754 * > 2 - the Tx timer unit at gigabit speed
1756 * The unit of the timer depends on both the speed and the setting of CPlusCmd
1757 * (0xe0) bit 1 and bit 0.
1760 * bit[1:0] \ speed 1000M 100M 10M
1761 * 0 0 320ns 2.56us 40.96us
1762 * 0 1 2.56us 20.48us 327.7us
1763 * 1 0 5.12us 40.96us 655.4us
1764 * 1 1 10.24us 81.92us 1.31ms
1767 * bit[1:0] \ speed 1000M 100M 10M
1768 * 0 0 5us 2.56us 40.96us
1769 * 0 1 40us 20.48us 327.7us
1770 * 1 0 80us 40.96us 655.4us
1771 * 1 1 160us 81.92us 1.31ms
1774 /* rx/tx scale factors for one particular CPlusCmd[0:1] value */
1775 struct rtl_coalesce_scale {
1780 /* rx/tx scale factors for all CPlusCmd[0:1] cases */
1781 struct rtl_coalesce_info {
1783 struct rtl_coalesce_scale scalev[4]; /* each CPlusCmd[0:1] case */
1786 /* produce (r,t) pairs with each being in series of *1, *8, *8*2, *8*2*2 */
1787 #define rxtx_x1822(r, t) { \
1790 {{(r)*8*2, (t)*8*2}}, \
1791 {{(r)*8*2*2, (t)*8*2*2}}, \
1793 static const struct rtl_coalesce_info rtl_coalesce_info_8169[] = {
1794 /* speed delays: rx00 tx00 */
1795 { SPEED_10, rxtx_x1822(40960, 40960) },
1796 { SPEED_100, rxtx_x1822( 2560, 2560) },
1797 { SPEED_1000, rxtx_x1822( 320, 320) },
1801 static const struct rtl_coalesce_info rtl_coalesce_info_8168_8136[] = {
1802 /* speed delays: rx00 tx00 */
1803 { SPEED_10, rxtx_x1822(40960, 40960) },
1804 { SPEED_100, rxtx_x1822( 2560, 2560) },
1805 { SPEED_1000, rxtx_x1822( 5000, 5000) },
1810 /* get rx/tx scale vector corresponding to current speed */
1811 static const struct rtl_coalesce_info *rtl_coalesce_info(struct net_device *dev)
1813 struct rtl8169_private *tp = netdev_priv(dev);
1814 struct ethtool_link_ksettings ecmd;
1815 const struct rtl_coalesce_info *ci;
1818 rc = phy_ethtool_get_link_ksettings(dev, &ecmd);
1822 for (ci = tp->coalesce_info; ci->speed != 0; ci++) {
1823 if (ecmd.base.speed == ci->speed) {
1828 return ERR_PTR(-ELNRNG);
1831 static int rtl_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1833 struct rtl8169_private *tp = netdev_priv(dev);
1834 const struct rtl_coalesce_info *ci;
1835 const struct rtl_coalesce_scale *scale;
1839 } coal_settings [] = {
1840 { &ec->rx_max_coalesced_frames, &ec->rx_coalesce_usecs },
1841 { &ec->tx_max_coalesced_frames, &ec->tx_coalesce_usecs }
1842 }, *p = coal_settings;
1846 memset(ec, 0, sizeof(*ec));
1848 /* get rx/tx scale corresponding to current speed and CPlusCmd[0:1] */
1849 ci = rtl_coalesce_info(dev);
1853 scale = &ci->scalev[tp->cp_cmd & INTT_MASK];
1855 /* read IntrMitigate and adjust according to scale */
1856 for (w = RTL_R16(tp, IntrMitigate); w; w >>= RTL_COALESCE_SHIFT, p++) {
1857 *p->max_frames = (w & RTL_COALESCE_MASK) << 2;
1858 w >>= RTL_COALESCE_SHIFT;
1859 *p->usecs = w & RTL_COALESCE_MASK;
1862 for (i = 0; i < 2; i++) {
1863 p = coal_settings + i;
1864 *p->usecs = (*p->usecs * scale->nsecs[i]) / 1000;
1867 * ethtool_coalesce says it is illegal to set both usecs and
1870 if (!*p->usecs && !*p->max_frames)
1877 /* choose appropriate scale factor and CPlusCmd[0:1] for (speed, nsec) */
1878 static const struct rtl_coalesce_scale *rtl_coalesce_choose_scale(
1879 struct net_device *dev, u32 nsec, u16 *cp01)
1881 const struct rtl_coalesce_info *ci;
1884 ci = rtl_coalesce_info(dev);
1886 return ERR_CAST(ci);
1888 for (i = 0; i < 4; i++) {
1889 u32 rxtx_maxscale = max(ci->scalev[i].nsecs[0],
1890 ci->scalev[i].nsecs[1]);
1891 if (nsec <= rxtx_maxscale * RTL_COALESCE_T_MAX) {
1893 return &ci->scalev[i];
1897 return ERR_PTR(-EINVAL);
1900 static int rtl_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1902 struct rtl8169_private *tp = netdev_priv(dev);
1903 const struct rtl_coalesce_scale *scale;
1907 } coal_settings [] = {
1908 { ec->rx_max_coalesced_frames, ec->rx_coalesce_usecs },
1909 { ec->tx_max_coalesced_frames, ec->tx_coalesce_usecs }
1910 }, *p = coal_settings;
1914 scale = rtl_coalesce_choose_scale(dev,
1915 max(p[0].usecs, p[1].usecs) * 1000, &cp01);
1917 return PTR_ERR(scale);
1919 for (i = 0; i < 2; i++, p++) {
1923 * accept max_frames=1 we returned in rtl_get_coalesce.
1924 * accept it not only when usecs=0 because of e.g. the following scenario:
1926 * - both rx_usecs=0 & rx_frames=0 in hardware (no delay on RX)
1927 * - rtl_get_coalesce returns rx_usecs=0, rx_frames=1
1928 * - then user does `ethtool -C eth0 rx-usecs 100`
1930 * since ethtool sends to kernel whole ethtool_coalesce
1931 * settings, if we do not handle rx_usecs=!0, rx_frames=1
1932 * we'll reject it below in `frames % 4 != 0`.
1934 if (p->frames == 1) {
1938 units = p->usecs * 1000 / scale->nsecs[i];
1939 if (p->frames > RTL_COALESCE_FRAME_MAX || p->frames % 4)
1942 w <<= RTL_COALESCE_SHIFT;
1944 w <<= RTL_COALESCE_SHIFT;
1945 w |= p->frames >> 2;
1950 RTL_W16(tp, IntrMitigate, swab16(w));
1952 tp->cp_cmd = (tp->cp_cmd & ~INTT_MASK) | cp01;
1953 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1954 RTL_R16(tp, CPlusCmd);
1956 rtl_unlock_work(tp);
1961 static int rtl_get_eee_supp(struct rtl8169_private *tp)
1963 struct phy_device *phydev = tp->phydev;
1966 switch (tp->mac_version) {
1967 case RTL_GIGA_MAC_VER_34:
1968 case RTL_GIGA_MAC_VER_35:
1969 case RTL_GIGA_MAC_VER_36:
1970 case RTL_GIGA_MAC_VER_38:
1971 ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE);
1973 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
1974 ret = phy_read_paged(phydev, 0x0a5c, 0x12);
1977 ret = -EPROTONOSUPPORT;
1984 static int rtl_get_eee_lpadv(struct rtl8169_private *tp)
1986 struct phy_device *phydev = tp->phydev;
1989 switch (tp->mac_version) {
1990 case RTL_GIGA_MAC_VER_34:
1991 case RTL_GIGA_MAC_VER_35:
1992 case RTL_GIGA_MAC_VER_36:
1993 case RTL_GIGA_MAC_VER_38:
1994 ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE);
1996 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
1997 ret = phy_read_paged(phydev, 0x0a5d, 0x11);
2000 ret = -EPROTONOSUPPORT;
2007 static int rtl_get_eee_adv(struct rtl8169_private *tp)
2009 struct phy_device *phydev = tp->phydev;
2012 switch (tp->mac_version) {
2013 case RTL_GIGA_MAC_VER_34:
2014 case RTL_GIGA_MAC_VER_35:
2015 case RTL_GIGA_MAC_VER_36:
2016 case RTL_GIGA_MAC_VER_38:
2017 ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV);
2019 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
2020 ret = phy_read_paged(phydev, 0x0a5d, 0x10);
2023 ret = -EPROTONOSUPPORT;
2030 static int rtl_set_eee_adv(struct rtl8169_private *tp, int val)
2032 struct phy_device *phydev = tp->phydev;
2035 switch (tp->mac_version) {
2036 case RTL_GIGA_MAC_VER_34:
2037 case RTL_GIGA_MAC_VER_35:
2038 case RTL_GIGA_MAC_VER_36:
2039 case RTL_GIGA_MAC_VER_38:
2040 ret = phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);
2042 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
2043 phy_write_paged(phydev, 0x0a5d, 0x10, val);
2046 ret = -EPROTONOSUPPORT;
2053 static int rtl8169_get_eee(struct net_device *dev, struct ethtool_eee *data)
2055 struct rtl8169_private *tp = netdev_priv(dev);
2056 struct device *d = tp_to_dev(tp);
2059 pm_runtime_get_noresume(d);
2061 if (!pm_runtime_active(d)) {
2066 /* Get Supported EEE */
2067 ret = rtl_get_eee_supp(tp);
2070 data->supported = mmd_eee_cap_to_ethtool_sup_t(ret);
2072 /* Get advertisement EEE */
2073 ret = rtl_get_eee_adv(tp);
2076 data->advertised = mmd_eee_adv_to_ethtool_adv_t(ret);
2077 data->eee_enabled = !!data->advertised;
2079 /* Get LP advertisement EEE */
2080 ret = rtl_get_eee_lpadv(tp);
2083 data->lp_advertised = mmd_eee_adv_to_ethtool_adv_t(ret);
2084 data->eee_active = !!(data->advertised & data->lp_advertised);
2086 pm_runtime_put_noidle(d);
2087 return ret < 0 ? ret : 0;
2090 static int rtl8169_set_eee(struct net_device *dev, struct ethtool_eee *data)
2092 struct rtl8169_private *tp = netdev_priv(dev);
2093 struct device *d = tp_to_dev(tp);
2094 int old_adv, adv = 0, cap, ret;
2096 pm_runtime_get_noresume(d);
2098 if (!dev->phydev || !pm_runtime_active(d)) {
2103 if (dev->phydev->autoneg == AUTONEG_DISABLE ||
2104 dev->phydev->duplex != DUPLEX_FULL) {
2105 ret = -EPROTONOSUPPORT;
2109 /* Get Supported EEE */
2110 ret = rtl_get_eee_supp(tp);
2115 ret = rtl_get_eee_adv(tp);
2120 if (data->eee_enabled) {
2121 adv = !data->advertised ? cap :
2122 ethtool_adv_to_mmd_eee_adv_t(data->advertised) & cap;
2123 /* Mask prohibited EEE modes */
2124 adv &= ~dev->phydev->eee_broken_modes;
2127 if (old_adv != adv) {
2128 ret = rtl_set_eee_adv(tp, adv);
2132 /* Restart autonegotiation so the new modes get sent to the
2135 ret = phy_restart_aneg(dev->phydev);
2139 pm_runtime_put_noidle(d);
2140 return ret < 0 ? ret : 0;
2143 static const struct ethtool_ops rtl8169_ethtool_ops = {
2144 .get_drvinfo = rtl8169_get_drvinfo,
2145 .get_regs_len = rtl8169_get_regs_len,
2146 .get_link = ethtool_op_get_link,
2147 .get_coalesce = rtl_get_coalesce,
2148 .set_coalesce = rtl_set_coalesce,
2149 .get_msglevel = rtl8169_get_msglevel,
2150 .set_msglevel = rtl8169_set_msglevel,
2151 .get_regs = rtl8169_get_regs,
2152 .get_wol = rtl8169_get_wol,
2153 .set_wol = rtl8169_set_wol,
2154 .get_strings = rtl8169_get_strings,
2155 .get_sset_count = rtl8169_get_sset_count,
2156 .get_ethtool_stats = rtl8169_get_ethtool_stats,
2157 .get_ts_info = ethtool_op_get_ts_info,
2158 .nway_reset = phy_ethtool_nway_reset,
2159 .get_eee = rtl8169_get_eee,
2160 .set_eee = rtl8169_set_eee,
2161 .get_link_ksettings = phy_ethtool_get_link_ksettings,
2162 .set_link_ksettings = phy_ethtool_set_link_ksettings,
2165 static void rtl_enable_eee(struct rtl8169_private *tp)
2167 int supported = rtl_get_eee_supp(tp);
2170 rtl_set_eee_adv(tp, supported);
2173 static void rtl8169_get_mac_version(struct rtl8169_private *tp)
2176 * The driver currently handles the 8168Bf and the 8168Be identically
2177 * but they can be identified more specifically through the test below
2180 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
2182 * Same thing for the 8101Eb and the 8101Ec:
2184 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
2186 static const struct rtl_mac_info {
2191 /* 8168EP family. */
2192 { 0x7cf, 0x502, RTL_GIGA_MAC_VER_51 },
2193 { 0x7cf, 0x501, RTL_GIGA_MAC_VER_50 },
2194 { 0x7cf, 0x500, RTL_GIGA_MAC_VER_49 },
2197 { 0x7cf, 0x541, RTL_GIGA_MAC_VER_46 },
2198 { 0x7cf, 0x540, RTL_GIGA_MAC_VER_45 },
2201 { 0x7cf, 0x5c8, RTL_GIGA_MAC_VER_44 },
2202 { 0x7cf, 0x509, RTL_GIGA_MAC_VER_42 },
2203 { 0x7cf, 0x4c1, RTL_GIGA_MAC_VER_41 },
2204 { 0x7cf, 0x4c0, RTL_GIGA_MAC_VER_40 },
2207 { 0x7c8, 0x488, RTL_GIGA_MAC_VER_38 },
2208 { 0x7cf, 0x481, RTL_GIGA_MAC_VER_36 },
2209 { 0x7cf, 0x480, RTL_GIGA_MAC_VER_35 },
2212 { 0x7c8, 0x2c8, RTL_GIGA_MAC_VER_34 },
2213 { 0x7cf, 0x2c1, RTL_GIGA_MAC_VER_32 },
2214 { 0x7c8, 0x2c0, RTL_GIGA_MAC_VER_33 },
2217 { 0x7cf, 0x281, RTL_GIGA_MAC_VER_25 },
2218 { 0x7c8, 0x280, RTL_GIGA_MAC_VER_26 },
2220 /* 8168DP family. */
2221 { 0x7cf, 0x288, RTL_GIGA_MAC_VER_27 },
2222 { 0x7cf, 0x28a, RTL_GIGA_MAC_VER_28 },
2223 { 0x7cf, 0x28b, RTL_GIGA_MAC_VER_31 },
2226 { 0x7cf, 0x3c9, RTL_GIGA_MAC_VER_23 },
2227 { 0x7cf, 0x3c8, RTL_GIGA_MAC_VER_18 },
2228 { 0x7c8, 0x3c8, RTL_GIGA_MAC_VER_24 },
2229 { 0x7cf, 0x3c0, RTL_GIGA_MAC_VER_19 },
2230 { 0x7cf, 0x3c2, RTL_GIGA_MAC_VER_20 },
2231 { 0x7cf, 0x3c3, RTL_GIGA_MAC_VER_21 },
2232 { 0x7c8, 0x3c0, RTL_GIGA_MAC_VER_22 },
2235 { 0x7cf, 0x380, RTL_GIGA_MAC_VER_12 },
2236 { 0x7c8, 0x380, RTL_GIGA_MAC_VER_17 },
2237 { 0x7c8, 0x300, RTL_GIGA_MAC_VER_11 },
2240 { 0x7c8, 0x448, RTL_GIGA_MAC_VER_39 },
2241 { 0x7c8, 0x440, RTL_GIGA_MAC_VER_37 },
2242 { 0x7cf, 0x409, RTL_GIGA_MAC_VER_29 },
2243 { 0x7c8, 0x408, RTL_GIGA_MAC_VER_30 },
2244 { 0x7cf, 0x349, RTL_GIGA_MAC_VER_08 },
2245 { 0x7cf, 0x249, RTL_GIGA_MAC_VER_08 },
2246 { 0x7cf, 0x348, RTL_GIGA_MAC_VER_07 },
2247 { 0x7cf, 0x248, RTL_GIGA_MAC_VER_07 },
2248 { 0x7cf, 0x340, RTL_GIGA_MAC_VER_13 },
2249 { 0x7cf, 0x343, RTL_GIGA_MAC_VER_10 },
2250 { 0x7cf, 0x342, RTL_GIGA_MAC_VER_16 },
2251 { 0x7c8, 0x348, RTL_GIGA_MAC_VER_09 },
2252 { 0x7c8, 0x248, RTL_GIGA_MAC_VER_09 },
2253 { 0x7c8, 0x340, RTL_GIGA_MAC_VER_16 },
2254 /* FIXME: where did these entries come from ? -- FR */
2255 { 0xfc8, 0x388, RTL_GIGA_MAC_VER_15 },
2256 { 0xfc8, 0x308, RTL_GIGA_MAC_VER_14 },
2259 { 0xfc8, 0x980, RTL_GIGA_MAC_VER_06 },
2260 { 0xfc8, 0x180, RTL_GIGA_MAC_VER_05 },
2261 { 0xfc8, 0x100, RTL_GIGA_MAC_VER_04 },
2262 { 0xfc8, 0x040, RTL_GIGA_MAC_VER_03 },
2263 { 0xfc8, 0x008, RTL_GIGA_MAC_VER_02 },
2266 { 0x000, 0x000, RTL_GIGA_MAC_NONE }
2268 const struct rtl_mac_info *p = mac_info;
2269 u16 reg = RTL_R32(tp, TxConfig) >> 20;
2271 while ((reg & p->mask) != p->val)
2273 tp->mac_version = p->mac_version;
2275 if (tp->mac_version == RTL_GIGA_MAC_NONE) {
2276 dev_err(tp_to_dev(tp), "unknown chip XID %03x\n", reg & 0xfcf);
2277 } else if (!tp->supports_gmii) {
2278 if (tp->mac_version == RTL_GIGA_MAC_VER_42)
2279 tp->mac_version = RTL_GIGA_MAC_VER_43;
2280 else if (tp->mac_version == RTL_GIGA_MAC_VER_45)
2281 tp->mac_version = RTL_GIGA_MAC_VER_47;
2282 else if (tp->mac_version == RTL_GIGA_MAC_VER_46)
2283 tp->mac_version = RTL_GIGA_MAC_VER_48;
2292 static void __rtl_writephy_batch(struct rtl8169_private *tp,
2293 const struct phy_reg *regs, int len)
2296 rtl_writephy(tp, regs->reg, regs->val);
2301 #define rtl_writephy_batch(tp, a) __rtl_writephy_batch(tp, a, ARRAY_SIZE(a))
2303 enum rtl_fw_opcode {
2309 PHY_CLEAR_READCOUNT = 0x7,
2311 PHY_READCOUNT_EQ_SKIP = 0x9,
2312 PHY_COMP_EQ_SKIPN = 0xa,
2313 PHY_COMP_NEQ_SKIPN = 0xb,
2314 PHY_WRITE_PREVIOUS = 0xc,
2321 char version[RTL_VER_SIZE];
2327 #define FW_OPCODE_SIZE sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
2329 static bool rtl_fw_format_ok(struct rtl_fw *rtl_fw)
2331 const struct firmware *fw = rtl_fw->fw;
2332 struct fw_info *fw_info = (struct fw_info *)fw->data;
2333 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2335 if (fw->size < FW_OPCODE_SIZE)
2338 if (!fw_info->magic) {
2339 size_t i, size, start;
2342 if (fw->size < sizeof(*fw_info))
2345 for (i = 0; i < fw->size; i++)
2346 checksum += fw->data[i];
2350 start = le32_to_cpu(fw_info->fw_start);
2351 if (start > fw->size)
2354 size = le32_to_cpu(fw_info->fw_len);
2355 if (size > (fw->size - start) / FW_OPCODE_SIZE)
2358 strscpy(rtl_fw->version, fw_info->version, RTL_VER_SIZE);
2360 pa->code = (__le32 *)(fw->data + start);
2363 if (fw->size % FW_OPCODE_SIZE)
2366 strscpy(rtl_fw->version, rtl_fw->fw_name, RTL_VER_SIZE);
2368 pa->code = (__le32 *)fw->data;
2369 pa->size = fw->size / FW_OPCODE_SIZE;
2375 static bool rtl_fw_data_ok(struct rtl_fw *rtl_fw)
2377 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2380 for (index = 0; index < pa->size; index++) {
2381 u32 action = le32_to_cpu(pa->code[index]);
2382 u32 regno = (action & 0x0fff0000) >> 16;
2384 switch (action >> 28) {
2389 case PHY_CLEAR_READCOUNT:
2391 case PHY_WRITE_PREVIOUS:
2399 case PHY_READCOUNT_EQ_SKIP:
2400 if (index + 2 >= pa->size)
2403 case PHY_COMP_EQ_SKIPN:
2404 case PHY_COMP_NEQ_SKIPN:
2406 if (index + 1 + regno >= pa->size)
2411 dev_err(rtl_fw->dev, "Invalid action 0x%08x\n", action);
2418 dev_err(rtl_fw->dev, "Out of range of firmware\n");
2422 static void rtl_fw_write_firmware(struct rtl8169_private *tp,
2423 struct rtl_fw *rtl_fw)
2425 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2426 rtl_fw_write_t fw_write = rtl_fw->phy_write;
2427 rtl_fw_read_t fw_read = rtl_fw->phy_read;
2428 int predata = 0, count = 0;
2431 for (index = 0; index < pa->size; index++) {
2432 u32 action = le32_to_cpu(pa->code[index]);
2433 u32 data = action & 0x0000ffff;
2434 u32 regno = (action & 0x0fff0000) >> 16;
2435 enum rtl_fw_opcode opcode = action >> 28;
2442 predata = fw_read(tp, regno);
2452 index -= (regno + 1);
2456 fw_write = rtl_fw->phy_write;
2457 fw_read = rtl_fw->phy_read;
2458 } else if (data == 1) {
2459 fw_write = rtl_fw->mac_mcu_write;
2460 fw_read = rtl_fw->mac_mcu_read;
2464 case PHY_CLEAR_READCOUNT:
2468 fw_write(tp, regno, data);
2470 case PHY_READCOUNT_EQ_SKIP:
2474 case PHY_COMP_EQ_SKIPN:
2475 if (predata == data)
2478 case PHY_COMP_NEQ_SKIPN:
2479 if (predata != data)
2482 case PHY_WRITE_PREVIOUS:
2483 fw_write(tp, regno, predata);
2495 static void rtl_fw_release_firmware(struct rtl_fw *rtl_fw)
2497 release_firmware(rtl_fw->fw);
2500 static void rtl_release_firmware(struct rtl8169_private *tp)
2503 rtl_fw_release_firmware(tp->rtl_fw);
2509 static void rtl_apply_firmware(struct rtl8169_private *tp)
2511 /* TODO: release firmware if rtl_fw_write_firmware signals failure. */
2513 rtl_fw_write_firmware(tp, tp->rtl_fw);
2516 static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
2518 if (rtl_readphy(tp, reg) != val)
2519 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
2521 rtl_apply_firmware(tp);
2524 static void rtl8168_config_eee_mac(struct rtl8169_private *tp)
2526 /* Adjust EEE LED frequency */
2527 if (tp->mac_version != RTL_GIGA_MAC_VER_38)
2528 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
2530 rtl_eri_set_bits(tp, 0x1b0, ERIAR_MASK_1111, 0x0003);
2533 static void rtl8168f_config_eee_phy(struct rtl8169_private *tp)
2535 struct phy_device *phydev = tp->phydev;
2537 phy_write(phydev, 0x1f, 0x0007);
2538 phy_write(phydev, 0x1e, 0x0020);
2539 phy_set_bits(phydev, 0x15, BIT(8));
2541 phy_write(phydev, 0x1f, 0x0005);
2542 phy_write(phydev, 0x05, 0x8b85);
2543 phy_set_bits(phydev, 0x06, BIT(13));
2545 phy_write(phydev, 0x1f, 0x0000);
2548 static void rtl8168g_config_eee_phy(struct rtl8169_private *tp)
2550 phy_modify_paged(tp->phydev, 0x0a43, 0x11, 0, BIT(4));
2553 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
2555 static const struct phy_reg phy_reg_init[] = {
2617 rtl_writephy_batch(tp, phy_reg_init);
2620 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
2622 static const struct phy_reg phy_reg_init[] = {
2628 rtl_writephy_batch(tp, phy_reg_init);
2631 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2633 struct pci_dev *pdev = tp->pci_dev;
2635 if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
2636 (pdev->subsystem_device != 0xe000))
2639 rtl_writephy(tp, 0x1f, 0x0001);
2640 rtl_writephy(tp, 0x10, 0xf01b);
2641 rtl_writephy(tp, 0x1f, 0x0000);
2644 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2646 static const struct phy_reg phy_reg_init[] = {
2686 rtl_writephy_batch(tp, phy_reg_init);
2688 rtl8169scd_hw_phy_config_quirk(tp);
2691 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
2693 static const struct phy_reg phy_reg_init[] = {
2741 rtl_writephy_batch(tp, phy_reg_init);
2744 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
2746 static const struct phy_reg phy_reg_init[] = {
2751 rtl_writephy(tp, 0x1f, 0x0001);
2752 rtl_patchphy(tp, 0x16, 1 << 0);
2754 rtl_writephy_batch(tp, phy_reg_init);
2757 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
2759 static const struct phy_reg phy_reg_init[] = {
2765 rtl_writephy_batch(tp, phy_reg_init);
2768 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
2770 static const struct phy_reg phy_reg_init[] = {
2778 rtl_writephy_batch(tp, phy_reg_init);
2781 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
2783 static const struct phy_reg phy_reg_init[] = {
2789 rtl_writephy(tp, 0x1f, 0x0000);
2790 rtl_patchphy(tp, 0x14, 1 << 5);
2791 rtl_patchphy(tp, 0x0d, 1 << 5);
2793 rtl_writephy_batch(tp, phy_reg_init);
2796 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
2798 static const struct phy_reg phy_reg_init[] = {
2818 rtl_writephy_batch(tp, phy_reg_init);
2820 rtl_patchphy(tp, 0x14, 1 << 5);
2821 rtl_patchphy(tp, 0x0d, 1 << 5);
2822 rtl_writephy(tp, 0x1f, 0x0000);
2825 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
2827 static const struct phy_reg phy_reg_init[] = {
2845 rtl_writephy_batch(tp, phy_reg_init);
2847 rtl_patchphy(tp, 0x16, 1 << 0);
2848 rtl_patchphy(tp, 0x14, 1 << 5);
2849 rtl_patchphy(tp, 0x0d, 1 << 5);
2850 rtl_writephy(tp, 0x1f, 0x0000);
2853 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
2855 static const struct phy_reg phy_reg_init[] = {
2867 rtl_writephy_batch(tp, phy_reg_init);
2869 rtl_patchphy(tp, 0x16, 1 << 0);
2870 rtl_patchphy(tp, 0x14, 1 << 5);
2871 rtl_patchphy(tp, 0x0d, 1 << 5);
2872 rtl_writephy(tp, 0x1f, 0x0000);
2875 static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
2877 rtl8168c_3_hw_phy_config(tp);
2880 static const struct phy_reg rtl8168d_1_phy_reg_init_0[] = {
2881 /* Channel Estimation */
2902 * Enhance line driver power
2911 * Can not link to 1Gbps with bad cable
2912 * Decrease SNR threshold form 21.07dB to 19.04dB
2921 static const struct phy_reg rtl8168d_1_phy_reg_init_1[] = {
2930 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
2932 rtl_writephy_batch(tp, rtl8168d_1_phy_reg_init_0);
2936 * Fine Tune Switching regulator parameter
2938 rtl_writephy(tp, 0x1f, 0x0002);
2939 rtl_w0w1_phy(tp, 0x0b, 0x0010, 0x00ef);
2940 rtl_w0w1_phy(tp, 0x0c, 0xa200, 0x5d00);
2942 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
2945 rtl_writephy_batch(tp, rtl8168d_1_phy_reg_init_1);
2947 val = rtl_readphy(tp, 0x0d);
2949 if ((val & 0x00ff) != 0x006c) {
2950 static const u32 set[] = {
2951 0x0065, 0x0066, 0x0067, 0x0068,
2952 0x0069, 0x006a, 0x006b, 0x006c
2956 rtl_writephy(tp, 0x1f, 0x0002);
2959 for (i = 0; i < ARRAY_SIZE(set); i++)
2960 rtl_writephy(tp, 0x0d, val | set[i]);
2963 static const struct phy_reg phy_reg_init[] = {
2971 rtl_writephy_batch(tp, phy_reg_init);
2974 /* RSET couple improve */
2975 rtl_writephy(tp, 0x1f, 0x0002);
2976 rtl_patchphy(tp, 0x0d, 0x0300);
2977 rtl_patchphy(tp, 0x0f, 0x0010);
2979 /* Fine tune PLL performance */
2980 rtl_writephy(tp, 0x1f, 0x0002);
2981 rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
2982 rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
2984 rtl_writephy(tp, 0x1f, 0x0005);
2985 rtl_writephy(tp, 0x05, 0x001b);
2987 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
2989 rtl_writephy(tp, 0x1f, 0x0000);
2992 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
2994 rtl_writephy_batch(tp, rtl8168d_1_phy_reg_init_0);
2996 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
2999 rtl_writephy_batch(tp, rtl8168d_1_phy_reg_init_1);
3001 val = rtl_readphy(tp, 0x0d);
3002 if ((val & 0x00ff) != 0x006c) {
3003 static const u32 set[] = {
3004 0x0065, 0x0066, 0x0067, 0x0068,
3005 0x0069, 0x006a, 0x006b, 0x006c
3009 rtl_writephy(tp, 0x1f, 0x0002);
3012 for (i = 0; i < ARRAY_SIZE(set); i++)
3013 rtl_writephy(tp, 0x0d, val | set[i]);
3016 static const struct phy_reg phy_reg_init[] = {
3024 rtl_writephy_batch(tp, phy_reg_init);
3027 /* Fine tune PLL performance */
3028 rtl_writephy(tp, 0x1f, 0x0002);
3029 rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
3030 rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
3032 /* Switching regulator Slew rate */
3033 rtl_writephy(tp, 0x1f, 0x0002);
3034 rtl_patchphy(tp, 0x0f, 0x0017);
3036 rtl_writephy(tp, 0x1f, 0x0005);
3037 rtl_writephy(tp, 0x05, 0x001b);
3039 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
3041 rtl_writephy(tp, 0x1f, 0x0000);
3044 static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
3046 static const struct phy_reg phy_reg_init[] = {
3102 rtl_writephy_batch(tp, phy_reg_init);
3105 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
3107 static const struct phy_reg phy_reg_init[] = {
3117 rtl_writephy_batch(tp, phy_reg_init);
3118 rtl_patchphy(tp, 0x0d, 1 << 5);
3121 static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
3123 static const struct phy_reg phy_reg_init[] = {
3124 /* Enable Delay cap */
3130 /* Channel estimation fine tune */
3139 /* Update PFM & 10M TX idle timer */
3151 rtl_apply_firmware(tp);
3153 rtl_writephy_batch(tp, phy_reg_init);
3155 /* DCO enable for 10M IDLE Power */
3156 rtl_writephy(tp, 0x1f, 0x0007);
3157 rtl_writephy(tp, 0x1e, 0x0023);
3158 rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
3159 rtl_writephy(tp, 0x1f, 0x0000);
3161 /* For impedance matching */
3162 rtl_writephy(tp, 0x1f, 0x0002);
3163 rtl_w0w1_phy(tp, 0x08, 0x8000, 0x7f00);
3164 rtl_writephy(tp, 0x1f, 0x0000);
3166 /* PHY auto speed down */
3167 rtl_writephy(tp, 0x1f, 0x0007);
3168 rtl_writephy(tp, 0x1e, 0x002d);
3169 rtl_w0w1_phy(tp, 0x18, 0x0050, 0x0000);
3170 rtl_writephy(tp, 0x1f, 0x0000);
3171 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3173 rtl_writephy(tp, 0x1f, 0x0005);
3174 rtl_writephy(tp, 0x05, 0x8b86);
3175 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3176 rtl_writephy(tp, 0x1f, 0x0000);
3178 rtl_writephy(tp, 0x1f, 0x0005);
3179 rtl_writephy(tp, 0x05, 0x8b85);
3180 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
3181 rtl_writephy(tp, 0x1f, 0x0007);
3182 rtl_writephy(tp, 0x1e, 0x0020);
3183 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x1100);
3184 rtl_writephy(tp, 0x1f, 0x0006);
3185 rtl_writephy(tp, 0x00, 0x5a00);
3186 rtl_writephy(tp, 0x1f, 0x0000);
3187 rtl_writephy(tp, 0x0d, 0x0007);
3188 rtl_writephy(tp, 0x0e, 0x003c);
3189 rtl_writephy(tp, 0x0d, 0x4007);
3190 rtl_writephy(tp, 0x0e, 0x0000);
3191 rtl_writephy(tp, 0x0d, 0x0000);
3194 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, u8 *addr)
3197 addr[0] | (addr[1] << 8),
3198 addr[2] | (addr[3] << 8),
3199 addr[4] | (addr[5] << 8)
3202 rtl_eri_write(tp, 0xe0, ERIAR_MASK_1111, w[0] | (w[1] << 16));
3203 rtl_eri_write(tp, 0xe4, ERIAR_MASK_1111, w[2]);
3204 rtl_eri_write(tp, 0xf0, ERIAR_MASK_1111, w[0] << 16);
3205 rtl_eri_write(tp, 0xf4, ERIAR_MASK_1111, w[1] | (w[2] << 16));
3208 static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
3210 static const struct phy_reg phy_reg_init[] = {
3211 /* Enable Delay cap */
3220 /* Channel estimation fine tune */
3237 rtl_apply_firmware(tp);
3239 rtl_writephy_batch(tp, phy_reg_init);
3241 /* For 4-corner performance improve */
3242 rtl_writephy(tp, 0x1f, 0x0005);
3243 rtl_writephy(tp, 0x05, 0x8b80);
3244 rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
3245 rtl_writephy(tp, 0x1f, 0x0000);
3247 /* PHY auto speed down */
3248 rtl_writephy(tp, 0x1f, 0x0004);
3249 rtl_writephy(tp, 0x1f, 0x0007);
3250 rtl_writephy(tp, 0x1e, 0x002d);
3251 rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
3252 rtl_writephy(tp, 0x1f, 0x0002);
3253 rtl_writephy(tp, 0x1f, 0x0000);
3254 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3256 /* improve 10M EEE waveform */
3257 rtl_writephy(tp, 0x1f, 0x0005);
3258 rtl_writephy(tp, 0x05, 0x8b86);
3259 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3260 rtl_writephy(tp, 0x1f, 0x0000);
3262 /* Improve 2-pair detection performance */
3263 rtl_writephy(tp, 0x1f, 0x0005);
3264 rtl_writephy(tp, 0x05, 0x8b85);
3265 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3266 rtl_writephy(tp, 0x1f, 0x0000);
3268 rtl8168f_config_eee_phy(tp);
3272 rtl_writephy(tp, 0x1f, 0x0003);
3273 rtl_w0w1_phy(tp, 0x19, 0x0001, 0x0000);
3274 rtl_w0w1_phy(tp, 0x10, 0x0400, 0x0000);
3275 rtl_writephy(tp, 0x1f, 0x0000);
3276 rtl_writephy(tp, 0x1f, 0x0005);
3277 rtl_w0w1_phy(tp, 0x01, 0x0100, 0x0000);
3278 rtl_writephy(tp, 0x1f, 0x0000);
3280 /* Broken BIOS workaround: feed GigaMAC registers with MAC address. */
3281 rtl_rar_exgmac_set(tp, tp->dev->dev_addr);
3284 static void rtl8168f_hw_phy_config(struct rtl8169_private *tp)
3286 /* For 4-corner performance improve */
3287 rtl_writephy(tp, 0x1f, 0x0005);
3288 rtl_writephy(tp, 0x05, 0x8b80);
3289 rtl_w0w1_phy(tp, 0x06, 0x0006, 0x0000);
3290 rtl_writephy(tp, 0x1f, 0x0000);
3292 /* PHY auto speed down */
3293 rtl_writephy(tp, 0x1f, 0x0007);
3294 rtl_writephy(tp, 0x1e, 0x002d);
3295 rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
3296 rtl_writephy(tp, 0x1f, 0x0000);
3297 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3299 /* Improve 10M EEE waveform */
3300 rtl_writephy(tp, 0x1f, 0x0005);
3301 rtl_writephy(tp, 0x05, 0x8b86);
3302 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3303 rtl_writephy(tp, 0x1f, 0x0000);
3305 rtl8168f_config_eee_phy(tp);
3309 static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp)
3311 static const struct phy_reg phy_reg_init[] = {
3312 /* Channel estimation fine tune */
3317 /* Modify green table for giga & fnet */
3334 /* Modify green table for 10M */
3340 /* Disable hiimpedance detection (RTCT) */
3346 rtl_apply_firmware(tp);
3348 rtl_writephy_batch(tp, phy_reg_init);
3350 rtl8168f_hw_phy_config(tp);
3352 /* Improve 2-pair detection performance */
3353 rtl_writephy(tp, 0x1f, 0x0005);
3354 rtl_writephy(tp, 0x05, 0x8b85);
3355 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3356 rtl_writephy(tp, 0x1f, 0x0000);
3359 static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp)
3361 rtl_apply_firmware(tp);
3363 rtl8168f_hw_phy_config(tp);
3366 static void rtl8411_hw_phy_config(struct rtl8169_private *tp)
3368 static const struct phy_reg phy_reg_init[] = {
3369 /* Channel estimation fine tune */
3374 /* Modify green table for giga & fnet */
3391 /* Modify green table for 10M */
3397 /* Disable hiimpedance detection (RTCT) */
3404 rtl_apply_firmware(tp);
3406 rtl8168f_hw_phy_config(tp);
3408 /* Improve 2-pair detection performance */
3409 rtl_writephy(tp, 0x1f, 0x0005);
3410 rtl_writephy(tp, 0x05, 0x8b85);
3411 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3412 rtl_writephy(tp, 0x1f, 0x0000);
3414 rtl_writephy_batch(tp, phy_reg_init);
3416 /* Modify green table for giga */
3417 rtl_writephy(tp, 0x1f, 0x0005);
3418 rtl_writephy(tp, 0x05, 0x8b54);
3419 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
3420 rtl_writephy(tp, 0x05, 0x8b5d);
3421 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
3422 rtl_writephy(tp, 0x05, 0x8a7c);
3423 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3424 rtl_writephy(tp, 0x05, 0x8a7f);
3425 rtl_w0w1_phy(tp, 0x06, 0x0100, 0x0000);
3426 rtl_writephy(tp, 0x05, 0x8a82);
3427 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3428 rtl_writephy(tp, 0x05, 0x8a85);
3429 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3430 rtl_writephy(tp, 0x05, 0x8a88);
3431 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3432 rtl_writephy(tp, 0x1f, 0x0000);
3434 /* uc same-seed solution */
3435 rtl_writephy(tp, 0x1f, 0x0005);
3436 rtl_writephy(tp, 0x05, 0x8b85);
3437 rtl_w0w1_phy(tp, 0x06, 0x8000, 0x0000);
3438 rtl_writephy(tp, 0x1f, 0x0000);
3441 rtl_writephy(tp, 0x1f, 0x0003);
3442 rtl_w0w1_phy(tp, 0x19, 0x0000, 0x0001);
3443 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0400);
3444 rtl_writephy(tp, 0x1f, 0x0000);
3447 static void rtl8168g_disable_aldps(struct rtl8169_private *tp)
3449 phy_modify_paged(tp->phydev, 0x0a43, 0x10, BIT(2), 0);
3452 static void rtl8168g_phy_adjust_10m_aldps(struct rtl8169_private *tp)
3454 struct phy_device *phydev = tp->phydev;
3456 phy_modify_paged(phydev, 0x0bcc, 0x14, BIT(8), 0);
3457 phy_modify_paged(phydev, 0x0a44, 0x11, 0, BIT(7) | BIT(6));
3458 phy_write(phydev, 0x1f, 0x0a43);
3459 phy_write(phydev, 0x13, 0x8084);
3460 phy_clear_bits(phydev, 0x14, BIT(14) | BIT(13));
3461 phy_set_bits(phydev, 0x10, BIT(12) | BIT(1) | BIT(0));
3463 phy_write(phydev, 0x1f, 0x0000);
3466 static void rtl8168g_1_hw_phy_config(struct rtl8169_private *tp)
3470 rtl_apply_firmware(tp);
3472 ret = phy_read_paged(tp->phydev, 0x0a46, 0x10);
3474 phy_modify_paged(tp->phydev, 0x0bcc, 0x12, BIT(15), 0);
3476 phy_modify_paged(tp->phydev, 0x0bcc, 0x12, 0, BIT(15));
3478 ret = phy_read_paged(tp->phydev, 0x0a46, 0x13);
3480 phy_modify_paged(tp->phydev, 0x0c41, 0x12, 0, BIT(1));
3482 phy_modify_paged(tp->phydev, 0x0c41, 0x12, BIT(1), 0);
3484 /* Enable PHY auto speed down */
3485 phy_modify_paged(tp->phydev, 0x0a44, 0x11, 0, BIT(3) | BIT(2));
3487 rtl8168g_phy_adjust_10m_aldps(tp);
3489 /* EEE auto-fallback function */
3490 phy_modify_paged(tp->phydev, 0x0a4b, 0x11, 0, BIT(2));
3492 /* Enable UC LPF tune function */
3493 rtl_writephy(tp, 0x1f, 0x0a43);
3494 rtl_writephy(tp, 0x13, 0x8012);
3495 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3497 phy_modify_paged(tp->phydev, 0x0c42, 0x11, BIT(13), BIT(14));
3499 /* Improve SWR Efficiency */
3500 rtl_writephy(tp, 0x1f, 0x0bcd);
3501 rtl_writephy(tp, 0x14, 0x5065);
3502 rtl_writephy(tp, 0x14, 0xd065);
3503 rtl_writephy(tp, 0x1f, 0x0bc8);
3504 rtl_writephy(tp, 0x11, 0x5655);
3505 rtl_writephy(tp, 0x1f, 0x0bcd);
3506 rtl_writephy(tp, 0x14, 0x1065);
3507 rtl_writephy(tp, 0x14, 0x9065);
3508 rtl_writephy(tp, 0x14, 0x1065);
3509 rtl_writephy(tp, 0x1f, 0x0000);
3511 rtl8168g_disable_aldps(tp);
3512 rtl8168g_config_eee_phy(tp);
3516 static void rtl8168g_2_hw_phy_config(struct rtl8169_private *tp)
3518 rtl_apply_firmware(tp);
3519 rtl8168g_config_eee_phy(tp);
3523 static void rtl8168h_1_hw_phy_config(struct rtl8169_private *tp)
3528 rtl_apply_firmware(tp);
3530 /* CHN EST parameters adjust - giga master */
3531 rtl_writephy(tp, 0x1f, 0x0a43);
3532 rtl_writephy(tp, 0x13, 0x809b);
3533 rtl_w0w1_phy(tp, 0x14, 0x8000, 0xf800);
3534 rtl_writephy(tp, 0x13, 0x80a2);
3535 rtl_w0w1_phy(tp, 0x14, 0x8000, 0xff00);
3536 rtl_writephy(tp, 0x13, 0x80a4);
3537 rtl_w0w1_phy(tp, 0x14, 0x8500, 0xff00);
3538 rtl_writephy(tp, 0x13, 0x809c);
3539 rtl_w0w1_phy(tp, 0x14, 0xbd00, 0xff00);
3540 rtl_writephy(tp, 0x1f, 0x0000);
3542 /* CHN EST parameters adjust - giga slave */
3543 rtl_writephy(tp, 0x1f, 0x0a43);
3544 rtl_writephy(tp, 0x13, 0x80ad);
3545 rtl_w0w1_phy(tp, 0x14, 0x7000, 0xf800);
3546 rtl_writephy(tp, 0x13, 0x80b4);
3547 rtl_w0w1_phy(tp, 0x14, 0x5000, 0xff00);
3548 rtl_writephy(tp, 0x13, 0x80ac);
3549 rtl_w0w1_phy(tp, 0x14, 0x4000, 0xff00);
3550 rtl_writephy(tp, 0x1f, 0x0000);
3552 /* CHN EST parameters adjust - fnet */
3553 rtl_writephy(tp, 0x1f, 0x0a43);
3554 rtl_writephy(tp, 0x13, 0x808e);
3555 rtl_w0w1_phy(tp, 0x14, 0x1200, 0xff00);
3556 rtl_writephy(tp, 0x13, 0x8090);
3557 rtl_w0w1_phy(tp, 0x14, 0xe500, 0xff00);
3558 rtl_writephy(tp, 0x13, 0x8092);
3559 rtl_w0w1_phy(tp, 0x14, 0x9f00, 0xff00);
3560 rtl_writephy(tp, 0x1f, 0x0000);
3562 /* enable R-tune & PGA-retune function */
3564 rtl_writephy(tp, 0x1f, 0x0a46);
3565 data = rtl_readphy(tp, 0x13);
3568 dout_tapbin |= data;
3569 data = rtl_readphy(tp, 0x12);
3572 dout_tapbin |= data;
3573 dout_tapbin = ~(dout_tapbin^0x08);
3575 dout_tapbin &= 0xf000;
3576 rtl_writephy(tp, 0x1f, 0x0a43);
3577 rtl_writephy(tp, 0x13, 0x827a);
3578 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3579 rtl_writephy(tp, 0x13, 0x827b);
3580 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3581 rtl_writephy(tp, 0x13, 0x827c);
3582 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3583 rtl_writephy(tp, 0x13, 0x827d);
3584 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3586 rtl_writephy(tp, 0x1f, 0x0a43);
3587 rtl_writephy(tp, 0x13, 0x0811);
3588 rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
3589 rtl_writephy(tp, 0x1f, 0x0a42);
3590 rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
3591 rtl_writephy(tp, 0x1f, 0x0000);
3593 /* enable GPHY 10M */
3594 phy_modify_paged(tp->phydev, 0x0a44, 0x11, 0, BIT(11));
3596 /* SAR ADC performance */
3597 phy_modify_paged(tp->phydev, 0x0bca, 0x17, BIT(12) | BIT(13), BIT(14));
3599 rtl_writephy(tp, 0x1f, 0x0a43);
3600 rtl_writephy(tp, 0x13, 0x803f);
3601 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3602 rtl_writephy(tp, 0x13, 0x8047);
3603 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3604 rtl_writephy(tp, 0x13, 0x804f);
3605 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3606 rtl_writephy(tp, 0x13, 0x8057);
3607 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3608 rtl_writephy(tp, 0x13, 0x805f);
3609 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3610 rtl_writephy(tp, 0x13, 0x8067);
3611 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3612 rtl_writephy(tp, 0x13, 0x806f);
3613 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3614 rtl_writephy(tp, 0x1f, 0x0000);
3616 /* disable phy pfm mode */
3617 phy_modify_paged(tp->phydev, 0x0a44, 0x11, BIT(7), 0);
3619 rtl8168g_disable_aldps(tp);
3620 rtl8168g_config_eee_phy(tp);
3624 static void rtl8168h_2_hw_phy_config(struct rtl8169_private *tp)
3626 u16 ioffset_p3, ioffset_p2, ioffset_p1, ioffset_p0;
3630 rtl_apply_firmware(tp);
3632 /* CHIN EST parameter update */
3633 rtl_writephy(tp, 0x1f, 0x0a43);
3634 rtl_writephy(tp, 0x13, 0x808a);
3635 rtl_w0w1_phy(tp, 0x14, 0x000a, 0x003f);
3636 rtl_writephy(tp, 0x1f, 0x0000);
3638 /* enable R-tune & PGA-retune function */
3639 rtl_writephy(tp, 0x1f, 0x0a43);
3640 rtl_writephy(tp, 0x13, 0x0811);
3641 rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
3642 rtl_writephy(tp, 0x1f, 0x0a42);
3643 rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
3644 rtl_writephy(tp, 0x1f, 0x0000);
3646 /* enable GPHY 10M */
3647 phy_modify_paged(tp->phydev, 0x0a44, 0x11, 0, BIT(11));
3649 r8168_mac_ocp_write(tp, 0xdd02, 0x807d);
3650 data = r8168_mac_ocp_read(tp, 0xdd02);
3651 ioffset_p3 = ((data & 0x80)>>7);
3654 data = r8168_mac_ocp_read(tp, 0xdd00);
3655 ioffset_p3 |= ((data & (0xe000))>>13);
3656 ioffset_p2 = ((data & (0x1e00))>>9);
3657 ioffset_p1 = ((data & (0x01e0))>>5);
3658 ioffset_p0 = ((data & 0x0010)>>4);
3660 ioffset_p0 |= (data & (0x07));
3661 data = (ioffset_p3<<12)|(ioffset_p2<<8)|(ioffset_p1<<4)|(ioffset_p0);
3663 if ((ioffset_p3 != 0x0f) || (ioffset_p2 != 0x0f) ||
3664 (ioffset_p1 != 0x0f) || (ioffset_p0 != 0x0f)) {
3665 rtl_writephy(tp, 0x1f, 0x0bcf);
3666 rtl_writephy(tp, 0x16, data);
3667 rtl_writephy(tp, 0x1f, 0x0000);
3670 /* Modify rlen (TX LPF corner frequency) level */
3671 rtl_writephy(tp, 0x1f, 0x0bcd);
3672 data = rtl_readphy(tp, 0x16);
3677 data = rlen | (rlen<<4) | (rlen<<8) | (rlen<<12);
3678 rtl_writephy(tp, 0x17, data);
3679 rtl_writephy(tp, 0x1f, 0x0bcd);
3680 rtl_writephy(tp, 0x1f, 0x0000);
3682 /* disable phy pfm mode */
3683 phy_modify_paged(tp->phydev, 0x0a44, 0x11, BIT(7), 0);
3685 rtl8168g_disable_aldps(tp);
3686 rtl8168g_config_eee_phy(tp);
3690 static void rtl8168ep_1_hw_phy_config(struct rtl8169_private *tp)
3692 /* Enable PHY auto speed down */
3693 phy_modify_paged(tp->phydev, 0x0a44, 0x11, 0, BIT(3) | BIT(2));
3695 rtl8168g_phy_adjust_10m_aldps(tp);
3697 /* Enable EEE auto-fallback function */
3698 phy_modify_paged(tp->phydev, 0x0a4b, 0x11, 0, BIT(2));
3700 /* Enable UC LPF tune function */
3701 rtl_writephy(tp, 0x1f, 0x0a43);
3702 rtl_writephy(tp, 0x13, 0x8012);
3703 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3704 rtl_writephy(tp, 0x1f, 0x0000);
3706 /* set rg_sel_sdm_rate */
3707 phy_modify_paged(tp->phydev, 0x0c42, 0x11, BIT(13), BIT(14));
3709 rtl8168g_disable_aldps(tp);
3710 rtl8168g_config_eee_phy(tp);
3714 static void rtl8168ep_2_hw_phy_config(struct rtl8169_private *tp)
3716 rtl8168g_phy_adjust_10m_aldps(tp);
3718 /* Enable UC LPF tune function */
3719 rtl_writephy(tp, 0x1f, 0x0a43);
3720 rtl_writephy(tp, 0x13, 0x8012);
3721 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3722 rtl_writephy(tp, 0x1f, 0x0000);
3724 /* Set rg_sel_sdm_rate */
3725 phy_modify_paged(tp->phydev, 0x0c42, 0x11, BIT(13), BIT(14));
3727 /* Channel estimation parameters */
3728 rtl_writephy(tp, 0x1f, 0x0a43);
3729 rtl_writephy(tp, 0x13, 0x80f3);
3730 rtl_w0w1_phy(tp, 0x14, 0x8b00, ~0x8bff);
3731 rtl_writephy(tp, 0x13, 0x80f0);
3732 rtl_w0w1_phy(tp, 0x14, 0x3a00, ~0x3aff);
3733 rtl_writephy(tp, 0x13, 0x80ef);
3734 rtl_w0w1_phy(tp, 0x14, 0x0500, ~0x05ff);
3735 rtl_writephy(tp, 0x13, 0x80f6);
3736 rtl_w0w1_phy(tp, 0x14, 0x6e00, ~0x6eff);
3737 rtl_writephy(tp, 0x13, 0x80ec);
3738 rtl_w0w1_phy(tp, 0x14, 0x6800, ~0x68ff);
3739 rtl_writephy(tp, 0x13, 0x80ed);
3740 rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
3741 rtl_writephy(tp, 0x13, 0x80f2);
3742 rtl_w0w1_phy(tp, 0x14, 0xf400, ~0xf4ff);
3743 rtl_writephy(tp, 0x13, 0x80f4);
3744 rtl_w0w1_phy(tp, 0x14, 0x8500, ~0x85ff);
3745 rtl_writephy(tp, 0x1f, 0x0a43);
3746 rtl_writephy(tp, 0x13, 0x8110);
3747 rtl_w0w1_phy(tp, 0x14, 0xa800, ~0xa8ff);
3748 rtl_writephy(tp, 0x13, 0x810f);
3749 rtl_w0w1_phy(tp, 0x14, 0x1d00, ~0x1dff);
3750 rtl_writephy(tp, 0x13, 0x8111);
3751 rtl_w0w1_phy(tp, 0x14, 0xf500, ~0xf5ff);
3752 rtl_writephy(tp, 0x13, 0x8113);
3753 rtl_w0w1_phy(tp, 0x14, 0x6100, ~0x61ff);
3754 rtl_writephy(tp, 0x13, 0x8115);
3755 rtl_w0w1_phy(tp, 0x14, 0x9200, ~0x92ff);
3756 rtl_writephy(tp, 0x13, 0x810e);
3757 rtl_w0w1_phy(tp, 0x14, 0x0400, ~0x04ff);
3758 rtl_writephy(tp, 0x13, 0x810c);
3759 rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
3760 rtl_writephy(tp, 0x13, 0x810b);
3761 rtl_w0w1_phy(tp, 0x14, 0x5a00, ~0x5aff);
3762 rtl_writephy(tp, 0x1f, 0x0a43);
3763 rtl_writephy(tp, 0x13, 0x80d1);
3764 rtl_w0w1_phy(tp, 0x14, 0xff00, ~0xffff);
3765 rtl_writephy(tp, 0x13, 0x80cd);
3766 rtl_w0w1_phy(tp, 0x14, 0x9e00, ~0x9eff);
3767 rtl_writephy(tp, 0x13, 0x80d3);
3768 rtl_w0w1_phy(tp, 0x14, 0x0e00, ~0x0eff);
3769 rtl_writephy(tp, 0x13, 0x80d5);
3770 rtl_w0w1_phy(tp, 0x14, 0xca00, ~0xcaff);
3771 rtl_writephy(tp, 0x13, 0x80d7);
3772 rtl_w0w1_phy(tp, 0x14, 0x8400, ~0x84ff);
3774 /* Force PWM-mode */
3775 rtl_writephy(tp, 0x1f, 0x0bcd);
3776 rtl_writephy(tp, 0x14, 0x5065);
3777 rtl_writephy(tp, 0x14, 0xd065);
3778 rtl_writephy(tp, 0x1f, 0x0bc8);
3779 rtl_writephy(tp, 0x12, 0x00ed);
3780 rtl_writephy(tp, 0x1f, 0x0bcd);
3781 rtl_writephy(tp, 0x14, 0x1065);
3782 rtl_writephy(tp, 0x14, 0x9065);
3783 rtl_writephy(tp, 0x14, 0x1065);
3784 rtl_writephy(tp, 0x1f, 0x0000);
3786 rtl8168g_disable_aldps(tp);
3787 rtl8168g_config_eee_phy(tp);
3791 static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
3793 static const struct phy_reg phy_reg_init[] = {
3800 rtl_writephy(tp, 0x1f, 0x0000);
3801 rtl_patchphy(tp, 0x11, 1 << 12);
3802 rtl_patchphy(tp, 0x19, 1 << 13);
3803 rtl_patchphy(tp, 0x10, 1 << 15);
3805 rtl_writephy_batch(tp, phy_reg_init);
3808 static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
3810 static const struct phy_reg phy_reg_init[] = {
3824 /* Disable ALDPS before ram code */
3825 rtl_writephy(tp, 0x1f, 0x0000);
3826 rtl_writephy(tp, 0x18, 0x0310);
3829 rtl_apply_firmware(tp);
3831 rtl_writephy_batch(tp, phy_reg_init);
3834 static void rtl8402_hw_phy_config(struct rtl8169_private *tp)
3836 /* Disable ALDPS before setting firmware */
3837 rtl_writephy(tp, 0x1f, 0x0000);
3838 rtl_writephy(tp, 0x18, 0x0310);
3841 rtl_apply_firmware(tp);
3844 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000);
3845 rtl_writephy(tp, 0x1f, 0x0004);
3846 rtl_writephy(tp, 0x10, 0x401f);
3847 rtl_writephy(tp, 0x19, 0x7030);
3848 rtl_writephy(tp, 0x1f, 0x0000);
3851 static void rtl8106e_hw_phy_config(struct rtl8169_private *tp)
3853 static const struct phy_reg phy_reg_init[] = {
3860 /* Disable ALDPS before ram code */
3861 rtl_writephy(tp, 0x1f, 0x0000);
3862 rtl_writephy(tp, 0x18, 0x0310);
3865 rtl_apply_firmware(tp);
3867 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000);
3868 rtl_writephy_batch(tp, phy_reg_init);
3870 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000);
3873 static void rtl_hw_phy_config(struct net_device *dev)
3875 static const rtl_generic_fct phy_configs[] = {
3877 [RTL_GIGA_MAC_VER_02] = rtl8169s_hw_phy_config,
3878 [RTL_GIGA_MAC_VER_03] = rtl8169s_hw_phy_config,
3879 [RTL_GIGA_MAC_VER_04] = rtl8169sb_hw_phy_config,
3880 [RTL_GIGA_MAC_VER_05] = rtl8169scd_hw_phy_config,
3881 [RTL_GIGA_MAC_VER_06] = rtl8169sce_hw_phy_config,
3882 /* PCI-E devices. */
3883 [RTL_GIGA_MAC_VER_07] = rtl8102e_hw_phy_config,
3884 [RTL_GIGA_MAC_VER_08] = rtl8102e_hw_phy_config,
3885 [RTL_GIGA_MAC_VER_09] = rtl8102e_hw_phy_config,
3886 [RTL_GIGA_MAC_VER_10] = NULL,
3887 [RTL_GIGA_MAC_VER_11] = rtl8168bb_hw_phy_config,
3888 [RTL_GIGA_MAC_VER_12] = rtl8168bef_hw_phy_config,
3889 [RTL_GIGA_MAC_VER_13] = NULL,
3890 [RTL_GIGA_MAC_VER_14] = NULL,
3891 [RTL_GIGA_MAC_VER_15] = NULL,
3892 [RTL_GIGA_MAC_VER_16] = NULL,
3893 [RTL_GIGA_MAC_VER_17] = rtl8168bef_hw_phy_config,
3894 [RTL_GIGA_MAC_VER_18] = rtl8168cp_1_hw_phy_config,
3895 [RTL_GIGA_MAC_VER_19] = rtl8168c_1_hw_phy_config,
3896 [RTL_GIGA_MAC_VER_20] = rtl8168c_2_hw_phy_config,
3897 [RTL_GIGA_MAC_VER_21] = rtl8168c_3_hw_phy_config,
3898 [RTL_GIGA_MAC_VER_22] = rtl8168c_4_hw_phy_config,
3899 [RTL_GIGA_MAC_VER_23] = rtl8168cp_2_hw_phy_config,
3900 [RTL_GIGA_MAC_VER_24] = rtl8168cp_2_hw_phy_config,
3901 [RTL_GIGA_MAC_VER_25] = rtl8168d_1_hw_phy_config,
3902 [RTL_GIGA_MAC_VER_26] = rtl8168d_2_hw_phy_config,
3903 [RTL_GIGA_MAC_VER_27] = rtl8168d_3_hw_phy_config,
3904 [RTL_GIGA_MAC_VER_28] = rtl8168d_4_hw_phy_config,
3905 [RTL_GIGA_MAC_VER_29] = rtl8105e_hw_phy_config,
3906 [RTL_GIGA_MAC_VER_30] = rtl8105e_hw_phy_config,
3907 [RTL_GIGA_MAC_VER_31] = NULL,
3908 [RTL_GIGA_MAC_VER_32] = rtl8168e_1_hw_phy_config,
3909 [RTL_GIGA_MAC_VER_33] = rtl8168e_1_hw_phy_config,
3910 [RTL_GIGA_MAC_VER_34] = rtl8168e_2_hw_phy_config,
3911 [RTL_GIGA_MAC_VER_35] = rtl8168f_1_hw_phy_config,
3912 [RTL_GIGA_MAC_VER_36] = rtl8168f_2_hw_phy_config,
3913 [RTL_GIGA_MAC_VER_37] = rtl8402_hw_phy_config,
3914 [RTL_GIGA_MAC_VER_38] = rtl8411_hw_phy_config,
3915 [RTL_GIGA_MAC_VER_39] = rtl8106e_hw_phy_config,
3916 [RTL_GIGA_MAC_VER_40] = rtl8168g_1_hw_phy_config,
3917 [RTL_GIGA_MAC_VER_41] = NULL,
3918 [RTL_GIGA_MAC_VER_42] = rtl8168g_2_hw_phy_config,
3919 [RTL_GIGA_MAC_VER_43] = rtl8168g_2_hw_phy_config,
3920 [RTL_GIGA_MAC_VER_44] = rtl8168g_2_hw_phy_config,
3921 [RTL_GIGA_MAC_VER_45] = rtl8168h_1_hw_phy_config,
3922 [RTL_GIGA_MAC_VER_46] = rtl8168h_2_hw_phy_config,
3923 [RTL_GIGA_MAC_VER_47] = rtl8168h_1_hw_phy_config,
3924 [RTL_GIGA_MAC_VER_48] = rtl8168h_2_hw_phy_config,
3925 [RTL_GIGA_MAC_VER_49] = rtl8168ep_1_hw_phy_config,
3926 [RTL_GIGA_MAC_VER_50] = rtl8168ep_2_hw_phy_config,
3927 [RTL_GIGA_MAC_VER_51] = rtl8168ep_2_hw_phy_config,
3929 struct rtl8169_private *tp = netdev_priv(dev);
3931 if (phy_configs[tp->mac_version])
3932 phy_configs[tp->mac_version](tp);
3935 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
3937 if (!test_and_set_bit(flag, tp->wk.flags))
3938 schedule_work(&tp->wk.work);
3941 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
3943 rtl_hw_phy_config(dev);
3945 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
3946 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
3947 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
3948 netif_dbg(tp, drv, dev,
3949 "Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3950 RTL_W8(tp, 0x82, 0x01);
3953 /* We may have called phy_speed_down before */
3954 phy_speed_up(tp->phydev);
3956 genphy_soft_reset(tp->phydev);
3959 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
3963 rtl_unlock_config_regs(tp);
3965 RTL_W32(tp, MAC4, addr[4] | addr[5] << 8);
3968 RTL_W32(tp, MAC0, addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24);
3971 if (tp->mac_version == RTL_GIGA_MAC_VER_34)
3972 rtl_rar_exgmac_set(tp, addr);
3974 rtl_lock_config_regs(tp);
3976 rtl_unlock_work(tp);
3979 static int rtl_set_mac_address(struct net_device *dev, void *p)
3981 struct rtl8169_private *tp = netdev_priv(dev);
3982 struct device *d = tp_to_dev(tp);
3985 ret = eth_mac_addr(dev, p);
3989 pm_runtime_get_noresume(d);
3991 if (pm_runtime_active(d))
3992 rtl_rar_set(tp, dev->dev_addr);
3994 pm_runtime_put_noidle(d);
3999 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
4001 struct rtl8169_private *tp = netdev_priv(dev);
4003 if (!netif_running(dev))
4006 return phy_mii_ioctl(tp->phydev, ifr, cmd);
4009 static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
4011 switch (tp->mac_version) {
4012 case RTL_GIGA_MAC_VER_25:
4013 case RTL_GIGA_MAC_VER_26:
4014 case RTL_GIGA_MAC_VER_29:
4015 case RTL_GIGA_MAC_VER_30:
4016 case RTL_GIGA_MAC_VER_32:
4017 case RTL_GIGA_MAC_VER_33:
4018 case RTL_GIGA_MAC_VER_34:
4019 case RTL_GIGA_MAC_VER_37 ... RTL_GIGA_MAC_VER_51:
4020 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) |
4021 AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
4028 static void rtl_pll_power_down(struct rtl8169_private *tp)
4030 if (r8168_check_dash(tp))
4033 if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
4034 tp->mac_version == RTL_GIGA_MAC_VER_33)
4035 rtl_ephy_write(tp, 0x19, 0xff64);
4037 if (device_may_wakeup(tp_to_dev(tp))) {
4038 phy_speed_down(tp->phydev, false);
4039 rtl_wol_suspend_quirk(tp);
4043 switch (tp->mac_version) {
4044 case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_33:
4045 case RTL_GIGA_MAC_VER_37:
4046 case RTL_GIGA_MAC_VER_39:
4047 case RTL_GIGA_MAC_VER_43:
4048 case RTL_GIGA_MAC_VER_44:
4049 case RTL_GIGA_MAC_VER_45:
4050 case RTL_GIGA_MAC_VER_46:
4051 case RTL_GIGA_MAC_VER_47:
4052 case RTL_GIGA_MAC_VER_48:
4053 case RTL_GIGA_MAC_VER_50:
4054 case RTL_GIGA_MAC_VER_51:
4055 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80);
4057 case RTL_GIGA_MAC_VER_40:
4058 case RTL_GIGA_MAC_VER_41:
4059 case RTL_GIGA_MAC_VER_49:
4060 rtl_eri_clear_bits(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000);
4061 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80);
4068 static void rtl_pll_power_up(struct rtl8169_private *tp)
4070 switch (tp->mac_version) {
4071 case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_33:
4072 case RTL_GIGA_MAC_VER_37:
4073 case RTL_GIGA_MAC_VER_39:
4074 case RTL_GIGA_MAC_VER_43:
4075 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0x80);
4077 case RTL_GIGA_MAC_VER_44:
4078 case RTL_GIGA_MAC_VER_45:
4079 case RTL_GIGA_MAC_VER_46:
4080 case RTL_GIGA_MAC_VER_47:
4081 case RTL_GIGA_MAC_VER_48:
4082 case RTL_GIGA_MAC_VER_50:
4083 case RTL_GIGA_MAC_VER_51:
4084 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0);
4086 case RTL_GIGA_MAC_VER_40:
4087 case RTL_GIGA_MAC_VER_41:
4088 case RTL_GIGA_MAC_VER_49:
4089 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0);
4090 rtl_eri_set_bits(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000);
4096 phy_resume(tp->phydev);
4097 /* give MAC/PHY some time to resume */
4101 static void rtl_init_rxcfg(struct rtl8169_private *tp)
4103 switch (tp->mac_version) {
4104 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
4105 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
4106 RTL_W32(tp, RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
4108 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
4109 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36:
4110 case RTL_GIGA_MAC_VER_38:
4111 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
4113 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
4114 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF);
4117 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_DMA_BURST);
4122 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
4124 tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0;
4127 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
4129 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
4130 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | Jumbo_En1);
4131 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_512B);
4134 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
4136 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
4137 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~Jumbo_En1);
4138 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4141 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
4143 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
4146 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
4148 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
4151 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
4153 RTL_W8(tp, MaxTxPacketSize, 0x3f);
4154 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
4155 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | 0x01);
4156 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_512B);
4159 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
4161 RTL_W8(tp, MaxTxPacketSize, 0x0c);
4162 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
4163 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~0x01);
4164 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4167 static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp)
4169 rtl_tx_performance_tweak(tp,
4170 PCI_EXP_DEVCTL_READRQ_512B | PCI_EXP_DEVCTL_NOSNOOP_EN);
4173 static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp)
4175 rtl_tx_performance_tweak(tp,
4176 PCI_EXP_DEVCTL_READRQ_4096B | PCI_EXP_DEVCTL_NOSNOOP_EN);
4179 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
4181 r8168b_0_hw_jumbo_enable(tp);
4183 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | (1 << 0));
4186 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
4188 r8168b_0_hw_jumbo_disable(tp);
4190 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0));
4193 static void rtl_hw_jumbo_enable(struct rtl8169_private *tp)
4195 rtl_unlock_config_regs(tp);
4196 switch (tp->mac_version) {
4197 case RTL_GIGA_MAC_VER_11:
4198 r8168b_0_hw_jumbo_enable(tp);
4200 case RTL_GIGA_MAC_VER_12:
4201 case RTL_GIGA_MAC_VER_17:
4202 r8168b_1_hw_jumbo_enable(tp);
4204 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_26:
4205 r8168c_hw_jumbo_enable(tp);
4207 case RTL_GIGA_MAC_VER_27 ... RTL_GIGA_MAC_VER_28:
4208 r8168dp_hw_jumbo_enable(tp);
4210 case RTL_GIGA_MAC_VER_31 ... RTL_GIGA_MAC_VER_34:
4211 r8168e_hw_jumbo_enable(tp);
4216 rtl_lock_config_regs(tp);
4219 static void rtl_hw_jumbo_disable(struct rtl8169_private *tp)
4221 rtl_unlock_config_regs(tp);
4222 switch (tp->mac_version) {
4223 case RTL_GIGA_MAC_VER_11:
4224 r8168b_0_hw_jumbo_disable(tp);
4226 case RTL_GIGA_MAC_VER_12:
4227 case RTL_GIGA_MAC_VER_17:
4228 r8168b_1_hw_jumbo_disable(tp);
4230 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_26:
4231 r8168c_hw_jumbo_disable(tp);
4233 case RTL_GIGA_MAC_VER_27 ... RTL_GIGA_MAC_VER_28:
4234 r8168dp_hw_jumbo_disable(tp);
4236 case RTL_GIGA_MAC_VER_31 ... RTL_GIGA_MAC_VER_34:
4237 r8168e_hw_jumbo_disable(tp);
4242 rtl_lock_config_regs(tp);
4245 DECLARE_RTL_COND(rtl_chipcmd_cond)
4247 return RTL_R8(tp, ChipCmd) & CmdReset;
4250 static void rtl_hw_reset(struct rtl8169_private *tp)
4252 RTL_W8(tp, ChipCmd, CmdReset);
4254 rtl_udelay_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100);
4257 static int rtl_fw_request_firmware(struct rtl_fw *rtl_fw)
4261 rc = request_firmware(&rtl_fw->fw, rtl_fw->fw_name, rtl_fw->dev);
4265 if (!rtl_fw_format_ok(rtl_fw) || !rtl_fw_data_ok(rtl_fw)) {
4266 release_firmware(rtl_fw->fw);
4272 dev_err(rtl_fw->dev, "Unable to load firmware %s (%d)\n",
4273 rtl_fw->fw_name, rc);
4277 static void rtl_request_firmware(struct rtl8169_private *tp)
4279 struct rtl_fw *rtl_fw;
4281 /* firmware loaded already or no firmware available */
4282 if (tp->rtl_fw || !tp->fw_name)
4285 rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
4287 netif_warn(tp, ifup, tp->dev, "Unable to load firmware, out of memory\n");
4291 rtl_fw->phy_write = rtl_writephy;
4292 rtl_fw->phy_read = rtl_readphy;
4293 rtl_fw->mac_mcu_write = mac_mcu_write;
4294 rtl_fw->mac_mcu_read = mac_mcu_read;
4295 rtl_fw->fw_name = tp->fw_name;
4296 rtl_fw->dev = tp_to_dev(tp);
4298 if (rtl_fw_request_firmware(rtl_fw))
4301 tp->rtl_fw = rtl_fw;
4304 static void rtl_rx_close(struct rtl8169_private *tp)
4306 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
4309 DECLARE_RTL_COND(rtl_npq_cond)
4311 return RTL_R8(tp, TxPoll) & NPQ;
4314 DECLARE_RTL_COND(rtl_txcfg_empty_cond)
4316 return RTL_R32(tp, TxConfig) & TXCFG_EMPTY;
4319 static void rtl8169_hw_reset(struct rtl8169_private *tp)
4321 /* Disable interrupts */
4322 rtl8169_irq_mask_and_ack(tp);
4326 switch (tp->mac_version) {
4327 case RTL_GIGA_MAC_VER_27:
4328 case RTL_GIGA_MAC_VER_28:
4329 case RTL_GIGA_MAC_VER_31:
4330 rtl_udelay_loop_wait_low(tp, &rtl_npq_cond, 20, 42*42);
4332 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
4333 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
4334 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
4335 rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);
4338 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
4346 static void rtl_set_tx_config_registers(struct rtl8169_private *tp)
4348 u32 val = TX_DMA_BURST << TxDMAShift |
4349 InterFrameGap << TxInterFrameGapShift;
4351 if (tp->mac_version >= RTL_GIGA_MAC_VER_34 &&
4352 tp->mac_version != RTL_GIGA_MAC_VER_39)
4353 val |= TXCFG_AUTO_FIFO;
4355 RTL_W32(tp, TxConfig, val);
4358 static void rtl_set_rx_max_size(struct rtl8169_private *tp)
4360 /* Low hurts. Let's disable the filtering. */
4361 RTL_W16(tp, RxMaxSize, R8169_RX_BUF_SIZE + 1);
4364 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp)
4367 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
4368 * register to be written before TxDescAddrLow to work.
4369 * Switching from MMIO to I/O access fixes the issue as well.
4371 RTL_W32(tp, TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
4372 RTL_W32(tp, TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
4373 RTL_W32(tp, RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
4374 RTL_W32(tp, RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
4377 static void rtl8169_set_magic_reg(struct rtl8169_private *tp, unsigned mac_version)
4381 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
4383 else if (tp->mac_version == RTL_GIGA_MAC_VER_06)
4388 if (RTL_R8(tp, Config2) & PCI_Clock_66MHz)
4391 RTL_W32(tp, 0x7c, val);
4394 static void rtl_set_rx_mode(struct net_device *dev)
4396 struct rtl8169_private *tp = netdev_priv(dev);
4397 u32 mc_filter[2]; /* Multicast hash filter */
4401 if (dev->flags & IFF_PROMISC) {
4402 /* Unconditionally log net taps. */
4403 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
4405 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
4407 mc_filter[1] = mc_filter[0] = 0xffffffff;
4408 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
4409 (dev->flags & IFF_ALLMULTI)) {
4410 /* Too many to filter perfectly -- accept all multicasts. */
4411 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
4412 mc_filter[1] = mc_filter[0] = 0xffffffff;
4414 struct netdev_hw_addr *ha;
4416 rx_mode = AcceptBroadcast | AcceptMyPhys;
4417 mc_filter[1] = mc_filter[0] = 0;
4418 netdev_for_each_mc_addr(ha, dev) {
4419 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
4420 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
4421 rx_mode |= AcceptMulticast;
4425 if (dev->features & NETIF_F_RXALL)
4426 rx_mode |= (AcceptErr | AcceptRunt);
4428 tmp = (RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK) | rx_mode;
4430 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
4431 u32 data = mc_filter[0];
4433 mc_filter[0] = swab32(mc_filter[1]);
4434 mc_filter[1] = swab32(data);
4437 if (tp->mac_version == RTL_GIGA_MAC_VER_35)
4438 mc_filter[1] = mc_filter[0] = 0xffffffff;
4440 RTL_W32(tp, MAR0 + 4, mc_filter[1]);
4441 RTL_W32(tp, MAR0 + 0, mc_filter[0]);
4443 RTL_W32(tp, RxConfig, tmp);
4446 static void rtl_hw_start(struct rtl8169_private *tp)
4448 rtl_unlock_config_regs(tp);
4452 rtl_set_rx_max_size(tp);
4453 rtl_set_rx_tx_desc_registers(tp);
4454 rtl_lock_config_regs(tp);
4456 /* disable interrupt coalescing */
4457 RTL_W16(tp, IntrMitigate, 0x0000);
4458 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
4459 RTL_R8(tp, IntrMask);
4460 RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb);
4462 rtl_set_tx_config_registers(tp);
4464 rtl_set_rx_mode(tp->dev);
4465 /* no early-rx interrupts */
4466 RTL_W16(tp, MultiIntr, RTL_R16(tp, MultiIntr) & 0xf000);
4470 static void rtl_hw_start_8169(struct rtl8169_private *tp)
4472 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
4473 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4475 RTL_W8(tp, EarlyTxThres, NoEarlyTx);
4477 tp->cp_cmd |= PCIMulRW;
4479 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4480 tp->mac_version == RTL_GIGA_MAC_VER_03) {
4481 netif_dbg(tp, drv, tp->dev,
4482 "Set MAC Reg C+CR Offset 0xe0. Bit 3 and Bit 14 MUST be 1\n");
4483 tp->cp_cmd |= (1 << 14);
4486 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4488 rtl8169_set_magic_reg(tp, tp->mac_version);
4490 RTL_W32(tp, RxMissed, 0);
4493 DECLARE_RTL_COND(rtl_csiar_cond)
4495 return RTL_R32(tp, CSIAR) & CSIAR_FLAG;
4498 static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)
4500 u32 func = PCI_FUNC(tp->pci_dev->devfn);
4502 RTL_W32(tp, CSIDR, value);
4503 RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
4504 CSIAR_BYTE_ENABLE | func << 16);
4506 rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
4509 static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)
4511 u32 func = PCI_FUNC(tp->pci_dev->devfn);
4513 RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) | func << 16 |
4516 return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
4517 RTL_R32(tp, CSIDR) : ~0;
4520 static void rtl_csi_access_enable(struct rtl8169_private *tp, u8 val)
4522 struct pci_dev *pdev = tp->pci_dev;
4525 /* According to Realtek the value at config space address 0x070f
4526 * controls the L0s/L1 entrance latency. We try standard ECAM access
4527 * first and if it fails fall back to CSI.
4529 if (pdev->cfg_size > 0x070f &&
4530 pci_write_config_byte(pdev, 0x070f, val) == PCIBIOS_SUCCESSFUL)
4533 netdev_notice_once(tp->dev,
4534 "No native access to PCI extended config space, falling back to CSI\n");
4535 csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff;
4536 rtl_csi_write(tp, 0x070c, csi | val << 24);
4539 static void rtl_set_def_aspm_entry_latency(struct rtl8169_private *tp)
4541 rtl_csi_access_enable(tp, 0x27);
4545 unsigned int offset;
4550 static void __rtl_ephy_init(struct rtl8169_private *tp,
4551 const struct ephy_info *e, int len)
4556 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits;
4557 rtl_ephy_write(tp, e->offset, w);
4562 #define rtl_ephy_init(tp, a) __rtl_ephy_init(tp, a, ARRAY_SIZE(a))
4564 static void rtl_disable_clock_request(struct rtl8169_private *tp)
4566 pcie_capability_clear_word(tp->pci_dev, PCI_EXP_LNKCTL,
4567 PCI_EXP_LNKCTL_CLKREQ_EN);
4570 static void rtl_enable_clock_request(struct rtl8169_private *tp)
4572 pcie_capability_set_word(tp->pci_dev, PCI_EXP_LNKCTL,
4573 PCI_EXP_LNKCTL_CLKREQ_EN);
4576 static void rtl_pcie_state_l2l3_disable(struct rtl8169_private *tp)
4578 /* work around an issue when PCI reset occurs during L2/L3 state */
4579 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Rdy_to_L23);
4582 static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable)
4585 RTL_W8(tp, Config5, RTL_R8(tp, Config5) | ASPM_en);
4586 RTL_W8(tp, Config2, RTL_R8(tp, Config2) | ClkReqEn);
4588 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
4589 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
4595 static void rtl_set_fifo_size(struct rtl8169_private *tp, u16 rx_stat,
4596 u16 tx_stat, u16 rx_dyn, u16 tx_dyn)
4598 /* Usage of dynamic vs. static FIFO is controlled by bit
4599 * TXCFG_AUTO_FIFO. Exact meaning of FIFO values isn't known.
4601 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, (rx_stat << 16) | rx_dyn);
4602 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, (tx_stat << 16) | tx_dyn);
4605 static void rtl8168g_set_pause_thresholds(struct rtl8169_private *tp,
4608 /* FIFO thresholds for pause flow control */
4609 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, low);
4610 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, high);
4613 static void rtl_hw_start_8168bb(struct rtl8169_private *tp)
4615 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4617 tp->cp_cmd &= CPCMD_QUIRK_MASK;
4618 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4620 if (tp->dev->mtu <= ETH_DATA_LEN) {
4621 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B |
4622 PCI_EXP_DEVCTL_NOSNOOP_EN);
4626 static void rtl_hw_start_8168bef(struct rtl8169_private *tp)
4628 rtl_hw_start_8168bb(tp);
4630 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4632 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0));
4635 static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)
4637 RTL_W8(tp, Config1, RTL_R8(tp, Config1) | Speed_down);
4639 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4641 if (tp->dev->mtu <= ETH_DATA_LEN)
4642 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4644 rtl_disable_clock_request(tp);
4646 tp->cp_cmd &= CPCMD_QUIRK_MASK;
4647 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4650 static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp)
4652 static const struct ephy_info e_info_8168cp[] = {
4653 { 0x01, 0, 0x0001 },
4654 { 0x02, 0x0800, 0x1000 },
4655 { 0x03, 0, 0x0042 },
4656 { 0x06, 0x0080, 0x0000 },
4660 rtl_set_def_aspm_entry_latency(tp);
4662 rtl_ephy_init(tp, e_info_8168cp);
4664 __rtl_hw_start_8168cp(tp);
4667 static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)
4669 rtl_set_def_aspm_entry_latency(tp);
4671 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4673 if (tp->dev->mtu <= ETH_DATA_LEN)
4674 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4676 tp->cp_cmd &= CPCMD_QUIRK_MASK;
4677 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4680 static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)
4682 rtl_set_def_aspm_entry_latency(tp);
4684 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4687 RTL_W8(tp, DBG_REG, 0x20);
4689 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4691 if (tp->dev->mtu <= ETH_DATA_LEN)
4692 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4694 tp->cp_cmd &= CPCMD_QUIRK_MASK;
4695 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4698 static void rtl_hw_start_8168c_1(struct rtl8169_private *tp)
4700 static const struct ephy_info e_info_8168c_1[] = {
4701 { 0x02, 0x0800, 0x1000 },
4702 { 0x03, 0, 0x0002 },
4703 { 0x06, 0x0080, 0x0000 }
4706 rtl_set_def_aspm_entry_latency(tp);
4708 RTL_W8(tp, DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
4710 rtl_ephy_init(tp, e_info_8168c_1);
4712 __rtl_hw_start_8168cp(tp);
4715 static void rtl_hw_start_8168c_2(struct rtl8169_private *tp)
4717 static const struct ephy_info e_info_8168c_2[] = {
4718 { 0x01, 0, 0x0001 },
4719 { 0x03, 0x0400, 0x0220 }
4722 rtl_set_def_aspm_entry_latency(tp);
4724 rtl_ephy_init(tp, e_info_8168c_2);
4726 __rtl_hw_start_8168cp(tp);
4729 static void rtl_hw_start_8168c_3(struct rtl8169_private *tp)
4731 rtl_hw_start_8168c_2(tp);
4734 static void rtl_hw_start_8168c_4(struct rtl8169_private *tp)
4736 rtl_set_def_aspm_entry_latency(tp);
4738 __rtl_hw_start_8168cp(tp);
4741 static void rtl_hw_start_8168d(struct rtl8169_private *tp)
4743 rtl_set_def_aspm_entry_latency(tp);
4745 rtl_disable_clock_request(tp);
4747 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4749 if (tp->dev->mtu <= ETH_DATA_LEN)
4750 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4752 tp->cp_cmd &= CPCMD_QUIRK_MASK;
4753 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4756 static void rtl_hw_start_8168dp(struct rtl8169_private *tp)
4758 rtl_set_def_aspm_entry_latency(tp);
4760 if (tp->dev->mtu <= ETH_DATA_LEN)
4761 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4763 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4765 rtl_disable_clock_request(tp);
4768 static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
4770 static const struct ephy_info e_info_8168d_4[] = {
4771 { 0x0b, 0x0000, 0x0048 },
4772 { 0x19, 0x0020, 0x0050 },
4773 { 0x0c, 0x0100, 0x0020 }
4776 rtl_set_def_aspm_entry_latency(tp);
4778 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4780 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4782 rtl_ephy_init(tp, e_info_8168d_4);
4784 rtl_enable_clock_request(tp);
4787 static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)
4789 static const struct ephy_info e_info_8168e_1[] = {
4790 { 0x00, 0x0200, 0x0100 },
4791 { 0x00, 0x0000, 0x0004 },
4792 { 0x06, 0x0002, 0x0001 },
4793 { 0x06, 0x0000, 0x0030 },
4794 { 0x07, 0x0000, 0x2000 },
4795 { 0x00, 0x0000, 0x0020 },
4796 { 0x03, 0x5800, 0x2000 },
4797 { 0x03, 0x0000, 0x0001 },
4798 { 0x01, 0x0800, 0x1000 },
4799 { 0x07, 0x0000, 0x4000 },
4800 { 0x1e, 0x0000, 0x2000 },
4801 { 0x19, 0xffff, 0xfe6c },
4802 { 0x0a, 0x0000, 0x0040 }
4805 rtl_set_def_aspm_entry_latency(tp);
4807 rtl_ephy_init(tp, e_info_8168e_1);
4809 if (tp->dev->mtu <= ETH_DATA_LEN)
4810 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4812 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4814 rtl_disable_clock_request(tp);
4816 /* Reset tx FIFO pointer */
4817 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | TXPLA_RST);
4818 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~TXPLA_RST);
4820 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
4823 static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
4825 static const struct ephy_info e_info_8168e_2[] = {
4826 { 0x09, 0x0000, 0x0080 },
4827 { 0x19, 0x0000, 0x0224 }
4830 rtl_set_def_aspm_entry_latency(tp);
4832 rtl_ephy_init(tp, e_info_8168e_2);
4834 if (tp->dev->mtu <= ETH_DATA_LEN)
4835 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4837 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
4838 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
4839 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06);
4840 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050);
4841 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060);
4842 rtl_eri_set_bits(tp, 0x1b0, ERIAR_MASK_0001, BIT(4));
4843 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00);
4845 RTL_W8(tp, MaxTxPacketSize, EarlySize);
4847 rtl_disable_clock_request(tp);
4849 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
4851 rtl8168_config_eee_mac(tp);
4853 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
4854 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
4855 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
4857 rtl_hw_aspm_clkreq_enable(tp, true);
4860 static void rtl_hw_start_8168f(struct rtl8169_private *tp)
4862 rtl_set_def_aspm_entry_latency(tp);
4864 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4866 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
4867 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
4868 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06);
4869 rtl_reset_packet_filter(tp);
4870 rtl_eri_set_bits(tp, 0x1b0, ERIAR_MASK_0001, BIT(4));
4871 rtl_eri_set_bits(tp, 0x1d0, ERIAR_MASK_0001, BIT(4));
4872 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050);
4873 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060);
4875 RTL_W8(tp, MaxTxPacketSize, EarlySize);
4877 rtl_disable_clock_request(tp);
4879 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
4880 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
4881 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
4882 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
4884 rtl8168_config_eee_mac(tp);
4887 static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
4889 static const struct ephy_info e_info_8168f_1[] = {
4890 { 0x06, 0x00c0, 0x0020 },
4891 { 0x08, 0x0001, 0x0002 },
4892 { 0x09, 0x0000, 0x0080 },
4893 { 0x19, 0x0000, 0x0224 }
4896 rtl_hw_start_8168f(tp);
4898 rtl_ephy_init(tp, e_info_8168f_1);
4900 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00);
4903 static void rtl_hw_start_8411(struct rtl8169_private *tp)
4905 static const struct ephy_info e_info_8168f_1[] = {
4906 { 0x06, 0x00c0, 0x0020 },
4907 { 0x0f, 0xffff, 0x5200 },
4908 { 0x1e, 0x0000, 0x4000 },
4909 { 0x19, 0x0000, 0x0224 }
4912 rtl_hw_start_8168f(tp);
4913 rtl_pcie_state_l2l3_disable(tp);
4915 rtl_ephy_init(tp, e_info_8168f_1);
4917 rtl_eri_set_bits(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00);
4920 static void rtl_hw_start_8168g(struct rtl8169_private *tp)
4922 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
4923 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48);
4925 rtl_set_def_aspm_entry_latency(tp);
4927 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4929 rtl_reset_packet_filter(tp);
4930 rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f);
4932 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
4933 RTL_W8(tp, MaxTxPacketSize, EarlySize);
4935 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
4936 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
4938 rtl8168_config_eee_mac(tp);
4940 rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06);
4941 rtl_eri_clear_bits(tp, 0x1b0, ERIAR_MASK_0011, BIT(12));
4943 rtl_pcie_state_l2l3_disable(tp);
4946 static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
4948 static const struct ephy_info e_info_8168g_1[] = {
4949 { 0x00, 0x0000, 0x0008 },
4950 { 0x0c, 0x37d0, 0x0820 },
4951 { 0x1e, 0x0000, 0x0001 },
4952 { 0x19, 0x8000, 0x0000 }
4955 rtl_hw_start_8168g(tp);
4957 /* disable aspm and clock request before access ephy */
4958 rtl_hw_aspm_clkreq_enable(tp, false);
4959 rtl_ephy_init(tp, e_info_8168g_1);
4960 rtl_hw_aspm_clkreq_enable(tp, true);
4963 static void rtl_hw_start_8168g_2(struct rtl8169_private *tp)
4965 static const struct ephy_info e_info_8168g_2[] = {
4966 { 0x00, 0x0000, 0x0008 },
4967 { 0x0c, 0x3df0, 0x0200 },
4968 { 0x19, 0xffff, 0xfc00 },
4969 { 0x1e, 0xffff, 0x20eb }
4972 rtl_hw_start_8168g(tp);
4974 /* disable aspm and clock request before access ephy */
4975 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
4976 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
4977 rtl_ephy_init(tp, e_info_8168g_2);
4980 static void rtl_hw_start_8411_2(struct rtl8169_private *tp)
4982 static const struct ephy_info e_info_8411_2[] = {
4983 { 0x00, 0x0000, 0x0008 },
4984 { 0x0c, 0x3df0, 0x0200 },
4985 { 0x0f, 0xffff, 0x5200 },
4986 { 0x19, 0x0020, 0x0000 },
4987 { 0x1e, 0x0000, 0x2000 }
4990 rtl_hw_start_8168g(tp);
4992 /* disable aspm and clock request before access ephy */
4993 rtl_hw_aspm_clkreq_enable(tp, false);
4994 rtl_ephy_init(tp, e_info_8411_2);
4995 rtl_hw_aspm_clkreq_enable(tp, true);
4998 static void rtl_hw_start_8168h_1(struct rtl8169_private *tp)
5002 static const struct ephy_info e_info_8168h_1[] = {
5003 { 0x1e, 0x0800, 0x0001 },
5004 { 0x1d, 0x0000, 0x0800 },
5005 { 0x05, 0xffff, 0x2089 },
5006 { 0x06, 0xffff, 0x5881 },
5007 { 0x04, 0xffff, 0x154a },
5008 { 0x01, 0xffff, 0x068b }
5011 /* disable aspm and clock request before access ephy */
5012 rtl_hw_aspm_clkreq_enable(tp, false);
5013 rtl_ephy_init(tp, e_info_8168h_1);
5015 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
5016 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48);
5018 rtl_set_def_aspm_entry_latency(tp);
5020 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5022 rtl_reset_packet_filter(tp);
5024 rtl_eri_set_bits(tp, 0xdc, ERIAR_MASK_1111, BIT(4));
5026 rtl_eri_set_bits(tp, 0xd4, ERIAR_MASK_1111, 0x1f00);
5028 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);
5030 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
5031 RTL_W8(tp, MaxTxPacketSize, EarlySize);
5033 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
5034 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
5036 rtl8168_config_eee_mac(tp);
5038 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5039 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
5041 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
5043 rtl_eri_clear_bits(tp, 0x1b0, ERIAR_MASK_0011, BIT(12));
5045 rtl_pcie_state_l2l3_disable(tp);
5047 rtl_writephy(tp, 0x1f, 0x0c42);
5048 rg_saw_cnt = (rtl_readphy(tp, 0x13) & 0x3fff);
5049 rtl_writephy(tp, 0x1f, 0x0000);
5050 if (rg_saw_cnt > 0) {
5053 sw_cnt_1ms_ini = 16000000/rg_saw_cnt;
5054 sw_cnt_1ms_ini &= 0x0fff;
5055 data = r8168_mac_ocp_read(tp, 0xd412);
5057 data |= sw_cnt_1ms_ini;
5058 r8168_mac_ocp_write(tp, 0xd412, data);
5061 data = r8168_mac_ocp_read(tp, 0xe056);
5064 r8168_mac_ocp_write(tp, 0xe056, data);
5066 data = r8168_mac_ocp_read(tp, 0xe052);
5069 r8168_mac_ocp_write(tp, 0xe052, data);
5071 data = r8168_mac_ocp_read(tp, 0xe0d6);
5074 r8168_mac_ocp_write(tp, 0xe0d6, data);
5076 data = r8168_mac_ocp_read(tp, 0xd420);
5079 r8168_mac_ocp_write(tp, 0xd420, data);
5081 r8168_mac_ocp_write(tp, 0xe63e, 0x0001);
5082 r8168_mac_ocp_write(tp, 0xe63e, 0x0000);
5083 r8168_mac_ocp_write(tp, 0xc094, 0x0000);
5084 r8168_mac_ocp_write(tp, 0xc09e, 0x0000);
5086 rtl_hw_aspm_clkreq_enable(tp, true);
5089 static void rtl_hw_start_8168ep(struct rtl8169_private *tp)
5091 rtl8168ep_stop_cmac(tp);
5093 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
5094 rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f);
5096 rtl_set_def_aspm_entry_latency(tp);
5098 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5100 rtl_reset_packet_filter(tp);
5102 rtl_eri_set_bits(tp, 0xd4, ERIAR_MASK_1111, 0x1f80);
5104 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);
5106 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
5107 RTL_W8(tp, MaxTxPacketSize, EarlySize);
5109 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
5110 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
5112 rtl8168_config_eee_mac(tp);
5114 rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06);
5116 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
5118 rtl_pcie_state_l2l3_disable(tp);
5121 static void rtl_hw_start_8168ep_1(struct rtl8169_private *tp)
5123 static const struct ephy_info e_info_8168ep_1[] = {
5124 { 0x00, 0xffff, 0x10ab },
5125 { 0x06, 0xffff, 0xf030 },
5126 { 0x08, 0xffff, 0x2006 },
5127 { 0x0d, 0xffff, 0x1666 },
5128 { 0x0c, 0x3ff0, 0x0000 }
5131 /* disable aspm and clock request before access ephy */
5132 rtl_hw_aspm_clkreq_enable(tp, false);
5133 rtl_ephy_init(tp, e_info_8168ep_1);
5135 rtl_hw_start_8168ep(tp);
5137 rtl_hw_aspm_clkreq_enable(tp, true);
5140 static void rtl_hw_start_8168ep_2(struct rtl8169_private *tp)
5142 static const struct ephy_info e_info_8168ep_2[] = {
5143 { 0x00, 0xffff, 0x10a3 },
5144 { 0x19, 0xffff, 0xfc00 },
5145 { 0x1e, 0xffff, 0x20ea }
5148 /* disable aspm and clock request before access ephy */
5149 rtl_hw_aspm_clkreq_enable(tp, false);
5150 rtl_ephy_init(tp, e_info_8168ep_2);
5152 rtl_hw_start_8168ep(tp);
5154 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5155 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
5157 rtl_hw_aspm_clkreq_enable(tp, true);
5160 static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp)
5163 static const struct ephy_info e_info_8168ep_3[] = {
5164 { 0x00, 0xffff, 0x10a3 },
5165 { 0x19, 0xffff, 0x7c00 },
5166 { 0x1e, 0xffff, 0x20eb },
5167 { 0x0d, 0xffff, 0x1666 }
5170 /* disable aspm and clock request before access ephy */
5171 rtl_hw_aspm_clkreq_enable(tp, false);
5172 rtl_ephy_init(tp, e_info_8168ep_3);
5174 rtl_hw_start_8168ep(tp);
5176 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5177 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
5179 data = r8168_mac_ocp_read(tp, 0xd3e2);
5182 r8168_mac_ocp_write(tp, 0xd3e2, data);
5184 data = r8168_mac_ocp_read(tp, 0xd3e4);
5186 r8168_mac_ocp_write(tp, 0xd3e4, data);
5188 data = r8168_mac_ocp_read(tp, 0xe860);
5190 r8168_mac_ocp_write(tp, 0xe860, data);
5192 rtl_hw_aspm_clkreq_enable(tp, true);
5195 static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)
5197 static const struct ephy_info e_info_8102e_1[] = {
5198 { 0x01, 0, 0x6e65 },
5199 { 0x02, 0, 0x091f },
5200 { 0x03, 0, 0xc2f9 },
5201 { 0x06, 0, 0xafb5 },
5202 { 0x07, 0, 0x0e00 },
5203 { 0x19, 0, 0xec80 },
5204 { 0x01, 0, 0x2e65 },
5209 rtl_set_def_aspm_entry_latency(tp);
5211 RTL_W8(tp, DBG_REG, FIX_NAK_1);
5213 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5216 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
5217 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
5219 cfg1 = RTL_R8(tp, Config1);
5220 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
5221 RTL_W8(tp, Config1, cfg1 & ~LEDS0);
5223 rtl_ephy_init(tp, e_info_8102e_1);
5226 static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)
5228 rtl_set_def_aspm_entry_latency(tp);
5230 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5232 RTL_W8(tp, Config1, MEMMAP | IOMAP | VPD | PMEnable);
5233 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
5236 static void rtl_hw_start_8102e_3(struct rtl8169_private *tp)
5238 rtl_hw_start_8102e_2(tp);
5240 rtl_ephy_write(tp, 0x03, 0xc2f9);
5243 static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)
5245 static const struct ephy_info e_info_8105e_1[] = {
5246 { 0x07, 0, 0x4000 },
5247 { 0x19, 0, 0x0200 },
5248 { 0x19, 0, 0x0020 },
5249 { 0x1e, 0, 0x2000 },
5250 { 0x03, 0, 0x0001 },
5251 { 0x19, 0, 0x0100 },
5252 { 0x19, 0, 0x0004 },
5256 /* Force LAN exit from ASPM if Rx/Tx are not idle */
5257 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
5259 /* Disable Early Tally Counter */
5260 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) & ~0x010000);
5262 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
5263 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
5265 rtl_ephy_init(tp, e_info_8105e_1);
5267 rtl_pcie_state_l2l3_disable(tp);
5270 static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)
5272 rtl_hw_start_8105e_1(tp);
5273 rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000);
5276 static void rtl_hw_start_8402(struct rtl8169_private *tp)
5278 static const struct ephy_info e_info_8402[] = {
5279 { 0x19, 0xffff, 0xff64 },
5283 rtl_set_def_aspm_entry_latency(tp);
5285 /* Force LAN exit from ASPM if Rx/Tx are not idle */
5286 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
5288 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
5290 rtl_ephy_init(tp, e_info_8402);
5292 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5294 rtl_set_fifo_size(tp, 0x00, 0x00, 0x02, 0x06);
5295 rtl_reset_packet_filter(tp);
5296 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
5297 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
5298 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0e00, 0xff00);
5300 rtl_pcie_state_l2l3_disable(tp);
5303 static void rtl_hw_start_8106(struct rtl8169_private *tp)
5305 rtl_hw_aspm_clkreq_enable(tp, false);
5307 /* Force LAN exit from ASPM if Rx/Tx are not idle */
5308 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
5310 RTL_W32(tp, MISC, (RTL_R32(tp, MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);
5311 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
5312 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5314 rtl_pcie_state_l2l3_disable(tp);
5315 rtl_hw_aspm_clkreq_enable(tp, true);
5318 static void rtl_hw_config(struct rtl8169_private *tp)
5320 static const rtl_generic_fct hw_configs[] = {
5321 [RTL_GIGA_MAC_VER_07] = rtl_hw_start_8102e_1,
5322 [RTL_GIGA_MAC_VER_08] = rtl_hw_start_8102e_3,
5323 [RTL_GIGA_MAC_VER_09] = rtl_hw_start_8102e_2,
5324 [RTL_GIGA_MAC_VER_10] = NULL,
5325 [RTL_GIGA_MAC_VER_11] = rtl_hw_start_8168bb,
5326 [RTL_GIGA_MAC_VER_12] = rtl_hw_start_8168bef,
5327 [RTL_GIGA_MAC_VER_13] = NULL,
5328 [RTL_GIGA_MAC_VER_14] = NULL,
5329 [RTL_GIGA_MAC_VER_15] = NULL,
5330 [RTL_GIGA_MAC_VER_16] = NULL,
5331 [RTL_GIGA_MAC_VER_17] = rtl_hw_start_8168bef,
5332 [RTL_GIGA_MAC_VER_18] = rtl_hw_start_8168cp_1,
5333 [RTL_GIGA_MAC_VER_19] = rtl_hw_start_8168c_1,
5334 [RTL_GIGA_MAC_VER_20] = rtl_hw_start_8168c_2,
5335 [RTL_GIGA_MAC_VER_21] = rtl_hw_start_8168c_3,
5336 [RTL_GIGA_MAC_VER_22] = rtl_hw_start_8168c_4,
5337 [RTL_GIGA_MAC_VER_23] = rtl_hw_start_8168cp_2,
5338 [RTL_GIGA_MAC_VER_24] = rtl_hw_start_8168cp_3,
5339 [RTL_GIGA_MAC_VER_25] = rtl_hw_start_8168d,
5340 [RTL_GIGA_MAC_VER_26] = rtl_hw_start_8168d,
5341 [RTL_GIGA_MAC_VER_27] = rtl_hw_start_8168d,
5342 [RTL_GIGA_MAC_VER_28] = rtl_hw_start_8168d_4,
5343 [RTL_GIGA_MAC_VER_29] = rtl_hw_start_8105e_1,
5344 [RTL_GIGA_MAC_VER_30] = rtl_hw_start_8105e_2,
5345 [RTL_GIGA_MAC_VER_31] = rtl_hw_start_8168dp,
5346 [RTL_GIGA_MAC_VER_32] = rtl_hw_start_8168e_1,
5347 [RTL_GIGA_MAC_VER_33] = rtl_hw_start_8168e_1,
5348 [RTL_GIGA_MAC_VER_34] = rtl_hw_start_8168e_2,
5349 [RTL_GIGA_MAC_VER_35] = rtl_hw_start_8168f_1,
5350 [RTL_GIGA_MAC_VER_36] = rtl_hw_start_8168f_1,
5351 [RTL_GIGA_MAC_VER_37] = rtl_hw_start_8402,
5352 [RTL_GIGA_MAC_VER_38] = rtl_hw_start_8411,
5353 [RTL_GIGA_MAC_VER_39] = rtl_hw_start_8106,
5354 [RTL_GIGA_MAC_VER_40] = rtl_hw_start_8168g_1,
5355 [RTL_GIGA_MAC_VER_41] = rtl_hw_start_8168g_1,
5356 [RTL_GIGA_MAC_VER_42] = rtl_hw_start_8168g_2,
5357 [RTL_GIGA_MAC_VER_43] = rtl_hw_start_8168g_2,
5358 [RTL_GIGA_MAC_VER_44] = rtl_hw_start_8411_2,
5359 [RTL_GIGA_MAC_VER_45] = rtl_hw_start_8168h_1,
5360 [RTL_GIGA_MAC_VER_46] = rtl_hw_start_8168h_1,
5361 [RTL_GIGA_MAC_VER_47] = rtl_hw_start_8168h_1,
5362 [RTL_GIGA_MAC_VER_48] = rtl_hw_start_8168h_1,
5363 [RTL_GIGA_MAC_VER_49] = rtl_hw_start_8168ep_1,
5364 [RTL_GIGA_MAC_VER_50] = rtl_hw_start_8168ep_2,
5365 [RTL_GIGA_MAC_VER_51] = rtl_hw_start_8168ep_3,
5368 if (hw_configs[tp->mac_version])
5369 hw_configs[tp->mac_version](tp);
5372 static void rtl_hw_start_8168(struct rtl8169_private *tp)
5374 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
5376 /* Workaround for RxFIFO overflow. */
5377 if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
5378 tp->irq_mask |= RxFIFOOver;
5379 tp->irq_mask &= ~RxOverflow;
5385 static void rtl_hw_start_8101(struct rtl8169_private *tp)
5387 if (tp->mac_version >= RTL_GIGA_MAC_VER_30)
5388 tp->irq_mask &= ~RxFIFOOver;
5390 if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
5391 tp->mac_version == RTL_GIGA_MAC_VER_16)
5392 pcie_capability_set_word(tp->pci_dev, PCI_EXP_DEVCTL,
5393 PCI_EXP_DEVCTL_NOSNOOP_EN);
5395 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
5397 tp->cp_cmd &= CPCMD_QUIRK_MASK;
5398 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
5403 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
5405 struct rtl8169_private *tp = netdev_priv(dev);
5407 if (new_mtu > ETH_DATA_LEN)
5408 rtl_hw_jumbo_enable(tp);
5410 rtl_hw_jumbo_disable(tp);
5413 netdev_update_features(dev);
5418 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
5420 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
5421 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
5424 static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
5425 void **data_buff, struct RxDesc *desc)
5427 dma_unmap_single(tp_to_dev(tp), le64_to_cpu(desc->addr),
5428 R8169_RX_BUF_SIZE, DMA_FROM_DEVICE);
5432 rtl8169_make_unusable_by_asic(desc);
5435 static inline void rtl8169_mark_to_asic(struct RxDesc *desc)
5437 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
5439 /* Force memory writes to complete before releasing descriptor */
5442 desc->opts1 = cpu_to_le32(DescOwn | eor | R8169_RX_BUF_SIZE);
5445 static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
5446 struct RxDesc *desc)
5450 struct device *d = tp_to_dev(tp);
5451 int node = dev_to_node(d);
5453 data = kmalloc_node(R8169_RX_BUF_SIZE, GFP_KERNEL, node);
5457 /* Memory should be properly aligned, but better check. */
5458 if (!IS_ALIGNED((unsigned long)data, 8)) {
5459 netdev_err_once(tp->dev, "RX buffer not 8-byte-aligned\n");
5463 mapping = dma_map_single(d, data, R8169_RX_BUF_SIZE, DMA_FROM_DEVICE);
5464 if (unlikely(dma_mapping_error(d, mapping))) {
5465 if (net_ratelimit())
5466 netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
5470 desc->addr = cpu_to_le64(mapping);
5471 rtl8169_mark_to_asic(desc);
5479 static void rtl8169_rx_clear(struct rtl8169_private *tp)
5483 for (i = 0; i < NUM_RX_DESC; i++) {
5484 if (tp->Rx_databuff[i]) {
5485 rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
5486 tp->RxDescArray + i);
5491 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
5493 desc->opts1 |= cpu_to_le32(RingEnd);
5496 static int rtl8169_rx_fill(struct rtl8169_private *tp)
5500 for (i = 0; i < NUM_RX_DESC; i++) {
5503 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
5505 rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
5508 tp->Rx_databuff[i] = data;
5511 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
5515 rtl8169_rx_clear(tp);
5519 static int rtl8169_init_ring(struct rtl8169_private *tp)
5521 rtl8169_init_ring_indexes(tp);
5523 memset(tp->tx_skb, 0, sizeof(tp->tx_skb));
5524 memset(tp->Rx_databuff, 0, sizeof(tp->Rx_databuff));
5526 return rtl8169_rx_fill(tp);
5529 static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
5530 struct TxDesc *desc)
5532 unsigned int len = tx_skb->len;
5534 dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
5542 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
5547 for (i = 0; i < n; i++) {
5548 unsigned int entry = (start + i) % NUM_TX_DESC;
5549 struct ring_info *tx_skb = tp->tx_skb + entry;
5550 unsigned int len = tx_skb->len;
5553 struct sk_buff *skb = tx_skb->skb;
5555 rtl8169_unmap_tx_skb(tp_to_dev(tp), tx_skb,
5556 tp->TxDescArray + entry);
5558 dev_consume_skb_any(skb);
5565 static void rtl8169_tx_clear(struct rtl8169_private *tp)
5567 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
5568 tp->cur_tx = tp->dirty_tx = 0;
5569 netdev_reset_queue(tp->dev);
5572 static void rtl_reset_work(struct rtl8169_private *tp)
5574 struct net_device *dev = tp->dev;
5577 napi_disable(&tp->napi);
5578 netif_stop_queue(dev);
5581 rtl8169_hw_reset(tp);
5583 for (i = 0; i < NUM_RX_DESC; i++)
5584 rtl8169_mark_to_asic(tp->RxDescArray + i);
5586 rtl8169_tx_clear(tp);
5587 rtl8169_init_ring_indexes(tp);
5589 napi_enable(&tp->napi);
5591 netif_wake_queue(dev);
5594 static void rtl8169_tx_timeout(struct net_device *dev)
5596 struct rtl8169_private *tp = netdev_priv(dev);
5598 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
5601 static __le32 rtl8169_get_txd_opts1(u32 opts0, u32 len, unsigned int entry)
5603 u32 status = opts0 | len;
5605 if (entry == NUM_TX_DESC - 1)
5608 return cpu_to_le32(status);
5611 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
5614 struct skb_shared_info *info = skb_shinfo(skb);
5615 unsigned int cur_frag, entry;
5616 struct TxDesc *uninitialized_var(txd);
5617 struct device *d = tp_to_dev(tp);
5620 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
5621 const skb_frag_t *frag = info->frags + cur_frag;
5626 entry = (entry + 1) % NUM_TX_DESC;
5628 txd = tp->TxDescArray + entry;
5629 len = skb_frag_size(frag);
5630 addr = skb_frag_address(frag);
5631 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
5632 if (unlikely(dma_mapping_error(d, mapping))) {
5633 if (net_ratelimit())
5634 netif_err(tp, drv, tp->dev,
5635 "Failed to map TX fragments DMA!\n");
5639 txd->opts1 = rtl8169_get_txd_opts1(opts[0], len, entry);
5640 txd->opts2 = cpu_to_le32(opts[1]);
5641 txd->addr = cpu_to_le64(mapping);
5643 tp->tx_skb[entry].len = len;
5647 tp->tx_skb[entry].skb = skb;
5648 txd->opts1 |= cpu_to_le32(LastFrag);
5654 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
5658 static bool rtl_test_hw_pad_bug(struct rtl8169_private *tp, struct sk_buff *skb)
5660 return skb->len < ETH_ZLEN && tp->mac_version == RTL_GIGA_MAC_VER_34;
5663 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
5664 struct net_device *dev);
5665 /* r8169_csum_workaround()
5666 * The hw limites the value the transport offset. When the offset is out of the
5667 * range, calculate the checksum by sw.
5669 static void r8169_csum_workaround(struct rtl8169_private *tp,
5670 struct sk_buff *skb)
5672 if (skb_is_gso(skb)) {
5673 netdev_features_t features = tp->dev->features;
5674 struct sk_buff *segs, *nskb;
5676 features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
5677 segs = skb_gso_segment(skb, features);
5678 if (IS_ERR(segs) || !segs)
5685 rtl8169_start_xmit(nskb, tp->dev);
5688 dev_consume_skb_any(skb);
5689 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5690 if (skb_checksum_help(skb) < 0)
5693 rtl8169_start_xmit(skb, tp->dev);
5696 tp->dev->stats.tx_dropped++;
5697 dev_kfree_skb_any(skb);
5701 /* msdn_giant_send_check()
5702 * According to the document of microsoft, the TCP Pseudo Header excludes the
5703 * packet length for IPv6 TCP large packets.
5705 static int msdn_giant_send_check(struct sk_buff *skb)
5707 const struct ipv6hdr *ipv6h;
5711 ret = skb_cow_head(skb, 0);
5715 ipv6h = ipv6_hdr(skb);
5719 th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0);
5724 static void rtl8169_tso_csum_v1(struct sk_buff *skb, u32 *opts)
5726 u32 mss = skb_shinfo(skb)->gso_size;
5730 opts[0] |= min(mss, TD_MSS_MAX) << TD0_MSS_SHIFT;
5731 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5732 const struct iphdr *ip = ip_hdr(skb);
5734 if (ip->protocol == IPPROTO_TCP)
5735 opts[0] |= TD0_IP_CS | TD0_TCP_CS;
5736 else if (ip->protocol == IPPROTO_UDP)
5737 opts[0] |= TD0_IP_CS | TD0_UDP_CS;
5743 static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp,
5744 struct sk_buff *skb, u32 *opts)
5746 u32 transport_offset = (u32)skb_transport_offset(skb);
5747 u32 mss = skb_shinfo(skb)->gso_size;
5750 if (transport_offset > GTTCPHO_MAX) {
5751 netif_warn(tp, tx_err, tp->dev,
5752 "Invalid transport offset 0x%x for TSO\n",
5757 switch (vlan_get_protocol(skb)) {
5758 case htons(ETH_P_IP):
5759 opts[0] |= TD1_GTSENV4;
5762 case htons(ETH_P_IPV6):
5763 if (msdn_giant_send_check(skb))
5766 opts[0] |= TD1_GTSENV6;
5774 opts[0] |= transport_offset << GTTCPHO_SHIFT;
5775 opts[1] |= min(mss, TD_MSS_MAX) << TD1_MSS_SHIFT;
5776 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5779 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
5780 return !(skb_checksum_help(skb) || eth_skb_pad(skb));
5782 if (transport_offset > TCPHO_MAX) {
5783 netif_warn(tp, tx_err, tp->dev,
5784 "Invalid transport offset 0x%x\n",
5789 switch (vlan_get_protocol(skb)) {
5790 case htons(ETH_P_IP):
5791 opts[1] |= TD1_IPv4_CS;
5792 ip_protocol = ip_hdr(skb)->protocol;
5795 case htons(ETH_P_IPV6):
5796 opts[1] |= TD1_IPv6_CS;
5797 ip_protocol = ipv6_hdr(skb)->nexthdr;
5801 ip_protocol = IPPROTO_RAW;
5805 if (ip_protocol == IPPROTO_TCP)
5806 opts[1] |= TD1_TCP_CS;
5807 else if (ip_protocol == IPPROTO_UDP)
5808 opts[1] |= TD1_UDP_CS;
5812 opts[1] |= transport_offset << TCPHO_SHIFT;
5814 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
5815 return !eth_skb_pad(skb);
5821 static bool rtl_tx_slots_avail(struct rtl8169_private *tp,
5822 unsigned int nr_frags)
5824 unsigned int slots_avail = tp->dirty_tx + NUM_TX_DESC - tp->cur_tx;
5826 /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
5827 return slots_avail > nr_frags;
5830 /* Versions RTL8102e and from RTL8168c onwards support csum_v2 */
5831 static bool rtl_chip_supports_csum_v2(struct rtl8169_private *tp)
5833 switch (tp->mac_version) {
5834 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
5835 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
5842 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
5843 struct net_device *dev)
5845 struct rtl8169_private *tp = netdev_priv(dev);
5846 unsigned int entry = tp->cur_tx % NUM_TX_DESC;
5847 struct TxDesc *txd = tp->TxDescArray + entry;
5848 struct device *d = tp_to_dev(tp);
5853 if (unlikely(!rtl_tx_slots_avail(tp, skb_shinfo(skb)->nr_frags))) {
5854 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
5858 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
5861 opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(skb));
5864 if (rtl_chip_supports_csum_v2(tp)) {
5865 if (!rtl8169_tso_csum_v2(tp, skb, opts)) {
5866 r8169_csum_workaround(tp, skb);
5867 return NETDEV_TX_OK;
5870 rtl8169_tso_csum_v1(skb, opts);
5873 len = skb_headlen(skb);
5874 mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
5875 if (unlikely(dma_mapping_error(d, mapping))) {
5876 if (net_ratelimit())
5877 netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
5881 tp->tx_skb[entry].len = len;
5882 txd->addr = cpu_to_le64(mapping);
5884 frags = rtl8169_xmit_frags(tp, skb, opts);
5888 opts[0] |= FirstFrag;
5890 opts[0] |= FirstFrag | LastFrag;
5891 tp->tx_skb[entry].skb = skb;
5894 txd->opts2 = cpu_to_le32(opts[1]);
5896 netdev_sent_queue(dev, skb->len);
5898 skb_tx_timestamp(skb);
5900 /* Force memory writes to complete before releasing descriptor */
5903 txd->opts1 = rtl8169_get_txd_opts1(opts[0], len, entry);
5905 /* Force all memory writes to complete before notifying device */
5908 tp->cur_tx += frags + 1;
5910 RTL_W8(tp, TxPoll, NPQ);
5912 if (!rtl_tx_slots_avail(tp, MAX_SKB_FRAGS)) {
5913 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
5914 * not miss a ring update when it notices a stopped queue.
5917 netif_stop_queue(dev);
5918 /* Sync with rtl_tx:
5919 * - publish queue status and cur_tx ring index (write barrier)
5920 * - refresh dirty_tx ring index (read barrier).
5921 * May the current thread have a pessimistic view of the ring
5922 * status and forget to wake up queue, a racing rtl_tx thread
5926 if (rtl_tx_slots_avail(tp, MAX_SKB_FRAGS))
5927 netif_start_queue(dev);
5930 return NETDEV_TX_OK;
5933 rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
5935 dev_kfree_skb_any(skb);
5936 dev->stats.tx_dropped++;
5937 return NETDEV_TX_OK;
5940 netif_stop_queue(dev);
5941 dev->stats.tx_dropped++;
5942 return NETDEV_TX_BUSY;
5945 static void rtl8169_pcierr_interrupt(struct net_device *dev)
5947 struct rtl8169_private *tp = netdev_priv(dev);
5948 struct pci_dev *pdev = tp->pci_dev;
5949 u16 pci_status, pci_cmd;
5951 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
5952 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
5954 netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
5955 pci_cmd, pci_status);
5958 * The recovery sequence below admits a very elaborated explanation:
5959 * - it seems to work;
5960 * - I did not see what else could be done;
5961 * - it makes iop3xx happy.
5963 * Feel free to adjust to your needs.
5965 if (pdev->broken_parity_status)
5966 pci_cmd &= ~PCI_COMMAND_PARITY;
5968 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
5970 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
5972 pci_write_config_word(pdev, PCI_STATUS,
5973 pci_status & (PCI_STATUS_DETECTED_PARITY |
5974 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
5975 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
5977 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
5980 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp,
5983 unsigned int dirty_tx, tx_left, bytes_compl = 0, pkts_compl = 0;
5985 dirty_tx = tp->dirty_tx;
5987 tx_left = tp->cur_tx - dirty_tx;
5989 while (tx_left > 0) {
5990 unsigned int entry = dirty_tx % NUM_TX_DESC;
5991 struct ring_info *tx_skb = tp->tx_skb + entry;
5994 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
5995 if (status & DescOwn)
5998 /* This barrier is needed to keep us from reading
5999 * any other fields out of the Tx descriptor until
6000 * we know the status of DescOwn
6004 rtl8169_unmap_tx_skb(tp_to_dev(tp), tx_skb,
6005 tp->TxDescArray + entry);
6006 if (status & LastFrag) {
6008 bytes_compl += tx_skb->skb->len;
6009 napi_consume_skb(tx_skb->skb, budget);
6016 if (tp->dirty_tx != dirty_tx) {
6017 netdev_completed_queue(dev, pkts_compl, bytes_compl);
6019 u64_stats_update_begin(&tp->tx_stats.syncp);
6020 tp->tx_stats.packets += pkts_compl;
6021 tp->tx_stats.bytes += bytes_compl;
6022 u64_stats_update_end(&tp->tx_stats.syncp);
6024 tp->dirty_tx = dirty_tx;
6025 /* Sync with rtl8169_start_xmit:
6026 * - publish dirty_tx ring index (write barrier)
6027 * - refresh cur_tx ring index and queue status (read barrier)
6028 * May the current thread miss the stopped queue condition,
6029 * a racing xmit thread can only have a right view of the
6033 if (netif_queue_stopped(dev) &&
6034 rtl_tx_slots_avail(tp, MAX_SKB_FRAGS)) {
6035 netif_wake_queue(dev);
6038 * 8168 hack: TxPoll requests are lost when the Tx packets are
6039 * too close. Let's kick an extra TxPoll request when a burst
6040 * of start_xmit activity is detected (if it is not detected,
6041 * it is slow enough). -- FR
6043 if (tp->cur_tx != dirty_tx)
6044 RTL_W8(tp, TxPoll, NPQ);
6048 static inline int rtl8169_fragmented_frame(u32 status)
6050 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
6053 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
6055 u32 status = opts1 & RxProtoMask;
6057 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
6058 ((status == RxProtoUDP) && !(opts1 & UDPFail)))
6059 skb->ip_summed = CHECKSUM_UNNECESSARY;
6061 skb_checksum_none_assert(skb);
6064 static struct sk_buff *rtl8169_try_rx_copy(void *data,
6065 struct rtl8169_private *tp,
6069 struct sk_buff *skb;
6070 struct device *d = tp_to_dev(tp);
6072 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
6074 skb = napi_alloc_skb(&tp->napi, pkt_size);
6076 skb_copy_to_linear_data(skb, data, pkt_size);
6077 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
6082 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget)
6084 unsigned int cur_rx, rx_left;
6087 cur_rx = tp->cur_rx;
6089 for (rx_left = min(budget, NUM_RX_DESC); rx_left > 0; rx_left--, cur_rx++) {
6090 unsigned int entry = cur_rx % NUM_RX_DESC;
6091 struct RxDesc *desc = tp->RxDescArray + entry;
6094 status = le32_to_cpu(desc->opts1);
6095 if (status & DescOwn)
6098 /* This barrier is needed to keep us from reading
6099 * any other fields out of the Rx descriptor until
6100 * we know the status of DescOwn
6104 if (unlikely(status & RxRES)) {
6105 netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
6107 dev->stats.rx_errors++;
6108 if (status & (RxRWT | RxRUNT))
6109 dev->stats.rx_length_errors++;
6111 dev->stats.rx_crc_errors++;
6112 if (status & (RxRUNT | RxCRC) && !(status & RxRWT) &&
6113 dev->features & NETIF_F_RXALL) {
6117 struct sk_buff *skb;
6122 addr = le64_to_cpu(desc->addr);
6123 if (likely(!(dev->features & NETIF_F_RXFCS)))
6124 pkt_size = (status & 0x00003fff) - 4;
6126 pkt_size = status & 0x00003fff;
6129 * The driver does not support incoming fragmented
6130 * frames. They are seen as a symptom of over-mtu
6133 if (unlikely(rtl8169_fragmented_frame(status))) {
6134 dev->stats.rx_dropped++;
6135 dev->stats.rx_length_errors++;
6136 goto release_descriptor;
6139 skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
6140 tp, pkt_size, addr);
6142 dev->stats.rx_dropped++;
6143 goto release_descriptor;
6146 rtl8169_rx_csum(skb, status);
6147 skb_put(skb, pkt_size);
6148 skb->protocol = eth_type_trans(skb, dev);
6150 rtl8169_rx_vlan_tag(desc, skb);
6152 if (skb->pkt_type == PACKET_MULTICAST)
6153 dev->stats.multicast++;
6155 napi_gro_receive(&tp->napi, skb);
6157 u64_stats_update_begin(&tp->rx_stats.syncp);
6158 tp->rx_stats.packets++;
6159 tp->rx_stats.bytes += pkt_size;
6160 u64_stats_update_end(&tp->rx_stats.syncp);
6164 rtl8169_mark_to_asic(desc);
6167 count = cur_rx - tp->cur_rx;
6168 tp->cur_rx = cur_rx;
6173 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
6175 struct rtl8169_private *tp = dev_instance;
6176 u16 status = RTL_R16(tp, IntrStatus);
6178 if (!tp->irq_enabled || status == 0xffff || !(status & tp->irq_mask))
6181 if (unlikely(status & SYSErr)) {
6182 rtl8169_pcierr_interrupt(tp->dev);
6186 if (status & LinkChg)
6187 phy_mac_interrupt(tp->phydev);
6189 if (unlikely(status & RxFIFOOver &&
6190 tp->mac_version == RTL_GIGA_MAC_VER_11)) {
6191 netif_stop_queue(tp->dev);
6192 /* XXX - Hack alert. See rtl_task(). */
6193 set_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags);
6196 rtl_irq_disable(tp);
6197 napi_schedule_irqoff(&tp->napi);
6199 rtl_ack_events(tp, status);
6204 static void rtl_task(struct work_struct *work)
6206 static const struct {
6208 void (*action)(struct rtl8169_private *);
6210 { RTL_FLAG_TASK_RESET_PENDING, rtl_reset_work },
6212 struct rtl8169_private *tp =
6213 container_of(work, struct rtl8169_private, wk.work);
6214 struct net_device *dev = tp->dev;
6219 if (!netif_running(dev) ||
6220 !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
6223 for (i = 0; i < ARRAY_SIZE(rtl_work); i++) {
6226 pending = test_and_clear_bit(rtl_work[i].bitnr, tp->wk.flags);
6228 rtl_work[i].action(tp);
6232 rtl_unlock_work(tp);
6235 static int rtl8169_poll(struct napi_struct *napi, int budget)
6237 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
6238 struct net_device *dev = tp->dev;
6241 work_done = rtl_rx(dev, tp, (u32) budget);
6243 rtl_tx(dev, tp, budget);
6245 if (work_done < budget) {
6246 napi_complete_done(napi, work_done);
6253 static void rtl8169_rx_missed(struct net_device *dev)
6255 struct rtl8169_private *tp = netdev_priv(dev);
6257 if (tp->mac_version > RTL_GIGA_MAC_VER_06)
6260 dev->stats.rx_missed_errors += RTL_R32(tp, RxMissed) & 0xffffff;
6261 RTL_W32(tp, RxMissed, 0);
6264 static void r8169_phylink_handler(struct net_device *ndev)
6266 struct rtl8169_private *tp = netdev_priv(ndev);
6268 if (netif_carrier_ok(ndev)) {
6269 rtl_link_chg_patch(tp);
6270 pm_request_resume(&tp->pci_dev->dev);
6272 pm_runtime_idle(&tp->pci_dev->dev);
6275 if (net_ratelimit())
6276 phy_print_status(tp->phydev);
6279 static int r8169_phy_connect(struct rtl8169_private *tp)
6281 struct phy_device *phydev = tp->phydev;
6282 phy_interface_t phy_mode;
6285 phy_mode = tp->supports_gmii ? PHY_INTERFACE_MODE_GMII :
6286 PHY_INTERFACE_MODE_MII;
6288 ret = phy_connect_direct(tp->dev, phydev, r8169_phylink_handler,
6293 if (tp->supports_gmii)
6294 phy_remove_link_mode(phydev,
6295 ETHTOOL_LINK_MODE_1000baseT_Half_BIT);
6297 phy_set_max_speed(phydev, SPEED_100);
6299 phy_support_asym_pause(phydev);
6301 phy_attached_info(phydev);
6306 static void rtl8169_down(struct net_device *dev)
6308 struct rtl8169_private *tp = netdev_priv(dev);
6310 phy_stop(tp->phydev);
6312 napi_disable(&tp->napi);
6313 netif_stop_queue(dev);
6315 rtl8169_hw_reset(tp);
6317 * At this point device interrupts can not be enabled in any function,
6318 * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task)
6319 * and napi is disabled (rtl8169_poll).
6321 rtl8169_rx_missed(dev);
6323 /* Give a racing hard_start_xmit a few cycles to complete. */
6326 rtl8169_tx_clear(tp);
6328 rtl8169_rx_clear(tp);
6330 rtl_pll_power_down(tp);
6333 static int rtl8169_close(struct net_device *dev)
6335 struct rtl8169_private *tp = netdev_priv(dev);
6336 struct pci_dev *pdev = tp->pci_dev;
6338 pm_runtime_get_sync(&pdev->dev);
6340 /* Update counters before going down */
6341 rtl8169_update_counters(tp);
6344 /* Clear all task flags */
6345 bitmap_zero(tp->wk.flags, RTL_FLAG_MAX);
6348 rtl_unlock_work(tp);
6350 cancel_work_sync(&tp->wk.work);
6352 phy_disconnect(tp->phydev);
6354 pci_free_irq(pdev, 0, tp);
6356 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6358 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6360 tp->TxDescArray = NULL;
6361 tp->RxDescArray = NULL;
6363 pm_runtime_put_sync(&pdev->dev);
6368 #ifdef CONFIG_NET_POLL_CONTROLLER
6369 static void rtl8169_netpoll(struct net_device *dev)
6371 struct rtl8169_private *tp = netdev_priv(dev);
6373 rtl8169_interrupt(pci_irq_vector(tp->pci_dev, 0), tp);
6377 static int rtl_open(struct net_device *dev)
6379 struct rtl8169_private *tp = netdev_priv(dev);
6380 struct pci_dev *pdev = tp->pci_dev;
6381 int retval = -ENOMEM;
6383 pm_runtime_get_sync(&pdev->dev);
6386 * Rx and Tx descriptors needs 256 bytes alignment.
6387 * dma_alloc_coherent provides more.
6389 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
6390 &tp->TxPhyAddr, GFP_KERNEL);
6391 if (!tp->TxDescArray)
6392 goto err_pm_runtime_put;
6394 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
6395 &tp->RxPhyAddr, GFP_KERNEL);
6396 if (!tp->RxDescArray)
6399 retval = rtl8169_init_ring(tp);
6403 rtl_request_firmware(tp);
6405 retval = pci_request_irq(pdev, 0, rtl8169_interrupt, NULL, tp,
6408 goto err_release_fw_2;
6410 retval = r8169_phy_connect(tp);
6416 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6418 napi_enable(&tp->napi);
6420 rtl8169_init_phy(dev, tp);
6422 rtl_pll_power_up(tp);
6426 if (!rtl8169_init_counter_offsets(tp))
6427 netif_warn(tp, hw, dev, "counter reset/update failed\n");
6429 phy_start(tp->phydev);
6430 netif_start_queue(dev);
6432 rtl_unlock_work(tp);
6434 pm_runtime_put_sync(&pdev->dev);
6439 pci_free_irq(pdev, 0, tp);
6441 rtl_release_firmware(tp);
6442 rtl8169_rx_clear(tp);
6444 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6446 tp->RxDescArray = NULL;
6448 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6450 tp->TxDescArray = NULL;
6452 pm_runtime_put_noidle(&pdev->dev);
6457 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
6459 struct rtl8169_private *tp = netdev_priv(dev);
6460 struct pci_dev *pdev = tp->pci_dev;
6461 struct rtl8169_counters *counters = tp->counters;
6464 pm_runtime_get_noresume(&pdev->dev);
6466 if (netif_running(dev) && pm_runtime_active(&pdev->dev))
6467 rtl8169_rx_missed(dev);
6470 start = u64_stats_fetch_begin_irq(&tp->rx_stats.syncp);
6471 stats->rx_packets = tp->rx_stats.packets;
6472 stats->rx_bytes = tp->rx_stats.bytes;
6473 } while (u64_stats_fetch_retry_irq(&tp->rx_stats.syncp, start));
6476 start = u64_stats_fetch_begin_irq(&tp->tx_stats.syncp);
6477 stats->tx_packets = tp->tx_stats.packets;
6478 stats->tx_bytes = tp->tx_stats.bytes;
6479 } while (u64_stats_fetch_retry_irq(&tp->tx_stats.syncp, start));
6481 stats->rx_dropped = dev->stats.rx_dropped;
6482 stats->tx_dropped = dev->stats.tx_dropped;
6483 stats->rx_length_errors = dev->stats.rx_length_errors;
6484 stats->rx_errors = dev->stats.rx_errors;
6485 stats->rx_crc_errors = dev->stats.rx_crc_errors;
6486 stats->rx_fifo_errors = dev->stats.rx_fifo_errors;
6487 stats->rx_missed_errors = dev->stats.rx_missed_errors;
6488 stats->multicast = dev->stats.multicast;
6491 * Fetch additonal counter values missing in stats collected by driver
6492 * from tally counters.
6494 if (pm_runtime_active(&pdev->dev))
6495 rtl8169_update_counters(tp);
6498 * Subtract values fetched during initalization.
6499 * See rtl8169_init_counter_offsets for a description why we do that.
6501 stats->tx_errors = le64_to_cpu(counters->tx_errors) -
6502 le64_to_cpu(tp->tc_offset.tx_errors);
6503 stats->collisions = le32_to_cpu(counters->tx_multi_collision) -
6504 le32_to_cpu(tp->tc_offset.tx_multi_collision);
6505 stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) -
6506 le16_to_cpu(tp->tc_offset.tx_aborted);
6508 pm_runtime_put_noidle(&pdev->dev);
6511 static void rtl8169_net_suspend(struct net_device *dev)
6513 struct rtl8169_private *tp = netdev_priv(dev);
6515 if (!netif_running(dev))
6518 phy_stop(tp->phydev);
6519 netif_device_detach(dev);
6522 napi_disable(&tp->napi);
6523 /* Clear all task flags */
6524 bitmap_zero(tp->wk.flags, RTL_FLAG_MAX);
6526 rtl_unlock_work(tp);
6528 rtl_pll_power_down(tp);
6533 static int rtl8169_suspend(struct device *device)
6535 struct net_device *dev = dev_get_drvdata(device);
6536 struct rtl8169_private *tp = netdev_priv(dev);
6538 rtl8169_net_suspend(dev);
6539 clk_disable_unprepare(tp->clk);
6544 static void __rtl8169_resume(struct net_device *dev)
6546 struct rtl8169_private *tp = netdev_priv(dev);
6548 netif_device_attach(dev);
6550 rtl_pll_power_up(tp);
6551 rtl8169_init_phy(dev, tp);
6553 phy_start(tp->phydev);
6556 napi_enable(&tp->napi);
6557 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6559 rtl_unlock_work(tp);
6562 static int rtl8169_resume(struct device *device)
6564 struct net_device *dev = dev_get_drvdata(device);
6565 struct rtl8169_private *tp = netdev_priv(dev);
6567 rtl_rar_set(tp, dev->dev_addr);
6569 clk_prepare_enable(tp->clk);
6571 if (netif_running(dev))
6572 __rtl8169_resume(dev);
6577 static int rtl8169_runtime_suspend(struct device *device)
6579 struct net_device *dev = dev_get_drvdata(device);
6580 struct rtl8169_private *tp = netdev_priv(dev);
6582 if (!tp->TxDescArray)
6586 __rtl8169_set_wol(tp, WAKE_ANY);
6587 rtl_unlock_work(tp);
6589 rtl8169_net_suspend(dev);
6591 /* Update counters before going runtime suspend */
6592 rtl8169_rx_missed(dev);
6593 rtl8169_update_counters(tp);
6598 static int rtl8169_runtime_resume(struct device *device)
6600 struct net_device *dev = dev_get_drvdata(device);
6601 struct rtl8169_private *tp = netdev_priv(dev);
6603 rtl_rar_set(tp, dev->dev_addr);
6605 if (!tp->TxDescArray)
6609 __rtl8169_set_wol(tp, tp->saved_wolopts);
6610 rtl_unlock_work(tp);
6612 __rtl8169_resume(dev);
6617 static int rtl8169_runtime_idle(struct device *device)
6619 struct net_device *dev = dev_get_drvdata(device);
6621 if (!netif_running(dev) || !netif_carrier_ok(dev))
6622 pm_schedule_suspend(device, 10000);
6627 static const struct dev_pm_ops rtl8169_pm_ops = {
6628 .suspend = rtl8169_suspend,
6629 .resume = rtl8169_resume,
6630 .freeze = rtl8169_suspend,
6631 .thaw = rtl8169_resume,
6632 .poweroff = rtl8169_suspend,
6633 .restore = rtl8169_resume,
6634 .runtime_suspend = rtl8169_runtime_suspend,
6635 .runtime_resume = rtl8169_runtime_resume,
6636 .runtime_idle = rtl8169_runtime_idle,
6639 #define RTL8169_PM_OPS (&rtl8169_pm_ops)
6641 #else /* !CONFIG_PM */
6643 #define RTL8169_PM_OPS NULL
6645 #endif /* !CONFIG_PM */
6647 static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
6649 /* WoL fails with 8168b when the receiver is disabled. */
6650 switch (tp->mac_version) {
6651 case RTL_GIGA_MAC_VER_11:
6652 case RTL_GIGA_MAC_VER_12:
6653 case RTL_GIGA_MAC_VER_17:
6654 pci_clear_master(tp->pci_dev);
6656 RTL_W8(tp, ChipCmd, CmdRxEnb);
6658 RTL_R8(tp, ChipCmd);
6665 static void rtl_shutdown(struct pci_dev *pdev)
6667 struct net_device *dev = pci_get_drvdata(pdev);
6668 struct rtl8169_private *tp = netdev_priv(dev);
6670 rtl8169_net_suspend(dev);
6672 /* Restore original MAC address */
6673 rtl_rar_set(tp, dev->perm_addr);
6675 rtl8169_hw_reset(tp);
6677 if (system_state == SYSTEM_POWER_OFF) {
6678 if (tp->saved_wolopts) {
6679 rtl_wol_suspend_quirk(tp);
6680 rtl_wol_shutdown_quirk(tp);
6683 pci_wake_from_d3(pdev, true);
6684 pci_set_power_state(pdev, PCI_D3hot);
6688 static void rtl_remove_one(struct pci_dev *pdev)
6690 struct net_device *dev = pci_get_drvdata(pdev);
6691 struct rtl8169_private *tp = netdev_priv(dev);
6693 if (r8168_check_dash(tp))
6694 rtl8168_driver_stop(tp);
6696 netif_napi_del(&tp->napi);
6698 unregister_netdev(dev);
6699 mdiobus_unregister(tp->phydev->mdio.bus);
6701 rtl_release_firmware(tp);
6703 if (pci_dev_run_wake(pdev))
6704 pm_runtime_get_noresume(&pdev->dev);
6706 /* restore original MAC address */
6707 rtl_rar_set(tp, dev->perm_addr);
6710 static const struct net_device_ops rtl_netdev_ops = {
6711 .ndo_open = rtl_open,
6712 .ndo_stop = rtl8169_close,
6713 .ndo_get_stats64 = rtl8169_get_stats64,
6714 .ndo_start_xmit = rtl8169_start_xmit,
6715 .ndo_tx_timeout = rtl8169_tx_timeout,
6716 .ndo_validate_addr = eth_validate_addr,
6717 .ndo_change_mtu = rtl8169_change_mtu,
6718 .ndo_fix_features = rtl8169_fix_features,
6719 .ndo_set_features = rtl8169_set_features,
6720 .ndo_set_mac_address = rtl_set_mac_address,
6721 .ndo_do_ioctl = rtl8169_ioctl,
6722 .ndo_set_rx_mode = rtl_set_rx_mode,
6723 #ifdef CONFIG_NET_POLL_CONTROLLER
6724 .ndo_poll_controller = rtl8169_netpoll,
6729 static const struct rtl_cfg_info {
6730 void (*hw_start)(struct rtl8169_private *tp);
6732 unsigned int has_gmii:1;
6733 const struct rtl_coalesce_info *coalesce_info;
6734 } rtl_cfg_infos [] = {
6736 .hw_start = rtl_hw_start_8169,
6737 .irq_mask = SYSErr | LinkChg | RxOverflow | RxFIFOOver,
6739 .coalesce_info = rtl_coalesce_info_8169,
6742 .hw_start = rtl_hw_start_8168,
6743 .irq_mask = LinkChg | RxOverflow,
6745 .coalesce_info = rtl_coalesce_info_8168_8136,
6748 .hw_start = rtl_hw_start_8101,
6749 .irq_mask = LinkChg | RxOverflow | RxFIFOOver,
6750 .coalesce_info = rtl_coalesce_info_8168_8136,
6754 static int rtl_alloc_irq(struct rtl8169_private *tp)
6758 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
6759 rtl_unlock_config_regs(tp);
6760 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~MSIEnable);
6761 rtl_lock_config_regs(tp);
6762 flags = PCI_IRQ_LEGACY;
6764 flags = PCI_IRQ_ALL_TYPES;
6767 return pci_alloc_irq_vectors(tp->pci_dev, 1, 1, flags);
6770 static void rtl_read_mac_address(struct rtl8169_private *tp,
6771 u8 mac_addr[ETH_ALEN])
6775 /* Get MAC address */
6776 switch (tp->mac_version) {
6777 case RTL_GIGA_MAC_VER_35 ... RTL_GIGA_MAC_VER_38:
6778 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
6779 value = rtl_eri_read(tp, 0xe0);
6780 mac_addr[0] = (value >> 0) & 0xff;
6781 mac_addr[1] = (value >> 8) & 0xff;
6782 mac_addr[2] = (value >> 16) & 0xff;
6783 mac_addr[3] = (value >> 24) & 0xff;
6785 value = rtl_eri_read(tp, 0xe4);
6786 mac_addr[4] = (value >> 0) & 0xff;
6787 mac_addr[5] = (value >> 8) & 0xff;
6794 DECLARE_RTL_COND(rtl_link_list_ready_cond)
6796 return RTL_R8(tp, MCU) & LINK_LIST_RDY;
6799 DECLARE_RTL_COND(rtl_rxtx_empty_cond)
6801 return (RTL_R8(tp, MCU) & RXTX_EMPTY) == RXTX_EMPTY;
6804 static int r8169_mdio_read_reg(struct mii_bus *mii_bus, int phyaddr, int phyreg)
6806 struct rtl8169_private *tp = mii_bus->priv;
6811 return rtl_readphy(tp, phyreg);
6814 static int r8169_mdio_write_reg(struct mii_bus *mii_bus, int phyaddr,
6815 int phyreg, u16 val)
6817 struct rtl8169_private *tp = mii_bus->priv;
6822 rtl_writephy(tp, phyreg, val);
6827 static int r8169_mdio_register(struct rtl8169_private *tp)
6829 struct pci_dev *pdev = tp->pci_dev;
6830 struct mii_bus *new_bus;
6833 new_bus = devm_mdiobus_alloc(&pdev->dev);
6837 new_bus->name = "r8169";
6839 new_bus->parent = &pdev->dev;
6840 new_bus->irq[0] = PHY_IGNORE_INTERRUPT;
6841 snprintf(new_bus->id, MII_BUS_ID_SIZE, "r8169-%x", pci_dev_id(pdev));
6843 new_bus->read = r8169_mdio_read_reg;
6844 new_bus->write = r8169_mdio_write_reg;
6846 ret = mdiobus_register(new_bus);
6850 tp->phydev = mdiobus_get_phy(new_bus, 0);
6852 mdiobus_unregister(new_bus);
6856 /* PHY will be woken up in rtl_open() */
6857 phy_suspend(tp->phydev);
6862 static void rtl_hw_init_8168g(struct rtl8169_private *tp)
6866 tp->ocp_base = OCP_STD_PHY_BASE;
6868 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN);
6870 if (!rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42))
6873 if (!rtl_udelay_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42))
6876 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
6878 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
6880 data = r8168_mac_ocp_read(tp, 0xe8de);
6882 r8168_mac_ocp_write(tp, 0xe8de, data);
6884 if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
6887 data = r8168_mac_ocp_read(tp, 0xe8de);
6889 r8168_mac_ocp_write(tp, 0xe8de, data);
6891 rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42);
6894 static void rtl_hw_initialize(struct rtl8169_private *tp)
6896 switch (tp->mac_version) {
6897 case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_51:
6898 rtl8168ep_stop_cmac(tp);
6900 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_48:
6901 rtl_hw_init_8168g(tp);
6908 static int rtl_jumbo_max(struct rtl8169_private *tp)
6910 /* Non-GBit versions don't support jumbo frames */
6911 if (!tp->supports_gmii)
6914 switch (tp->mac_version) {
6916 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
6919 case RTL_GIGA_MAC_VER_11:
6920 case RTL_GIGA_MAC_VER_12:
6921 case RTL_GIGA_MAC_VER_17:
6924 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
6931 static void rtl_disable_clk(void *data)
6933 clk_disable_unprepare(data);
6936 static int rtl_get_ether_clk(struct rtl8169_private *tp)
6938 struct device *d = tp_to_dev(tp);
6942 clk = devm_clk_get(d, "ether_clk");
6946 /* clk-core allows NULL (for suspend / resume) */
6948 else if (rc != -EPROBE_DEFER)
6949 dev_err(d, "failed to get clk: %d\n", rc);
6952 rc = clk_prepare_enable(clk);
6954 dev_err(d, "failed to enable clk: %d\n", rc);
6956 rc = devm_add_action_or_reset(d, rtl_disable_clk, clk);
6962 static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
6964 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
6965 /* align to u16 for is_valid_ether_addr() */
6966 u8 mac_addr[ETH_ALEN] __aligned(2) = {};
6967 struct rtl8169_private *tp;
6968 struct net_device *dev;
6969 int chipset, region, i;
6972 dev = devm_alloc_etherdev(&pdev->dev, sizeof (*tp));
6976 SET_NETDEV_DEV(dev, &pdev->dev);
6977 dev->netdev_ops = &rtl_netdev_ops;
6978 tp = netdev_priv(dev);
6981 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
6982 tp->supports_gmii = cfg->has_gmii;
6984 /* Get the *optional* external "ether_clk" used on some boards */
6985 rc = rtl_get_ether_clk(tp);
6989 /* Disable ASPM completely as that cause random device stop working
6990 * problems as well as full system hangs for some PCIe devices users.
6992 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1);
6994 /* enable device (incl. PCI PM wakeup and hotplug setup) */
6995 rc = pcim_enable_device(pdev);
6997 dev_err(&pdev->dev, "enable failure\n");
7001 if (pcim_set_mwi(pdev) < 0)
7002 dev_info(&pdev->dev, "Mem-Wr-Inval unavailable\n");
7004 /* use first MMIO region */
7005 region = ffs(pci_select_bars(pdev, IORESOURCE_MEM)) - 1;
7007 dev_err(&pdev->dev, "no MMIO resource found\n");
7011 /* check for weird/broken PCI region reporting */
7012 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
7013 dev_err(&pdev->dev, "Invalid PCI region size(s), aborting\n");
7017 rc = pcim_iomap_regions(pdev, BIT(region), MODULENAME);
7019 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
7023 tp->mmio_addr = pcim_iomap_table(pdev)[region];
7025 /* Identify chip attached to board */
7026 rtl8169_get_mac_version(tp);
7027 if (tp->mac_version == RTL_GIGA_MAC_NONE)
7030 tp->cp_cmd = RTL_R16(tp, CPlusCmd);
7032 if (sizeof(dma_addr_t) > 4 && tp->mac_version >= RTL_GIGA_MAC_VER_18 &&
7033 !dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) {
7034 dev->features |= NETIF_F_HIGHDMA;
7036 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
7038 dev_err(&pdev->dev, "DMA configuration failed\n");
7045 rtl8169_irq_mask_and_ack(tp);
7047 rtl_hw_initialize(tp);
7051 pci_set_master(pdev);
7053 chipset = tp->mac_version;
7055 rc = rtl_alloc_irq(tp);
7057 dev_err(&pdev->dev, "Can't allocate interrupt\n");
7061 mutex_init(&tp->wk.mutex);
7062 INIT_WORK(&tp->wk.work, rtl_task);
7063 u64_stats_init(&tp->rx_stats.syncp);
7064 u64_stats_init(&tp->tx_stats.syncp);
7066 /* get MAC address */
7067 rc = eth_platform_get_mac_address(&pdev->dev, mac_addr);
7069 rtl_read_mac_address(tp, mac_addr);
7071 if (is_valid_ether_addr(mac_addr))
7072 rtl_rar_set(tp, mac_addr);
7074 for (i = 0; i < ETH_ALEN; i++)
7075 dev->dev_addr[i] = RTL_R8(tp, MAC0 + i);
7077 dev->ethtool_ops = &rtl8169_ethtool_ops;
7079 netif_napi_add(dev, &tp->napi, rtl8169_poll, NAPI_POLL_WEIGHT);
7081 /* don't enable SG, IP_CSUM and TSO by default - it might not work
7082 * properly for all devices */
7083 dev->features |= NETIF_F_RXCSUM |
7084 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
7086 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
7087 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_TX |
7088 NETIF_F_HW_VLAN_CTAG_RX;
7089 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
7091 dev->priv_flags |= IFF_LIVE_ADDR_CHANGE;
7093 tp->cp_cmd |= RxChkSum | RxVlan;
7096 * Pretend we are using VLANs; This bypasses a nasty bug where
7097 * Interrupts stop flowing on high load on 8110SCd controllers.
7099 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
7100 /* Disallow toggling */
7101 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX;
7103 if (rtl_chip_supports_csum_v2(tp))
7104 dev->hw_features |= NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
7106 dev->hw_features |= NETIF_F_RXALL;
7107 dev->hw_features |= NETIF_F_RXFCS;
7109 /* MTU range: 60 - hw-specific max */
7110 dev->min_mtu = ETH_ZLEN;
7111 jumbo_max = rtl_jumbo_max(tp);
7112 dev->max_mtu = jumbo_max;
7114 tp->hw_start = cfg->hw_start;
7115 tp->irq_mask = RTL_EVENT_NAPI | cfg->irq_mask;
7116 tp->coalesce_info = cfg->coalesce_info;
7118 tp->fw_name = rtl_chip_infos[chipset].fw_name;
7120 tp->counters = dmam_alloc_coherent (&pdev->dev, sizeof(*tp->counters),
7121 &tp->counters_phys_addr,
7126 pci_set_drvdata(pdev, dev);
7128 rc = r8169_mdio_register(tp);
7132 /* chip gets powered up in rtl_open() */
7133 rtl_pll_power_down(tp);
7135 rc = register_netdev(dev);
7137 goto err_mdio_unregister;
7139 netif_info(tp, probe, dev, "%s, %pM, XID %03x, IRQ %d\n",
7140 rtl_chip_infos[chipset].name, dev->dev_addr,
7141 (RTL_R32(tp, TxConfig) >> 20) & 0xfcf,
7142 pci_irq_vector(pdev, 0));
7144 if (jumbo_max > JUMBO_1K)
7145 netif_info(tp, probe, dev,
7146 "jumbo features [frames: %d bytes, tx checksumming: %s]\n",
7147 jumbo_max, tp->mac_version <= RTL_GIGA_MAC_VER_06 ?
7150 if (r8168_check_dash(tp))
7151 rtl8168_driver_start(tp);
7153 if (pci_dev_run_wake(pdev))
7154 pm_runtime_put_sync(&pdev->dev);
7158 err_mdio_unregister:
7159 mdiobus_unregister(tp->phydev->mdio.bus);
7163 static struct pci_driver rtl8169_pci_driver = {
7165 .id_table = rtl8169_pci_tbl,
7166 .probe = rtl_init_one,
7167 .remove = rtl_remove_one,
7168 .shutdown = rtl_shutdown,
7169 .driver.pm = RTL8169_PM_OPS,
7172 module_pci_driver(rtl8169_pci_driver);