1 // SPDX-License-Identifier: GPL-2.0
2 /* SuperH Ethernet device driver
4 * Copyright (C) 2014 Renesas Electronics Corporation
5 * Copyright (C) 2006-2012 Nobuhiro Iwamatsu
6 * Copyright (C) 2008-2014 Renesas Solutions Corp.
7 * Copyright (C) 2013-2017 Cogent Embedded, Inc.
8 * Copyright (C) 2014 Codethink Limited
11 #include <linux/module.h>
12 #include <linux/kernel.h>
13 #include <linux/spinlock.h>
14 #include <linux/interrupt.h>
15 #include <linux/dma-mapping.h>
16 #include <linux/etherdevice.h>
17 #include <linux/delay.h>
18 #include <linux/platform_device.h>
19 #include <linux/mdio-bitbang.h>
20 #include <linux/netdevice.h>
22 #include <linux/of_device.h>
23 #include <linux/of_irq.h>
24 #include <linux/of_net.h>
25 #include <linux/phy.h>
26 #include <linux/cache.h>
28 #include <linux/pm_runtime.h>
29 #include <linux/slab.h>
30 #include <linux/ethtool.h>
31 #include <linux/if_vlan.h>
32 #include <linux/sh_eth.h>
33 #include <linux/of_mdio.h>
37 #define SH_ETH_DEF_MSG_ENABLE \
43 #define SH_ETH_OFFSET_INVALID ((u16)~0)
45 #define SH_ETH_OFFSET_DEFAULTS \
46 [0 ... SH_ETH_MAX_REGISTER_OFFSET - 1] = SH_ETH_OFFSET_INVALID
48 static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = {
49 SH_ETH_OFFSET_DEFAULTS,
104 [TSU_CTRST] = 0x0004,
105 [TSU_FWEN0] = 0x0010,
106 [TSU_FWEN1] = 0x0014,
108 [TSU_BSYSL0] = 0x0020,
109 [TSU_BSYSL1] = 0x0024,
110 [TSU_PRISL0] = 0x0028,
111 [TSU_PRISL1] = 0x002c,
112 [TSU_FWSL0] = 0x0030,
113 [TSU_FWSL1] = 0x0034,
114 [TSU_FWSLC] = 0x0038,
115 [TSU_QTAGM0] = 0x0040,
116 [TSU_QTAGM1] = 0x0044,
118 [TSU_FWINMK] = 0x0054,
119 [TSU_ADQT0] = 0x0048,
120 [TSU_ADQT1] = 0x004c,
121 [TSU_VTAG0] = 0x0058,
122 [TSU_VTAG1] = 0x005c,
123 [TSU_ADSBSY] = 0x0060,
125 [TSU_POST1] = 0x0070,
126 [TSU_POST2] = 0x0074,
127 [TSU_POST3] = 0x0078,
128 [TSU_POST4] = 0x007c,
129 [TSU_ADRH0] = 0x0100,
145 static const u16 sh_eth_offset_fast_rz[SH_ETH_MAX_REGISTER_OFFSET] = {
146 SH_ETH_OFFSET_DEFAULTS,
191 [TSU_CTRST] = 0x0004,
192 [TSU_FWSLC] = 0x0038,
193 [TSU_VTAG0] = 0x0058,
194 [TSU_ADSBSY] = 0x0060,
196 [TSU_POST1] = 0x0070,
197 [TSU_POST2] = 0x0074,
198 [TSU_POST3] = 0x0078,
199 [TSU_POST4] = 0x007c,
200 [TSU_ADRH0] = 0x0100,
208 static const u16 sh_eth_offset_fast_rcar[SH_ETH_MAX_REGISTER_OFFSET] = {
209 SH_ETH_OFFSET_DEFAULTS,
256 static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
257 SH_ETH_OFFSET_DEFAULTS,
310 static const u16 sh_eth_offset_fast_sh3_sh2[SH_ETH_MAX_REGISTER_OFFSET] = {
311 SH_ETH_OFFSET_DEFAULTS,
359 [TSU_CTRST] = 0x0004,
360 [TSU_FWEN0] = 0x0010,
361 [TSU_FWEN1] = 0x0014,
363 [TSU_BSYSL0] = 0x0020,
364 [TSU_BSYSL1] = 0x0024,
365 [TSU_PRISL0] = 0x0028,
366 [TSU_PRISL1] = 0x002c,
367 [TSU_FWSL0] = 0x0030,
368 [TSU_FWSL1] = 0x0034,
369 [TSU_FWSLC] = 0x0038,
370 [TSU_QTAGM0] = 0x0040,
371 [TSU_QTAGM1] = 0x0044,
372 [TSU_ADQT0] = 0x0048,
373 [TSU_ADQT1] = 0x004c,
375 [TSU_FWINMK] = 0x0054,
376 [TSU_ADSBSY] = 0x0060,
378 [TSU_POST1] = 0x0070,
379 [TSU_POST2] = 0x0074,
380 [TSU_POST3] = 0x0078,
381 [TSU_POST4] = 0x007c,
396 [TSU_ADRH0] = 0x0100,
399 static void sh_eth_rcv_snd_disable(struct net_device *ndev);
400 static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev);
402 static void sh_eth_write(struct net_device *ndev, u32 data, int enum_index)
404 struct sh_eth_private *mdp = netdev_priv(ndev);
405 u16 offset = mdp->reg_offset[enum_index];
407 if (WARN_ON(offset == SH_ETH_OFFSET_INVALID))
410 iowrite32(data, mdp->addr + offset);
413 static u32 sh_eth_read(struct net_device *ndev, int enum_index)
415 struct sh_eth_private *mdp = netdev_priv(ndev);
416 u16 offset = mdp->reg_offset[enum_index];
418 if (WARN_ON(offset == SH_ETH_OFFSET_INVALID))
421 return ioread32(mdp->addr + offset);
424 static void sh_eth_modify(struct net_device *ndev, int enum_index, u32 clear,
427 sh_eth_write(ndev, (sh_eth_read(ndev, enum_index) & ~clear) | set,
431 static u16 sh_eth_tsu_get_offset(struct sh_eth_private *mdp, int enum_index)
433 return mdp->reg_offset[enum_index];
436 static void sh_eth_tsu_write(struct sh_eth_private *mdp, u32 data,
439 u16 offset = sh_eth_tsu_get_offset(mdp, enum_index);
441 if (WARN_ON(offset == SH_ETH_OFFSET_INVALID))
444 iowrite32(data, mdp->tsu_addr + offset);
447 static u32 sh_eth_tsu_read(struct sh_eth_private *mdp, int enum_index)
449 u16 offset = sh_eth_tsu_get_offset(mdp, enum_index);
451 if (WARN_ON(offset == SH_ETH_OFFSET_INVALID))
454 return ioread32(mdp->tsu_addr + offset);
457 static void sh_eth_soft_swap(char *src, int len)
459 #ifdef __LITTLE_ENDIAN
461 u32 *maxp = p + DIV_ROUND_UP(len, sizeof(u32));
463 for (; p < maxp; p++)
468 static void sh_eth_select_mii(struct net_device *ndev)
470 struct sh_eth_private *mdp = netdev_priv(ndev);
473 switch (mdp->phy_interface) {
474 case PHY_INTERFACE_MODE_RGMII ... PHY_INTERFACE_MODE_RGMII_TXID:
477 case PHY_INTERFACE_MODE_GMII:
480 case PHY_INTERFACE_MODE_MII:
483 case PHY_INTERFACE_MODE_RMII:
488 "PHY interface mode was not setup. Set to MII.\n");
493 sh_eth_write(ndev, value, RMII_MII);
496 static void sh_eth_set_duplex(struct net_device *ndev)
498 struct sh_eth_private *mdp = netdev_priv(ndev);
500 sh_eth_modify(ndev, ECMR, ECMR_DM, mdp->duplex ? ECMR_DM : 0);
503 static void sh_eth_chip_reset(struct net_device *ndev)
505 struct sh_eth_private *mdp = netdev_priv(ndev);
508 sh_eth_tsu_write(mdp, ARSTR_ARST, ARSTR);
512 static int sh_eth_soft_reset(struct net_device *ndev)
514 sh_eth_modify(ndev, EDMR, EDMR_SRST_ETHER, EDMR_SRST_ETHER);
516 sh_eth_modify(ndev, EDMR, EDMR_SRST_ETHER, 0);
521 static int sh_eth_check_soft_reset(struct net_device *ndev)
525 for (cnt = 100; cnt > 0; cnt--) {
526 if (!(sh_eth_read(ndev, EDMR) & EDMR_SRST_GETHER))
531 netdev_err(ndev, "Device reset failed\n");
535 static int sh_eth_soft_reset_gether(struct net_device *ndev)
537 struct sh_eth_private *mdp = netdev_priv(ndev);
540 sh_eth_write(ndev, EDSR_ENALL, EDSR);
541 sh_eth_modify(ndev, EDMR, EDMR_SRST_GETHER, EDMR_SRST_GETHER);
543 ret = sh_eth_check_soft_reset(ndev);
548 sh_eth_write(ndev, 0, TDLAR);
549 sh_eth_write(ndev, 0, TDFAR);
550 sh_eth_write(ndev, 0, TDFXR);
551 sh_eth_write(ndev, 0, TDFFR);
552 sh_eth_write(ndev, 0, RDLAR);
553 sh_eth_write(ndev, 0, RDFAR);
554 sh_eth_write(ndev, 0, RDFXR);
555 sh_eth_write(ndev, 0, RDFFR);
557 /* Reset HW CRC register */
559 sh_eth_write(ndev, 0, CSMR);
561 /* Select MII mode */
562 if (mdp->cd->select_mii)
563 sh_eth_select_mii(ndev);
568 static void sh_eth_set_rate_gether(struct net_device *ndev)
570 struct sh_eth_private *mdp = netdev_priv(ndev);
572 switch (mdp->speed) {
573 case 10: /* 10BASE */
574 sh_eth_write(ndev, GECMR_10, GECMR);
576 case 100:/* 100BASE */
577 sh_eth_write(ndev, GECMR_100, GECMR);
579 case 1000: /* 1000BASE */
580 sh_eth_write(ndev, GECMR_1000, GECMR);
587 static struct sh_eth_cpu_data r7s72100_data = {
588 .soft_reset = sh_eth_soft_reset_gether,
590 .chip_reset = sh_eth_chip_reset,
591 .set_duplex = sh_eth_set_duplex,
593 .register_type = SH_ETH_REG_FAST_RZ,
595 .edtrr_trns = EDTRR_TRNS_GETHER,
596 .ecsr_value = ECSR_ICD,
597 .ecsipr_value = ECSIPR_ICDIP,
598 .eesipr_value = EESIPR_TWB1IP | EESIPR_TWBIP | EESIPR_TC1IP |
599 EESIPR_TABTIP | EESIPR_RABTIP | EESIPR_RFCOFIP |
601 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
602 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
603 EESIPR_RMAFIP | EESIPR_RRFIP |
604 EESIPR_RTLFIP | EESIPR_RTSFIP |
605 EESIPR_PREIP | EESIPR_CERFIP,
607 .tx_check = EESR_TC1 | EESR_FTC,
608 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
609 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
611 .fdr_value = 0x0000070f,
628 static void sh_eth_chip_reset_r8a7740(struct net_device *ndev)
630 sh_eth_chip_reset(ndev);
632 sh_eth_select_mii(ndev);
636 static struct sh_eth_cpu_data r8a7740_data = {
637 .soft_reset = sh_eth_soft_reset_gether,
639 .chip_reset = sh_eth_chip_reset_r8a7740,
640 .set_duplex = sh_eth_set_duplex,
641 .set_rate = sh_eth_set_rate_gether,
643 .register_type = SH_ETH_REG_GIGABIT,
645 .edtrr_trns = EDTRR_TRNS_GETHER,
646 .ecsr_value = ECSR_ICD | ECSR_MPD,
647 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
648 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP |
649 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
650 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
651 0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP |
652 EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP |
653 EESIPR_CEEFIP | EESIPR_CELFIP |
654 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
655 EESIPR_PREIP | EESIPR_CERFIP,
657 .tx_check = EESR_TC1 | EESR_FTC,
658 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
659 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
661 .fdr_value = 0x0000070f,
680 /* There is CPU dependent code */
681 static void sh_eth_set_rate_rcar(struct net_device *ndev)
683 struct sh_eth_private *mdp = netdev_priv(ndev);
685 switch (mdp->speed) {
686 case 10: /* 10BASE */
687 sh_eth_modify(ndev, ECMR, ECMR_ELB, 0);
689 case 100:/* 100BASE */
690 sh_eth_modify(ndev, ECMR, ECMR_ELB, ECMR_ELB);
696 static struct sh_eth_cpu_data rcar_gen1_data = {
697 .soft_reset = sh_eth_soft_reset,
699 .set_duplex = sh_eth_set_duplex,
700 .set_rate = sh_eth_set_rate_rcar,
702 .register_type = SH_ETH_REG_FAST_RCAR,
704 .edtrr_trns = EDTRR_TRNS_ETHER,
705 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
706 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
707 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ADEIP | EESIPR_ECIIP |
708 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
709 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
710 EESIPR_RMAFIP | EESIPR_RRFIP |
711 EESIPR_RTLFIP | EESIPR_RTSFIP |
712 EESIPR_PREIP | EESIPR_CERFIP,
714 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_TRO,
715 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
716 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE,
717 .fdr_value = 0x00000f0f,
726 /* R-Car Gen2 and RZ/G1 */
727 static struct sh_eth_cpu_data rcar_gen2_data = {
728 .soft_reset = sh_eth_soft_reset,
730 .set_duplex = sh_eth_set_duplex,
731 .set_rate = sh_eth_set_rate_rcar,
733 .register_type = SH_ETH_REG_FAST_RCAR,
735 .edtrr_trns = EDTRR_TRNS_ETHER,
736 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD | ECSR_MPD,
737 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP |
739 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ADEIP | EESIPR_ECIIP |
740 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
741 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
742 EESIPR_RMAFIP | EESIPR_RRFIP |
743 EESIPR_RTLFIP | EESIPR_RTSFIP |
744 EESIPR_PREIP | EESIPR_CERFIP,
746 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_TRO,
747 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
748 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE,
749 .fdr_value = 0x00000f0f,
751 .trscer_err_mask = DESC_I_RINT8,
763 static struct sh_eth_cpu_data r8a77980_data = {
764 .soft_reset = sh_eth_soft_reset_gether,
766 .set_duplex = sh_eth_set_duplex,
767 .set_rate = sh_eth_set_rate_gether,
769 .register_type = SH_ETH_REG_GIGABIT,
771 .edtrr_trns = EDTRR_TRNS_GETHER,
772 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD | ECSR_MPD,
773 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP |
775 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP |
776 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
777 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
778 EESIPR_RMAFIP | EESIPR_RRFIP |
779 EESIPR_RTLFIP | EESIPR_RTSFIP |
780 EESIPR_PREIP | EESIPR_CERFIP,
782 .tx_check = EESR_FTC | EESR_CD | EESR_TRO,
783 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
784 EESR_RFE | EESR_RDE | EESR_RFRMER |
785 EESR_TFE | EESR_TDE | EESR_ECI,
786 .fdr_value = 0x0000070f,
806 static struct sh_eth_cpu_data r7s9210_data = {
807 .soft_reset = sh_eth_soft_reset,
809 .set_duplex = sh_eth_set_duplex,
810 .set_rate = sh_eth_set_rate_rcar,
812 .register_type = SH_ETH_REG_FAST_SH4,
814 .edtrr_trns = EDTRR_TRNS_ETHER,
815 .ecsr_value = ECSR_ICD,
816 .ecsipr_value = ECSIPR_ICDIP,
817 .eesipr_value = EESIPR_TWBIP | EESIPR_TABTIP | EESIPR_RABTIP |
818 EESIPR_RFCOFIP | EESIPR_ECIIP | EESIPR_FTCIP |
819 EESIPR_TDEIP | EESIPR_TFUFIP | EESIPR_FRIP |
820 EESIPR_RDEIP | EESIPR_RFOFIP | EESIPR_CNDIP |
821 EESIPR_DLCIP | EESIPR_CDIP | EESIPR_TROIP |
822 EESIPR_RMAFIP | EESIPR_RRFIP | EESIPR_RTLFIP |
823 EESIPR_RTSFIP | EESIPR_PREIP | EESIPR_CERFIP,
825 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_TRO,
826 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
827 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE,
829 .fdr_value = 0x0000070f,
839 #endif /* CONFIG_OF */
841 static void sh_eth_set_rate_sh7724(struct net_device *ndev)
843 struct sh_eth_private *mdp = netdev_priv(ndev);
845 switch (mdp->speed) {
846 case 10: /* 10BASE */
847 sh_eth_modify(ndev, ECMR, ECMR_RTM, 0);
849 case 100:/* 100BASE */
850 sh_eth_modify(ndev, ECMR, ECMR_RTM, ECMR_RTM);
856 static struct sh_eth_cpu_data sh7724_data = {
857 .soft_reset = sh_eth_soft_reset,
859 .set_duplex = sh_eth_set_duplex,
860 .set_rate = sh_eth_set_rate_sh7724,
862 .register_type = SH_ETH_REG_FAST_SH4,
864 .edtrr_trns = EDTRR_TRNS_ETHER,
865 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
866 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
867 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ADEIP | EESIPR_ECIIP |
868 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
869 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
870 EESIPR_RMAFIP | EESIPR_RRFIP |
871 EESIPR_RTLFIP | EESIPR_RTSFIP |
872 EESIPR_PREIP | EESIPR_CERFIP,
874 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_TRO,
875 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
876 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE,
885 static void sh_eth_set_rate_sh7757(struct net_device *ndev)
887 struct sh_eth_private *mdp = netdev_priv(ndev);
889 switch (mdp->speed) {
890 case 10: /* 10BASE */
891 sh_eth_write(ndev, 0, RTRATE);
893 case 100:/* 100BASE */
894 sh_eth_write(ndev, 1, RTRATE);
900 static struct sh_eth_cpu_data sh7757_data = {
901 .soft_reset = sh_eth_soft_reset,
903 .set_duplex = sh_eth_set_duplex,
904 .set_rate = sh_eth_set_rate_sh7757,
906 .register_type = SH_ETH_REG_FAST_SH4,
908 .edtrr_trns = EDTRR_TRNS_ETHER,
909 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP |
910 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
911 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
912 0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP |
913 EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP |
914 EESIPR_CEEFIP | EESIPR_CELFIP |
915 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
916 EESIPR_PREIP | EESIPR_CERFIP,
918 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_TRO,
919 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
920 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE,
922 .irq_flags = IRQF_SHARED,
933 #define SH_GIGA_ETH_BASE 0xfee00000UL
934 #define GIGA_MALR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c8)
935 #define GIGA_MAHR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c0)
936 static void sh_eth_chip_reset_giga(struct net_device *ndev)
938 u32 mahr[2], malr[2];
941 /* save MAHR and MALR */
942 for (i = 0; i < 2; i++) {
943 malr[i] = ioread32((void *)GIGA_MALR(i));
944 mahr[i] = ioread32((void *)GIGA_MAHR(i));
947 sh_eth_chip_reset(ndev);
949 /* restore MAHR and MALR */
950 for (i = 0; i < 2; i++) {
951 iowrite32(malr[i], (void *)GIGA_MALR(i));
952 iowrite32(mahr[i], (void *)GIGA_MAHR(i));
956 static void sh_eth_set_rate_giga(struct net_device *ndev)
958 struct sh_eth_private *mdp = netdev_priv(ndev);
960 switch (mdp->speed) {
961 case 10: /* 10BASE */
962 sh_eth_write(ndev, 0x00000000, GECMR);
964 case 100:/* 100BASE */
965 sh_eth_write(ndev, 0x00000010, GECMR);
967 case 1000: /* 1000BASE */
968 sh_eth_write(ndev, 0x00000020, GECMR);
973 /* SH7757(GETHERC) */
974 static struct sh_eth_cpu_data sh7757_data_giga = {
975 .soft_reset = sh_eth_soft_reset_gether,
977 .chip_reset = sh_eth_chip_reset_giga,
978 .set_duplex = sh_eth_set_duplex,
979 .set_rate = sh_eth_set_rate_giga,
981 .register_type = SH_ETH_REG_GIGABIT,
983 .edtrr_trns = EDTRR_TRNS_GETHER,
984 .ecsr_value = ECSR_ICD | ECSR_MPD,
985 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
986 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP |
987 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
988 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
989 0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP |
990 EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP |
991 EESIPR_CEEFIP | EESIPR_CELFIP |
992 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
993 EESIPR_PREIP | EESIPR_CERFIP,
995 .tx_check = EESR_TC1 | EESR_FTC,
996 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
997 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
999 .fdr_value = 0x0000072f,
1001 .irq_flags = IRQF_SHARED,
1017 static struct sh_eth_cpu_data sh7734_data = {
1018 .soft_reset = sh_eth_soft_reset_gether,
1020 .chip_reset = sh_eth_chip_reset,
1021 .set_duplex = sh_eth_set_duplex,
1022 .set_rate = sh_eth_set_rate_gether,
1024 .register_type = SH_ETH_REG_GIGABIT,
1026 .edtrr_trns = EDTRR_TRNS_GETHER,
1027 .ecsr_value = ECSR_ICD | ECSR_MPD,
1028 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
1029 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP |
1030 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
1031 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
1032 EESIPR_DLCIP | EESIPR_CDIP | EESIPR_TROIP |
1033 EESIPR_RMAFIP | EESIPR_CEEFIP | EESIPR_CELFIP |
1034 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
1035 EESIPR_PREIP | EESIPR_CERFIP,
1037 .tx_check = EESR_TC1 | EESR_FTC,
1038 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
1039 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
1059 static struct sh_eth_cpu_data sh7763_data = {
1060 .soft_reset = sh_eth_soft_reset_gether,
1062 .chip_reset = sh_eth_chip_reset,
1063 .set_duplex = sh_eth_set_duplex,
1064 .set_rate = sh_eth_set_rate_gether,
1066 .register_type = SH_ETH_REG_GIGABIT,
1068 .edtrr_trns = EDTRR_TRNS_GETHER,
1069 .ecsr_value = ECSR_ICD | ECSR_MPD,
1070 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
1071 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP |
1072 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
1073 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
1074 EESIPR_DLCIP | EESIPR_CDIP | EESIPR_TROIP |
1075 EESIPR_RMAFIP | EESIPR_CEEFIP | EESIPR_CELFIP |
1076 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
1077 EESIPR_PREIP | EESIPR_CERFIP,
1079 .tx_check = EESR_TC1 | EESR_FTC,
1080 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
1081 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE,
1092 .irq_flags = IRQF_SHARED,
1099 static struct sh_eth_cpu_data sh7619_data = {
1100 .soft_reset = sh_eth_soft_reset,
1102 .register_type = SH_ETH_REG_FAST_SH3_SH2,
1104 .edtrr_trns = EDTRR_TRNS_ETHER,
1105 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP |
1106 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
1107 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
1108 0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP |
1109 EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP |
1110 EESIPR_CEEFIP | EESIPR_CELFIP |
1111 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
1112 EESIPR_PREIP | EESIPR_CERFIP,
1120 static struct sh_eth_cpu_data sh771x_data = {
1121 .soft_reset = sh_eth_soft_reset,
1123 .register_type = SH_ETH_REG_FAST_SH3_SH2,
1125 .edtrr_trns = EDTRR_TRNS_ETHER,
1126 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP |
1127 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
1128 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
1129 0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP |
1130 EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP |
1131 EESIPR_CEEFIP | EESIPR_CELFIP |
1132 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
1133 EESIPR_PREIP | EESIPR_CERFIP,
1138 static void sh_eth_set_default_cpu_data(struct sh_eth_cpu_data *cd)
1140 if (!cd->ecsr_value)
1141 cd->ecsr_value = DEFAULT_ECSR_INIT;
1143 if (!cd->ecsipr_value)
1144 cd->ecsipr_value = DEFAULT_ECSIPR_INIT;
1146 if (!cd->fcftr_value)
1147 cd->fcftr_value = DEFAULT_FIFO_F_D_RFF |
1148 DEFAULT_FIFO_F_D_RFD;
1151 cd->fdr_value = DEFAULT_FDR_INIT;
1154 cd->tx_check = DEFAULT_TX_CHECK;
1156 if (!cd->eesr_err_check)
1157 cd->eesr_err_check = DEFAULT_EESR_ERR_CHECK;
1159 if (!cd->trscer_err_mask)
1160 cd->trscer_err_mask = DEFAULT_TRSCER_ERR_MASK;
1163 static void sh_eth_set_receive_align(struct sk_buff *skb)
1165 uintptr_t reserve = (uintptr_t)skb->data & (SH_ETH_RX_ALIGN - 1);
1168 skb_reserve(skb, SH_ETH_RX_ALIGN - reserve);
1171 /* Program the hardware MAC address from dev->dev_addr. */
1172 static void update_mac_address(struct net_device *ndev)
1175 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) |
1176 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR);
1178 (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR);
1181 /* Get MAC address from SuperH MAC address register
1183 * SuperH's Ethernet device doesn't have 'ROM' to MAC address.
1184 * This driver get MAC address that use by bootloader(U-boot or sh-ipl+g).
1185 * When you want use this device, you must set MAC address in bootloader.
1188 static void read_mac_address(struct net_device *ndev, unsigned char *mac)
1190 if (mac[0] || mac[1] || mac[2] || mac[3] || mac[4] || mac[5]) {
1191 memcpy(ndev->dev_addr, mac, ETH_ALEN);
1193 u32 mahr = sh_eth_read(ndev, MAHR);
1194 u32 malr = sh_eth_read(ndev, MALR);
1196 ndev->dev_addr[0] = (mahr >> 24) & 0xFF;
1197 ndev->dev_addr[1] = (mahr >> 16) & 0xFF;
1198 ndev->dev_addr[2] = (mahr >> 8) & 0xFF;
1199 ndev->dev_addr[3] = (mahr >> 0) & 0xFF;
1200 ndev->dev_addr[4] = (malr >> 8) & 0xFF;
1201 ndev->dev_addr[5] = (malr >> 0) & 0xFF;
1206 void (*set_gate)(void *addr);
1207 struct mdiobb_ctrl ctrl;
1211 static void sh_mdio_ctrl(struct mdiobb_ctrl *ctrl, u32 mask, int set)
1213 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1216 if (bitbang->set_gate)
1217 bitbang->set_gate(bitbang->addr);
1219 pir = ioread32(bitbang->addr);
1224 iowrite32(pir, bitbang->addr);
1227 /* Data I/O pin control */
1228 static void sh_mmd_ctrl(struct mdiobb_ctrl *ctrl, int bit)
1230 sh_mdio_ctrl(ctrl, PIR_MMD, bit);
1234 static void sh_set_mdio(struct mdiobb_ctrl *ctrl, int bit)
1236 sh_mdio_ctrl(ctrl, PIR_MDO, bit);
1240 static int sh_get_mdio(struct mdiobb_ctrl *ctrl)
1242 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1244 if (bitbang->set_gate)
1245 bitbang->set_gate(bitbang->addr);
1247 return (ioread32(bitbang->addr) & PIR_MDI) != 0;
1250 /* MDC pin control */
1251 static void sh_mdc_ctrl(struct mdiobb_ctrl *ctrl, int bit)
1253 sh_mdio_ctrl(ctrl, PIR_MDC, bit);
1256 /* mdio bus control struct */
1257 static struct mdiobb_ops bb_ops = {
1258 .owner = THIS_MODULE,
1259 .set_mdc = sh_mdc_ctrl,
1260 .set_mdio_dir = sh_mmd_ctrl,
1261 .set_mdio_data = sh_set_mdio,
1262 .get_mdio_data = sh_get_mdio,
1265 /* free Tx skb function */
1266 static int sh_eth_tx_free(struct net_device *ndev, bool sent_only)
1268 struct sh_eth_private *mdp = netdev_priv(ndev);
1269 struct sh_eth_txdesc *txdesc;
1274 for (; mdp->cur_tx - mdp->dirty_tx > 0; mdp->dirty_tx++) {
1275 entry = mdp->dirty_tx % mdp->num_tx_ring;
1276 txdesc = &mdp->tx_ring[entry];
1277 sent = !(txdesc->status & cpu_to_le32(TD_TACT));
1278 if (sent_only && !sent)
1280 /* TACT bit must be checked before all the following reads */
1282 netif_info(mdp, tx_done, ndev,
1283 "tx entry %d status 0x%08x\n",
1284 entry, le32_to_cpu(txdesc->status));
1285 /* Free the original skb. */
1286 if (mdp->tx_skbuff[entry]) {
1287 dma_unmap_single(&mdp->pdev->dev,
1288 le32_to_cpu(txdesc->addr),
1289 le32_to_cpu(txdesc->len) >> 16,
1291 dev_kfree_skb_irq(mdp->tx_skbuff[entry]);
1292 mdp->tx_skbuff[entry] = NULL;
1295 txdesc->status = cpu_to_le32(TD_TFP);
1296 if (entry >= mdp->num_tx_ring - 1)
1297 txdesc->status |= cpu_to_le32(TD_TDLE);
1300 ndev->stats.tx_packets++;
1301 ndev->stats.tx_bytes += le32_to_cpu(txdesc->len) >> 16;
1307 /* free skb and descriptor buffer */
1308 static void sh_eth_ring_free(struct net_device *ndev)
1310 struct sh_eth_private *mdp = netdev_priv(ndev);
1314 for (i = 0; i < mdp->num_rx_ring; i++) {
1315 if (mdp->rx_skbuff[i]) {
1316 struct sh_eth_rxdesc *rxdesc = &mdp->rx_ring[i];
1318 dma_unmap_single(&mdp->pdev->dev,
1319 le32_to_cpu(rxdesc->addr),
1320 ALIGN(mdp->rx_buf_sz, 32),
1324 ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
1325 dma_free_coherent(&mdp->pdev->dev, ringsize, mdp->rx_ring,
1327 mdp->rx_ring = NULL;
1330 /* Free Rx skb ringbuffer */
1331 if (mdp->rx_skbuff) {
1332 for (i = 0; i < mdp->num_rx_ring; i++)
1333 dev_kfree_skb(mdp->rx_skbuff[i]);
1335 kfree(mdp->rx_skbuff);
1336 mdp->rx_skbuff = NULL;
1339 sh_eth_tx_free(ndev, false);
1341 ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
1342 dma_free_coherent(&mdp->pdev->dev, ringsize, mdp->tx_ring,
1344 mdp->tx_ring = NULL;
1347 /* Free Tx skb ringbuffer */
1348 kfree(mdp->tx_skbuff);
1349 mdp->tx_skbuff = NULL;
1352 /* format skb and descriptor buffer */
1353 static void sh_eth_ring_format(struct net_device *ndev)
1355 struct sh_eth_private *mdp = netdev_priv(ndev);
1357 struct sk_buff *skb;
1358 struct sh_eth_rxdesc *rxdesc = NULL;
1359 struct sh_eth_txdesc *txdesc = NULL;
1360 int rx_ringsize = sizeof(*rxdesc) * mdp->num_rx_ring;
1361 int tx_ringsize = sizeof(*txdesc) * mdp->num_tx_ring;
1362 int skbuff_size = mdp->rx_buf_sz + SH_ETH_RX_ALIGN + 32 - 1;
1363 dma_addr_t dma_addr;
1371 memset(mdp->rx_ring, 0, rx_ringsize);
1373 /* build Rx ring buffer */
1374 for (i = 0; i < mdp->num_rx_ring; i++) {
1376 mdp->rx_skbuff[i] = NULL;
1377 skb = netdev_alloc_skb(ndev, skbuff_size);
1380 sh_eth_set_receive_align(skb);
1382 /* The size of the buffer is a multiple of 32 bytes. */
1383 buf_len = ALIGN(mdp->rx_buf_sz, 32);
1384 dma_addr = dma_map_single(&mdp->pdev->dev, skb->data, buf_len,
1386 if (dma_mapping_error(&mdp->pdev->dev, dma_addr)) {
1390 mdp->rx_skbuff[i] = skb;
1393 rxdesc = &mdp->rx_ring[i];
1394 rxdesc->len = cpu_to_le32(buf_len << 16);
1395 rxdesc->addr = cpu_to_le32(dma_addr);
1396 rxdesc->status = cpu_to_le32(RD_RACT | RD_RFP);
1398 /* Rx descriptor address set */
1400 sh_eth_write(ndev, mdp->rx_desc_dma, RDLAR);
1401 if (mdp->cd->xdfar_rw)
1402 sh_eth_write(ndev, mdp->rx_desc_dma, RDFAR);
1406 mdp->dirty_rx = (u32) (i - mdp->num_rx_ring);
1408 /* Mark the last entry as wrapping the ring. */
1410 rxdesc->status |= cpu_to_le32(RD_RDLE);
1412 memset(mdp->tx_ring, 0, tx_ringsize);
1414 /* build Tx ring buffer */
1415 for (i = 0; i < mdp->num_tx_ring; i++) {
1416 mdp->tx_skbuff[i] = NULL;
1417 txdesc = &mdp->tx_ring[i];
1418 txdesc->status = cpu_to_le32(TD_TFP);
1419 txdesc->len = cpu_to_le32(0);
1421 /* Tx descriptor address set */
1422 sh_eth_write(ndev, mdp->tx_desc_dma, TDLAR);
1423 if (mdp->cd->xdfar_rw)
1424 sh_eth_write(ndev, mdp->tx_desc_dma, TDFAR);
1428 txdesc->status |= cpu_to_le32(TD_TDLE);
1431 /* Get skb and descriptor buffer */
1432 static int sh_eth_ring_init(struct net_device *ndev)
1434 struct sh_eth_private *mdp = netdev_priv(ndev);
1435 int rx_ringsize, tx_ringsize;
1437 /* +26 gets the maximum ethernet encapsulation, +7 & ~7 because the
1438 * card needs room to do 8 byte alignment, +2 so we can reserve
1439 * the first 2 bytes, and +16 gets room for the status word from the
1442 mdp->rx_buf_sz = (ndev->mtu <= 1492 ? PKT_BUF_SZ :
1443 (((ndev->mtu + 26 + 7) & ~7) + 2 + 16));
1444 if (mdp->cd->rpadir)
1445 mdp->rx_buf_sz += NET_IP_ALIGN;
1447 /* Allocate RX and TX skb rings */
1448 mdp->rx_skbuff = kcalloc(mdp->num_rx_ring, sizeof(*mdp->rx_skbuff),
1450 if (!mdp->rx_skbuff)
1453 mdp->tx_skbuff = kcalloc(mdp->num_tx_ring, sizeof(*mdp->tx_skbuff),
1455 if (!mdp->tx_skbuff)
1458 /* Allocate all Rx descriptors. */
1459 rx_ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
1460 mdp->rx_ring = dma_alloc_coherent(&mdp->pdev->dev, rx_ringsize,
1461 &mdp->rx_desc_dma, GFP_KERNEL);
1467 /* Allocate all Tx descriptors. */
1468 tx_ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
1469 mdp->tx_ring = dma_alloc_coherent(&mdp->pdev->dev, tx_ringsize,
1470 &mdp->tx_desc_dma, GFP_KERNEL);
1476 /* Free Rx and Tx skb ring buffer and DMA buffer */
1477 sh_eth_ring_free(ndev);
1482 static int sh_eth_dev_init(struct net_device *ndev)
1484 struct sh_eth_private *mdp = netdev_priv(ndev);
1488 ret = mdp->cd->soft_reset(ndev);
1492 if (mdp->cd->rmiimode)
1493 sh_eth_write(ndev, 0x1, RMIIMODE);
1495 /* Descriptor format */
1496 sh_eth_ring_format(ndev);
1497 if (mdp->cd->rpadir)
1498 sh_eth_write(ndev, NET_IP_ALIGN << 16, RPADIR);
1500 /* all sh_eth int mask */
1501 sh_eth_write(ndev, 0, EESIPR);
1503 #if defined(__LITTLE_ENDIAN)
1504 if (mdp->cd->hw_swap)
1505 sh_eth_write(ndev, EDMR_EL, EDMR);
1508 sh_eth_write(ndev, 0, EDMR);
1511 sh_eth_write(ndev, mdp->cd->fdr_value, FDR);
1512 sh_eth_write(ndev, 0, TFTR);
1514 /* Frame recv control (enable multiple-packets per rx irq) */
1515 sh_eth_write(ndev, RMCR_RNC, RMCR);
1517 sh_eth_write(ndev, mdp->cd->trscer_err_mask, TRSCER);
1519 /* DMA transfer burst mode */
1521 sh_eth_modify(ndev, EDMR, EDMR_NBST, EDMR_NBST);
1523 /* Burst cycle count upper-limit */
1525 sh_eth_write(ndev, 0x800, BCULR);
1527 sh_eth_write(ndev, mdp->cd->fcftr_value, FCFTR);
1529 if (!mdp->cd->no_trimd)
1530 sh_eth_write(ndev, 0, TRIMD);
1532 /* Recv frame limit set register */
1533 sh_eth_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN,
1536 sh_eth_modify(ndev, EESR, 0, 0);
1537 mdp->irq_enabled = true;
1538 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
1540 /* EMAC Mode: PAUSE prohibition; Duplex; RX Checksum; TX; RX */
1541 sh_eth_write(ndev, ECMR_ZPF | (mdp->duplex ? ECMR_DM : 0) |
1542 (ndev->features & NETIF_F_RXCSUM ? ECMR_RCSC : 0) |
1543 ECMR_TE | ECMR_RE, ECMR);
1545 if (mdp->cd->set_rate)
1546 mdp->cd->set_rate(ndev);
1548 /* E-MAC Status Register clear */
1549 sh_eth_write(ndev, mdp->cd->ecsr_value, ECSR);
1551 /* E-MAC Interrupt Enable register */
1552 sh_eth_write(ndev, mdp->cd->ecsipr_value, ECSIPR);
1554 /* Set MAC address */
1555 update_mac_address(ndev);
1559 sh_eth_write(ndev, 1, APR);
1561 sh_eth_write(ndev, 1, MPR);
1562 if (mdp->cd->tpauser)
1563 sh_eth_write(ndev, TPAUSER_UNLIMITED, TPAUSER);
1565 /* Setting the Rx mode will start the Rx process. */
1566 sh_eth_write(ndev, EDRRR_R, EDRRR);
1571 static void sh_eth_dev_exit(struct net_device *ndev)
1573 struct sh_eth_private *mdp = netdev_priv(ndev);
1576 /* Deactivate all TX descriptors, so DMA should stop at next
1577 * packet boundary if it's currently running
1579 for (i = 0; i < mdp->num_tx_ring; i++)
1580 mdp->tx_ring[i].status &= ~cpu_to_le32(TD_TACT);
1582 /* Disable TX FIFO egress to MAC */
1583 sh_eth_rcv_snd_disable(ndev);
1585 /* Stop RX DMA at next packet boundary */
1586 sh_eth_write(ndev, 0, EDRRR);
1588 /* Aside from TX DMA, we can't tell when the hardware is
1589 * really stopped, so we need to reset to make sure.
1590 * Before doing that, wait for long enough to *probably*
1591 * finish transmitting the last packet and poll stats.
1593 msleep(2); /* max frame time at 10 Mbps < 1250 us */
1594 sh_eth_get_stats(ndev);
1595 mdp->cd->soft_reset(ndev);
1597 /* Set MAC address again */
1598 update_mac_address(ndev);
1601 static void sh_eth_rx_csum(struct sk_buff *skb)
1605 /* The hardware checksum is 2 bytes appended to packet data */
1606 if (unlikely(skb->len < sizeof(__sum16)))
1608 hw_csum = skb_tail_pointer(skb) - sizeof(__sum16);
1609 skb->csum = csum_unfold((__force __sum16)get_unaligned_le16(hw_csum));
1610 skb->ip_summed = CHECKSUM_COMPLETE;
1611 skb_trim(skb, skb->len - sizeof(__sum16));
1614 /* Packet receive function */
1615 static int sh_eth_rx(struct net_device *ndev, u32 intr_status, int *quota)
1617 struct sh_eth_private *mdp = netdev_priv(ndev);
1618 struct sh_eth_rxdesc *rxdesc;
1620 int entry = mdp->cur_rx % mdp->num_rx_ring;
1621 int boguscnt = (mdp->dirty_rx + mdp->num_rx_ring) - mdp->cur_rx;
1623 struct sk_buff *skb;
1625 int skbuff_size = mdp->rx_buf_sz + SH_ETH_RX_ALIGN + 32 - 1;
1626 dma_addr_t dma_addr;
1630 boguscnt = min(boguscnt, *quota);
1632 rxdesc = &mdp->rx_ring[entry];
1633 while (!(rxdesc->status & cpu_to_le32(RD_RACT))) {
1634 /* RACT bit must be checked before all the following reads */
1636 desc_status = le32_to_cpu(rxdesc->status);
1637 pkt_len = le32_to_cpu(rxdesc->len) & RD_RFL;
1642 netif_info(mdp, rx_status, ndev,
1643 "rx entry %d status 0x%08x len %d\n",
1644 entry, desc_status, pkt_len);
1646 if (!(desc_status & RDFEND))
1647 ndev->stats.rx_length_errors++;
1649 /* In case of almost all GETHER/ETHERs, the Receive Frame State
1650 * (RFS) bits in the Receive Descriptor 0 are from bit 9 to
1651 * bit 0. However, in case of the R8A7740 and R7S72100
1652 * the RFS bits are from bit 25 to bit 16. So, the
1653 * driver needs right shifting by 16.
1658 skb = mdp->rx_skbuff[entry];
1659 if (desc_status & (RD_RFS1 | RD_RFS2 | RD_RFS3 | RD_RFS4 |
1660 RD_RFS5 | RD_RFS6 | RD_RFS10)) {
1661 ndev->stats.rx_errors++;
1662 if (desc_status & RD_RFS1)
1663 ndev->stats.rx_crc_errors++;
1664 if (desc_status & RD_RFS2)
1665 ndev->stats.rx_frame_errors++;
1666 if (desc_status & RD_RFS3)
1667 ndev->stats.rx_length_errors++;
1668 if (desc_status & RD_RFS4)
1669 ndev->stats.rx_length_errors++;
1670 if (desc_status & RD_RFS6)
1671 ndev->stats.rx_missed_errors++;
1672 if (desc_status & RD_RFS10)
1673 ndev->stats.rx_over_errors++;
1675 dma_addr = le32_to_cpu(rxdesc->addr);
1676 if (!mdp->cd->hw_swap)
1678 phys_to_virt(ALIGN(dma_addr, 4)),
1680 mdp->rx_skbuff[entry] = NULL;
1681 if (mdp->cd->rpadir)
1682 skb_reserve(skb, NET_IP_ALIGN);
1683 dma_unmap_single(&mdp->pdev->dev, dma_addr,
1684 ALIGN(mdp->rx_buf_sz, 32),
1686 skb_put(skb, pkt_len);
1687 skb->protocol = eth_type_trans(skb, ndev);
1688 if (ndev->features & NETIF_F_RXCSUM)
1689 sh_eth_rx_csum(skb);
1690 netif_receive_skb(skb);
1691 ndev->stats.rx_packets++;
1692 ndev->stats.rx_bytes += pkt_len;
1693 if (desc_status & RD_RFS8)
1694 ndev->stats.multicast++;
1696 entry = (++mdp->cur_rx) % mdp->num_rx_ring;
1697 rxdesc = &mdp->rx_ring[entry];
1700 /* Refill the Rx ring buffers. */
1701 for (; mdp->cur_rx - mdp->dirty_rx > 0; mdp->dirty_rx++) {
1702 entry = mdp->dirty_rx % mdp->num_rx_ring;
1703 rxdesc = &mdp->rx_ring[entry];
1704 /* The size of the buffer is 32 byte boundary. */
1705 buf_len = ALIGN(mdp->rx_buf_sz, 32);
1706 rxdesc->len = cpu_to_le32(buf_len << 16);
1708 if (mdp->rx_skbuff[entry] == NULL) {
1709 skb = netdev_alloc_skb(ndev, skbuff_size);
1711 break; /* Better luck next round. */
1712 sh_eth_set_receive_align(skb);
1713 dma_addr = dma_map_single(&mdp->pdev->dev, skb->data,
1714 buf_len, DMA_FROM_DEVICE);
1715 if (dma_mapping_error(&mdp->pdev->dev, dma_addr)) {
1719 mdp->rx_skbuff[entry] = skb;
1721 skb_checksum_none_assert(skb);
1722 rxdesc->addr = cpu_to_le32(dma_addr);
1724 dma_wmb(); /* RACT bit must be set after all the above writes */
1725 if (entry >= mdp->num_rx_ring - 1)
1727 cpu_to_le32(RD_RACT | RD_RFP | RD_RDLE);
1729 rxdesc->status |= cpu_to_le32(RD_RACT | RD_RFP);
1732 /* Restart Rx engine if stopped. */
1733 /* If we don't need to check status, don't. -KDU */
1734 if (!(sh_eth_read(ndev, EDRRR) & EDRRR_R)) {
1735 /* fix the values for the next receiving if RDE is set */
1736 if (intr_status & EESR_RDE && !mdp->cd->no_xdfar) {
1737 u32 count = (sh_eth_read(ndev, RDFAR) -
1738 sh_eth_read(ndev, RDLAR)) >> 4;
1740 mdp->cur_rx = count;
1741 mdp->dirty_rx = count;
1743 sh_eth_write(ndev, EDRRR_R, EDRRR);
1746 *quota -= limit - boguscnt - 1;
1751 static void sh_eth_rcv_snd_disable(struct net_device *ndev)
1753 /* disable tx and rx */
1754 sh_eth_modify(ndev, ECMR, ECMR_RE | ECMR_TE, 0);
1757 static void sh_eth_rcv_snd_enable(struct net_device *ndev)
1759 /* enable tx and rx */
1760 sh_eth_modify(ndev, ECMR, ECMR_RE | ECMR_TE, ECMR_RE | ECMR_TE);
1763 /* E-MAC interrupt handler */
1764 static void sh_eth_emac_interrupt(struct net_device *ndev)
1766 struct sh_eth_private *mdp = netdev_priv(ndev);
1770 felic_stat = sh_eth_read(ndev, ECSR) & sh_eth_read(ndev, ECSIPR);
1771 sh_eth_write(ndev, felic_stat, ECSR); /* clear int */
1772 if (felic_stat & ECSR_ICD)
1773 ndev->stats.tx_carrier_errors++;
1774 if (felic_stat & ECSR_MPD)
1775 pm_wakeup_event(&mdp->pdev->dev, 0);
1776 if (felic_stat & ECSR_LCHNG) {
1778 if (mdp->cd->no_psr || mdp->no_ether_link)
1780 link_stat = sh_eth_read(ndev, PSR);
1781 if (mdp->ether_link_active_low)
1782 link_stat = ~link_stat;
1783 if (!(link_stat & PHY_ST_LINK)) {
1784 sh_eth_rcv_snd_disable(ndev);
1787 sh_eth_modify(ndev, EESIPR, EESIPR_ECIIP, 0);
1789 sh_eth_modify(ndev, ECSR, 0, 0);
1790 sh_eth_modify(ndev, EESIPR, EESIPR_ECIIP, EESIPR_ECIIP);
1791 /* enable tx and rx */
1792 sh_eth_rcv_snd_enable(ndev);
1797 /* error control function */
1798 static void sh_eth_error(struct net_device *ndev, u32 intr_status)
1800 struct sh_eth_private *mdp = netdev_priv(ndev);
1803 if (intr_status & EESR_TWB) {
1804 /* Unused write back interrupt */
1805 if (intr_status & EESR_TABT) { /* Transmit Abort int */
1806 ndev->stats.tx_aborted_errors++;
1807 netif_err(mdp, tx_err, ndev, "Transmit Abort\n");
1811 if (intr_status & EESR_RABT) {
1812 /* Receive Abort int */
1813 if (intr_status & EESR_RFRMER) {
1814 /* Receive Frame Overflow int */
1815 ndev->stats.rx_frame_errors++;
1819 if (intr_status & EESR_TDE) {
1820 /* Transmit Descriptor Empty int */
1821 ndev->stats.tx_fifo_errors++;
1822 netif_err(mdp, tx_err, ndev, "Transmit Descriptor Empty\n");
1825 if (intr_status & EESR_TFE) {
1826 /* FIFO under flow */
1827 ndev->stats.tx_fifo_errors++;
1828 netif_err(mdp, tx_err, ndev, "Transmit FIFO Under flow\n");
1831 if (intr_status & EESR_RDE) {
1832 /* Receive Descriptor Empty int */
1833 ndev->stats.rx_over_errors++;
1836 if (intr_status & EESR_RFE) {
1837 /* Receive FIFO Overflow int */
1838 ndev->stats.rx_fifo_errors++;
1841 if (!mdp->cd->no_ade && (intr_status & EESR_ADE)) {
1843 ndev->stats.tx_fifo_errors++;
1844 netif_err(mdp, tx_err, ndev, "Address Error\n");
1847 mask = EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE;
1848 if (mdp->cd->no_ade)
1850 if (intr_status & mask) {
1852 u32 edtrr = sh_eth_read(ndev, EDTRR);
1855 netdev_err(ndev, "TX error. status=%8.8x cur_tx=%8.8x dirty_tx=%8.8x state=%8.8x EDTRR=%8.8x.\n",
1856 intr_status, mdp->cur_tx, mdp->dirty_tx,
1857 (u32)ndev->state, edtrr);
1858 /* dirty buffer free */
1859 sh_eth_tx_free(ndev, true);
1862 if (edtrr ^ mdp->cd->edtrr_trns) {
1864 sh_eth_write(ndev, mdp->cd->edtrr_trns, EDTRR);
1867 netif_wake_queue(ndev);
1871 static irqreturn_t sh_eth_interrupt(int irq, void *netdev)
1873 struct net_device *ndev = netdev;
1874 struct sh_eth_private *mdp = netdev_priv(ndev);
1875 struct sh_eth_cpu_data *cd = mdp->cd;
1876 irqreturn_t ret = IRQ_NONE;
1877 u32 intr_status, intr_enable;
1879 spin_lock(&mdp->lock);
1881 /* Get interrupt status */
1882 intr_status = sh_eth_read(ndev, EESR);
1883 /* Mask it with the interrupt mask, forcing ECI interrupt to be always
1884 * enabled since it's the one that comes thru regardless of the mask,
1885 * and we need to fully handle it in sh_eth_emac_interrupt() in order
1886 * to quench it as it doesn't get cleared by just writing 1 to the ECI
1889 intr_enable = sh_eth_read(ndev, EESIPR);
1890 intr_status &= intr_enable | EESIPR_ECIIP;
1891 if (intr_status & (EESR_RX_CHECK | cd->tx_check | EESR_ECI |
1892 cd->eesr_err_check))
1897 if (unlikely(!mdp->irq_enabled)) {
1898 sh_eth_write(ndev, 0, EESIPR);
1902 if (intr_status & EESR_RX_CHECK) {
1903 if (napi_schedule_prep(&mdp->napi)) {
1904 /* Mask Rx interrupts */
1905 sh_eth_write(ndev, intr_enable & ~EESR_RX_CHECK,
1907 __napi_schedule(&mdp->napi);
1910 "ignoring interrupt, status 0x%08x, mask 0x%08x.\n",
1911 intr_status, intr_enable);
1916 if (intr_status & cd->tx_check) {
1917 /* Clear Tx interrupts */
1918 sh_eth_write(ndev, intr_status & cd->tx_check, EESR);
1920 sh_eth_tx_free(ndev, true);
1921 netif_wake_queue(ndev);
1924 /* E-MAC interrupt */
1925 if (intr_status & EESR_ECI)
1926 sh_eth_emac_interrupt(ndev);
1928 if (intr_status & cd->eesr_err_check) {
1929 /* Clear error interrupts */
1930 sh_eth_write(ndev, intr_status & cd->eesr_err_check, EESR);
1932 sh_eth_error(ndev, intr_status);
1936 spin_unlock(&mdp->lock);
1941 static int sh_eth_poll(struct napi_struct *napi, int budget)
1943 struct sh_eth_private *mdp = container_of(napi, struct sh_eth_private,
1945 struct net_device *ndev = napi->dev;
1950 intr_status = sh_eth_read(ndev, EESR);
1951 if (!(intr_status & EESR_RX_CHECK))
1953 /* Clear Rx interrupts */
1954 sh_eth_write(ndev, intr_status & EESR_RX_CHECK, EESR);
1956 if (sh_eth_rx(ndev, intr_status, "a))
1960 napi_complete(napi);
1962 /* Reenable Rx interrupts */
1963 if (mdp->irq_enabled)
1964 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
1966 return budget - quota;
1969 /* PHY state control function */
1970 static void sh_eth_adjust_link(struct net_device *ndev)
1972 struct sh_eth_private *mdp = netdev_priv(ndev);
1973 struct phy_device *phydev = ndev->phydev;
1974 unsigned long flags;
1977 spin_lock_irqsave(&mdp->lock, flags);
1979 /* Disable TX and RX right over here, if E-MAC change is ignored */
1980 if (mdp->cd->no_psr || mdp->no_ether_link)
1981 sh_eth_rcv_snd_disable(ndev);
1984 if (phydev->duplex != mdp->duplex) {
1986 mdp->duplex = phydev->duplex;
1987 if (mdp->cd->set_duplex)
1988 mdp->cd->set_duplex(ndev);
1991 if (phydev->speed != mdp->speed) {
1993 mdp->speed = phydev->speed;
1994 if (mdp->cd->set_rate)
1995 mdp->cd->set_rate(ndev);
1998 sh_eth_modify(ndev, ECMR, ECMR_TXF, 0);
2000 mdp->link = phydev->link;
2002 } else if (mdp->link) {
2009 /* Enable TX and RX right over here, if E-MAC change is ignored */
2010 if ((mdp->cd->no_psr || mdp->no_ether_link) && phydev->link)
2011 sh_eth_rcv_snd_enable(ndev);
2014 spin_unlock_irqrestore(&mdp->lock, flags);
2016 if (new_state && netif_msg_link(mdp))
2017 phy_print_status(phydev);
2020 /* PHY init function */
2021 static int sh_eth_phy_init(struct net_device *ndev)
2023 struct device_node *np = ndev->dev.parent->of_node;
2024 struct sh_eth_private *mdp = netdev_priv(ndev);
2025 struct phy_device *phydev;
2031 /* Try connect to PHY */
2033 struct device_node *pn;
2035 pn = of_parse_phandle(np, "phy-handle", 0);
2036 phydev = of_phy_connect(ndev, pn,
2037 sh_eth_adjust_link, 0,
2038 mdp->phy_interface);
2042 phydev = ERR_PTR(-ENOENT);
2044 char phy_id[MII_BUS_ID_SIZE + 3];
2046 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
2047 mdp->mii_bus->id, mdp->phy_id);
2049 phydev = phy_connect(ndev, phy_id, sh_eth_adjust_link,
2050 mdp->phy_interface);
2053 if (IS_ERR(phydev)) {
2054 netdev_err(ndev, "failed to connect PHY\n");
2055 return PTR_ERR(phydev);
2058 /* mask with MAC supported features */
2059 if (mdp->cd->register_type != SH_ETH_REG_GIGABIT) {
2060 int err = phy_set_max_speed(phydev, SPEED_100);
2062 netdev_err(ndev, "failed to limit PHY to 100 Mbit/s\n");
2063 phy_disconnect(phydev);
2068 phy_attached_info(phydev);
2073 /* PHY control start function */
2074 static int sh_eth_phy_start(struct net_device *ndev)
2078 ret = sh_eth_phy_init(ndev);
2082 phy_start(ndev->phydev);
2087 /* If it is ever necessary to increase SH_ETH_REG_DUMP_MAX_REGS, the
2088 * version must be bumped as well. Just adding registers up to that
2089 * limit is fine, as long as the existing register indices don't
2092 #define SH_ETH_REG_DUMP_VERSION 1
2093 #define SH_ETH_REG_DUMP_MAX_REGS 256
2095 static size_t __sh_eth_get_regs(struct net_device *ndev, u32 *buf)
2097 struct sh_eth_private *mdp = netdev_priv(ndev);
2098 struct sh_eth_cpu_data *cd = mdp->cd;
2102 BUILD_BUG_ON(SH_ETH_MAX_REGISTER_OFFSET > SH_ETH_REG_DUMP_MAX_REGS);
2104 /* Dump starts with a bitmap that tells ethtool which
2105 * registers are defined for this chip.
2107 len = DIV_ROUND_UP(SH_ETH_REG_DUMP_MAX_REGS, 32);
2115 /* Add a register to the dump, if it has a defined offset.
2116 * This automatically skips most undefined registers, but for
2117 * some it is also necessary to check a capability flag in
2118 * struct sh_eth_cpu_data.
2120 #define mark_reg_valid(reg) valid_map[reg / 32] |= 1U << (reg % 32)
2121 #define add_reg_from(reg, read_expr) do { \
2122 if (mdp->reg_offset[reg] != SH_ETH_OFFSET_INVALID) { \
2124 mark_reg_valid(reg); \
2125 *buf++ = read_expr; \
2130 #define add_reg(reg) add_reg_from(reg, sh_eth_read(ndev, reg))
2131 #define add_tsu_reg(reg) add_reg_from(reg, sh_eth_tsu_read(mdp, reg))
2203 add_tsu_reg(TSU_CTRST);
2204 add_tsu_reg(TSU_FWEN0);
2205 add_tsu_reg(TSU_FWEN1);
2206 add_tsu_reg(TSU_FCM);
2207 add_tsu_reg(TSU_BSYSL0);
2208 add_tsu_reg(TSU_BSYSL1);
2209 add_tsu_reg(TSU_PRISL0);
2210 add_tsu_reg(TSU_PRISL1);
2211 add_tsu_reg(TSU_FWSL0);
2212 add_tsu_reg(TSU_FWSL1);
2213 add_tsu_reg(TSU_FWSLC);
2214 add_tsu_reg(TSU_QTAGM0);
2215 add_tsu_reg(TSU_QTAGM1);
2216 add_tsu_reg(TSU_FWSR);
2217 add_tsu_reg(TSU_FWINMK);
2218 add_tsu_reg(TSU_ADQT0);
2219 add_tsu_reg(TSU_ADQT1);
2220 add_tsu_reg(TSU_VTAG0);
2221 add_tsu_reg(TSU_VTAG1);
2222 add_tsu_reg(TSU_ADSBSY);
2223 add_tsu_reg(TSU_TEN);
2224 add_tsu_reg(TSU_POST1);
2225 add_tsu_reg(TSU_POST2);
2226 add_tsu_reg(TSU_POST3);
2227 add_tsu_reg(TSU_POST4);
2228 /* This is the start of a table, not just a single register. */
2232 mark_reg_valid(TSU_ADRH0);
2233 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES * 2; i++)
2234 *buf++ = ioread32(mdp->tsu_addr +
2235 mdp->reg_offset[TSU_ADRH0] +
2238 len += SH_ETH_TSU_CAM_ENTRIES * 2;
2241 #undef mark_reg_valid
2249 static int sh_eth_get_regs_len(struct net_device *ndev)
2251 return __sh_eth_get_regs(ndev, NULL);
2254 static void sh_eth_get_regs(struct net_device *ndev, struct ethtool_regs *regs,
2257 struct sh_eth_private *mdp = netdev_priv(ndev);
2259 regs->version = SH_ETH_REG_DUMP_VERSION;
2261 pm_runtime_get_sync(&mdp->pdev->dev);
2262 __sh_eth_get_regs(ndev, buf);
2263 pm_runtime_put_sync(&mdp->pdev->dev);
2266 static u32 sh_eth_get_msglevel(struct net_device *ndev)
2268 struct sh_eth_private *mdp = netdev_priv(ndev);
2269 return mdp->msg_enable;
2272 static void sh_eth_set_msglevel(struct net_device *ndev, u32 value)
2274 struct sh_eth_private *mdp = netdev_priv(ndev);
2275 mdp->msg_enable = value;
2278 static const char sh_eth_gstrings_stats[][ETH_GSTRING_LEN] = {
2279 "rx_current", "tx_current",
2280 "rx_dirty", "tx_dirty",
2282 #define SH_ETH_STATS_LEN ARRAY_SIZE(sh_eth_gstrings_stats)
2284 static int sh_eth_get_sset_count(struct net_device *netdev, int sset)
2288 return SH_ETH_STATS_LEN;
2294 static void sh_eth_get_ethtool_stats(struct net_device *ndev,
2295 struct ethtool_stats *stats, u64 *data)
2297 struct sh_eth_private *mdp = netdev_priv(ndev);
2300 /* device-specific stats */
2301 data[i++] = mdp->cur_rx;
2302 data[i++] = mdp->cur_tx;
2303 data[i++] = mdp->dirty_rx;
2304 data[i++] = mdp->dirty_tx;
2307 static void sh_eth_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
2309 switch (stringset) {
2311 memcpy(data, *sh_eth_gstrings_stats,
2312 sizeof(sh_eth_gstrings_stats));
2317 static void sh_eth_get_ringparam(struct net_device *ndev,
2318 struct ethtool_ringparam *ring)
2320 struct sh_eth_private *mdp = netdev_priv(ndev);
2322 ring->rx_max_pending = RX_RING_MAX;
2323 ring->tx_max_pending = TX_RING_MAX;
2324 ring->rx_pending = mdp->num_rx_ring;
2325 ring->tx_pending = mdp->num_tx_ring;
2328 static int sh_eth_set_ringparam(struct net_device *ndev,
2329 struct ethtool_ringparam *ring)
2331 struct sh_eth_private *mdp = netdev_priv(ndev);
2334 if (ring->tx_pending > TX_RING_MAX ||
2335 ring->rx_pending > RX_RING_MAX ||
2336 ring->tx_pending < TX_RING_MIN ||
2337 ring->rx_pending < RX_RING_MIN)
2339 if (ring->rx_mini_pending || ring->rx_jumbo_pending)
2342 if (netif_running(ndev)) {
2343 netif_device_detach(ndev);
2344 netif_tx_disable(ndev);
2346 /* Serialise with the interrupt handler and NAPI, then
2347 * disable interrupts. We have to clear the
2348 * irq_enabled flag first to ensure that interrupts
2349 * won't be re-enabled.
2351 mdp->irq_enabled = false;
2352 synchronize_irq(ndev->irq);
2353 napi_synchronize(&mdp->napi);
2354 sh_eth_write(ndev, 0x0000, EESIPR);
2356 sh_eth_dev_exit(ndev);
2358 /* Free all the skbuffs in the Rx queue and the DMA buffers. */
2359 sh_eth_ring_free(ndev);
2362 /* Set new parameters */
2363 mdp->num_rx_ring = ring->rx_pending;
2364 mdp->num_tx_ring = ring->tx_pending;
2366 if (netif_running(ndev)) {
2367 ret = sh_eth_ring_init(ndev);
2369 netdev_err(ndev, "%s: sh_eth_ring_init failed.\n",
2373 ret = sh_eth_dev_init(ndev);
2375 netdev_err(ndev, "%s: sh_eth_dev_init failed.\n",
2380 netif_device_attach(ndev);
2386 static void sh_eth_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
2388 struct sh_eth_private *mdp = netdev_priv(ndev);
2393 if (mdp->cd->magic) {
2394 wol->supported = WAKE_MAGIC;
2395 wol->wolopts = mdp->wol_enabled ? WAKE_MAGIC : 0;
2399 static int sh_eth_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
2401 struct sh_eth_private *mdp = netdev_priv(ndev);
2403 if (!mdp->cd->magic || wol->wolopts & ~WAKE_MAGIC)
2406 mdp->wol_enabled = !!(wol->wolopts & WAKE_MAGIC);
2408 device_set_wakeup_enable(&mdp->pdev->dev, mdp->wol_enabled);
2413 static const struct ethtool_ops sh_eth_ethtool_ops = {
2414 .get_regs_len = sh_eth_get_regs_len,
2415 .get_regs = sh_eth_get_regs,
2416 .nway_reset = phy_ethtool_nway_reset,
2417 .get_msglevel = sh_eth_get_msglevel,
2418 .set_msglevel = sh_eth_set_msglevel,
2419 .get_link = ethtool_op_get_link,
2420 .get_strings = sh_eth_get_strings,
2421 .get_ethtool_stats = sh_eth_get_ethtool_stats,
2422 .get_sset_count = sh_eth_get_sset_count,
2423 .get_ringparam = sh_eth_get_ringparam,
2424 .set_ringparam = sh_eth_set_ringparam,
2425 .get_link_ksettings = phy_ethtool_get_link_ksettings,
2426 .set_link_ksettings = phy_ethtool_set_link_ksettings,
2427 .get_wol = sh_eth_get_wol,
2428 .set_wol = sh_eth_set_wol,
2431 /* network device open function */
2432 static int sh_eth_open(struct net_device *ndev)
2434 struct sh_eth_private *mdp = netdev_priv(ndev);
2437 pm_runtime_get_sync(&mdp->pdev->dev);
2439 napi_enable(&mdp->napi);
2441 ret = request_irq(ndev->irq, sh_eth_interrupt,
2442 mdp->cd->irq_flags, ndev->name, ndev);
2444 netdev_err(ndev, "Can not assign IRQ number\n");
2448 /* Descriptor set */
2449 ret = sh_eth_ring_init(ndev);
2454 ret = sh_eth_dev_init(ndev);
2458 /* PHY control start*/
2459 ret = sh_eth_phy_start(ndev);
2463 netif_start_queue(ndev);
2470 free_irq(ndev->irq, ndev);
2472 napi_disable(&mdp->napi);
2473 pm_runtime_put_sync(&mdp->pdev->dev);
2477 /* Timeout function */
2478 static void sh_eth_tx_timeout(struct net_device *ndev)
2480 struct sh_eth_private *mdp = netdev_priv(ndev);
2481 struct sh_eth_rxdesc *rxdesc;
2484 netif_stop_queue(ndev);
2486 netif_err(mdp, timer, ndev,
2487 "transmit timed out, status %8.8x, resetting...\n",
2488 sh_eth_read(ndev, EESR));
2490 /* tx_errors count up */
2491 ndev->stats.tx_errors++;
2493 /* Free all the skbuffs in the Rx queue. */
2494 for (i = 0; i < mdp->num_rx_ring; i++) {
2495 rxdesc = &mdp->rx_ring[i];
2496 rxdesc->status = cpu_to_le32(0);
2497 rxdesc->addr = cpu_to_le32(0xBADF00D0);
2498 dev_kfree_skb(mdp->rx_skbuff[i]);
2499 mdp->rx_skbuff[i] = NULL;
2501 for (i = 0; i < mdp->num_tx_ring; i++) {
2502 dev_kfree_skb(mdp->tx_skbuff[i]);
2503 mdp->tx_skbuff[i] = NULL;
2507 sh_eth_dev_init(ndev);
2509 netif_start_queue(ndev);
2512 /* Packet transmit function */
2513 static int sh_eth_start_xmit(struct sk_buff *skb, struct net_device *ndev)
2515 struct sh_eth_private *mdp = netdev_priv(ndev);
2516 struct sh_eth_txdesc *txdesc;
2517 dma_addr_t dma_addr;
2519 unsigned long flags;
2521 spin_lock_irqsave(&mdp->lock, flags);
2522 if ((mdp->cur_tx - mdp->dirty_tx) >= (mdp->num_tx_ring - 4)) {
2523 if (!sh_eth_tx_free(ndev, true)) {
2524 netif_warn(mdp, tx_queued, ndev, "TxFD exhausted.\n");
2525 netif_stop_queue(ndev);
2526 spin_unlock_irqrestore(&mdp->lock, flags);
2527 return NETDEV_TX_BUSY;
2530 spin_unlock_irqrestore(&mdp->lock, flags);
2532 if (skb_put_padto(skb, ETH_ZLEN))
2533 return NETDEV_TX_OK;
2535 entry = mdp->cur_tx % mdp->num_tx_ring;
2536 mdp->tx_skbuff[entry] = skb;
2537 txdesc = &mdp->tx_ring[entry];
2539 if (!mdp->cd->hw_swap)
2540 sh_eth_soft_swap(PTR_ALIGN(skb->data, 4), skb->len + 2);
2541 dma_addr = dma_map_single(&mdp->pdev->dev, skb->data, skb->len,
2543 if (dma_mapping_error(&mdp->pdev->dev, dma_addr)) {
2545 return NETDEV_TX_OK;
2547 txdesc->addr = cpu_to_le32(dma_addr);
2548 txdesc->len = cpu_to_le32(skb->len << 16);
2550 dma_wmb(); /* TACT bit must be set after all the above writes */
2551 if (entry >= mdp->num_tx_ring - 1)
2552 txdesc->status |= cpu_to_le32(TD_TACT | TD_TDLE);
2554 txdesc->status |= cpu_to_le32(TD_TACT);
2558 if (!(sh_eth_read(ndev, EDTRR) & mdp->cd->edtrr_trns))
2559 sh_eth_write(ndev, mdp->cd->edtrr_trns, EDTRR);
2561 return NETDEV_TX_OK;
2564 /* The statistics registers have write-clear behaviour, which means we
2565 * will lose any increment between the read and write. We mitigate
2566 * this by only clearing when we read a non-zero value, so we will
2567 * never falsely report a total of zero.
2570 sh_eth_update_stat(struct net_device *ndev, unsigned long *stat, int reg)
2572 u32 delta = sh_eth_read(ndev, reg);
2576 sh_eth_write(ndev, 0, reg);
2580 static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev)
2582 struct sh_eth_private *mdp = netdev_priv(ndev);
2584 if (mdp->cd->no_tx_cntrs)
2585 return &ndev->stats;
2587 if (!mdp->is_opened)
2588 return &ndev->stats;
2590 sh_eth_update_stat(ndev, &ndev->stats.tx_dropped, TROCR);
2591 sh_eth_update_stat(ndev, &ndev->stats.collisions, CDCR);
2592 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors, LCCR);
2594 if (mdp->cd->cexcr) {
2595 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,
2597 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,
2600 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,
2604 return &ndev->stats;
2607 /* device close function */
2608 static int sh_eth_close(struct net_device *ndev)
2610 struct sh_eth_private *mdp = netdev_priv(ndev);
2612 netif_stop_queue(ndev);
2614 /* Serialise with the interrupt handler and NAPI, then disable
2615 * interrupts. We have to clear the irq_enabled flag first to
2616 * ensure that interrupts won't be re-enabled.
2618 mdp->irq_enabled = false;
2619 synchronize_irq(ndev->irq);
2620 napi_disable(&mdp->napi);
2621 sh_eth_write(ndev, 0x0000, EESIPR);
2623 sh_eth_dev_exit(ndev);
2625 /* PHY Disconnect */
2627 phy_stop(ndev->phydev);
2628 phy_disconnect(ndev->phydev);
2631 free_irq(ndev->irq, ndev);
2633 /* Free all the skbuffs in the Rx queue and the DMA buffer. */
2634 sh_eth_ring_free(ndev);
2636 pm_runtime_put_sync(&mdp->pdev->dev);
2643 /* ioctl to device function */
2644 static int sh_eth_do_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
2646 struct phy_device *phydev = ndev->phydev;
2648 if (!netif_running(ndev))
2654 return phy_mii_ioctl(phydev, rq, cmd);
2657 static int sh_eth_change_mtu(struct net_device *ndev, int new_mtu)
2659 if (netif_running(ndev))
2662 ndev->mtu = new_mtu;
2663 netdev_update_features(ndev);
2668 /* For TSU_POSTn. Please refer to the manual about this (strange) bitfields */
2669 static u32 sh_eth_tsu_get_post_mask(int entry)
2671 return 0x0f << (28 - ((entry % 8) * 4));
2674 static u32 sh_eth_tsu_get_post_bit(struct sh_eth_private *mdp, int entry)
2676 return (0x08 >> (mdp->port << 1)) << (28 - ((entry % 8) * 4));
2679 static void sh_eth_tsu_enable_cam_entry_post(struct net_device *ndev,
2682 struct sh_eth_private *mdp = netdev_priv(ndev);
2683 int reg = TSU_POST1 + entry / 8;
2686 tmp = sh_eth_tsu_read(mdp, reg);
2687 sh_eth_tsu_write(mdp, tmp | sh_eth_tsu_get_post_bit(mdp, entry), reg);
2690 static bool sh_eth_tsu_disable_cam_entry_post(struct net_device *ndev,
2693 struct sh_eth_private *mdp = netdev_priv(ndev);
2694 int reg = TSU_POST1 + entry / 8;
2695 u32 post_mask, ref_mask, tmp;
2697 post_mask = sh_eth_tsu_get_post_mask(entry);
2698 ref_mask = sh_eth_tsu_get_post_bit(mdp, entry) & ~post_mask;
2700 tmp = sh_eth_tsu_read(mdp, reg);
2701 sh_eth_tsu_write(mdp, tmp & ~post_mask, reg);
2703 /* If other port enables, the function returns "true" */
2704 return tmp & ref_mask;
2707 static int sh_eth_tsu_busy(struct net_device *ndev)
2709 int timeout = SH_ETH_TSU_TIMEOUT_MS * 100;
2710 struct sh_eth_private *mdp = netdev_priv(ndev);
2712 while ((sh_eth_tsu_read(mdp, TSU_ADSBSY) & TSU_ADSBSY_0)) {
2716 netdev_err(ndev, "%s: timeout\n", __func__);
2724 static int sh_eth_tsu_write_entry(struct net_device *ndev, u16 offset,
2727 struct sh_eth_private *mdp = netdev_priv(ndev);
2730 val = addr[0] << 24 | addr[1] << 16 | addr[2] << 8 | addr[3];
2731 iowrite32(val, mdp->tsu_addr + offset);
2732 if (sh_eth_tsu_busy(ndev) < 0)
2735 val = addr[4] << 8 | addr[5];
2736 iowrite32(val, mdp->tsu_addr + offset + 4);
2737 if (sh_eth_tsu_busy(ndev) < 0)
2743 static void sh_eth_tsu_read_entry(struct net_device *ndev, u16 offset, u8 *addr)
2745 struct sh_eth_private *mdp = netdev_priv(ndev);
2748 val = ioread32(mdp->tsu_addr + offset);
2749 addr[0] = (val >> 24) & 0xff;
2750 addr[1] = (val >> 16) & 0xff;
2751 addr[2] = (val >> 8) & 0xff;
2752 addr[3] = val & 0xff;
2753 val = ioread32(mdp->tsu_addr + offset + 4);
2754 addr[4] = (val >> 8) & 0xff;
2755 addr[5] = val & 0xff;
2759 static int sh_eth_tsu_find_entry(struct net_device *ndev, const u8 *addr)
2761 struct sh_eth_private *mdp = netdev_priv(ndev);
2762 u16 reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2764 u8 c_addr[ETH_ALEN];
2766 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2767 sh_eth_tsu_read_entry(ndev, reg_offset, c_addr);
2768 if (ether_addr_equal(addr, c_addr))
2775 static int sh_eth_tsu_find_empty(struct net_device *ndev)
2780 memset(blank, 0, sizeof(blank));
2781 entry = sh_eth_tsu_find_entry(ndev, blank);
2782 return (entry < 0) ? -ENOMEM : entry;
2785 static int sh_eth_tsu_disable_cam_entry_table(struct net_device *ndev,
2788 struct sh_eth_private *mdp = netdev_priv(ndev);
2789 u16 reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2793 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) &
2794 ~(1 << (31 - entry)), TSU_TEN);
2796 memset(blank, 0, sizeof(blank));
2797 ret = sh_eth_tsu_write_entry(ndev, reg_offset + entry * 8, blank);
2803 static int sh_eth_tsu_add_entry(struct net_device *ndev, const u8 *addr)
2805 struct sh_eth_private *mdp = netdev_priv(ndev);
2806 u16 reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2812 i = sh_eth_tsu_find_entry(ndev, addr);
2814 /* No entry found, create one */
2815 i = sh_eth_tsu_find_empty(ndev);
2818 ret = sh_eth_tsu_write_entry(ndev, reg_offset + i * 8, addr);
2822 /* Enable the entry */
2823 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) |
2824 (1 << (31 - i)), TSU_TEN);
2827 /* Entry found or created, enable POST */
2828 sh_eth_tsu_enable_cam_entry_post(ndev, i);
2833 static int sh_eth_tsu_del_entry(struct net_device *ndev, const u8 *addr)
2835 struct sh_eth_private *mdp = netdev_priv(ndev);
2841 i = sh_eth_tsu_find_entry(ndev, addr);
2844 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2847 /* Disable the entry if both ports was disabled */
2848 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2856 static int sh_eth_tsu_purge_all(struct net_device *ndev)
2858 struct sh_eth_private *mdp = netdev_priv(ndev);
2864 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++) {
2865 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2868 /* Disable the entry if both ports was disabled */
2869 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2877 static void sh_eth_tsu_purge_mcast(struct net_device *ndev)
2879 struct sh_eth_private *mdp = netdev_priv(ndev);
2880 u16 reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2887 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2888 sh_eth_tsu_read_entry(ndev, reg_offset, addr);
2889 if (is_multicast_ether_addr(addr))
2890 sh_eth_tsu_del_entry(ndev, addr);
2894 /* Update promiscuous flag and multicast filter */
2895 static void sh_eth_set_rx_mode(struct net_device *ndev)
2897 struct sh_eth_private *mdp = netdev_priv(ndev);
2900 unsigned long flags;
2902 spin_lock_irqsave(&mdp->lock, flags);
2903 /* Initial condition is MCT = 1, PRM = 0.
2904 * Depending on ndev->flags, set PRM or clear MCT
2906 ecmr_bits = sh_eth_read(ndev, ECMR) & ~ECMR_PRM;
2908 ecmr_bits |= ECMR_MCT;
2910 if (!(ndev->flags & IFF_MULTICAST)) {
2911 sh_eth_tsu_purge_mcast(ndev);
2914 if (ndev->flags & IFF_ALLMULTI) {
2915 sh_eth_tsu_purge_mcast(ndev);
2916 ecmr_bits &= ~ECMR_MCT;
2920 if (ndev->flags & IFF_PROMISC) {
2921 sh_eth_tsu_purge_all(ndev);
2922 ecmr_bits = (ecmr_bits & ~ECMR_MCT) | ECMR_PRM;
2923 } else if (mdp->cd->tsu) {
2924 struct netdev_hw_addr *ha;
2925 netdev_for_each_mc_addr(ha, ndev) {
2926 if (mcast_all && is_multicast_ether_addr(ha->addr))
2929 if (sh_eth_tsu_add_entry(ndev, ha->addr) < 0) {
2931 sh_eth_tsu_purge_mcast(ndev);
2932 ecmr_bits &= ~ECMR_MCT;
2939 /* update the ethernet mode */
2940 sh_eth_write(ndev, ecmr_bits, ECMR);
2942 spin_unlock_irqrestore(&mdp->lock, flags);
2945 static void sh_eth_set_rx_csum(struct net_device *ndev, bool enable)
2947 struct sh_eth_private *mdp = netdev_priv(ndev);
2948 unsigned long flags;
2950 spin_lock_irqsave(&mdp->lock, flags);
2952 /* Disable TX and RX */
2953 sh_eth_rcv_snd_disable(ndev);
2955 /* Modify RX Checksum setting */
2956 sh_eth_modify(ndev, ECMR, ECMR_RCSC, enable ? ECMR_RCSC : 0);
2958 /* Enable TX and RX */
2959 sh_eth_rcv_snd_enable(ndev);
2961 spin_unlock_irqrestore(&mdp->lock, flags);
2964 static int sh_eth_set_features(struct net_device *ndev,
2965 netdev_features_t features)
2967 netdev_features_t changed = ndev->features ^ features;
2968 struct sh_eth_private *mdp = netdev_priv(ndev);
2970 if (changed & NETIF_F_RXCSUM && mdp->cd->rx_csum)
2971 sh_eth_set_rx_csum(ndev, features & NETIF_F_RXCSUM);
2973 ndev->features = features;
2978 static int sh_eth_get_vtag_index(struct sh_eth_private *mdp)
2986 static int sh_eth_vlan_rx_add_vid(struct net_device *ndev,
2987 __be16 proto, u16 vid)
2989 struct sh_eth_private *mdp = netdev_priv(ndev);
2990 int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2992 if (unlikely(!mdp->cd->tsu))
2995 /* No filtering if vid = 0 */
2999 mdp->vlan_num_ids++;
3001 /* The controller has one VLAN tag HW filter. So, if the filter is
3002 * already enabled, the driver disables it and the filte
3004 if (mdp->vlan_num_ids > 1) {
3005 /* disable VLAN filter */
3006 sh_eth_tsu_write(mdp, 0, vtag_reg_index);
3010 sh_eth_tsu_write(mdp, TSU_VTAG_ENABLE | (vid & TSU_VTAG_VID_MASK),
3016 static int sh_eth_vlan_rx_kill_vid(struct net_device *ndev,
3017 __be16 proto, u16 vid)
3019 struct sh_eth_private *mdp = netdev_priv(ndev);
3020 int vtag_reg_index = sh_eth_get_vtag_index(mdp);
3022 if (unlikely(!mdp->cd->tsu))
3025 /* No filtering if vid = 0 */
3029 mdp->vlan_num_ids--;
3030 sh_eth_tsu_write(mdp, 0, vtag_reg_index);
3035 /* SuperH's TSU register init function */
3036 static void sh_eth_tsu_init(struct sh_eth_private *mdp)
3038 if (!mdp->cd->dual_port) {
3039 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */
3040 sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL,
3041 TSU_FWSLC); /* Enable POST registers */
3045 sh_eth_tsu_write(mdp, 0, TSU_FWEN0); /* Disable forward(0->1) */
3046 sh_eth_tsu_write(mdp, 0, TSU_FWEN1); /* Disable forward(1->0) */
3047 sh_eth_tsu_write(mdp, 0, TSU_FCM); /* forward fifo 3k-3k */
3048 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL0);
3049 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL1);
3050 sh_eth_tsu_write(mdp, 0, TSU_PRISL0);
3051 sh_eth_tsu_write(mdp, 0, TSU_PRISL1);
3052 sh_eth_tsu_write(mdp, 0, TSU_FWSL0);
3053 sh_eth_tsu_write(mdp, 0, TSU_FWSL1);
3054 sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, TSU_FWSLC);
3055 sh_eth_tsu_write(mdp, 0, TSU_QTAGM0); /* Disable QTAG(0->1) */
3056 sh_eth_tsu_write(mdp, 0, TSU_QTAGM1); /* Disable QTAG(1->0) */
3057 sh_eth_tsu_write(mdp, 0, TSU_FWSR); /* all interrupt status clear */
3058 sh_eth_tsu_write(mdp, 0, TSU_FWINMK); /* Disable all interrupt */
3059 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */
3060 sh_eth_tsu_write(mdp, 0, TSU_POST1); /* Disable CAM entry [ 0- 7] */
3061 sh_eth_tsu_write(mdp, 0, TSU_POST2); /* Disable CAM entry [ 8-15] */
3062 sh_eth_tsu_write(mdp, 0, TSU_POST3); /* Disable CAM entry [16-23] */
3063 sh_eth_tsu_write(mdp, 0, TSU_POST4); /* Disable CAM entry [24-31] */
3066 /* MDIO bus release function */
3067 static int sh_mdio_release(struct sh_eth_private *mdp)
3069 /* unregister mdio bus */
3070 mdiobus_unregister(mdp->mii_bus);
3072 /* free bitbang info */
3073 free_mdio_bitbang(mdp->mii_bus);
3078 /* MDIO bus init function */
3079 static int sh_mdio_init(struct sh_eth_private *mdp,
3080 struct sh_eth_plat_data *pd)
3083 struct bb_info *bitbang;
3084 struct platform_device *pdev = mdp->pdev;
3085 struct device *dev = &mdp->pdev->dev;
3087 /* create bit control struct for PHY */
3088 bitbang = devm_kzalloc(dev, sizeof(struct bb_info), GFP_KERNEL);
3093 bitbang->addr = mdp->addr + mdp->reg_offset[PIR];
3094 bitbang->set_gate = pd->set_mdio_gate;
3095 bitbang->ctrl.ops = &bb_ops;
3097 /* MII controller setting */
3098 mdp->mii_bus = alloc_mdio_bitbang(&bitbang->ctrl);
3102 /* Hook up MII support for ethtool */
3103 mdp->mii_bus->name = "sh_mii";
3104 mdp->mii_bus->parent = dev;
3105 snprintf(mdp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
3106 pdev->name, pdev->id);
3108 /* register MDIO bus */
3109 if (pd->phy_irq > 0)
3110 mdp->mii_bus->irq[pd->phy] = pd->phy_irq;
3112 ret = of_mdiobus_register(mdp->mii_bus, dev->of_node);
3119 free_mdio_bitbang(mdp->mii_bus);
3123 static const u16 *sh_eth_get_register_offset(int register_type)
3125 const u16 *reg_offset = NULL;
3127 switch (register_type) {
3128 case SH_ETH_REG_GIGABIT:
3129 reg_offset = sh_eth_offset_gigabit;
3131 case SH_ETH_REG_FAST_RZ:
3132 reg_offset = sh_eth_offset_fast_rz;
3134 case SH_ETH_REG_FAST_RCAR:
3135 reg_offset = sh_eth_offset_fast_rcar;
3137 case SH_ETH_REG_FAST_SH4:
3138 reg_offset = sh_eth_offset_fast_sh4;
3140 case SH_ETH_REG_FAST_SH3_SH2:
3141 reg_offset = sh_eth_offset_fast_sh3_sh2;
3148 static const struct net_device_ops sh_eth_netdev_ops = {
3149 .ndo_open = sh_eth_open,
3150 .ndo_stop = sh_eth_close,
3151 .ndo_start_xmit = sh_eth_start_xmit,
3152 .ndo_get_stats = sh_eth_get_stats,
3153 .ndo_set_rx_mode = sh_eth_set_rx_mode,
3154 .ndo_tx_timeout = sh_eth_tx_timeout,
3155 .ndo_do_ioctl = sh_eth_do_ioctl,
3156 .ndo_change_mtu = sh_eth_change_mtu,
3157 .ndo_validate_addr = eth_validate_addr,
3158 .ndo_set_mac_address = eth_mac_addr,
3159 .ndo_set_features = sh_eth_set_features,
3162 static const struct net_device_ops sh_eth_netdev_ops_tsu = {
3163 .ndo_open = sh_eth_open,
3164 .ndo_stop = sh_eth_close,
3165 .ndo_start_xmit = sh_eth_start_xmit,
3166 .ndo_get_stats = sh_eth_get_stats,
3167 .ndo_set_rx_mode = sh_eth_set_rx_mode,
3168 .ndo_vlan_rx_add_vid = sh_eth_vlan_rx_add_vid,
3169 .ndo_vlan_rx_kill_vid = sh_eth_vlan_rx_kill_vid,
3170 .ndo_tx_timeout = sh_eth_tx_timeout,
3171 .ndo_do_ioctl = sh_eth_do_ioctl,
3172 .ndo_change_mtu = sh_eth_change_mtu,
3173 .ndo_validate_addr = eth_validate_addr,
3174 .ndo_set_mac_address = eth_mac_addr,
3175 .ndo_set_features = sh_eth_set_features,
3179 static struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev)
3181 struct device_node *np = dev->of_node;
3182 struct sh_eth_plat_data *pdata;
3183 const char *mac_addr;
3186 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
3190 ret = of_get_phy_mode(np);
3193 pdata->phy_interface = ret;
3195 mac_addr = of_get_mac_address(np);
3197 memcpy(pdata->mac_addr, mac_addr, ETH_ALEN);
3199 pdata->no_ether_link =
3200 of_property_read_bool(np, "renesas,no-ether-link");
3201 pdata->ether_link_active_low =
3202 of_property_read_bool(np, "renesas,ether-link-active-low");
3207 static const struct of_device_id sh_eth_match_table[] = {
3208 { .compatible = "renesas,gether-r8a7740", .data = &r8a7740_data },
3209 { .compatible = "renesas,ether-r8a7743", .data = &rcar_gen2_data },
3210 { .compatible = "renesas,ether-r8a7745", .data = &rcar_gen2_data },
3211 { .compatible = "renesas,ether-r8a7778", .data = &rcar_gen1_data },
3212 { .compatible = "renesas,ether-r8a7779", .data = &rcar_gen1_data },
3213 { .compatible = "renesas,ether-r8a7790", .data = &rcar_gen2_data },
3214 { .compatible = "renesas,ether-r8a7791", .data = &rcar_gen2_data },
3215 { .compatible = "renesas,ether-r8a7793", .data = &rcar_gen2_data },
3216 { .compatible = "renesas,ether-r8a7794", .data = &rcar_gen2_data },
3217 { .compatible = "renesas,gether-r8a77980", .data = &r8a77980_data },
3218 { .compatible = "renesas,ether-r7s72100", .data = &r7s72100_data },
3219 { .compatible = "renesas,ether-r7s9210", .data = &r7s9210_data },
3220 { .compatible = "renesas,rcar-gen1-ether", .data = &rcar_gen1_data },
3221 { .compatible = "renesas,rcar-gen2-ether", .data = &rcar_gen2_data },
3224 MODULE_DEVICE_TABLE(of, sh_eth_match_table);
3226 static inline struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev)
3232 static int sh_eth_drv_probe(struct platform_device *pdev)
3234 struct resource *res;
3235 struct sh_eth_plat_data *pd = dev_get_platdata(&pdev->dev);
3236 const struct platform_device_id *id = platform_get_device_id(pdev);
3237 struct sh_eth_private *mdp;
3238 struct net_device *ndev;
3242 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3244 ndev = alloc_etherdev(sizeof(struct sh_eth_private));
3248 pm_runtime_enable(&pdev->dev);
3249 pm_runtime_get_sync(&pdev->dev);
3251 ret = platform_get_irq(pdev, 0);
3256 SET_NETDEV_DEV(ndev, &pdev->dev);
3258 mdp = netdev_priv(ndev);
3259 mdp->num_tx_ring = TX_RING_SIZE;
3260 mdp->num_rx_ring = RX_RING_SIZE;
3261 mdp->addr = devm_ioremap_resource(&pdev->dev, res);
3262 if (IS_ERR(mdp->addr)) {
3263 ret = PTR_ERR(mdp->addr);
3267 ndev->base_addr = res->start;
3269 spin_lock_init(&mdp->lock);
3272 if (pdev->dev.of_node)
3273 pd = sh_eth_parse_dt(&pdev->dev);
3275 dev_err(&pdev->dev, "no platform data\n");
3281 mdp->phy_id = pd->phy;
3282 mdp->phy_interface = pd->phy_interface;
3283 mdp->no_ether_link = pd->no_ether_link;
3284 mdp->ether_link_active_low = pd->ether_link_active_low;
3288 mdp->cd = (struct sh_eth_cpu_data *)id->driver_data;
3290 mdp->cd = (struct sh_eth_cpu_data *)of_device_get_match_data(&pdev->dev);
3292 mdp->reg_offset = sh_eth_get_register_offset(mdp->cd->register_type);
3293 if (!mdp->reg_offset) {
3294 dev_err(&pdev->dev, "Unknown register type (%d)\n",
3295 mdp->cd->register_type);
3299 sh_eth_set_default_cpu_data(mdp->cd);
3301 /* User's manual states max MTU should be 2048 but due to the
3302 * alignment calculations in sh_eth_ring_init() the practical
3303 * MTU is a bit less. Maybe this can be optimized some more.
3305 ndev->max_mtu = 2000 - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN);
3306 ndev->min_mtu = ETH_MIN_MTU;
3308 if (mdp->cd->rx_csum) {
3309 ndev->features = NETIF_F_RXCSUM;
3310 ndev->hw_features = NETIF_F_RXCSUM;
3315 ndev->netdev_ops = &sh_eth_netdev_ops_tsu;
3317 ndev->netdev_ops = &sh_eth_netdev_ops;
3318 ndev->ethtool_ops = &sh_eth_ethtool_ops;
3319 ndev->watchdog_timeo = TX_TIMEOUT;
3321 /* debug message level */
3322 mdp->msg_enable = SH_ETH_DEF_MSG_ENABLE;
3324 /* read and set MAC address */
3325 read_mac_address(ndev, pd->mac_addr);
3326 if (!is_valid_ether_addr(ndev->dev_addr)) {
3327 dev_warn(&pdev->dev,
3328 "no valid MAC address supplied, using a random one.\n");
3329 eth_hw_addr_random(ndev);
3333 int port = pdev->id < 0 ? 0 : pdev->id % 2;
3334 struct resource *rtsu;
3336 rtsu = platform_get_resource(pdev, IORESOURCE_MEM, 1);
3338 dev_err(&pdev->dev, "no TSU resource\n");
3342 /* We can only request the TSU region for the first port
3343 * of the two sharing this TSU for the probe to succeed...
3346 !devm_request_mem_region(&pdev->dev, rtsu->start,
3347 resource_size(rtsu),
3348 dev_name(&pdev->dev))) {
3349 dev_err(&pdev->dev, "can't request TSU resource.\n");
3353 /* ioremap the TSU registers */
3354 mdp->tsu_addr = devm_ioremap(&pdev->dev, rtsu->start,
3355 resource_size(rtsu));
3356 if (!mdp->tsu_addr) {
3357 dev_err(&pdev->dev, "TSU region ioremap() failed.\n");
3362 ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
3364 /* Need to init only the first port of the two sharing a TSU */
3366 if (mdp->cd->chip_reset)
3367 mdp->cd->chip_reset(ndev);
3369 /* TSU init (Init only)*/
3370 sh_eth_tsu_init(mdp);
3374 if (mdp->cd->rmiimode)
3375 sh_eth_write(ndev, 0x1, RMIIMODE);
3378 ret = sh_mdio_init(mdp, pd);
3380 if (ret != -EPROBE_DEFER)
3381 dev_err(&pdev->dev, "MDIO init failed: %d\n", ret);
3385 netif_napi_add(ndev, &mdp->napi, sh_eth_poll, 64);
3387 /* network device register */
3388 ret = register_netdev(ndev);
3393 device_set_wakeup_capable(&pdev->dev, 1);
3395 /* print device information */
3396 netdev_info(ndev, "Base address at 0x%x, %pM, IRQ %d.\n",
3397 (u32)ndev->base_addr, ndev->dev_addr, ndev->irq);
3399 pm_runtime_put(&pdev->dev);
3400 platform_set_drvdata(pdev, ndev);
3405 netif_napi_del(&mdp->napi);
3406 sh_mdio_release(mdp);
3412 pm_runtime_put(&pdev->dev);
3413 pm_runtime_disable(&pdev->dev);
3417 static int sh_eth_drv_remove(struct platform_device *pdev)
3419 struct net_device *ndev = platform_get_drvdata(pdev);
3420 struct sh_eth_private *mdp = netdev_priv(ndev);
3422 unregister_netdev(ndev);
3423 netif_napi_del(&mdp->napi);
3424 sh_mdio_release(mdp);
3425 pm_runtime_disable(&pdev->dev);
3432 #ifdef CONFIG_PM_SLEEP
3433 static int sh_eth_wol_setup(struct net_device *ndev)
3435 struct sh_eth_private *mdp = netdev_priv(ndev);
3437 /* Only allow ECI interrupts */
3438 synchronize_irq(ndev->irq);
3439 napi_disable(&mdp->napi);
3440 sh_eth_write(ndev, EESIPR_ECIIP, EESIPR);
3442 /* Enable MagicPacket */
3443 sh_eth_modify(ndev, ECMR, ECMR_MPDE, ECMR_MPDE);
3445 return enable_irq_wake(ndev->irq);
3448 static int sh_eth_wol_restore(struct net_device *ndev)
3450 struct sh_eth_private *mdp = netdev_priv(ndev);
3453 napi_enable(&mdp->napi);
3455 /* Disable MagicPacket */
3456 sh_eth_modify(ndev, ECMR, ECMR_MPDE, 0);
3458 /* The device needs to be reset to restore MagicPacket logic
3459 * for next wakeup. If we close and open the device it will
3460 * both be reset and all registers restored. This is what
3461 * happens during suspend and resume without WoL enabled.
3463 ret = sh_eth_close(ndev);
3466 ret = sh_eth_open(ndev);
3470 return disable_irq_wake(ndev->irq);
3473 static int sh_eth_suspend(struct device *dev)
3475 struct net_device *ndev = dev_get_drvdata(dev);
3476 struct sh_eth_private *mdp = netdev_priv(ndev);
3479 if (!netif_running(ndev))
3482 netif_device_detach(ndev);
3484 if (mdp->wol_enabled)
3485 ret = sh_eth_wol_setup(ndev);
3487 ret = sh_eth_close(ndev);
3492 static int sh_eth_resume(struct device *dev)
3494 struct net_device *ndev = dev_get_drvdata(dev);
3495 struct sh_eth_private *mdp = netdev_priv(ndev);
3498 if (!netif_running(ndev))
3501 if (mdp->wol_enabled)
3502 ret = sh_eth_wol_restore(ndev);
3504 ret = sh_eth_open(ndev);
3509 netif_device_attach(ndev);
3515 static int sh_eth_runtime_nop(struct device *dev)
3517 /* Runtime PM callback shared between ->runtime_suspend()
3518 * and ->runtime_resume(). Simply returns success.
3520 * This driver re-initializes all registers after
3521 * pm_runtime_get_sync() anyway so there is no need
3522 * to save and restore registers here.
3527 static const struct dev_pm_ops sh_eth_dev_pm_ops = {
3528 SET_SYSTEM_SLEEP_PM_OPS(sh_eth_suspend, sh_eth_resume)
3529 SET_RUNTIME_PM_OPS(sh_eth_runtime_nop, sh_eth_runtime_nop, NULL)
3531 #define SH_ETH_PM_OPS (&sh_eth_dev_pm_ops)
3533 #define SH_ETH_PM_OPS NULL
3536 static const struct platform_device_id sh_eth_id_table[] = {
3537 { "sh7619-ether", (kernel_ulong_t)&sh7619_data },
3538 { "sh771x-ether", (kernel_ulong_t)&sh771x_data },
3539 { "sh7724-ether", (kernel_ulong_t)&sh7724_data },
3540 { "sh7734-gether", (kernel_ulong_t)&sh7734_data },
3541 { "sh7757-ether", (kernel_ulong_t)&sh7757_data },
3542 { "sh7757-gether", (kernel_ulong_t)&sh7757_data_giga },
3543 { "sh7763-gether", (kernel_ulong_t)&sh7763_data },
3546 MODULE_DEVICE_TABLE(platform, sh_eth_id_table);
3548 static struct platform_driver sh_eth_driver = {
3549 .probe = sh_eth_drv_probe,
3550 .remove = sh_eth_drv_remove,
3551 .id_table = sh_eth_id_table,
3554 .pm = SH_ETH_PM_OPS,
3555 .of_match_table = of_match_ptr(sh_eth_match_table),
3559 module_platform_driver(sh_eth_driver);
3561 MODULE_AUTHOR("Nobuhiro Iwamatsu, Yoshihiro Shimoda");
3562 MODULE_DESCRIPTION("Renesas SuperH Ethernet driver");
3563 MODULE_LICENSE("GPL v2");