1 /* SuperH Ethernet device driver
3 * Copyright (C) 2014 Renesas Electronics Corporation
4 * Copyright (C) 2006-2012 Nobuhiro Iwamatsu
5 * Copyright (C) 2008-2014 Renesas Solutions Corp.
6 * Copyright (C) 2013-2017 Cogent Embedded, Inc.
7 * Copyright (C) 2014 Codethink Limited
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms and conditions of the GNU General Public License,
11 * version 2, as published by the Free Software Foundation.
13 * This program is distributed in the hope it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
22 #include <linux/module.h>
23 #include <linux/kernel.h>
24 #include <linux/spinlock.h>
25 #include <linux/interrupt.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/etherdevice.h>
28 #include <linux/delay.h>
29 #include <linux/platform_device.h>
30 #include <linux/mdio-bitbang.h>
31 #include <linux/netdevice.h>
33 #include <linux/of_device.h>
34 #include <linux/of_irq.h>
35 #include <linux/of_net.h>
36 #include <linux/phy.h>
37 #include <linux/cache.h>
39 #include <linux/pm_runtime.h>
40 #include <linux/slab.h>
41 #include <linux/ethtool.h>
42 #include <linux/if_vlan.h>
43 #include <linux/clk.h>
44 #include <linux/sh_eth.h>
45 #include <linux/of_mdio.h>
49 #define SH_ETH_DEF_MSG_ENABLE \
55 #define SH_ETH_OFFSET_INVALID ((u16)~0)
57 #define SH_ETH_OFFSET_DEFAULTS \
58 [0 ... SH_ETH_MAX_REGISTER_OFFSET - 1] = SH_ETH_OFFSET_INVALID
60 static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = {
61 SH_ETH_OFFSET_DEFAULTS,
116 [TSU_CTRST] = 0x0004,
117 [TSU_FWEN0] = 0x0010,
118 [TSU_FWEN1] = 0x0014,
120 [TSU_BSYSL0] = 0x0020,
121 [TSU_BSYSL1] = 0x0024,
122 [TSU_PRISL0] = 0x0028,
123 [TSU_PRISL1] = 0x002c,
124 [TSU_FWSL0] = 0x0030,
125 [TSU_FWSL1] = 0x0034,
126 [TSU_FWSLC] = 0x0038,
127 [TSU_QTAG0] = 0x0040,
128 [TSU_QTAG1] = 0x0044,
130 [TSU_FWINMK] = 0x0054,
131 [TSU_ADQT0] = 0x0048,
132 [TSU_ADQT1] = 0x004c,
133 [TSU_VTAG0] = 0x0058,
134 [TSU_VTAG1] = 0x005c,
135 [TSU_ADSBSY] = 0x0060,
137 [TSU_POST1] = 0x0070,
138 [TSU_POST2] = 0x0074,
139 [TSU_POST3] = 0x0078,
140 [TSU_POST4] = 0x007c,
141 [TSU_ADRH0] = 0x0100,
157 static const u16 sh_eth_offset_fast_rz[SH_ETH_MAX_REGISTER_OFFSET] = {
158 SH_ETH_OFFSET_DEFAULTS,
203 [TSU_CTRST] = 0x0004,
204 [TSU_FWSLC] = 0x0038,
205 [TSU_VTAG0] = 0x0058,
206 [TSU_ADSBSY] = 0x0060,
208 [TSU_POST1] = 0x0070,
209 [TSU_POST2] = 0x0074,
210 [TSU_POST3] = 0x0078,
211 [TSU_POST4] = 0x007c,
212 [TSU_ADRH0] = 0x0100,
220 static const u16 sh_eth_offset_fast_rcar[SH_ETH_MAX_REGISTER_OFFSET] = {
221 SH_ETH_OFFSET_DEFAULTS,
268 static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
269 SH_ETH_OFFSET_DEFAULTS,
322 static const u16 sh_eth_offset_fast_sh3_sh2[SH_ETH_MAX_REGISTER_OFFSET] = {
323 SH_ETH_OFFSET_DEFAULTS,
371 [TSU_CTRST] = 0x0004,
372 [TSU_FWEN0] = 0x0010,
373 [TSU_FWEN1] = 0x0014,
375 [TSU_BSYSL0] = 0x0020,
376 [TSU_BSYSL1] = 0x0024,
377 [TSU_PRISL0] = 0x0028,
378 [TSU_PRISL1] = 0x002c,
379 [TSU_FWSL0] = 0x0030,
380 [TSU_FWSL1] = 0x0034,
381 [TSU_FWSLC] = 0x0038,
382 [TSU_QTAGM0] = 0x0040,
383 [TSU_QTAGM1] = 0x0044,
384 [TSU_ADQT0] = 0x0048,
385 [TSU_ADQT1] = 0x004c,
387 [TSU_FWINMK] = 0x0054,
388 [TSU_ADSBSY] = 0x0060,
390 [TSU_POST1] = 0x0070,
391 [TSU_POST2] = 0x0074,
392 [TSU_POST3] = 0x0078,
393 [TSU_POST4] = 0x007c,
408 [TSU_ADRH0] = 0x0100,
411 static void sh_eth_rcv_snd_disable(struct net_device *ndev);
412 static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev);
414 static void sh_eth_write(struct net_device *ndev, u32 data, int enum_index)
416 struct sh_eth_private *mdp = netdev_priv(ndev);
417 u16 offset = mdp->reg_offset[enum_index];
419 if (WARN_ON(offset == SH_ETH_OFFSET_INVALID))
422 iowrite32(data, mdp->addr + offset);
425 static u32 sh_eth_read(struct net_device *ndev, int enum_index)
427 struct sh_eth_private *mdp = netdev_priv(ndev);
428 u16 offset = mdp->reg_offset[enum_index];
430 if (WARN_ON(offset == SH_ETH_OFFSET_INVALID))
433 return ioread32(mdp->addr + offset);
436 static void sh_eth_modify(struct net_device *ndev, int enum_index, u32 clear,
439 sh_eth_write(ndev, (sh_eth_read(ndev, enum_index) & ~clear) | set,
443 static bool sh_eth_is_gether(struct sh_eth_private *mdp)
445 return mdp->reg_offset == sh_eth_offset_gigabit;
448 static bool sh_eth_is_rz_fast_ether(struct sh_eth_private *mdp)
450 return mdp->reg_offset == sh_eth_offset_fast_rz;
453 static void sh_eth_select_mii(struct net_device *ndev)
455 struct sh_eth_private *mdp = netdev_priv(ndev);
458 switch (mdp->phy_interface) {
459 case PHY_INTERFACE_MODE_GMII:
462 case PHY_INTERFACE_MODE_MII:
465 case PHY_INTERFACE_MODE_RMII:
470 "PHY interface mode was not setup. Set to MII.\n");
475 sh_eth_write(ndev, value, RMII_MII);
478 static void sh_eth_set_duplex(struct net_device *ndev)
480 struct sh_eth_private *mdp = netdev_priv(ndev);
482 sh_eth_modify(ndev, ECMR, ECMR_DM, mdp->duplex ? ECMR_DM : 0);
485 static void sh_eth_chip_reset(struct net_device *ndev)
487 struct sh_eth_private *mdp = netdev_priv(ndev);
490 sh_eth_tsu_write(mdp, ARSTR_ARST, ARSTR);
494 static void sh_eth_set_rate_gether(struct net_device *ndev)
496 struct sh_eth_private *mdp = netdev_priv(ndev);
498 switch (mdp->speed) {
499 case 10: /* 10BASE */
500 sh_eth_write(ndev, GECMR_10, GECMR);
502 case 100:/* 100BASE */
503 sh_eth_write(ndev, GECMR_100, GECMR);
505 case 1000: /* 1000BASE */
506 sh_eth_write(ndev, GECMR_1000, GECMR);
513 static struct sh_eth_cpu_data r7s72100_data = {
514 .chip_reset = sh_eth_chip_reset,
515 .set_duplex = sh_eth_set_duplex,
517 .register_type = SH_ETH_REG_FAST_RZ,
519 .ecsr_value = ECSR_ICD,
520 .ecsipr_value = ECSIPR_ICDIP,
521 .eesipr_value = EESIPR_TWB1IP | EESIPR_TWBIP | EESIPR_TC1IP |
522 EESIPR_TABTIP | EESIPR_RABTIP | EESIPR_RFCOFIP |
524 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
525 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
526 EESIPR_RMAFIP | EESIPR_RRFIP |
527 EESIPR_RTLFIP | EESIPR_RTSFIP |
528 EESIPR_PREIP | EESIPR_CERFIP,
530 .tx_check = EESR_TC1 | EESR_FTC,
531 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
532 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
534 .fdr_value = 0x0000070f,
542 .rpadir_value = 2 << 16,
549 static void sh_eth_chip_reset_r8a7740(struct net_device *ndev)
551 sh_eth_chip_reset(ndev);
553 sh_eth_select_mii(ndev);
557 static struct sh_eth_cpu_data r8a7740_data = {
558 .chip_reset = sh_eth_chip_reset_r8a7740,
559 .set_duplex = sh_eth_set_duplex,
560 .set_rate = sh_eth_set_rate_gether,
562 .register_type = SH_ETH_REG_GIGABIT,
564 .ecsr_value = ECSR_ICD | ECSR_MPD,
565 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
566 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP |
567 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
568 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
569 0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP |
570 EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP |
571 EESIPR_CEEFIP | EESIPR_CELFIP |
572 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
573 EESIPR_PREIP | EESIPR_CERFIP,
575 .tx_check = EESR_TC1 | EESR_FTC,
576 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
577 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
579 .fdr_value = 0x0000070f,
587 .rpadir_value = 2 << 16,
596 /* There is CPU dependent code */
597 static void sh_eth_set_rate_r8a777x(struct net_device *ndev)
599 struct sh_eth_private *mdp = netdev_priv(ndev);
601 switch (mdp->speed) {
602 case 10: /* 10BASE */
603 sh_eth_modify(ndev, ECMR, ECMR_ELB, 0);
605 case 100:/* 100BASE */
606 sh_eth_modify(ndev, ECMR, ECMR_ELB, ECMR_ELB);
612 static struct sh_eth_cpu_data r8a777x_data = {
613 .set_duplex = sh_eth_set_duplex,
614 .set_rate = sh_eth_set_rate_r8a777x,
616 .register_type = SH_ETH_REG_FAST_RCAR,
618 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
619 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
620 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ADEIP | EESIPR_ECIIP |
621 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
622 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
623 EESIPR_RMAFIP | EESIPR_RRFIP |
624 EESIPR_RTLFIP | EESIPR_RTSFIP |
625 EESIPR_PREIP | EESIPR_CERFIP,
627 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
628 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
629 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE,
630 .fdr_value = 0x00000f0f,
639 static struct sh_eth_cpu_data r8a779x_data = {
640 .set_duplex = sh_eth_set_duplex,
641 .set_rate = sh_eth_set_rate_r8a777x,
643 .register_type = SH_ETH_REG_FAST_RCAR,
645 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD | ECSR_MPD,
646 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP |
648 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ADEIP | EESIPR_ECIIP |
649 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
650 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
651 EESIPR_RMAFIP | EESIPR_RRFIP |
652 EESIPR_RTLFIP | EESIPR_RTSFIP |
653 EESIPR_PREIP | EESIPR_CERFIP,
655 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
656 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
657 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE,
658 .fdr_value = 0x00000f0f,
660 .trscer_err_mask = DESC_I_RINT8,
669 #endif /* CONFIG_OF */
671 static void sh_eth_set_rate_sh7724(struct net_device *ndev)
673 struct sh_eth_private *mdp = netdev_priv(ndev);
675 switch (mdp->speed) {
676 case 10: /* 10BASE */
677 sh_eth_modify(ndev, ECMR, ECMR_RTM, 0);
679 case 100:/* 100BASE */
680 sh_eth_modify(ndev, ECMR, ECMR_RTM, ECMR_RTM);
686 static struct sh_eth_cpu_data sh7724_data = {
687 .set_duplex = sh_eth_set_duplex,
688 .set_rate = sh_eth_set_rate_sh7724,
690 .register_type = SH_ETH_REG_FAST_SH4,
692 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
693 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
694 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ADEIP | EESIPR_ECIIP |
695 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
696 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
697 EESIPR_RMAFIP | EESIPR_RRFIP |
698 EESIPR_RTLFIP | EESIPR_RTSFIP |
699 EESIPR_PREIP | EESIPR_CERFIP,
701 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
702 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
703 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE,
710 .rpadir_value = 0x00020000, /* NET_IP_ALIGN assumed to be 2 */
713 static void sh_eth_set_rate_sh7757(struct net_device *ndev)
715 struct sh_eth_private *mdp = netdev_priv(ndev);
717 switch (mdp->speed) {
718 case 10: /* 10BASE */
719 sh_eth_write(ndev, 0, RTRATE);
721 case 100:/* 100BASE */
722 sh_eth_write(ndev, 1, RTRATE);
728 static struct sh_eth_cpu_data sh7757_data = {
729 .set_duplex = sh_eth_set_duplex,
730 .set_rate = sh_eth_set_rate_sh7757,
732 .register_type = SH_ETH_REG_FAST_SH4,
734 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP |
735 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
736 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
737 0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP |
738 EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP |
739 EESIPR_CEEFIP | EESIPR_CELFIP |
740 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
741 EESIPR_PREIP | EESIPR_CERFIP,
743 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
744 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
745 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE,
747 .irq_flags = IRQF_SHARED,
754 .rpadir_value = 2 << 16,
758 #define SH_GIGA_ETH_BASE 0xfee00000UL
759 #define GIGA_MALR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c8)
760 #define GIGA_MAHR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c0)
761 static void sh_eth_chip_reset_giga(struct net_device *ndev)
763 u32 mahr[2], malr[2];
766 /* save MAHR and MALR */
767 for (i = 0; i < 2; i++) {
768 malr[i] = ioread32((void *)GIGA_MALR(i));
769 mahr[i] = ioread32((void *)GIGA_MAHR(i));
772 sh_eth_chip_reset(ndev);
774 /* restore MAHR and MALR */
775 for (i = 0; i < 2; i++) {
776 iowrite32(malr[i], (void *)GIGA_MALR(i));
777 iowrite32(mahr[i], (void *)GIGA_MAHR(i));
781 static void sh_eth_set_rate_giga(struct net_device *ndev)
783 struct sh_eth_private *mdp = netdev_priv(ndev);
785 switch (mdp->speed) {
786 case 10: /* 10BASE */
787 sh_eth_write(ndev, 0x00000000, GECMR);
789 case 100:/* 100BASE */
790 sh_eth_write(ndev, 0x00000010, GECMR);
792 case 1000: /* 1000BASE */
793 sh_eth_write(ndev, 0x00000020, GECMR);
798 /* SH7757(GETHERC) */
799 static struct sh_eth_cpu_data sh7757_data_giga = {
800 .chip_reset = sh_eth_chip_reset_giga,
801 .set_duplex = sh_eth_set_duplex,
802 .set_rate = sh_eth_set_rate_giga,
804 .register_type = SH_ETH_REG_GIGABIT,
806 .ecsr_value = ECSR_ICD | ECSR_MPD,
807 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
808 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP |
809 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
810 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
811 0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP |
812 EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP |
813 EESIPR_CEEFIP | EESIPR_CELFIP |
814 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
815 EESIPR_PREIP | EESIPR_CERFIP,
817 .tx_check = EESR_TC1 | EESR_FTC,
818 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
819 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
821 .fdr_value = 0x0000072f,
823 .irq_flags = IRQF_SHARED,
830 .rpadir_value = 2 << 16,
837 static struct sh_eth_cpu_data sh7734_data = {
838 .chip_reset = sh_eth_chip_reset,
839 .set_duplex = sh_eth_set_duplex,
840 .set_rate = sh_eth_set_rate_gether,
842 .register_type = SH_ETH_REG_GIGABIT,
844 .ecsr_value = ECSR_ICD | ECSR_MPD,
845 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
846 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP |
847 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
848 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
849 EESIPR_DLCIP | EESIPR_CDIP | EESIPR_TROIP |
850 EESIPR_RMAFIP | EESIPR_CEEFIP | EESIPR_CELFIP |
851 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
852 EESIPR_PREIP | EESIPR_CERFIP,
854 .tx_check = EESR_TC1 | EESR_FTC,
855 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
856 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
873 static struct sh_eth_cpu_data sh7763_data = {
874 .chip_reset = sh_eth_chip_reset,
875 .set_duplex = sh_eth_set_duplex,
876 .set_rate = sh_eth_set_rate_gether,
878 .register_type = SH_ETH_REG_GIGABIT,
880 .ecsr_value = ECSR_ICD | ECSR_MPD,
881 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
882 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP |
883 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
884 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
885 EESIPR_DLCIP | EESIPR_CDIP | EESIPR_TROIP |
886 EESIPR_RMAFIP | EESIPR_CEEFIP | EESIPR_CELFIP |
887 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
888 EESIPR_PREIP | EESIPR_CERFIP,
890 .tx_check = EESR_TC1 | EESR_FTC,
891 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
892 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE,
902 .irq_flags = IRQF_SHARED,
906 static struct sh_eth_cpu_data sh7619_data = {
907 .register_type = SH_ETH_REG_FAST_SH3_SH2,
909 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP |
910 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
911 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
912 0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP |
913 EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP |
914 EESIPR_CEEFIP | EESIPR_CELFIP |
915 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
916 EESIPR_PREIP | EESIPR_CERFIP,
924 static struct sh_eth_cpu_data sh771x_data = {
925 .register_type = SH_ETH_REG_FAST_SH3_SH2,
927 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP |
928 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
929 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
930 0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP |
931 EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP |
932 EESIPR_CEEFIP | EESIPR_CELFIP |
933 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
934 EESIPR_PREIP | EESIPR_CERFIP,
938 static void sh_eth_set_default_cpu_data(struct sh_eth_cpu_data *cd)
941 cd->ecsr_value = DEFAULT_ECSR_INIT;
943 if (!cd->ecsipr_value)
944 cd->ecsipr_value = DEFAULT_ECSIPR_INIT;
946 if (!cd->fcftr_value)
947 cd->fcftr_value = DEFAULT_FIFO_F_D_RFF |
948 DEFAULT_FIFO_F_D_RFD;
951 cd->fdr_value = DEFAULT_FDR_INIT;
954 cd->tx_check = DEFAULT_TX_CHECK;
956 if (!cd->eesr_err_check)
957 cd->eesr_err_check = DEFAULT_EESR_ERR_CHECK;
959 if (!cd->trscer_err_mask)
960 cd->trscer_err_mask = DEFAULT_TRSCER_ERR_MASK;
963 static int sh_eth_check_reset(struct net_device *ndev)
969 if (!(sh_eth_read(ndev, EDMR) & EDMR_SRST_GETHER))
975 netdev_err(ndev, "Device reset failed\n");
981 static int sh_eth_reset(struct net_device *ndev)
983 struct sh_eth_private *mdp = netdev_priv(ndev);
986 if (sh_eth_is_gether(mdp) || sh_eth_is_rz_fast_ether(mdp)) {
987 sh_eth_write(ndev, EDSR_ENALL, EDSR);
988 sh_eth_modify(ndev, EDMR, EDMR_SRST_GETHER, EDMR_SRST_GETHER);
990 ret = sh_eth_check_reset(ndev);
995 sh_eth_write(ndev, 0x0, TDLAR);
996 sh_eth_write(ndev, 0x0, TDFAR);
997 sh_eth_write(ndev, 0x0, TDFXR);
998 sh_eth_write(ndev, 0x0, TDFFR);
999 sh_eth_write(ndev, 0x0, RDLAR);
1000 sh_eth_write(ndev, 0x0, RDFAR);
1001 sh_eth_write(ndev, 0x0, RDFXR);
1002 sh_eth_write(ndev, 0x0, RDFFR);
1004 /* Reset HW CRC register */
1005 if (mdp->cd->hw_checksum)
1006 sh_eth_write(ndev, 0x0, CSMR);
1008 /* Select MII mode */
1009 if (mdp->cd->select_mii)
1010 sh_eth_select_mii(ndev);
1012 sh_eth_modify(ndev, EDMR, EDMR_SRST_ETHER, EDMR_SRST_ETHER);
1014 sh_eth_modify(ndev, EDMR, EDMR_SRST_ETHER, 0);
1020 static void sh_eth_set_receive_align(struct sk_buff *skb)
1022 uintptr_t reserve = (uintptr_t)skb->data & (SH_ETH_RX_ALIGN - 1);
1025 skb_reserve(skb, SH_ETH_RX_ALIGN - reserve);
1028 /* Program the hardware MAC address from dev->dev_addr. */
1029 static void update_mac_address(struct net_device *ndev)
1032 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) |
1033 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR);
1035 (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR);
1038 /* Get MAC address from SuperH MAC address register
1040 * SuperH's Ethernet device doesn't have 'ROM' to MAC address.
1041 * This driver get MAC address that use by bootloader(U-boot or sh-ipl+g).
1042 * When you want use this device, you must set MAC address in bootloader.
1045 static void read_mac_address(struct net_device *ndev, unsigned char *mac)
1047 if (mac[0] || mac[1] || mac[2] || mac[3] || mac[4] || mac[5]) {
1048 memcpy(ndev->dev_addr, mac, ETH_ALEN);
1050 u32 mahr = sh_eth_read(ndev, MAHR);
1051 u32 malr = sh_eth_read(ndev, MALR);
1053 ndev->dev_addr[0] = (mahr >> 24) & 0xFF;
1054 ndev->dev_addr[1] = (mahr >> 16) & 0xFF;
1055 ndev->dev_addr[2] = (mahr >> 8) & 0xFF;
1056 ndev->dev_addr[3] = (mahr >> 0) & 0xFF;
1057 ndev->dev_addr[4] = (malr >> 8) & 0xFF;
1058 ndev->dev_addr[5] = (malr >> 0) & 0xFF;
1062 static u32 sh_eth_get_edtrr_trns(struct sh_eth_private *mdp)
1064 if (sh_eth_is_gether(mdp) || sh_eth_is_rz_fast_ether(mdp))
1065 return EDTRR_TRNS_GETHER;
1067 return EDTRR_TRNS_ETHER;
1071 void (*set_gate)(void *addr);
1072 struct mdiobb_ctrl ctrl;
1076 static void sh_mdio_ctrl(struct mdiobb_ctrl *ctrl, u32 mask, int set)
1078 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1081 if (bitbang->set_gate)
1082 bitbang->set_gate(bitbang->addr);
1084 pir = ioread32(bitbang->addr);
1089 iowrite32(pir, bitbang->addr);
1092 /* Data I/O pin control */
1093 static void sh_mmd_ctrl(struct mdiobb_ctrl *ctrl, int bit)
1095 sh_mdio_ctrl(ctrl, PIR_MMD, bit);
1099 static void sh_set_mdio(struct mdiobb_ctrl *ctrl, int bit)
1101 sh_mdio_ctrl(ctrl, PIR_MDO, bit);
1105 static int sh_get_mdio(struct mdiobb_ctrl *ctrl)
1107 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1109 if (bitbang->set_gate)
1110 bitbang->set_gate(bitbang->addr);
1112 return (ioread32(bitbang->addr) & PIR_MDI) != 0;
1115 /* MDC pin control */
1116 static void sh_mdc_ctrl(struct mdiobb_ctrl *ctrl, int bit)
1118 sh_mdio_ctrl(ctrl, PIR_MDC, bit);
1121 /* mdio bus control struct */
1122 static struct mdiobb_ops bb_ops = {
1123 .owner = THIS_MODULE,
1124 .set_mdc = sh_mdc_ctrl,
1125 .set_mdio_dir = sh_mmd_ctrl,
1126 .set_mdio_data = sh_set_mdio,
1127 .get_mdio_data = sh_get_mdio,
1130 /* free Tx skb function */
1131 static int sh_eth_tx_free(struct net_device *ndev, bool sent_only)
1133 struct sh_eth_private *mdp = netdev_priv(ndev);
1134 struct sh_eth_txdesc *txdesc;
1139 for (; mdp->cur_tx - mdp->dirty_tx > 0; mdp->dirty_tx++) {
1140 entry = mdp->dirty_tx % mdp->num_tx_ring;
1141 txdesc = &mdp->tx_ring[entry];
1142 sent = !(txdesc->status & cpu_to_le32(TD_TACT));
1143 if (sent_only && !sent)
1145 /* TACT bit must be checked before all the following reads */
1147 netif_info(mdp, tx_done, ndev,
1148 "tx entry %d status 0x%08x\n",
1149 entry, le32_to_cpu(txdesc->status));
1150 /* Free the original skb. */
1151 if (mdp->tx_skbuff[entry]) {
1152 dma_unmap_single(&ndev->dev, le32_to_cpu(txdesc->addr),
1153 le32_to_cpu(txdesc->len) >> 16,
1155 dev_kfree_skb_irq(mdp->tx_skbuff[entry]);
1156 mdp->tx_skbuff[entry] = NULL;
1159 txdesc->status = cpu_to_le32(TD_TFP);
1160 if (entry >= mdp->num_tx_ring - 1)
1161 txdesc->status |= cpu_to_le32(TD_TDLE);
1164 ndev->stats.tx_packets++;
1165 ndev->stats.tx_bytes += le32_to_cpu(txdesc->len) >> 16;
1171 /* free skb and descriptor buffer */
1172 static void sh_eth_ring_free(struct net_device *ndev)
1174 struct sh_eth_private *mdp = netdev_priv(ndev);
1178 for (i = 0; i < mdp->num_rx_ring; i++) {
1179 if (mdp->rx_skbuff[i]) {
1180 struct sh_eth_rxdesc *rxdesc = &mdp->rx_ring[i];
1182 dma_unmap_single(&ndev->dev,
1183 le32_to_cpu(rxdesc->addr),
1184 ALIGN(mdp->rx_buf_sz, 32),
1188 ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
1189 dma_free_coherent(NULL, ringsize, mdp->rx_ring,
1191 mdp->rx_ring = NULL;
1194 /* Free Rx skb ringbuffer */
1195 if (mdp->rx_skbuff) {
1196 for (i = 0; i < mdp->num_rx_ring; i++)
1197 dev_kfree_skb(mdp->rx_skbuff[i]);
1199 kfree(mdp->rx_skbuff);
1200 mdp->rx_skbuff = NULL;
1203 sh_eth_tx_free(ndev, false);
1205 ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
1206 dma_free_coherent(NULL, ringsize, mdp->tx_ring,
1208 mdp->tx_ring = NULL;
1211 /* Free Tx skb ringbuffer */
1212 kfree(mdp->tx_skbuff);
1213 mdp->tx_skbuff = NULL;
1216 /* format skb and descriptor buffer */
1217 static void sh_eth_ring_format(struct net_device *ndev)
1219 struct sh_eth_private *mdp = netdev_priv(ndev);
1221 struct sk_buff *skb;
1222 struct sh_eth_rxdesc *rxdesc = NULL;
1223 struct sh_eth_txdesc *txdesc = NULL;
1224 int rx_ringsize = sizeof(*rxdesc) * mdp->num_rx_ring;
1225 int tx_ringsize = sizeof(*txdesc) * mdp->num_tx_ring;
1226 int skbuff_size = mdp->rx_buf_sz + SH_ETH_RX_ALIGN + 32 - 1;
1227 dma_addr_t dma_addr;
1235 memset(mdp->rx_ring, 0, rx_ringsize);
1237 /* build Rx ring buffer */
1238 for (i = 0; i < mdp->num_rx_ring; i++) {
1240 mdp->rx_skbuff[i] = NULL;
1241 skb = netdev_alloc_skb(ndev, skbuff_size);
1244 sh_eth_set_receive_align(skb);
1246 /* The size of the buffer is a multiple of 32 bytes. */
1247 buf_len = ALIGN(mdp->rx_buf_sz, 32);
1248 dma_addr = dma_map_single(&ndev->dev, skb->data, buf_len,
1250 if (dma_mapping_error(&ndev->dev, dma_addr)) {
1254 mdp->rx_skbuff[i] = skb;
1257 rxdesc = &mdp->rx_ring[i];
1258 rxdesc->len = cpu_to_le32(buf_len << 16);
1259 rxdesc->addr = cpu_to_le32(dma_addr);
1260 rxdesc->status = cpu_to_le32(RD_RACT | RD_RFP);
1262 /* Rx descriptor address set */
1264 sh_eth_write(ndev, mdp->rx_desc_dma, RDLAR);
1265 if (sh_eth_is_gether(mdp) ||
1266 sh_eth_is_rz_fast_ether(mdp))
1267 sh_eth_write(ndev, mdp->rx_desc_dma, RDFAR);
1271 mdp->dirty_rx = (u32) (i - mdp->num_rx_ring);
1273 /* Mark the last entry as wrapping the ring. */
1275 rxdesc->status |= cpu_to_le32(RD_RDLE);
1277 memset(mdp->tx_ring, 0, tx_ringsize);
1279 /* build Tx ring buffer */
1280 for (i = 0; i < mdp->num_tx_ring; i++) {
1281 mdp->tx_skbuff[i] = NULL;
1282 txdesc = &mdp->tx_ring[i];
1283 txdesc->status = cpu_to_le32(TD_TFP);
1284 txdesc->len = cpu_to_le32(0);
1286 /* Tx descriptor address set */
1287 sh_eth_write(ndev, mdp->tx_desc_dma, TDLAR);
1288 if (sh_eth_is_gether(mdp) ||
1289 sh_eth_is_rz_fast_ether(mdp))
1290 sh_eth_write(ndev, mdp->tx_desc_dma, TDFAR);
1294 txdesc->status |= cpu_to_le32(TD_TDLE);
1297 /* Get skb and descriptor buffer */
1298 static int sh_eth_ring_init(struct net_device *ndev)
1300 struct sh_eth_private *mdp = netdev_priv(ndev);
1301 int rx_ringsize, tx_ringsize;
1303 /* +26 gets the maximum ethernet encapsulation, +7 & ~7 because the
1304 * card needs room to do 8 byte alignment, +2 so we can reserve
1305 * the first 2 bytes, and +16 gets room for the status word from the
1308 mdp->rx_buf_sz = (ndev->mtu <= 1492 ? PKT_BUF_SZ :
1309 (((ndev->mtu + 26 + 7) & ~7) + 2 + 16));
1310 if (mdp->cd->rpadir)
1311 mdp->rx_buf_sz += NET_IP_ALIGN;
1313 /* Allocate RX and TX skb rings */
1314 mdp->rx_skbuff = kcalloc(mdp->num_rx_ring, sizeof(*mdp->rx_skbuff),
1316 if (!mdp->rx_skbuff)
1319 mdp->tx_skbuff = kcalloc(mdp->num_tx_ring, sizeof(*mdp->tx_skbuff),
1321 if (!mdp->tx_skbuff)
1324 /* Allocate all Rx descriptors. */
1325 rx_ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
1326 mdp->rx_ring = dma_alloc_coherent(NULL, rx_ringsize, &mdp->rx_desc_dma,
1333 /* Allocate all Tx descriptors. */
1334 tx_ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
1335 mdp->tx_ring = dma_alloc_coherent(NULL, tx_ringsize, &mdp->tx_desc_dma,
1342 /* Free Rx and Tx skb ring buffer and DMA buffer */
1343 sh_eth_ring_free(ndev);
1348 static int sh_eth_dev_init(struct net_device *ndev)
1350 struct sh_eth_private *mdp = netdev_priv(ndev);
1354 ret = sh_eth_reset(ndev);
1358 if (mdp->cd->rmiimode)
1359 sh_eth_write(ndev, 0x1, RMIIMODE);
1361 /* Descriptor format */
1362 sh_eth_ring_format(ndev);
1363 if (mdp->cd->rpadir)
1364 sh_eth_write(ndev, mdp->cd->rpadir_value, RPADIR);
1366 /* all sh_eth int mask */
1367 sh_eth_write(ndev, 0, EESIPR);
1369 #if defined(__LITTLE_ENDIAN)
1370 if (mdp->cd->hw_swap)
1371 sh_eth_write(ndev, EDMR_EL, EDMR);
1374 sh_eth_write(ndev, 0, EDMR);
1377 sh_eth_write(ndev, mdp->cd->fdr_value, FDR);
1378 sh_eth_write(ndev, 0, TFTR);
1380 /* Frame recv control (enable multiple-packets per rx irq) */
1381 sh_eth_write(ndev, RMCR_RNC, RMCR);
1383 sh_eth_write(ndev, mdp->cd->trscer_err_mask, TRSCER);
1386 sh_eth_write(ndev, 0x800, BCULR); /* Burst sycle set */
1388 sh_eth_write(ndev, mdp->cd->fcftr_value, FCFTR);
1390 if (!mdp->cd->no_trimd)
1391 sh_eth_write(ndev, 0, TRIMD);
1393 /* Recv frame limit set register */
1394 sh_eth_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN,
1397 sh_eth_modify(ndev, EESR, 0, 0);
1398 mdp->irq_enabled = true;
1399 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
1401 /* PAUSE Prohibition */
1402 sh_eth_write(ndev, ECMR_ZPF | (mdp->duplex ? ECMR_DM : 0) |
1403 ECMR_TE | ECMR_RE, ECMR);
1405 if (mdp->cd->set_rate)
1406 mdp->cd->set_rate(ndev);
1408 /* E-MAC Status Register clear */
1409 sh_eth_write(ndev, mdp->cd->ecsr_value, ECSR);
1411 /* E-MAC Interrupt Enable register */
1412 sh_eth_write(ndev, mdp->cd->ecsipr_value, ECSIPR);
1414 /* Set MAC address */
1415 update_mac_address(ndev);
1419 sh_eth_write(ndev, APR_AP, APR);
1421 sh_eth_write(ndev, MPR_MP, MPR);
1422 if (mdp->cd->tpauser)
1423 sh_eth_write(ndev, TPAUSER_UNLIMITED, TPAUSER);
1425 /* Setting the Rx mode will start the Rx process. */
1426 sh_eth_write(ndev, EDRRR_R, EDRRR);
1431 static void sh_eth_dev_exit(struct net_device *ndev)
1433 struct sh_eth_private *mdp = netdev_priv(ndev);
1436 /* Deactivate all TX descriptors, so DMA should stop at next
1437 * packet boundary if it's currently running
1439 for (i = 0; i < mdp->num_tx_ring; i++)
1440 mdp->tx_ring[i].status &= ~cpu_to_le32(TD_TACT);
1442 /* Disable TX FIFO egress to MAC */
1443 sh_eth_rcv_snd_disable(ndev);
1445 /* Stop RX DMA at next packet boundary */
1446 sh_eth_write(ndev, 0, EDRRR);
1448 /* Aside from TX DMA, we can't tell when the hardware is
1449 * really stopped, so we need to reset to make sure.
1450 * Before doing that, wait for long enough to *probably*
1451 * finish transmitting the last packet and poll stats.
1453 msleep(2); /* max frame time at 10 Mbps < 1250 us */
1454 sh_eth_get_stats(ndev);
1457 /* Set MAC address again */
1458 update_mac_address(ndev);
1461 /* Packet receive function */
1462 static int sh_eth_rx(struct net_device *ndev, u32 intr_status, int *quota)
1464 struct sh_eth_private *mdp = netdev_priv(ndev);
1465 struct sh_eth_rxdesc *rxdesc;
1467 int entry = mdp->cur_rx % mdp->num_rx_ring;
1468 int boguscnt = (mdp->dirty_rx + mdp->num_rx_ring) - mdp->cur_rx;
1470 struct sk_buff *skb;
1472 int skbuff_size = mdp->rx_buf_sz + SH_ETH_RX_ALIGN + 32 - 1;
1473 dma_addr_t dma_addr;
1477 boguscnt = min(boguscnt, *quota);
1479 rxdesc = &mdp->rx_ring[entry];
1480 while (!(rxdesc->status & cpu_to_le32(RD_RACT))) {
1481 /* RACT bit must be checked before all the following reads */
1483 desc_status = le32_to_cpu(rxdesc->status);
1484 pkt_len = le32_to_cpu(rxdesc->len) & RD_RFL;
1489 netif_info(mdp, rx_status, ndev,
1490 "rx entry %d status 0x%08x len %d\n",
1491 entry, desc_status, pkt_len);
1493 if (!(desc_status & RDFEND))
1494 ndev->stats.rx_length_errors++;
1496 /* In case of almost all GETHER/ETHERs, the Receive Frame State
1497 * (RFS) bits in the Receive Descriptor 0 are from bit 9 to
1498 * bit 0. However, in case of the R8A7740 and R7S72100
1499 * the RFS bits are from bit 25 to bit 16. So, the
1500 * driver needs right shifting by 16.
1502 if (mdp->cd->hw_checksum)
1505 skb = mdp->rx_skbuff[entry];
1506 if (desc_status & (RD_RFS1 | RD_RFS2 | RD_RFS3 | RD_RFS4 |
1507 RD_RFS5 | RD_RFS6 | RD_RFS10)) {
1508 ndev->stats.rx_errors++;
1509 if (desc_status & RD_RFS1)
1510 ndev->stats.rx_crc_errors++;
1511 if (desc_status & RD_RFS2)
1512 ndev->stats.rx_frame_errors++;
1513 if (desc_status & RD_RFS3)
1514 ndev->stats.rx_length_errors++;
1515 if (desc_status & RD_RFS4)
1516 ndev->stats.rx_length_errors++;
1517 if (desc_status & RD_RFS6)
1518 ndev->stats.rx_missed_errors++;
1519 if (desc_status & RD_RFS10)
1520 ndev->stats.rx_over_errors++;
1522 dma_addr = le32_to_cpu(rxdesc->addr);
1523 if (!mdp->cd->hw_swap)
1525 phys_to_virt(ALIGN(dma_addr, 4)),
1527 mdp->rx_skbuff[entry] = NULL;
1528 if (mdp->cd->rpadir)
1529 skb_reserve(skb, NET_IP_ALIGN);
1530 dma_unmap_single(&ndev->dev, dma_addr,
1531 ALIGN(mdp->rx_buf_sz, 32),
1533 skb_put(skb, pkt_len);
1534 skb->protocol = eth_type_trans(skb, ndev);
1535 netif_receive_skb(skb);
1536 ndev->stats.rx_packets++;
1537 ndev->stats.rx_bytes += pkt_len;
1538 if (desc_status & RD_RFS8)
1539 ndev->stats.multicast++;
1541 entry = (++mdp->cur_rx) % mdp->num_rx_ring;
1542 rxdesc = &mdp->rx_ring[entry];
1545 /* Refill the Rx ring buffers. */
1546 for (; mdp->cur_rx - mdp->dirty_rx > 0; mdp->dirty_rx++) {
1547 entry = mdp->dirty_rx % mdp->num_rx_ring;
1548 rxdesc = &mdp->rx_ring[entry];
1549 /* The size of the buffer is 32 byte boundary. */
1550 buf_len = ALIGN(mdp->rx_buf_sz, 32);
1551 rxdesc->len = cpu_to_le32(buf_len << 16);
1553 if (mdp->rx_skbuff[entry] == NULL) {
1554 skb = netdev_alloc_skb(ndev, skbuff_size);
1556 break; /* Better luck next round. */
1557 sh_eth_set_receive_align(skb);
1558 dma_addr = dma_map_single(&ndev->dev, skb->data,
1559 buf_len, DMA_FROM_DEVICE);
1560 if (dma_mapping_error(&ndev->dev, dma_addr)) {
1564 mdp->rx_skbuff[entry] = skb;
1566 skb_checksum_none_assert(skb);
1567 rxdesc->addr = cpu_to_le32(dma_addr);
1569 dma_wmb(); /* RACT bit must be set after all the above writes */
1570 if (entry >= mdp->num_rx_ring - 1)
1572 cpu_to_le32(RD_RACT | RD_RFP | RD_RDLE);
1574 rxdesc->status |= cpu_to_le32(RD_RACT | RD_RFP);
1577 /* Restart Rx engine if stopped. */
1578 /* If we don't need to check status, don't. -KDU */
1579 if (!(sh_eth_read(ndev, EDRRR) & EDRRR_R)) {
1580 /* fix the values for the next receiving if RDE is set */
1581 if (intr_status & EESR_RDE &&
1582 mdp->reg_offset[RDFAR] != SH_ETH_OFFSET_INVALID) {
1583 u32 count = (sh_eth_read(ndev, RDFAR) -
1584 sh_eth_read(ndev, RDLAR)) >> 4;
1586 mdp->cur_rx = count;
1587 mdp->dirty_rx = count;
1589 sh_eth_write(ndev, EDRRR_R, EDRRR);
1592 *quota -= limit - boguscnt - 1;
1597 static void sh_eth_rcv_snd_disable(struct net_device *ndev)
1599 /* disable tx and rx */
1600 sh_eth_modify(ndev, ECMR, ECMR_RE | ECMR_TE, 0);
1603 static void sh_eth_rcv_snd_enable(struct net_device *ndev)
1605 /* enable tx and rx */
1606 sh_eth_modify(ndev, ECMR, ECMR_RE | ECMR_TE, ECMR_RE | ECMR_TE);
1609 /* E-MAC interrupt handler */
1610 static void sh_eth_emac_interrupt(struct net_device *ndev)
1612 struct sh_eth_private *mdp = netdev_priv(ndev);
1616 felic_stat = sh_eth_read(ndev, ECSR) & sh_eth_read(ndev, ECSIPR);
1617 sh_eth_write(ndev, felic_stat, ECSR); /* clear int */
1618 if (felic_stat & ECSR_ICD)
1619 ndev->stats.tx_carrier_errors++;
1620 if (felic_stat & ECSR_MPD)
1621 pm_wakeup_event(&mdp->pdev->dev, 0);
1622 if (felic_stat & ECSR_LCHNG) {
1624 if (mdp->cd->no_psr || mdp->no_ether_link)
1626 link_stat = sh_eth_read(ndev, PSR);
1627 if (mdp->ether_link_active_low)
1628 link_stat = ~link_stat;
1629 if (!(link_stat & PHY_ST_LINK)) {
1630 sh_eth_rcv_snd_disable(ndev);
1633 sh_eth_modify(ndev, EESIPR, EESIPR_ECIIP, 0);
1635 sh_eth_modify(ndev, ECSR, 0, 0);
1636 sh_eth_modify(ndev, EESIPR, EESIPR_ECIIP, EESIPR_ECIIP);
1637 /* enable tx and rx */
1638 sh_eth_rcv_snd_enable(ndev);
1643 /* error control function */
1644 static void sh_eth_error(struct net_device *ndev, u32 intr_status)
1646 struct sh_eth_private *mdp = netdev_priv(ndev);
1649 if (intr_status & EESR_TWB) {
1650 /* Unused write back interrupt */
1651 if (intr_status & EESR_TABT) { /* Transmit Abort int */
1652 ndev->stats.tx_aborted_errors++;
1653 netif_err(mdp, tx_err, ndev, "Transmit Abort\n");
1657 if (intr_status & EESR_RABT) {
1658 /* Receive Abort int */
1659 if (intr_status & EESR_RFRMER) {
1660 /* Receive Frame Overflow int */
1661 ndev->stats.rx_frame_errors++;
1665 if (intr_status & EESR_TDE) {
1666 /* Transmit Descriptor Empty int */
1667 ndev->stats.tx_fifo_errors++;
1668 netif_err(mdp, tx_err, ndev, "Transmit Descriptor Empty\n");
1671 if (intr_status & EESR_TFE) {
1672 /* FIFO under flow */
1673 ndev->stats.tx_fifo_errors++;
1674 netif_err(mdp, tx_err, ndev, "Transmit FIFO Under flow\n");
1677 if (intr_status & EESR_RDE) {
1678 /* Receive Descriptor Empty int */
1679 ndev->stats.rx_over_errors++;
1682 if (intr_status & EESR_RFE) {
1683 /* Receive FIFO Overflow int */
1684 ndev->stats.rx_fifo_errors++;
1687 if (!mdp->cd->no_ade && (intr_status & EESR_ADE)) {
1689 ndev->stats.tx_fifo_errors++;
1690 netif_err(mdp, tx_err, ndev, "Address Error\n");
1693 mask = EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE;
1694 if (mdp->cd->no_ade)
1696 if (intr_status & mask) {
1698 u32 edtrr = sh_eth_read(ndev, EDTRR);
1701 netdev_err(ndev, "TX error. status=%8.8x cur_tx=%8.8x dirty_tx=%8.8x state=%8.8x EDTRR=%8.8x.\n",
1702 intr_status, mdp->cur_tx, mdp->dirty_tx,
1703 (u32)ndev->state, edtrr);
1704 /* dirty buffer free */
1705 sh_eth_tx_free(ndev, true);
1708 if (edtrr ^ sh_eth_get_edtrr_trns(mdp)) {
1710 sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
1713 netif_wake_queue(ndev);
1717 static irqreturn_t sh_eth_interrupt(int irq, void *netdev)
1719 struct net_device *ndev = netdev;
1720 struct sh_eth_private *mdp = netdev_priv(ndev);
1721 struct sh_eth_cpu_data *cd = mdp->cd;
1722 irqreturn_t ret = IRQ_NONE;
1723 u32 intr_status, intr_enable;
1725 spin_lock(&mdp->lock);
1727 /* Get interrupt status */
1728 intr_status = sh_eth_read(ndev, EESR);
1729 /* Mask it with the interrupt mask, forcing ECI interrupt to be always
1730 * enabled since it's the one that comes thru regardless of the mask,
1731 * and we need to fully handle it in sh_eth_emac_interrupt() in order
1732 * to quench it as it doesn't get cleared by just writing 1 to the ECI
1735 intr_enable = sh_eth_read(ndev, EESIPR);
1736 intr_status &= intr_enable | EESIPR_ECIIP;
1737 if (intr_status & (EESR_RX_CHECK | cd->tx_check | EESR_ECI |
1738 cd->eesr_err_check))
1743 if (unlikely(!mdp->irq_enabled)) {
1744 sh_eth_write(ndev, 0, EESIPR);
1748 if (intr_status & EESR_RX_CHECK) {
1749 if (napi_schedule_prep(&mdp->napi)) {
1750 /* Mask Rx interrupts */
1751 sh_eth_write(ndev, intr_enable & ~EESR_RX_CHECK,
1753 __napi_schedule(&mdp->napi);
1756 "ignoring interrupt, status 0x%08x, mask 0x%08x.\n",
1757 intr_status, intr_enable);
1762 if (intr_status & cd->tx_check) {
1763 /* Clear Tx interrupts */
1764 sh_eth_write(ndev, intr_status & cd->tx_check, EESR);
1766 sh_eth_tx_free(ndev, true);
1767 netif_wake_queue(ndev);
1770 /* E-MAC interrupt */
1771 if (intr_status & EESR_ECI)
1772 sh_eth_emac_interrupt(ndev);
1774 if (intr_status & cd->eesr_err_check) {
1775 /* Clear error interrupts */
1776 sh_eth_write(ndev, intr_status & cd->eesr_err_check, EESR);
1778 sh_eth_error(ndev, intr_status);
1782 spin_unlock(&mdp->lock);
1787 static int sh_eth_poll(struct napi_struct *napi, int budget)
1789 struct sh_eth_private *mdp = container_of(napi, struct sh_eth_private,
1791 struct net_device *ndev = napi->dev;
1796 intr_status = sh_eth_read(ndev, EESR);
1797 if (!(intr_status & EESR_RX_CHECK))
1799 /* Clear Rx interrupts */
1800 sh_eth_write(ndev, intr_status & EESR_RX_CHECK, EESR);
1802 if (sh_eth_rx(ndev, intr_status, "a))
1806 napi_complete(napi);
1808 /* Reenable Rx interrupts */
1809 if (mdp->irq_enabled)
1810 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
1812 return budget - quota;
1815 /* PHY state control function */
1816 static void sh_eth_adjust_link(struct net_device *ndev)
1818 struct sh_eth_private *mdp = netdev_priv(ndev);
1819 struct phy_device *phydev = ndev->phydev;
1823 if (phydev->duplex != mdp->duplex) {
1825 mdp->duplex = phydev->duplex;
1826 if (mdp->cd->set_duplex)
1827 mdp->cd->set_duplex(ndev);
1830 if (phydev->speed != mdp->speed) {
1832 mdp->speed = phydev->speed;
1833 if (mdp->cd->set_rate)
1834 mdp->cd->set_rate(ndev);
1837 sh_eth_modify(ndev, ECMR, ECMR_TXF, 0);
1839 mdp->link = phydev->link;
1840 if (mdp->cd->no_psr || mdp->no_ether_link)
1841 sh_eth_rcv_snd_enable(ndev);
1843 } else if (mdp->link) {
1848 if (mdp->cd->no_psr || mdp->no_ether_link)
1849 sh_eth_rcv_snd_disable(ndev);
1852 if (new_state && netif_msg_link(mdp))
1853 phy_print_status(phydev);
1856 /* PHY init function */
1857 static int sh_eth_phy_init(struct net_device *ndev)
1859 struct device_node *np = ndev->dev.parent->of_node;
1860 struct sh_eth_private *mdp = netdev_priv(ndev);
1861 struct phy_device *phydev;
1867 /* Try connect to PHY */
1869 struct device_node *pn;
1871 pn = of_parse_phandle(np, "phy-handle", 0);
1872 phydev = of_phy_connect(ndev, pn,
1873 sh_eth_adjust_link, 0,
1874 mdp->phy_interface);
1878 phydev = ERR_PTR(-ENOENT);
1880 char phy_id[MII_BUS_ID_SIZE + 3];
1882 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
1883 mdp->mii_bus->id, mdp->phy_id);
1885 phydev = phy_connect(ndev, phy_id, sh_eth_adjust_link,
1886 mdp->phy_interface);
1889 if (IS_ERR(phydev)) {
1890 netdev_err(ndev, "failed to connect PHY\n");
1891 return PTR_ERR(phydev);
1894 phy_attached_info(phydev);
1899 /* PHY control start function */
1900 static int sh_eth_phy_start(struct net_device *ndev)
1904 ret = sh_eth_phy_init(ndev);
1908 phy_start(ndev->phydev);
1913 static int sh_eth_get_link_ksettings(struct net_device *ndev,
1914 struct ethtool_link_ksettings *cmd)
1916 struct sh_eth_private *mdp = netdev_priv(ndev);
1917 unsigned long flags;
1923 spin_lock_irqsave(&mdp->lock, flags);
1924 ret = phy_ethtool_ksettings_get(ndev->phydev, cmd);
1925 spin_unlock_irqrestore(&mdp->lock, flags);
1930 static int sh_eth_set_link_ksettings(struct net_device *ndev,
1931 const struct ethtool_link_ksettings *cmd)
1933 struct sh_eth_private *mdp = netdev_priv(ndev);
1934 unsigned long flags;
1940 spin_lock_irqsave(&mdp->lock, flags);
1942 /* disable tx and rx */
1943 sh_eth_rcv_snd_disable(ndev);
1945 ret = phy_ethtool_ksettings_set(ndev->phydev, cmd);
1949 if (cmd->base.duplex == DUPLEX_FULL)
1954 if (mdp->cd->set_duplex)
1955 mdp->cd->set_duplex(ndev);
1960 /* enable tx and rx */
1961 sh_eth_rcv_snd_enable(ndev);
1963 spin_unlock_irqrestore(&mdp->lock, flags);
1968 /* If it is ever necessary to increase SH_ETH_REG_DUMP_MAX_REGS, the
1969 * version must be bumped as well. Just adding registers up to that
1970 * limit is fine, as long as the existing register indices don't
1973 #define SH_ETH_REG_DUMP_VERSION 1
1974 #define SH_ETH_REG_DUMP_MAX_REGS 256
1976 static size_t __sh_eth_get_regs(struct net_device *ndev, u32 *buf)
1978 struct sh_eth_private *mdp = netdev_priv(ndev);
1979 struct sh_eth_cpu_data *cd = mdp->cd;
1983 BUILD_BUG_ON(SH_ETH_MAX_REGISTER_OFFSET > SH_ETH_REG_DUMP_MAX_REGS);
1985 /* Dump starts with a bitmap that tells ethtool which
1986 * registers are defined for this chip.
1988 len = DIV_ROUND_UP(SH_ETH_REG_DUMP_MAX_REGS, 32);
1996 /* Add a register to the dump, if it has a defined offset.
1997 * This automatically skips most undefined registers, but for
1998 * some it is also necessary to check a capability flag in
1999 * struct sh_eth_cpu_data.
2001 #define mark_reg_valid(reg) valid_map[reg / 32] |= 1U << (reg % 32)
2002 #define add_reg_from(reg, read_expr) do { \
2003 if (mdp->reg_offset[reg] != SH_ETH_OFFSET_INVALID) { \
2005 mark_reg_valid(reg); \
2006 *buf++ = read_expr; \
2011 #define add_reg(reg) add_reg_from(reg, sh_eth_read(ndev, reg))
2012 #define add_tsu_reg(reg) add_reg_from(reg, sh_eth_tsu_read(mdp, reg))
2078 if (cd->hw_checksum)
2084 add_tsu_reg(TSU_CTRST);
2085 add_tsu_reg(TSU_FWEN0);
2086 add_tsu_reg(TSU_FWEN1);
2087 add_tsu_reg(TSU_FCM);
2088 add_tsu_reg(TSU_BSYSL0);
2089 add_tsu_reg(TSU_BSYSL1);
2090 add_tsu_reg(TSU_PRISL0);
2091 add_tsu_reg(TSU_PRISL1);
2092 add_tsu_reg(TSU_FWSL0);
2093 add_tsu_reg(TSU_FWSL1);
2094 add_tsu_reg(TSU_FWSLC);
2095 add_tsu_reg(TSU_QTAG0);
2096 add_tsu_reg(TSU_QTAG1);
2097 add_tsu_reg(TSU_QTAGM0);
2098 add_tsu_reg(TSU_QTAGM1);
2099 add_tsu_reg(TSU_FWSR);
2100 add_tsu_reg(TSU_FWINMK);
2101 add_tsu_reg(TSU_ADQT0);
2102 add_tsu_reg(TSU_ADQT1);
2103 add_tsu_reg(TSU_VTAG0);
2104 add_tsu_reg(TSU_VTAG1);
2105 add_tsu_reg(TSU_ADSBSY);
2106 add_tsu_reg(TSU_TEN);
2107 add_tsu_reg(TSU_POST1);
2108 add_tsu_reg(TSU_POST2);
2109 add_tsu_reg(TSU_POST3);
2110 add_tsu_reg(TSU_POST4);
2111 if (mdp->reg_offset[TSU_ADRH0] != SH_ETH_OFFSET_INVALID) {
2112 /* This is the start of a table, not just a single
2118 mark_reg_valid(TSU_ADRH0);
2119 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES * 2; i++)
2122 mdp->reg_offset[TSU_ADRH0] +
2125 len += SH_ETH_TSU_CAM_ENTRIES * 2;
2129 #undef mark_reg_valid
2137 static int sh_eth_get_regs_len(struct net_device *ndev)
2139 return __sh_eth_get_regs(ndev, NULL);
2142 static void sh_eth_get_regs(struct net_device *ndev, struct ethtool_regs *regs,
2145 struct sh_eth_private *mdp = netdev_priv(ndev);
2147 regs->version = SH_ETH_REG_DUMP_VERSION;
2149 pm_runtime_get_sync(&mdp->pdev->dev);
2150 __sh_eth_get_regs(ndev, buf);
2151 pm_runtime_put_sync(&mdp->pdev->dev);
2154 static int sh_eth_nway_reset(struct net_device *ndev)
2156 struct sh_eth_private *mdp = netdev_priv(ndev);
2157 unsigned long flags;
2163 spin_lock_irqsave(&mdp->lock, flags);
2164 ret = phy_start_aneg(ndev->phydev);
2165 spin_unlock_irqrestore(&mdp->lock, flags);
2170 static u32 sh_eth_get_msglevel(struct net_device *ndev)
2172 struct sh_eth_private *mdp = netdev_priv(ndev);
2173 return mdp->msg_enable;
2176 static void sh_eth_set_msglevel(struct net_device *ndev, u32 value)
2178 struct sh_eth_private *mdp = netdev_priv(ndev);
2179 mdp->msg_enable = value;
2182 static const char sh_eth_gstrings_stats[][ETH_GSTRING_LEN] = {
2183 "rx_current", "tx_current",
2184 "rx_dirty", "tx_dirty",
2186 #define SH_ETH_STATS_LEN ARRAY_SIZE(sh_eth_gstrings_stats)
2188 static int sh_eth_get_sset_count(struct net_device *netdev, int sset)
2192 return SH_ETH_STATS_LEN;
2198 static void sh_eth_get_ethtool_stats(struct net_device *ndev,
2199 struct ethtool_stats *stats, u64 *data)
2201 struct sh_eth_private *mdp = netdev_priv(ndev);
2204 /* device-specific stats */
2205 data[i++] = mdp->cur_rx;
2206 data[i++] = mdp->cur_tx;
2207 data[i++] = mdp->dirty_rx;
2208 data[i++] = mdp->dirty_tx;
2211 static void sh_eth_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
2213 switch (stringset) {
2215 memcpy(data, *sh_eth_gstrings_stats,
2216 sizeof(sh_eth_gstrings_stats));
2221 static void sh_eth_get_ringparam(struct net_device *ndev,
2222 struct ethtool_ringparam *ring)
2224 struct sh_eth_private *mdp = netdev_priv(ndev);
2226 ring->rx_max_pending = RX_RING_MAX;
2227 ring->tx_max_pending = TX_RING_MAX;
2228 ring->rx_pending = mdp->num_rx_ring;
2229 ring->tx_pending = mdp->num_tx_ring;
2232 static int sh_eth_set_ringparam(struct net_device *ndev,
2233 struct ethtool_ringparam *ring)
2235 struct sh_eth_private *mdp = netdev_priv(ndev);
2238 if (ring->tx_pending > TX_RING_MAX ||
2239 ring->rx_pending > RX_RING_MAX ||
2240 ring->tx_pending < TX_RING_MIN ||
2241 ring->rx_pending < RX_RING_MIN)
2243 if (ring->rx_mini_pending || ring->rx_jumbo_pending)
2246 if (netif_running(ndev)) {
2247 netif_device_detach(ndev);
2248 netif_tx_disable(ndev);
2250 /* Serialise with the interrupt handler and NAPI, then
2251 * disable interrupts. We have to clear the
2252 * irq_enabled flag first to ensure that interrupts
2253 * won't be re-enabled.
2255 mdp->irq_enabled = false;
2256 synchronize_irq(ndev->irq);
2257 napi_synchronize(&mdp->napi);
2258 sh_eth_write(ndev, 0x0000, EESIPR);
2260 sh_eth_dev_exit(ndev);
2262 /* Free all the skbuffs in the Rx queue and the DMA buffers. */
2263 sh_eth_ring_free(ndev);
2266 /* Set new parameters */
2267 mdp->num_rx_ring = ring->rx_pending;
2268 mdp->num_tx_ring = ring->tx_pending;
2270 if (netif_running(ndev)) {
2271 ret = sh_eth_ring_init(ndev);
2273 netdev_err(ndev, "%s: sh_eth_ring_init failed.\n",
2277 ret = sh_eth_dev_init(ndev);
2279 netdev_err(ndev, "%s: sh_eth_dev_init failed.\n",
2284 netif_device_attach(ndev);
2290 static void sh_eth_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
2292 struct sh_eth_private *mdp = netdev_priv(ndev);
2297 if (mdp->cd->magic && mdp->clk) {
2298 wol->supported = WAKE_MAGIC;
2299 wol->wolopts = mdp->wol_enabled ? WAKE_MAGIC : 0;
2303 static int sh_eth_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
2305 struct sh_eth_private *mdp = netdev_priv(ndev);
2307 if (!mdp->cd->magic || !mdp->clk || wol->wolopts & ~WAKE_MAGIC)
2310 mdp->wol_enabled = !!(wol->wolopts & WAKE_MAGIC);
2312 device_set_wakeup_enable(&mdp->pdev->dev, mdp->wol_enabled);
2317 static const struct ethtool_ops sh_eth_ethtool_ops = {
2318 .get_regs_len = sh_eth_get_regs_len,
2319 .get_regs = sh_eth_get_regs,
2320 .nway_reset = sh_eth_nway_reset,
2321 .get_msglevel = sh_eth_get_msglevel,
2322 .set_msglevel = sh_eth_set_msglevel,
2323 .get_link = ethtool_op_get_link,
2324 .get_strings = sh_eth_get_strings,
2325 .get_ethtool_stats = sh_eth_get_ethtool_stats,
2326 .get_sset_count = sh_eth_get_sset_count,
2327 .get_ringparam = sh_eth_get_ringparam,
2328 .set_ringparam = sh_eth_set_ringparam,
2329 .get_link_ksettings = sh_eth_get_link_ksettings,
2330 .set_link_ksettings = sh_eth_set_link_ksettings,
2331 .get_wol = sh_eth_get_wol,
2332 .set_wol = sh_eth_set_wol,
2335 /* network device open function */
2336 static int sh_eth_open(struct net_device *ndev)
2338 struct sh_eth_private *mdp = netdev_priv(ndev);
2341 pm_runtime_get_sync(&mdp->pdev->dev);
2343 napi_enable(&mdp->napi);
2345 ret = request_irq(ndev->irq, sh_eth_interrupt,
2346 mdp->cd->irq_flags, ndev->name, ndev);
2348 netdev_err(ndev, "Can not assign IRQ number\n");
2352 /* Descriptor set */
2353 ret = sh_eth_ring_init(ndev);
2358 ret = sh_eth_dev_init(ndev);
2362 /* PHY control start*/
2363 ret = sh_eth_phy_start(ndev);
2367 netif_start_queue(ndev);
2374 free_irq(ndev->irq, ndev);
2376 napi_disable(&mdp->napi);
2377 pm_runtime_put_sync(&mdp->pdev->dev);
2381 /* Timeout function */
2382 static void sh_eth_tx_timeout(struct net_device *ndev)
2384 struct sh_eth_private *mdp = netdev_priv(ndev);
2385 struct sh_eth_rxdesc *rxdesc;
2388 netif_stop_queue(ndev);
2390 netif_err(mdp, timer, ndev,
2391 "transmit timed out, status %8.8x, resetting...\n",
2392 sh_eth_read(ndev, EESR));
2394 /* tx_errors count up */
2395 ndev->stats.tx_errors++;
2397 /* Free all the skbuffs in the Rx queue. */
2398 for (i = 0; i < mdp->num_rx_ring; i++) {
2399 rxdesc = &mdp->rx_ring[i];
2400 rxdesc->status = cpu_to_le32(0);
2401 rxdesc->addr = cpu_to_le32(0xBADF00D0);
2402 dev_kfree_skb(mdp->rx_skbuff[i]);
2403 mdp->rx_skbuff[i] = NULL;
2405 for (i = 0; i < mdp->num_tx_ring; i++) {
2406 dev_kfree_skb(mdp->tx_skbuff[i]);
2407 mdp->tx_skbuff[i] = NULL;
2411 sh_eth_dev_init(ndev);
2413 netif_start_queue(ndev);
2416 /* Packet transmit function */
2417 static int sh_eth_start_xmit(struct sk_buff *skb, struct net_device *ndev)
2419 struct sh_eth_private *mdp = netdev_priv(ndev);
2420 struct sh_eth_txdesc *txdesc;
2421 dma_addr_t dma_addr;
2423 unsigned long flags;
2425 spin_lock_irqsave(&mdp->lock, flags);
2426 if ((mdp->cur_tx - mdp->dirty_tx) >= (mdp->num_tx_ring - 4)) {
2427 if (!sh_eth_tx_free(ndev, true)) {
2428 netif_warn(mdp, tx_queued, ndev, "TxFD exhausted.\n");
2429 netif_stop_queue(ndev);
2430 spin_unlock_irqrestore(&mdp->lock, flags);
2431 return NETDEV_TX_BUSY;
2434 spin_unlock_irqrestore(&mdp->lock, flags);
2436 if (skb_put_padto(skb, ETH_ZLEN))
2437 return NETDEV_TX_OK;
2439 entry = mdp->cur_tx % mdp->num_tx_ring;
2440 mdp->tx_skbuff[entry] = skb;
2441 txdesc = &mdp->tx_ring[entry];
2443 if (!mdp->cd->hw_swap)
2444 sh_eth_soft_swap(PTR_ALIGN(skb->data, 4), skb->len + 2);
2445 dma_addr = dma_map_single(&ndev->dev, skb->data, skb->len,
2447 if (dma_mapping_error(&ndev->dev, dma_addr)) {
2449 return NETDEV_TX_OK;
2451 txdesc->addr = cpu_to_le32(dma_addr);
2452 txdesc->len = cpu_to_le32(skb->len << 16);
2454 dma_wmb(); /* TACT bit must be set after all the above writes */
2455 if (entry >= mdp->num_tx_ring - 1)
2456 txdesc->status |= cpu_to_le32(TD_TACT | TD_TDLE);
2458 txdesc->status |= cpu_to_le32(TD_TACT);
2462 if (!(sh_eth_read(ndev, EDTRR) & sh_eth_get_edtrr_trns(mdp)))
2463 sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
2465 return NETDEV_TX_OK;
2468 /* The statistics registers have write-clear behaviour, which means we
2469 * will lose any increment between the read and write. We mitigate
2470 * this by only clearing when we read a non-zero value, so we will
2471 * never falsely report a total of zero.
2474 sh_eth_update_stat(struct net_device *ndev, unsigned long *stat, int reg)
2476 u32 delta = sh_eth_read(ndev, reg);
2480 sh_eth_write(ndev, 0, reg);
2484 static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev)
2486 struct sh_eth_private *mdp = netdev_priv(ndev);
2488 if (sh_eth_is_rz_fast_ether(mdp))
2489 return &ndev->stats;
2491 if (!mdp->is_opened)
2492 return &ndev->stats;
2494 sh_eth_update_stat(ndev, &ndev->stats.tx_dropped, TROCR);
2495 sh_eth_update_stat(ndev, &ndev->stats.collisions, CDCR);
2496 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors, LCCR);
2498 if (sh_eth_is_gether(mdp)) {
2499 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,
2501 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,
2504 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,
2508 return &ndev->stats;
2511 /* device close function */
2512 static int sh_eth_close(struct net_device *ndev)
2514 struct sh_eth_private *mdp = netdev_priv(ndev);
2516 netif_stop_queue(ndev);
2518 /* Serialise with the interrupt handler and NAPI, then disable
2519 * interrupts. We have to clear the irq_enabled flag first to
2520 * ensure that interrupts won't be re-enabled.
2522 mdp->irq_enabled = false;
2523 synchronize_irq(ndev->irq);
2524 napi_disable(&mdp->napi);
2525 sh_eth_write(ndev, 0x0000, EESIPR);
2527 sh_eth_dev_exit(ndev);
2529 /* PHY Disconnect */
2531 phy_stop(ndev->phydev);
2532 phy_disconnect(ndev->phydev);
2535 free_irq(ndev->irq, ndev);
2537 /* Free all the skbuffs in the Rx queue and the DMA buffer. */
2538 sh_eth_ring_free(ndev);
2540 pm_runtime_put_sync(&mdp->pdev->dev);
2547 /* ioctl to device function */
2548 static int sh_eth_do_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
2550 struct phy_device *phydev = ndev->phydev;
2552 if (!netif_running(ndev))
2558 return phy_mii_ioctl(phydev, rq, cmd);
2561 /* For TSU_POSTn. Please refer to the manual about this (strange) bitfields */
2562 static void *sh_eth_tsu_get_post_reg_offset(struct sh_eth_private *mdp,
2565 return sh_eth_tsu_get_offset(mdp, TSU_POST1) + (entry / 8 * 4);
2568 static u32 sh_eth_tsu_get_post_mask(int entry)
2570 return 0x0f << (28 - ((entry % 8) * 4));
2573 static u32 sh_eth_tsu_get_post_bit(struct sh_eth_private *mdp, int entry)
2575 return (0x08 >> (mdp->port << 1)) << (28 - ((entry % 8) * 4));
2578 static void sh_eth_tsu_enable_cam_entry_post(struct net_device *ndev,
2581 struct sh_eth_private *mdp = netdev_priv(ndev);
2585 reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
2586 tmp = ioread32(reg_offset);
2587 iowrite32(tmp | sh_eth_tsu_get_post_bit(mdp, entry), reg_offset);
2590 static bool sh_eth_tsu_disable_cam_entry_post(struct net_device *ndev,
2593 struct sh_eth_private *mdp = netdev_priv(ndev);
2594 u32 post_mask, ref_mask, tmp;
2597 reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
2598 post_mask = sh_eth_tsu_get_post_mask(entry);
2599 ref_mask = sh_eth_tsu_get_post_bit(mdp, entry) & ~post_mask;
2601 tmp = ioread32(reg_offset);
2602 iowrite32(tmp & ~post_mask, reg_offset);
2604 /* If other port enables, the function returns "true" */
2605 return tmp & ref_mask;
2608 static int sh_eth_tsu_busy(struct net_device *ndev)
2610 int timeout = SH_ETH_TSU_TIMEOUT_MS * 100;
2611 struct sh_eth_private *mdp = netdev_priv(ndev);
2613 while ((sh_eth_tsu_read(mdp, TSU_ADSBSY) & TSU_ADSBSY_0)) {
2617 netdev_err(ndev, "%s: timeout\n", __func__);
2625 static int sh_eth_tsu_write_entry(struct net_device *ndev, void *reg,
2630 val = addr[0] << 24 | addr[1] << 16 | addr[2] << 8 | addr[3];
2631 iowrite32(val, reg);
2632 if (sh_eth_tsu_busy(ndev) < 0)
2635 val = addr[4] << 8 | addr[5];
2636 iowrite32(val, reg + 4);
2637 if (sh_eth_tsu_busy(ndev) < 0)
2643 static void sh_eth_tsu_read_entry(void *reg, u8 *addr)
2647 val = ioread32(reg);
2648 addr[0] = (val >> 24) & 0xff;
2649 addr[1] = (val >> 16) & 0xff;
2650 addr[2] = (val >> 8) & 0xff;
2651 addr[3] = val & 0xff;
2652 val = ioread32(reg + 4);
2653 addr[4] = (val >> 8) & 0xff;
2654 addr[5] = val & 0xff;
2658 static int sh_eth_tsu_find_entry(struct net_device *ndev, const u8 *addr)
2660 struct sh_eth_private *mdp = netdev_priv(ndev);
2661 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2663 u8 c_addr[ETH_ALEN];
2665 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2666 sh_eth_tsu_read_entry(reg_offset, c_addr);
2667 if (ether_addr_equal(addr, c_addr))
2674 static int sh_eth_tsu_find_empty(struct net_device *ndev)
2679 memset(blank, 0, sizeof(blank));
2680 entry = sh_eth_tsu_find_entry(ndev, blank);
2681 return (entry < 0) ? -ENOMEM : entry;
2684 static int sh_eth_tsu_disable_cam_entry_table(struct net_device *ndev,
2687 struct sh_eth_private *mdp = netdev_priv(ndev);
2688 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2692 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) &
2693 ~(1 << (31 - entry)), TSU_TEN);
2695 memset(blank, 0, sizeof(blank));
2696 ret = sh_eth_tsu_write_entry(ndev, reg_offset + entry * 8, blank);
2702 static int sh_eth_tsu_add_entry(struct net_device *ndev, const u8 *addr)
2704 struct sh_eth_private *mdp = netdev_priv(ndev);
2705 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2711 i = sh_eth_tsu_find_entry(ndev, addr);
2713 /* No entry found, create one */
2714 i = sh_eth_tsu_find_empty(ndev);
2717 ret = sh_eth_tsu_write_entry(ndev, reg_offset + i * 8, addr);
2721 /* Enable the entry */
2722 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) |
2723 (1 << (31 - i)), TSU_TEN);
2726 /* Entry found or created, enable POST */
2727 sh_eth_tsu_enable_cam_entry_post(ndev, i);
2732 static int sh_eth_tsu_del_entry(struct net_device *ndev, const u8 *addr)
2734 struct sh_eth_private *mdp = netdev_priv(ndev);
2740 i = sh_eth_tsu_find_entry(ndev, addr);
2743 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2746 /* Disable the entry if both ports was disabled */
2747 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2755 static int sh_eth_tsu_purge_all(struct net_device *ndev)
2757 struct sh_eth_private *mdp = netdev_priv(ndev);
2763 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++) {
2764 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2767 /* Disable the entry if both ports was disabled */
2768 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2776 static void sh_eth_tsu_purge_mcast(struct net_device *ndev)
2778 struct sh_eth_private *mdp = netdev_priv(ndev);
2780 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2786 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2787 sh_eth_tsu_read_entry(reg_offset, addr);
2788 if (is_multicast_ether_addr(addr))
2789 sh_eth_tsu_del_entry(ndev, addr);
2793 /* Update promiscuous flag and multicast filter */
2794 static void sh_eth_set_rx_mode(struct net_device *ndev)
2796 struct sh_eth_private *mdp = netdev_priv(ndev);
2799 unsigned long flags;
2801 spin_lock_irqsave(&mdp->lock, flags);
2802 /* Initial condition is MCT = 1, PRM = 0.
2803 * Depending on ndev->flags, set PRM or clear MCT
2805 ecmr_bits = sh_eth_read(ndev, ECMR) & ~ECMR_PRM;
2807 ecmr_bits |= ECMR_MCT;
2809 if (!(ndev->flags & IFF_MULTICAST)) {
2810 sh_eth_tsu_purge_mcast(ndev);
2813 if (ndev->flags & IFF_ALLMULTI) {
2814 sh_eth_tsu_purge_mcast(ndev);
2815 ecmr_bits &= ~ECMR_MCT;
2819 if (ndev->flags & IFF_PROMISC) {
2820 sh_eth_tsu_purge_all(ndev);
2821 ecmr_bits = (ecmr_bits & ~ECMR_MCT) | ECMR_PRM;
2822 } else if (mdp->cd->tsu) {
2823 struct netdev_hw_addr *ha;
2824 netdev_for_each_mc_addr(ha, ndev) {
2825 if (mcast_all && is_multicast_ether_addr(ha->addr))
2828 if (sh_eth_tsu_add_entry(ndev, ha->addr) < 0) {
2830 sh_eth_tsu_purge_mcast(ndev);
2831 ecmr_bits &= ~ECMR_MCT;
2838 /* update the ethernet mode */
2839 sh_eth_write(ndev, ecmr_bits, ECMR);
2841 spin_unlock_irqrestore(&mdp->lock, flags);
2844 static int sh_eth_get_vtag_index(struct sh_eth_private *mdp)
2852 static int sh_eth_vlan_rx_add_vid(struct net_device *ndev,
2853 __be16 proto, u16 vid)
2855 struct sh_eth_private *mdp = netdev_priv(ndev);
2856 int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2858 if (unlikely(!mdp->cd->tsu))
2861 /* No filtering if vid = 0 */
2865 mdp->vlan_num_ids++;
2867 /* The controller has one VLAN tag HW filter. So, if the filter is
2868 * already enabled, the driver disables it and the filte
2870 if (mdp->vlan_num_ids > 1) {
2871 /* disable VLAN filter */
2872 sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2876 sh_eth_tsu_write(mdp, TSU_VTAG_ENABLE | (vid & TSU_VTAG_VID_MASK),
2882 static int sh_eth_vlan_rx_kill_vid(struct net_device *ndev,
2883 __be16 proto, u16 vid)
2885 struct sh_eth_private *mdp = netdev_priv(ndev);
2886 int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2888 if (unlikely(!mdp->cd->tsu))
2891 /* No filtering if vid = 0 */
2895 mdp->vlan_num_ids--;
2896 sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2901 /* SuperH's TSU register init function */
2902 static void sh_eth_tsu_init(struct sh_eth_private *mdp)
2904 if (sh_eth_is_rz_fast_ether(mdp)) {
2905 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */
2906 sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL,
2907 TSU_FWSLC); /* Enable POST registers */
2911 sh_eth_tsu_write(mdp, 0, TSU_FWEN0); /* Disable forward(0->1) */
2912 sh_eth_tsu_write(mdp, 0, TSU_FWEN1); /* Disable forward(1->0) */
2913 sh_eth_tsu_write(mdp, 0, TSU_FCM); /* forward fifo 3k-3k */
2914 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL0);
2915 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL1);
2916 sh_eth_tsu_write(mdp, 0, TSU_PRISL0);
2917 sh_eth_tsu_write(mdp, 0, TSU_PRISL1);
2918 sh_eth_tsu_write(mdp, 0, TSU_FWSL0);
2919 sh_eth_tsu_write(mdp, 0, TSU_FWSL1);
2920 sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, TSU_FWSLC);
2921 if (sh_eth_is_gether(mdp)) {
2922 sh_eth_tsu_write(mdp, 0, TSU_QTAG0); /* Disable QTAG(0->1) */
2923 sh_eth_tsu_write(mdp, 0, TSU_QTAG1); /* Disable QTAG(1->0) */
2925 sh_eth_tsu_write(mdp, 0, TSU_QTAGM0); /* Disable QTAG(0->1) */
2926 sh_eth_tsu_write(mdp, 0, TSU_QTAGM1); /* Disable QTAG(1->0) */
2928 sh_eth_tsu_write(mdp, 0, TSU_FWSR); /* all interrupt status clear */
2929 sh_eth_tsu_write(mdp, 0, TSU_FWINMK); /* Disable all interrupt */
2930 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */
2931 sh_eth_tsu_write(mdp, 0, TSU_POST1); /* Disable CAM entry [ 0- 7] */
2932 sh_eth_tsu_write(mdp, 0, TSU_POST2); /* Disable CAM entry [ 8-15] */
2933 sh_eth_tsu_write(mdp, 0, TSU_POST3); /* Disable CAM entry [16-23] */
2934 sh_eth_tsu_write(mdp, 0, TSU_POST4); /* Disable CAM entry [24-31] */
2937 /* MDIO bus release function */
2938 static int sh_mdio_release(struct sh_eth_private *mdp)
2940 /* unregister mdio bus */
2941 mdiobus_unregister(mdp->mii_bus);
2943 /* free bitbang info */
2944 free_mdio_bitbang(mdp->mii_bus);
2949 /* MDIO bus init function */
2950 static int sh_mdio_init(struct sh_eth_private *mdp,
2951 struct sh_eth_plat_data *pd)
2954 struct bb_info *bitbang;
2955 struct platform_device *pdev = mdp->pdev;
2956 struct device *dev = &mdp->pdev->dev;
2958 /* create bit control struct for PHY */
2959 bitbang = devm_kzalloc(dev, sizeof(struct bb_info), GFP_KERNEL);
2964 bitbang->addr = mdp->addr + mdp->reg_offset[PIR];
2965 bitbang->set_gate = pd->set_mdio_gate;
2966 bitbang->ctrl.ops = &bb_ops;
2968 /* MII controller setting */
2969 mdp->mii_bus = alloc_mdio_bitbang(&bitbang->ctrl);
2973 /* Hook up MII support for ethtool */
2974 mdp->mii_bus->name = "sh_mii";
2975 mdp->mii_bus->parent = dev;
2976 snprintf(mdp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
2977 pdev->name, pdev->id);
2979 /* register MDIO bus */
2981 ret = of_mdiobus_register(mdp->mii_bus, dev->of_node);
2983 if (pd->phy_irq > 0)
2984 mdp->mii_bus->irq[pd->phy] = pd->phy_irq;
2986 ret = mdiobus_register(mdp->mii_bus);
2995 free_mdio_bitbang(mdp->mii_bus);
2999 static const u16 *sh_eth_get_register_offset(int register_type)
3001 const u16 *reg_offset = NULL;
3003 switch (register_type) {
3004 case SH_ETH_REG_GIGABIT:
3005 reg_offset = sh_eth_offset_gigabit;
3007 case SH_ETH_REG_FAST_RZ:
3008 reg_offset = sh_eth_offset_fast_rz;
3010 case SH_ETH_REG_FAST_RCAR:
3011 reg_offset = sh_eth_offset_fast_rcar;
3013 case SH_ETH_REG_FAST_SH4:
3014 reg_offset = sh_eth_offset_fast_sh4;
3016 case SH_ETH_REG_FAST_SH3_SH2:
3017 reg_offset = sh_eth_offset_fast_sh3_sh2;
3024 static const struct net_device_ops sh_eth_netdev_ops = {
3025 .ndo_open = sh_eth_open,
3026 .ndo_stop = sh_eth_close,
3027 .ndo_start_xmit = sh_eth_start_xmit,
3028 .ndo_get_stats = sh_eth_get_stats,
3029 .ndo_set_rx_mode = sh_eth_set_rx_mode,
3030 .ndo_tx_timeout = sh_eth_tx_timeout,
3031 .ndo_do_ioctl = sh_eth_do_ioctl,
3032 .ndo_validate_addr = eth_validate_addr,
3033 .ndo_set_mac_address = eth_mac_addr,
3036 static const struct net_device_ops sh_eth_netdev_ops_tsu = {
3037 .ndo_open = sh_eth_open,
3038 .ndo_stop = sh_eth_close,
3039 .ndo_start_xmit = sh_eth_start_xmit,
3040 .ndo_get_stats = sh_eth_get_stats,
3041 .ndo_set_rx_mode = sh_eth_set_rx_mode,
3042 .ndo_vlan_rx_add_vid = sh_eth_vlan_rx_add_vid,
3043 .ndo_vlan_rx_kill_vid = sh_eth_vlan_rx_kill_vid,
3044 .ndo_tx_timeout = sh_eth_tx_timeout,
3045 .ndo_do_ioctl = sh_eth_do_ioctl,
3046 .ndo_validate_addr = eth_validate_addr,
3047 .ndo_set_mac_address = eth_mac_addr,
3051 static struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev)
3053 struct device_node *np = dev->of_node;
3054 struct sh_eth_plat_data *pdata;
3055 const char *mac_addr;
3057 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
3061 pdata->phy_interface = of_get_phy_mode(np);
3063 mac_addr = of_get_mac_address(np);
3065 memcpy(pdata->mac_addr, mac_addr, ETH_ALEN);
3067 pdata->no_ether_link =
3068 of_property_read_bool(np, "renesas,no-ether-link");
3069 pdata->ether_link_active_low =
3070 of_property_read_bool(np, "renesas,ether-link-active-low");
3075 static const struct of_device_id sh_eth_match_table[] = {
3076 { .compatible = "renesas,gether-r8a7740", .data = &r8a7740_data },
3077 { .compatible = "renesas,ether-r8a7743", .data = &r8a779x_data },
3078 { .compatible = "renesas,ether-r8a7745", .data = &r8a779x_data },
3079 { .compatible = "renesas,ether-r8a7778", .data = &r8a777x_data },
3080 { .compatible = "renesas,ether-r8a7779", .data = &r8a777x_data },
3081 { .compatible = "renesas,ether-r8a7790", .data = &r8a779x_data },
3082 { .compatible = "renesas,ether-r8a7791", .data = &r8a779x_data },
3083 { .compatible = "renesas,ether-r8a7793", .data = &r8a779x_data },
3084 { .compatible = "renesas,ether-r8a7794", .data = &r8a779x_data },
3085 { .compatible = "renesas,ether-r7s72100", .data = &r7s72100_data },
3088 MODULE_DEVICE_TABLE(of, sh_eth_match_table);
3090 static inline struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev)
3096 static int sh_eth_drv_probe(struct platform_device *pdev)
3098 struct resource *res;
3099 struct sh_eth_plat_data *pd = dev_get_platdata(&pdev->dev);
3100 const struct platform_device_id *id = platform_get_device_id(pdev);
3101 struct sh_eth_private *mdp;
3102 struct net_device *ndev;
3106 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3108 ndev = alloc_etherdev(sizeof(struct sh_eth_private));
3112 pm_runtime_enable(&pdev->dev);
3113 pm_runtime_get_sync(&pdev->dev);
3119 ret = platform_get_irq(pdev, 0);
3124 SET_NETDEV_DEV(ndev, &pdev->dev);
3126 mdp = netdev_priv(ndev);
3127 mdp->num_tx_ring = TX_RING_SIZE;
3128 mdp->num_rx_ring = RX_RING_SIZE;
3129 mdp->addr = devm_ioremap_resource(&pdev->dev, res);
3130 if (IS_ERR(mdp->addr)) {
3131 ret = PTR_ERR(mdp->addr);
3135 /* Get clock, if not found that's OK but Wake-On-Lan is unavailable */
3136 mdp->clk = devm_clk_get(&pdev->dev, NULL);
3137 if (IS_ERR(mdp->clk))
3140 ndev->base_addr = res->start;
3142 spin_lock_init(&mdp->lock);
3145 if (pdev->dev.of_node)
3146 pd = sh_eth_parse_dt(&pdev->dev);
3148 dev_err(&pdev->dev, "no platform data\n");
3154 mdp->phy_id = pd->phy;
3155 mdp->phy_interface = pd->phy_interface;
3156 mdp->no_ether_link = pd->no_ether_link;
3157 mdp->ether_link_active_low = pd->ether_link_active_low;
3161 mdp->cd = (struct sh_eth_cpu_data *)id->driver_data;
3163 mdp->cd = (struct sh_eth_cpu_data *)of_device_get_match_data(&pdev->dev);
3165 mdp->reg_offset = sh_eth_get_register_offset(mdp->cd->register_type);
3166 if (!mdp->reg_offset) {
3167 dev_err(&pdev->dev, "Unknown register type (%d)\n",
3168 mdp->cd->register_type);
3172 sh_eth_set_default_cpu_data(mdp->cd);
3176 ndev->netdev_ops = &sh_eth_netdev_ops_tsu;
3178 ndev->netdev_ops = &sh_eth_netdev_ops;
3179 ndev->ethtool_ops = &sh_eth_ethtool_ops;
3180 ndev->watchdog_timeo = TX_TIMEOUT;
3182 /* debug message level */
3183 mdp->msg_enable = SH_ETH_DEF_MSG_ENABLE;
3185 /* read and set MAC address */
3186 read_mac_address(ndev, pd->mac_addr);
3187 if (!is_valid_ether_addr(ndev->dev_addr)) {
3188 dev_warn(&pdev->dev,
3189 "no valid MAC address supplied, using a random one.\n");
3190 eth_hw_addr_random(ndev);
3193 /* ioremap the TSU registers */
3195 struct resource *rtsu;
3196 rtsu = platform_get_resource(pdev, IORESOURCE_MEM, 1);
3197 mdp->tsu_addr = devm_ioremap_resource(&pdev->dev, rtsu);
3198 if (IS_ERR(mdp->tsu_addr)) {
3199 ret = PTR_ERR(mdp->tsu_addr);
3202 mdp->port = devno % 2;
3203 ndev->features = NETIF_F_HW_VLAN_CTAG_FILTER;
3206 /* initialize first or needed device */
3207 if (!devno || pd->needs_init) {
3208 if (mdp->cd->chip_reset)
3209 mdp->cd->chip_reset(ndev);
3212 /* TSU init (Init only)*/
3213 sh_eth_tsu_init(mdp);
3217 if (mdp->cd->rmiimode)
3218 sh_eth_write(ndev, 0x1, RMIIMODE);
3221 ret = sh_mdio_init(mdp, pd);
3223 dev_err(&ndev->dev, "failed to initialise MDIO\n");
3227 netif_napi_add(ndev, &mdp->napi, sh_eth_poll, 64);
3229 /* network device register */
3230 ret = register_netdev(ndev);
3234 if (mdp->cd->magic && mdp->clk)
3235 device_set_wakeup_capable(&pdev->dev, 1);
3237 /* print device information */
3238 netdev_info(ndev, "Base address at 0x%x, %pM, IRQ %d.\n",
3239 (u32)ndev->base_addr, ndev->dev_addr, ndev->irq);
3241 pm_runtime_put(&pdev->dev);
3242 platform_set_drvdata(pdev, ndev);
3247 netif_napi_del(&mdp->napi);
3248 sh_mdio_release(mdp);
3255 pm_runtime_put(&pdev->dev);
3256 pm_runtime_disable(&pdev->dev);
3260 static int sh_eth_drv_remove(struct platform_device *pdev)
3262 struct net_device *ndev = platform_get_drvdata(pdev);
3263 struct sh_eth_private *mdp = netdev_priv(ndev);
3265 unregister_netdev(ndev);
3266 netif_napi_del(&mdp->napi);
3267 sh_mdio_release(mdp);
3268 pm_runtime_disable(&pdev->dev);
3275 #ifdef CONFIG_PM_SLEEP
3276 static int sh_eth_wol_setup(struct net_device *ndev)
3278 struct sh_eth_private *mdp = netdev_priv(ndev);
3280 /* Only allow ECI interrupts */
3281 synchronize_irq(ndev->irq);
3282 napi_disable(&mdp->napi);
3283 sh_eth_write(ndev, EESIPR_ECIIP, EESIPR);
3285 /* Enable MagicPacket */
3286 sh_eth_modify(ndev, ECMR, ECMR_MPDE, ECMR_MPDE);
3288 /* Increased clock usage so device won't be suspended */
3289 clk_enable(mdp->clk);
3291 return enable_irq_wake(ndev->irq);
3294 static int sh_eth_wol_restore(struct net_device *ndev)
3296 struct sh_eth_private *mdp = netdev_priv(ndev);
3299 napi_enable(&mdp->napi);
3301 /* Disable MagicPacket */
3302 sh_eth_modify(ndev, ECMR, ECMR_MPDE, 0);
3304 /* The device needs to be reset to restore MagicPacket logic
3305 * for next wakeup. If we close and open the device it will
3306 * both be reset and all registers restored. This is what
3307 * happens during suspend and resume without WoL enabled.
3309 ret = sh_eth_close(ndev);
3312 ret = sh_eth_open(ndev);
3316 /* Restore clock usage count */
3317 clk_disable(mdp->clk);
3319 return disable_irq_wake(ndev->irq);
3322 static int sh_eth_suspend(struct device *dev)
3324 struct net_device *ndev = dev_get_drvdata(dev);
3325 struct sh_eth_private *mdp = netdev_priv(ndev);
3328 if (!netif_running(ndev))
3331 netif_device_detach(ndev);
3333 if (mdp->wol_enabled)
3334 ret = sh_eth_wol_setup(ndev);
3336 ret = sh_eth_close(ndev);
3341 static int sh_eth_resume(struct device *dev)
3343 struct net_device *ndev = dev_get_drvdata(dev);
3344 struct sh_eth_private *mdp = netdev_priv(ndev);
3347 if (!netif_running(ndev))
3350 if (mdp->wol_enabled)
3351 ret = sh_eth_wol_restore(ndev);
3353 ret = sh_eth_open(ndev);
3358 netif_device_attach(ndev);
3364 static int sh_eth_runtime_nop(struct device *dev)
3366 /* Runtime PM callback shared between ->runtime_suspend()
3367 * and ->runtime_resume(). Simply returns success.
3369 * This driver re-initializes all registers after
3370 * pm_runtime_get_sync() anyway so there is no need
3371 * to save and restore registers here.
3376 static const struct dev_pm_ops sh_eth_dev_pm_ops = {
3377 SET_SYSTEM_SLEEP_PM_OPS(sh_eth_suspend, sh_eth_resume)
3378 SET_RUNTIME_PM_OPS(sh_eth_runtime_nop, sh_eth_runtime_nop, NULL)
3380 #define SH_ETH_PM_OPS (&sh_eth_dev_pm_ops)
3382 #define SH_ETH_PM_OPS NULL
3385 static struct platform_device_id sh_eth_id_table[] = {
3386 { "sh7619-ether", (kernel_ulong_t)&sh7619_data },
3387 { "sh771x-ether", (kernel_ulong_t)&sh771x_data },
3388 { "sh7724-ether", (kernel_ulong_t)&sh7724_data },
3389 { "sh7734-gether", (kernel_ulong_t)&sh7734_data },
3390 { "sh7757-ether", (kernel_ulong_t)&sh7757_data },
3391 { "sh7757-gether", (kernel_ulong_t)&sh7757_data_giga },
3392 { "sh7763-gether", (kernel_ulong_t)&sh7763_data },
3395 MODULE_DEVICE_TABLE(platform, sh_eth_id_table);
3397 static struct platform_driver sh_eth_driver = {
3398 .probe = sh_eth_drv_probe,
3399 .remove = sh_eth_drv_remove,
3400 .id_table = sh_eth_id_table,
3403 .pm = SH_ETH_PM_OPS,
3404 .of_match_table = of_match_ptr(sh_eth_match_table),
3408 module_platform_driver(sh_eth_driver);
3410 MODULE_AUTHOR("Nobuhiro Iwamatsu, Yoshihiro Shimoda");
3411 MODULE_DESCRIPTION("Renesas SuperH Ethernet driver");
3412 MODULE_LICENSE("GPL v2");