drivers/net/ethernet/sfc/ef10.c

   1 /****************************************************************************
   2  * Driver for Solarflare network controllers and boards
   3  * Copyright 2012-2013 Solarflare Communications Inc.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 as published
   7  * by the Free Software Foundation, incorporated herein by reference.
   8  */
   9
  10 #include "net_driver.h"
  11 #include "ef10_regs.h"
  12 #include "io.h"
  13 #include "mcdi.h"
  14 #include "mcdi_pcol.h"
  15 #include "nic.h"
  16 #include "workarounds.h"
  17 #include "selftest.h"
  18 #include "ef10_sriov.h"
  19 #include <linux/in.h>
  20 #include <linux/jhash.h>
  21 #include <linux/wait.h>
  22 #include <linux/workqueue.h>
  23
  24 /* Hardware control for EF10 architecture including 'Huntington'. */
  25
  26 #define EFX_EF10_DRVGEN_EV              7
  27 enum {
  28         EFX_EF10_TEST = 1,
  29         EFX_EF10_REFILL,
  30 };
  31
  32 /* The reserved RSS context value */
  33 #define EFX_EF10_RSS_CONTEXT_INVALID    0xffffffff
  34 /* The maximum size of a shared RSS context */
  35 /* TODO: this should really be from the mcdi protocol export */
  36 #define EFX_EF10_MAX_SHARED_RSS_CONTEXT_SIZE 64UL
  37
  38 /* The filter table(s) are managed by firmware and we have write-only
  39  * access.  When removing filters we must identify them to the
  40  * firmware by a 64-bit handle, but this is too wide for Linux kernel
  41  * interfaces (32-bit for RX NFC, 16-bit for RFS).  Also, we need to
  42  * be able to tell in advance whether a requested insertion will
  43  * replace an existing filter.  Therefore we maintain a software hash
  44  * table, which should be at least as large as the hardware hash
  45  * table.
  46  *
  47  * Huntington has a single 8K filter table shared between all filter
  48  * types and both ports.
  49  */
  50 #define HUNT_FILTER_TBL_ROWS 8192
  51
  52 struct efx_ef10_filter_table {
  53 /* The RX match field masks supported by this fw & hw, in order of priority */
  54         enum efx_filter_match_flags rx_match_flags[
  55                 MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_MAXNUM];
  56         unsigned int rx_match_count;
  57
  58         struct {
  59                 unsigned long spec;     /* pointer to spec plus flag bits */
  60 /* BUSY flag indicates that an update is in progress.  AUTO_OLD is
  61  * used to mark and sweep MAC filters for the device address lists.
  62  */
  63 #define EFX_EF10_FILTER_FLAG_BUSY       1UL
  64 #define EFX_EF10_FILTER_FLAG_AUTO_OLD   2UL
  65 #define EFX_EF10_FILTER_FLAGS           3UL
  66                 u64 handle;             /* firmware handle */
  67         } *entry;
  68         wait_queue_head_t waitq;
  69 /* Shadow of net_device address lists, guarded by mac_lock */
  70 #define EFX_EF10_FILTER_DEV_UC_MAX      32
  71 #define EFX_EF10_FILTER_DEV_MC_MAX      256
  72         struct {
  73                 u8 addr[ETH_ALEN];
  74                 u16 id;
  75         } dev_uc_list[EFX_EF10_FILTER_DEV_UC_MAX],
  76           dev_mc_list[EFX_EF10_FILTER_DEV_MC_MAX];
  77         int dev_uc_count;               /* negative for PROMISC */
  78         int dev_mc_count;               /* negative for PROMISC/ALLMULTI */
  79 };
  80
  81 /* An arbitrary search limit for the software hash table */
  82 #define EFX_EF10_FILTER_SEARCH_LIMIT 200
  83
  84 static void efx_ef10_rx_free_indir_table(struct efx_nic *efx);
  85 static void efx_ef10_filter_table_remove(struct efx_nic *efx);
  86
  87 static int efx_ef10_get_warm_boot_count(struct efx_nic *efx)
  88 {
  89         efx_dword_t reg;
  90
  91         efx_readd(efx, &reg, ER_DZ_BIU_MC_SFT_STATUS);
  92         return EFX_DWORD_FIELD(reg, EFX_WORD_1) == 0xb007 ?
  93                 EFX_DWORD_FIELD(reg, EFX_WORD_0) : -EIO;
  94 }
  95
  96 static unsigned int efx_ef10_mem_map_size(struct efx_nic *efx)
  97 {
  98         int bar;
  99
 100         bar = efx->type->mem_bar;
 101         return resource_size(&efx->pci_dev->resource[bar]);
 102 }
 103
 104 static int efx_ef10_get_pf_index(struct efx_nic *efx)
 105 {
 106         MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_FUNCTION_INFO_OUT_LEN);
 107         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 108         size_t outlen;
 109         int rc;
 110
 111         rc = efx_mcdi_rpc(efx, MC_CMD_GET_FUNCTION_INFO, NULL, 0, outbuf,
 112                           sizeof(outbuf), &outlen);
 113         if (rc)
 114                 return rc;
 115         if (outlen < sizeof(outbuf))
 116                 return -EIO;
 117
 118         nic_data->pf_index = MCDI_DWORD(outbuf, GET_FUNCTION_INFO_OUT_PF);
 119         return 0;
 120 }
 121
 122 #ifdef CONFIG_SFC_SRIOV
 123 static int efx_ef10_get_vf_index(struct efx_nic *efx)
 124 {
 125         MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_FUNCTION_INFO_OUT_LEN);
 126         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 127         size_t outlen;
 128         int rc;
 129
 130         rc = efx_mcdi_rpc(efx, MC_CMD_GET_FUNCTION_INFO, NULL, 0, outbuf,
 131                           sizeof(outbuf), &outlen);
 132         if (rc)
 133                 return rc;
 134         if (outlen < sizeof(outbuf))
 135                 return -EIO;
 136
 137         nic_data->vf_index = MCDI_DWORD(outbuf, GET_FUNCTION_INFO_OUT_VF);
 138         return 0;
 139 }
 140 #endif
 141
 142 static int efx_ef10_init_datapath_caps(struct efx_nic *efx)
 143 {
 144         MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_CAPABILITIES_OUT_LEN);
 145         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 146         size_t outlen;
 147         int rc;
 148
 149         BUILD_BUG_ON(MC_CMD_GET_CAPABILITIES_IN_LEN != 0);
 150
 151         rc = efx_mcdi_rpc(efx, MC_CMD_GET_CAPABILITIES, NULL, 0,
 152                           outbuf, sizeof(outbuf), &outlen);
 153         if (rc)
 154                 return rc;
 155         if (outlen < sizeof(outbuf)) {
 156                 netif_err(efx, drv, efx->net_dev,
 157                           "unable to read datapath firmware capabilities\n");
 158                 return -EIO;
 159         }
 160
 161         nic_data->datapath_caps =
 162                 MCDI_DWORD(outbuf, GET_CAPABILITIES_OUT_FLAGS1);
 163
 164         /* record the DPCPU firmware IDs to determine VEB vswitching support.
 165          */
 166         nic_data->rx_dpcpu_fw_id =
 167                 MCDI_WORD(outbuf, GET_CAPABILITIES_OUT_RX_DPCPU_FW_ID);
 168         nic_data->tx_dpcpu_fw_id =
 169                 MCDI_WORD(outbuf, GET_CAPABILITIES_OUT_TX_DPCPU_FW_ID);
 170
 171         if (!(nic_data->datapath_caps &
 172               (1 << MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_LBN))) {
 173                 netif_err(efx, drv, efx->net_dev,
 174                           "current firmware does not support TSO\n");
 175                 return -ENODEV;
 176         }
 177
 178         if (!(nic_data->datapath_caps &
 179               (1 << MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_14_LBN))) {
 180                 netif_err(efx, probe, efx->net_dev,
 181                           "current firmware does not support an RX prefix\n");
 182                 return -ENODEV;
 183         }
 184
 185         return 0;
 186 }
 187
 188 static int efx_ef10_get_sysclk_freq(struct efx_nic *efx)
 189 {
 190         MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_CLOCK_OUT_LEN);
 191         int rc;
 192
 193         rc = efx_mcdi_rpc(efx, MC_CMD_GET_CLOCK, NULL, 0,
 194                           outbuf, sizeof(outbuf), NULL);
 195         if (rc)
 196                 return rc;
 197         rc = MCDI_DWORD(outbuf, GET_CLOCK_OUT_SYS_FREQ);
 198         return rc > 0 ? rc : -ERANGE;
 199 }
 200
 201 static int efx_ef10_get_mac_address_pf(struct efx_nic *efx, u8 *mac_address)
 202 {
 203         MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_MAC_ADDRESSES_OUT_LEN);
 204         size_t outlen;
 205         int rc;
 206
 207         BUILD_BUG_ON(MC_CMD_GET_MAC_ADDRESSES_IN_LEN != 0);
 208
 209         rc = efx_mcdi_rpc(efx, MC_CMD_GET_MAC_ADDRESSES, NULL, 0,
 210                           outbuf, sizeof(outbuf), &outlen);
 211         if (rc)
 212                 return rc;
 213         if (outlen < MC_CMD_GET_MAC_ADDRESSES_OUT_LEN)
 214                 return -EIO;
 215
 216         ether_addr_copy(mac_address,
 217                         MCDI_PTR(outbuf, GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE));
 218         return 0;
 219 }
 220
 221 static int efx_ef10_get_mac_address_vf(struct efx_nic *efx, u8 *mac_address)
 222 {
 223         MCDI_DECLARE_BUF(inbuf, MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_LEN);
 224         MCDI_DECLARE_BUF(outbuf, MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMAX);
 225         size_t outlen;
 226         int num_addrs, rc;
 227
 228         MCDI_SET_DWORD(inbuf, VPORT_GET_MAC_ADDRESSES_IN_VPORT_ID,
 229                        EVB_PORT_ID_ASSIGNED);
 230         rc = efx_mcdi_rpc(efx, MC_CMD_VPORT_GET_MAC_ADDRESSES, inbuf,
 231                           sizeof(inbuf), outbuf, sizeof(outbuf), &outlen);
 232
 233         if (rc)
 234                 return rc;
 235         if (outlen < MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMIN)
 236                 return -EIO;
 237
 238         num_addrs = MCDI_DWORD(outbuf,
 239                                VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_COUNT);
 240
 241         WARN_ON(num_addrs != 1);
 242
 243         ether_addr_copy(mac_address,
 244                         MCDI_PTR(outbuf, VPORT_GET_MAC_ADDRESSES_OUT_MACADDR));
 245
 246         return 0;
 247 }
 248
 249 static int efx_ef10_probe(struct efx_nic *efx)
 250 {
 251         struct efx_ef10_nic_data *nic_data;
 252         int i, rc;
 253
 254         /* We can have one VI for each 8K region.  However, until we
 255          * use TX option descriptors we need two TX queues per channel.
 256          */
 257         efx->max_channels =
 258                 min_t(unsigned int,
 259                       EFX_MAX_CHANNELS,
 260                       efx_ef10_mem_map_size(efx) /
 261                       (EFX_VI_PAGE_SIZE * EFX_TXQ_TYPES));
 262         if (WARN_ON(efx->max_channels == 0))
 263                 return -EIO;
 264
 265         nic_data = kzalloc(sizeof(*nic_data), GFP_KERNEL);
 266         if (!nic_data)
 267                 return -ENOMEM;
 268         efx->nic_data = nic_data;
 269
 270         rc = efx_nic_alloc_buffer(efx, &nic_data->mcdi_buf,
 271                                   8 + MCDI_CTL_SDU_LEN_MAX_V2, GFP_KERNEL);
 272         if (rc)
 273                 goto fail1;
 274
 275         /* Get the MC's warm boot count.  In case it's rebooting right
 276          * now, be prepared to retry.
 277          */
 278         i = 0;
 279         for (;;) {
 280                 rc = efx_ef10_get_warm_boot_count(efx);
 281                 if (rc >= 0)
 282                         break;
 283                 if (++i == 5)
 284                         goto fail2;
 285                 ssleep(1);
 286         }
 287         nic_data->warm_boot_count = rc;
 288
 289         nic_data->rx_rss_context = EFX_EF10_RSS_CONTEXT_INVALID;
 290
 291         nic_data->vport_id = EVB_PORT_ID_ASSIGNED;
 292
 293         /* In case we're recovering from a crash (kexec), we want to
 294          * cancel any outstanding request by the previous user of this
 295          * function.  We send a special message using the least
 296          * significant bits of the 'high' (doorbell) register.
 297          */
 298         _efx_writed(efx, cpu_to_le32(1), ER_DZ_MC_DB_HWRD);
 299
 300         rc = efx_mcdi_init(efx);
 301         if (rc)
 302                 goto fail2;
 303
 304         /* Reset (most) configuration for this function */
 305         rc = efx_mcdi_reset(efx, RESET_TYPE_ALL);
 306         if (rc)
 307                 goto fail3;
 308
 309         /* Enable event logging */
 310         rc = efx_mcdi_log_ctrl(efx, true, false, 0);
 311         if (rc)
 312                 goto fail3;
 313
 314         rc = efx_ef10_get_pf_index(efx);
 315         if (rc)
 316                 goto fail3;
 317
 318         rc = efx_ef10_init_datapath_caps(efx);
 319         if (rc < 0)
 320                 goto fail3;
 321
 322         efx->rx_packet_len_offset =
 323                 ES_DZ_RX_PREFIX_PKTLEN_OFST - ES_DZ_RX_PREFIX_SIZE;
 324
 325         rc = efx_mcdi_port_get_number(efx);
 326         if (rc < 0)
 327                 goto fail3;
 328         efx->port_num = rc;
 329
 330         rc = efx->type->get_mac_address(efx, efx->net_dev->perm_addr);
 331         if (rc)
 332                 goto fail3;
 333
 334         rc = efx_ef10_get_sysclk_freq(efx);
 335         if (rc < 0)
 336                 goto fail3;
 337         efx->timer_quantum_ns = 1536000 / rc; /* 1536 cycles */
 338
 339         /* Check whether firmware supports bug 35388 workaround.
 340          * First try to enable it, then if we get EPERM, just
 341          * ask if it's already enabled
 342          */
 343         rc = efx_mcdi_set_workaround(efx, MC_CMD_WORKAROUND_BUG35388, true);
 344         if (rc == 0)
 345                 nic_data->workaround_35388 = true;
 346         else if (rc == -EPERM) {
 347                 unsigned int enabled;
 348
 349                 rc = efx_mcdi_get_workarounds(efx, NULL, &enabled);
 350                 if (rc)
 351                         goto fail3;
 352                 nic_data->workaround_35388 = enabled &
 353                         MC_CMD_GET_WORKAROUNDS_OUT_BUG35388;
 354         }
 355         else if (rc != -ENOSYS && rc != -ENOENT)
 356                 goto fail3;
 357         netif_dbg(efx, probe, efx->net_dev,
 358                   "workaround for bug 35388 is %sabled\n",
 359                   nic_data->workaround_35388 ? "en" : "dis");
 360
 361         rc = efx_mcdi_mon_probe(efx);
 362         if (rc && rc != -EPERM)
 363                 goto fail3;
 364
 365         efx_ptp_probe(efx, NULL);
 366
 367         return 0;
 368
 369 fail3:
 370         efx_mcdi_fini(efx);
 371 fail2:
 372         efx_nic_free_buffer(efx, &nic_data->mcdi_buf);
 373 fail1:
 374         kfree(nic_data);
 375         efx->nic_data = NULL;
 376         return rc;
 377 }
 378
 379 static int efx_ef10_free_vis(struct efx_nic *efx)
 380 {
 381         MCDI_DECLARE_BUF_ERR(outbuf);
 382         size_t outlen;
 383         int rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FREE_VIS, NULL, 0,
 384                                     outbuf, sizeof(outbuf), &outlen);
 385
 386         /* -EALREADY means nothing to free, so ignore */
 387         if (rc == -EALREADY)
 388                 rc = 0;
 389         if (rc)
 390                 efx_mcdi_display_error(efx, MC_CMD_FREE_VIS, 0, outbuf, outlen,
 391                                        rc);
 392         return rc;
 393 }
 394
 395 #ifdef EFX_USE_PIO
 396
 397 static void efx_ef10_free_piobufs(struct efx_nic *efx)
 398 {
 399         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 400         MCDI_DECLARE_BUF(inbuf, MC_CMD_FREE_PIOBUF_IN_LEN);
 401         unsigned int i;
 402         int rc;
 403
 404         BUILD_BUG_ON(MC_CMD_FREE_PIOBUF_OUT_LEN != 0);
 405
 406         for (i = 0; i < nic_data->n_piobufs; i++) {
 407                 MCDI_SET_DWORD(inbuf, FREE_PIOBUF_IN_PIOBUF_HANDLE,
 408                                nic_data->piobuf_handle[i]);
 409                 rc = efx_mcdi_rpc(efx, MC_CMD_FREE_PIOBUF, inbuf, sizeof(inbuf),
 410                                   NULL, 0, NULL);
 411                 WARN_ON(rc);
 412         }
 413
 414         nic_data->n_piobufs = 0;
 415 }
 416
 417 static int efx_ef10_alloc_piobufs(struct efx_nic *efx, unsigned int n)
 418 {
 419         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 420         MCDI_DECLARE_BUF(outbuf, MC_CMD_ALLOC_PIOBUF_OUT_LEN);
 421         unsigned int i;
 422         size_t outlen;
 423         int rc = 0;
 424
 425         BUILD_BUG_ON(MC_CMD_ALLOC_PIOBUF_IN_LEN != 0);
 426
 427         for (i = 0; i < n; i++) {
 428                 rc = efx_mcdi_rpc(efx, MC_CMD_ALLOC_PIOBUF, NULL, 0,
 429                                   outbuf, sizeof(outbuf), &outlen);
 430                 if (rc)
 431                         break;
 432                 if (outlen < MC_CMD_ALLOC_PIOBUF_OUT_LEN) {
 433                         rc = -EIO;
 434                         break;
 435                 }
 436                 nic_data->piobuf_handle[i] =
 437                         MCDI_DWORD(outbuf, ALLOC_PIOBUF_OUT_PIOBUF_HANDLE);
 438                 netif_dbg(efx, probe, efx->net_dev,
 439                           "allocated PIO buffer %u handle %x\n", i,
 440                           nic_data->piobuf_handle[i]);
 441         }
 442
 443         nic_data->n_piobufs = i;
 444         if (rc)
 445                 efx_ef10_free_piobufs(efx);
 446         return rc;
 447 }
 448
 449 static int efx_ef10_link_piobufs(struct efx_nic *efx)
 450 {
 451         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 452         _MCDI_DECLARE_BUF(inbuf,
 453                           max(MC_CMD_LINK_PIOBUF_IN_LEN,
 454                               MC_CMD_UNLINK_PIOBUF_IN_LEN));
 455         struct efx_channel *channel;
 456         struct efx_tx_queue *tx_queue;
 457         unsigned int offset, index;
 458         int rc;
 459
 460         BUILD_BUG_ON(MC_CMD_LINK_PIOBUF_OUT_LEN != 0);
 461         BUILD_BUG_ON(MC_CMD_UNLINK_PIOBUF_OUT_LEN != 0);
 462
 463         memset(inbuf, 0, sizeof(inbuf));
 464
 465         /* Link a buffer to each VI in the write-combining mapping */
 466         for (index = 0; index < nic_data->n_piobufs; ++index) {
 467                 MCDI_SET_DWORD(inbuf, LINK_PIOBUF_IN_PIOBUF_HANDLE,
 468                                nic_data->piobuf_handle[index]);
 469                 MCDI_SET_DWORD(inbuf, LINK_PIOBUF_IN_TXQ_INSTANCE,
 470                                nic_data->pio_write_vi_base + index);
 471                 rc = efx_mcdi_rpc(efx, MC_CMD_LINK_PIOBUF,
 472                                   inbuf, MC_CMD_LINK_PIOBUF_IN_LEN,
 473                                   NULL, 0, NULL);
 474                 if (rc) {
 475                         netif_err(efx, drv, efx->net_dev,
 476                                   "failed to link VI %u to PIO buffer %u (%d)\n",
 477                                   nic_data->pio_write_vi_base + index, index,
 478                                   rc);
 479                         goto fail;
 480                 }
 481                 netif_dbg(efx, probe, efx->net_dev,
 482                           "linked VI %u to PIO buffer %u\n",
 483                           nic_data->pio_write_vi_base + index, index);
 484         }
 485
 486         /* Link a buffer to each TX queue */
 487         efx_for_each_channel(channel, efx) {
 488                 efx_for_each_channel_tx_queue(tx_queue, channel) {
 489                         /* We assign the PIO buffers to queues in
 490                          * reverse order to allow for the following
 491                          * special case.
 492                          */
 493                         offset = ((efx->tx_channel_offset + efx->n_tx_channels -
 494                                    tx_queue->channel->channel - 1) *
 495                                   efx_piobuf_size);
 496                         index = offset / ER_DZ_TX_PIOBUF_SIZE;
 497                         offset = offset % ER_DZ_TX_PIOBUF_SIZE;
 498
 499                         /* When the host page size is 4K, the first
 500                          * host page in the WC mapping may be within
 501                          * the same VI page as the last TX queue.  We
 502                          * can only link one buffer to each VI.
 503                          */
 504                         if (tx_queue->queue == nic_data->pio_write_vi_base) {
 505                                 BUG_ON(index != 0);
 506                                 rc = 0;
 507                         } else {
 508                                 MCDI_SET_DWORD(inbuf,
 509                                                LINK_PIOBUF_IN_PIOBUF_HANDLE,
 510                                                nic_data->piobuf_handle[index]);
 511                                 MCDI_SET_DWORD(inbuf,
 512                                                LINK_PIOBUF_IN_TXQ_INSTANCE,
 513                                                tx_queue->queue);
 514                                 rc = efx_mcdi_rpc(efx, MC_CMD_LINK_PIOBUF,
 515                                                   inbuf, MC_CMD_LINK_PIOBUF_IN_LEN,
 516                                                   NULL, 0, NULL);
 517                         }
 518
 519                         if (rc) {
 520                                 /* This is non-fatal; the TX path just
 521                                  * won't use PIO for this queue
 522                                  */
 523                                 netif_err(efx, drv, efx->net_dev,
 524                                           "failed to link VI %u to PIO buffer %u (%d)\n",
 525                                           tx_queue->queue, index, rc);
 526                                 tx_queue->piobuf = NULL;
 527                         } else {
 528                                 tx_queue->piobuf =
 529                                         nic_data->pio_write_base +
 530                                         index * EFX_VI_PAGE_SIZE + offset;
 531                                 tx_queue->piobuf_offset = offset;
 532                                 netif_dbg(efx, probe, efx->net_dev,
 533                                           "linked VI %u to PIO buffer %u offset %x addr %p\n",
 534                                           tx_queue->queue, index,
 535                                           tx_queue->piobuf_offset,
 536                                           tx_queue->piobuf);
 537                         }
 538                 }
 539         }
 540
 541         return 0;
 542
 543 fail:
 544         while (index--) {
 545                 MCDI_SET_DWORD(inbuf, UNLINK_PIOBUF_IN_TXQ_INSTANCE,
 546                                nic_data->pio_write_vi_base + index);
 547                 efx_mcdi_rpc(efx, MC_CMD_UNLINK_PIOBUF,
 548                              inbuf, MC_CMD_UNLINK_PIOBUF_IN_LEN,
 549                              NULL, 0, NULL);
 550         }
 551         return rc;
 552 }
 553
 554 #else /* !EFX_USE_PIO */
 555
 556 static int efx_ef10_alloc_piobufs(struct efx_nic *efx, unsigned int n)
 557 {
 558         return n == 0 ? 0 : -ENOBUFS;
 559 }
 560
 561 static int efx_ef10_link_piobufs(struct efx_nic *efx)
 562 {
 563         return 0;
 564 }
 565
 566 static void efx_ef10_free_piobufs(struct efx_nic *efx)
 567 {
 568 }
 569
 570 #endif /* EFX_USE_PIO */
 571
 572 static void efx_ef10_remove(struct efx_nic *efx)
 573 {
 574         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 575         int rc;
 576
 577 #ifdef CONFIG_SFC_SRIOV
 578         struct efx_ef10_nic_data *nic_data_pf;
 579         struct pci_dev *pci_dev_pf;
 580         struct efx_nic *efx_pf;
 581         struct ef10_vf *vf;
 582
 583         if (efx->pci_dev->is_virtfn) {
 584                 pci_dev_pf = efx->pci_dev->physfn;
 585                 if (pci_dev_pf) {
 586                         efx_pf = pci_get_drvdata(pci_dev_pf);
 587                         nic_data_pf = efx_pf->nic_data;
 588                         vf = nic_data_pf->vf + nic_data->vf_index;
 589                         vf->efx = NULL;
 590                 } else
 591                         netif_info(efx, drv, efx->net_dev,
 592                                    "Could not get the PF id from VF\n");
 593         }
 594 #endif
 595
 596         efx_ptp_remove(efx);
 597
 598         efx_mcdi_mon_remove(efx);
 599
 600         efx_ef10_rx_free_indir_table(efx);
 601
 602         if (nic_data->wc_membase)
 603                 iounmap(nic_data->wc_membase);
 604
 605         rc = efx_ef10_free_vis(efx);
 606         WARN_ON(rc != 0);
 607
 608         if (!nic_data->must_restore_piobufs)
 609                 efx_ef10_free_piobufs(efx);
 610
 611         efx_mcdi_fini(efx);
 612         efx_nic_free_buffer(efx, &nic_data->mcdi_buf);
 613         kfree(nic_data);
 614 }
 615
 616 static int efx_ef10_probe_pf(struct efx_nic *efx)
 617 {
 618         return efx_ef10_probe(efx);
 619 }
 620
 621 #ifdef CONFIG_SFC_SRIOV
 622 static int efx_ef10_probe_vf(struct efx_nic *efx)
 623 {
 624         int rc;
 625
 626         rc = efx_ef10_probe(efx);
 627         if (rc)
 628                 return rc;
 629
 630         rc = efx_ef10_get_vf_index(efx);
 631         if (rc)
 632                 goto fail;
 633
 634         if (efx->pci_dev->is_virtfn) {
 635                 if (efx->pci_dev->physfn) {
 636                         struct efx_nic *efx_pf =
 637                                 pci_get_drvdata(efx->pci_dev->physfn);
 638                         struct efx_ef10_nic_data *nic_data_p = efx_pf->nic_data;
 639                         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 640
 641                         nic_data_p->vf[nic_data->vf_index].efx = efx;
 642                 } else
 643                         netif_info(efx, drv, efx->net_dev,
 644                                    "Could not get the PF id from VF\n");
 645         }
 646
 647         return 0;
 648
 649 fail:
 650         efx_ef10_remove(efx);
 651         return rc;
 652 }
 653 #else
 654 static int efx_ef10_probe_vf(struct efx_nic *efx __attribute__ ((unused)))
 655 {
 656         return 0;
 657 }
 658 #endif
 659
 660 static int efx_ef10_alloc_vis(struct efx_nic *efx,
 661                               unsigned int min_vis, unsigned int max_vis)
 662 {
 663         MCDI_DECLARE_BUF(inbuf, MC_CMD_ALLOC_VIS_IN_LEN);
 664         MCDI_DECLARE_BUF(outbuf, MC_CMD_ALLOC_VIS_OUT_LEN);
 665         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 666         size_t outlen;
 667         int rc;
 668
 669         MCDI_SET_DWORD(inbuf, ALLOC_VIS_IN_MIN_VI_COUNT, min_vis);
 670         MCDI_SET_DWORD(inbuf, ALLOC_VIS_IN_MAX_VI_COUNT, max_vis);
 671         rc = efx_mcdi_rpc(efx, MC_CMD_ALLOC_VIS, inbuf, sizeof(inbuf),
 672                           outbuf, sizeof(outbuf), &outlen);
 673         if (rc != 0)
 674                 return rc;
 675
 676         if (outlen < MC_CMD_ALLOC_VIS_OUT_LEN)
 677                 return -EIO;
 678
 679         netif_dbg(efx, drv, efx->net_dev, "base VI is A0x%03x\n",
 680                   MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_BASE));
 681
 682         nic_data->vi_base = MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_BASE);
 683         nic_data->n_allocated_vis = MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_COUNT);
 684         return 0;
 685 }
 686
 687 /* Note that the failure path of this function does not free
 688  * resources, as this will be done by efx_ef10_remove().
 689  */
 690 static int efx_ef10_dimension_resources(struct efx_nic *efx)
 691 {
 692         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 693         unsigned int uc_mem_map_size, wc_mem_map_size;
 694         unsigned int min_vis, pio_write_vi_base, max_vis;
 695         void __iomem *membase;
 696         int rc;
 697
 698         min_vis = max(efx->n_channels, efx->n_tx_channels * EFX_TXQ_TYPES);
 699
 700 #ifdef EFX_USE_PIO
 701         /* Try to allocate PIO buffers if wanted and if the full
 702          * number of PIO buffers would be sufficient to allocate one
 703          * copy-buffer per TX channel.  Failure is non-fatal, as there
 704          * are only a small number of PIO buffers shared between all
 705          * functions of the controller.
 706          */
 707         if (efx_piobuf_size != 0 &&
 708             ER_DZ_TX_PIOBUF_SIZE / efx_piobuf_size * EF10_TX_PIOBUF_COUNT >=
 709             efx->n_tx_channels) {
 710                 unsigned int n_piobufs =
 711                         DIV_ROUND_UP(efx->n_tx_channels,
 712                                      ER_DZ_TX_PIOBUF_SIZE / efx_piobuf_size);
 713
 714                 rc = efx_ef10_alloc_piobufs(efx, n_piobufs);
 715                 if (rc)
 716                         netif_err(efx, probe, efx->net_dev,
 717                                   "failed to allocate PIO buffers (%d)\n", rc);
 718                 else
 719                         netif_dbg(efx, probe, efx->net_dev,
 720                                   "allocated %u PIO buffers\n", n_piobufs);
 721         }
 722 #else
 723         nic_data->n_piobufs = 0;
 724 #endif
 725
 726         /* PIO buffers should be mapped with write-combining enabled,
 727          * and we want to make single UC and WC mappings rather than
 728          * several of each (in fact that's the only option if host
 729          * page size is >4K).  So we may allocate some extra VIs just
 730          * for writing PIO buffers through.
 731          *
 732          * The UC mapping contains (min_vis - 1) complete VIs and the
 733          * first half of the next VI.  Then the WC mapping begins with
 734          * the second half of this last VI.
 735          */
 736         uc_mem_map_size = PAGE_ALIGN((min_vis - 1) * EFX_VI_PAGE_SIZE +
 737                                      ER_DZ_TX_PIOBUF);
 738         if (nic_data->n_piobufs) {
 739                 /* pio_write_vi_base rounds down to give the number of complete
 740                  * VIs inside the UC mapping.
 741                  */
 742                 pio_write_vi_base = uc_mem_map_size / EFX_VI_PAGE_SIZE;
 743                 wc_mem_map_size = (PAGE_ALIGN((pio_write_vi_base +
 744                                                nic_data->n_piobufs) *
 745                                               EFX_VI_PAGE_SIZE) -
 746                                    uc_mem_map_size);
 747                 max_vis = pio_write_vi_base + nic_data->n_piobufs;
 748         } else {
 749                 pio_write_vi_base = 0;
 750                 wc_mem_map_size = 0;
 751                 max_vis = min_vis;
 752         }
 753
 754         /* In case the last attached driver failed to free VIs, do it now */
 755         rc = efx_ef10_free_vis(efx);
 756         if (rc != 0)
 757                 return rc;
 758
 759         rc = efx_ef10_alloc_vis(efx, min_vis, max_vis);
 760         if (rc != 0)
 761                 return rc;
 762
 763         /* If we didn't get enough VIs to map all the PIO buffers, free the
 764          * PIO buffers
 765          */
 766         if (nic_data->n_piobufs &&
 767             nic_data->n_allocated_vis <
 768             pio_write_vi_base + nic_data->n_piobufs) {
 769                 netif_dbg(efx, probe, efx->net_dev,
 770                           "%u VIs are not sufficient to map %u PIO buffers\n",
 771                           nic_data->n_allocated_vis, nic_data->n_piobufs);
 772                 efx_ef10_free_piobufs(efx);
 773         }
 774
 775         /* Shrink the original UC mapping of the memory BAR */
 776         membase = ioremap_nocache(efx->membase_phys, uc_mem_map_size);
 777         if (!membase) {
 778                 netif_err(efx, probe, efx->net_dev,
 779                           "could not shrink memory BAR to %x\n",
 780                           uc_mem_map_size);
 781                 return -ENOMEM;
 782         }
 783         iounmap(efx->membase);
 784         efx->membase = membase;
 785
 786         /* Set up the WC mapping if needed */
 787         if (wc_mem_map_size) {
 788                 nic_data->wc_membase = ioremap_wc(efx->membase_phys +
 789                                                   uc_mem_map_size,
 790                                                   wc_mem_map_size);
 791                 if (!nic_data->wc_membase) {
 792                         netif_err(efx, probe, efx->net_dev,
 793                                   "could not allocate WC mapping of size %x\n",
 794                                   wc_mem_map_size);
 795                         return -ENOMEM;
 796                 }
 797                 nic_data->pio_write_vi_base = pio_write_vi_base;
 798                 nic_data->pio_write_base =
 799                         nic_data->wc_membase +
 800                         (pio_write_vi_base * EFX_VI_PAGE_SIZE + ER_DZ_TX_PIOBUF -
 801                          uc_mem_map_size);
 802
 803                 rc = efx_ef10_link_piobufs(efx);
 804                 if (rc)
 805                         efx_ef10_free_piobufs(efx);
 806         }
 807
 808         netif_dbg(efx, probe, efx->net_dev,
 809                   "memory BAR at %pa (virtual %p+%x UC, %p+%x WC)\n",
 810                   &efx->membase_phys, efx->membase, uc_mem_map_size,
 811                   nic_data->wc_membase, wc_mem_map_size);
 812
 813         return 0;
 814 }
 815
 816 static int efx_ef10_init_nic(struct efx_nic *efx)
 817 {
 818         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 819         int rc;
 820
 821         if (nic_data->must_check_datapath_caps) {
 822                 rc = efx_ef10_init_datapath_caps(efx);
 823                 if (rc)
 824                         return rc;
 825                 nic_data->must_check_datapath_caps = false;
 826         }
 827
 828         if (nic_data->must_realloc_vis) {
 829                 /* We cannot let the number of VIs change now */
 830                 rc = efx_ef10_alloc_vis(efx, nic_data->n_allocated_vis,
 831                                         nic_data->n_allocated_vis);
 832                 if (rc)
 833                         return rc;
 834                 nic_data->must_realloc_vis = false;
 835         }
 836
 837         if (nic_data->must_restore_piobufs && nic_data->n_piobufs) {
 838                 rc = efx_ef10_alloc_piobufs(efx, nic_data->n_piobufs);
 839                 if (rc == 0) {
 840                         rc = efx_ef10_link_piobufs(efx);
 841                         if (rc)
 842                                 efx_ef10_free_piobufs(efx);
 843                 }
 844
 845                 /* Log an error on failure, but this is non-fatal */
 846                 if (rc)
 847                         netif_err(efx, drv, efx->net_dev,
 848                                   "failed to restore PIO buffers (%d)\n", rc);
 849                 nic_data->must_restore_piobufs = false;
 850         }
 851
 852         /* don't fail init if RSS setup doesn't work */
 853         efx->type->rx_push_rss_config(efx, false, efx->rx_indir_table);
 854
 855         return 0;
 856 }
 857
 858 static void efx_ef10_reset_mc_allocations(struct efx_nic *efx)
 859 {
 860         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 861
 862         /* All our allocations have been reset */
 863         nic_data->must_realloc_vis = true;
 864         nic_data->must_restore_filters = true;
 865         nic_data->must_restore_piobufs = true;
 866         nic_data->rx_rss_context = EFX_EF10_RSS_CONTEXT_INVALID;
 867 }
 868
 869 static int efx_ef10_map_reset_flags(u32 *flags)
 870 {
 871         enum {
 872                 EF10_RESET_PORT = ((ETH_RESET_MAC | ETH_RESET_PHY) <<
 873                                    ETH_RESET_SHARED_SHIFT),
 874                 EF10_RESET_MC = ((ETH_RESET_DMA | ETH_RESET_FILTER |
 875                                   ETH_RESET_OFFLOAD | ETH_RESET_MAC |
 876                                   ETH_RESET_PHY | ETH_RESET_MGMT) <<
 877                                  ETH_RESET_SHARED_SHIFT)
 878         };
 879
 880         /* We assume for now that our PCI function is permitted to
 881          * reset everything.
 882          */
 883
 884         if ((*flags & EF10_RESET_MC) == EF10_RESET_MC) {
 885                 *flags &= ~EF10_RESET_MC;
 886                 return RESET_TYPE_WORLD;
 887         }
 888
 889         if ((*flags & EF10_RESET_PORT) == EF10_RESET_PORT) {
 890                 *flags &= ~EF10_RESET_PORT;
 891                 return RESET_TYPE_ALL;
 892         }
 893
 894         /* no invisible reset implemented */
 895
 896         return -EINVAL;
 897 }
 898
 899 static int efx_ef10_reset(struct efx_nic *efx, enum reset_type reset_type)
 900 {
 901         int rc = efx_mcdi_reset(efx, reset_type);
 902
 903         /* If it was a port reset, trigger reallocation of MC resources.
 904          * Note that on an MC reset nothing needs to be done now because we'll
 905          * detect the MC reset later and handle it then.
 906          * For an FLR, we never get an MC reset event, but the MC has reset all
 907          * resources assigned to us, so we have to trigger reallocation now.
 908          */
 909         if ((reset_type == RESET_TYPE_ALL ||
 910              reset_type == RESET_TYPE_MCDI_TIMEOUT) && !rc)
 911                 efx_ef10_reset_mc_allocations(efx);
 912         return rc;
 913 }
 914
 915 #define EF10_DMA_STAT(ext_name, mcdi_name)                      \
 916         [EF10_STAT_ ## ext_name] =                              \
 917         { #ext_name, 64, 8 * MC_CMD_MAC_ ## mcdi_name }
 918 #define EF10_DMA_INVIS_STAT(int_name, mcdi_name)                \
 919         [EF10_STAT_ ## int_name] =                              \
 920         { NULL, 64, 8 * MC_CMD_MAC_ ## mcdi_name }
 921 #define EF10_OTHER_STAT(ext_name)                               \
 922         [EF10_STAT_ ## ext_name] = { #ext_name, 0, 0 }
 923 #define GENERIC_SW_STAT(ext_name)                               \
 924         [GENERIC_STAT_ ## ext_name] = { #ext_name, 0, 0 }
 925
 926 static const struct efx_hw_stat_desc efx_ef10_stat_desc[EF10_STAT_COUNT] = {
 927         EF10_DMA_STAT(tx_bytes, TX_BYTES),
 928         EF10_DMA_STAT(tx_packets, TX_PKTS),
 929         EF10_DMA_STAT(tx_pause, TX_PAUSE_PKTS),
 930         EF10_DMA_STAT(tx_control, TX_CONTROL_PKTS),
 931         EF10_DMA_STAT(tx_unicast, TX_UNICAST_PKTS),
 932         EF10_DMA_STAT(tx_multicast, TX_MULTICAST_PKTS),
 933         EF10_DMA_STAT(tx_broadcast, TX_BROADCAST_PKTS),
 934         EF10_DMA_STAT(tx_lt64, TX_LT64_PKTS),
 935         EF10_DMA_STAT(tx_64, TX_64_PKTS),
 936         EF10_DMA_STAT(tx_65_to_127, TX_65_TO_127_PKTS),
 937         EF10_DMA_STAT(tx_128_to_255, TX_128_TO_255_PKTS),
 938         EF10_DMA_STAT(tx_256_to_511, TX_256_TO_511_PKTS),
 939         EF10_DMA_STAT(tx_512_to_1023, TX_512_TO_1023_PKTS),
 940         EF10_DMA_STAT(tx_1024_to_15xx, TX_1024_TO_15XX_PKTS),
 941         EF10_DMA_STAT(tx_15xx_to_jumbo, TX_15XX_TO_JUMBO_PKTS),
 942         EF10_DMA_STAT(rx_bytes, RX_BYTES),
 943         EF10_DMA_INVIS_STAT(rx_bytes_minus_good_bytes, RX_BAD_BYTES),
 944         EF10_OTHER_STAT(rx_good_bytes),
 945         EF10_OTHER_STAT(rx_bad_bytes),
 946         EF10_DMA_STAT(rx_packets, RX_PKTS),
 947         EF10_DMA_STAT(rx_good, RX_GOOD_PKTS),
 948         EF10_DMA_STAT(rx_bad, RX_BAD_FCS_PKTS),
 949         EF10_DMA_STAT(rx_pause, RX_PAUSE_PKTS),
 950         EF10_DMA_STAT(rx_control, RX_CONTROL_PKTS),
 951         EF10_DMA_STAT(rx_unicast, RX_UNICAST_PKTS),
 952         EF10_DMA_STAT(rx_multicast, RX_MULTICAST_PKTS),
 953         EF10_DMA_STAT(rx_broadcast, RX_BROADCAST_PKTS),
 954         EF10_DMA_STAT(rx_lt64, RX_UNDERSIZE_PKTS),
 955         EF10_DMA_STAT(rx_64, RX_64_PKTS),
 956         EF10_DMA_STAT(rx_65_to_127, RX_65_TO_127_PKTS),
 957         EF10_DMA_STAT(rx_128_to_255, RX_128_TO_255_PKTS),
 958         EF10_DMA_STAT(rx_256_to_511, RX_256_TO_511_PKTS),
 959         EF10_DMA_STAT(rx_512_to_1023, RX_512_TO_1023_PKTS),
 960         EF10_DMA_STAT(rx_1024_to_15xx, RX_1024_TO_15XX_PKTS),
 961         EF10_DMA_STAT(rx_15xx_to_jumbo, RX_15XX_TO_JUMBO_PKTS),
 962         EF10_DMA_STAT(rx_gtjumbo, RX_GTJUMBO_PKTS),
 963         EF10_DMA_STAT(rx_bad_gtjumbo, RX_JABBER_PKTS),
 964         EF10_DMA_STAT(rx_overflow, RX_OVERFLOW_PKTS),
 965         EF10_DMA_STAT(rx_align_error, RX_ALIGN_ERROR_PKTS),
 966         EF10_DMA_STAT(rx_length_error, RX_LENGTH_ERROR_PKTS),
 967         EF10_DMA_STAT(rx_nodesc_drops, RX_NODESC_DROPS),
 968         GENERIC_SW_STAT(rx_nodesc_trunc),
 969         GENERIC_SW_STAT(rx_noskb_drops),
 970         EF10_DMA_STAT(rx_pm_trunc_bb_overflow, PM_TRUNC_BB_OVERFLOW),
 971         EF10_DMA_STAT(rx_pm_discard_bb_overflow, PM_DISCARD_BB_OVERFLOW),
 972         EF10_DMA_STAT(rx_pm_trunc_vfifo_full, PM_TRUNC_VFIFO_FULL),
 973         EF10_DMA_STAT(rx_pm_discard_vfifo_full, PM_DISCARD_VFIFO_FULL),
 974         EF10_DMA_STAT(rx_pm_trunc_qbb, PM_TRUNC_QBB),
 975         EF10_DMA_STAT(rx_pm_discard_qbb, PM_DISCARD_QBB),
 976         EF10_DMA_STAT(rx_pm_discard_mapping, PM_DISCARD_MAPPING),
 977         EF10_DMA_STAT(rx_dp_q_disabled_packets, RXDP_Q_DISABLED_PKTS),
 978         EF10_DMA_STAT(rx_dp_di_dropped_packets, RXDP_DI_DROPPED_PKTS),
 979         EF10_DMA_STAT(rx_dp_streaming_packets, RXDP_STREAMING_PKTS),
 980         EF10_DMA_STAT(rx_dp_hlb_fetch, RXDP_EMERGENCY_FETCH_CONDITIONS),
 981         EF10_DMA_STAT(rx_dp_hlb_wait, RXDP_EMERGENCY_WAIT_CONDITIONS),
 982 };
 983
 984 #define HUNT_COMMON_STAT_MASK ((1ULL << EF10_STAT_tx_bytes) |           \
 985                                (1ULL << EF10_STAT_tx_packets) |         \
 986                                (1ULL << EF10_STAT_tx_pause) |           \
 987                                (1ULL << EF10_STAT_tx_unicast) |         \
 988                                (1ULL << EF10_STAT_tx_multicast) |       \
 989                                (1ULL << EF10_STAT_tx_broadcast) |       \
 990                                (1ULL << EF10_STAT_rx_bytes) |           \
 991                                (1ULL << EF10_STAT_rx_bytes_minus_good_bytes) | \
 992                                (1ULL << EF10_STAT_rx_good_bytes) |      \
 993                                (1ULL << EF10_STAT_rx_bad_bytes) |       \
 994                                (1ULL << EF10_STAT_rx_packets) |         \
 995                                (1ULL << EF10_STAT_rx_good) |            \
 996                                (1ULL << EF10_STAT_rx_bad) |             \
 997                                (1ULL << EF10_STAT_rx_pause) |           \
 998                                (1ULL << EF10_STAT_rx_control) |         \
 999                                (1ULL << EF10_STAT_rx_unicast) |         \
1000                                (1ULL << EF10_STAT_rx_multicast) |       \
1001                                (1ULL << EF10_STAT_rx_broadcast) |       \
1002                                (1ULL << EF10_STAT_rx_lt64) |            \
1003                                (1ULL << EF10_STAT_rx_64) |              \
1004                                (1ULL << EF10_STAT_rx_65_to_127) |       \
1005                                (1ULL << EF10_STAT_rx_128_to_255) |      \
1006                                (1ULL << EF10_STAT_rx_256_to_511) |      \
1007                                (1ULL << EF10_STAT_rx_512_to_1023) |     \
1008                                (1ULL << EF10_STAT_rx_1024_to_15xx) |    \
1009                                (1ULL << EF10_STAT_rx_15xx_to_jumbo) |   \
1010                                (1ULL << EF10_STAT_rx_gtjumbo) |         \
1011                                (1ULL << EF10_STAT_rx_bad_gtjumbo) |     \
1012                                (1ULL << EF10_STAT_rx_overflow) |        \
1013                                (1ULL << EF10_STAT_rx_nodesc_drops) |    \
1014                                (1ULL << GENERIC_STAT_rx_nodesc_trunc) | \
1015                                (1ULL << GENERIC_STAT_rx_noskb_drops))
1016
1017 /* These statistics are only provided by the 10G MAC.  For a 10G/40G
1018  * switchable port we do not expose these because they might not
1019  * include all the packets they should.
1020  */
1021 #define HUNT_10G_ONLY_STAT_MASK ((1ULL << EF10_STAT_tx_control) |       \
1022                                  (1ULL << EF10_STAT_tx_lt64) |          \
1023                                  (1ULL << EF10_STAT_tx_64) |            \
1024                                  (1ULL << EF10_STAT_tx_65_to_127) |     \
1025                                  (1ULL << EF10_STAT_tx_128_to_255) |    \
1026                                  (1ULL << EF10_STAT_tx_256_to_511) |    \
1027                                  (1ULL << EF10_STAT_tx_512_to_1023) |   \
1028                                  (1ULL << EF10_STAT_tx_1024_to_15xx) |  \
1029                                  (1ULL << EF10_STAT_tx_15xx_to_jumbo))
1030
1031 /* These statistics are only provided by the 40G MAC.  For a 10G/40G
1032  * switchable port we do expose these because the errors will otherwise
1033  * be silent.
1034  */
1035 #define HUNT_40G_EXTRA_STAT_MASK ((1ULL << EF10_STAT_rx_align_error) |  \
1036                                   (1ULL << EF10_STAT_rx_length_error))
1037
1038 /* These statistics are only provided if the firmware supports the
1039  * capability PM_AND_RXDP_COUNTERS.
1040  */
1041 #define HUNT_PM_AND_RXDP_STAT_MASK (                                    \
1042         (1ULL << EF10_STAT_rx_pm_trunc_bb_overflow) |                   \
1043         (1ULL << EF10_STAT_rx_pm_discard_bb_overflow) |                 \
1044         (1ULL << EF10_STAT_rx_pm_trunc_vfifo_full) |                    \
1045         (1ULL << EF10_STAT_rx_pm_discard_vfifo_full) |                  \
1046         (1ULL << EF10_STAT_rx_pm_trunc_qbb) |                           \
1047         (1ULL << EF10_STAT_rx_pm_discard_qbb) |                         \
1048         (1ULL << EF10_STAT_rx_pm_discard_mapping) |                     \
1049         (1ULL << EF10_STAT_rx_dp_q_disabled_packets) |                  \
1050         (1ULL << EF10_STAT_rx_dp_di_dropped_packets) |                  \
1051         (1ULL << EF10_STAT_rx_dp_streaming_packets) |                   \
1052         (1ULL << EF10_STAT_rx_dp_hlb_fetch) |                           \
1053         (1ULL << EF10_STAT_rx_dp_hlb_wait))
1054
1055 static u64 efx_ef10_raw_stat_mask(struct efx_nic *efx)
1056 {
1057         u64 raw_mask = HUNT_COMMON_STAT_MASK;
1058         u32 port_caps = efx_mcdi_phy_get_caps(efx);
1059         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1060
1061         if (port_caps & (1 << MC_CMD_PHY_CAP_40000FDX_LBN))
1062                 raw_mask |= HUNT_40G_EXTRA_STAT_MASK;
1063         else
1064                 raw_mask |= HUNT_10G_ONLY_STAT_MASK;
1065
1066         if (nic_data->datapath_caps &
1067             (1 << MC_CMD_GET_CAPABILITIES_OUT_PM_AND_RXDP_COUNTERS_LBN))
1068                 raw_mask |= HUNT_PM_AND_RXDP_STAT_MASK;
1069
1070         return raw_mask;
1071 }
1072
1073 static void efx_ef10_get_stat_mask(struct efx_nic *efx, unsigned long *mask)
1074 {
1075         u64 raw_mask = efx_ef10_raw_stat_mask(efx);
1076
1077 #if BITS_PER_LONG == 64
1078         mask[0] = raw_mask;
1079 #else
1080         mask[0] = raw_mask & 0xffffffff;
1081         mask[1] = raw_mask >> 32;
1082 #endif
1083 }
1084
1085 static size_t efx_ef10_describe_stats(struct efx_nic *efx, u8 *names)
1086 {
1087         DECLARE_BITMAP(mask, EF10_STAT_COUNT);
1088
1089         efx_ef10_get_stat_mask(efx, mask);
1090         return efx_nic_describe_stats(efx_ef10_stat_desc, EF10_STAT_COUNT,
1091                                       mask, names);
1092 }
1093
1094 static int efx_ef10_try_update_nic_stats(struct efx_nic *efx)
1095 {
1096         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1097         DECLARE_BITMAP(mask, EF10_STAT_COUNT);
1098         __le64 generation_start, generation_end;
1099         u64 *stats = nic_data->stats;
1100         __le64 *dma_stats;
1101
1102         efx_ef10_get_stat_mask(efx, mask);
1103
1104         dma_stats = efx->stats_buffer.addr;
1105         nic_data = efx->nic_data;
1106
1107         generation_end = dma_stats[MC_CMD_MAC_GENERATION_END];
1108         if (generation_end == EFX_MC_STATS_GENERATION_INVALID)
1109                 return 0;
1110         rmb();
1111         efx_nic_update_stats(efx_ef10_stat_desc, EF10_STAT_COUNT, mask,
1112                              stats, efx->stats_buffer.addr, false);
1113         rmb();
1114         generation_start = dma_stats[MC_CMD_MAC_GENERATION_START];
1115         if (generation_end != generation_start)
1116                 return -EAGAIN;
1117
1118         /* Update derived statistics */
1119         efx_nic_fix_nodesc_drop_stat(efx, &stats[EF10_STAT_rx_nodesc_drops]);
1120         stats[EF10_STAT_rx_good_bytes] =
1121                 stats[EF10_STAT_rx_bytes] -
1122                 stats[EF10_STAT_rx_bytes_minus_good_bytes];
1123         efx_update_diff_stat(&stats[EF10_STAT_rx_bad_bytes],
1124                              stats[EF10_STAT_rx_bytes_minus_good_bytes]);
1125         efx_update_sw_stats(efx, stats);
1126         return 0;
1127 }
1128
1129
1130 static size_t efx_ef10_update_stats(struct efx_nic *efx, u64 *full_stats,
1131                                     struct rtnl_link_stats64 *core_stats)
1132 {
1133         DECLARE_BITMAP(mask, EF10_STAT_COUNT);
1134         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1135         u64 *stats = nic_data->stats;
1136         size_t stats_count = 0, index;
1137         int retry;
1138
1139         efx_ef10_get_stat_mask(efx, mask);
1140
1141         /* If we're unlucky enough to read statistics during the DMA, wait
1142          * up to 10ms for it to finish (typically takes <500us)
1143          */
1144         for (retry = 0; retry < 100; ++retry) {
1145                 if (efx_ef10_try_update_nic_stats(efx) == 0)
1146                         break;
1147                 udelay(100);
1148         }
1149
1150         if (full_stats) {
1151                 for_each_set_bit(index, mask, EF10_STAT_COUNT) {
1152                         if (efx_ef10_stat_desc[index].name) {
1153                                 *full_stats++ = stats[index];
1154                                 ++stats_count;
1155                         }
1156                 }
1157         }
1158
1159         if (core_stats) {
1160                 core_stats->rx_packets = stats[EF10_STAT_rx_packets];
1161                 core_stats->tx_packets = stats[EF10_STAT_tx_packets];
1162                 core_stats->rx_bytes = stats[EF10_STAT_rx_bytes];
1163                 core_stats->tx_bytes = stats[EF10_STAT_tx_bytes];
1164                 core_stats->rx_dropped = stats[EF10_STAT_rx_nodesc_drops] +
1165                                          stats[GENERIC_STAT_rx_nodesc_trunc] +
1166                                          stats[GENERIC_STAT_rx_noskb_drops];
1167                 core_stats->multicast = stats[EF10_STAT_rx_multicast];
1168                 core_stats->rx_length_errors =
1169                         stats[EF10_STAT_rx_gtjumbo] +
1170                         stats[EF10_STAT_rx_length_error];
1171                 core_stats->rx_crc_errors = stats[EF10_STAT_rx_bad];
1172                 core_stats->rx_frame_errors = stats[EF10_STAT_rx_align_error];
1173                 core_stats->rx_fifo_errors = stats[EF10_STAT_rx_overflow];
1174                 core_stats->rx_errors = (core_stats->rx_length_errors +
1175                                          core_stats->rx_crc_errors +
1176                                          core_stats->rx_frame_errors);
1177         }
1178
1179         return stats_count;
1180 }
1181
1182 static void efx_ef10_push_irq_moderation(struct efx_channel *channel)
1183 {
1184         struct efx_nic *efx = channel->efx;
1185         unsigned int mode, value;
1186         efx_dword_t timer_cmd;
1187
1188         if (channel->irq_moderation) {
1189                 mode = 3;
1190                 value = channel->irq_moderation - 1;
1191         } else {
1192                 mode = 0;
1193                 value = 0;
1194         }
1195
1196         if (EFX_EF10_WORKAROUND_35388(efx)) {
1197                 EFX_POPULATE_DWORD_3(timer_cmd, ERF_DD_EVQ_IND_TIMER_FLAGS,
1198                                      EFE_DD_EVQ_IND_TIMER_FLAGS,
1199                                      ERF_DD_EVQ_IND_TIMER_MODE, mode,
1200                                      ERF_DD_EVQ_IND_TIMER_VAL, value);
1201                 efx_writed_page(efx, &timer_cmd, ER_DD_EVQ_INDIRECT,
1202                                 channel->channel);
1203         } else {
1204                 EFX_POPULATE_DWORD_2(timer_cmd, ERF_DZ_TC_TIMER_MODE, mode,
1205                                      ERF_DZ_TC_TIMER_VAL, value);
1206                 efx_writed_page(efx, &timer_cmd, ER_DZ_EVQ_TMR,
1207                                 channel->channel);
1208         }
1209 }
1210
1211 static void efx_ef10_get_wol_vf(struct efx_nic *efx,
1212                                 struct ethtool_wolinfo *wol) {}
1213
1214 static int efx_ef10_set_wol_vf(struct efx_nic *efx, u32 type)
1215 {
1216         return -EOPNOTSUPP;
1217 }
1218
1219 static void efx_ef10_get_wol(struct efx_nic *efx, struct ethtool_wolinfo *wol)
1220 {
1221         wol->supported = 0;
1222         wol->wolopts = 0;
1223         memset(&wol->sopass, 0, sizeof(wol->sopass));
1224 }
1225
1226 static int efx_ef10_set_wol(struct efx_nic *efx, u32 type)
1227 {
1228         if (type != 0)
1229                 return -EINVAL;
1230         return 0;
1231 }
1232
1233 static void efx_ef10_mcdi_request(struct efx_nic *efx,
1234                                   const efx_dword_t *hdr, size_t hdr_len,
1235                                   const efx_dword_t *sdu, size_t sdu_len)
1236 {
1237         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1238         u8 *pdu = nic_data->mcdi_buf.addr;
1239
1240         memcpy(pdu, hdr, hdr_len);
1241         memcpy(pdu + hdr_len, sdu, sdu_len);
1242         wmb();
1243
1244         /* The hardware provides 'low' and 'high' (doorbell) registers
1245          * for passing the 64-bit address of an MCDI request to
1246          * firmware.  However the dwords are swapped by firmware.  The
1247          * least significant bits of the doorbell are then 0 for all
1248          * MCDI requests due to alignment.
1249          */
1250         _efx_writed(efx, cpu_to_le32((u64)nic_data->mcdi_buf.dma_addr >> 32),
1251                     ER_DZ_MC_DB_LWRD);
1252         _efx_writed(efx, cpu_to_le32((u32)nic_data->mcdi_buf.dma_addr),
1253                     ER_DZ_MC_DB_HWRD);
1254 }
1255
1256 static bool efx_ef10_mcdi_poll_response(struct efx_nic *efx)
1257 {
1258         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1259         const efx_dword_t hdr = *(const efx_dword_t *)nic_data->mcdi_buf.addr;
1260
1261         rmb();
1262         return EFX_DWORD_FIELD(hdr, MCDI_HEADER_RESPONSE);
1263 }
1264
1265 static void
1266 efx_ef10_mcdi_read_response(struct efx_nic *efx, efx_dword_t *outbuf,
1267                             size_t offset, size_t outlen)
1268 {
1269         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1270         const u8 *pdu = nic_data->mcdi_buf.addr;
1271
1272         memcpy(outbuf, pdu + offset, outlen);
1273 }
1274
1275 static int efx_ef10_mcdi_poll_reboot(struct efx_nic *efx)
1276 {
1277         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1278         int rc;
1279
1280         rc = efx_ef10_get_warm_boot_count(efx);
1281         if (rc < 0) {
1282                 /* The firmware is presumably in the process of
1283                  * rebooting.  However, we are supposed to report each
1284                  * reboot just once, so we must only do that once we
1285                  * can read and store the updated warm boot count.
1286                  */
1287                 return 0;
1288         }
1289
1290         if (rc == nic_data->warm_boot_count)
1291                 return 0;
1292
1293         nic_data->warm_boot_count = rc;
1294
1295         /* All our allocations have been reset */
1296         efx_ef10_reset_mc_allocations(efx);
1297
1298         /* Driver-created vswitches and vports must be re-created */
1299         nic_data->must_probe_vswitching = true;
1300         nic_data->vport_id = EVB_PORT_ID_ASSIGNED;
1301
1302         /* The datapath firmware might have been changed */
1303         nic_data->must_check_datapath_caps = true;
1304
1305         /* MAC statistics have been cleared on the NIC; clear the local
1306          * statistic that we update with efx_update_diff_stat().
1307          */
1308         nic_data->stats[EF10_STAT_rx_bad_bytes] = 0;
1309
1310         return -EIO;
1311 }
1312
1313 /* Handle an MSI interrupt
1314  *
1315  * Handle an MSI hardware interrupt.  This routine schedules event
1316  * queue processing.  No interrupt acknowledgement cycle is necessary.
1317  * Also, we never need to check that the interrupt is for us, since
1318  * MSI interrupts cannot be shared.
1319  */
1320 static irqreturn_t efx_ef10_msi_interrupt(int irq, void *dev_id)
1321 {
1322         struct efx_msi_context *context = dev_id;
1323         struct efx_nic *efx = context->efx;
1324
1325         netif_vdbg(efx, intr, efx->net_dev,
1326                    "IRQ %d on CPU %d\n", irq, raw_smp_processor_id());
1327
1328         if (likely(ACCESS_ONCE(efx->irq_soft_enabled))) {
1329                 /* Note test interrupts */
1330                 if (context->index == efx->irq_level)
1331                         efx->last_irq_cpu = raw_smp_processor_id();
1332
1333                 /* Schedule processing of the channel */
1334                 efx_schedule_channel_irq(efx->channel[context->index]);
1335         }
1336
1337         return IRQ_HANDLED;
1338 }
1339
1340 static irqreturn_t efx_ef10_legacy_interrupt(int irq, void *dev_id)
1341 {
1342         struct efx_nic *efx = dev_id;
1343         bool soft_enabled = ACCESS_ONCE(efx->irq_soft_enabled);
1344         struct efx_channel *channel;
1345         efx_dword_t reg;
1346         u32 queues;
1347
1348         /* Read the ISR which also ACKs the interrupts */
1349         efx_readd(efx, &reg, ER_DZ_BIU_INT_ISR);
1350         queues = EFX_DWORD_FIELD(reg, ERF_DZ_ISR_REG);
1351
1352         if (queues == 0)
1353                 return IRQ_NONE;
1354
1355         if (likely(soft_enabled)) {
1356                 /* Note test interrupts */
1357                 if (queues & (1U << efx->irq_level))
1358                         efx->last_irq_cpu = raw_smp_processor_id();
1359
1360                 efx_for_each_channel(channel, efx) {
1361                         if (queues & 1)
1362                                 efx_schedule_channel_irq(channel);
1363                         queues >>= 1;
1364                 }
1365         }
1366
1367         netif_vdbg(efx, intr, efx->net_dev,
1368                    "IRQ %d on CPU %d status " EFX_DWORD_FMT "\n",
1369                    irq, raw_smp_processor_id(), EFX_DWORD_VAL(reg));
1370
1371         return IRQ_HANDLED;
1372 }
1373
1374 static void efx_ef10_irq_test_generate(struct efx_nic *efx)
1375 {
1376         MCDI_DECLARE_BUF(inbuf, MC_CMD_TRIGGER_INTERRUPT_IN_LEN);
1377
1378         BUILD_BUG_ON(MC_CMD_TRIGGER_INTERRUPT_OUT_LEN != 0);
1379
1380         MCDI_SET_DWORD(inbuf, TRIGGER_INTERRUPT_IN_INTR_LEVEL, efx->irq_level);
1381         (void) efx_mcdi_rpc(efx, MC_CMD_TRIGGER_INTERRUPT,
1382                             inbuf, sizeof(inbuf), NULL, 0, NULL);
1383 }
1384
1385 static int efx_ef10_tx_probe(struct efx_tx_queue *tx_queue)
1386 {
1387         return efx_nic_alloc_buffer(tx_queue->efx, &tx_queue->txd.buf,
1388                                     (tx_queue->ptr_mask + 1) *
1389                                     sizeof(efx_qword_t),
1390                                     GFP_KERNEL);
1391 }
1392
1393 /* This writes to the TX_DESC_WPTR and also pushes data */
1394 static inline void efx_ef10_push_tx_desc(struct efx_tx_queue *tx_queue,
1395                                          const efx_qword_t *txd)
1396 {
1397         unsigned int write_ptr;
1398         efx_oword_t reg;
1399
1400         write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
1401         EFX_POPULATE_OWORD_1(reg, ERF_DZ_TX_DESC_WPTR, write_ptr);
1402         reg.qword[0] = *txd;
1403         efx_writeo_page(tx_queue->efx, &reg,
1404                         ER_DZ_TX_DESC_UPD, tx_queue->queue);
1405 }
1406
1407 static void efx_ef10_tx_init(struct efx_tx_queue *tx_queue)
1408 {
1409         MCDI_DECLARE_BUF(inbuf, MC_CMD_INIT_TXQ_IN_LEN(EFX_MAX_DMAQ_SIZE * 8 /
1410                                                        EFX_BUF_SIZE));
1411         bool csum_offload = tx_queue->queue & EFX_TXQ_TYPE_OFFLOAD;
1412         size_t entries = tx_queue->txd.buf.len / EFX_BUF_SIZE;
1413         struct efx_channel *channel = tx_queue->channel;
1414         struct efx_nic *efx = tx_queue->efx;
1415         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1416         size_t inlen;
1417         dma_addr_t dma_addr;
1418         efx_qword_t *txd;
1419         int rc;
1420         int i;
1421         BUILD_BUG_ON(MC_CMD_INIT_TXQ_OUT_LEN != 0);
1422
1423         MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_SIZE, tx_queue->ptr_mask + 1);
1424         MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_TARGET_EVQ, channel->channel);
1425         MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_LABEL, tx_queue->queue);
1426         MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_INSTANCE, tx_queue->queue);
1427         MCDI_POPULATE_DWORD_2(inbuf, INIT_TXQ_IN_FLAGS,
1428                               INIT_TXQ_IN_FLAG_IP_CSUM_DIS, !csum_offload,
1429                               INIT_TXQ_IN_FLAG_TCP_CSUM_DIS, !csum_offload);
1430         MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_OWNER_ID, 0);
1431         MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_PORT_ID, nic_data->vport_id);
1432
1433         dma_addr = tx_queue->txd.buf.dma_addr;
1434
1435         netif_dbg(efx, hw, efx->net_dev, "pushing TXQ %d. %zu entries (%llx)\n",
1436                   tx_queue->queue, entries, (u64)dma_addr);
1437
1438         for (i = 0; i < entries; ++i) {
1439                 MCDI_SET_ARRAY_QWORD(inbuf, INIT_TXQ_IN_DMA_ADDR, i, dma_addr);
1440                 dma_addr += EFX_BUF_SIZE;
1441         }
1442
1443         inlen = MC_CMD_INIT_TXQ_IN_LEN(entries);
1444
1445         rc = efx_mcdi_rpc(efx, MC_CMD_INIT_TXQ, inbuf, inlen,
1446                           NULL, 0, NULL);
1447         if (rc)
1448                 goto fail;
1449
1450         /* A previous user of this TX queue might have set us up the
1451          * bomb by writing a descriptor to the TX push collector but
1452          * not the doorbell.  (Each collector belongs to a port, not a
1453          * queue or function, so cannot easily be reset.)  We must
1454          * attempt to push a no-op descriptor in its place.
1455          */
1456         tx_queue->buffer[0].flags = EFX_TX_BUF_OPTION;
1457         tx_queue->insert_count = 1;
1458         txd = efx_tx_desc(tx_queue, 0);
1459         EFX_POPULATE_QWORD_4(*txd,
1460                              ESF_DZ_TX_DESC_IS_OPT, true,
1461                              ESF_DZ_TX_OPTION_TYPE,
1462                              ESE_DZ_TX_OPTION_DESC_CRC_CSUM,
1463                              ESF_DZ_TX_OPTION_UDP_TCP_CSUM, csum_offload,
1464                              ESF_DZ_TX_OPTION_IP_CSUM, csum_offload);
1465         tx_queue->write_count = 1;
1466         wmb();
1467         efx_ef10_push_tx_desc(tx_queue, txd);
1468
1469         return;
1470
1471 fail:
1472         netdev_WARN(efx->net_dev, "failed to initialise TXQ %d\n",
1473                     tx_queue->queue);
1474 }
1475
1476 static void efx_ef10_tx_fini(struct efx_tx_queue *tx_queue)
1477 {
1478         MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_TXQ_IN_LEN);
1479         MCDI_DECLARE_BUF_ERR(outbuf);
1480         struct efx_nic *efx = tx_queue->efx;
1481         size_t outlen;
1482         int rc;
1483
1484         MCDI_SET_DWORD(inbuf, FINI_TXQ_IN_INSTANCE,
1485                        tx_queue->queue);
1486
1487         rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_TXQ, inbuf, sizeof(inbuf),
1488                           outbuf, sizeof(outbuf), &outlen);
1489
1490         if (rc && rc != -EALREADY)
1491                 goto fail;
1492
1493         return;
1494
1495 fail:
1496         efx_mcdi_display_error(efx, MC_CMD_FINI_TXQ, MC_CMD_FINI_TXQ_IN_LEN,
1497                                outbuf, outlen, rc);
1498 }
1499
1500 static void efx_ef10_tx_remove(struct efx_tx_queue *tx_queue)
1501 {
1502         efx_nic_free_buffer(tx_queue->efx, &tx_queue->txd.buf);
1503 }
1504
1505 /* This writes to the TX_DESC_WPTR; write pointer for TX descriptor ring */
1506 static inline void efx_ef10_notify_tx_desc(struct efx_tx_queue *tx_queue)
1507 {
1508         unsigned int write_ptr;
1509         efx_dword_t reg;
1510
1511         write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
1512         EFX_POPULATE_DWORD_1(reg, ERF_DZ_TX_DESC_WPTR_DWORD, write_ptr);
1513         efx_writed_page(tx_queue->efx, &reg,
1514                         ER_DZ_TX_DESC_UPD_DWORD, tx_queue->queue);
1515 }
1516
1517 static void efx_ef10_tx_write(struct efx_tx_queue *tx_queue)
1518 {
1519         unsigned int old_write_count = tx_queue->write_count;
1520         struct efx_tx_buffer *buffer;
1521         unsigned int write_ptr;
1522         efx_qword_t *txd;
1523
1524         BUG_ON(tx_queue->write_count == tx_queue->insert_count);
1525
1526         do {
1527                 write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
1528                 buffer = &tx_queue->buffer[write_ptr];
1529                 txd = efx_tx_desc(tx_queue, write_ptr);
1530                 ++tx_queue->write_count;
1531
1532                 /* Create TX descriptor ring entry */
1533                 if (buffer->flags & EFX_TX_BUF_OPTION) {
1534                         *txd = buffer->option;
1535                 } else {
1536                         BUILD_BUG_ON(EFX_TX_BUF_CONT != 1);
1537                         EFX_POPULATE_QWORD_3(
1538                                 *txd,
1539                                 ESF_DZ_TX_KER_CONT,
1540                                 buffer->flags & EFX_TX_BUF_CONT,
1541                                 ESF_DZ_TX_KER_BYTE_CNT, buffer->len,
1542                                 ESF_DZ_TX_KER_BUF_ADDR, buffer->dma_addr);
1543                 }
1544         } while (tx_queue->write_count != tx_queue->insert_count);
1545
1546         wmb(); /* Ensure descriptors are written before they are fetched */
1547
1548         if (efx_nic_may_push_tx_desc(tx_queue, old_write_count)) {
1549                 txd = efx_tx_desc(tx_queue,
1550                                   old_write_count & tx_queue->ptr_mask);
1551                 efx_ef10_push_tx_desc(tx_queue, txd);
1552                 ++tx_queue->pushes;
1553         } else {
1554                 efx_ef10_notify_tx_desc(tx_queue);
1555         }
1556 }
1557
1558 static int efx_ef10_alloc_rss_context(struct efx_nic *efx, u32 *context,
1559                                       bool exclusive, unsigned *context_size)
1560 {
1561         MCDI_DECLARE_BUF(inbuf, MC_CMD_RSS_CONTEXT_ALLOC_IN_LEN);
1562         MCDI_DECLARE_BUF(outbuf, MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN);
1563         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1564         size_t outlen;
1565         int rc;
1566         u32 alloc_type = exclusive ?
1567                                 MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_EXCLUSIVE :
1568                                 MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_SHARED;
1569         unsigned rss_spread = exclusive ?
1570                                 efx->rss_spread :
1571                                 min(rounddown_pow_of_two(efx->rss_spread),
1572                                     EFX_EF10_MAX_SHARED_RSS_CONTEXT_SIZE);
1573
1574         if (!exclusive && rss_spread == 1) {
1575                 *context = EFX_EF10_RSS_CONTEXT_INVALID;
1576                 if (context_size)
1577                         *context_size = 1;
1578                 return 0;
1579         }
1580
1581         MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_UPSTREAM_PORT_ID,
1582                        nic_data->vport_id);
1583         MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_TYPE, alloc_type);
1584         MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_NUM_QUEUES, rss_spread);
1585
1586         rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_ALLOC, inbuf, sizeof(inbuf),
1587                 outbuf, sizeof(outbuf), &outlen);
1588         if (rc != 0)
1589                 return rc;
1590
1591         if (outlen < MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN)
1592                 return -EIO;
1593
1594         *context = MCDI_DWORD(outbuf, RSS_CONTEXT_ALLOC_OUT_RSS_CONTEXT_ID);
1595
1596         if (context_size)
1597                 *context_size = rss_spread;
1598
1599         return 0;
1600 }
1601
1602 static void efx_ef10_free_rss_context(struct efx_nic *efx, u32 context)
1603 {
1604         MCDI_DECLARE_BUF(inbuf, MC_CMD_RSS_CONTEXT_FREE_IN_LEN);
1605         int rc;
1606
1607         MCDI_SET_DWORD(inbuf, RSS_CONTEXT_FREE_IN_RSS_CONTEXT_ID,
1608                        context);
1609
1610         rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_FREE, inbuf, sizeof(inbuf),
1611                             NULL, 0, NULL);
1612         WARN_ON(rc != 0);
1613 }
1614
1615 static int efx_ef10_populate_rss_table(struct efx_nic *efx, u32 context,
1616                                        const u32 *rx_indir_table)
1617 {
1618         MCDI_DECLARE_BUF(tablebuf, MC_CMD_RSS_CONTEXT_SET_TABLE_IN_LEN);
1619         MCDI_DECLARE_BUF(keybuf, MC_CMD_RSS_CONTEXT_SET_KEY_IN_LEN);
1620         int i, rc;
1621
1622         MCDI_SET_DWORD(tablebuf, RSS_CONTEXT_SET_TABLE_IN_RSS_CONTEXT_ID,
1623                        context);
1624         BUILD_BUG_ON(ARRAY_SIZE(efx->rx_indir_table) !=
1625                      MC_CMD_RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE_LEN);
1626
1627         for (i = 0; i < ARRAY_SIZE(efx->rx_indir_table); ++i)
1628                 MCDI_PTR(tablebuf,
1629                          RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE)[i] =
1630                                 (u8) rx_indir_table[i];
1631
1632         rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_SET_TABLE, tablebuf,
1633                           sizeof(tablebuf), NULL, 0, NULL);
1634         if (rc != 0)
1635                 return rc;
1636
1637         MCDI_SET_DWORD(keybuf, RSS_CONTEXT_SET_KEY_IN_RSS_CONTEXT_ID,
1638                        context);
1639         BUILD_BUG_ON(ARRAY_SIZE(efx->rx_hash_key) !=
1640                      MC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_LEN);
1641         for (i = 0; i < ARRAY_SIZE(efx->rx_hash_key); ++i)
1642                 MCDI_PTR(keybuf, RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY)[i] =
1643                         efx->rx_hash_key[i];
1644
1645         return efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_SET_KEY, keybuf,
1646                             sizeof(keybuf), NULL, 0, NULL);
1647 }
1648
1649 static void efx_ef10_rx_free_indir_table(struct efx_nic *efx)
1650 {
1651         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1652
1653         if (nic_data->rx_rss_context != EFX_EF10_RSS_CONTEXT_INVALID)
1654                 efx_ef10_free_rss_context(efx, nic_data->rx_rss_context);
1655         nic_data->rx_rss_context = EFX_EF10_RSS_CONTEXT_INVALID;
1656 }
1657
1658 static int efx_ef10_rx_push_shared_rss_config(struct efx_nic *efx,
1659                                               unsigned *context_size)
1660 {
1661         u32 new_rx_rss_context;
1662         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1663         int rc = efx_ef10_alloc_rss_context(efx, &new_rx_rss_context,
1664                                             false, context_size);
1665
1666         if (rc != 0)
1667                 return rc;
1668
1669         nic_data->rx_rss_context = new_rx_rss_context;
1670         nic_data->rx_rss_context_exclusive = false;
1671         efx_set_default_rx_indir_table(efx);
1672         return 0;
1673 }
1674
1675 static int efx_ef10_rx_push_exclusive_rss_config(struct efx_nic *efx,
1676                                                  const u32 *rx_indir_table)
1677 {
1678         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1679         int rc;
1680         u32 new_rx_rss_context;
1681
1682         if (nic_data->rx_rss_context == EFX_EF10_RSS_CONTEXT_INVALID ||
1683             !nic_data->rx_rss_context_exclusive) {
1684                 rc = efx_ef10_alloc_rss_context(efx, &new_rx_rss_context,
1685                                                 true, NULL);
1686                 if (rc == -EOPNOTSUPP)
1687                         return rc;
1688                 else if (rc != 0)
1689                         goto fail1;
1690         } else {
1691                 new_rx_rss_context = nic_data->rx_rss_context;
1692         }
1693
1694         rc = efx_ef10_populate_rss_table(efx, new_rx_rss_context,
1695                                          rx_indir_table);
1696         if (rc != 0)
1697                 goto fail2;
1698
1699         if (nic_data->rx_rss_context != new_rx_rss_context)
1700                 efx_ef10_rx_free_indir_table(efx);
1701         nic_data->rx_rss_context = new_rx_rss_context;
1702         nic_data->rx_rss_context_exclusive = true;
1703         if (rx_indir_table != efx->rx_indir_table)
1704                 memcpy(efx->rx_indir_table, rx_indir_table,
1705                        sizeof(efx->rx_indir_table));
1706         return 0;
1707
1708 fail2:
1709         if (new_rx_rss_context != nic_data->rx_rss_context)
1710                 efx_ef10_free_rss_context(efx, new_rx_rss_context);
1711 fail1:
1712         netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
1713         return rc;
1714 }
1715
1716 static int efx_ef10_pf_rx_push_rss_config(struct efx_nic *efx, bool user,
1717                                           const u32 *rx_indir_table)
1718 {
1719         int rc;
1720
1721         if (efx->rss_spread == 1)
1722                 return 0;
1723
1724         rc = efx_ef10_rx_push_exclusive_rss_config(efx, rx_indir_table);
1725
1726         if (rc == -ENOBUFS && !user) {
1727                 unsigned context_size;
1728                 bool mismatch = false;
1729                 size_t i;
1730
1731                 for (i = 0; i < ARRAY_SIZE(efx->rx_indir_table) && !mismatch;
1732                      i++)
1733                         mismatch = rx_indir_table[i] !=
1734                                 ethtool_rxfh_indir_default(i, efx->rss_spread);
1735
1736                 rc = efx_ef10_rx_push_shared_rss_config(efx, &context_size);
1737                 if (rc == 0) {
1738                         if (context_size != efx->rss_spread)
1739                                 netif_warn(efx, probe, efx->net_dev,
1740                                            "Could not allocate an exclusive RSS"
1741                                            " context; allocated a shared one of"
1742                                            " different size."
1743                                            " Wanted %u, got %u.\n",
1744                                            efx->rss_spread, context_size);
1745                         else if (mismatch)
1746                                 netif_warn(efx, probe, efx->net_dev,
1747                                            "Could not allocate an exclusive RSS"
1748                                            " context; allocated a shared one but"
1749                                            " could not apply custom"
1750                                            " indirection.\n");
1751                         else
1752                                 netif_info(efx, probe, efx->net_dev,
1753                                            "Could not allocate an exclusive RSS"
1754                                            " context; allocated a shared one.\n");
1755                 }
1756         }
1757         return rc;
1758 }
1759
1760 static int efx_ef10_vf_rx_push_rss_config(struct efx_nic *efx, bool user,
1761                                           const u32 *rx_indir_table
1762                                           __attribute__ ((unused)))
1763 {
1764         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1765
1766         if (user)
1767                 return -EOPNOTSUPP;
1768         if (nic_data->rx_rss_context != EFX_EF10_RSS_CONTEXT_INVALID)
1769                 return 0;
1770         return efx_ef10_rx_push_shared_rss_config(efx, NULL);
1771 }
1772
1773 static int efx_ef10_rx_probe(struct efx_rx_queue *rx_queue)
1774 {
1775         return efx_nic_alloc_buffer(rx_queue->efx, &rx_queue->rxd.buf,
1776                                     (rx_queue->ptr_mask + 1) *
1777                                     sizeof(efx_qword_t),
1778                                     GFP_KERNEL);
1779 }
1780
1781 static void efx_ef10_rx_init(struct efx_rx_queue *rx_queue)
1782 {
1783         MCDI_DECLARE_BUF(inbuf,
1784                          MC_CMD_INIT_RXQ_IN_LEN(EFX_MAX_DMAQ_SIZE * 8 /
1785                                                 EFX_BUF_SIZE));
1786         struct efx_channel *channel = efx_rx_queue_channel(rx_queue);
1787         size_t entries = rx_queue->rxd.buf.len / EFX_BUF_SIZE;
1788         struct efx_nic *efx = rx_queue->efx;
1789         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1790         size_t inlen;
1791         dma_addr_t dma_addr;
1792         int rc;
1793         int i;
1794         BUILD_BUG_ON(MC_CMD_INIT_RXQ_OUT_LEN != 0);
1795
1796         rx_queue->scatter_n = 0;
1797         rx_queue->scatter_len = 0;
1798
1799         MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_SIZE, rx_queue->ptr_mask + 1);
1800         MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_TARGET_EVQ, channel->channel);
1801         MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_LABEL, efx_rx_queue_index(rx_queue));
1802         MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_INSTANCE,
1803                        efx_rx_queue_index(rx_queue));
1804         MCDI_POPULATE_DWORD_2(inbuf, INIT_RXQ_IN_FLAGS,
1805                               INIT_RXQ_IN_FLAG_PREFIX, 1,
1806                               INIT_RXQ_IN_FLAG_TIMESTAMP, 1);
1807         MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_OWNER_ID, 0);
1808         MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_PORT_ID, nic_data->vport_id);
1809
1810         dma_addr = rx_queue->rxd.buf.dma_addr;
1811
1812         netif_dbg(efx, hw, efx->net_dev, "pushing RXQ %d. %zu entries (%llx)\n",
1813                   efx_rx_queue_index(rx_queue), entries, (u64)dma_addr);
1814
1815         for (i = 0; i < entries; ++i) {
1816                 MCDI_SET_ARRAY_QWORD(inbuf, INIT_RXQ_IN_DMA_ADDR, i, dma_addr);
1817                 dma_addr += EFX_BUF_SIZE;
1818         }
1819
1820         inlen = MC_CMD_INIT_RXQ_IN_LEN(entries);
1821
1822         rc = efx_mcdi_rpc(efx, MC_CMD_INIT_RXQ, inbuf, inlen,
1823                           NULL, 0, NULL);
1824         if (rc)
1825                 netdev_WARN(efx->net_dev, "failed to initialise RXQ %d\n",
1826                             efx_rx_queue_index(rx_queue));
1827 }
1828
1829 static void efx_ef10_rx_fini(struct efx_rx_queue *rx_queue)
1830 {
1831         MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_RXQ_IN_LEN);
1832         MCDI_DECLARE_BUF_ERR(outbuf);
1833         struct efx_nic *efx = rx_queue->efx;
1834         size_t outlen;
1835         int rc;
1836
1837         MCDI_SET_DWORD(inbuf, FINI_RXQ_IN_INSTANCE,
1838                        efx_rx_queue_index(rx_queue));
1839
1840         rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_RXQ, inbuf, sizeof(inbuf),
1841                           outbuf, sizeof(outbuf), &outlen);
1842
1843         if (rc && rc != -EALREADY)
1844                 goto fail;
1845
1846         return;
1847
1848 fail:
1849         efx_mcdi_display_error(efx, MC_CMD_FINI_RXQ, MC_CMD_FINI_RXQ_IN_LEN,
1850                                outbuf, outlen, rc);
1851 }
1852
1853 static void efx_ef10_rx_remove(struct efx_rx_queue *rx_queue)
1854 {
1855         efx_nic_free_buffer(rx_queue->efx, &rx_queue->rxd.buf);
1856 }
1857
1858 /* This creates an entry in the RX descriptor queue */
1859 static inline void
1860 efx_ef10_build_rx_desc(struct efx_rx_queue *rx_queue, unsigned int index)
1861 {
1862         struct efx_rx_buffer *rx_buf;
1863         efx_qword_t *rxd;
1864
1865         rxd = efx_rx_desc(rx_queue, index);
1866         rx_buf = efx_rx_buffer(rx_queue, index);
1867         EFX_POPULATE_QWORD_2(*rxd,
1868                              ESF_DZ_RX_KER_BYTE_CNT, rx_buf->len,
1869                              ESF_DZ_RX_KER_BUF_ADDR, rx_buf->dma_addr);
1870 }
1871
1872 static void efx_ef10_rx_write(struct efx_rx_queue *rx_queue)
1873 {
1874         struct efx_nic *efx = rx_queue->efx;
1875         unsigned int write_count;
1876         efx_dword_t reg;
1877
1878         /* Firmware requires that RX_DESC_WPTR be a multiple of 8 */
1879         write_count = rx_queue->added_count & ~7;
1880         if (rx_queue->notified_count == write_count)
1881                 return;
1882
1883         do
1884                 efx_ef10_build_rx_desc(
1885                         rx_queue,
1886                         rx_queue->notified_count & rx_queue->ptr_mask);
1887         while (++rx_queue->notified_count != write_count);
1888
1889         wmb();
1890         EFX_POPULATE_DWORD_1(reg, ERF_DZ_RX_DESC_WPTR,
1891                              write_count & rx_queue->ptr_mask);
1892         efx_writed_page(efx, &reg, ER_DZ_RX_DESC_UPD,
1893                         efx_rx_queue_index(rx_queue));
1894 }
1895
1896 static efx_mcdi_async_completer efx_ef10_rx_defer_refill_complete;
1897
1898 static void efx_ef10_rx_defer_refill(struct efx_rx_queue *rx_queue)
1899 {
1900         struct efx_channel *channel = efx_rx_queue_channel(rx_queue);
1901         MCDI_DECLARE_BUF(inbuf, MC_CMD_DRIVER_EVENT_IN_LEN);
1902         efx_qword_t event;
1903
1904         EFX_POPULATE_QWORD_2(event,
1905                              ESF_DZ_EV_CODE, EFX_EF10_DRVGEN_EV,
1906                              ESF_DZ_EV_DATA, EFX_EF10_REFILL);
1907
1908         MCDI_SET_DWORD(inbuf, DRIVER_EVENT_IN_EVQ, channel->channel);
1909
1910         /* MCDI_SET_QWORD is not appropriate here since EFX_POPULATE_* has
1911          * already swapped the data to little-endian order.
1912          */
1913         memcpy(MCDI_PTR(inbuf, DRIVER_EVENT_IN_DATA), &event.u64[0],
1914                sizeof(efx_qword_t));
1915
1916         efx_mcdi_rpc_async(channel->efx, MC_CMD_DRIVER_EVENT,
1917                            inbuf, sizeof(inbuf), 0,
1918                            efx_ef10_rx_defer_refill_complete, 0);
1919 }
1920
1921 static void
1922 efx_ef10_rx_defer_refill_complete(struct efx_nic *efx, unsigned long cookie,
1923                                   int rc, efx_dword_t *outbuf,
1924                                   size_t outlen_actual)
1925 {
1926         /* nothing to do */
1927 }
1928
1929 static int efx_ef10_ev_probe(struct efx_channel *channel)
1930 {
1931         return efx_nic_alloc_buffer(channel->efx, &channel->eventq.buf,
1932                                     (channel->eventq_mask + 1) *
1933                                     sizeof(efx_qword_t),
1934                                     GFP_KERNEL);
1935 }
1936
1937 static int efx_ef10_ev_init(struct efx_channel *channel)
1938 {
1939         MCDI_DECLARE_BUF(inbuf,
1940                          MC_CMD_INIT_EVQ_IN_LEN(EFX_MAX_EVQ_SIZE * 8 /
1941                                                 EFX_BUF_SIZE));
1942         MCDI_DECLARE_BUF(outbuf, MC_CMD_INIT_EVQ_OUT_LEN);
1943         size_t entries = channel->eventq.buf.len / EFX_BUF_SIZE;
1944         struct efx_nic *efx = channel->efx;
1945         struct efx_ef10_nic_data *nic_data;
1946         bool supports_rx_merge;
1947         size_t inlen, outlen;
1948         dma_addr_t dma_addr;
1949         int rc;
1950         int i;
1951
1952         nic_data = efx->nic_data;
1953         supports_rx_merge =
1954                 !!(nic_data->datapath_caps &
1955                    1 << MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN);
1956
1957         /* Fill event queue with all ones (i.e. empty events) */
1958         memset(channel->eventq.buf.addr, 0xff, channel->eventq.buf.len);
1959
1960         MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_SIZE, channel->eventq_mask + 1);
1961         MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_INSTANCE, channel->channel);
1962         /* INIT_EVQ expects index in vector table, not absolute */
1963         MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_IRQ_NUM, channel->channel);
1964         MCDI_POPULATE_DWORD_4(inbuf, INIT_EVQ_IN_FLAGS,
1965                               INIT_EVQ_IN_FLAG_INTERRUPTING, 1,
1966                               INIT_EVQ_IN_FLAG_RX_MERGE, 1,
1967                               INIT_EVQ_IN_FLAG_TX_MERGE, 1,
1968                               INIT_EVQ_IN_FLAG_CUT_THRU, !supports_rx_merge);
1969         MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_MODE,
1970                        MC_CMD_INIT_EVQ_IN_TMR_MODE_DIS);
1971         MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_LOAD, 0);
1972         MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_RELOAD, 0);
1973         MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_COUNT_MODE,
1974                        MC_CMD_INIT_EVQ_IN_COUNT_MODE_DIS);
1975         MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_COUNT_THRSHLD, 0);
1976
1977         dma_addr = channel->eventq.buf.dma_addr;
1978         for (i = 0; i < entries; ++i) {
1979                 MCDI_SET_ARRAY_QWORD(inbuf, INIT_EVQ_IN_DMA_ADDR, i, dma_addr);
1980                 dma_addr += EFX_BUF_SIZE;
1981         }
1982
1983         inlen = MC_CMD_INIT_EVQ_IN_LEN(entries);
1984
1985         rc = efx_mcdi_rpc(efx, MC_CMD_INIT_EVQ, inbuf, inlen,
1986                           outbuf, sizeof(outbuf), &outlen);
1987         /* IRQ return is ignored */
1988         return rc;
1989 }
1990
1991 static void efx_ef10_ev_fini(struct efx_channel *channel)
1992 {
1993         MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_EVQ_IN_LEN);
1994         MCDI_DECLARE_BUF_ERR(outbuf);
1995         struct efx_nic *efx = channel->efx;
1996         size_t outlen;
1997         int rc;
1998
1999         MCDI_SET_DWORD(inbuf, FINI_EVQ_IN_INSTANCE, channel->channel);
2000
2001         rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_EVQ, inbuf, sizeof(inbuf),
2002                           outbuf, sizeof(outbuf), &outlen);
2003
2004         if (rc && rc != -EALREADY)
2005                 goto fail;
2006
2007         return;
2008
2009 fail:
2010         efx_mcdi_display_error(efx, MC_CMD_FINI_EVQ, MC_CMD_FINI_EVQ_IN_LEN,
2011                                outbuf, outlen, rc);
2012 }
2013
2014 static void efx_ef10_ev_remove(struct efx_channel *channel)
2015 {
2016         efx_nic_free_buffer(channel->efx, &channel->eventq.buf);
2017 }
2018
2019 static void efx_ef10_handle_rx_wrong_queue(struct efx_rx_queue *rx_queue,
2020                                            unsigned int rx_queue_label)
2021 {
2022         struct efx_nic *efx = rx_queue->efx;
2023
2024         netif_info(efx, hw, efx->net_dev,
2025                    "rx event arrived on queue %d labeled as queue %u\n",
2026                    efx_rx_queue_index(rx_queue), rx_queue_label);
2027
2028         efx_schedule_reset(efx, RESET_TYPE_DISABLE);
2029 }
2030
2031 static void
2032 efx_ef10_handle_rx_bad_lbits(struct efx_rx_queue *rx_queue,
2033                              unsigned int actual, unsigned int expected)
2034 {
2035         unsigned int dropped = (actual - expected) & rx_queue->ptr_mask;
2036         struct efx_nic *efx = rx_queue->efx;
2037
2038         netif_info(efx, hw, efx->net_dev,
2039                    "dropped %d events (index=%d expected=%d)\n",
2040                    dropped, actual, expected);
2041
2042         efx_schedule_reset(efx, RESET_TYPE_DISABLE);
2043 }
2044
2045 /* partially received RX was aborted. clean up. */
2046 static void efx_ef10_handle_rx_abort(struct efx_rx_queue *rx_queue)
2047 {
2048         unsigned int rx_desc_ptr;
2049
2050         netif_dbg(rx_queue->efx, hw, rx_queue->efx->net_dev,
2051                   "scattered RX aborted (dropping %u buffers)\n",
2052                   rx_queue->scatter_n);
2053
2054         rx_desc_ptr = rx_queue->removed_count & rx_queue->ptr_mask;
2055
2056         efx_rx_packet(rx_queue, rx_desc_ptr, rx_queue->scatter_n,
2057                       0, EFX_RX_PKT_DISCARD);
2058
2059         rx_queue->removed_count += rx_queue->scatter_n;
2060         rx_queue->scatter_n = 0;
2061         rx_queue->scatter_len = 0;
2062         ++efx_rx_queue_channel(rx_queue)->n_rx_nodesc_trunc;
2063 }
2064
2065 static int efx_ef10_handle_rx_event(struct efx_channel *channel,
2066                                     const efx_qword_t *event)
2067 {
2068         unsigned int rx_bytes, next_ptr_lbits, rx_queue_label, rx_l4_class;
2069         unsigned int n_descs, n_packets, i;
2070         struct efx_nic *efx = channel->efx;
2071         struct efx_rx_queue *rx_queue;
2072         bool rx_cont;
2073         u16 flags = 0;
2074
2075         if (unlikely(ACCESS_ONCE(efx->reset_pending)))
2076                 return 0;
2077
2078         /* Basic packet information */
2079         rx_bytes = EFX_QWORD_FIELD(*event, ESF_DZ_RX_BYTES);
2080         next_ptr_lbits = EFX_QWORD_FIELD(*event, ESF_DZ_RX_DSC_PTR_LBITS);
2081         rx_queue_label = EFX_QWORD_FIELD(*event, ESF_DZ_RX_QLABEL);
2082         rx_l4_class = EFX_QWORD_FIELD(*event, ESF_DZ_RX_L4_CLASS);
2083         rx_cont = EFX_QWORD_FIELD(*event, ESF_DZ_RX_CONT);
2084
2085         if (EFX_QWORD_FIELD(*event, ESF_DZ_RX_DROP_EVENT))
2086                 netdev_WARN(efx->net_dev, "saw RX_DROP_EVENT: event="
2087                             EFX_QWORD_FMT "\n",
2088                             EFX_QWORD_VAL(*event));
2089
2090         rx_queue = efx_channel_get_rx_queue(channel);
2091
2092         if (unlikely(rx_queue_label != efx_rx_queue_index(rx_queue)))
2093                 efx_ef10_handle_rx_wrong_queue(rx_queue, rx_queue_label);
2094
2095         n_descs = ((next_ptr_lbits - rx_queue->removed_count) &
2096                    ((1 << ESF_DZ_RX_DSC_PTR_LBITS_WIDTH) - 1));
2097
2098         if (n_descs != rx_queue->scatter_n + 1) {
2099                 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2100
2101                 /* detect rx abort */
2102                 if (unlikely(n_descs == rx_queue->scatter_n)) {
2103                         if (rx_queue->scatter_n == 0 || rx_bytes != 0)
2104                                 netdev_WARN(efx->net_dev,
2105                                             "invalid RX abort: scatter_n=%u event="
2106                                             EFX_QWORD_FMT "\n",
2107                                             rx_queue->scatter_n,
2108                                             EFX_QWORD_VAL(*event));
2109                         efx_ef10_handle_rx_abort(rx_queue);
2110                         return 0;
2111                 }
2112
2113                 /* Check that RX completion merging is valid, i.e.
2114                  * the current firmware supports it and this is a
2115                  * non-scattered packet.
2116                  */
2117                 if (!(nic_data->datapath_caps &
2118                       (1 << MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN)) ||
2119                     rx_queue->scatter_n != 0 || rx_cont) {
2120                         efx_ef10_handle_rx_bad_lbits(
2121                                 rx_queue, next_ptr_lbits,
2122                                 (rx_queue->removed_count +
2123                                  rx_queue->scatter_n + 1) &
2124                                 ((1 << ESF_DZ_RX_DSC_PTR_LBITS_WIDTH) - 1));
2125                         return 0;
2126                 }
2127
2128                 /* Merged completion for multiple non-scattered packets */
2129                 rx_queue->scatter_n = 1;
2130                 rx_queue->scatter_len = 0;
2131                 n_packets = n_descs;
2132                 ++channel->n_rx_merge_events;
2133                 channel->n_rx_merge_packets += n_packets;
2134                 flags |= EFX_RX_PKT_PREFIX_LEN;
2135         } else {
2136                 ++rx_queue->scatter_n;
2137                 rx_queue->scatter_len += rx_bytes;
2138                 if (rx_cont)
2139                         return 0;
2140                 n_packets = 1;
2141         }
2142
2143         if (unlikely(EFX_QWORD_FIELD(*event, ESF_DZ_RX_ECRC_ERR)))
2144                 flags |= EFX_RX_PKT_DISCARD;
2145
2146         if (unlikely(EFX_QWORD_FIELD(*event, ESF_DZ_RX_IPCKSUM_ERR))) {
2147                 channel->n_rx_ip_hdr_chksum_err += n_packets;
2148         } else if (unlikely(EFX_QWORD_FIELD(*event,
2149                                             ESF_DZ_RX_TCPUDP_CKSUM_ERR))) {
2150                 channel->n_rx_tcp_udp_chksum_err += n_packets;
2151         } else if (rx_l4_class == ESE_DZ_L4_CLASS_TCP ||
2152                    rx_l4_class == ESE_DZ_L4_CLASS_UDP) {
2153                 flags |= EFX_RX_PKT_CSUMMED;
2154         }
2155
2156         if (rx_l4_class == ESE_DZ_L4_CLASS_TCP)
2157                 flags |= EFX_RX_PKT_TCP;
2158
2159         channel->irq_mod_score += 2 * n_packets;
2160
2161         /* Handle received packet(s) */
2162         for (i = 0; i < n_packets; i++) {
2163                 efx_rx_packet(rx_queue,
2164                               rx_queue->removed_count & rx_queue->ptr_mask,
2165                               rx_queue->scatter_n, rx_queue->scatter_len,
2166                               flags);
2167                 rx_queue->removed_count += rx_queue->scatter_n;
2168         }
2169
2170         rx_queue->scatter_n = 0;
2171         rx_queue->scatter_len = 0;
2172
2173         return n_packets;
2174 }
2175
2176 static int
2177 efx_ef10_handle_tx_event(struct efx_channel *channel, efx_qword_t *event)
2178 {
2179         struct efx_nic *efx = channel->efx;
2180         struct efx_tx_queue *tx_queue;
2181         unsigned int tx_ev_desc_ptr;
2182         unsigned int tx_ev_q_label;
2183         int tx_descs = 0;
2184
2185         if (unlikely(ACCESS_ONCE(efx->reset_pending)))
2186                 return 0;
2187
2188         if (unlikely(EFX_QWORD_FIELD(*event, ESF_DZ_TX_DROP_EVENT)))
2189                 return 0;
2190
2191         /* Transmit completion */
2192         tx_ev_desc_ptr = EFX_QWORD_FIELD(*event, ESF_DZ_TX_DESCR_INDX);
2193         tx_ev_q_label = EFX_QWORD_FIELD(*event, ESF_DZ_TX_QLABEL);
2194         tx_queue = efx_channel_get_tx_queue(channel,
2195                                             tx_ev_q_label % EFX_TXQ_TYPES);
2196         tx_descs = ((tx_ev_desc_ptr + 1 - tx_queue->read_count) &
2197                     tx_queue->ptr_mask);
2198         efx_xmit_done(tx_queue, tx_ev_desc_ptr & tx_queue->ptr_mask);
2199
2200         return tx_descs;
2201 }
2202
2203 static void
2204 efx_ef10_handle_driver_event(struct efx_channel *channel, efx_qword_t *event)
2205 {
2206         struct efx_nic *efx = channel->efx;
2207         int subcode;
2208
2209         subcode = EFX_QWORD_FIELD(*event, ESF_DZ_DRV_SUB_CODE);
2210
2211         switch (subcode) {
2212         case ESE_DZ_DRV_TIMER_EV:
2213         case ESE_DZ_DRV_WAKE_UP_EV:
2214                 break;
2215         case ESE_DZ_DRV_START_UP_EV:
2216                 /* event queue init complete. ok. */
2217                 break;
2218         default:
2219                 netif_err(efx, hw, efx->net_dev,
2220                           "channel %d unknown driver event type %d"
2221                           " (data " EFX_QWORD_FMT ")\n",
2222                           channel->channel, subcode,
2223                           EFX_QWORD_VAL(*event));
2224
2225         }
2226 }
2227
2228 static void efx_ef10_handle_driver_generated_event(struct efx_channel *channel,
2229                                                    efx_qword_t *event)
2230 {
2231         struct efx_nic *efx = channel->efx;
2232         u32 subcode;
2233
2234         subcode = EFX_QWORD_FIELD(*event, EFX_DWORD_0);
2235
2236         switch (subcode) {
2237         case EFX_EF10_TEST:
2238                 channel->event_test_cpu = raw_smp_processor_id();
2239                 break;
2240         case EFX_EF10_REFILL:
2241                 /* The queue must be empty, so we won't receive any rx
2242                  * events, so efx_process_channel() won't refill the
2243                  * queue. Refill it here
2244                  */
2245                 efx_fast_push_rx_descriptors(&channel->rx_queue, true);
2246                 break;
2247         default:
2248                 netif_err(efx, hw, efx->net_dev,
2249                           "channel %d unknown driver event type %u"
2250                           " (data " EFX_QWORD_FMT ")\n",
2251                           channel->channel, (unsigned) subcode,
2252                           EFX_QWORD_VAL(*event));
2253         }
2254 }
2255
2256 static int efx_ef10_ev_process(struct efx_channel *channel, int quota)
2257 {
2258         struct efx_nic *efx = channel->efx;
2259         efx_qword_t event, *p_event;
2260         unsigned int read_ptr;
2261         int ev_code;
2262         int tx_descs = 0;
2263         int spent = 0;
2264
2265         if (quota <= 0)
2266                 return spent;
2267
2268         read_ptr = channel->eventq_read_ptr;
2269
2270         for (;;) {
2271                 p_event = efx_event(channel, read_ptr);
2272                 event = *p_event;
2273
2274                 if (!efx_event_present(&event))
2275                         break;
2276
2277                 EFX_SET_QWORD(*p_event);
2278
2279                 ++read_ptr;
2280
2281                 ev_code = EFX_QWORD_FIELD(event, ESF_DZ_EV_CODE);
2282
2283                 netif_vdbg(efx, drv, efx->net_dev,
2284                            "processing event on %d " EFX_QWORD_FMT "\n",
2285                            channel->channel, EFX_QWORD_VAL(event));
2286
2287                 switch (ev_code) {
2288                 case ESE_DZ_EV_CODE_MCDI_EV:
2289                         efx_mcdi_process_event(channel, &event);
2290                         break;
2291                 case ESE_DZ_EV_CODE_RX_EV:
2292                         spent += efx_ef10_handle_rx_event(channel, &event);
2293                         if (spent >= quota) {
2294                                 /* XXX can we split a merged event to
2295                                  * avoid going over-quota?
2296                                  */
2297                                 spent = quota;
2298                                 goto out;
2299                         }
2300                         break;
2301                 case ESE_DZ_EV_CODE_TX_EV:
2302                         tx_descs += efx_ef10_handle_tx_event(channel, &event);
2303                         if (tx_descs > efx->txq_entries) {
2304                                 spent = quota;
2305                                 goto out;
2306                         } else if (++spent == quota) {
2307                                 goto out;
2308                         }
2309                         break;
2310                 case ESE_DZ_EV_CODE_DRIVER_EV:
2311                         efx_ef10_handle_driver_event(channel, &event);
2312                         if (++spent == quota)
2313                                 goto out;
2314                         break;
2315                 case EFX_EF10_DRVGEN_EV:
2316                         efx_ef10_handle_driver_generated_event(channel, &event);
2317                         break;
2318                 default:
2319                         netif_err(efx, hw, efx->net_dev,
2320                                   "channel %d unknown event type %d"
2321                                   " (data " EFX_QWORD_FMT ")\n",
2322                                   channel->channel, ev_code,
2323                                   EFX_QWORD_VAL(event));
2324                 }
2325         }
2326
2327 out:
2328         channel->eventq_read_ptr = read_ptr;
2329         return spent;
2330 }
2331
2332 static void efx_ef10_ev_read_ack(struct efx_channel *channel)
2333 {
2334         struct efx_nic *efx = channel->efx;
2335         efx_dword_t rptr;
2336
2337         if (EFX_EF10_WORKAROUND_35388(efx)) {
2338                 BUILD_BUG_ON(EFX_MIN_EVQ_SIZE <
2339                              (1 << ERF_DD_EVQ_IND_RPTR_WIDTH));
2340                 BUILD_BUG_ON(EFX_MAX_EVQ_SIZE >
2341                              (1 << 2 * ERF_DD_EVQ_IND_RPTR_WIDTH));
2342
2343                 EFX_POPULATE_DWORD_2(rptr, ERF_DD_EVQ_IND_RPTR_FLAGS,
2344                                      EFE_DD_EVQ_IND_RPTR_FLAGS_HIGH,
2345                                      ERF_DD_EVQ_IND_RPTR,
2346                                      (channel->eventq_read_ptr &
2347                                       channel->eventq_mask) >>
2348                                      ERF_DD_EVQ_IND_RPTR_WIDTH);
2349                 efx_writed_page(efx, &rptr, ER_DD_EVQ_INDIRECT,
2350                                 channel->channel);
2351                 EFX_POPULATE_DWORD_2(rptr, ERF_DD_EVQ_IND_RPTR_FLAGS,
2352                                      EFE_DD_EVQ_IND_RPTR_FLAGS_LOW,
2353                                      ERF_DD_EVQ_IND_RPTR,
2354                                      channel->eventq_read_ptr &
2355                                      ((1 << ERF_DD_EVQ_IND_RPTR_WIDTH) - 1));
2356                 efx_writed_page(efx, &rptr, ER_DD_EVQ_INDIRECT,
2357                                 channel->channel);
2358         } else {
2359                 EFX_POPULATE_DWORD_1(rptr, ERF_DZ_EVQ_RPTR,
2360                                      channel->eventq_read_ptr &
2361                                      channel->eventq_mask);
2362                 efx_writed_page(efx, &rptr, ER_DZ_EVQ_RPTR, channel->channel);
2363         }
2364 }
2365
2366 static void efx_ef10_ev_test_generate(struct efx_channel *channel)
2367 {
2368         MCDI_DECLARE_BUF(inbuf, MC_CMD_DRIVER_EVENT_IN_LEN);
2369         struct efx_nic *efx = channel->efx;
2370         efx_qword_t event;
2371         int rc;
2372
2373         EFX_POPULATE_QWORD_2(event,
2374                              ESF_DZ_EV_CODE, EFX_EF10_DRVGEN_EV,
2375                              ESF_DZ_EV_DATA, EFX_EF10_TEST);
2376
2377         MCDI_SET_DWORD(inbuf, DRIVER_EVENT_IN_EVQ, channel->channel);
2378
2379         /* MCDI_SET_QWORD is not appropriate here since EFX_POPULATE_* has
2380          * already swapped the data to little-endian order.
2381          */
2382         memcpy(MCDI_PTR(inbuf, DRIVER_EVENT_IN_DATA), &event.u64[0],
2383                sizeof(efx_qword_t));
2384
2385         rc = efx_mcdi_rpc(efx, MC_CMD_DRIVER_EVENT, inbuf, sizeof(inbuf),
2386                           NULL, 0, NULL);
2387         if (rc != 0)
2388                 goto fail;
2389
2390         return;
2391
2392 fail:
2393         WARN_ON(true);
2394         netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
2395 }
2396
2397 void efx_ef10_handle_drain_event(struct efx_nic *efx)
2398 {
2399         if (atomic_dec_and_test(&efx->active_queues))
2400                 wake_up(&efx->flush_wq);
2401
2402         WARN_ON(atomic_read(&efx->active_queues) < 0);
2403 }
2404
2405 static int efx_ef10_fini_dmaq(struct efx_nic *efx)
2406 {
2407         struct efx_ef10_nic_data *nic_data = efx->nic_data;
2408         struct efx_channel *channel;
2409         struct efx_tx_queue *tx_queue;
2410         struct efx_rx_queue *rx_queue;
2411         int pending;
2412
2413         /* If the MC has just rebooted, the TX/RX queues will have already been
2414          * torn down, but efx->active_queues needs to be set to zero.
2415          */
2416         if (nic_data->must_realloc_vis) {
2417                 atomic_set(&efx->active_queues, 0);
2418                 return 0;
2419         }
2420
2421         /* Do not attempt to write to the NIC during EEH recovery */
2422         if (efx->state != STATE_RECOVERY) {
2423                 efx_for_each_channel(channel, efx) {
2424                         efx_for_each_channel_rx_queue(rx_queue, channel)
2425                                 efx_ef10_rx_fini(rx_queue);
2426                         efx_for_each_channel_tx_queue(tx_queue, channel)
2427                                 efx_ef10_tx_fini(tx_queue);
2428                 }
2429
2430                 wait_event_timeout(efx->flush_wq,
2431                                    atomic_read(&efx->active_queues) == 0,
2432                                    msecs_to_jiffies(EFX_MAX_FLUSH_TIME));
2433                 pending = atomic_read(&efx->active_queues);
2434                 if (pending) {
2435                         netif_err(efx, hw, efx->net_dev, "failed to flush %d queues\n",
2436                                   pending);
2437                         return -ETIMEDOUT;
2438                 }
2439         }
2440
2441         return 0;
2442 }
2443
2444 static void efx_ef10_prepare_flr(struct efx_nic *efx)
2445 {
2446         atomic_set(&efx->active_queues, 0);
2447 }
2448
2449 static bool efx_ef10_filter_equal(const struct efx_filter_spec *left,
2450                                   const struct efx_filter_spec *right)
2451 {
2452         if ((left->match_flags ^ right->match_flags) |
2453             ((left->flags ^ right->flags) &
2454              (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_TX)))
2455                 return false;
2456
2457         return memcmp(&left->outer_vid, &right->outer_vid,
2458                       sizeof(struct efx_filter_spec) -
2459                       offsetof(struct efx_filter_spec, outer_vid)) == 0;
2460 }
2461
2462 static unsigned int efx_ef10_filter_hash(const struct efx_filter_spec *spec)
2463 {
2464         BUILD_BUG_ON(offsetof(struct efx_filter_spec, outer_vid) & 3);
2465         return jhash2((const u32 *)&spec->outer_vid,
2466                       (sizeof(struct efx_filter_spec) -
2467                        offsetof(struct efx_filter_spec, outer_vid)) / 4,
2468                       0);
2469         /* XXX should we randomise the initval? */
2470 }
2471
2472 /* Decide whether a filter should be exclusive or else should allow
2473  * delivery to additional recipients.  Currently we decide that
2474  * filters for specific local unicast MAC and IP addresses are
2475  * exclusive.
2476  */
2477 static bool efx_ef10_filter_is_exclusive(const struct efx_filter_spec *spec)
2478 {
2479         if (spec->match_flags & EFX_FILTER_MATCH_LOC_MAC &&
2480             !is_multicast_ether_addr(spec->loc_mac))
2481                 return true;
2482
2483         if ((spec->match_flags &
2484              (EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_LOC_HOST)) ==
2485             (EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_LOC_HOST)) {
2486                 if (spec->ether_type == htons(ETH_P_IP) &&
2487                     !ipv4_is_multicast(spec->loc_host[0]))
2488                         return true;
2489                 if (spec->ether_type == htons(ETH_P_IPV6) &&
2490                     ((const u8 *)spec->loc_host)[0] != 0xff)
2491                         return true;
2492         }
2493
2494         return false;
2495 }
2496
2497 static struct efx_filter_spec *
2498 efx_ef10_filter_entry_spec(const struct efx_ef10_filter_table *table,
2499                            unsigned int filter_idx)
2500 {
2501         return (struct efx_filter_spec *)(table->entry[filter_idx].spec &
2502                                           ~EFX_EF10_FILTER_FLAGS);
2503 }
2504
2505 static unsigned int
2506 efx_ef10_filter_entry_flags(const struct efx_ef10_filter_table *table,
2507                            unsigned int filter_idx)
2508 {
2509         return table->entry[filter_idx].spec & EFX_EF10_FILTER_FLAGS;
2510 }
2511
2512 static void
2513 efx_ef10_filter_set_entry(struct efx_ef10_filter_table *table,
2514                           unsigned int filter_idx,
2515                           const struct efx_filter_spec *spec,
2516                           unsigned int flags)
2517 {
2518         table->entry[filter_idx].spec = (unsigned long)spec | flags;
2519 }
2520
2521 static void efx_ef10_filter_push_prep(struct efx_nic *efx,
2522                                       const struct efx_filter_spec *spec,
2523                                       efx_dword_t *inbuf, u64 handle,
2524                                       bool replacing)
2525 {
2526         struct efx_ef10_nic_data *nic_data = efx->nic_data;
2527
2528         memset(inbuf, 0, MC_CMD_FILTER_OP_IN_LEN);
2529
2530         if (replacing) {
2531                 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
2532                                MC_CMD_FILTER_OP_IN_OP_REPLACE);
2533                 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE, handle);
2534         } else {
2535                 u32 match_fields = 0;
2536
2537                 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
2538                                efx_ef10_filter_is_exclusive(spec) ?
2539                                MC_CMD_FILTER_OP_IN_OP_INSERT :
2540                                MC_CMD_FILTER_OP_IN_OP_SUBSCRIBE);
2541
2542                 /* Convert match flags and values.  Unlike almost
2543                  * everything else in MCDI, these fields are in
2544                  * network byte order.
2545                  */
2546                 if (spec->match_flags & EFX_FILTER_MATCH_LOC_MAC_IG)
2547                         match_fields |=
2548                                 is_multicast_ether_addr(spec->loc_mac) ?
2549                                 1 << MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_MCAST_DST_LBN :
2550                                 1 << MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_UCAST_DST_LBN;
2551 #define COPY_FIELD(gen_flag, gen_field, mcdi_field)                          \
2552                 if (spec->match_flags & EFX_FILTER_MATCH_ ## gen_flag) {     \
2553                         match_fields |=                                      \
2554                                 1 << MC_CMD_FILTER_OP_IN_MATCH_ ##           \
2555                                 mcdi_field ## _LBN;                          \
2556                         BUILD_BUG_ON(                                        \
2557                                 MC_CMD_FILTER_OP_IN_ ## mcdi_field ## _LEN < \
2558                                 sizeof(spec->gen_field));                    \
2559                         memcpy(MCDI_PTR(inbuf, FILTER_OP_IN_ ## mcdi_field), \
2560                                &spec->gen_field, sizeof(spec->gen_field));   \
2561                 }
2562                 COPY_FIELD(REM_HOST, rem_host, SRC_IP);
2563                 COPY_FIELD(LOC_HOST, loc_host, DST_IP);
2564                 COPY_FIELD(REM_MAC, rem_mac, SRC_MAC);
2565                 COPY_FIELD(REM_PORT, rem_port, SRC_PORT);
2566                 COPY_FIELD(LOC_MAC, loc_mac, DST_MAC);
2567                 COPY_FIELD(LOC_PORT, loc_port, DST_PORT);
2568                 COPY_FIELD(ETHER_TYPE, ether_type, ETHER_TYPE);
2569                 COPY_FIELD(INNER_VID, inner_vid, INNER_VLAN);
2570                 COPY_FIELD(OUTER_VID, outer_vid, OUTER_VLAN);
2571                 COPY_FIELD(IP_PROTO, ip_proto, IP_PROTO);
2572 #undef COPY_FIELD
2573                 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_MATCH_FIELDS,
2574                                match_fields);
2575         }
2576
2577         MCDI_SET_DWORD(inbuf, FILTER_OP_IN_PORT_ID, nic_data->vport_id);
2578         MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_DEST,
2579                        spec->dmaq_id == EFX_FILTER_RX_DMAQ_ID_DROP ?
2580                        MC_CMD_FILTER_OP_IN_RX_DEST_DROP :
2581                        MC_CMD_FILTER_OP_IN_RX_DEST_HOST);
2582         MCDI_SET_DWORD(inbuf, FILTER_OP_IN_TX_DOMAIN, 0);
2583         MCDI_SET_DWORD(inbuf, FILTER_OP_IN_TX_DEST,
2584                        MC_CMD_FILTER_OP_IN_TX_DEST_DEFAULT);
2585         MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_QUEUE,
2586                        spec->dmaq_id == EFX_FILTER_RX_DMAQ_ID_DROP ?
2587                        0 : spec->dmaq_id);
2588         MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_MODE,
2589                        (spec->flags & EFX_FILTER_FLAG_RX_RSS) ?
2590                        MC_CMD_FILTER_OP_IN_RX_MODE_RSS :
2591                        MC_CMD_FILTER_OP_IN_RX_MODE_SIMPLE);
2592         if (spec->flags & EFX_FILTER_FLAG_RX_RSS)
2593                 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_CONTEXT,
2594                                spec->rss_context !=
2595                                EFX_FILTER_RSS_CONTEXT_DEFAULT ?
2596                                spec->rss_context : nic_data->rx_rss_context);
2597 }
2598
2599 static int efx_ef10_filter_push(struct efx_nic *efx,
2600                                 const struct efx_filter_spec *spec,
2601                                 u64 *handle, bool replacing)
2602 {
2603         MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN);
2604         MCDI_DECLARE_BUF(outbuf, MC_CMD_FILTER_OP_OUT_LEN);
2605         int rc;
2606
2607         efx_ef10_filter_push_prep(efx, spec, inbuf, *handle, replacing);
2608         rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf),
2609                           outbuf, sizeof(outbuf), NULL);
2610         if (rc == 0)
2611                 *handle = MCDI_QWORD(outbuf, FILTER_OP_OUT_HANDLE);
2612         if (rc == -ENOSPC)
2613                 rc = -EBUSY; /* to match efx_farch_filter_insert() */
2614         return rc;
2615 }
2616
2617 static int efx_ef10_filter_rx_match_pri(struct efx_ef10_filter_table *table,
2618                                         enum efx_filter_match_flags match_flags)
2619 {
2620         unsigned int match_pri;
2621
2622         for (match_pri = 0;
2623              match_pri < table->rx_match_count;
2624              match_pri++)
2625                 if (table->rx_match_flags[match_pri] == match_flags)
2626                         return match_pri;
2627
2628         return -EPROTONOSUPPORT;
2629 }
2630
2631 static s32 efx_ef10_filter_insert(struct efx_nic *efx,
2632                                   struct efx_filter_spec *spec,
2633                                   bool replace_equal)
2634 {
2635         struct efx_ef10_filter_table *table = efx->filter_state;
2636         DECLARE_BITMAP(mc_rem_map, EFX_EF10_FILTER_SEARCH_LIMIT);
2637         struct efx_filter_spec *saved_spec;
2638         unsigned int match_pri, hash;
2639         unsigned int priv_flags;
2640         bool replacing = false;
2641         int ins_index = -1;
2642         DEFINE_WAIT(wait);
2643         bool is_mc_recip;
2644         s32 rc;
2645
2646         /* For now, only support RX filters */
2647         if ((spec->flags & (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_TX)) !=
2648             EFX_FILTER_FLAG_RX)
2649                 return -EINVAL;
2650
2651         rc = efx_ef10_filter_rx_match_pri(table, spec->match_flags);
2652         if (rc < 0)
2653                 return rc;
2654         match_pri = rc;
2655
2656         hash = efx_ef10_filter_hash(spec);
2657         is_mc_recip = efx_filter_is_mc_recipient(spec);
2658         if (is_mc_recip)
2659                 bitmap_zero(mc_rem_map, EFX_EF10_FILTER_SEARCH_LIMIT);
2660
2661         /* Find any existing filters with the same match tuple or
2662          * else a free slot to insert at.  If any of them are busy,
2663          * we have to wait and retry.
2664          */
2665         for (;;) {
2666                 unsigned int depth = 1;
2667                 unsigned int i;
2668
2669                 spin_lock_bh(&efx->filter_lock);
2670
2671                 for (;;) {
2672                         i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
2673                         saved_spec = efx_ef10_filter_entry_spec(table, i);
2674
2675                         if (!saved_spec) {
2676                                 if (ins_index < 0)
2677                                         ins_index = i;
2678                         } else if (efx_ef10_filter_equal(spec, saved_spec)) {
2679                                 if (table->entry[i].spec &
2680                                     EFX_EF10_FILTER_FLAG_BUSY)
2681                                         break;
2682                                 if (spec->priority < saved_spec->priority &&
2683                                     spec->priority != EFX_FILTER_PRI_AUTO) {
2684                                         rc = -EPERM;
2685                                         goto out_unlock;
2686                                 }
2687                                 if (!is_mc_recip) {
2688                                         /* This is the only one */
2689                                         if (spec->priority ==
2690                                             saved_spec->priority &&
2691                                             !replace_equal) {
2692                                                 rc = -EEXIST;
2693                                                 goto out_unlock;
2694                                         }
2695                                         ins_index = i;
2696                                         goto found;
2697                                 } else if (spec->priority >
2698                                            saved_spec->priority ||
2699                                            (spec->priority ==
2700                                             saved_spec->priority &&
2701                                             replace_equal)) {
2702                                         if (ins_index < 0)
2703                                                 ins_index = i;
2704                                         else
2705                                                 __set_bit(depth, mc_rem_map);
2706                                 }
2707                         }
2708
2709                         /* Once we reach the maximum search depth, use
2710                          * the first suitable slot or return -EBUSY if
2711                          * there was none
2712                          */
2713                         if (depth == EFX_EF10_FILTER_SEARCH_LIMIT) {
2714                                 if (ins_index < 0) {
2715                                         rc = -EBUSY;
2716                                         goto out_unlock;
2717                                 }
2718                                 goto found;
2719                         }
2720
2721                         ++depth;
2722                 }
2723
2724                 prepare_to_wait(&table->waitq, &wait, TASK_UNINTERRUPTIBLE);
2725                 spin_unlock_bh(&efx->filter_lock);
2726                 schedule();
2727         }
2728
2729 found:
2730         /* Create a software table entry if necessary, and mark it
2731          * busy.  We might yet fail to insert, but any attempt to
2732          * insert a conflicting filter while we're waiting for the
2733          * firmware must find the busy entry.
2734          */
2735         saved_spec = efx_ef10_filter_entry_spec(table, ins_index);
2736         if (saved_spec) {
2737                 if (spec->priority == EFX_FILTER_PRI_AUTO &&
2738                     saved_spec->priority >= EFX_FILTER_PRI_AUTO) {
2739                         /* Just make sure it won't be removed */
2740                         if (saved_spec->priority > EFX_FILTER_PRI_AUTO)
2741                                 saved_spec->flags |= EFX_FILTER_FLAG_RX_OVER_AUTO;
2742                         table->entry[ins_index].spec &=
2743                                 ~EFX_EF10_FILTER_FLAG_AUTO_OLD;
2744                         rc = ins_index;
2745                         goto out_unlock;
2746                 }
2747                 replacing = true;
2748                 priv_flags = efx_ef10_filter_entry_flags(table, ins_index);
2749         } else {
2750                 saved_spec = kmalloc(sizeof(*spec), GFP_ATOMIC);
2751                 if (!saved_spec) {
2752                         rc = -ENOMEM;
2753                         goto out_unlock;
2754                 }
2755                 *saved_spec = *spec;
2756                 priv_flags = 0;
2757         }
2758         efx_ef10_filter_set_entry(table, ins_index, saved_spec,
2759                                   priv_flags | EFX_EF10_FILTER_FLAG_BUSY);
2760
2761         /* Mark lower-priority multicast recipients busy prior to removal */
2762         if (is_mc_recip) {
2763                 unsigned int depth, i;
2764
2765                 for (depth = 0; depth < EFX_EF10_FILTER_SEARCH_LIMIT; depth++) {
2766                         i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
2767                         if (test_bit(depth, mc_rem_map))
2768                                 table->entry[i].spec |=
2769                                         EFX_EF10_FILTER_FLAG_BUSY;
2770                 }
2771         }
2772
2773         spin_unlock_bh(&efx->filter_lock);
2774
2775         rc = efx_ef10_filter_push(efx, spec, &table->entry[ins_index].handle,
2776                                   replacing);
2777
2778         /* Finalise the software table entry */
2779         spin_lock_bh(&efx->filter_lock);
2780         if (rc == 0) {
2781                 if (replacing) {
2782                         /* Update the fields that may differ */
2783                         if (saved_spec->priority == EFX_FILTER_PRI_AUTO)
2784                                 saved_spec->flags |=
2785                                         EFX_FILTER_FLAG_RX_OVER_AUTO;
2786                         saved_spec->priority = spec->priority;
2787                         saved_spec->flags &= EFX_FILTER_FLAG_RX_OVER_AUTO;
2788                         saved_spec->flags |= spec->flags;
2789                         saved_spec->rss_context = spec->rss_context;
2790                         saved_spec->dmaq_id = spec->dmaq_id;
2791                 }
2792         } else if (!replacing) {
2793                 kfree(saved_spec);
2794                 saved_spec = NULL;
2795         }
2796         efx_ef10_filter_set_entry(table, ins_index, saved_spec, priv_flags);
2797
2798         /* Remove and finalise entries for lower-priority multicast
2799          * recipients
2800          */
2801         if (is_mc_recip) {
2802                 MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN);
2803                 unsigned int depth, i;
2804
2805                 memset(inbuf, 0, sizeof(inbuf));
2806
2807                 for (depth = 0; depth < EFX_EF10_FILTER_SEARCH_LIMIT; depth++) {
2808                         if (!test_bit(depth, mc_rem_map))
2809                                 continue;
2810
2811                         i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
2812                         saved_spec = efx_ef10_filter_entry_spec(table, i);
2813                         priv_flags = efx_ef10_filter_entry_flags(table, i);
2814
2815                         if (rc == 0) {
2816                                 spin_unlock_bh(&efx->filter_lock);
2817                                 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
2818                                                MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE);
2819                                 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
2820                                                table->entry[i].handle);
2821                                 rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP,
2822                                                   inbuf, sizeof(inbuf),
2823                                                   NULL, 0, NULL);
2824                                 spin_lock_bh(&efx->filter_lock);
2825                         }
2826
2827                         if (rc == 0) {
2828                                 kfree(saved_spec);
2829                                 saved_spec = NULL;
2830                                 priv_flags = 0;
2831                         } else {
2832                                 priv_flags &= ~EFX_EF10_FILTER_FLAG_BUSY;
2833                         }
2834                         efx_ef10_filter_set_entry(table, i, saved_spec,
2835                                                   priv_flags);
2836                 }
2837         }
2838
2839         /* If successful, return the inserted filter ID */
2840         if (rc == 0)
2841                 rc = match_pri * HUNT_FILTER_TBL_ROWS + ins_index;
2842
2843         wake_up_all(&table->waitq);
2844 out_unlock:
2845         spin_unlock_bh(&efx->filter_lock);
2846         finish_wait(&table->waitq, &wait);
2847         return rc;
2848 }
2849
2850 static void efx_ef10_filter_update_rx_scatter(struct efx_nic *efx)
2851 {
2852         /* no need to do anything here on EF10 */
2853 }
2854
2855 /* Remove a filter.
2856  * If !by_index, remove by ID
2857  * If by_index, remove by index
2858  * Filter ID may come from userland and must be range-checked.
2859  */
2860 static int efx_ef10_filter_remove_internal(struct efx_nic *efx,
2861                                            unsigned int priority_mask,
2862                                            u32 filter_id, bool by_index)
2863 {
2864         unsigned int filter_idx = filter_id % HUNT_FILTER_TBL_ROWS;
2865         struct efx_ef10_filter_table *table = efx->filter_state;
2866         MCDI_DECLARE_BUF(inbuf,
2867                          MC_CMD_FILTER_OP_IN_HANDLE_OFST +
2868                          MC_CMD_FILTER_OP_IN_HANDLE_LEN);
2869         struct efx_filter_spec *spec;
2870         DEFINE_WAIT(wait);
2871         int rc;
2872
2873         /* Find the software table entry and mark it busy.  Don't
2874          * remove it yet; any attempt to update while we're waiting
2875          * for the firmware must find the busy entry.
2876          */
2877         for (;;) {
2878                 spin_lock_bh(&efx->filter_lock);
2879                 if (!(table->entry[filter_idx].spec &
2880                       EFX_EF10_FILTER_FLAG_BUSY))
2881                         break;
2882                 prepare_to_wait(&table->waitq, &wait, TASK_UNINTERRUPTIBLE);
2883                 spin_unlock_bh(&efx->filter_lock);
2884                 schedule();
2885         }
2886
2887         spec = efx_ef10_filter_entry_spec(table, filter_idx);
2888         if (!spec ||
2889             (!by_index &&
2890              efx_ef10_filter_rx_match_pri(table, spec->match_flags) !=
2891              filter_id / HUNT_FILTER_TBL_ROWS)) {
2892                 rc = -ENOENT;
2893                 goto out_unlock;
2894         }
2895
2896         if (spec->flags & EFX_FILTER_FLAG_RX_OVER_AUTO &&
2897             priority_mask == (1U << EFX_FILTER_PRI_AUTO)) {
2898                 /* Just remove flags */
2899                 spec->flags &= ~EFX_FILTER_FLAG_RX_OVER_AUTO;
2900                 table->entry[filter_idx].spec &= ~EFX_EF10_FILTER_FLAG_AUTO_OLD;
2901                 rc = 0;
2902                 goto out_unlock;
2903         }
2904
2905         if (!(priority_mask & (1U << spec->priority))) {
2906                 rc = -ENOENT;
2907                 goto out_unlock;
2908         }
2909
2910         table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_BUSY;
2911         spin_unlock_bh(&efx->filter_lock);
2912
2913         if (spec->flags & EFX_FILTER_FLAG_RX_OVER_AUTO) {
2914                 /* Reset to an automatic filter */
2915
2916                 struct efx_filter_spec new_spec = *spec;
2917
2918                 new_spec.priority = EFX_FILTER_PRI_AUTO;
2919                 new_spec.flags = (EFX_FILTER_FLAG_RX |
2920                                   EFX_FILTER_FLAG_RX_RSS);
2921                 new_spec.dmaq_id = 0;
2922                 new_spec.rss_context = EFX_FILTER_RSS_CONTEXT_DEFAULT;
2923                 rc = efx_ef10_filter_push(efx, &new_spec,
2924                                           &table->entry[filter_idx].handle,
2925                                           true);
2926
2927                 spin_lock_bh(&efx->filter_lock);
2928                 if (rc == 0)
2929                         *spec = new_spec;
2930         } else {
2931                 /* Really remove the filter */
2932
2933                 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
2934                                efx_ef10_filter_is_exclusive(spec) ?
2935                                MC_CMD_FILTER_OP_IN_OP_REMOVE :
2936                                MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE);
2937                 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
2938                                table->entry[filter_idx].handle);
2939                 rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP,
2940                                   inbuf, sizeof(inbuf), NULL, 0, NULL);
2941
2942                 spin_lock_bh(&efx->filter_lock);
2943                 if (rc == 0) {
2944                         kfree(spec);
2945                         efx_ef10_filter_set_entry(table, filter_idx, NULL, 0);
2946                 }
2947         }
2948
2949         table->entry[filter_idx].spec &= ~EFX_EF10_FILTER_FLAG_BUSY;
2950         wake_up_all(&table->waitq);
2951 out_unlock:
2952         spin_unlock_bh(&efx->filter_lock);
2953         finish_wait(&table->waitq, &wait);
2954         return rc;
2955 }
2956
2957 static int efx_ef10_filter_remove_safe(struct efx_nic *efx,
2958                                        enum efx_filter_priority priority,
2959                                        u32 filter_id)
2960 {
2961         return efx_ef10_filter_remove_internal(efx, 1U << priority,
2962                                                filter_id, false);
2963 }
2964
2965 static int efx_ef10_filter_get_safe(struct efx_nic *efx,
2966                                     enum efx_filter_priority priority,
2967                                     u32 filter_id, struct efx_filter_spec *spec)
2968 {
2969         unsigned int filter_idx = filter_id % HUNT_FILTER_TBL_ROWS;
2970         struct efx_ef10_filter_table *table = efx->filter_state;
2971         const struct efx_filter_spec *saved_spec;
2972         int rc;
2973
2974         spin_lock_bh(&efx->filter_lock);
2975         saved_spec = efx_ef10_filter_entry_spec(table, filter_idx);
2976         if (saved_spec && saved_spec->priority == priority &&
2977             efx_ef10_filter_rx_match_pri(table, saved_spec->match_flags) ==
2978             filter_id / HUNT_FILTER_TBL_ROWS) {
2979                 *spec = *saved_spec;
2980                 rc = 0;
2981         } else {
2982                 rc = -ENOENT;
2983         }
2984         spin_unlock_bh(&efx->filter_lock);
2985         return rc;
2986 }
2987
2988 static int efx_ef10_filter_clear_rx(struct efx_nic *efx,
2989                                      enum efx_filter_priority priority)
2990 {
2991         unsigned int priority_mask;
2992         unsigned int i;
2993         int rc;
2994
2995         priority_mask = (((1U << (priority + 1)) - 1) &
2996                          ~(1U << EFX_FILTER_PRI_AUTO));
2997
2998         for (i = 0; i < HUNT_FILTER_TBL_ROWS; i++) {
2999                 rc = efx_ef10_filter_remove_internal(efx, priority_mask,
3000                                                      i, true);
3001                 if (rc && rc != -ENOENT)
3002                         return rc;
3003         }
3004
3005         return 0;
3006 }
3007
3008 static u32 efx_ef10_filter_count_rx_used(struct efx_nic *efx,
3009                                          enum efx_filter_priority priority)
3010 {
3011         struct efx_ef10_filter_table *table = efx->filter_state;
3012         unsigned int filter_idx;
3013         s32 count = 0;
3014
3015         spin_lock_bh(&efx->filter_lock);
3016         for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
3017                 if (table->entry[filter_idx].spec &&
3018                     efx_ef10_filter_entry_spec(table, filter_idx)->priority ==
3019                     priority)
3020                         ++count;
3021         }
3022         spin_unlock_bh(&efx->filter_lock);
3023         return count;
3024 }
3025
3026 static u32 efx_ef10_filter_get_rx_id_limit(struct efx_nic *efx)
3027 {
3028         struct efx_ef10_filter_table *table = efx->filter_state;
3029
3030         return table->rx_match_count * HUNT_FILTER_TBL_ROWS;
3031 }
3032
3033 static s32 efx_ef10_filter_get_rx_ids(struct efx_nic *efx,
3034                                       enum efx_filter_priority priority,
3035                                       u32 *buf, u32 size)
3036 {
3037         struct efx_ef10_filter_table *table = efx->filter_state;
3038         struct efx_filter_spec *spec;
3039         unsigned int filter_idx;
3040         s32 count = 0;
3041
3042         spin_lock_bh(&efx->filter_lock);
3043         for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
3044                 spec = efx_ef10_filter_entry_spec(table, filter_idx);
3045                 if (spec && spec->priority == priority) {
3046                         if (count == size) {
3047                                 count = -EMSGSIZE;
3048                                 break;
3049                         }
3050                         buf[count++] = (efx_ef10_filter_rx_match_pri(
3051                                                 table, spec->match_flags) *
3052                                         HUNT_FILTER_TBL_ROWS +
3053                                         filter_idx);
3054                 }
3055         }
3056         spin_unlock_bh(&efx->filter_lock);
3057         return count;
3058 }
3059
3060 #ifdef CONFIG_RFS_ACCEL
3061
3062 static efx_mcdi_async_completer efx_ef10_filter_rfs_insert_complete;
3063
3064 static s32 efx_ef10_filter_rfs_insert(struct efx_nic *efx,
3065                                       struct efx_filter_spec *spec)
3066 {
3067         struct efx_ef10_filter_table *table = efx->filter_state;
3068         MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN);
3069         struct efx_filter_spec *saved_spec;
3070         unsigned int hash, i, depth = 1;
3071         bool replacing = false;
3072         int ins_index = -1;
3073         u64 cookie;
3074         s32 rc;
3075
3076         /* Must be an RX filter without RSS and not for a multicast
3077          * destination address (RFS only works for connected sockets).
3078          * These restrictions allow us to pass only a tiny amount of
3079          * data through to the completion function.
3080          */
3081         EFX_WARN_ON_PARANOID(spec->flags !=
3082                              (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_RX_SCATTER));
3083         EFX_WARN_ON_PARANOID(spec->priority != EFX_FILTER_PRI_HINT);
3084         EFX_WARN_ON_PARANOID(efx_filter_is_mc_recipient(spec));
3085
3086         hash = efx_ef10_filter_hash(spec);
3087
3088         spin_lock_bh(&efx->filter_lock);
3089
3090         /* Find any existing filter with the same match tuple or else
3091          * a free slot to insert at.  If an existing filter is busy,
3092          * we have to give up.
3093          */
3094         for (;;) {
3095                 i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
3096                 saved_spec = efx_ef10_filter_entry_spec(table, i);
3097
3098                 if (!saved_spec) {
3099                         if (ins_index < 0)
3100                                 ins_index = i;
3101                 } else if (efx_ef10_filter_equal(spec, saved_spec)) {
3102                         if (table->entry[i].spec & EFX_EF10_FILTER_FLAG_BUSY) {
3103                                 rc = -EBUSY;
3104                                 goto fail_unlock;
3105                         }
3106                         if (spec->priority < saved_spec->priority) {
3107                                 rc = -EPERM;
3108                                 goto fail_unlock;
3109                         }
3110                         ins_index = i;
3111                         break;
3112                 }
3113
3114                 /* Once we reach the maximum search depth, use the
3115                  * first suitable slot or return -EBUSY if there was
3116                  * none
3117                  */
3118                 if (depth == EFX_EF10_FILTER_SEARCH_LIMIT) {
3119                         if (ins_index < 0) {
3120                                 rc = -EBUSY;
3121                                 goto fail_unlock;
3122                         }
3123                         break;
3124                 }
3125
3126                 ++depth;
3127         }
3128
3129         /* Create a software table entry if necessary, and mark it
3130          * busy.  We might yet fail to insert, but any attempt to
3131          * insert a conflicting filter while we're waiting for the
3132          * firmware must find the busy entry.
3133          */
3134         saved_spec = efx_ef10_filter_entry_spec(table, ins_index);
3135         if (saved_spec) {
3136                 replacing = true;
3137         } else {
3138                 saved_spec = kmalloc(sizeof(*spec), GFP_ATOMIC);
3139                 if (!saved_spec) {
3140                         rc = -ENOMEM;
3141                         goto fail_unlock;
3142                 }
3143                 *saved_spec = *spec;
3144         }
3145         efx_ef10_filter_set_entry(table, ins_index, saved_spec,
3146                                   EFX_EF10_FILTER_FLAG_BUSY);
3147
3148         spin_unlock_bh(&efx->filter_lock);
3149
3150         /* Pack up the variables needed on completion */
3151         cookie = replacing << 31 | ins_index << 16 | spec->dmaq_id;
3152
3153         efx_ef10_filter_push_prep(efx, spec, inbuf,
3154                                   table->entry[ins_index].handle, replacing);
3155         efx_mcdi_rpc_async(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf),
3156                            MC_CMD_FILTER_OP_OUT_LEN,
3157                            efx_ef10_filter_rfs_insert_complete, cookie);
3158
3159         return ins_index;
3160
3161 fail_unlock:
3162         spin_unlock_bh(&efx->filter_lock);
3163         return rc;
3164 }
3165
3166 static void
3167 efx_ef10_filter_rfs_insert_complete(struct efx_nic *efx, unsigned long cookie,
3168                                     int rc, efx_dword_t *outbuf,
3169                                     size_t outlen_actual)
3170 {
3171         struct efx_ef10_filter_table *table = efx->filter_state;
3172         unsigned int ins_index, dmaq_id;
3173         struct efx_filter_spec *spec;
3174         bool replacing;
3175
3176         /* Unpack the cookie */
3177         replacing = cookie >> 31;
3178         ins_index = (cookie >> 16) & (HUNT_FILTER_TBL_ROWS - 1);
3179         dmaq_id = cookie & 0xffff;
3180
3181         spin_lock_bh(&efx->filter_lock);
3182         spec = efx_ef10_filter_entry_spec(table, ins_index);
3183         if (rc == 0) {
3184                 table->entry[ins_index].handle =
3185                         MCDI_QWORD(outbuf, FILTER_OP_OUT_HANDLE);
3186                 if (replacing)
3187                         spec->dmaq_id = dmaq_id;
3188         } else if (!replacing) {
3189                 kfree(spec);
3190                 spec = NULL;
3191         }
3192         efx_ef10_filter_set_entry(table, ins_index, spec, 0);
3193         spin_unlock_bh(&efx->filter_lock);
3194
3195         wake_up_all(&table->waitq);
3196 }
3197
3198 static void
3199 efx_ef10_filter_rfs_expire_complete(struct efx_nic *efx,
3200                                     unsigned long filter_idx,
3201                                     int rc, efx_dword_t *outbuf,
3202                                     size_t outlen_actual);
3203
3204 static bool efx_ef10_filter_rfs_expire_one(struct efx_nic *efx, u32 flow_id,
3205                                            unsigned int filter_idx)
3206 {
3207         struct efx_ef10_filter_table *table = efx->filter_state;
3208         struct efx_filter_spec *spec =
3209                 efx_ef10_filter_entry_spec(table, filter_idx);
3210         MCDI_DECLARE_BUF(inbuf,
3211                          MC_CMD_FILTER_OP_IN_HANDLE_OFST +
3212                          MC_CMD_FILTER_OP_IN_HANDLE_LEN);
3213
3214         if (!spec ||
3215             (table->entry[filter_idx].spec & EFX_EF10_FILTER_FLAG_BUSY) ||
3216             spec->priority != EFX_FILTER_PRI_HINT ||
3217             !rps_may_expire_flow(efx->net_dev, spec->dmaq_id,
3218                                  flow_id, filter_idx))
3219                 return false;
3220
3221         MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
3222                        MC_CMD_FILTER_OP_IN_OP_REMOVE);
3223         MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
3224                        table->entry[filter_idx].handle);
3225         if (efx_mcdi_rpc_async(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf), 0,
3226                                efx_ef10_filter_rfs_expire_complete, filter_idx))
3227                 return false;
3228
3229         table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_BUSY;
3230         return true;
3231 }
3232
3233 static void
3234 efx_ef10_filter_rfs_expire_complete(struct efx_nic *efx,
3235                                     unsigned long filter_idx,
3236                                     int rc, efx_dword_t *outbuf,
3237                                     size_t outlen_actual)
3238 {
3239         struct efx_ef10_filter_table *table = efx->filter_state;
3240         struct efx_filter_spec *spec =
3241                 efx_ef10_filter_entry_spec(table, filter_idx);
3242
3243         spin_lock_bh(&efx->filter_lock);
3244         if (rc == 0) {
3245                 kfree(spec);
3246                 efx_ef10_filter_set_entry(table, filter_idx, NULL, 0);
3247         }
3248         table->entry[filter_idx].spec &= ~EFX_EF10_FILTER_FLAG_BUSY;
3249         wake_up_all(&table->waitq);
3250         spin_unlock_bh(&efx->filter_lock);
3251 }
3252
3253 #endif /* CONFIG_RFS_ACCEL */
3254
3255 static int efx_ef10_filter_match_flags_from_mcdi(u32 mcdi_flags)
3256 {
3257         int match_flags = 0;
3258
3259 #define MAP_FLAG(gen_flag, mcdi_field) {                                \
3260                 u32 old_mcdi_flags = mcdi_flags;                        \
3261                 mcdi_flags &= ~(1 << MC_CMD_FILTER_OP_IN_MATCH_ ##      \
3262                                 mcdi_field ## _LBN);                    \
3263                 if (mcdi_flags != old_mcdi_flags)                       \
3264                         match_flags |= EFX_FILTER_MATCH_ ## gen_flag;   \
3265         }
3266         MAP_FLAG(LOC_MAC_IG, UNKNOWN_UCAST_DST);
3267         MAP_FLAG(LOC_MAC_IG, UNKNOWN_MCAST_DST);
3268         MAP_FLAG(REM_HOST, SRC_IP);
3269         MAP_FLAG(LOC_HOST, DST_IP);
3270         MAP_FLAG(REM_MAC, SRC_MAC);
3271         MAP_FLAG(REM_PORT, SRC_PORT);
3272         MAP_FLAG(LOC_MAC, DST_MAC);
3273         MAP_FLAG(LOC_PORT, DST_PORT);
3274         MAP_FLAG(ETHER_TYPE, ETHER_TYPE);
3275         MAP_FLAG(INNER_VID, INNER_VLAN);
3276         MAP_FLAG(OUTER_VID, OUTER_VLAN);
3277         MAP_FLAG(IP_PROTO, IP_PROTO);
3278 #undef MAP_FLAG
3279
3280         /* Did we map them all? */
3281         if (mcdi_flags)
3282                 return -EINVAL;
3283
3284         return match_flags;
3285 }
3286
3287 static int efx_ef10_filter_table_probe(struct efx_nic *efx)
3288 {
3289         MCDI_DECLARE_BUF(inbuf, MC_CMD_GET_PARSER_DISP_INFO_IN_LEN);
3290         MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_PARSER_DISP_INFO_OUT_LENMAX);
3291         unsigned int pd_match_pri, pd_match_count;
3292         struct efx_ef10_filter_table *table;
3293         size_t outlen;
3294         int rc;
3295
3296         table = kzalloc(sizeof(*table), GFP_KERNEL);
3297         if (!table)
3298                 return -ENOMEM;
3299
3300         /* Find out which RX filter types are supported, and their priorities */
3301         MCDI_SET_DWORD(inbuf, GET_PARSER_DISP_INFO_IN_OP,
3302                        MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_RX_MATCHES);
3303         rc = efx_mcdi_rpc(efx, MC_CMD_GET_PARSER_DISP_INFO,
3304                           inbuf, sizeof(inbuf), outbuf, sizeof(outbuf),
3305                           &outlen);
3306         if (rc)
3307                 goto fail;
3308         pd_match_count = MCDI_VAR_ARRAY_LEN(
3309                 outlen, GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES);
3310         table->rx_match_count = 0;
3311
3312         for (pd_match_pri = 0; pd_match_pri < pd_match_count; pd_match_pri++) {
3313                 u32 mcdi_flags =
3314                         MCDI_ARRAY_DWORD(
3315                                 outbuf,
3316                                 GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES,
3317                                 pd_match_pri);
3318                 rc = efx_ef10_filter_match_flags_from_mcdi(mcdi_flags);
3319                 if (rc < 0) {
3320                         netif_dbg(efx, probe, efx->net_dev,
3321                                   "%s: fw flags %#x pri %u not supported in driver\n",
3322                                   __func__, mcdi_flags, pd_match_pri);
3323                 } else {
3324                         netif_dbg(efx, probe, efx->net_dev,
3325                                   "%s: fw flags %#x pri %u supported as driver flags %#x pri %u\n",
3326                                   __func__, mcdi_flags, pd_match_pri,
3327                                   rc, table->rx_match_count);
3328                         table->rx_match_flags[table->rx_match_count++] = rc;
3329                 }
3330         }
3331
3332         table->entry = vzalloc(HUNT_FILTER_TBL_ROWS * sizeof(*table->entry));
3333         if (!table->entry) {
3334                 rc = -ENOMEM;
3335                 goto fail;
3336         }
3337
3338         efx->filter_state = table;
3339         init_waitqueue_head(&table->waitq);
3340         return 0;
3341
3342 fail:
3343         kfree(table);
3344         return rc;
3345 }
3346
3347 /* Caller must hold efx->filter_sem for read if race against
3348  * efx_ef10_filter_table_remove() is possible
3349  */
3350 static void efx_ef10_filter_table_restore(struct efx_nic *efx)
3351 {
3352         struct efx_ef10_filter_table *table = efx->filter_state;
3353         struct efx_ef10_nic_data *nic_data = efx->nic_data;
3354         struct efx_filter_spec *spec;
3355         unsigned int filter_idx;
3356         bool failed = false;
3357         int rc;
3358
3359         WARN_ON(!rwsem_is_locked(&efx->filter_sem));
3360
3361         if (!nic_data->must_restore_filters)
3362                 return;
3363
3364         if (!table)
3365                 return;
3366
3367         spin_lock_bh(&efx->filter_lock);
3368
3369         for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
3370                 spec = efx_ef10_filter_entry_spec(table, filter_idx);
3371                 if (!spec)
3372                         continue;
3373
3374                 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_BUSY;
3375                 spin_unlock_bh(&efx->filter_lock);
3376
3377                 rc = efx_ef10_filter_push(efx, spec,
3378                                           &table->entry[filter_idx].handle,
3379                                           false);
3380                 if (rc)
3381                         failed = true;
3382
3383                 spin_lock_bh(&efx->filter_lock);
3384                 if (rc) {
3385                         kfree(spec);
3386                         efx_ef10_filter_set_entry(table, filter_idx, NULL, 0);
3387                 } else {
3388                         table->entry[filter_idx].spec &=
3389                                 ~EFX_EF10_FILTER_FLAG_BUSY;
3390                 }
3391         }
3392
3393         spin_unlock_bh(&efx->filter_lock);
3394
3395         if (failed)
3396                 netif_err(efx, hw, efx->net_dev,
3397                           "unable to restore all filters\n");
3398         else
3399                 nic_data->must_restore_filters = false;
3400 }
3401
3402 /* Caller must hold efx->filter_sem for write */
3403 static void efx_ef10_filter_table_remove(struct efx_nic *efx)
3404 {
3405         struct efx_ef10_filter_table *table = efx->filter_state;
3406         MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN);
3407         struct efx_filter_spec *spec;
3408         unsigned int filter_idx;
3409         int rc;
3410
3411         efx->filter_state = NULL;
3412         if (!table)
3413                 return;
3414
3415         for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
3416                 spec = efx_ef10_filter_entry_spec(table, filter_idx);
3417                 if (!spec)
3418                         continue;
3419
3420                 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
3421                                efx_ef10_filter_is_exclusive(spec) ?
3422                                MC_CMD_FILTER_OP_IN_OP_REMOVE :
3423                                MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE);
3424                 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
3425                                table->entry[filter_idx].handle);
3426                 rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf),
3427                                   NULL, 0, NULL);
3428                 if (rc)
3429                         netdev_WARN(efx->net_dev,
3430                                     "filter_idx=%#x handle=%#llx\n",
3431                                     filter_idx,
3432                                     table->entry[filter_idx].handle);
3433                 kfree(spec);
3434         }
3435
3436         vfree(table->entry);
3437         kfree(table);
3438 }
3439
3440 /* Caller must hold efx->filter_sem for read if race against
3441  * efx_ef10_filter_table_remove() is possible
3442  */
3443 static void efx_ef10_filter_sync_rx_mode(struct efx_nic *efx)
3444 {
3445         struct efx_ef10_filter_table *table = efx->filter_state;
3446         struct net_device *net_dev = efx->net_dev;
3447         struct efx_filter_spec spec;
3448         bool remove_failed = false;
3449         struct netdev_hw_addr *uc;
3450         struct netdev_hw_addr *mc;
3451         unsigned int filter_idx;
3452         int i, n, rc;
3453
3454         if (!efx_dev_registered(efx))
3455                 return;
3456
3457         if (!table)
3458                 return;
3459
3460         /* Mark old filters that may need to be removed */
3461         spin_lock_bh(&efx->filter_lock);
3462         n = table->dev_uc_count < 0 ? 1 : table->dev_uc_count;
3463         for (i = 0; i < n; i++) {
3464                 filter_idx = table->dev_uc_list[i].id % HUNT_FILTER_TBL_ROWS;
3465                 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_AUTO_OLD;
3466         }
3467         n = table->dev_mc_count < 0 ? 1 : table->dev_mc_count;
3468         for (i = 0; i < n; i++) {
3469                 filter_idx = table->dev_mc_list[i].id % HUNT_FILTER_TBL_ROWS;
3470                 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_AUTO_OLD;
3471         }
3472         spin_unlock_bh(&efx->filter_lock);
3473
3474         /* Copy/convert the address lists; add the primary station
3475          * address and broadcast address
3476          */
3477         netif_addr_lock_bh(net_dev);
3478         if (net_dev->flags & IFF_PROMISC ||
3479             netdev_uc_count(net_dev) >= EFX_EF10_FILTER_DEV_UC_MAX) {
3480                 table->dev_uc_count = -1;
3481         } else {
3482                 table->dev_uc_count = 1 + netdev_uc_count(net_dev);
3483                 ether_addr_copy(table->dev_uc_list[0].addr, net_dev->dev_addr);
3484                 i = 1;
3485                 netdev_for_each_uc_addr(uc, net_dev) {
3486                         ether_addr_copy(table->dev_uc_list[i].addr, uc->addr);
3487                         i++;
3488                 }
3489         }
3490         if (net_dev->flags & (IFF_PROMISC | IFF_ALLMULTI) ||
3491             netdev_mc_count(net_dev) >= EFX_EF10_FILTER_DEV_MC_MAX) {
3492                 table->dev_mc_count = -1;
3493         } else {
3494                 table->dev_mc_count = 1 + netdev_mc_count(net_dev);
3495                 eth_broadcast_addr(table->dev_mc_list[0].addr);
3496                 i = 1;
3497                 netdev_for_each_mc_addr(mc, net_dev) {
3498                         ether_addr_copy(table->dev_mc_list[i].addr, mc->addr);
3499                         i++;
3500                 }
3501         }
3502         netif_addr_unlock_bh(net_dev);
3503
3504         /* Insert/renew unicast filters */
3505         if (table->dev_uc_count >= 0) {
3506                 for (i = 0; i < table->dev_uc_count; i++) {
3507                         efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO,
3508                                            EFX_FILTER_FLAG_RX_RSS,
3509                                            0);
3510                         efx_filter_set_eth_local(&spec, EFX_FILTER_VID_UNSPEC,
3511                                                  table->dev_uc_list[i].addr);
3512                         rc = efx_ef10_filter_insert(efx, &spec, true);
3513                         if (rc < 0) {
3514                                 /* Fall back to unicast-promisc */
3515                                 while (i--)
3516                                         efx_ef10_filter_remove_safe(
3517                                                 efx, EFX_FILTER_PRI_AUTO,
3518                                                 table->dev_uc_list[i].id);
3519                                 table->dev_uc_count = -1;
3520                                 break;
3521                         }
3522                         table->dev_uc_list[i].id = rc;
3523                 }
3524         }
3525         if (table->dev_uc_count < 0) {
3526                 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO,
3527                                    EFX_FILTER_FLAG_RX_RSS,
3528                                    0);
3529                 efx_filter_set_uc_def(&spec);
3530                 rc = efx_ef10_filter_insert(efx, &spec, true);
3531                 if (rc < 0) {
3532                         WARN_ON(1);
3533                         table->dev_uc_count = 0;
3534                 } else {
3535                         table->dev_uc_list[0].id = rc;
3536                 }
3537         }
3538
3539         /* Insert/renew multicast filters */
3540         if (table->dev_mc_count >= 0) {
3541                 for (i = 0; i < table->dev_mc_count; i++) {
3542                         efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO,
3543                                            EFX_FILTER_FLAG_RX_RSS,
3544                                            0);
3545                         efx_filter_set_eth_local(&spec, EFX_FILTER_VID_UNSPEC,
3546                                                  table->dev_mc_list[i].addr);
3547                         rc = efx_ef10_filter_insert(efx, &spec, true);
3548                         if (rc < 0) {
3549                                 /* Fall back to multicast-promisc */
3550                                 while (i--)
3551                                         efx_ef10_filter_remove_safe(
3552                                                 efx, EFX_FILTER_PRI_AUTO,
3553                                                 table->dev_mc_list[i].id);
3554                                 table->dev_mc_count = -1;
3555                                 break;
3556                         }
3557                         table->dev_mc_list[i].id = rc;
3558                 }
3559         }
3560         if (table->dev_mc_count < 0) {
3561                 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO,
3562                                    EFX_FILTER_FLAG_RX_RSS,
3563                                    0);
3564                 efx_filter_set_mc_def(&spec);
3565                 rc = efx_ef10_filter_insert(efx, &spec, true);
3566                 if (rc < 0) {
3567                         WARN_ON(1);
3568                         table->dev_mc_count = 0;
3569                 } else {
3570                         table->dev_mc_list[0].id = rc;
3571                 }
3572         }
3573
3574         /* Remove filters that weren't renewed.  Since nothing else
3575          * changes the AUTO_OLD flag or removes these filters, we
3576          * don't need to hold the filter_lock while scanning for
3577          * these filters.
3578          */
3579         for (i = 0; i < HUNT_FILTER_TBL_ROWS; i++) {
3580                 if (ACCESS_ONCE(table->entry[i].spec) &
3581                     EFX_EF10_FILTER_FLAG_AUTO_OLD) {
3582                         if (efx_ef10_filter_remove_internal(
3583                                     efx, 1U << EFX_FILTER_PRI_AUTO,
3584                                     i, true) < 0)
3585                                 remove_failed = true;
3586                 }
3587         }
3588         WARN_ON(remove_failed);
3589 }
3590
3591 static int efx_ef10_mac_reconfigure(struct efx_nic *efx)
3592 {
3593         efx_ef10_filter_sync_rx_mode(efx);
3594
3595         return efx_mcdi_set_mac(efx);
3596 }
3597
3598 static int efx_ef10_mac_reconfigure_vf(struct efx_nic *efx)
3599 {
3600         efx_ef10_filter_sync_rx_mode(efx);
3601
3602         return 0;
3603 }
3604
3605 static int efx_ef10_start_bist(struct efx_nic *efx, u32 bist_type)
3606 {
3607         MCDI_DECLARE_BUF(inbuf, MC_CMD_START_BIST_IN_LEN);
3608
3609         MCDI_SET_DWORD(inbuf, START_BIST_IN_TYPE, bist_type);
3610         return efx_mcdi_rpc(efx, MC_CMD_START_BIST, inbuf, sizeof(inbuf),
3611                             NULL, 0, NULL);
3612 }
3613
3614 /* MC BISTs follow a different poll mechanism to phy BISTs.
3615  * The BIST is done in the poll handler on the MC, and the MCDI command
3616  * will block until the BIST is done.
3617  */
3618 static int efx_ef10_poll_bist(struct efx_nic *efx)
3619 {
3620         int rc;
3621         MCDI_DECLARE_BUF(outbuf, MC_CMD_POLL_BIST_OUT_LEN);
3622         size_t outlen;
3623         u32 result;
3624
3625         rc = efx_mcdi_rpc(efx, MC_CMD_POLL_BIST, NULL, 0,
3626                            outbuf, sizeof(outbuf), &outlen);
3627         if (rc != 0)
3628                 return rc;
3629
3630         if (outlen < MC_CMD_POLL_BIST_OUT_LEN)
3631                 return -EIO;
3632
3633         result = MCDI_DWORD(outbuf, POLL_BIST_OUT_RESULT);
3634         switch (result) {
3635         case MC_CMD_POLL_BIST_PASSED:
3636                 netif_dbg(efx, hw, efx->net_dev, "BIST passed.\n");
3637                 return 0;
3638         case MC_CMD_POLL_BIST_TIMEOUT:
3639                 netif_err(efx, hw, efx->net_dev, "BIST timed out\n");
3640                 return -EIO;
3641         case MC_CMD_POLL_BIST_FAILED:
3642                 netif_err(efx, hw, efx->net_dev, "BIST failed.\n");
3643                 return -EIO;
3644         default:
3645                 netif_err(efx, hw, efx->net_dev,
3646                           "BIST returned unknown result %u", result);
3647                 return -EIO;
3648         }
3649 }
3650
3651 static int efx_ef10_run_bist(struct efx_nic *efx, u32 bist_type)
3652 {
3653         int rc;
3654
3655         netif_dbg(efx, drv, efx->net_dev, "starting BIST type %u\n", bist_type);
3656
3657         rc = efx_ef10_start_bist(efx, bist_type);
3658         if (rc != 0)
3659                 return rc;
3660
3661         return efx_ef10_poll_bist(efx);
3662 }
3663
3664 static int
3665 efx_ef10_test_chip(struct efx_nic *efx, struct efx_self_tests *tests)
3666 {
3667         int rc, rc2;
3668
3669         efx_reset_down(efx, RESET_TYPE_WORLD);
3670
3671         rc = efx_mcdi_rpc(efx, MC_CMD_ENABLE_OFFLINE_BIST,
3672                           NULL, 0, NULL, 0, NULL);
3673         if (rc != 0)
3674                 goto out;
3675
3676         tests->memory = efx_ef10_run_bist(efx, MC_CMD_MC_MEM_BIST) ? -1 : 1;
3677         tests->registers = efx_ef10_run_bist(efx, MC_CMD_REG_BIST) ? -1 : 1;
3678
3679         rc = efx_mcdi_reset(efx, RESET_TYPE_WORLD);
3680
3681 out:
3682         rc2 = efx_reset_up(efx, RESET_TYPE_WORLD, rc == 0);
3683         return rc ? rc : rc2;
3684 }
3685
3686 #ifdef CONFIG_SFC_MTD
3687
3688 struct efx_ef10_nvram_type_info {
3689         u16 type, type_mask;
3690         u8 port;
3691         const char *name;
3692 };
3693
3694 static const struct efx_ef10_nvram_type_info efx_ef10_nvram_types[] = {
3695         { NVRAM_PARTITION_TYPE_MC_FIRMWARE,        0,    0, "sfc_mcfw" },
3696         { NVRAM_PARTITION_TYPE_MC_FIRMWARE_BACKUP, 0,    0, "sfc_mcfw_backup" },
3697         { NVRAM_PARTITION_TYPE_EXPANSION_ROM,      0,    0, "sfc_exp_rom" },
3698         { NVRAM_PARTITION_TYPE_STATIC_CONFIG,      0,    0, "sfc_static_cfg" },
3699         { NVRAM_PARTITION_TYPE_DYNAMIC_CONFIG,     0,    0, "sfc_dynamic_cfg" },
3700         { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT0, 0,   0, "sfc_exp_rom_cfg" },
3701         { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT1, 0,   1, "sfc_exp_rom_cfg" },
3702         { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT2, 0,   2, "sfc_exp_rom_cfg" },
3703         { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT3, 0,   3, "sfc_exp_rom_cfg" },
3704         { NVRAM_PARTITION_TYPE_LICENSE,            0,    0, "sfc_license" },
3705         { NVRAM_PARTITION_TYPE_PHY_MIN,            0xff, 0, "sfc_phy_fw" },
3706 };
3707
3708 static int efx_ef10_mtd_probe_partition(struct efx_nic *efx,
3709                                         struct efx_mcdi_mtd_partition *part,
3710                                         unsigned int type)
3711 {
3712         MCDI_DECLARE_BUF(inbuf, MC_CMD_NVRAM_METADATA_IN_LEN);
3713         MCDI_DECLARE_BUF(outbuf, MC_CMD_NVRAM_METADATA_OUT_LENMAX);
3714         const struct efx_ef10_nvram_type_info *info;
3715         size_t size, erase_size, outlen;
3716         bool protected;
3717         int rc;
3718
3719         for (info = efx_ef10_nvram_types; ; info++) {
3720                 if (info ==
3721                     efx_ef10_nvram_types + ARRAY_SIZE(efx_ef10_nvram_types))
3722                         return -ENODEV;
3723                 if ((type & ~info->type_mask) == info->type)
3724                         break;
3725         }
3726         if (info->port != efx_port_num(efx))
3727                 return -ENODEV;
3728
3729         rc = efx_mcdi_nvram_info(efx, type, &size, &erase_size, &protected);
3730         if (rc)
3731                 return rc;
3732         if (protected)
3733                 return -ENODEV; /* hide it */
3734
3735         part->nvram_type = type;
3736
3737         MCDI_SET_DWORD(inbuf, NVRAM_METADATA_IN_TYPE, type);
3738         rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_METADATA, inbuf, sizeof(inbuf),
3739                           outbuf, sizeof(outbuf), &outlen);
3740         if (rc)
3741                 return rc;
3742         if (outlen < MC_CMD_NVRAM_METADATA_OUT_LENMIN)
3743                 return -EIO;
3744         if (MCDI_DWORD(outbuf, NVRAM_METADATA_OUT_FLAGS) &
3745             (1 << MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_VALID_LBN))
3746                 part->fw_subtype = MCDI_DWORD(outbuf,
3747                                               NVRAM_METADATA_OUT_SUBTYPE);
3748
3749         part->common.dev_type_name = "EF10 NVRAM manager";
3750         part->common.type_name = info->name;
3751
3752         part->common.mtd.type = MTD_NORFLASH;
3753         part->common.mtd.flags = MTD_CAP_NORFLASH;
3754         part->common.mtd.size = size;
3755         part->common.mtd.erasesize = erase_size;
3756
3757         return 0;
3758 }
3759
3760 static int efx_ef10_mtd_probe(struct efx_nic *efx)
3761 {
3762         MCDI_DECLARE_BUF(outbuf, MC_CMD_NVRAM_PARTITIONS_OUT_LENMAX);
3763         struct efx_mcdi_mtd_partition *parts;
3764         size_t outlen, n_parts_total, i, n_parts;
3765         unsigned int type;
3766         int rc;
3767
3768         ASSERT_RTNL();
3769
3770         BUILD_BUG_ON(MC_CMD_NVRAM_PARTITIONS_IN_LEN != 0);
3771         rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_PARTITIONS, NULL, 0,
3772                           outbuf, sizeof(outbuf), &outlen);
3773         if (rc)
3774                 return rc;
3775         if (outlen < MC_CMD_NVRAM_PARTITIONS_OUT_LENMIN)
3776                 return -EIO;
3777
3778         n_parts_total = MCDI_DWORD(outbuf, NVRAM_PARTITIONS_OUT_NUM_PARTITIONS);
3779         if (n_parts_total >
3780             MCDI_VAR_ARRAY_LEN(outlen, NVRAM_PARTITIONS_OUT_TYPE_ID))
3781                 return -EIO;
3782
3783         parts = kcalloc(n_parts_total, sizeof(*parts), GFP_KERNEL);
3784         if (!parts)
3785                 return -ENOMEM;
3786
3787         n_parts = 0;
3788         for (i = 0; i < n_parts_total; i++) {
3789                 type = MCDI_ARRAY_DWORD(outbuf, NVRAM_PARTITIONS_OUT_TYPE_ID,
3790                                         i);
3791                 rc = efx_ef10_mtd_probe_partition(efx, &parts[n_parts], type);
3792                 if (rc == 0)
3793                         n_parts++;
3794                 else if (rc != -ENODEV)
3795                         goto fail;
3796         }
3797
3798         rc = efx_mtd_add(efx, &parts[0].common, n_parts, sizeof(*parts));
3799 fail:
3800         if (rc)
3801                 kfree(parts);
3802         return rc;
3803 }
3804
3805 #endif /* CONFIG_SFC_MTD */
3806
3807 static void efx_ef10_ptp_write_host_time(struct efx_nic *efx, u32 host_time)
3808 {
3809         _efx_writed(efx, cpu_to_le32(host_time), ER_DZ_MC_DB_LWRD);
3810 }
3811
3812 static void efx_ef10_ptp_write_host_time_vf(struct efx_nic *efx,
3813                                             u32 host_time) {}
3814
3815 static int efx_ef10_rx_enable_timestamping(struct efx_channel *channel,
3816                                            bool temp)
3817 {
3818         MCDI_DECLARE_BUF(inbuf, MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_LEN);
3819         int rc;
3820
3821         if (channel->sync_events_state == SYNC_EVENTS_REQUESTED ||
3822             channel->sync_events_state == SYNC_EVENTS_VALID ||
3823             (temp && channel->sync_events_state == SYNC_EVENTS_DISABLED))
3824                 return 0;
3825         channel->sync_events_state = SYNC_EVENTS_REQUESTED;
3826
3827         MCDI_SET_DWORD(inbuf, PTP_IN_OP, MC_CMD_PTP_OP_TIME_EVENT_SUBSCRIBE);
3828         MCDI_SET_DWORD(inbuf, PTP_IN_PERIPH_ID, 0);
3829         MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE,
3830                        channel->channel);
3831
3832         rc = efx_mcdi_rpc(channel->efx, MC_CMD_PTP,
3833                           inbuf, sizeof(inbuf), NULL, 0, NULL);
3834
3835         if (rc != 0)
3836                 channel->sync_events_state = temp ? SYNC_EVENTS_QUIESCENT :
3837                                                     SYNC_EVENTS_DISABLED;
3838
3839         return rc;
3840 }
3841
3842 static int efx_ef10_rx_disable_timestamping(struct efx_channel *channel,
3843                                             bool temp)
3844 {
3845         MCDI_DECLARE_BUF(inbuf, MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_LEN);
3846         int rc;
3847
3848         if (channel->sync_events_state == SYNC_EVENTS_DISABLED ||
3849             (temp && channel->sync_events_state == SYNC_EVENTS_QUIESCENT))
3850                 return 0;
3851         if (channel->sync_events_state == SYNC_EVENTS_QUIESCENT) {
3852                 channel->sync_events_state = SYNC_EVENTS_DISABLED;
3853                 return 0;
3854         }
3855         channel->sync_events_state = temp ? SYNC_EVENTS_QUIESCENT :
3856                                             SYNC_EVENTS_DISABLED;
3857
3858         MCDI_SET_DWORD(inbuf, PTP_IN_OP, MC_CMD_PTP_OP_TIME_EVENT_UNSUBSCRIBE);
3859         MCDI_SET_DWORD(inbuf, PTP_IN_PERIPH_ID, 0);
3860         MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_UNSUBSCRIBE_CONTROL,
3861                        MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_SINGLE);
3862         MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_UNSUBSCRIBE_QUEUE,
3863                        channel->channel);
3864
3865         rc = efx_mcdi_rpc(channel->efx, MC_CMD_PTP,
3866                           inbuf, sizeof(inbuf), NULL, 0, NULL);
3867
3868         return rc;
3869 }
3870
3871 static int efx_ef10_ptp_set_ts_sync_events(struct efx_nic *efx, bool en,
3872                                            bool temp)
3873 {
3874         int (*set)(struct efx_channel *channel, bool temp);
3875         struct efx_channel *channel;
3876
3877         set = en ?
3878               efx_ef10_rx_enable_timestamping :
3879               efx_ef10_rx_disable_timestamping;
3880
3881         efx_for_each_channel(channel, efx) {
3882                 int rc = set(channel, temp);
3883                 if (en && rc != 0) {
3884                         efx_ef10_ptp_set_ts_sync_events(efx, false, temp);
3885                         return rc;
3886                 }
3887         }
3888
3889         return 0;
3890 }
3891
3892 static int efx_ef10_ptp_set_ts_config_vf(struct efx_nic *efx,
3893                                          struct hwtstamp_config *init)
3894 {
3895         return -EOPNOTSUPP;
3896 }
3897
3898 static int efx_ef10_ptp_set_ts_config(struct efx_nic *efx,
3899                                       struct hwtstamp_config *init)
3900 {
3901         int rc;
3902
3903         switch (init->rx_filter) {
3904         case HWTSTAMP_FILTER_NONE:
3905                 efx_ef10_ptp_set_ts_sync_events(efx, false, false);
3906                 /* if TX timestamping is still requested then leave PTP on */
3907                 return efx_ptp_change_mode(efx,
3908                                            init->tx_type != HWTSTAMP_TX_OFF, 0);
3909         case HWTSTAMP_FILTER_ALL:
3910         case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
3911         case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
3912         case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
3913         case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
3914         case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
3915         case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
3916         case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
3917         case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
3918         case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
3919         case HWTSTAMP_FILTER_PTP_V2_EVENT:
3920         case HWTSTAMP_FILTER_PTP_V2_SYNC:
3921         case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
3922                 init->rx_filter = HWTSTAMP_FILTER_ALL;
3923                 rc = efx_ptp_change_mode(efx, true, 0);
3924                 if (!rc)
3925                         rc = efx_ef10_ptp_set_ts_sync_events(efx, true, false);
3926                 if (rc)
3927                         efx_ptp_change_mode(efx, false, 0);
3928                 return rc;
3929         default:
3930                 return -ERANGE;
3931         }
3932 }
3933
3934 const struct efx_nic_type efx_hunt_a0_vf_nic_type = {
3935         .is_vf = true,
3936         .mem_bar = EFX_MEM_VF_BAR,
3937         .mem_map_size = efx_ef10_mem_map_size,
3938         .probe = efx_ef10_probe_vf,
3939         .remove = efx_ef10_remove,
3940         .dimension_resources = efx_ef10_dimension_resources,
3941         .init = efx_ef10_init_nic,
3942         .fini = efx_port_dummy_op_void,
3943         .map_reset_reason = efx_mcdi_map_reset_reason,
3944         .map_reset_flags = efx_ef10_map_reset_flags,
3945         .reset = efx_ef10_reset,
3946         .probe_port = efx_mcdi_port_probe,
3947         .remove_port = efx_mcdi_port_remove,
3948         .fini_dmaq = efx_ef10_fini_dmaq,
3949         .prepare_flr = efx_ef10_prepare_flr,
3950         .finish_flr = efx_port_dummy_op_void,
3951         .describe_stats = efx_ef10_describe_stats,
3952         .update_stats = efx_ef10_update_stats,
3953         .start_stats = efx_port_dummy_op_void,
3954         .pull_stats = efx_port_dummy_op_void,
3955         .stop_stats = efx_port_dummy_op_void,
3956         .set_id_led = efx_mcdi_set_id_led,
3957         .push_irq_moderation = efx_ef10_push_irq_moderation,
3958         .reconfigure_mac = efx_ef10_mac_reconfigure_vf,
3959         .check_mac_fault = efx_mcdi_mac_check_fault,
3960         .reconfigure_port = efx_mcdi_port_reconfigure,
3961         .get_wol = efx_ef10_get_wol_vf,
3962         .set_wol = efx_ef10_set_wol_vf,
3963         .resume_wol = efx_port_dummy_op_void,
3964         .mcdi_request = efx_ef10_mcdi_request,
3965         .mcdi_poll_response = efx_ef10_mcdi_poll_response,
3966         .mcdi_read_response = efx_ef10_mcdi_read_response,
3967         .mcdi_poll_reboot = efx_ef10_mcdi_poll_reboot,
3968         .irq_enable_master = efx_port_dummy_op_void,
3969         .irq_test_generate = efx_ef10_irq_test_generate,
3970         .irq_disable_non_ev = efx_port_dummy_op_void,
3971         .irq_handle_msi = efx_ef10_msi_interrupt,
3972         .irq_handle_legacy = efx_ef10_legacy_interrupt,
3973         .tx_probe = efx_ef10_tx_probe,
3974         .tx_init = efx_ef10_tx_init,
3975         .tx_remove = efx_ef10_tx_remove,
3976         .tx_write = efx_ef10_tx_write,
3977         .rx_push_rss_config = efx_ef10_vf_rx_push_rss_config,
3978         .rx_probe = efx_ef10_rx_probe,
3979         .rx_init = efx_ef10_rx_init,
3980         .rx_remove = efx_ef10_rx_remove,
3981         .rx_write = efx_ef10_rx_write,
3982         .rx_defer_refill = efx_ef10_rx_defer_refill,
3983         .ev_probe = efx_ef10_ev_probe,
3984         .ev_init = efx_ef10_ev_init,
3985         .ev_fini = efx_ef10_ev_fini,
3986         .ev_remove = efx_ef10_ev_remove,
3987         .ev_process = efx_ef10_ev_process,
3988         .ev_read_ack = efx_ef10_ev_read_ack,
3989         .ev_test_generate = efx_ef10_ev_test_generate,
3990         .filter_table_probe = efx_ef10_filter_table_probe,
3991         .filter_table_restore = efx_ef10_filter_table_restore,
3992         .filter_table_remove = efx_ef10_filter_table_remove,
3993         .filter_update_rx_scatter = efx_ef10_filter_update_rx_scatter,
3994         .filter_insert = efx_ef10_filter_insert,
3995         .filter_remove_safe = efx_ef10_filter_remove_safe,
3996         .filter_get_safe = efx_ef10_filter_get_safe,
3997         .filter_clear_rx = efx_ef10_filter_clear_rx,
3998         .filter_count_rx_used = efx_ef10_filter_count_rx_used,
3999         .filter_get_rx_id_limit = efx_ef10_filter_get_rx_id_limit,
4000         .filter_get_rx_ids = efx_ef10_filter_get_rx_ids,
4001 #ifdef CONFIG_RFS_ACCEL
4002         .filter_rfs_insert = efx_ef10_filter_rfs_insert,
4003         .filter_rfs_expire_one = efx_ef10_filter_rfs_expire_one,
4004 #endif
4005 #ifdef CONFIG_SFC_MTD
4006         .mtd_probe = efx_port_dummy_op_int,
4007 #endif
4008         .ptp_write_host_time = efx_ef10_ptp_write_host_time_vf,
4009         .ptp_set_ts_config = efx_ef10_ptp_set_ts_config_vf,
4010 #ifdef CONFIG_SFC_SRIOV
4011         .vswitching_probe = efx_ef10_vswitching_probe_vf,
4012         .vswitching_restore = efx_ef10_vswitching_restore_vf,
4013         .vswitching_remove = efx_ef10_vswitching_remove_vf,
4014 #endif
4015         .get_mac_address = efx_ef10_get_mac_address_vf,
4016
4017         .revision = EFX_REV_HUNT_A0,
4018         .max_dma_mask = DMA_BIT_MASK(ESF_DZ_TX_KER_BUF_ADDR_WIDTH),
4019         .rx_prefix_size = ES_DZ_RX_PREFIX_SIZE,
4020         .rx_hash_offset = ES_DZ_RX_PREFIX_HASH_OFST,
4021         .rx_ts_offset = ES_DZ_RX_PREFIX_TSTAMP_OFST,
4022         .can_rx_scatter = true,
4023         .always_rx_scatter = true,
4024         .max_interrupt_mode = EFX_INT_MODE_MSIX,
4025         .timer_period_max = 1 << ERF_DD_EVQ_IND_TIMER_VAL_WIDTH,
4026         .offload_features = (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
4027                              NETIF_F_RXHASH | NETIF_F_NTUPLE),
4028         .mcdi_max_ver = 2,
4029         .max_rx_ip_filters = HUNT_FILTER_TBL_ROWS,
4030         .hwtstamp_filters = 1 << HWTSTAMP_FILTER_NONE |
4031                             1 << HWTSTAMP_FILTER_ALL,
4032 };
4033
4034 const struct efx_nic_type efx_hunt_a0_nic_type = {
4035         .is_vf = false,
4036         .mem_bar = EFX_MEM_BAR,
4037         .mem_map_size = efx_ef10_mem_map_size,
4038         .probe = efx_ef10_probe_pf,
4039         .remove = efx_ef10_remove,
4040         .dimension_resources = efx_ef10_dimension_resources,
4041         .init = efx_ef10_init_nic,
4042         .fini = efx_port_dummy_op_void,
4043         .map_reset_reason = efx_mcdi_map_reset_reason,
4044         .map_reset_flags = efx_ef10_map_reset_flags,
4045         .reset = efx_ef10_reset,
4046         .probe_port = efx_mcdi_port_probe,
4047         .remove_port = efx_mcdi_port_remove,
4048         .fini_dmaq = efx_ef10_fini_dmaq,
4049         .prepare_flr = efx_ef10_prepare_flr,
4050         .finish_flr = efx_port_dummy_op_void,
4051         .describe_stats = efx_ef10_describe_stats,
4052         .update_stats = efx_ef10_update_stats,
4053         .start_stats = efx_mcdi_mac_start_stats,
4054         .pull_stats = efx_mcdi_mac_pull_stats,
4055         .stop_stats = efx_mcdi_mac_stop_stats,
4056         .set_id_led = efx_mcdi_set_id_led,
4057         .push_irq_moderation = efx_ef10_push_irq_moderation,
4058         .reconfigure_mac = efx_ef10_mac_reconfigure,
4059         .check_mac_fault = efx_mcdi_mac_check_fault,
4060         .reconfigure_port = efx_mcdi_port_reconfigure,
4061         .get_wol = efx_ef10_get_wol,
4062         .set_wol = efx_ef10_set_wol,
4063         .resume_wol = efx_port_dummy_op_void,
4064         .test_chip = efx_ef10_test_chip,
4065         .test_nvram = efx_mcdi_nvram_test_all,
4066         .mcdi_request = efx_ef10_mcdi_request,
4067         .mcdi_poll_response = efx_ef10_mcdi_poll_response,
4068         .mcdi_read_response = efx_ef10_mcdi_read_response,
4069         .mcdi_poll_reboot = efx_ef10_mcdi_poll_reboot,
4070         .irq_enable_master = efx_port_dummy_op_void,
4071         .irq_test_generate = efx_ef10_irq_test_generate,
4072         .irq_disable_non_ev = efx_port_dummy_op_void,
4073         .irq_handle_msi = efx_ef10_msi_interrupt,
4074         .irq_handle_legacy = efx_ef10_legacy_interrupt,
4075         .tx_probe = efx_ef10_tx_probe,
4076         .tx_init = efx_ef10_tx_init,
4077         .tx_remove = efx_ef10_tx_remove,
4078         .tx_write = efx_ef10_tx_write,
4079         .rx_push_rss_config = efx_ef10_pf_rx_push_rss_config,
4080         .rx_probe = efx_ef10_rx_probe,
4081         .rx_init = efx_ef10_rx_init,
4082         .rx_remove = efx_ef10_rx_remove,
4083         .rx_write = efx_ef10_rx_write,
4084         .rx_defer_refill = efx_ef10_rx_defer_refill,
4085         .ev_probe = efx_ef10_ev_probe,
4086         .ev_init = efx_ef10_ev_init,
4087         .ev_fini = efx_ef10_ev_fini,
4088         .ev_remove = efx_ef10_ev_remove,
4089         .ev_process = efx_ef10_ev_process,
4090         .ev_read_ack = efx_ef10_ev_read_ack,
4091         .ev_test_generate = efx_ef10_ev_test_generate,
4092         .filter_table_probe = efx_ef10_filter_table_probe,
4093         .filter_table_restore = efx_ef10_filter_table_restore,
4094         .filter_table_remove = efx_ef10_filter_table_remove,
4095         .filter_update_rx_scatter = efx_ef10_filter_update_rx_scatter,
4096         .filter_insert = efx_ef10_filter_insert,
4097         .filter_remove_safe = efx_ef10_filter_remove_safe,
4098         .filter_get_safe = efx_ef10_filter_get_safe,
4099         .filter_clear_rx = efx_ef10_filter_clear_rx,
4100         .filter_count_rx_used = efx_ef10_filter_count_rx_used,
4101         .filter_get_rx_id_limit = efx_ef10_filter_get_rx_id_limit,
4102         .filter_get_rx_ids = efx_ef10_filter_get_rx_ids,
4103 #ifdef CONFIG_RFS_ACCEL
4104         .filter_rfs_insert = efx_ef10_filter_rfs_insert,
4105         .filter_rfs_expire_one = efx_ef10_filter_rfs_expire_one,
4106 #endif
4107 #ifdef CONFIG_SFC_MTD
4108         .mtd_probe = efx_ef10_mtd_probe,
4109         .mtd_rename = efx_mcdi_mtd_rename,
4110         .mtd_read = efx_mcdi_mtd_read,
4111         .mtd_erase = efx_mcdi_mtd_erase,
4112         .mtd_write = efx_mcdi_mtd_write,
4113         .mtd_sync = efx_mcdi_mtd_sync,
4114 #endif
4115         .ptp_write_host_time = efx_ef10_ptp_write_host_time,
4116         .ptp_set_ts_sync_events = efx_ef10_ptp_set_ts_sync_events,
4117         .ptp_set_ts_config = efx_ef10_ptp_set_ts_config,
4118 #ifdef CONFIG_SFC_SRIOV
4119         .sriov_configure = efx_ef10_sriov_configure,
4120         .sriov_init = efx_ef10_sriov_init,
4121         .sriov_fini = efx_ef10_sriov_fini,
4122         .sriov_mac_address_changed = efx_ef10_sriov_mac_address_changed,
4123         .sriov_wanted = efx_ef10_sriov_wanted,
4124         .sriov_reset = efx_ef10_sriov_reset,
4125         .sriov_flr = efx_ef10_sriov_flr,
4126         .sriov_set_vf_mac = efx_ef10_sriov_set_vf_mac,
4127         .sriov_set_vf_vlan = efx_ef10_sriov_set_vf_vlan,
4128         .sriov_set_vf_spoofchk = efx_ef10_sriov_set_vf_spoofchk,
4129         .sriov_get_vf_config = efx_ef10_sriov_get_vf_config,
4130         .vswitching_probe = efx_ef10_vswitching_probe_pf,
4131         .vswitching_restore = efx_ef10_vswitching_restore_pf,
4132         .vswitching_remove = efx_ef10_vswitching_remove_pf,
4133 #endif
4134         .get_mac_address = efx_ef10_get_mac_address_pf,
4135
4136         .revision = EFX_REV_HUNT_A0,
4137         .max_dma_mask = DMA_BIT_MASK(ESF_DZ_TX_KER_BUF_ADDR_WIDTH),
4138         .rx_prefix_size = ES_DZ_RX_PREFIX_SIZE,
4139         .rx_hash_offset = ES_DZ_RX_PREFIX_HASH_OFST,
4140         .rx_ts_offset = ES_DZ_RX_PREFIX_TSTAMP_OFST,
4141         .can_rx_scatter = true,
4142         .always_rx_scatter = true,
4143         .max_interrupt_mode = EFX_INT_MODE_MSIX,
4144         .timer_period_max = 1 << ERF_DD_EVQ_IND_TIMER_VAL_WIDTH,
4145         .offload_features = (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
4146                              NETIF_F_RXHASH | NETIF_F_NTUPLE),
4147         .mcdi_max_ver = 2,
4148         .max_rx_ip_filters = HUNT_FILTER_TBL_ROWS,
4149         .hwtstamp_filters = 1 << HWTSTAMP_FILTER_NONE |
4150                             1 << HWTSTAMP_FILTER_ALL,
4151 };