1 // SPDX-License-Identifier: GPL-2.0-only
2 /****************************************************************************
3 * Driver for Solarflare network controllers and boards
4 * Copyright 2005-2006 Fen Systems Ltd.
5 * Copyright 2005-2013 Solarflare Communications Inc.
8 #include <linux/module.h>
10 #include <linux/netdevice.h>
11 #include <linux/etherdevice.h>
12 #include <linux/delay.h>
13 #include <linux/notifier.h>
15 #include <linux/tcp.h>
17 #include <linux/ethtool.h>
18 #include <linux/topology.h>
19 #include <linux/gfp.h>
20 #include <linux/aer.h>
21 #include <linux/interrupt.h>
22 #include "net_driver.h"
24 #include <net/udp_tunnel.h>
26 #include "efx_common.h"
27 #include "efx_channels.h"
28 #include "rx_common.h"
29 #include "tx_common.h"
36 #include "mcdi_pcol.h"
37 #include "workarounds.h"
39 /**************************************************************************
43 **************************************************************************
46 /* Loopback mode names (see LOOPBACK_MODE()) */
47 const unsigned int efx_loopback_mode_max = LOOPBACK_MAX;
48 const char *const efx_loopback_mode_names[] = {
49 [LOOPBACK_NONE] = "NONE",
50 [LOOPBACK_DATA] = "DATAPATH",
51 [LOOPBACK_GMAC] = "GMAC",
52 [LOOPBACK_XGMII] = "XGMII",
53 [LOOPBACK_XGXS] = "XGXS",
54 [LOOPBACK_XAUI] = "XAUI",
55 [LOOPBACK_GMII] = "GMII",
56 [LOOPBACK_SGMII] = "SGMII",
57 [LOOPBACK_XGBR] = "XGBR",
58 [LOOPBACK_XFI] = "XFI",
59 [LOOPBACK_XAUI_FAR] = "XAUI_FAR",
60 [LOOPBACK_GMII_FAR] = "GMII_FAR",
61 [LOOPBACK_SGMII_FAR] = "SGMII_FAR",
62 [LOOPBACK_XFI_FAR] = "XFI_FAR",
63 [LOOPBACK_GPHY] = "GPHY",
64 [LOOPBACK_PHYXS] = "PHYXS",
65 [LOOPBACK_PCS] = "PCS",
66 [LOOPBACK_PMAPMD] = "PMA/PMD",
67 [LOOPBACK_XPORT] = "XPORT",
68 [LOOPBACK_XGMII_WS] = "XGMII_WS",
69 [LOOPBACK_XAUI_WS] = "XAUI_WS",
70 [LOOPBACK_XAUI_WS_FAR] = "XAUI_WS_FAR",
71 [LOOPBACK_XAUI_WS_NEAR] = "XAUI_WS_NEAR",
72 [LOOPBACK_GMII_WS] = "GMII_WS",
73 [LOOPBACK_XFI_WS] = "XFI_WS",
74 [LOOPBACK_XFI_WS_FAR] = "XFI_WS_FAR",
75 [LOOPBACK_PHYXS_WS] = "PHYXS_WS",
78 const unsigned int efx_reset_type_max = RESET_TYPE_MAX;
79 const char *const efx_reset_type_names[] = {
80 [RESET_TYPE_INVISIBLE] = "INVISIBLE",
81 [RESET_TYPE_ALL] = "ALL",
82 [RESET_TYPE_RECOVER_OR_ALL] = "RECOVER_OR_ALL",
83 [RESET_TYPE_WORLD] = "WORLD",
84 [RESET_TYPE_RECOVER_OR_DISABLE] = "RECOVER_OR_DISABLE",
85 [RESET_TYPE_DATAPATH] = "DATAPATH",
86 [RESET_TYPE_MC_BIST] = "MC_BIST",
87 [RESET_TYPE_DISABLE] = "DISABLE",
88 [RESET_TYPE_TX_WATCHDOG] = "TX_WATCHDOG",
89 [RESET_TYPE_INT_ERROR] = "INT_ERROR",
90 [RESET_TYPE_DMA_ERROR] = "DMA_ERROR",
91 [RESET_TYPE_TX_SKIP] = "TX_SKIP",
92 [RESET_TYPE_MC_FAILURE] = "MC_FAILURE",
93 [RESET_TYPE_MCDI_TIMEOUT] = "MCDI_TIMEOUT (FLR)",
96 /* UDP tunnel type names */
97 static const char *const efx_udp_tunnel_type_names[] = {
98 [TUNNEL_ENCAP_UDP_PORT_ENTRY_VXLAN] = "vxlan",
99 [TUNNEL_ENCAP_UDP_PORT_ENTRY_GENEVE] = "geneve",
102 void efx_get_udp_tunnel_type_name(u16 type, char *buf, size_t buflen)
104 if (type < ARRAY_SIZE(efx_udp_tunnel_type_names) &&
105 efx_udp_tunnel_type_names[type] != NULL)
106 snprintf(buf, buflen, "%s", efx_udp_tunnel_type_names[type]);
108 snprintf(buf, buflen, "type %d", type);
111 /* How often and how many times to poll for a reset while waiting for a
112 * BIST that another function started to complete.
114 #define BIST_WAIT_DELAY_MS 100
115 #define BIST_WAIT_DELAY_COUNT 100
117 /**************************************************************************
119 * Configurable values
121 *************************************************************************/
124 * Use separate channels for TX and RX events
126 * Set this to 1 to use separate channels for TX and RX. It allows us
127 * to control interrupt affinity separately for TX and RX.
129 * This is only used in MSI-X interrupt mode
131 bool efx_separate_tx_channels;
132 module_param(efx_separate_tx_channels, bool, 0444);
133 MODULE_PARM_DESC(efx_separate_tx_channels,
134 "Use separate channels for TX and RX");
136 /* This is the weight assigned to each of the (per-channel) virtual
139 static int napi_weight = 64;
141 /* This is the time (in jiffies) between invocations of the hardware
143 * On Falcon-based NICs, this will:
144 * - Check the on-board hardware monitor;
145 * - Poll the link state and reconfigure the hardware as necessary.
146 * On Siena-based NICs for power systems with EEH support, this will give EEH a
149 static unsigned int efx_monitor_interval = 1 * HZ;
151 /* Initial interrupt moderation settings. They can be modified after
152 * module load with ethtool.
154 * The default for RX should strike a balance between increasing the
155 * round-trip latency and reducing overhead.
157 static unsigned int rx_irq_mod_usec = 60;
159 /* Initial interrupt moderation settings. They can be modified after
160 * module load with ethtool.
162 * This default is chosen to ensure that a 10G link does not go idle
163 * while a TX queue is stopped after it has become full. A queue is
164 * restarted when it drops below half full. The time this takes (assuming
165 * worst case 3 descriptors per packet and 1024 descriptors) is
166 * 512 / 3 * 1.2 = 205 usec.
168 static unsigned int tx_irq_mod_usec = 150;
170 /* This is the first interrupt mode to try out of:
175 static unsigned int interrupt_mode;
177 /* This is the requested number of CPUs to use for Receive-Side Scaling (RSS),
178 * i.e. the number of CPUs among which we may distribute simultaneous
179 * interrupt handling.
181 * Cards without MSI-X will only target one CPU via legacy or MSI interrupt.
182 * The default (0) means to assign an interrupt to each core.
184 static unsigned int rss_cpus;
185 module_param(rss_cpus, uint, 0444);
186 MODULE_PARM_DESC(rss_cpus, "Number of CPUs to use for Receive-Side Scaling");
188 static bool phy_flash_cfg;
189 module_param(phy_flash_cfg, bool, 0644);
190 MODULE_PARM_DESC(phy_flash_cfg, "Set PHYs into reflash mode initially");
192 static unsigned irq_adapt_low_thresh = 8000;
193 module_param(irq_adapt_low_thresh, uint, 0644);
194 MODULE_PARM_DESC(irq_adapt_low_thresh,
195 "Threshold score for reducing IRQ moderation");
197 static unsigned irq_adapt_high_thresh = 16000;
198 module_param(irq_adapt_high_thresh, uint, 0644);
199 MODULE_PARM_DESC(irq_adapt_high_thresh,
200 "Threshold score for increasing IRQ moderation");
202 static unsigned debug = (NETIF_MSG_DRV | NETIF_MSG_PROBE |
203 NETIF_MSG_LINK | NETIF_MSG_IFDOWN |
204 NETIF_MSG_IFUP | NETIF_MSG_RX_ERR |
205 NETIF_MSG_TX_ERR | NETIF_MSG_HW);
206 module_param(debug, uint, 0);
207 MODULE_PARM_DESC(debug, "Bitmapped debugging message enable value");
209 /**************************************************************************
211 * Utility functions and prototypes
213 *************************************************************************/
215 static const struct efx_channel_type efx_default_channel_type;
216 static void efx_remove_port(struct efx_nic *efx);
217 static int efx_xdp_setup_prog(struct efx_nic *efx, struct bpf_prog *prog);
218 static int efx_xdp(struct net_device *dev, struct netdev_bpf *xdp);
219 static int efx_xdp_xmit(struct net_device *dev, int n, struct xdp_frame **xdpfs,
222 #define EFX_ASSERT_RESET_SERIALISED(efx) \
224 if ((efx->state == STATE_READY) || \
225 (efx->state == STATE_RECOVERY) || \
226 (efx->state == STATE_DISABLED)) \
230 /**************************************************************************
232 * Event queue processing
234 *************************************************************************/
236 /* Process channel's event queue
238 * This function is responsible for processing the event queue of a
239 * single channel. The caller must guarantee that this function will
240 * never be concurrently called more than once on the same channel,
241 * though different channels may be being processed concurrently.
243 static int efx_process_channel(struct efx_channel *channel, int budget)
245 struct efx_tx_queue *tx_queue;
246 struct list_head rx_list;
249 if (unlikely(!channel->enabled))
252 /* Prepare the batch receive list */
253 EFX_WARN_ON_PARANOID(channel->rx_list != NULL);
254 INIT_LIST_HEAD(&rx_list);
255 channel->rx_list = &rx_list;
257 efx_for_each_channel_tx_queue(tx_queue, channel) {
258 tx_queue->pkts_compl = 0;
259 tx_queue->bytes_compl = 0;
262 spent = efx_nic_process_eventq(channel, budget);
263 if (spent && efx_channel_has_rx_queue(channel)) {
264 struct efx_rx_queue *rx_queue =
265 efx_channel_get_rx_queue(channel);
267 efx_rx_flush_packet(channel);
268 efx_fast_push_rx_descriptors(rx_queue, true);
272 efx_for_each_channel_tx_queue(tx_queue, channel) {
273 if (tx_queue->bytes_compl) {
274 netdev_tx_completed_queue(tx_queue->core_txq,
275 tx_queue->pkts_compl, tx_queue->bytes_compl);
279 /* Receive any packets we queued up */
280 netif_receive_skb_list(channel->rx_list);
281 channel->rx_list = NULL;
288 * NAPI guarantees serialisation of polls of the same device, which
289 * provides the guarantee required by efx_process_channel().
291 static void efx_update_irq_mod(struct efx_nic *efx, struct efx_channel *channel)
293 int step = efx->irq_mod_step_us;
295 if (channel->irq_mod_score < irq_adapt_low_thresh) {
296 if (channel->irq_moderation_us > step) {
297 channel->irq_moderation_us -= step;
298 efx->type->push_irq_moderation(channel);
300 } else if (channel->irq_mod_score > irq_adapt_high_thresh) {
301 if (channel->irq_moderation_us <
302 efx->irq_rx_moderation_us) {
303 channel->irq_moderation_us += step;
304 efx->type->push_irq_moderation(channel);
308 channel->irq_count = 0;
309 channel->irq_mod_score = 0;
312 static int efx_poll(struct napi_struct *napi, int budget)
314 struct efx_channel *channel =
315 container_of(napi, struct efx_channel, napi_str);
316 struct efx_nic *efx = channel->efx;
319 netif_vdbg(efx, intr, efx->net_dev,
320 "channel %d NAPI poll executing on CPU %d\n",
321 channel->channel, raw_smp_processor_id());
323 spent = efx_process_channel(channel, budget);
327 if (spent < budget) {
328 if (efx_channel_has_rx_queue(channel) &&
329 efx->irq_rx_adaptive &&
330 unlikely(++channel->irq_count == 1000)) {
331 efx_update_irq_mod(efx, channel);
334 #ifdef CONFIG_RFS_ACCEL
335 /* Perhaps expire some ARFS filters */
336 mod_delayed_work(system_wq, &channel->filter_work, 0);
339 /* There is no race here; although napi_disable() will
340 * only wait for napi_complete(), this isn't a problem
341 * since efx_nic_eventq_read_ack() will have no effect if
342 * interrupts have already been disabled.
344 if (napi_complete_done(napi, spent))
345 efx_nic_eventq_read_ack(channel);
351 /* Create event queue
352 * Event queue memory allocations are done only once. If the channel
353 * is reset, the memory buffer will be reused; this guards against
354 * errors during channel reset and also simplifies interrupt handling.
356 int efx_probe_eventq(struct efx_channel *channel)
358 struct efx_nic *efx = channel->efx;
359 unsigned long entries;
361 netif_dbg(efx, probe, efx->net_dev,
362 "chan %d create event queue\n", channel->channel);
364 /* Build an event queue with room for one event per tx and rx buffer,
365 * plus some extra for link state events and MCDI completions. */
366 entries = roundup_pow_of_two(efx->rxq_entries + efx->txq_entries + 128);
367 EFX_WARN_ON_PARANOID(entries > EFX_MAX_EVQ_SIZE);
368 channel->eventq_mask = max(entries, EFX_MIN_EVQ_SIZE) - 1;
370 return efx_nic_probe_eventq(channel);
373 /* Prepare channel's event queue */
374 int efx_init_eventq(struct efx_channel *channel)
376 struct efx_nic *efx = channel->efx;
379 EFX_WARN_ON_PARANOID(channel->eventq_init);
381 netif_dbg(efx, drv, efx->net_dev,
382 "chan %d init event queue\n", channel->channel);
384 rc = efx_nic_init_eventq(channel);
386 efx->type->push_irq_moderation(channel);
387 channel->eventq_read_ptr = 0;
388 channel->eventq_init = true;
393 /* Enable event queue processing and NAPI */
394 void efx_start_eventq(struct efx_channel *channel)
396 netif_dbg(channel->efx, ifup, channel->efx->net_dev,
397 "chan %d start event queue\n", channel->channel);
399 /* Make sure the NAPI handler sees the enabled flag set */
400 channel->enabled = true;
403 napi_enable(&channel->napi_str);
404 efx_nic_eventq_read_ack(channel);
407 /* Disable event queue processing and NAPI */
408 void efx_stop_eventq(struct efx_channel *channel)
410 if (!channel->enabled)
413 napi_disable(&channel->napi_str);
414 channel->enabled = false;
417 void efx_fini_eventq(struct efx_channel *channel)
419 if (!channel->eventq_init)
422 netif_dbg(channel->efx, drv, channel->efx->net_dev,
423 "chan %d fini event queue\n", channel->channel);
425 efx_nic_fini_eventq(channel);
426 channel->eventq_init = false;
429 void efx_remove_eventq(struct efx_channel *channel)
431 netif_dbg(channel->efx, drv, channel->efx->net_dev,
432 "chan %d remove event queue\n", channel->channel);
434 efx_nic_remove_eventq(channel);
437 /**************************************************************************
441 *************************************************************************/
443 /* Allocate and initialise a channel structure. */
445 efx_alloc_channel(struct efx_nic *efx, int i, struct efx_channel *old_channel)
447 struct efx_channel *channel;
448 struct efx_rx_queue *rx_queue;
449 struct efx_tx_queue *tx_queue;
452 channel = kzalloc(sizeof(*channel), GFP_KERNEL);
457 channel->channel = i;
458 channel->type = &efx_default_channel_type;
460 for (j = 0; j < EFX_TXQ_TYPES; j++) {
461 tx_queue = &channel->tx_queue[j];
463 tx_queue->queue = i * EFX_TXQ_TYPES + j;
464 tx_queue->channel = channel;
467 #ifdef CONFIG_RFS_ACCEL
468 INIT_DELAYED_WORK(&channel->filter_work, efx_filter_rfs_expire);
471 rx_queue = &channel->rx_queue;
473 timer_setup(&rx_queue->slow_fill, efx_rx_slow_fill, 0);
478 /* Allocate and initialise a channel structure, copying parameters
479 * (but not resources) from an old channel structure.
481 struct efx_channel *efx_copy_channel(const struct efx_channel *old_channel)
483 struct efx_channel *channel;
484 struct efx_rx_queue *rx_queue;
485 struct efx_tx_queue *tx_queue;
488 channel = kmalloc(sizeof(*channel), GFP_KERNEL);
492 *channel = *old_channel;
494 channel->napi_dev = NULL;
495 INIT_HLIST_NODE(&channel->napi_str.napi_hash_node);
496 channel->napi_str.napi_id = 0;
497 channel->napi_str.state = 0;
498 memset(&channel->eventq, 0, sizeof(channel->eventq));
500 for (j = 0; j < EFX_TXQ_TYPES; j++) {
501 tx_queue = &channel->tx_queue[j];
502 if (tx_queue->channel)
503 tx_queue->channel = channel;
504 tx_queue->buffer = NULL;
505 memset(&tx_queue->txd, 0, sizeof(tx_queue->txd));
508 rx_queue = &channel->rx_queue;
509 rx_queue->buffer = NULL;
510 memset(&rx_queue->rxd, 0, sizeof(rx_queue->rxd));
511 timer_setup(&rx_queue->slow_fill, efx_rx_slow_fill, 0);
512 #ifdef CONFIG_RFS_ACCEL
513 INIT_DELAYED_WORK(&channel->filter_work, efx_filter_rfs_expire);
519 static int efx_probe_channel(struct efx_channel *channel)
521 struct efx_tx_queue *tx_queue;
522 struct efx_rx_queue *rx_queue;
525 netif_dbg(channel->efx, probe, channel->efx->net_dev,
526 "creating channel %d\n", channel->channel);
528 rc = channel->type->pre_probe(channel);
532 rc = efx_probe_eventq(channel);
536 efx_for_each_channel_tx_queue(tx_queue, channel) {
537 rc = efx_probe_tx_queue(tx_queue);
542 efx_for_each_channel_rx_queue(rx_queue, channel) {
543 rc = efx_probe_rx_queue(rx_queue);
548 channel->rx_list = NULL;
553 efx_remove_channel(channel);
557 void efx_get_channel_name(struct efx_channel *channel, char *buf, size_t len)
559 struct efx_nic *efx = channel->efx;
563 number = channel->channel;
565 if (number >= efx->xdp_channel_offset &&
566 !WARN_ON_ONCE(!efx->n_xdp_channels)) {
568 number -= efx->xdp_channel_offset;
569 } else if (efx->tx_channel_offset == 0) {
571 } else if (number < efx->tx_channel_offset) {
575 number -= efx->tx_channel_offset;
577 snprintf(buf, len, "%s%s-%d", efx->name, type, number);
580 void efx_set_channel_names(struct efx_nic *efx)
582 struct efx_channel *channel;
584 efx_for_each_channel(channel, efx)
585 channel->type->get_name(channel,
586 efx->msi_context[channel->channel].name,
587 sizeof(efx->msi_context[0].name));
590 int efx_probe_channels(struct efx_nic *efx)
592 struct efx_channel *channel;
595 /* Restart special buffer allocation */
596 efx->next_buffer_table = 0;
598 /* Probe channels in reverse, so that any 'extra' channels
599 * use the start of the buffer table. This allows the traffic
600 * channels to be resized without moving them or wasting the
601 * entries before them.
603 efx_for_each_channel_rev(channel, efx) {
604 rc = efx_probe_channel(channel);
606 netif_err(efx, probe, efx->net_dev,
607 "failed to create channel %d\n",
612 efx_set_channel_names(efx);
617 efx_remove_channels(efx);
621 /* Channels are shutdown and reinitialised whilst the NIC is running
622 * to propagate configuration changes (mtu, checksum offload), or
623 * to clear hardware error conditions
625 static void efx_start_datapath(struct efx_nic *efx)
627 netdev_features_t old_features = efx->net_dev->features;
628 bool old_rx_scatter = efx->rx_scatter;
629 struct efx_tx_queue *tx_queue;
630 struct efx_rx_queue *rx_queue;
631 struct efx_channel *channel;
634 /* Calculate the rx buffer allocation parameters required to
635 * support the current MTU, including padding for header
636 * alignment and overruns.
638 efx->rx_dma_len = (efx->rx_prefix_size +
639 EFX_MAX_FRAME_LEN(efx->net_dev->mtu) +
640 efx->type->rx_buffer_padding);
641 rx_buf_len = (sizeof(struct efx_rx_page_state) + XDP_PACKET_HEADROOM +
642 efx->rx_ip_align + efx->rx_dma_len);
643 if (rx_buf_len <= PAGE_SIZE) {
644 efx->rx_scatter = efx->type->always_rx_scatter;
645 efx->rx_buffer_order = 0;
646 } else if (efx->type->can_rx_scatter) {
647 BUILD_BUG_ON(EFX_RX_USR_BUF_SIZE % L1_CACHE_BYTES);
648 BUILD_BUG_ON(sizeof(struct efx_rx_page_state) +
649 2 * ALIGN(NET_IP_ALIGN + EFX_RX_USR_BUF_SIZE,
650 EFX_RX_BUF_ALIGNMENT) >
652 efx->rx_scatter = true;
653 efx->rx_dma_len = EFX_RX_USR_BUF_SIZE;
654 efx->rx_buffer_order = 0;
656 efx->rx_scatter = false;
657 efx->rx_buffer_order = get_order(rx_buf_len);
660 efx_rx_config_page_split(efx);
661 if (efx->rx_buffer_order)
662 netif_dbg(efx, drv, efx->net_dev,
663 "RX buf len=%u; page order=%u batch=%u\n",
664 efx->rx_dma_len, efx->rx_buffer_order,
665 efx->rx_pages_per_batch);
667 netif_dbg(efx, drv, efx->net_dev,
668 "RX buf len=%u step=%u bpp=%u; page batch=%u\n",
669 efx->rx_dma_len, efx->rx_page_buf_step,
670 efx->rx_bufs_per_page, efx->rx_pages_per_batch);
672 /* Restore previously fixed features in hw_features and remove
673 * features which are fixed now
675 efx->net_dev->hw_features |= efx->net_dev->features;
676 efx->net_dev->hw_features &= ~efx->fixed_features;
677 efx->net_dev->features |= efx->fixed_features;
678 if (efx->net_dev->features != old_features)
679 netdev_features_change(efx->net_dev);
681 /* RX filters may also have scatter-enabled flags */
682 if (efx->rx_scatter != old_rx_scatter)
683 efx->type->filter_update_rx_scatter(efx);
685 /* We must keep at least one descriptor in a TX ring empty.
686 * We could avoid this when the queue size does not exactly
687 * match the hardware ring size, but it's not that important.
688 * Therefore we stop the queue when one more skb might fill
689 * the ring completely. We wake it when half way back to
692 efx->txq_stop_thresh = efx->txq_entries - efx_tx_max_skb_descs(efx);
693 efx->txq_wake_thresh = efx->txq_stop_thresh / 2;
695 /* Initialise the channels */
696 efx_for_each_channel(channel, efx) {
697 efx_for_each_channel_tx_queue(tx_queue, channel) {
698 efx_init_tx_queue(tx_queue);
699 atomic_inc(&efx->active_queues);
702 efx_for_each_channel_rx_queue(rx_queue, channel) {
703 efx_init_rx_queue(rx_queue);
704 atomic_inc(&efx->active_queues);
705 efx_stop_eventq(channel);
706 efx_fast_push_rx_descriptors(rx_queue, false);
707 efx_start_eventq(channel);
710 WARN_ON(channel->rx_pkt_n_frags);
713 efx_ptp_start_datapath(efx);
715 if (netif_device_present(efx->net_dev))
716 netif_tx_wake_all_queues(efx->net_dev);
719 static void efx_stop_datapath(struct efx_nic *efx)
721 struct efx_channel *channel;
722 struct efx_tx_queue *tx_queue;
723 struct efx_rx_queue *rx_queue;
726 EFX_ASSERT_RESET_SERIALISED(efx);
727 BUG_ON(efx->port_enabled);
729 efx_ptp_stop_datapath(efx);
732 efx_for_each_channel(channel, efx) {
733 efx_for_each_channel_rx_queue(rx_queue, channel)
734 rx_queue->refill_enabled = false;
737 efx_for_each_channel(channel, efx) {
738 /* RX packet processing is pipelined, so wait for the
739 * NAPI handler to complete. At least event queue 0
740 * might be kept active by non-data events, so don't
741 * use napi_synchronize() but actually disable NAPI
744 if (efx_channel_has_rx_queue(channel)) {
745 efx_stop_eventq(channel);
746 efx_start_eventq(channel);
750 rc = efx->type->fini_dmaq(efx);
752 netif_err(efx, drv, efx->net_dev, "failed to flush queues\n");
754 netif_dbg(efx, drv, efx->net_dev,
755 "successfully flushed all queues\n");
758 efx_for_each_channel(channel, efx) {
759 efx_for_each_channel_rx_queue(rx_queue, channel)
760 efx_fini_rx_queue(rx_queue);
761 efx_for_each_possible_channel_tx_queue(tx_queue, channel)
762 efx_fini_tx_queue(tx_queue);
764 efx->xdp_rxq_info_failed = false;
767 void efx_remove_channel(struct efx_channel *channel)
769 struct efx_tx_queue *tx_queue;
770 struct efx_rx_queue *rx_queue;
772 netif_dbg(channel->efx, drv, channel->efx->net_dev,
773 "destroy chan %d\n", channel->channel);
775 efx_for_each_channel_rx_queue(rx_queue, channel)
776 efx_remove_rx_queue(rx_queue);
777 efx_for_each_possible_channel_tx_queue(tx_queue, channel)
778 efx_remove_tx_queue(tx_queue);
779 efx_remove_eventq(channel);
780 channel->type->post_remove(channel);
783 void efx_remove_channels(struct efx_nic *efx)
785 struct efx_channel *channel;
787 efx_for_each_channel(channel, efx)
788 efx_remove_channel(channel);
790 kfree(efx->xdp_tx_queues);
793 int efx_realloc_channels(struct efx_nic *efx, u32 rxq_entries, u32 txq_entries)
795 struct efx_channel *other_channel[EFX_MAX_CHANNELS], *channel;
796 u32 old_rxq_entries, old_txq_entries;
797 unsigned i, next_buffer_table = 0;
800 rc = efx_check_disabled(efx);
804 /* Not all channels should be reallocated. We must avoid
805 * reallocating their buffer table entries.
807 efx_for_each_channel(channel, efx) {
808 struct efx_rx_queue *rx_queue;
809 struct efx_tx_queue *tx_queue;
811 if (channel->type->copy)
813 next_buffer_table = max(next_buffer_table,
814 channel->eventq.index +
815 channel->eventq.entries);
816 efx_for_each_channel_rx_queue(rx_queue, channel)
817 next_buffer_table = max(next_buffer_table,
818 rx_queue->rxd.index +
819 rx_queue->rxd.entries);
820 efx_for_each_channel_tx_queue(tx_queue, channel)
821 next_buffer_table = max(next_buffer_table,
822 tx_queue->txd.index +
823 tx_queue->txd.entries);
826 efx_device_detach_sync(efx);
828 efx_soft_disable_interrupts(efx);
830 /* Clone channels (where possible) */
831 memset(other_channel, 0, sizeof(other_channel));
832 for (i = 0; i < efx->n_channels; i++) {
833 channel = efx->channel[i];
834 if (channel->type->copy)
835 channel = channel->type->copy(channel);
840 other_channel[i] = channel;
843 /* Swap entry counts and channel pointers */
844 old_rxq_entries = efx->rxq_entries;
845 old_txq_entries = efx->txq_entries;
846 efx->rxq_entries = rxq_entries;
847 efx->txq_entries = txq_entries;
848 for (i = 0; i < efx->n_channels; i++) {
849 channel = efx->channel[i];
850 efx->channel[i] = other_channel[i];
851 other_channel[i] = channel;
854 /* Restart buffer table allocation */
855 efx->next_buffer_table = next_buffer_table;
857 for (i = 0; i < efx->n_channels; i++) {
858 channel = efx->channel[i];
859 if (!channel->type->copy)
861 rc = efx_probe_channel(channel);
864 efx_init_napi_channel(efx->channel[i]);
868 /* Destroy unused channel structures */
869 for (i = 0; i < efx->n_channels; i++) {
870 channel = other_channel[i];
871 if (channel && channel->type->copy) {
872 efx_fini_napi_channel(channel);
873 efx_remove_channel(channel);
878 rc2 = efx_soft_enable_interrupts(efx);
881 netif_err(efx, drv, efx->net_dev,
882 "unable to restart interrupts on channel reallocation\n");
883 efx_schedule_reset(efx, RESET_TYPE_DISABLE);
886 efx_device_attach_if_not_resetting(efx);
892 efx->rxq_entries = old_rxq_entries;
893 efx->txq_entries = old_txq_entries;
894 for (i = 0; i < efx->n_channels; i++) {
895 channel = efx->channel[i];
896 efx->channel[i] = other_channel[i];
897 other_channel[i] = channel;
902 void efx_schedule_slow_fill(struct efx_rx_queue *rx_queue)
904 mod_timer(&rx_queue->slow_fill, jiffies + msecs_to_jiffies(10));
907 bool efx_default_channel_want_txqs(struct efx_channel *channel)
909 return channel->channel - channel->efx->tx_channel_offset <
910 channel->efx->n_tx_channels;
913 static const struct efx_channel_type efx_default_channel_type = {
914 .pre_probe = efx_channel_dummy_op_int,
915 .post_remove = efx_channel_dummy_op_void,
916 .get_name = efx_get_channel_name,
917 .copy = efx_copy_channel,
918 .want_txqs = efx_default_channel_want_txqs,
919 .keep_eventq = false,
923 int efx_channel_dummy_op_int(struct efx_channel *channel)
928 void efx_channel_dummy_op_void(struct efx_channel *channel)
932 /**************************************************************************
936 **************************************************************************/
938 void efx_link_set_advertising(struct efx_nic *efx,
939 const unsigned long *advertising)
941 memcpy(efx->link_advertising, advertising,
942 sizeof(__ETHTOOL_DECLARE_LINK_MODE_MASK()));
944 efx->link_advertising[0] |= ADVERTISED_Autoneg;
945 if (advertising[0] & ADVERTISED_Pause)
946 efx->wanted_fc |= (EFX_FC_TX | EFX_FC_RX);
948 efx->wanted_fc &= ~(EFX_FC_TX | EFX_FC_RX);
949 if (advertising[0] & ADVERTISED_Asym_Pause)
950 efx->wanted_fc ^= EFX_FC_TX;
953 /* Equivalent to efx_link_set_advertising with all-zeroes, except does not
954 * force the Autoneg bit on.
956 void efx_link_clear_advertising(struct efx_nic *efx)
958 bitmap_zero(efx->link_advertising, __ETHTOOL_LINK_MODE_MASK_NBITS);
959 efx->wanted_fc &= ~(EFX_FC_TX | EFX_FC_RX);
962 void efx_link_set_wanted_fc(struct efx_nic *efx, u8 wanted_fc)
964 efx->wanted_fc = wanted_fc;
965 if (efx->link_advertising[0]) {
966 if (wanted_fc & EFX_FC_RX)
967 efx->link_advertising[0] |= (ADVERTISED_Pause |
968 ADVERTISED_Asym_Pause);
970 efx->link_advertising[0] &= ~(ADVERTISED_Pause |
971 ADVERTISED_Asym_Pause);
972 if (wanted_fc & EFX_FC_TX)
973 efx->link_advertising[0] ^= ADVERTISED_Asym_Pause;
977 static void efx_fini_port(struct efx_nic *efx);
979 /* Push loopback/power/transmit disable settings to the PHY, and reconfigure
980 * the MAC appropriately. All other PHY configuration changes are pushed
981 * through phy_op->set_settings(), and pushed asynchronously to the MAC
982 * through efx_monitor().
984 * Callers must hold the mac_lock
986 int __efx_reconfigure_port(struct efx_nic *efx)
988 enum efx_phy_mode phy_mode;
991 WARN_ON(!mutex_is_locked(&efx->mac_lock));
993 /* Disable PHY transmit in mac level loopbacks */
994 phy_mode = efx->phy_mode;
995 if (LOOPBACK_INTERNAL(efx))
996 efx->phy_mode |= PHY_MODE_TX_DISABLED;
998 efx->phy_mode &= ~PHY_MODE_TX_DISABLED;
1000 rc = efx->type->reconfigure_port(efx);
1003 efx->phy_mode = phy_mode;
1008 /* Reinitialise the MAC to pick up new PHY settings, even if the port is
1010 int efx_reconfigure_port(struct efx_nic *efx)
1014 EFX_ASSERT_RESET_SERIALISED(efx);
1016 mutex_lock(&efx->mac_lock);
1017 rc = __efx_reconfigure_port(efx);
1018 mutex_unlock(&efx->mac_lock);
1023 /* Asynchronous work item for changing MAC promiscuity and multicast
1024 * hash. Avoid a drain/rx_ingress enable by reconfiguring the current
1026 static void efx_mac_work(struct work_struct *data)
1028 struct efx_nic *efx = container_of(data, struct efx_nic, mac_work);
1030 mutex_lock(&efx->mac_lock);
1031 if (efx->port_enabled)
1032 efx_mac_reconfigure(efx);
1033 mutex_unlock(&efx->mac_lock);
1036 static int efx_probe_port(struct efx_nic *efx)
1040 netif_dbg(efx, probe, efx->net_dev, "create port\n");
1043 efx->phy_mode = PHY_MODE_SPECIAL;
1045 /* Connect up MAC/PHY operations table */
1046 rc = efx->type->probe_port(efx);
1050 /* Initialise MAC address to permanent address */
1051 ether_addr_copy(efx->net_dev->dev_addr, efx->net_dev->perm_addr);
1056 static int efx_init_port(struct efx_nic *efx)
1060 netif_dbg(efx, drv, efx->net_dev, "init port\n");
1062 mutex_lock(&efx->mac_lock);
1064 rc = efx->phy_op->init(efx);
1068 efx->port_initialized = true;
1070 /* Reconfigure the MAC before creating dma queues (required for
1071 * Falcon/A1 where RX_INGR_EN/TX_DRAIN_EN isn't supported) */
1072 efx_mac_reconfigure(efx);
1074 /* Ensure the PHY advertises the correct flow control settings */
1075 rc = efx->phy_op->reconfigure(efx);
1076 if (rc && rc != -EPERM)
1079 mutex_unlock(&efx->mac_lock);
1083 efx->phy_op->fini(efx);
1085 mutex_unlock(&efx->mac_lock);
1089 static void efx_start_port(struct efx_nic *efx)
1091 netif_dbg(efx, ifup, efx->net_dev, "start port\n");
1092 BUG_ON(efx->port_enabled);
1094 mutex_lock(&efx->mac_lock);
1095 efx->port_enabled = true;
1097 /* Ensure MAC ingress/egress is enabled */
1098 efx_mac_reconfigure(efx);
1100 mutex_unlock(&efx->mac_lock);
1103 /* Cancel work for MAC reconfiguration, periodic hardware monitoring
1104 * and the async self-test, wait for them to finish and prevent them
1105 * being scheduled again. This doesn't cover online resets, which
1106 * should only be cancelled when removing the device.
1108 static void efx_stop_port(struct efx_nic *efx)
1110 netif_dbg(efx, ifdown, efx->net_dev, "stop port\n");
1112 EFX_ASSERT_RESET_SERIALISED(efx);
1114 mutex_lock(&efx->mac_lock);
1115 efx->port_enabled = false;
1116 mutex_unlock(&efx->mac_lock);
1118 /* Serialise against efx_set_multicast_list() */
1119 netif_addr_lock_bh(efx->net_dev);
1120 netif_addr_unlock_bh(efx->net_dev);
1122 cancel_delayed_work_sync(&efx->monitor_work);
1123 efx_selftest_async_cancel(efx);
1124 cancel_work_sync(&efx->mac_work);
1127 static void efx_fini_port(struct efx_nic *efx)
1129 netif_dbg(efx, drv, efx->net_dev, "shut down port\n");
1131 if (!efx->port_initialized)
1134 efx->phy_op->fini(efx);
1135 efx->port_initialized = false;
1137 efx->link_state.up = false;
1138 efx_link_status_changed(efx);
1141 static void efx_remove_port(struct efx_nic *efx)
1143 netif_dbg(efx, drv, efx->net_dev, "destroying port\n");
1145 efx->type->remove_port(efx);
1148 /**************************************************************************
1152 **************************************************************************/
1154 static LIST_HEAD(efx_primary_list);
1155 static LIST_HEAD(efx_unassociated_list);
1157 static bool efx_same_controller(struct efx_nic *left, struct efx_nic *right)
1159 return left->type == right->type &&
1160 left->vpd_sn && right->vpd_sn &&
1161 !strcmp(left->vpd_sn, right->vpd_sn);
1164 static void efx_associate(struct efx_nic *efx)
1166 struct efx_nic *other, *next;
1168 if (efx->primary == efx) {
1169 /* Adding primary function; look for secondaries */
1171 netif_dbg(efx, probe, efx->net_dev, "adding to primary list\n");
1172 list_add_tail(&efx->node, &efx_primary_list);
1174 list_for_each_entry_safe(other, next, &efx_unassociated_list,
1176 if (efx_same_controller(efx, other)) {
1177 list_del(&other->node);
1178 netif_dbg(other, probe, other->net_dev,
1179 "moving to secondary list of %s %s\n",
1180 pci_name(efx->pci_dev),
1181 efx->net_dev->name);
1182 list_add_tail(&other->node,
1183 &efx->secondary_list);
1184 other->primary = efx;
1188 /* Adding secondary function; look for primary */
1190 list_for_each_entry(other, &efx_primary_list, node) {
1191 if (efx_same_controller(efx, other)) {
1192 netif_dbg(efx, probe, efx->net_dev,
1193 "adding to secondary list of %s %s\n",
1194 pci_name(other->pci_dev),
1195 other->net_dev->name);
1196 list_add_tail(&efx->node,
1197 &other->secondary_list);
1198 efx->primary = other;
1203 netif_dbg(efx, probe, efx->net_dev,
1204 "adding to unassociated list\n");
1205 list_add_tail(&efx->node, &efx_unassociated_list);
1209 static void efx_dissociate(struct efx_nic *efx)
1211 struct efx_nic *other, *next;
1213 list_del(&efx->node);
1214 efx->primary = NULL;
1216 list_for_each_entry_safe(other, next, &efx->secondary_list, node) {
1217 list_del(&other->node);
1218 netif_dbg(other, probe, other->net_dev,
1219 "moving to unassociated list\n");
1220 list_add_tail(&other->node, &efx_unassociated_list);
1221 other->primary = NULL;
1225 /* This configures the PCI device to enable I/O and DMA. */
1226 int efx_init_io(struct efx_nic *efx, int bar, dma_addr_t dma_mask,
1227 unsigned int mem_map_size)
1229 struct pci_dev *pci_dev = efx->pci_dev;
1232 netif_dbg(efx, probe, efx->net_dev, "initialising I/O\n");
1234 rc = pci_enable_device(pci_dev);
1236 netif_err(efx, probe, efx->net_dev,
1237 "failed to enable PCI device\n");
1241 pci_set_master(pci_dev);
1243 /* Set the PCI DMA mask. Try all possibilities from our genuine mask
1244 * down to 32 bits, because some architectures will allow 40 bit
1245 * masks event though they reject 46 bit masks.
1247 while (dma_mask > 0x7fffffffUL) {
1248 rc = dma_set_mask_and_coherent(&pci_dev->dev, dma_mask);
1254 netif_err(efx, probe, efx->net_dev,
1255 "could not find a suitable DMA mask\n");
1258 netif_dbg(efx, probe, efx->net_dev,
1259 "using DMA mask %llx\n", (unsigned long long) dma_mask);
1261 efx->membase_phys = pci_resource_start(efx->pci_dev, bar);
1262 rc = pci_request_region(pci_dev, bar, "sfc");
1264 netif_err(efx, probe, efx->net_dev,
1265 "request for memory BAR failed\n");
1269 efx->membase = ioremap_nocache(efx->membase_phys, mem_map_size);
1270 if (!efx->membase) {
1271 netif_err(efx, probe, efx->net_dev,
1272 "could not map memory BAR at %llx+%x\n",
1273 (unsigned long long)efx->membase_phys, mem_map_size);
1277 netif_dbg(efx, probe, efx->net_dev,
1278 "memory BAR at %llx+%x (virtual %p)\n",
1279 (unsigned long long)efx->membase_phys, mem_map_size,
1285 pci_release_region(efx->pci_dev, bar);
1287 efx->membase_phys = 0;
1289 pci_disable_device(efx->pci_dev);
1294 void efx_fini_io(struct efx_nic *efx, int bar)
1296 netif_dbg(efx, drv, efx->net_dev, "shutting down I/O\n");
1299 iounmap(efx->membase);
1300 efx->membase = NULL;
1303 if (efx->membase_phys) {
1304 pci_release_region(efx->pci_dev, bar);
1305 efx->membase_phys = 0;
1308 /* Don't disable bus-mastering if VFs are assigned */
1309 if (!pci_vfs_assigned(efx->pci_dev))
1310 pci_disable_device(efx->pci_dev);
1313 void efx_set_default_rx_indir_table(struct efx_nic *efx,
1314 struct efx_rss_context *ctx)
1318 for (i = 0; i < ARRAY_SIZE(ctx->rx_indir_table); i++)
1319 ctx->rx_indir_table[i] =
1320 ethtool_rxfh_indir_default(i, efx->rss_spread);
1323 static unsigned int efx_wanted_parallelism(struct efx_nic *efx)
1325 cpumask_var_t thread_mask;
1332 if (unlikely(!zalloc_cpumask_var(&thread_mask, GFP_KERNEL))) {
1333 netif_warn(efx, probe, efx->net_dev,
1334 "RSS disabled due to allocation failure\n");
1339 for_each_online_cpu(cpu) {
1340 if (!cpumask_test_cpu(cpu, thread_mask)) {
1342 cpumask_or(thread_mask, thread_mask,
1343 topology_sibling_cpumask(cpu));
1347 free_cpumask_var(thread_mask);
1350 if (count > EFX_MAX_RX_QUEUES) {
1351 netif_cond_dbg(efx, probe, efx->net_dev, !rss_cpus, warn,
1352 "Reducing number of rx queues from %u to %u.\n",
1353 count, EFX_MAX_RX_QUEUES);
1354 count = EFX_MAX_RX_QUEUES;
1357 /* If RSS is requested for the PF *and* VFs then we can't write RSS
1358 * table entries that are inaccessible to VFs
1360 #ifdef CONFIG_SFC_SRIOV
1361 if (efx->type->sriov_wanted) {
1362 if (efx->type->sriov_wanted(efx) && efx_vf_size(efx) > 1 &&
1363 count > efx_vf_size(efx)) {
1364 netif_warn(efx, probe, efx->net_dev,
1365 "Reducing number of RSS channels from %u to %u for "
1366 "VF support. Increase vf-msix-limit to use more "
1367 "channels on the PF.\n",
1368 count, efx_vf_size(efx));
1369 count = efx_vf_size(efx);
1377 static int efx_allocate_msix_channels(struct efx_nic *efx,
1378 unsigned int max_channels,
1379 unsigned int extra_channels,
1380 unsigned int parallelism)
1382 unsigned int n_channels = parallelism;
1387 if (efx_separate_tx_channels)
1389 n_channels += extra_channels;
1391 /* To allow XDP transmit to happen from arbitrary NAPI contexts
1392 * we allocate a TX queue per CPU. We share event queues across
1393 * multiple tx queues, assuming tx and ev queues are both
1397 n_xdp_tx = num_possible_cpus();
1398 n_xdp_ev = DIV_ROUND_UP(n_xdp_tx, EFX_TXQ_TYPES);
1400 vec_count = pci_msix_vec_count(efx->pci_dev);
1404 max_channels = min_t(unsigned int, vec_count, max_channels);
1407 * We need a channel per event queue, plus a VI per tx queue.
1408 * This may be more pessimistic than it needs to be.
1410 if (n_channels + n_xdp_ev > max_channels) {
1411 netif_err(efx, drv, efx->net_dev,
1412 "Insufficient resources for %d XDP event queues (%d other channels, max %d)\n",
1413 n_xdp_ev, n_channels, max_channels);
1414 efx->n_xdp_channels = 0;
1415 efx->xdp_tx_per_channel = 0;
1416 efx->xdp_tx_queue_count = 0;
1418 efx->n_xdp_channels = n_xdp_ev;
1419 efx->xdp_tx_per_channel = EFX_TXQ_TYPES;
1420 efx->xdp_tx_queue_count = n_xdp_tx;
1421 n_channels += n_xdp_ev;
1422 netif_dbg(efx, drv, efx->net_dev,
1423 "Allocating %d TX and %d event queues for XDP\n",
1424 n_xdp_tx, n_xdp_ev);
1427 if (vec_count < n_channels) {
1428 netif_err(efx, drv, efx->net_dev,
1429 "WARNING: Insufficient MSI-X vectors available (%d < %u).\n",
1430 vec_count, n_channels);
1431 netif_err(efx, drv, efx->net_dev,
1432 "WARNING: Performance may be reduced.\n");
1433 n_channels = vec_count;
1436 n_channels = min(n_channels, max_channels);
1438 efx->n_channels = n_channels;
1440 /* Ignore XDP tx channels when creating rx channels. */
1441 n_channels -= efx->n_xdp_channels;
1443 if (efx_separate_tx_channels) {
1444 efx->n_tx_channels =
1445 min(max(n_channels / 2, 1U),
1446 efx->max_tx_channels);
1447 efx->tx_channel_offset =
1448 n_channels - efx->n_tx_channels;
1449 efx->n_rx_channels =
1451 efx->n_tx_channels, 1U);
1453 efx->n_tx_channels = min(n_channels, efx->max_tx_channels);
1454 efx->tx_channel_offset = 0;
1455 efx->n_rx_channels = n_channels;
1458 efx->n_rx_channels = min(efx->n_rx_channels, parallelism);
1459 efx->n_tx_channels = min(efx->n_tx_channels, parallelism);
1461 efx->xdp_channel_offset = n_channels;
1463 netif_dbg(efx, drv, efx->net_dev,
1464 "Allocating %u RX channels\n",
1465 efx->n_rx_channels);
1467 return efx->n_channels;
1470 /* Probe the number and type of interrupts we are able to obtain, and
1471 * the resulting numbers of channels and RX queues.
1473 int efx_probe_interrupts(struct efx_nic *efx)
1475 unsigned int extra_channels = 0;
1476 unsigned int rss_spread;
1480 for (i = 0; i < EFX_MAX_EXTRA_CHANNELS; i++)
1481 if (efx->extra_channel_type[i])
1484 if (efx->interrupt_mode == EFX_INT_MODE_MSIX) {
1485 unsigned int parallelism = efx_wanted_parallelism(efx);
1486 struct msix_entry xentries[EFX_MAX_CHANNELS];
1487 unsigned int n_channels;
1489 rc = efx_allocate_msix_channels(efx, efx->max_channels,
1490 extra_channels, parallelism);
1493 for (i = 0; i < n_channels; i++)
1494 xentries[i].entry = i;
1495 rc = pci_enable_msix_range(efx->pci_dev, xentries, 1,
1499 /* Fall back to single channel MSI */
1500 netif_err(efx, drv, efx->net_dev,
1501 "could not enable MSI-X\n");
1502 if (efx->type->min_interrupt_mode >= EFX_INT_MODE_MSI)
1503 efx->interrupt_mode = EFX_INT_MODE_MSI;
1506 } else if (rc < n_channels) {
1507 netif_err(efx, drv, efx->net_dev,
1508 "WARNING: Insufficient MSI-X vectors"
1509 " available (%d < %u).\n", rc, n_channels);
1510 netif_err(efx, drv, efx->net_dev,
1511 "WARNING: Performance may be reduced.\n");
1516 for (i = 0; i < efx->n_channels; i++)
1517 efx_get_channel(efx, i)->irq =
1522 /* Try single interrupt MSI */
1523 if (efx->interrupt_mode == EFX_INT_MODE_MSI) {
1524 efx->n_channels = 1;
1525 efx->n_rx_channels = 1;
1526 efx->n_tx_channels = 1;
1527 efx->n_xdp_channels = 0;
1528 efx->xdp_channel_offset = efx->n_channels;
1529 rc = pci_enable_msi(efx->pci_dev);
1531 efx_get_channel(efx, 0)->irq = efx->pci_dev->irq;
1533 netif_err(efx, drv, efx->net_dev,
1534 "could not enable MSI\n");
1535 if (efx->type->min_interrupt_mode >= EFX_INT_MODE_LEGACY)
1536 efx->interrupt_mode = EFX_INT_MODE_LEGACY;
1542 /* Assume legacy interrupts */
1543 if (efx->interrupt_mode == EFX_INT_MODE_LEGACY) {
1544 efx->n_channels = 1 + (efx_separate_tx_channels ? 1 : 0);
1545 efx->n_rx_channels = 1;
1546 efx->n_tx_channels = 1;
1547 efx->n_xdp_channels = 0;
1548 efx->xdp_channel_offset = efx->n_channels;
1549 efx->legacy_irq = efx->pci_dev->irq;
1552 /* Assign extra channels if possible, before XDP channels */
1553 efx->n_extra_tx_channels = 0;
1554 j = efx->xdp_channel_offset;
1555 for (i = 0; i < EFX_MAX_EXTRA_CHANNELS; i++) {
1556 if (!efx->extra_channel_type[i])
1558 if (j <= efx->tx_channel_offset + efx->n_tx_channels) {
1559 efx->extra_channel_type[i]->handle_no_channel(efx);
1562 efx_get_channel(efx, j)->type =
1563 efx->extra_channel_type[i];
1564 if (efx_channel_has_tx_queues(efx_get_channel(efx, j)))
1565 efx->n_extra_tx_channels++;
1569 rss_spread = efx->n_rx_channels;
1570 /* RSS might be usable on VFs even if it is disabled on the PF */
1571 #ifdef CONFIG_SFC_SRIOV
1572 if (efx->type->sriov_wanted) {
1573 efx->rss_spread = ((rss_spread > 1 ||
1574 !efx->type->sriov_wanted(efx)) ?
1575 rss_spread : efx_vf_size(efx));
1579 efx->rss_spread = rss_spread;
1584 #if defined(CONFIG_SMP)
1585 void efx_set_interrupt_affinity(struct efx_nic *efx)
1587 struct efx_channel *channel;
1590 efx_for_each_channel(channel, efx) {
1591 cpu = cpumask_local_spread(channel->channel,
1592 pcibus_to_node(efx->pci_dev->bus));
1593 irq_set_affinity_hint(channel->irq, cpumask_of(cpu));
1597 void efx_clear_interrupt_affinity(struct efx_nic *efx)
1599 struct efx_channel *channel;
1601 efx_for_each_channel(channel, efx)
1602 irq_set_affinity_hint(channel->irq, NULL);
1605 void efx_set_interrupt_affinity(struct efx_nic *efx __attribute__ ((unused)))
1609 void efx_clear_interrupt_affinity(struct efx_nic *efx __attribute__ ((unused)))
1612 #endif /* CONFIG_SMP */
1614 int efx_soft_enable_interrupts(struct efx_nic *efx)
1616 struct efx_channel *channel, *end_channel;
1619 BUG_ON(efx->state == STATE_DISABLED);
1621 efx->irq_soft_enabled = true;
1624 efx_for_each_channel(channel, efx) {
1625 if (!channel->type->keep_eventq) {
1626 rc = efx_init_eventq(channel);
1630 efx_start_eventq(channel);
1633 efx_mcdi_mode_event(efx);
1637 end_channel = channel;
1638 efx_for_each_channel(channel, efx) {
1639 if (channel == end_channel)
1641 efx_stop_eventq(channel);
1642 if (!channel->type->keep_eventq)
1643 efx_fini_eventq(channel);
1649 void efx_soft_disable_interrupts(struct efx_nic *efx)
1651 struct efx_channel *channel;
1653 if (efx->state == STATE_DISABLED)
1656 efx_mcdi_mode_poll(efx);
1658 efx->irq_soft_enabled = false;
1661 if (efx->legacy_irq)
1662 synchronize_irq(efx->legacy_irq);
1664 efx_for_each_channel(channel, efx) {
1666 synchronize_irq(channel->irq);
1668 efx_stop_eventq(channel);
1669 if (!channel->type->keep_eventq)
1670 efx_fini_eventq(channel);
1673 /* Flush the asynchronous MCDI request queue */
1674 efx_mcdi_flush_async(efx);
1677 int efx_enable_interrupts(struct efx_nic *efx)
1679 struct efx_channel *channel, *end_channel;
1682 BUG_ON(efx->state == STATE_DISABLED);
1684 if (efx->eeh_disabled_legacy_irq) {
1685 enable_irq(efx->legacy_irq);
1686 efx->eeh_disabled_legacy_irq = false;
1689 efx->type->irq_enable_master(efx);
1691 efx_for_each_channel(channel, efx) {
1692 if (channel->type->keep_eventq) {
1693 rc = efx_init_eventq(channel);
1699 rc = efx_soft_enable_interrupts(efx);
1706 end_channel = channel;
1707 efx_for_each_channel(channel, efx) {
1708 if (channel == end_channel)
1710 if (channel->type->keep_eventq)
1711 efx_fini_eventq(channel);
1714 efx->type->irq_disable_non_ev(efx);
1719 void efx_disable_interrupts(struct efx_nic *efx)
1721 struct efx_channel *channel;
1723 efx_soft_disable_interrupts(efx);
1725 efx_for_each_channel(channel, efx) {
1726 if (channel->type->keep_eventq)
1727 efx_fini_eventq(channel);
1730 efx->type->irq_disable_non_ev(efx);
1733 void efx_remove_interrupts(struct efx_nic *efx)
1735 struct efx_channel *channel;
1737 /* Remove MSI/MSI-X interrupts */
1738 efx_for_each_channel(channel, efx)
1740 pci_disable_msi(efx->pci_dev);
1741 pci_disable_msix(efx->pci_dev);
1743 /* Remove legacy interrupt */
1744 efx->legacy_irq = 0;
1747 int efx_set_channels(struct efx_nic *efx)
1749 struct efx_channel *channel;
1750 struct efx_tx_queue *tx_queue;
1751 int xdp_queue_number;
1753 efx->tx_channel_offset =
1754 efx_separate_tx_channels ?
1755 efx->n_channels - efx->n_tx_channels : 0;
1757 if (efx->xdp_tx_queue_count) {
1758 EFX_WARN_ON_PARANOID(efx->xdp_tx_queues);
1760 /* Allocate array for XDP TX queue lookup. */
1761 efx->xdp_tx_queues = kcalloc(efx->xdp_tx_queue_count,
1762 sizeof(*efx->xdp_tx_queues),
1764 if (!efx->xdp_tx_queues)
1768 /* We need to mark which channels really have RX and TX
1769 * queues, and adjust the TX queue numbers if we have separate
1770 * RX-only and TX-only channels.
1772 xdp_queue_number = 0;
1773 efx_for_each_channel(channel, efx) {
1774 if (channel->channel < efx->n_rx_channels)
1775 channel->rx_queue.core_index = channel->channel;
1777 channel->rx_queue.core_index = -1;
1779 efx_for_each_channel_tx_queue(tx_queue, channel) {
1780 tx_queue->queue -= (efx->tx_channel_offset *
1783 if (efx_channel_is_xdp_tx(channel) &&
1784 xdp_queue_number < efx->xdp_tx_queue_count) {
1785 efx->xdp_tx_queues[xdp_queue_number] = tx_queue;
1793 static int efx_probe_nic(struct efx_nic *efx)
1797 netif_dbg(efx, probe, efx->net_dev, "creating NIC\n");
1799 /* Carry out hardware-type specific initialisation */
1800 rc = efx->type->probe(efx);
1805 if (!efx->max_channels || !efx->max_tx_channels) {
1806 netif_err(efx, drv, efx->net_dev,
1807 "Insufficient resources to allocate"
1813 /* Determine the number of channels and queues by trying
1814 * to hook in MSI-X interrupts.
1816 rc = efx_probe_interrupts(efx);
1820 rc = efx_set_channels(efx);
1824 /* dimension_resources can fail with EAGAIN */
1825 rc = efx->type->dimension_resources(efx);
1826 if (rc != 0 && rc != -EAGAIN)
1830 /* try again with new max_channels */
1831 efx_remove_interrupts(efx);
1833 } while (rc == -EAGAIN);
1835 if (efx->n_channels > 1)
1836 netdev_rss_key_fill(efx->rss_context.rx_hash_key,
1837 sizeof(efx->rss_context.rx_hash_key));
1838 efx_set_default_rx_indir_table(efx, &efx->rss_context);
1840 netif_set_real_num_tx_queues(efx->net_dev, efx->n_tx_channels);
1841 netif_set_real_num_rx_queues(efx->net_dev, efx->n_rx_channels);
1843 /* Initialise the interrupt moderation settings */
1844 efx->irq_mod_step_us = DIV_ROUND_UP(efx->timer_quantum_ns, 1000);
1845 efx_init_irq_moderation(efx, tx_irq_mod_usec, rx_irq_mod_usec, true,
1851 efx_remove_interrupts(efx);
1853 efx->type->remove(efx);
1857 static void efx_remove_nic(struct efx_nic *efx)
1859 netif_dbg(efx, drv, efx->net_dev, "destroying NIC\n");
1861 efx_remove_interrupts(efx);
1862 efx->type->remove(efx);
1865 static int efx_probe_filters(struct efx_nic *efx)
1869 init_rwsem(&efx->filter_sem);
1870 mutex_lock(&efx->mac_lock);
1871 down_write(&efx->filter_sem);
1872 rc = efx->type->filter_table_probe(efx);
1876 #ifdef CONFIG_RFS_ACCEL
1877 if (efx->type->offload_features & NETIF_F_NTUPLE) {
1878 struct efx_channel *channel;
1881 efx_for_each_channel(channel, efx) {
1882 channel->rps_flow_id =
1883 kcalloc(efx->type->max_rx_ip_filters,
1884 sizeof(*channel->rps_flow_id),
1886 if (!channel->rps_flow_id)
1890 i < efx->type->max_rx_ip_filters;
1892 channel->rps_flow_id[i] =
1893 RPS_FLOW_ID_INVALID;
1894 channel->rfs_expire_index = 0;
1895 channel->rfs_filter_count = 0;
1899 efx_for_each_channel(channel, efx)
1900 kfree(channel->rps_flow_id);
1901 efx->type->filter_table_remove(efx);
1908 up_write(&efx->filter_sem);
1909 mutex_unlock(&efx->mac_lock);
1913 static void efx_remove_filters(struct efx_nic *efx)
1915 #ifdef CONFIG_RFS_ACCEL
1916 struct efx_channel *channel;
1918 efx_for_each_channel(channel, efx) {
1919 cancel_delayed_work_sync(&channel->filter_work);
1920 kfree(channel->rps_flow_id);
1923 down_write(&efx->filter_sem);
1924 efx->type->filter_table_remove(efx);
1925 up_write(&efx->filter_sem);
1929 /**************************************************************************
1931 * NIC startup/shutdown
1933 *************************************************************************/
1935 static int efx_probe_all(struct efx_nic *efx)
1939 rc = efx_probe_nic(efx);
1941 netif_err(efx, probe, efx->net_dev, "failed to create NIC\n");
1945 rc = efx_probe_port(efx);
1947 netif_err(efx, probe, efx->net_dev, "failed to create port\n");
1951 BUILD_BUG_ON(EFX_DEFAULT_DMAQ_SIZE < EFX_RXQ_MIN_ENT);
1952 if (WARN_ON(EFX_DEFAULT_DMAQ_SIZE < EFX_TXQ_MIN_ENT(efx))) {
1956 efx->rxq_entries = efx->txq_entries = EFX_DEFAULT_DMAQ_SIZE;
1958 #ifdef CONFIG_SFC_SRIOV
1959 rc = efx->type->vswitching_probe(efx);
1960 if (rc) /* not fatal; the PF will still work fine */
1961 netif_warn(efx, probe, efx->net_dev,
1962 "failed to setup vswitching rc=%d;"
1963 " VFs may not function\n", rc);
1966 rc = efx_probe_filters(efx);
1968 netif_err(efx, probe, efx->net_dev,
1969 "failed to create filter tables\n");
1973 rc = efx_probe_channels(efx);
1980 efx_remove_filters(efx);
1982 #ifdef CONFIG_SFC_SRIOV
1983 efx->type->vswitching_remove(efx);
1986 efx_remove_port(efx);
1988 efx_remove_nic(efx);
1993 /* If the interface is supposed to be running but is not, start
1994 * the hardware and software data path, regular activity for the port
1995 * (MAC statistics, link polling, etc.) and schedule the port to be
1996 * reconfigured. Interrupts must already be enabled. This function
1997 * is safe to call multiple times, so long as the NIC is not disabled.
1998 * Requires the RTNL lock.
2000 void efx_start_all(struct efx_nic *efx)
2002 EFX_ASSERT_RESET_SERIALISED(efx);
2003 BUG_ON(efx->state == STATE_DISABLED);
2005 /* Check that it is appropriate to restart the interface. All
2006 * of these flags are safe to read under just the rtnl lock */
2007 if (efx->port_enabled || !netif_running(efx->net_dev) ||
2011 efx_start_port(efx);
2012 efx_start_datapath(efx);
2014 /* Start the hardware monitor if there is one */
2015 if (efx->type->monitor != NULL)
2016 queue_delayed_work(efx->workqueue, &efx->monitor_work,
2017 efx_monitor_interval);
2019 /* Link state detection is normally event-driven; we have
2020 * to poll now because we could have missed a change
2022 mutex_lock(&efx->mac_lock);
2023 if (efx->phy_op->poll(efx))
2024 efx_link_status_changed(efx);
2025 mutex_unlock(&efx->mac_lock);
2027 efx->type->start_stats(efx);
2028 efx->type->pull_stats(efx);
2029 spin_lock_bh(&efx->stats_lock);
2030 efx->type->update_stats(efx, NULL, NULL);
2031 spin_unlock_bh(&efx->stats_lock);
2034 /* Quiesce the hardware and software data path, and regular activity
2035 * for the port without bringing the link down. Safe to call multiple
2036 * times with the NIC in almost any state, but interrupts should be
2037 * enabled. Requires the RTNL lock.
2039 void efx_stop_all(struct efx_nic *efx)
2041 EFX_ASSERT_RESET_SERIALISED(efx);
2043 /* port_enabled can be read safely under the rtnl lock */
2044 if (!efx->port_enabled)
2047 /* update stats before we go down so we can accurately count
2050 efx->type->pull_stats(efx);
2051 spin_lock_bh(&efx->stats_lock);
2052 efx->type->update_stats(efx, NULL, NULL);
2053 spin_unlock_bh(&efx->stats_lock);
2054 efx->type->stop_stats(efx);
2057 /* Stop the kernel transmit interface. This is only valid if
2058 * the device is stopped or detached; otherwise the watchdog
2059 * may fire immediately.
2061 WARN_ON(netif_running(efx->net_dev) &&
2062 netif_device_present(efx->net_dev));
2063 netif_tx_disable(efx->net_dev);
2065 efx_stop_datapath(efx);
2068 static void efx_remove_all(struct efx_nic *efx)
2071 efx_xdp_setup_prog(efx, NULL);
2074 efx_remove_channels(efx);
2075 efx_remove_filters(efx);
2076 #ifdef CONFIG_SFC_SRIOV
2077 efx->type->vswitching_remove(efx);
2079 efx_remove_port(efx);
2080 efx_remove_nic(efx);
2083 /**************************************************************************
2085 * Interrupt moderation
2087 **************************************************************************/
2088 unsigned int efx_usecs_to_ticks(struct efx_nic *efx, unsigned int usecs)
2092 if (usecs * 1000 < efx->timer_quantum_ns)
2093 return 1; /* never round down to 0 */
2094 return usecs * 1000 / efx->timer_quantum_ns;
2097 unsigned int efx_ticks_to_usecs(struct efx_nic *efx, unsigned int ticks)
2099 /* We must round up when converting ticks to microseconds
2100 * because we round down when converting the other way.
2102 return DIV_ROUND_UP(ticks * efx->timer_quantum_ns, 1000);
2105 /* Set interrupt moderation parameters */
2106 int efx_init_irq_moderation(struct efx_nic *efx, unsigned int tx_usecs,
2107 unsigned int rx_usecs, bool rx_adaptive,
2108 bool rx_may_override_tx)
2110 struct efx_channel *channel;
2111 unsigned int timer_max_us;
2113 EFX_ASSERT_RESET_SERIALISED(efx);
2115 timer_max_us = efx->timer_max_ns / 1000;
2117 if (tx_usecs > timer_max_us || rx_usecs > timer_max_us)
2120 if (tx_usecs != rx_usecs && efx->tx_channel_offset == 0 &&
2121 !rx_may_override_tx) {
2122 netif_err(efx, drv, efx->net_dev, "Channels are shared. "
2123 "RX and TX IRQ moderation must be equal\n");
2127 efx->irq_rx_adaptive = rx_adaptive;
2128 efx->irq_rx_moderation_us = rx_usecs;
2129 efx_for_each_channel(channel, efx) {
2130 if (efx_channel_has_rx_queue(channel))
2131 channel->irq_moderation_us = rx_usecs;
2132 else if (efx_channel_has_tx_queues(channel))
2133 channel->irq_moderation_us = tx_usecs;
2134 else if (efx_channel_is_xdp_tx(channel))
2135 channel->irq_moderation_us = tx_usecs;
2141 void efx_get_irq_moderation(struct efx_nic *efx, unsigned int *tx_usecs,
2142 unsigned int *rx_usecs, bool *rx_adaptive)
2144 *rx_adaptive = efx->irq_rx_adaptive;
2145 *rx_usecs = efx->irq_rx_moderation_us;
2147 /* If channels are shared between RX and TX, so is IRQ
2148 * moderation. Otherwise, IRQ moderation is the same for all
2149 * TX channels and is not adaptive.
2151 if (efx->tx_channel_offset == 0) {
2152 *tx_usecs = *rx_usecs;
2154 struct efx_channel *tx_channel;
2156 tx_channel = efx->channel[efx->tx_channel_offset];
2157 *tx_usecs = tx_channel->irq_moderation_us;
2161 /**************************************************************************
2165 **************************************************************************/
2167 /* Run periodically off the general workqueue */
2168 static void efx_monitor(struct work_struct *data)
2170 struct efx_nic *efx = container_of(data, struct efx_nic,
2173 netif_vdbg(efx, timer, efx->net_dev,
2174 "hardware monitor executing on CPU %d\n",
2175 raw_smp_processor_id());
2176 BUG_ON(efx->type->monitor == NULL);
2178 /* If the mac_lock is already held then it is likely a port
2179 * reconfiguration is already in place, which will likely do
2180 * most of the work of monitor() anyway. */
2181 if (mutex_trylock(&efx->mac_lock)) {
2182 if (efx->port_enabled)
2183 efx->type->monitor(efx);
2184 mutex_unlock(&efx->mac_lock);
2187 queue_delayed_work(efx->workqueue, &efx->monitor_work,
2188 efx_monitor_interval);
2191 /**************************************************************************
2195 *************************************************************************/
2198 * Context: process, rtnl_lock() held.
2200 static int efx_ioctl(struct net_device *net_dev, struct ifreq *ifr, int cmd)
2202 struct efx_nic *efx = netdev_priv(net_dev);
2203 struct mii_ioctl_data *data = if_mii(ifr);
2205 if (cmd == SIOCSHWTSTAMP)
2206 return efx_ptp_set_ts_config(efx, ifr);
2207 if (cmd == SIOCGHWTSTAMP)
2208 return efx_ptp_get_ts_config(efx, ifr);
2210 /* Convert phy_id from older PRTAD/DEVAD format */
2211 if ((cmd == SIOCGMIIREG || cmd == SIOCSMIIREG) &&
2212 (data->phy_id & 0xfc00) == 0x0400)
2213 data->phy_id ^= MDIO_PHY_ID_C45 | 0x0400;
2215 return mdio_mii_ioctl(&efx->mdio, data, cmd);
2218 /**************************************************************************
2222 **************************************************************************/
2224 void efx_init_napi_channel(struct efx_channel *channel)
2226 struct efx_nic *efx = channel->efx;
2228 channel->napi_dev = efx->net_dev;
2229 netif_napi_add(channel->napi_dev, &channel->napi_str,
2230 efx_poll, napi_weight);
2233 void efx_init_napi(struct efx_nic *efx)
2235 struct efx_channel *channel;
2237 efx_for_each_channel(channel, efx)
2238 efx_init_napi_channel(channel);
2241 void efx_fini_napi_channel(struct efx_channel *channel)
2243 if (channel->napi_dev)
2244 netif_napi_del(&channel->napi_str);
2246 channel->napi_dev = NULL;
2249 void efx_fini_napi(struct efx_nic *efx)
2251 struct efx_channel *channel;
2253 efx_for_each_channel(channel, efx)
2254 efx_fini_napi_channel(channel);
2257 /**************************************************************************
2259 * Kernel net device interface
2261 *************************************************************************/
2263 /* Context: process, rtnl_lock() held. */
2264 int efx_net_open(struct net_device *net_dev)
2266 struct efx_nic *efx = netdev_priv(net_dev);
2269 netif_dbg(efx, ifup, efx->net_dev, "opening device on CPU %d\n",
2270 raw_smp_processor_id());
2272 rc = efx_check_disabled(efx);
2275 if (efx->phy_mode & PHY_MODE_SPECIAL)
2277 if (efx_mcdi_poll_reboot(efx) && efx_reset(efx, RESET_TYPE_ALL))
2280 /* Notify the kernel of the link state polled during driver load,
2281 * before the monitor starts running */
2282 efx_link_status_changed(efx);
2285 if (efx->state == STATE_DISABLED || efx->reset_pending)
2286 netif_device_detach(efx->net_dev);
2287 efx_selftest_async_start(efx);
2291 /* Context: process, rtnl_lock() held.
2292 * Note that the kernel will ignore our return code; this method
2293 * should really be a void.
2295 int efx_net_stop(struct net_device *net_dev)
2297 struct efx_nic *efx = netdev_priv(net_dev);
2299 netif_dbg(efx, ifdown, efx->net_dev, "closing on CPU %d\n",
2300 raw_smp_processor_id());
2302 /* Stop the device and flush all the channels */
2308 /* Context: process, dev_base_lock or RTNL held, non-blocking. */
2309 static void efx_net_stats(struct net_device *net_dev,
2310 struct rtnl_link_stats64 *stats)
2312 struct efx_nic *efx = netdev_priv(net_dev);
2314 spin_lock_bh(&efx->stats_lock);
2315 efx->type->update_stats(efx, NULL, stats);
2316 spin_unlock_bh(&efx->stats_lock);
2319 /* Context: netif_tx_lock held, BHs disabled. */
2320 static void efx_watchdog(struct net_device *net_dev, unsigned int txqueue)
2322 struct efx_nic *efx = netdev_priv(net_dev);
2324 netif_err(efx, tx_err, efx->net_dev,
2325 "TX stuck with port_enabled=%d: resetting channels\n",
2328 efx_schedule_reset(efx, RESET_TYPE_TX_WATCHDOG);
2331 static unsigned int efx_xdp_max_mtu(struct efx_nic *efx)
2333 /* The maximum MTU that we can fit in a single page, allowing for
2334 * framing, overhead and XDP headroom.
2336 int overhead = EFX_MAX_FRAME_LEN(0) + sizeof(struct efx_rx_page_state) +
2337 efx->rx_prefix_size + efx->type->rx_buffer_padding +
2338 efx->rx_ip_align + XDP_PACKET_HEADROOM;
2340 return PAGE_SIZE - overhead;
2343 /* Context: process, rtnl_lock() held. */
2344 static int efx_change_mtu(struct net_device *net_dev, int new_mtu)
2346 struct efx_nic *efx = netdev_priv(net_dev);
2349 rc = efx_check_disabled(efx);
2353 if (rtnl_dereference(efx->xdp_prog) &&
2354 new_mtu > efx_xdp_max_mtu(efx)) {
2355 netif_err(efx, drv, efx->net_dev,
2356 "Requested MTU of %d too big for XDP (max: %d)\n",
2357 new_mtu, efx_xdp_max_mtu(efx));
2361 netif_dbg(efx, drv, efx->net_dev, "changing MTU to %d\n", new_mtu);
2363 efx_device_detach_sync(efx);
2366 mutex_lock(&efx->mac_lock);
2367 net_dev->mtu = new_mtu;
2368 efx_mac_reconfigure(efx);
2369 mutex_unlock(&efx->mac_lock);
2372 efx_device_attach_if_not_resetting(efx);
2376 static int efx_set_mac_address(struct net_device *net_dev, void *data)
2378 struct efx_nic *efx = netdev_priv(net_dev);
2379 struct sockaddr *addr = data;
2380 u8 *new_addr = addr->sa_data;
2384 if (!is_valid_ether_addr(new_addr)) {
2385 netif_err(efx, drv, efx->net_dev,
2386 "invalid ethernet MAC address requested: %pM\n",
2388 return -EADDRNOTAVAIL;
2391 /* save old address */
2392 ether_addr_copy(old_addr, net_dev->dev_addr);
2393 ether_addr_copy(net_dev->dev_addr, new_addr);
2394 if (efx->type->set_mac_address) {
2395 rc = efx->type->set_mac_address(efx);
2397 ether_addr_copy(net_dev->dev_addr, old_addr);
2402 /* Reconfigure the MAC */
2403 mutex_lock(&efx->mac_lock);
2404 efx_mac_reconfigure(efx);
2405 mutex_unlock(&efx->mac_lock);
2410 /* Context: netif_addr_lock held, BHs disabled. */
2411 static void efx_set_rx_mode(struct net_device *net_dev)
2413 struct efx_nic *efx = netdev_priv(net_dev);
2415 if (efx->port_enabled)
2416 queue_work(efx->workqueue, &efx->mac_work);
2417 /* Otherwise efx_start_port() will do this */
2420 static int efx_set_features(struct net_device *net_dev, netdev_features_t data)
2422 struct efx_nic *efx = netdev_priv(net_dev);
2425 /* If disabling RX n-tuple filtering, clear existing filters */
2426 if (net_dev->features & ~data & NETIF_F_NTUPLE) {
2427 rc = efx->type->filter_clear_rx(efx, EFX_FILTER_PRI_MANUAL);
2432 /* If Rx VLAN filter is changed, update filters via mac_reconfigure.
2433 * If rx-fcs is changed, mac_reconfigure updates that too.
2435 if ((net_dev->features ^ data) & (NETIF_F_HW_VLAN_CTAG_FILTER |
2437 /* efx_set_rx_mode() will schedule MAC work to update filters
2438 * when a new features are finally set in net_dev.
2440 efx_set_rx_mode(net_dev);
2446 static int efx_get_phys_port_id(struct net_device *net_dev,
2447 struct netdev_phys_item_id *ppid)
2449 struct efx_nic *efx = netdev_priv(net_dev);
2451 if (efx->type->get_phys_port_id)
2452 return efx->type->get_phys_port_id(efx, ppid);
2457 static int efx_get_phys_port_name(struct net_device *net_dev,
2458 char *name, size_t len)
2460 struct efx_nic *efx = netdev_priv(net_dev);
2462 if (snprintf(name, len, "p%u", efx->port_num) >= len)
2467 static int efx_vlan_rx_add_vid(struct net_device *net_dev, __be16 proto, u16 vid)
2469 struct efx_nic *efx = netdev_priv(net_dev);
2471 if (efx->type->vlan_rx_add_vid)
2472 return efx->type->vlan_rx_add_vid(efx, proto, vid);
2477 static int efx_vlan_rx_kill_vid(struct net_device *net_dev, __be16 proto, u16 vid)
2479 struct efx_nic *efx = netdev_priv(net_dev);
2481 if (efx->type->vlan_rx_kill_vid)
2482 return efx->type->vlan_rx_kill_vid(efx, proto, vid);
2487 static int efx_udp_tunnel_type_map(enum udp_parsable_tunnel_type in)
2490 case UDP_TUNNEL_TYPE_VXLAN:
2491 return TUNNEL_ENCAP_UDP_PORT_ENTRY_VXLAN;
2492 case UDP_TUNNEL_TYPE_GENEVE:
2493 return TUNNEL_ENCAP_UDP_PORT_ENTRY_GENEVE;
2499 static void efx_udp_tunnel_add(struct net_device *dev, struct udp_tunnel_info *ti)
2501 struct efx_nic *efx = netdev_priv(dev);
2502 struct efx_udp_tunnel tnl;
2503 int efx_tunnel_type;
2505 efx_tunnel_type = efx_udp_tunnel_type_map(ti->type);
2506 if (efx_tunnel_type < 0)
2509 tnl.type = (u16)efx_tunnel_type;
2510 tnl.port = ti->port;
2512 if (efx->type->udp_tnl_add_port)
2513 (void)efx->type->udp_tnl_add_port(efx, tnl);
2516 static void efx_udp_tunnel_del(struct net_device *dev, struct udp_tunnel_info *ti)
2518 struct efx_nic *efx = netdev_priv(dev);
2519 struct efx_udp_tunnel tnl;
2520 int efx_tunnel_type;
2522 efx_tunnel_type = efx_udp_tunnel_type_map(ti->type);
2523 if (efx_tunnel_type < 0)
2526 tnl.type = (u16)efx_tunnel_type;
2527 tnl.port = ti->port;
2529 if (efx->type->udp_tnl_del_port)
2530 (void)efx->type->udp_tnl_del_port(efx, tnl);
2533 static const struct net_device_ops efx_netdev_ops = {
2534 .ndo_open = efx_net_open,
2535 .ndo_stop = efx_net_stop,
2536 .ndo_get_stats64 = efx_net_stats,
2537 .ndo_tx_timeout = efx_watchdog,
2538 .ndo_start_xmit = efx_hard_start_xmit,
2539 .ndo_validate_addr = eth_validate_addr,
2540 .ndo_do_ioctl = efx_ioctl,
2541 .ndo_change_mtu = efx_change_mtu,
2542 .ndo_set_mac_address = efx_set_mac_address,
2543 .ndo_set_rx_mode = efx_set_rx_mode,
2544 .ndo_set_features = efx_set_features,
2545 .ndo_vlan_rx_add_vid = efx_vlan_rx_add_vid,
2546 .ndo_vlan_rx_kill_vid = efx_vlan_rx_kill_vid,
2547 #ifdef CONFIG_SFC_SRIOV
2548 .ndo_set_vf_mac = efx_sriov_set_vf_mac,
2549 .ndo_set_vf_vlan = efx_sriov_set_vf_vlan,
2550 .ndo_set_vf_spoofchk = efx_sriov_set_vf_spoofchk,
2551 .ndo_get_vf_config = efx_sriov_get_vf_config,
2552 .ndo_set_vf_link_state = efx_sriov_set_vf_link_state,
2554 .ndo_get_phys_port_id = efx_get_phys_port_id,
2555 .ndo_get_phys_port_name = efx_get_phys_port_name,
2556 .ndo_setup_tc = efx_setup_tc,
2557 #ifdef CONFIG_RFS_ACCEL
2558 .ndo_rx_flow_steer = efx_filter_rfs,
2560 .ndo_udp_tunnel_add = efx_udp_tunnel_add,
2561 .ndo_udp_tunnel_del = efx_udp_tunnel_del,
2562 .ndo_xdp_xmit = efx_xdp_xmit,
2566 static int efx_xdp_setup_prog(struct efx_nic *efx, struct bpf_prog *prog)
2568 struct bpf_prog *old_prog;
2570 if (efx->xdp_rxq_info_failed) {
2571 netif_err(efx, drv, efx->net_dev,
2572 "Unable to bind XDP program due to previous failure of rxq_info\n");
2576 if (prog && efx->net_dev->mtu > efx_xdp_max_mtu(efx)) {
2577 netif_err(efx, drv, efx->net_dev,
2578 "Unable to configure XDP with MTU of %d (max: %d)\n",
2579 efx->net_dev->mtu, efx_xdp_max_mtu(efx));
2583 old_prog = rtnl_dereference(efx->xdp_prog);
2584 rcu_assign_pointer(efx->xdp_prog, prog);
2585 /* Release the reference that was originally passed by the caller. */
2587 bpf_prog_put(old_prog);
2592 /* Context: process, rtnl_lock() held. */
2593 static int efx_xdp(struct net_device *dev, struct netdev_bpf *xdp)
2595 struct efx_nic *efx = netdev_priv(dev);
2596 struct bpf_prog *xdp_prog;
2598 switch (xdp->command) {
2599 case XDP_SETUP_PROG:
2600 return efx_xdp_setup_prog(efx, xdp->prog);
2601 case XDP_QUERY_PROG:
2602 xdp_prog = rtnl_dereference(efx->xdp_prog);
2603 xdp->prog_id = xdp_prog ? xdp_prog->aux->id : 0;
2610 static int efx_xdp_xmit(struct net_device *dev, int n, struct xdp_frame **xdpfs,
2613 struct efx_nic *efx = netdev_priv(dev);
2615 if (!netif_running(dev))
2618 return efx_xdp_tx_buffers(efx, n, xdpfs, flags & XDP_XMIT_FLUSH);
2621 static void efx_update_name(struct efx_nic *efx)
2623 strcpy(efx->name, efx->net_dev->name);
2624 efx_mtd_rename(efx);
2625 efx_set_channel_names(efx);
2628 static int efx_netdev_event(struct notifier_block *this,
2629 unsigned long event, void *ptr)
2631 struct net_device *net_dev = netdev_notifier_info_to_dev(ptr);
2633 if ((net_dev->netdev_ops == &efx_netdev_ops) &&
2634 event == NETDEV_CHANGENAME)
2635 efx_update_name(netdev_priv(net_dev));
2640 static struct notifier_block efx_netdev_notifier = {
2641 .notifier_call = efx_netdev_event,
2645 show_phy_type(struct device *dev, struct device_attribute *attr, char *buf)
2647 struct efx_nic *efx = dev_get_drvdata(dev);
2648 return sprintf(buf, "%d\n", efx->phy_type);
2650 static DEVICE_ATTR(phy_type, 0444, show_phy_type, NULL);
2652 #ifdef CONFIG_SFC_MCDI_LOGGING
2653 static ssize_t show_mcdi_log(struct device *dev, struct device_attribute *attr,
2656 struct efx_nic *efx = dev_get_drvdata(dev);
2657 struct efx_mcdi_iface *mcdi = efx_mcdi(efx);
2659 return scnprintf(buf, PAGE_SIZE, "%d\n", mcdi->logging_enabled);
2661 static ssize_t set_mcdi_log(struct device *dev, struct device_attribute *attr,
2662 const char *buf, size_t count)
2664 struct efx_nic *efx = dev_get_drvdata(dev);
2665 struct efx_mcdi_iface *mcdi = efx_mcdi(efx);
2666 bool enable = count > 0 && *buf != '0';
2668 mcdi->logging_enabled = enable;
2671 static DEVICE_ATTR(mcdi_logging, 0644, show_mcdi_log, set_mcdi_log);
2674 static int efx_register_netdev(struct efx_nic *efx)
2676 struct net_device *net_dev = efx->net_dev;
2677 struct efx_channel *channel;
2680 net_dev->watchdog_timeo = 5 * HZ;
2681 net_dev->irq = efx->pci_dev->irq;
2682 net_dev->netdev_ops = &efx_netdev_ops;
2683 if (efx_nic_rev(efx) >= EFX_REV_HUNT_A0)
2684 net_dev->priv_flags |= IFF_UNICAST_FLT;
2685 net_dev->ethtool_ops = &efx_ethtool_ops;
2686 net_dev->gso_max_segs = EFX_TSO_MAX_SEGS;
2687 net_dev->min_mtu = EFX_MIN_MTU;
2688 net_dev->max_mtu = EFX_MAX_MTU;
2692 /* Enable resets to be scheduled and check whether any were
2693 * already requested. If so, the NIC is probably hosed so we
2696 efx->state = STATE_READY;
2697 smp_mb(); /* ensure we change state before checking reset_pending */
2698 if (efx->reset_pending) {
2699 netif_err(efx, probe, efx->net_dev,
2700 "aborting probe due to scheduled reset\n");
2705 rc = dev_alloc_name(net_dev, net_dev->name);
2708 efx_update_name(efx);
2710 /* Always start with carrier off; PHY events will detect the link */
2711 netif_carrier_off(net_dev);
2713 rc = register_netdevice(net_dev);
2717 efx_for_each_channel(channel, efx) {
2718 struct efx_tx_queue *tx_queue;
2719 efx_for_each_channel_tx_queue(tx_queue, channel)
2720 efx_init_tx_queue_core_txq(tx_queue);
2727 rc = device_create_file(&efx->pci_dev->dev, &dev_attr_phy_type);
2729 netif_err(efx, drv, efx->net_dev,
2730 "failed to init net dev attributes\n");
2731 goto fail_registered;
2733 #ifdef CONFIG_SFC_MCDI_LOGGING
2734 rc = device_create_file(&efx->pci_dev->dev, &dev_attr_mcdi_logging);
2736 netif_err(efx, drv, efx->net_dev,
2737 "failed to init net dev attributes\n");
2738 goto fail_attr_mcdi_logging;
2744 #ifdef CONFIG_SFC_MCDI_LOGGING
2745 fail_attr_mcdi_logging:
2746 device_remove_file(&efx->pci_dev->dev, &dev_attr_phy_type);
2750 efx_dissociate(efx);
2751 unregister_netdevice(net_dev);
2753 efx->state = STATE_UNINIT;
2755 netif_err(efx, drv, efx->net_dev, "could not register net dev\n");
2759 static void efx_unregister_netdev(struct efx_nic *efx)
2764 BUG_ON(netdev_priv(efx->net_dev) != efx);
2766 if (efx_dev_registered(efx)) {
2767 strlcpy(efx->name, pci_name(efx->pci_dev), sizeof(efx->name));
2768 #ifdef CONFIG_SFC_MCDI_LOGGING
2769 device_remove_file(&efx->pci_dev->dev, &dev_attr_mcdi_logging);
2771 device_remove_file(&efx->pci_dev->dev, &dev_attr_phy_type);
2772 unregister_netdev(efx->net_dev);
2776 /**************************************************************************
2778 * Device reset and suspend
2780 **************************************************************************/
2782 /* Tears down the entire software state and most of the hardware state
2784 void efx_reset_down(struct efx_nic *efx, enum reset_type method)
2786 EFX_ASSERT_RESET_SERIALISED(efx);
2788 if (method == RESET_TYPE_MCDI_TIMEOUT)
2789 efx->type->prepare_flr(efx);
2792 efx_disable_interrupts(efx);
2794 mutex_lock(&efx->mac_lock);
2795 down_write(&efx->filter_sem);
2796 mutex_lock(&efx->rss_lock);
2797 if (efx->port_initialized && method != RESET_TYPE_INVISIBLE &&
2798 method != RESET_TYPE_DATAPATH)
2799 efx->phy_op->fini(efx);
2800 efx->type->fini(efx);
2803 /* This function will always ensure that the locks acquired in
2804 * efx_reset_down() are released. A failure return code indicates
2805 * that we were unable to reinitialise the hardware, and the
2806 * driver should be disabled. If ok is false, then the rx and tx
2807 * engines are not restarted, pending a RESET_DISABLE. */
2808 int efx_reset_up(struct efx_nic *efx, enum reset_type method, bool ok)
2812 EFX_ASSERT_RESET_SERIALISED(efx);
2814 if (method == RESET_TYPE_MCDI_TIMEOUT)
2815 efx->type->finish_flr(efx);
2817 /* Ensure that SRAM is initialised even if we're disabling the device */
2818 rc = efx->type->init(efx);
2820 netif_err(efx, drv, efx->net_dev, "failed to initialise NIC\n");
2827 if (efx->port_initialized && method != RESET_TYPE_INVISIBLE &&
2828 method != RESET_TYPE_DATAPATH) {
2829 rc = efx->phy_op->init(efx);
2832 rc = efx->phy_op->reconfigure(efx);
2833 if (rc && rc != -EPERM)
2834 netif_err(efx, drv, efx->net_dev,
2835 "could not restore PHY settings\n");
2838 rc = efx_enable_interrupts(efx);
2842 #ifdef CONFIG_SFC_SRIOV
2843 rc = efx->type->vswitching_restore(efx);
2844 if (rc) /* not fatal; the PF will still work fine */
2845 netif_warn(efx, probe, efx->net_dev,
2846 "failed to restore vswitching rc=%d;"
2847 " VFs may not function\n", rc);
2850 if (efx->type->rx_restore_rss_contexts)
2851 efx->type->rx_restore_rss_contexts(efx);
2852 mutex_unlock(&efx->rss_lock);
2853 efx->type->filter_table_restore(efx);
2854 up_write(&efx->filter_sem);
2855 if (efx->type->sriov_reset)
2856 efx->type->sriov_reset(efx);
2858 mutex_unlock(&efx->mac_lock);
2862 if (efx->type->udp_tnl_push_ports)
2863 efx->type->udp_tnl_push_ports(efx);
2868 efx->port_initialized = false;
2870 mutex_unlock(&efx->rss_lock);
2871 up_write(&efx->filter_sem);
2872 mutex_unlock(&efx->mac_lock);
2877 /* Reset the NIC using the specified method. Note that the reset may
2878 * fail, in which case the card will be left in an unusable state.
2880 * Caller must hold the rtnl_lock.
2882 int efx_reset(struct efx_nic *efx, enum reset_type method)
2887 netif_info(efx, drv, efx->net_dev, "resetting (%s)\n",
2888 RESET_TYPE(method));
2890 efx_device_detach_sync(efx);
2891 efx_reset_down(efx, method);
2893 rc = efx->type->reset(efx, method);
2895 netif_err(efx, drv, efx->net_dev, "failed to reset hardware\n");
2899 /* Clear flags for the scopes we covered. We assume the NIC and
2900 * driver are now quiescent so that there is no race here.
2902 if (method < RESET_TYPE_MAX_METHOD)
2903 efx->reset_pending &= -(1 << (method + 1));
2904 else /* it doesn't fit into the well-ordered scope hierarchy */
2905 __clear_bit(method, &efx->reset_pending);
2907 /* Reinitialise bus-mastering, which may have been turned off before
2908 * the reset was scheduled. This is still appropriate, even in the
2909 * RESET_TYPE_DISABLE since this driver generally assumes the hardware
2910 * can respond to requests. */
2911 pci_set_master(efx->pci_dev);
2914 /* Leave device stopped if necessary */
2916 method == RESET_TYPE_DISABLE ||
2917 method == RESET_TYPE_RECOVER_OR_DISABLE;
2918 rc2 = efx_reset_up(efx, method, !disabled);
2926 dev_close(efx->net_dev);
2927 netif_err(efx, drv, efx->net_dev, "has been disabled\n");
2928 efx->state = STATE_DISABLED;
2930 netif_dbg(efx, drv, efx->net_dev, "reset complete\n");
2931 efx_device_attach_if_not_resetting(efx);
2936 /* Try recovery mechanisms.
2937 * For now only EEH is supported.
2938 * Returns 0 if the recovery mechanisms are unsuccessful.
2939 * Returns a non-zero value otherwise.
2941 int efx_try_recovery(struct efx_nic *efx)
2944 /* A PCI error can occur and not be seen by EEH because nothing
2945 * happens on the PCI bus. In this case the driver may fail and
2946 * schedule a 'recover or reset', leading to this recovery handler.
2947 * Manually call the eeh failure check function.
2949 struct eeh_dev *eehdev = pci_dev_to_eeh_dev(efx->pci_dev);
2950 if (eeh_dev_check_failure(eehdev)) {
2951 /* The EEH mechanisms will handle the error and reset the
2952 * device if necessary.
2960 static void efx_wait_for_bist_end(struct efx_nic *efx)
2964 for (i = 0; i < BIST_WAIT_DELAY_COUNT; ++i) {
2965 if (efx_mcdi_poll_reboot(efx))
2967 msleep(BIST_WAIT_DELAY_MS);
2970 netif_err(efx, drv, efx->net_dev, "Warning: No MC reboot after BIST mode\n");
2972 /* Either way unset the BIST flag. If we found no reboot we probably
2973 * won't recover, but we should try.
2975 efx->mc_bist_for_other_fn = false;
2978 /* The worker thread exists so that code that cannot sleep can
2979 * schedule a reset for later.
2981 static void efx_reset_work(struct work_struct *data)
2983 struct efx_nic *efx = container_of(data, struct efx_nic, reset_work);
2984 unsigned long pending;
2985 enum reset_type method;
2987 pending = READ_ONCE(efx->reset_pending);
2988 method = fls(pending) - 1;
2990 if (method == RESET_TYPE_MC_BIST)
2991 efx_wait_for_bist_end(efx);
2993 if ((method == RESET_TYPE_RECOVER_OR_DISABLE ||
2994 method == RESET_TYPE_RECOVER_OR_ALL) &&
2995 efx_try_recovery(efx))
3003 /* We checked the state in efx_schedule_reset() but it may
3004 * have changed by now. Now that we have the RTNL lock,
3005 * it cannot change again.
3007 if (efx->state == STATE_READY)
3008 (void)efx_reset(efx, method);
3013 void efx_schedule_reset(struct efx_nic *efx, enum reset_type type)
3015 enum reset_type method;
3017 if (efx->state == STATE_RECOVERY) {
3018 netif_dbg(efx, drv, efx->net_dev,
3019 "recovering: skip scheduling %s reset\n",
3025 case RESET_TYPE_INVISIBLE:
3026 case RESET_TYPE_ALL:
3027 case RESET_TYPE_RECOVER_OR_ALL:
3028 case RESET_TYPE_WORLD:
3029 case RESET_TYPE_DISABLE:
3030 case RESET_TYPE_RECOVER_OR_DISABLE:
3031 case RESET_TYPE_DATAPATH:
3032 case RESET_TYPE_MC_BIST:
3033 case RESET_TYPE_MCDI_TIMEOUT:
3035 netif_dbg(efx, drv, efx->net_dev, "scheduling %s reset\n",
3036 RESET_TYPE(method));
3039 method = efx->type->map_reset_reason(type);
3040 netif_dbg(efx, drv, efx->net_dev,
3041 "scheduling %s reset for %s\n",
3042 RESET_TYPE(method), RESET_TYPE(type));
3046 set_bit(method, &efx->reset_pending);
3047 smp_mb(); /* ensure we change reset_pending before checking state */
3049 /* If we're not READY then just leave the flags set as the cue
3050 * to abort probing or reschedule the reset later.
3052 if (READ_ONCE(efx->state) != STATE_READY)
3055 /* efx_process_channel() will no longer read events once a
3056 * reset is scheduled. So switch back to poll'd MCDI completions. */
3057 efx_mcdi_mode_poll(efx);
3059 efx_queue_reset_work(efx);
3062 /**************************************************************************
3064 * List of NICs we support
3066 **************************************************************************/
3068 /* PCI device ID table */
3069 static const struct pci_device_id efx_pci_table[] = {
3070 {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE, 0x0803), /* SFC9020 */
3071 .driver_data = (unsigned long) &siena_a0_nic_type},
3072 {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE, 0x0813), /* SFL9021 */
3073 .driver_data = (unsigned long) &siena_a0_nic_type},
3074 {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE, 0x0903), /* SFC9120 PF */
3075 .driver_data = (unsigned long) &efx_hunt_a0_nic_type},
3076 {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE, 0x1903), /* SFC9120 VF */
3077 .driver_data = (unsigned long) &efx_hunt_a0_vf_nic_type},
3078 {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE, 0x0923), /* SFC9140 PF */
3079 .driver_data = (unsigned long) &efx_hunt_a0_nic_type},
3080 {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE, 0x1923), /* SFC9140 VF */
3081 .driver_data = (unsigned long) &efx_hunt_a0_vf_nic_type},
3082 {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE, 0x0a03), /* SFC9220 PF */
3083 .driver_data = (unsigned long) &efx_hunt_a0_nic_type},
3084 {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE, 0x1a03), /* SFC9220 VF */
3085 .driver_data = (unsigned long) &efx_hunt_a0_vf_nic_type},
3086 {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE, 0x0b03), /* SFC9250 PF */
3087 .driver_data = (unsigned long) &efx_hunt_a0_nic_type},
3088 {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE, 0x1b03), /* SFC9250 VF */
3089 .driver_data = (unsigned long) &efx_hunt_a0_vf_nic_type},
3090 {0} /* end of list */
3093 /**************************************************************************
3095 * Dummy PHY/MAC operations
3097 * Can be used for some unimplemented operations
3098 * Needed so all function pointers are valid and do not have to be tested
3101 **************************************************************************/
3102 int efx_port_dummy_op_int(struct efx_nic *efx)
3106 void efx_port_dummy_op_void(struct efx_nic *efx) {}
3108 static bool efx_port_dummy_op_poll(struct efx_nic *efx)
3113 static const struct efx_phy_operations efx_dummy_phy_operations = {
3114 .init = efx_port_dummy_op_int,
3115 .reconfigure = efx_port_dummy_op_int,
3116 .poll = efx_port_dummy_op_poll,
3117 .fini = efx_port_dummy_op_void,
3120 /**************************************************************************
3124 **************************************************************************/
3126 /* This zeroes out and then fills in the invariants in a struct
3127 * efx_nic (including all sub-structures).
3129 int efx_init_struct(struct efx_nic *efx, struct pci_dev *pci_dev,
3130 struct net_device *net_dev)
3132 int rc = -ENOMEM, i;
3134 /* Initialise common structures */
3135 INIT_LIST_HEAD(&efx->node);
3136 INIT_LIST_HEAD(&efx->secondary_list);
3137 spin_lock_init(&efx->biu_lock);
3138 #ifdef CONFIG_SFC_MTD
3139 INIT_LIST_HEAD(&efx->mtd_list);
3141 INIT_WORK(&efx->reset_work, efx_reset_work);
3142 INIT_DELAYED_WORK(&efx->monitor_work, efx_monitor);
3143 INIT_DELAYED_WORK(&efx->selftest_work, efx_selftest_async_work);
3144 efx->pci_dev = pci_dev;
3145 efx->msg_enable = debug;
3146 efx->state = STATE_UNINIT;
3147 strlcpy(efx->name, pci_name(pci_dev), sizeof(efx->name));
3149 efx->net_dev = net_dev;
3150 efx->rx_prefix_size = efx->type->rx_prefix_size;
3152 NET_IP_ALIGN ? (efx->rx_prefix_size + NET_IP_ALIGN) % 4 : 0;
3153 efx->rx_packet_hash_offset =
3154 efx->type->rx_hash_offset - efx->type->rx_prefix_size;
3155 efx->rx_packet_ts_offset =
3156 efx->type->rx_ts_offset - efx->type->rx_prefix_size;
3157 INIT_LIST_HEAD(&efx->rss_context.list);
3158 mutex_init(&efx->rss_lock);
3159 spin_lock_init(&efx->stats_lock);
3160 efx->vi_stride = EFX_DEFAULT_VI_STRIDE;
3161 efx->num_mac_stats = MC_CMD_MAC_NSTATS;
3162 BUILD_BUG_ON(MC_CMD_MAC_NSTATS - 1 != MC_CMD_MAC_GENERATION_END);
3163 mutex_init(&efx->mac_lock);
3164 #ifdef CONFIG_RFS_ACCEL
3165 mutex_init(&efx->rps_mutex);
3166 spin_lock_init(&efx->rps_hash_lock);
3167 /* Failure to allocate is not fatal, but may degrade ARFS performance */
3168 efx->rps_hash_table = kcalloc(EFX_ARFS_HASH_TABLE_SIZE,
3169 sizeof(*efx->rps_hash_table), GFP_KERNEL);
3171 efx->phy_op = &efx_dummy_phy_operations;
3172 efx->mdio.dev = net_dev;
3173 INIT_WORK(&efx->mac_work, efx_mac_work);
3174 init_waitqueue_head(&efx->flush_wq);
3176 for (i = 0; i < EFX_MAX_CHANNELS; i++) {
3177 efx->channel[i] = efx_alloc_channel(efx, i, NULL);
3178 if (!efx->channel[i])
3180 efx->msi_context[i].efx = efx;
3181 efx->msi_context[i].index = i;
3184 /* Higher numbered interrupt modes are less capable! */
3185 if (WARN_ON_ONCE(efx->type->max_interrupt_mode >
3186 efx->type->min_interrupt_mode)) {
3190 efx->interrupt_mode = max(efx->type->max_interrupt_mode,
3192 efx->interrupt_mode = min(efx->type->min_interrupt_mode,
3195 /* Would be good to use the net_dev name, but we're too early */
3196 snprintf(efx->workqueue_name, sizeof(efx->workqueue_name), "sfc%s",
3198 efx->workqueue = create_singlethread_workqueue(efx->workqueue_name);
3199 if (!efx->workqueue)
3205 efx_fini_struct(efx);
3209 void efx_fini_struct(struct efx_nic *efx)
3213 #ifdef CONFIG_RFS_ACCEL
3214 kfree(efx->rps_hash_table);
3217 for (i = 0; i < EFX_MAX_CHANNELS; i++)
3218 kfree(efx->channel[i]);
3222 if (efx->workqueue) {
3223 destroy_workqueue(efx->workqueue);
3224 efx->workqueue = NULL;
3228 void efx_update_sw_stats(struct efx_nic *efx, u64 *stats)
3230 u64 n_rx_nodesc_trunc = 0;
3231 struct efx_channel *channel;
3233 efx_for_each_channel(channel, efx)
3234 n_rx_nodesc_trunc += channel->n_rx_nodesc_trunc;
3235 stats[GENERIC_STAT_rx_nodesc_trunc] = n_rx_nodesc_trunc;
3236 stats[GENERIC_STAT_rx_noskb_drops] = atomic_read(&efx->n_rx_noskb_drops);
3239 bool efx_filter_spec_equal(const struct efx_filter_spec *left,
3240 const struct efx_filter_spec *right)
3242 if ((left->match_flags ^ right->match_flags) |
3243 ((left->flags ^ right->flags) &
3244 (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_TX)))
3247 return memcmp(&left->outer_vid, &right->outer_vid,
3248 sizeof(struct efx_filter_spec) -
3249 offsetof(struct efx_filter_spec, outer_vid)) == 0;
3252 u32 efx_filter_spec_hash(const struct efx_filter_spec *spec)
3254 BUILD_BUG_ON(offsetof(struct efx_filter_spec, outer_vid) & 3);
3255 return jhash2((const u32 *)&spec->outer_vid,
3256 (sizeof(struct efx_filter_spec) -
3257 offsetof(struct efx_filter_spec, outer_vid)) / 4,
3261 #ifdef CONFIG_RFS_ACCEL
3262 bool efx_rps_check_rule(struct efx_arfs_rule *rule, unsigned int filter_idx,
3265 if (rule->filter_id == EFX_ARFS_FILTER_ID_PENDING) {
3266 /* ARFS is currently updating this entry, leave it */
3269 if (rule->filter_id == EFX_ARFS_FILTER_ID_ERROR) {
3270 /* ARFS tried and failed to update this, so it's probably out
3271 * of date. Remove the filter and the ARFS rule entry.
3273 rule->filter_id = EFX_ARFS_FILTER_ID_REMOVING;
3276 } else if (WARN_ON(rule->filter_id != filter_idx)) { /* can't happen */
3277 /* ARFS has moved on, so old filter is not needed. Since we did
3278 * not mark the rule with EFX_ARFS_FILTER_ID_REMOVING, it will
3279 * not be removed by efx_rps_hash_del() subsequently.
3284 /* Remove it iff ARFS wants to. */
3289 struct hlist_head *efx_rps_hash_bucket(struct efx_nic *efx,
3290 const struct efx_filter_spec *spec)
3292 u32 hash = efx_filter_spec_hash(spec);
3294 lockdep_assert_held(&efx->rps_hash_lock);
3295 if (!efx->rps_hash_table)
3297 return &efx->rps_hash_table[hash % EFX_ARFS_HASH_TABLE_SIZE];
3300 struct efx_arfs_rule *efx_rps_hash_find(struct efx_nic *efx,
3301 const struct efx_filter_spec *spec)
3303 struct efx_arfs_rule *rule;
3304 struct hlist_head *head;
3305 struct hlist_node *node;
3307 head = efx_rps_hash_bucket(efx, spec);
3310 hlist_for_each(node, head) {
3311 rule = container_of(node, struct efx_arfs_rule, node);
3312 if (efx_filter_spec_equal(spec, &rule->spec))
3318 struct efx_arfs_rule *efx_rps_hash_add(struct efx_nic *efx,
3319 const struct efx_filter_spec *spec,
3322 struct efx_arfs_rule *rule;
3323 struct hlist_head *head;
3324 struct hlist_node *node;
3326 head = efx_rps_hash_bucket(efx, spec);
3329 hlist_for_each(node, head) {
3330 rule = container_of(node, struct efx_arfs_rule, node);
3331 if (efx_filter_spec_equal(spec, &rule->spec)) {
3336 rule = kmalloc(sizeof(*rule), GFP_ATOMIC);
3339 memcpy(&rule->spec, spec, sizeof(rule->spec));
3340 hlist_add_head(&rule->node, head);
3345 void efx_rps_hash_del(struct efx_nic *efx, const struct efx_filter_spec *spec)
3347 struct efx_arfs_rule *rule;
3348 struct hlist_head *head;
3349 struct hlist_node *node;
3351 head = efx_rps_hash_bucket(efx, spec);
3354 hlist_for_each(node, head) {
3355 rule = container_of(node, struct efx_arfs_rule, node);
3356 if (efx_filter_spec_equal(spec, &rule->spec)) {
3357 /* Someone already reused the entry. We know that if
3358 * this check doesn't fire (i.e. filter_id == REMOVING)
3359 * then the REMOVING mark was put there by our caller,
3360 * because caller is holding a lock on filter table and
3361 * only holders of that lock set REMOVING.
3363 if (rule->filter_id != EFX_ARFS_FILTER_ID_REMOVING)
3370 /* We didn't find it. */
3375 /* RSS contexts. We're using linked lists and crappy O(n) algorithms, because
3376 * (a) this is an infrequent control-plane operation and (b) n is small (max 64)
3378 struct efx_rss_context *efx_alloc_rss_context_entry(struct efx_nic *efx)
3380 struct list_head *head = &efx->rss_context.list;
3381 struct efx_rss_context *ctx, *new;
3382 u32 id = 1; /* Don't use zero, that refers to the master RSS context */
3384 WARN_ON(!mutex_is_locked(&efx->rss_lock));
3386 /* Search for first gap in the numbering */
3387 list_for_each_entry(ctx, head, list) {
3388 if (ctx->user_id != id)
3391 /* Check for wrap. If this happens, we have nearly 2^32
3392 * allocated RSS contexts, which seems unlikely.
3394 if (WARN_ON_ONCE(!id))
3398 /* Create the new entry */
3399 new = kmalloc(sizeof(struct efx_rss_context), GFP_KERNEL);
3402 new->context_id = EFX_EF10_RSS_CONTEXT_INVALID;
3403 new->rx_hash_udp_4tuple = false;
3405 /* Insert the new entry into the gap */
3407 list_add_tail(&new->list, &ctx->list);
3411 struct efx_rss_context *efx_find_rss_context_entry(struct efx_nic *efx, u32 id)
3413 struct list_head *head = &efx->rss_context.list;
3414 struct efx_rss_context *ctx;
3416 WARN_ON(!mutex_is_locked(&efx->rss_lock));
3418 list_for_each_entry(ctx, head, list)
3419 if (ctx->user_id == id)
3424 void efx_free_rss_context_entry(struct efx_rss_context *ctx)
3426 list_del(&ctx->list);
3430 /**************************************************************************
3434 **************************************************************************/
3436 /* Main body of final NIC shutdown code
3437 * This is called only at module unload (or hotplug removal).
3439 static void efx_pci_remove_main(struct efx_nic *efx)
3441 /* Flush reset_work. It can no longer be scheduled since we
3444 BUG_ON(efx->state == STATE_READY);
3445 efx_flush_reset_workqueue(efx);
3447 efx_disable_interrupts(efx);
3448 efx_clear_interrupt_affinity(efx);
3449 efx_nic_fini_interrupt(efx);
3451 efx->type->fini(efx);
3453 efx_remove_all(efx);
3456 /* Final NIC shutdown
3457 * This is called only at module unload (or hotplug removal). A PF can call
3458 * this on its VFs to ensure they are unbound first.
3460 static void efx_pci_remove(struct pci_dev *pci_dev)
3462 struct efx_nic *efx;
3464 efx = pci_get_drvdata(pci_dev);
3468 /* Mark the NIC as fini, then stop the interface */
3470 efx_dissociate(efx);
3471 dev_close(efx->net_dev);
3472 efx_disable_interrupts(efx);
3473 efx->state = STATE_UNINIT;
3476 if (efx->type->sriov_fini)
3477 efx->type->sriov_fini(efx);
3479 efx_unregister_netdev(efx);
3481 efx_mtd_remove(efx);
3483 efx_pci_remove_main(efx);
3485 efx_fini_io(efx, efx->type->mem_bar(efx));
3486 netif_dbg(efx, drv, efx->net_dev, "shutdown successful\n");
3488 efx_fini_struct(efx);
3489 free_netdev(efx->net_dev);
3491 pci_disable_pcie_error_reporting(pci_dev);
3494 /* NIC VPD information
3495 * Called during probe to display the part number of the
3496 * installed NIC. VPD is potentially very large but this should
3497 * always appear within the first 512 bytes.
3499 #define SFC_VPD_LEN 512
3500 static void efx_probe_vpd_strings(struct efx_nic *efx)
3502 struct pci_dev *dev = efx->pci_dev;
3503 char vpd_data[SFC_VPD_LEN];
3505 int ro_start, ro_size, i, j;
3507 /* Get the vpd data from the device */
3508 vpd_size = pci_read_vpd(dev, 0, sizeof(vpd_data), vpd_data);
3509 if (vpd_size <= 0) {
3510 netif_err(efx, drv, efx->net_dev, "Unable to read VPD\n");
3514 /* Get the Read only section */
3515 ro_start = pci_vpd_find_tag(vpd_data, 0, vpd_size, PCI_VPD_LRDT_RO_DATA);
3517 netif_err(efx, drv, efx->net_dev, "VPD Read-only not found\n");
3521 ro_size = pci_vpd_lrdt_size(&vpd_data[ro_start]);
3523 i = ro_start + PCI_VPD_LRDT_TAG_SIZE;
3524 if (i + j > vpd_size)
3527 /* Get the Part number */
3528 i = pci_vpd_find_info_keyword(vpd_data, i, j, "PN");
3530 netif_err(efx, drv, efx->net_dev, "Part number not found\n");
3534 j = pci_vpd_info_field_size(&vpd_data[i]);
3535 i += PCI_VPD_INFO_FLD_HDR_SIZE;
3536 if (i + j > vpd_size) {
3537 netif_err(efx, drv, efx->net_dev, "Incomplete part number\n");
3541 netif_info(efx, drv, efx->net_dev,
3542 "Part Number : %.*s\n", j, &vpd_data[i]);
3544 i = ro_start + PCI_VPD_LRDT_TAG_SIZE;
3546 i = pci_vpd_find_info_keyword(vpd_data, i, j, "SN");
3548 netif_err(efx, drv, efx->net_dev, "Serial number not found\n");
3552 j = pci_vpd_info_field_size(&vpd_data[i]);
3553 i += PCI_VPD_INFO_FLD_HDR_SIZE;
3554 if (i + j > vpd_size) {
3555 netif_err(efx, drv, efx->net_dev, "Incomplete serial number\n");
3559 efx->vpd_sn = kmalloc(j + 1, GFP_KERNEL);
3563 snprintf(efx->vpd_sn, j + 1, "%s", &vpd_data[i]);
3567 /* Main body of NIC initialisation
3568 * This is called at module load (or hotplug insertion, theoretically).
3570 static int efx_pci_probe_main(struct efx_nic *efx)
3574 /* Do start-of-day initialisation */
3575 rc = efx_probe_all(efx);
3581 down_write(&efx->filter_sem);
3582 rc = efx->type->init(efx);
3583 up_write(&efx->filter_sem);
3585 netif_err(efx, probe, efx->net_dev,
3586 "failed to initialise NIC\n");
3590 rc = efx_init_port(efx);
3592 netif_err(efx, probe, efx->net_dev,
3593 "failed to initialise port\n");
3597 rc = efx_nic_init_interrupt(efx);
3601 efx_set_interrupt_affinity(efx);
3602 rc = efx_enable_interrupts(efx);
3609 efx_clear_interrupt_affinity(efx);
3610 efx_nic_fini_interrupt(efx);
3614 efx->type->fini(efx);
3617 efx_remove_all(efx);
3622 static int efx_pci_probe_post_io(struct efx_nic *efx)
3624 struct net_device *net_dev = efx->net_dev;
3625 int rc = efx_pci_probe_main(efx);
3630 if (efx->type->sriov_init) {
3631 rc = efx->type->sriov_init(efx);
3633 netif_err(efx, probe, efx->net_dev,
3634 "SR-IOV can't be enabled rc %d\n", rc);
3637 /* Determine netdevice features */
3638 net_dev->features |= (efx->type->offload_features | NETIF_F_SG |
3639 NETIF_F_TSO | NETIF_F_RXCSUM | NETIF_F_RXALL);
3640 if (efx->type->offload_features & (NETIF_F_IPV6_CSUM | NETIF_F_HW_CSUM))
3641 net_dev->features |= NETIF_F_TSO6;
3642 /* Check whether device supports TSO */
3643 if (!efx->type->tso_versions || !efx->type->tso_versions(efx))
3644 net_dev->features &= ~NETIF_F_ALL_TSO;
3645 /* Mask for features that also apply to VLAN devices */
3646 net_dev->vlan_features |= (NETIF_F_HW_CSUM | NETIF_F_SG |
3647 NETIF_F_HIGHDMA | NETIF_F_ALL_TSO |
3650 net_dev->hw_features |= net_dev->features & ~efx->fixed_features;
3652 /* Disable receiving frames with bad FCS, by default. */
3653 net_dev->features &= ~NETIF_F_RXALL;
3655 /* Disable VLAN filtering by default. It may be enforced if
3656 * the feature is fixed (i.e. VLAN filters are required to
3657 * receive VLAN tagged packets due to vPort restrictions).
3659 net_dev->features &= ~NETIF_F_HW_VLAN_CTAG_FILTER;
3660 net_dev->features |= efx->fixed_features;
3662 rc = efx_register_netdev(efx);
3666 efx_pci_remove_main(efx);
3670 /* NIC initialisation
3672 * This is called at module load (or hotplug insertion,
3673 * theoretically). It sets up PCI mappings, resets the NIC,
3674 * sets up and registers the network devices with the kernel and hooks
3675 * the interrupt service routine. It does not prepare the device for
3676 * transmission; this is left to the first time one of the network
3677 * interfaces is brought up (i.e. efx_net_open).
3679 static int efx_pci_probe(struct pci_dev *pci_dev,
3680 const struct pci_device_id *entry)
3682 struct net_device *net_dev;
3683 struct efx_nic *efx;
3686 /* Allocate and initialise a struct net_device and struct efx_nic */
3687 net_dev = alloc_etherdev_mqs(sizeof(*efx), EFX_MAX_CORE_TX_QUEUES,
3691 efx = netdev_priv(net_dev);
3692 efx->type = (const struct efx_nic_type *) entry->driver_data;
3693 efx->fixed_features |= NETIF_F_HIGHDMA;
3695 pci_set_drvdata(pci_dev, efx);
3696 SET_NETDEV_DEV(net_dev, &pci_dev->dev);
3697 rc = efx_init_struct(efx, pci_dev, net_dev);
3701 netif_info(efx, probe, efx->net_dev,
3702 "Solarflare NIC detected\n");
3704 if (!efx->type->is_vf)
3705 efx_probe_vpd_strings(efx);
3707 /* Set up basic I/O (BAR mappings etc) */
3708 rc = efx_init_io(efx, efx->type->mem_bar(efx), efx->type->max_dma_mask,
3709 efx->type->mem_map_size(efx));
3713 rc = efx_pci_probe_post_io(efx);
3715 /* On failure, retry once immediately.
3716 * If we aborted probe due to a scheduled reset, dismiss it.
3718 efx->reset_pending = 0;
3719 rc = efx_pci_probe_post_io(efx);
3721 /* On another failure, retry once more
3722 * after a 50-305ms delay.
3726 get_random_bytes(&r, 1);
3727 msleep((unsigned int)r + 50);
3728 efx->reset_pending = 0;
3729 rc = efx_pci_probe_post_io(efx);
3735 netif_dbg(efx, probe, efx->net_dev, "initialisation successful\n");
3737 /* Try to create MTDs, but allow this to fail */
3739 rc = efx_mtd_probe(efx);
3741 if (rc && rc != -EPERM)
3742 netif_warn(efx, probe, efx->net_dev,
3743 "failed to create MTDs (%d)\n", rc);
3745 (void)pci_enable_pcie_error_reporting(pci_dev);
3747 if (efx->type->udp_tnl_push_ports)
3748 efx->type->udp_tnl_push_ports(efx);
3753 efx_fini_io(efx, efx->type->mem_bar(efx));
3755 efx_fini_struct(efx);
3758 netif_dbg(efx, drv, efx->net_dev, "initialisation failed. rc=%d\n", rc);
3759 free_netdev(net_dev);
3763 /* efx_pci_sriov_configure returns the actual number of Virtual Functions
3764 * enabled on success
3766 #ifdef CONFIG_SFC_SRIOV
3767 static int efx_pci_sriov_configure(struct pci_dev *dev, int num_vfs)
3770 struct efx_nic *efx = pci_get_drvdata(dev);
3772 if (efx->type->sriov_configure) {
3773 rc = efx->type->sriov_configure(efx, num_vfs);
3783 static int efx_pm_freeze(struct device *dev)
3785 struct efx_nic *efx = dev_get_drvdata(dev);
3789 if (efx->state != STATE_DISABLED) {
3790 efx->state = STATE_UNINIT;
3792 efx_device_detach_sync(efx);
3795 efx_disable_interrupts(efx);
3803 static int efx_pm_thaw(struct device *dev)
3806 struct efx_nic *efx = dev_get_drvdata(dev);
3810 if (efx->state != STATE_DISABLED) {
3811 rc = efx_enable_interrupts(efx);
3815 mutex_lock(&efx->mac_lock);
3816 efx->phy_op->reconfigure(efx);
3817 mutex_unlock(&efx->mac_lock);
3821 efx_device_attach_if_not_resetting(efx);
3823 efx->state = STATE_READY;
3825 efx->type->resume_wol(efx);
3830 /* Reschedule any quenched resets scheduled during efx_pm_freeze() */
3831 efx_queue_reset_work(efx);
3841 static int efx_pm_poweroff(struct device *dev)
3843 struct pci_dev *pci_dev = to_pci_dev(dev);
3844 struct efx_nic *efx = pci_get_drvdata(pci_dev);
3846 efx->type->fini(efx);
3848 efx->reset_pending = 0;
3850 pci_save_state(pci_dev);
3851 return pci_set_power_state(pci_dev, PCI_D3hot);
3854 /* Used for both resume and restore */
3855 static int efx_pm_resume(struct device *dev)
3857 struct pci_dev *pci_dev = to_pci_dev(dev);
3858 struct efx_nic *efx = pci_get_drvdata(pci_dev);
3861 rc = pci_set_power_state(pci_dev, PCI_D0);
3864 pci_restore_state(pci_dev);
3865 rc = pci_enable_device(pci_dev);
3868 pci_set_master(efx->pci_dev);
3869 rc = efx->type->reset(efx, RESET_TYPE_ALL);
3872 down_write(&efx->filter_sem);
3873 rc = efx->type->init(efx);
3874 up_write(&efx->filter_sem);
3877 rc = efx_pm_thaw(dev);
3881 static int efx_pm_suspend(struct device *dev)
3886 rc = efx_pm_poweroff(dev);
3892 static const struct dev_pm_ops efx_pm_ops = {
3893 .suspend = efx_pm_suspend,
3894 .resume = efx_pm_resume,
3895 .freeze = efx_pm_freeze,
3896 .thaw = efx_pm_thaw,
3897 .poweroff = efx_pm_poweroff,
3898 .restore = efx_pm_resume,
3901 /* A PCI error affecting this device was detected.
3902 * At this point MMIO and DMA may be disabled.
3903 * Stop the software path and request a slot reset.
3905 static pci_ers_result_t efx_io_error_detected(struct pci_dev *pdev,
3906 enum pci_channel_state state)
3908 pci_ers_result_t status = PCI_ERS_RESULT_RECOVERED;
3909 struct efx_nic *efx = pci_get_drvdata(pdev);
3911 if (state == pci_channel_io_perm_failure)
3912 return PCI_ERS_RESULT_DISCONNECT;
3916 if (efx->state != STATE_DISABLED) {
3917 efx->state = STATE_RECOVERY;
3918 efx->reset_pending = 0;
3920 efx_device_detach_sync(efx);
3923 efx_disable_interrupts(efx);
3925 status = PCI_ERS_RESULT_NEED_RESET;
3927 /* If the interface is disabled we don't want to do anything
3930 status = PCI_ERS_RESULT_RECOVERED;
3935 pci_disable_device(pdev);
3940 /* Fake a successful reset, which will be performed later in efx_io_resume. */
3941 static pci_ers_result_t efx_io_slot_reset(struct pci_dev *pdev)
3943 struct efx_nic *efx = pci_get_drvdata(pdev);
3944 pci_ers_result_t status = PCI_ERS_RESULT_RECOVERED;
3946 if (pci_enable_device(pdev)) {
3947 netif_err(efx, hw, efx->net_dev,
3948 "Cannot re-enable PCI device after reset.\n");
3949 status = PCI_ERS_RESULT_DISCONNECT;
3955 /* Perform the actual reset and resume I/O operations. */
3956 static void efx_io_resume(struct pci_dev *pdev)
3958 struct efx_nic *efx = pci_get_drvdata(pdev);
3963 if (efx->state == STATE_DISABLED)
3966 rc = efx_reset(efx, RESET_TYPE_ALL);
3968 netif_err(efx, hw, efx->net_dev,
3969 "efx_reset failed after PCI error (%d)\n", rc);
3971 efx->state = STATE_READY;
3972 netif_dbg(efx, hw, efx->net_dev,
3973 "Done resetting and resuming IO after PCI error.\n");
3980 /* For simplicity and reliability, we always require a slot reset and try to
3981 * reset the hardware when a pci error affecting the device is detected.
3982 * We leave both the link_reset and mmio_enabled callback unimplemented:
3983 * with our request for slot reset the mmio_enabled callback will never be
3984 * called, and the link_reset callback is not used by AER or EEH mechanisms.
3986 static const struct pci_error_handlers efx_err_handlers = {
3987 .error_detected = efx_io_error_detected,
3988 .slot_reset = efx_io_slot_reset,
3989 .resume = efx_io_resume,
3992 static struct pci_driver efx_pci_driver = {
3993 .name = KBUILD_MODNAME,
3994 .id_table = efx_pci_table,
3995 .probe = efx_pci_probe,
3996 .remove = efx_pci_remove,
3997 .driver.pm = &efx_pm_ops,
3998 .err_handler = &efx_err_handlers,
3999 #ifdef CONFIG_SFC_SRIOV
4000 .sriov_configure = efx_pci_sriov_configure,
4004 /**************************************************************************
4006 * Kernel module interface
4008 *************************************************************************/
4010 module_param(interrupt_mode, uint, 0444);
4011 MODULE_PARM_DESC(interrupt_mode,
4012 "Interrupt mode (0=>MSIX 1=>MSI 2=>legacy)");
4014 static int __init efx_init_module(void)
4018 printk(KERN_INFO "Solarflare NET driver v" EFX_DRIVER_VERSION "\n");
4020 rc = register_netdevice_notifier(&efx_netdev_notifier);
4024 #ifdef CONFIG_SFC_SRIOV
4025 rc = efx_init_sriov();
4030 rc = efx_create_reset_workqueue();
4034 rc = pci_register_driver(&efx_pci_driver);
4041 efx_destroy_reset_workqueue();
4043 #ifdef CONFIG_SFC_SRIOV
4047 unregister_netdevice_notifier(&efx_netdev_notifier);
4052 static void __exit efx_exit_module(void)
4054 printk(KERN_INFO "Solarflare NET driver unloading\n");
4056 pci_unregister_driver(&efx_pci_driver);
4057 efx_destroy_reset_workqueue();
4058 #ifdef CONFIG_SFC_SRIOV
4061 unregister_netdevice_notifier(&efx_netdev_notifier);
4065 module_init(efx_init_module);
4066 module_exit(efx_exit_module);
4068 MODULE_AUTHOR("Solarflare Communications and "
4069 "Michael Brown <mbrown@fensystems.co.uk>");
4070 MODULE_DESCRIPTION("Solarflare network driver");
4071 MODULE_LICENSE("GPL");
4072 MODULE_DEVICE_TABLE(pci, efx_pci_table);
4073 MODULE_VERSION(EFX_DRIVER_VERSION);