1 /****************************************************************************
2 * Driver for Solarflare network controllers and boards
3 * Copyright 2005-2006 Fen Systems Ltd.
4 * Copyright 2006-2013 Solarflare Communications Inc.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation, incorporated herein by reference.
15 #include <linux/spinlock.h>
17 /**************************************************************************
21 **************************************************************************
23 * Notes on locking strategy for the Falcon architecture:
25 * Many CSRs are very wide and cannot be read or written atomically.
26 * Writes from the host are buffered by the Bus Interface Unit (BIU)
27 * up to 128 bits. Whenever the host writes part of such a register,
28 * the BIU collects the written value and does not write to the
29 * underlying register until all 4 dwords have been written. A
30 * similar buffering scheme applies to host access to the NIC's 64-bit
33 * Writes to different CSRs and 64-bit SRAM words must be serialised,
34 * since interleaved access can result in lost writes. We use
35 * ef4_nic::biu_lock for this.
37 * We also serialise reads from 128-bit CSRs and SRAM with the same
38 * spinlock. This may not be necessary, but it doesn't really matter
39 * as there are no such reads on the fast path.
41 * The DMA descriptor pointers (RX_DESC_UPD and TX_DESC_UPD) are
42 * 128-bit but are special-cased in the BIU to avoid the need for
43 * locking in the host:
45 * - They are write-only.
46 * - The semantics of writing to these registers are such that
47 * replacing the low 96 bits with zero does not affect functionality.
48 * - If the host writes to the last dword address of such a register
49 * (i.e. the high 32 bits) the underlying register will always be
50 * written. If the collector and the current write together do not
51 * provide values for all 128 bits of the register, the low 96 bits
52 * will be written as zero.
53 * - If the host writes to the address of any other part of such a
54 * register while the collector already holds values for some other
55 * register, the write is discarded and the collector maintains its
58 * The EF10 architecture exposes very few registers to the host and
59 * most of them are only 32 bits wide. The only exceptions are the MC
60 * doorbell register pair, which has its own latching, and
61 * TX_DESC_UPD, which works in a similar way to the Falcon
65 #if BITS_PER_LONG == 64
66 #define EF4_USE_QWORD_IO 1
69 #ifdef EF4_USE_QWORD_IO
70 static inline void _ef4_writeq(struct ef4_nic *efx, __le64 value,
73 __raw_writeq((__force u64)value, efx->membase + reg);
75 static inline __le64 _ef4_readq(struct ef4_nic *efx, unsigned int reg)
77 return (__force __le64)__raw_readq(efx->membase + reg);
81 static inline void _ef4_writed(struct ef4_nic *efx, __le32 value,
84 __raw_writel((__force u32)value, efx->membase + reg);
86 static inline __le32 _ef4_readd(struct ef4_nic *efx, unsigned int reg)
88 return (__force __le32)__raw_readl(efx->membase + reg);
91 /* Write a normal 128-bit CSR, locking as appropriate. */
92 static inline void ef4_writeo(struct ef4_nic *efx, const ef4_oword_t *value,
95 unsigned long flags __attribute__ ((unused));
97 netif_vdbg(efx, hw, efx->net_dev,
98 "writing register %x with " EF4_OWORD_FMT "\n", reg,
99 EF4_OWORD_VAL(*value));
101 spin_lock_irqsave(&efx->biu_lock, flags);
102 #ifdef EF4_USE_QWORD_IO
103 _ef4_writeq(efx, value->u64[0], reg + 0);
104 _ef4_writeq(efx, value->u64[1], reg + 8);
106 _ef4_writed(efx, value->u32[0], reg + 0);
107 _ef4_writed(efx, value->u32[1], reg + 4);
108 _ef4_writed(efx, value->u32[2], reg + 8);
109 _ef4_writed(efx, value->u32[3], reg + 12);
111 spin_unlock_irqrestore(&efx->biu_lock, flags);
114 /* Write 64-bit SRAM through the supplied mapping, locking as appropriate. */
115 static inline void ef4_sram_writeq(struct ef4_nic *efx, void __iomem *membase,
116 const ef4_qword_t *value, unsigned int index)
118 unsigned int addr = index * sizeof(*value);
119 unsigned long flags __attribute__ ((unused));
121 netif_vdbg(efx, hw, efx->net_dev,
122 "writing SRAM address %x with " EF4_QWORD_FMT "\n",
123 addr, EF4_QWORD_VAL(*value));
125 spin_lock_irqsave(&efx->biu_lock, flags);
126 #ifdef EF4_USE_QWORD_IO
127 __raw_writeq((__force u64)value->u64[0], membase + addr);
129 __raw_writel((__force u32)value->u32[0], membase + addr);
130 __raw_writel((__force u32)value->u32[1], membase + addr + 4);
132 spin_unlock_irqrestore(&efx->biu_lock, flags);
135 /* Write a 32-bit CSR or the last dword of a special 128-bit CSR */
136 static inline void ef4_writed(struct ef4_nic *efx, const ef4_dword_t *value,
139 netif_vdbg(efx, hw, efx->net_dev,
140 "writing register %x with "EF4_DWORD_FMT"\n",
141 reg, EF4_DWORD_VAL(*value));
143 /* No lock required */
144 _ef4_writed(efx, value->u32[0], reg);
147 /* Read a 128-bit CSR, locking as appropriate. */
148 static inline void ef4_reado(struct ef4_nic *efx, ef4_oword_t *value,
151 unsigned long flags __attribute__ ((unused));
153 spin_lock_irqsave(&efx->biu_lock, flags);
154 value->u32[0] = _ef4_readd(efx, reg + 0);
155 value->u32[1] = _ef4_readd(efx, reg + 4);
156 value->u32[2] = _ef4_readd(efx, reg + 8);
157 value->u32[3] = _ef4_readd(efx, reg + 12);
158 spin_unlock_irqrestore(&efx->biu_lock, flags);
160 netif_vdbg(efx, hw, efx->net_dev,
161 "read from register %x, got " EF4_OWORD_FMT "\n", reg,
162 EF4_OWORD_VAL(*value));
165 /* Read 64-bit SRAM through the supplied mapping, locking as appropriate. */
166 static inline void ef4_sram_readq(struct ef4_nic *efx, void __iomem *membase,
167 ef4_qword_t *value, unsigned int index)
169 unsigned int addr = index * sizeof(*value);
170 unsigned long flags __attribute__ ((unused));
172 spin_lock_irqsave(&efx->biu_lock, flags);
173 #ifdef EF4_USE_QWORD_IO
174 value->u64[0] = (__force __le64)__raw_readq(membase + addr);
176 value->u32[0] = (__force __le32)__raw_readl(membase + addr);
177 value->u32[1] = (__force __le32)__raw_readl(membase + addr + 4);
179 spin_unlock_irqrestore(&efx->biu_lock, flags);
181 netif_vdbg(efx, hw, efx->net_dev,
182 "read from SRAM address %x, got "EF4_QWORD_FMT"\n",
183 addr, EF4_QWORD_VAL(*value));
186 /* Read a 32-bit CSR or SRAM */
187 static inline void ef4_readd(struct ef4_nic *efx, ef4_dword_t *value,
190 value->u32[0] = _ef4_readd(efx, reg);
191 netif_vdbg(efx, hw, efx->net_dev,
192 "read from register %x, got "EF4_DWORD_FMT"\n",
193 reg, EF4_DWORD_VAL(*value));
196 /* Write a 128-bit CSR forming part of a table */
198 ef4_writeo_table(struct ef4_nic *efx, const ef4_oword_t *value,
199 unsigned int reg, unsigned int index)
201 ef4_writeo(efx, value, reg + index * sizeof(ef4_oword_t));
204 /* Read a 128-bit CSR forming part of a table */
205 static inline void ef4_reado_table(struct ef4_nic *efx, ef4_oword_t *value,
206 unsigned int reg, unsigned int index)
208 ef4_reado(efx, value, reg + index * sizeof(ef4_oword_t));
211 /* Page size used as step between per-VI registers */
212 #define EF4_VI_PAGE_SIZE 0x2000
214 /* Calculate offset to page-mapped register */
215 #define EF4_PAGED_REG(page, reg) \
216 ((page) * EF4_VI_PAGE_SIZE + (reg))
218 /* Write the whole of RX_DESC_UPD or TX_DESC_UPD */
219 static inline void _ef4_writeo_page(struct ef4_nic *efx, ef4_oword_t *value,
220 unsigned int reg, unsigned int page)
222 reg = EF4_PAGED_REG(page, reg);
224 netif_vdbg(efx, hw, efx->net_dev,
225 "writing register %x with " EF4_OWORD_FMT "\n", reg,
226 EF4_OWORD_VAL(*value));
228 #ifdef EF4_USE_QWORD_IO
229 _ef4_writeq(efx, value->u64[0], reg + 0);
230 _ef4_writeq(efx, value->u64[1], reg + 8);
232 _ef4_writed(efx, value->u32[0], reg + 0);
233 _ef4_writed(efx, value->u32[1], reg + 4);
234 _ef4_writed(efx, value->u32[2], reg + 8);
235 _ef4_writed(efx, value->u32[3], reg + 12);
238 #define ef4_writeo_page(efx, value, reg, page) \
239 _ef4_writeo_page(efx, value, \
241 BUILD_BUG_ON_ZERO((reg) != 0x830 && (reg) != 0xa10), \
244 /* Write a page-mapped 32-bit CSR (EVQ_RPTR, EVQ_TMR (EF10), or the
245 * high bits of RX_DESC_UPD or TX_DESC_UPD)
248 _ef4_writed_page(struct ef4_nic *efx, const ef4_dword_t *value,
249 unsigned int reg, unsigned int page)
251 ef4_writed(efx, value, EF4_PAGED_REG(page, reg));
253 #define ef4_writed_page(efx, value, reg, page) \
254 _ef4_writed_page(efx, value, \
256 BUILD_BUG_ON_ZERO((reg) != 0x400 && \
264 /* Write TIMER_COMMAND. This is a page-mapped 32-bit CSR, but a bug
265 * in the BIU means that writes to TIMER_COMMAND[0] invalidate the
266 * collector register.
268 static inline void _ef4_writed_page_locked(struct ef4_nic *efx,
269 const ef4_dword_t *value,
273 unsigned long flags __attribute__ ((unused));
276 spin_lock_irqsave(&efx->biu_lock, flags);
277 ef4_writed(efx, value, EF4_PAGED_REG(page, reg));
278 spin_unlock_irqrestore(&efx->biu_lock, flags);
280 ef4_writed(efx, value, EF4_PAGED_REG(page, reg));
283 #define ef4_writed_page_locked(efx, value, reg, page) \
284 _ef4_writed_page_locked(efx, value, \
285 reg + BUILD_BUG_ON_ZERO((reg) != 0x420), \
288 #endif /* EF4_IO_H */