1 // SPDX-License-Identifier: GPL-2.0-only
2 /****************************************************************************
3 * Driver for Solarflare network controllers and boards
4 * Copyright 2005-2006 Fen Systems Ltd.
5 * Copyright 2005-2013 Solarflare Communications Inc.
12 #include <linux/ipv6.h>
13 #include <linux/slab.h>
15 #include <linux/if_ether.h>
16 #include <linux/highmem.h>
17 #include <linux/cache.h>
18 #include "net_driver.h"
23 #include "tx_common.h"
24 #include "workarounds.h"
25 #include "ef10_regs.h"
29 #define EFX_PIOBUF_SIZE_DEF ALIGN(256, L1_CACHE_BYTES)
30 unsigned int efx_piobuf_size __read_mostly = EFX_PIOBUF_SIZE_DEF;
32 #endif /* EFX_USE_PIO */
34 static inline u8 *efx_tx_get_copy_buffer(struct efx_tx_queue *tx_queue,
35 struct efx_tx_buffer *buffer)
37 unsigned int index = efx_tx_queue_get_insert_index(tx_queue);
38 struct efx_buffer *page_buf =
39 &tx_queue->cb_page[index >> (PAGE_SHIFT - EFX_TX_CB_ORDER)];
41 ((index << EFX_TX_CB_ORDER) + NET_IP_ALIGN) & (PAGE_SIZE - 1);
43 if (unlikely(!page_buf->addr) &&
44 efx_nic_alloc_buffer(tx_queue->efx, page_buf, PAGE_SIZE,
47 buffer->dma_addr = page_buf->dma_addr + offset;
48 buffer->unmap_len = 0;
49 return (u8 *)page_buf->addr + offset;
52 u8 *efx_tx_get_copy_buffer_limited(struct efx_tx_queue *tx_queue,
53 struct efx_tx_buffer *buffer, size_t len)
55 if (len > EFX_TX_CB_SIZE)
57 return efx_tx_get_copy_buffer(tx_queue, buffer);
60 void efx_dequeue_buffer(struct efx_tx_queue *tx_queue,
61 struct efx_tx_buffer *buffer,
62 unsigned int *pkts_compl,
63 unsigned int *bytes_compl)
65 if (buffer->unmap_len) {
66 struct device *dma_dev = &tx_queue->efx->pci_dev->dev;
67 dma_addr_t unmap_addr = buffer->dma_addr - buffer->dma_offset;
68 if (buffer->flags & EFX_TX_BUF_MAP_SINGLE)
69 dma_unmap_single(dma_dev, unmap_addr, buffer->unmap_len,
72 dma_unmap_page(dma_dev, unmap_addr, buffer->unmap_len,
74 buffer->unmap_len = 0;
77 if (buffer->flags & EFX_TX_BUF_SKB) {
78 struct sk_buff *skb = (struct sk_buff *)buffer->skb;
80 EFX_WARN_ON_PARANOID(!pkts_compl || !bytes_compl);
82 (*bytes_compl) += skb->len;
83 if (tx_queue->timestamping &&
84 (tx_queue->completed_timestamp_major ||
85 tx_queue->completed_timestamp_minor)) {
86 struct skb_shared_hwtstamps hwtstamp;
89 efx_ptp_nic_to_kernel_time(tx_queue);
90 skb_tstamp_tx(skb, &hwtstamp);
92 tx_queue->completed_timestamp_major = 0;
93 tx_queue->completed_timestamp_minor = 0;
95 dev_consume_skb_any((struct sk_buff *)buffer->skb);
96 netif_vdbg(tx_queue->efx, tx_done, tx_queue->efx->net_dev,
97 "TX queue %d transmission id %x complete\n",
98 tx_queue->queue, tx_queue->read_count);
99 } else if (buffer->flags & EFX_TX_BUF_XDP) {
100 xdp_return_frame_rx_napi(buffer->xdpf);
107 unsigned int efx_tx_max_skb_descs(struct efx_nic *efx)
109 /* Header and payload descriptor for each output segment, plus
110 * one for every input fragment boundary within a segment
112 unsigned int max_descs = EFX_TSO_MAX_SEGS * 2 + MAX_SKB_FRAGS;
114 /* Possibly one more per segment for option descriptors */
115 if (efx_nic_rev(efx) >= EFX_REV_HUNT_A0)
116 max_descs += EFX_TSO_MAX_SEGS;
118 /* Possibly more for PCIe page boundaries within input fragments */
119 if (PAGE_SIZE > EFX_PAGE_SIZE)
120 max_descs += max_t(unsigned int, MAX_SKB_FRAGS,
121 DIV_ROUND_UP(GSO_MAX_SIZE, EFX_PAGE_SIZE));
126 static void efx_tx_maybe_stop_queue(struct efx_tx_queue *txq1)
128 /* We need to consider both queues that the net core sees as one */
129 struct efx_tx_queue *txq2 = efx_tx_queue_partner(txq1);
130 struct efx_nic *efx = txq1->efx;
131 unsigned int fill_level;
133 fill_level = max(txq1->insert_count - txq1->old_read_count,
134 txq2->insert_count - txq2->old_read_count);
135 if (likely(fill_level < efx->txq_stop_thresh))
138 /* We used the stale old_read_count above, which gives us a
139 * pessimistic estimate of the fill level (which may even
140 * validly be >= efx->txq_entries). Now try again using
141 * read_count (more likely to be a cache miss).
143 * If we read read_count and then conditionally stop the
144 * queue, it is possible for the completion path to race with
145 * us and complete all outstanding descriptors in the middle,
146 * after which there will be no more completions to wake it.
147 * Therefore we stop the queue first, then read read_count
148 * (with a memory barrier to ensure the ordering), then
149 * restart the queue if the fill level turns out to be low
152 netif_tx_stop_queue(txq1->core_txq);
154 txq1->old_read_count = READ_ONCE(txq1->read_count);
155 txq2->old_read_count = READ_ONCE(txq2->read_count);
157 fill_level = max(txq1->insert_count - txq1->old_read_count,
158 txq2->insert_count - txq2->old_read_count);
159 EFX_WARN_ON_ONCE_PARANOID(fill_level >= efx->txq_entries);
160 if (likely(fill_level < efx->txq_stop_thresh)) {
162 if (likely(!efx->loopback_selftest))
163 netif_tx_start_queue(txq1->core_txq);
167 static int efx_enqueue_skb_copy(struct efx_tx_queue *tx_queue,
170 unsigned int copy_len = skb->len;
171 struct efx_tx_buffer *buffer;
175 EFX_WARN_ON_ONCE_PARANOID(copy_len > EFX_TX_CB_SIZE);
177 buffer = efx_tx_queue_get_insert_buffer(tx_queue);
179 copy_buffer = efx_tx_get_copy_buffer(tx_queue, buffer);
180 if (unlikely(!copy_buffer))
183 rc = skb_copy_bits(skb, 0, copy_buffer, copy_len);
184 EFX_WARN_ON_PARANOID(rc);
185 buffer->len = copy_len;
188 buffer->flags = EFX_TX_BUF_SKB;
190 ++tx_queue->insert_count;
196 struct efx_short_copy_buffer {
198 u8 buf[L1_CACHE_BYTES];
201 /* Copy to PIO, respecting that writes to PIO buffers must be dword aligned.
202 * Advances piobuf pointer. Leaves additional data in the copy buffer.
204 static void efx_memcpy_toio_aligned(struct efx_nic *efx, u8 __iomem **piobuf,
206 struct efx_short_copy_buffer *copy_buf)
208 int block_len = len & ~(sizeof(copy_buf->buf) - 1);
210 __iowrite64_copy(*piobuf, data, block_len >> 3);
211 *piobuf += block_len;
216 BUG_ON(copy_buf->used);
217 BUG_ON(len > sizeof(copy_buf->buf));
218 memcpy(copy_buf->buf, data, len);
219 copy_buf->used = len;
223 /* Copy to PIO, respecting dword alignment, popping data from copy buffer first.
224 * Advances piobuf pointer. Leaves additional data in the copy buffer.
226 static void efx_memcpy_toio_aligned_cb(struct efx_nic *efx, u8 __iomem **piobuf,
228 struct efx_short_copy_buffer *copy_buf)
230 if (copy_buf->used) {
231 /* if the copy buffer is partially full, fill it up and write */
233 min_t(int, sizeof(copy_buf->buf) - copy_buf->used, len);
235 memcpy(copy_buf->buf + copy_buf->used, data, copy_to_buf);
236 copy_buf->used += copy_to_buf;
238 /* if we didn't fill it up then we're done for now */
239 if (copy_buf->used < sizeof(copy_buf->buf))
242 __iowrite64_copy(*piobuf, copy_buf->buf,
243 sizeof(copy_buf->buf) >> 3);
244 *piobuf += sizeof(copy_buf->buf);
250 efx_memcpy_toio_aligned(efx, piobuf, data, len, copy_buf);
253 static void efx_flush_copy_buffer(struct efx_nic *efx, u8 __iomem *piobuf,
254 struct efx_short_copy_buffer *copy_buf)
256 /* if there's anything in it, write the whole buffer, including junk */
258 __iowrite64_copy(piobuf, copy_buf->buf,
259 sizeof(copy_buf->buf) >> 3);
262 /* Traverse skb structure and copy fragments in to PIO buffer.
263 * Advances piobuf pointer.
265 static void efx_skb_copy_bits_to_pio(struct efx_nic *efx, struct sk_buff *skb,
267 struct efx_short_copy_buffer *copy_buf)
271 efx_memcpy_toio_aligned(efx, piobuf, skb->data, skb_headlen(skb),
274 for (i = 0; i < skb_shinfo(skb)->nr_frags; ++i) {
275 skb_frag_t *f = &skb_shinfo(skb)->frags[i];
278 vaddr = kmap_atomic(skb_frag_page(f));
280 efx_memcpy_toio_aligned_cb(efx, piobuf, vaddr + skb_frag_off(f),
281 skb_frag_size(f), copy_buf);
282 kunmap_atomic(vaddr);
285 EFX_WARN_ON_ONCE_PARANOID(skb_shinfo(skb)->frag_list);
288 static int efx_enqueue_skb_pio(struct efx_tx_queue *tx_queue,
291 struct efx_tx_buffer *buffer =
292 efx_tx_queue_get_insert_buffer(tx_queue);
293 u8 __iomem *piobuf = tx_queue->piobuf;
295 /* Copy to PIO buffer. Ensure the writes are padded to the end
296 * of a cache line, as this is required for write-combining to be
297 * effective on at least x86.
300 if (skb_shinfo(skb)->nr_frags) {
301 /* The size of the copy buffer will ensure all writes
302 * are the size of a cache line.
304 struct efx_short_copy_buffer copy_buf;
308 efx_skb_copy_bits_to_pio(tx_queue->efx, skb,
310 efx_flush_copy_buffer(tx_queue->efx, piobuf, ©_buf);
312 /* Pad the write to the size of a cache line.
313 * We can do this because we know the skb_shared_info struct is
314 * after the source, and the destination buffer is big enough.
316 BUILD_BUG_ON(L1_CACHE_BYTES >
317 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)));
318 __iowrite64_copy(tx_queue->piobuf, skb->data,
319 ALIGN(skb->len, L1_CACHE_BYTES) >> 3);
323 buffer->flags = EFX_TX_BUF_SKB | EFX_TX_BUF_OPTION;
325 EFX_POPULATE_QWORD_5(buffer->option,
326 ESF_DZ_TX_DESC_IS_OPT, 1,
327 ESF_DZ_TX_OPTION_TYPE, ESE_DZ_TX_OPTION_DESC_PIO,
328 ESF_DZ_TX_PIO_CONT, 0,
329 ESF_DZ_TX_PIO_BYTE_CNT, skb->len,
330 ESF_DZ_TX_PIO_BUF_ADDR,
331 tx_queue->piobuf_offset);
332 ++tx_queue->insert_count;
335 #endif /* EFX_USE_PIO */
337 struct efx_tx_buffer *efx_tx_map_chunk(struct efx_tx_queue *tx_queue,
341 const struct efx_nic_type *nic_type = tx_queue->efx->type;
342 struct efx_tx_buffer *buffer;
343 unsigned int dma_len;
345 /* Map the fragment taking account of NIC-dependent DMA limits. */
347 buffer = efx_tx_queue_get_insert_buffer(tx_queue);
348 dma_len = nic_type->tx_limit_len(tx_queue, dma_addr, len);
350 buffer->len = dma_len;
351 buffer->dma_addr = dma_addr;
352 buffer->flags = EFX_TX_BUF_CONT;
355 ++tx_queue->insert_count;
361 /* Map all data from an SKB for DMA and create descriptors on the queue.
363 int efx_tx_map_data(struct efx_tx_queue *tx_queue, struct sk_buff *skb,
364 unsigned int segment_count)
366 struct efx_nic *efx = tx_queue->efx;
367 struct device *dma_dev = &efx->pci_dev->dev;
368 unsigned int frag_index, nr_frags;
369 dma_addr_t dma_addr, unmap_addr;
370 unsigned short dma_flags;
371 size_t len, unmap_len;
373 nr_frags = skb_shinfo(skb)->nr_frags;
376 /* Map header data. */
377 len = skb_headlen(skb);
378 dma_addr = dma_map_single(dma_dev, skb->data, len, DMA_TO_DEVICE);
379 dma_flags = EFX_TX_BUF_MAP_SINGLE;
381 unmap_addr = dma_addr;
383 if (unlikely(dma_mapping_error(dma_dev, dma_addr)))
387 /* For TSO we need to put the header in to a separate
388 * descriptor. Map this separately if necessary.
390 size_t header_len = skb_transport_header(skb) - skb->data +
391 (tcp_hdr(skb)->doff << 2u);
393 if (header_len != len) {
394 tx_queue->tso_long_headers++;
395 efx_tx_map_chunk(tx_queue, dma_addr, header_len);
397 dma_addr += header_len;
401 /* Add descriptors for each fragment. */
403 struct efx_tx_buffer *buffer;
404 skb_frag_t *fragment;
406 buffer = efx_tx_map_chunk(tx_queue, dma_addr, len);
408 /* The final descriptor for a fragment is responsible for
409 * unmapping the whole fragment.
411 buffer->flags = EFX_TX_BUF_CONT | dma_flags;
412 buffer->unmap_len = unmap_len;
413 buffer->dma_offset = buffer->dma_addr - unmap_addr;
415 if (frag_index >= nr_frags) {
416 /* Store SKB details with the final buffer for
420 buffer->flags = EFX_TX_BUF_SKB | dma_flags;
424 /* Move on to the next fragment. */
425 fragment = &skb_shinfo(skb)->frags[frag_index++];
426 len = skb_frag_size(fragment);
427 dma_addr = skb_frag_dma_map(dma_dev, fragment,
428 0, len, DMA_TO_DEVICE);
431 unmap_addr = dma_addr;
433 if (unlikely(dma_mapping_error(dma_dev, dma_addr)))
438 /* Remove buffers put into a tx_queue for the current packet.
439 * None of the buffers must have an skb attached.
441 static void efx_enqueue_unwind(struct efx_tx_queue *tx_queue,
442 unsigned int insert_count)
444 struct efx_tx_buffer *buffer;
445 unsigned int bytes_compl = 0;
446 unsigned int pkts_compl = 0;
448 /* Work backwards until we hit the original insert pointer value */
449 while (tx_queue->insert_count != insert_count) {
450 --tx_queue->insert_count;
451 buffer = __efx_tx_queue_get_insert_buffer(tx_queue);
452 efx_dequeue_buffer(tx_queue, buffer, &pkts_compl, &bytes_compl);
457 * Fallback to software TSO.
459 * This is used if we are unable to send a GSO packet through hardware TSO.
460 * This should only ever happen due to per-queue restrictions - unsupported
461 * packets should first be filtered by the feature flags.
463 * Returns 0 on success, error code otherwise.
465 static int efx_tx_tso_fallback(struct efx_tx_queue *tx_queue,
468 struct sk_buff *segments, *next;
470 segments = skb_gso_segment(skb, 0);
471 if (IS_ERR(segments))
472 return PTR_ERR(segments);
474 dev_consume_skb_any(skb);
481 efx_enqueue_skb(tx_queue, skb);
489 * Add a socket buffer to a TX queue
491 * This maps all fragments of a socket buffer for DMA and adds them to
492 * the TX queue. The queue's insert pointer will be incremented by
493 * the number of fragments in the socket buffer.
495 * If any DMA mapping fails, any mapped fragments will be unmapped,
496 * the queue's insert pointer will be restored to its original value.
498 * This function is split out from efx_hard_start_xmit to allow the
499 * loopback test to direct packets via specific TX queues.
501 * Returns NETDEV_TX_OK.
502 * You must hold netif_tx_lock() to call this function.
504 netdev_tx_t efx_enqueue_skb(struct efx_tx_queue *tx_queue, struct sk_buff *skb)
506 unsigned int old_insert_count = tx_queue->insert_count;
507 bool xmit_more = netdev_xmit_more();
508 bool data_mapped = false;
509 unsigned int segments;
510 unsigned int skb_len;
514 segments = skb_is_gso(skb) ? skb_shinfo(skb)->gso_segs : 0;
516 segments = 0; /* Don't use TSO for a single segment. */
518 /* Handle TSO first - it's *possible* (although unlikely) that we might
519 * be passed a packet to segment that's smaller than the copybreak/PIO
523 EFX_WARN_ON_ONCE_PARANOID(!tx_queue->handle_tso);
524 rc = tx_queue->handle_tso(tx_queue, skb, &data_mapped);
526 rc = efx_tx_tso_fallback(tx_queue, skb);
527 tx_queue->tso_fallbacks++;
534 } else if (skb_len <= efx_piobuf_size && !xmit_more &&
535 efx_nic_may_tx_pio(tx_queue)) {
536 /* Use PIO for short packets with an empty queue. */
537 if (efx_enqueue_skb_pio(tx_queue, skb))
539 tx_queue->pio_packets++;
542 } else if (skb->data_len && skb_len <= EFX_TX_CB_SIZE) {
543 /* Pad short packets or coalesce short fragmented packets. */
544 if (efx_enqueue_skb_copy(tx_queue, skb))
546 tx_queue->cb_packets++;
550 /* Map for DMA and create descriptors if we haven't done so already. */
551 if (!data_mapped && (efx_tx_map_data(tx_queue, skb, segments)))
554 efx_tx_maybe_stop_queue(tx_queue);
556 /* Pass off to hardware */
557 if (__netdev_tx_sent_queue(tx_queue->core_txq, skb_len, xmit_more)) {
558 struct efx_tx_queue *txq2 = efx_tx_queue_partner(tx_queue);
560 /* There could be packets left on the partner queue if
561 * xmit_more was set. If we do not push those they
562 * could be left for a long time and cause a netdev watchdog.
564 if (txq2->xmit_more_available)
565 efx_nic_push_buffers(txq2);
567 efx_nic_push_buffers(tx_queue);
569 tx_queue->xmit_more_available = xmit_more;
573 tx_queue->tso_bursts++;
574 tx_queue->tso_packets += segments;
575 tx_queue->tx_packets += segments;
577 tx_queue->tx_packets++;
584 efx_enqueue_unwind(tx_queue, old_insert_count);
585 dev_kfree_skb_any(skb);
587 /* If we're not expecting another transmit and we had something to push
588 * on this queue or a partner queue then we need to push here to get the
589 * previous packets out.
592 struct efx_tx_queue *txq2 = efx_tx_queue_partner(tx_queue);
594 if (txq2->xmit_more_available)
595 efx_nic_push_buffers(txq2);
597 efx_nic_push_buffers(tx_queue);
603 static void efx_xdp_return_frames(int n, struct xdp_frame **xdpfs)
607 for (i = 0; i < n; i++)
608 xdp_return_frame_rx_napi(xdpfs[i]);
611 /* Transmit a packet from an XDP buffer
613 * Returns number of packets sent on success, error code otherwise.
614 * Runs in NAPI context, either in our poll (for XDP TX) or a different NIC
615 * (for XDP redirect).
617 int efx_xdp_tx_buffers(struct efx_nic *efx, int n, struct xdp_frame **xdpfs,
620 struct efx_tx_buffer *tx_buffer;
621 struct efx_tx_queue *tx_queue;
622 struct xdp_frame *xdpf;
629 cpu = raw_smp_processor_id();
631 if (!efx->xdp_tx_queue_count ||
632 unlikely(cpu >= efx->xdp_tx_queue_count))
635 tx_queue = efx->xdp_tx_queues[cpu];
636 if (unlikely(!tx_queue))
639 if (unlikely(n && !xdpfs))
645 /* Check for available space. We should never need multiple
646 * descriptors per frame.
648 space = efx->txq_entries +
649 tx_queue->read_count - tx_queue->insert_count;
651 for (i = 0; i < n; i++) {
657 /* We'll want a descriptor for this tx. */
658 prefetchw(__efx_tx_queue_get_insert_buffer(tx_queue));
663 dma_addr = dma_map_single(&efx->pci_dev->dev,
666 if (dma_mapping_error(&efx->pci_dev->dev, dma_addr))
669 /* Create descriptor and set up for unmapping DMA. */
670 tx_buffer = efx_tx_map_chunk(tx_queue, dma_addr, len);
671 tx_buffer->xdpf = xdpf;
672 tx_buffer->flags = EFX_TX_BUF_XDP |
673 EFX_TX_BUF_MAP_SINGLE;
674 tx_buffer->dma_offset = 0;
675 tx_buffer->unmap_len = len;
676 tx_queue->tx_packets++;
679 /* Pass mapped frames to hardware. */
681 efx_nic_push_buffers(tx_queue);
686 efx_xdp_return_frames(n - i, xdpfs + i);
691 /* Remove packets from the TX queue
693 * This removes packets from the TX queue, up to and including the
696 static void efx_dequeue_buffers(struct efx_tx_queue *tx_queue,
698 unsigned int *pkts_compl,
699 unsigned int *bytes_compl)
701 struct efx_nic *efx = tx_queue->efx;
702 unsigned int stop_index, read_ptr;
704 stop_index = (index + 1) & tx_queue->ptr_mask;
705 read_ptr = tx_queue->read_count & tx_queue->ptr_mask;
707 while (read_ptr != stop_index) {
708 struct efx_tx_buffer *buffer = &tx_queue->buffer[read_ptr];
710 if (!(buffer->flags & EFX_TX_BUF_OPTION) &&
711 unlikely(buffer->len == 0)) {
712 netif_err(efx, tx_err, efx->net_dev,
713 "TX queue %d spurious TX completion id %x\n",
714 tx_queue->queue, read_ptr);
715 efx_schedule_reset(efx, RESET_TYPE_TX_SKIP);
719 efx_dequeue_buffer(tx_queue, buffer, pkts_compl, bytes_compl);
721 ++tx_queue->read_count;
722 read_ptr = tx_queue->read_count & tx_queue->ptr_mask;
726 /* Initiate a packet transmission. We use one channel per CPU
727 * (sharing when we have more CPUs than channels). On Falcon, the TX
728 * completion events will be directed back to the CPU that transmitted
729 * the packet, which should be cache-efficient.
731 * Context: non-blocking.
732 * Note that returning anything other than NETDEV_TX_OK will cause the
733 * OS to free the skb.
735 netdev_tx_t efx_hard_start_xmit(struct sk_buff *skb,
736 struct net_device *net_dev)
738 struct efx_nic *efx = netdev_priv(net_dev);
739 struct efx_tx_queue *tx_queue;
740 unsigned index, type;
742 EFX_WARN_ON_PARANOID(!netif_device_present(net_dev));
744 /* PTP "event" packet */
745 if (unlikely(efx_xmit_with_hwtstamp(skb)) &&
746 unlikely(efx_ptp_is_ptp_tx(efx, skb))) {
747 return efx_ptp_tx(efx, skb);
750 index = skb_get_queue_mapping(skb);
751 type = skb->ip_summed == CHECKSUM_PARTIAL ? EFX_TXQ_TYPE_OFFLOAD : 0;
752 if (index >= efx->n_tx_channels) {
753 index -= efx->n_tx_channels;
754 type |= EFX_TXQ_TYPE_HIGHPRI;
756 tx_queue = efx_get_tx_queue(efx, index, type);
758 return efx_enqueue_skb(tx_queue, skb);
761 void efx_init_tx_queue_core_txq(struct efx_tx_queue *tx_queue)
763 struct efx_nic *efx = tx_queue->efx;
765 /* Must be inverse of queue lookup in efx_hard_start_xmit() */
767 netdev_get_tx_queue(efx->net_dev,
768 tx_queue->queue / EFX_TXQ_TYPES +
769 ((tx_queue->queue & EFX_TXQ_TYPE_HIGHPRI) ?
770 efx->n_tx_channels : 0));
773 int efx_setup_tc(struct net_device *net_dev, enum tc_setup_type type,
776 struct efx_nic *efx = netdev_priv(net_dev);
777 struct tc_mqprio_qopt *mqprio = type_data;
778 struct efx_channel *channel;
779 struct efx_tx_queue *tx_queue;
783 if (type != TC_SETUP_QDISC_MQPRIO)
786 num_tc = mqprio->num_tc;
788 if (num_tc > EFX_MAX_TX_TC)
791 mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
793 if (num_tc == net_dev->num_tc)
796 for (tc = 0; tc < num_tc; tc++) {
797 net_dev->tc_to_txq[tc].offset = tc * efx->n_tx_channels;
798 net_dev->tc_to_txq[tc].count = efx->n_tx_channels;
801 if (num_tc > net_dev->num_tc) {
802 /* Initialise high-priority queues as necessary */
803 efx_for_each_channel(channel, efx) {
804 efx_for_each_possible_channel_tx_queue(tx_queue,
806 if (!(tx_queue->queue & EFX_TXQ_TYPE_HIGHPRI))
808 if (!tx_queue->buffer) {
809 rc = efx_probe_tx_queue(tx_queue);
813 if (!tx_queue->initialised)
814 efx_init_tx_queue(tx_queue);
815 efx_init_tx_queue_core_txq(tx_queue);
819 /* Reduce number of classes before number of queues */
820 net_dev->num_tc = num_tc;
823 rc = netif_set_real_num_tx_queues(net_dev,
824 max_t(int, num_tc, 1) *
829 /* Do not destroy high-priority queues when they become
830 * unused. We would have to flush them first, and it is
831 * fairly difficult to flush a subset of TX queues. Leave
832 * it to efx_fini_channels().
835 net_dev->num_tc = num_tc;
839 void efx_xmit_done(struct efx_tx_queue *tx_queue, unsigned int index)
842 struct efx_nic *efx = tx_queue->efx;
843 struct efx_tx_queue *txq2;
844 unsigned int pkts_compl = 0, bytes_compl = 0;
846 EFX_WARN_ON_ONCE_PARANOID(index > tx_queue->ptr_mask);
848 efx_dequeue_buffers(tx_queue, index, &pkts_compl, &bytes_compl);
849 tx_queue->pkts_compl += pkts_compl;
850 tx_queue->bytes_compl += bytes_compl;
853 ++tx_queue->merge_events;
855 /* See if we need to restart the netif queue. This memory
856 * barrier ensures that we write read_count (inside
857 * efx_dequeue_buffers()) before reading the queue status.
860 if (unlikely(netif_tx_queue_stopped(tx_queue->core_txq)) &&
861 likely(efx->port_enabled) &&
862 likely(netif_device_present(efx->net_dev))) {
863 txq2 = efx_tx_queue_partner(tx_queue);
864 fill_level = max(tx_queue->insert_count - tx_queue->read_count,
865 txq2->insert_count - txq2->read_count);
866 if (fill_level <= efx->txq_wake_thresh)
867 netif_tx_wake_queue(tx_queue->core_txq);
870 /* Check whether the hardware queue is now empty */
871 if ((int)(tx_queue->read_count - tx_queue->old_write_count) >= 0) {
872 tx_queue->old_write_count = READ_ONCE(tx_queue->write_count);
873 if (tx_queue->read_count == tx_queue->old_write_count) {
875 tx_queue->empty_read_count =
876 tx_queue->read_count | EFX_EMPTY_COUNT_VALID;
881 static unsigned int efx_tx_cb_page_count(struct efx_tx_queue *tx_queue)
883 return DIV_ROUND_UP(tx_queue->ptr_mask + 1, PAGE_SIZE >> EFX_TX_CB_ORDER);
886 int efx_probe_tx_queue(struct efx_tx_queue *tx_queue)
888 struct efx_nic *efx = tx_queue->efx;
889 unsigned int entries;
892 /* Create the smallest power-of-two aligned ring */
893 entries = max(roundup_pow_of_two(efx->txq_entries), EFX_MIN_DMAQ_SIZE);
894 EFX_WARN_ON_PARANOID(entries > EFX_MAX_DMAQ_SIZE);
895 tx_queue->ptr_mask = entries - 1;
897 netif_dbg(efx, probe, efx->net_dev,
898 "creating TX queue %d size %#x mask %#x\n",
899 tx_queue->queue, efx->txq_entries, tx_queue->ptr_mask);
901 /* Allocate software ring */
902 tx_queue->buffer = kcalloc(entries, sizeof(*tx_queue->buffer),
904 if (!tx_queue->buffer)
907 tx_queue->cb_page = kcalloc(efx_tx_cb_page_count(tx_queue),
908 sizeof(tx_queue->cb_page[0]), GFP_KERNEL);
909 if (!tx_queue->cb_page) {
914 /* Allocate hardware ring */
915 rc = efx_nic_probe_tx(tx_queue);
922 kfree(tx_queue->cb_page);
923 tx_queue->cb_page = NULL;
925 kfree(tx_queue->buffer);
926 tx_queue->buffer = NULL;
930 void efx_init_tx_queue(struct efx_tx_queue *tx_queue)
932 struct efx_nic *efx = tx_queue->efx;
934 netif_dbg(efx, drv, efx->net_dev,
935 "initialising TX queue %d\n", tx_queue->queue);
937 tx_queue->insert_count = 0;
938 tx_queue->write_count = 0;
939 tx_queue->packet_write_count = 0;
940 tx_queue->old_write_count = 0;
941 tx_queue->read_count = 0;
942 tx_queue->old_read_count = 0;
943 tx_queue->empty_read_count = 0 | EFX_EMPTY_COUNT_VALID;
944 tx_queue->xmit_more_available = false;
945 tx_queue->timestamping = (efx_ptp_use_mac_tx_timestamps(efx) &&
946 tx_queue->channel == efx_ptp_channel(efx));
947 tx_queue->completed_desc_ptr = tx_queue->ptr_mask;
948 tx_queue->completed_timestamp_major = 0;
949 tx_queue->completed_timestamp_minor = 0;
951 tx_queue->xdp_tx = efx_channel_is_xdp_tx(tx_queue->channel);
953 /* Set up default function pointers. These may get replaced by
954 * efx_nic_init_tx() based off NIC/queue capabilities.
956 tx_queue->handle_tso = efx_enqueue_skb_tso;
958 /* Set up TX descriptor ring */
959 efx_nic_init_tx(tx_queue);
961 tx_queue->initialised = true;
964 void efx_fini_tx_queue(struct efx_tx_queue *tx_queue)
966 struct efx_tx_buffer *buffer;
968 netif_dbg(tx_queue->efx, drv, tx_queue->efx->net_dev,
969 "shutting down TX queue %d\n", tx_queue->queue);
971 if (!tx_queue->buffer)
974 /* Free any buffers left in the ring */
975 while (tx_queue->read_count != tx_queue->write_count) {
976 unsigned int pkts_compl = 0, bytes_compl = 0;
977 buffer = &tx_queue->buffer[tx_queue->read_count & tx_queue->ptr_mask];
978 efx_dequeue_buffer(tx_queue, buffer, &pkts_compl, &bytes_compl);
980 ++tx_queue->read_count;
982 tx_queue->xmit_more_available = false;
983 netdev_tx_reset_queue(tx_queue->core_txq);
986 void efx_remove_tx_queue(struct efx_tx_queue *tx_queue)
990 if (!tx_queue->buffer)
993 netif_dbg(tx_queue->efx, drv, tx_queue->efx->net_dev,
994 "destroying TX queue %d\n", tx_queue->queue);
995 efx_nic_remove_tx(tx_queue);
997 if (tx_queue->cb_page) {
998 for (i = 0; i < efx_tx_cb_page_count(tx_queue); i++)
999 efx_nic_free_buffer(tx_queue->efx,
1000 &tx_queue->cb_page[i]);
1001 kfree(tx_queue->cb_page);
1002 tx_queue->cb_page = NULL;
1005 kfree(tx_queue->buffer);
1006 tx_queue->buffer = NULL;