1 /*******************************************************************************
2 STMMAC Common Header File
4 Copyright (C) 2007-2009 STMicroelectronics Ltd
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 The full GNU General Public License is included in this distribution in
16 the file called "COPYING".
18 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
19 *******************************************************************************/
24 #include <linux/etherdevice.h>
25 #include <linux/netdevice.h>
26 #include <linux/stmmac.h>
27 #include <linux/phy.h>
28 #include <linux/module.h>
29 #if IS_ENABLED(CONFIG_VLAN_8021Q)
30 #define STMMAC_VLAN_TAG_USED
31 #include <linux/if_vlan.h>
38 /* Synopsys Core versions */
39 #define DWMAC_CORE_3_40 0x34
40 #define DWMAC_CORE_3_50 0x35
41 #define DWMAC_CORE_4_00 0x40
42 #define DWMAC_CORE_4_10 0x41
43 #define DWMAC_CORE_5_00 0x50
44 #define DWMAC_CORE_5_10 0x51
45 #define DWXGMAC_CORE_2_10 0x21
47 #define STMMAC_CHAN0 0 /* Always supported and default for all chips */
49 /* These need to be power of two, and >= 4 */
50 #define DMA_TX_SIZE 512
51 #define DMA_RX_SIZE 512
52 #define STMMAC_GET_ENTRY(x, size) ((x + 1) & (size - 1))
54 #undef FRAME_FILTER_DEBUG
55 /* #define FRAME_FILTER_DEBUG */
57 /* Extra statistic and debug information exposed by ethtool */
58 struct stmmac_extra_stats {
60 unsigned long tx_underflow ____cacheline_aligned;
61 unsigned long tx_carrier;
62 unsigned long tx_losscarrier;
63 unsigned long vlan_tag;
64 unsigned long tx_deferred;
65 unsigned long tx_vlan;
66 unsigned long tx_jabber;
67 unsigned long tx_frame_flushed;
68 unsigned long tx_payload_error;
69 unsigned long tx_ip_header_error;
71 unsigned long rx_desc;
72 unsigned long sa_filter_fail;
73 unsigned long overflow_error;
74 unsigned long ipc_csum_error;
75 unsigned long rx_collision;
76 unsigned long rx_crc_errors;
77 unsigned long dribbling_bit;
78 unsigned long rx_length;
80 unsigned long rx_multicast;
81 unsigned long rx_gmac_overflow;
82 unsigned long rx_watchdog;
83 unsigned long da_rx_filter_fail;
84 unsigned long sa_rx_filter_fail;
85 unsigned long rx_missed_cntr;
86 unsigned long rx_overflow_cntr;
87 unsigned long rx_vlan;
88 /* Tx/Rx IRQ error info */
89 unsigned long tx_undeflow_irq;
90 unsigned long tx_process_stopped_irq;
91 unsigned long tx_jabber_irq;
92 unsigned long rx_overflow_irq;
93 unsigned long rx_buf_unav_irq;
94 unsigned long rx_process_stopped_irq;
95 unsigned long rx_watchdog_irq;
96 unsigned long tx_early_irq;
97 unsigned long fatal_bus_error_irq;
98 /* Tx/Rx IRQ Events */
99 unsigned long rx_early_irq;
100 unsigned long threshold;
101 unsigned long tx_pkt_n;
102 unsigned long rx_pkt_n;
103 unsigned long normal_irq_n;
104 unsigned long rx_normal_irq_n;
105 unsigned long napi_poll;
106 unsigned long tx_normal_irq_n;
107 unsigned long tx_clean;
108 unsigned long tx_set_ic_bit;
109 unsigned long irq_receive_pmt_irq_n;
111 unsigned long mmc_tx_irq_n;
112 unsigned long mmc_rx_irq_n;
113 unsigned long mmc_rx_csum_offload_irq_n;
115 unsigned long irq_tx_path_in_lpi_mode_n;
116 unsigned long irq_tx_path_exit_lpi_mode_n;
117 unsigned long irq_rx_path_in_lpi_mode_n;
118 unsigned long irq_rx_path_exit_lpi_mode_n;
119 unsigned long phy_eee_wakeup_error_n;
120 /* Extended RDES status */
121 unsigned long ip_hdr_err;
122 unsigned long ip_payload_err;
123 unsigned long ip_csum_bypassed;
124 unsigned long ipv4_pkt_rcvd;
125 unsigned long ipv6_pkt_rcvd;
126 unsigned long no_ptp_rx_msg_type_ext;
127 unsigned long ptp_rx_msg_type_sync;
128 unsigned long ptp_rx_msg_type_follow_up;
129 unsigned long ptp_rx_msg_type_delay_req;
130 unsigned long ptp_rx_msg_type_delay_resp;
131 unsigned long ptp_rx_msg_type_pdelay_req;
132 unsigned long ptp_rx_msg_type_pdelay_resp;
133 unsigned long ptp_rx_msg_type_pdelay_follow_up;
134 unsigned long ptp_rx_msg_type_announce;
135 unsigned long ptp_rx_msg_type_management;
136 unsigned long ptp_rx_msg_pkt_reserved_type;
137 unsigned long ptp_frame_type;
138 unsigned long ptp_ver;
139 unsigned long timestamp_dropped;
140 unsigned long av_pkt_rcvd;
141 unsigned long av_tagged_pkt_rcvd;
142 unsigned long vlan_tag_priority_val;
143 unsigned long l3_filter_match;
144 unsigned long l4_filter_match;
145 unsigned long l3_l4_filter_no_match;
147 unsigned long irq_pcs_ane_n;
148 unsigned long irq_pcs_link_n;
149 unsigned long irq_rgmii_n;
150 unsigned long pcs_link;
151 unsigned long pcs_duplex;
152 unsigned long pcs_speed;
154 unsigned long mtl_tx_status_fifo_full;
155 unsigned long mtl_tx_fifo_not_empty;
156 unsigned long mmtl_fifo_ctrl;
157 unsigned long mtl_tx_fifo_read_ctrl_write;
158 unsigned long mtl_tx_fifo_read_ctrl_wait;
159 unsigned long mtl_tx_fifo_read_ctrl_read;
160 unsigned long mtl_tx_fifo_read_ctrl_idle;
161 unsigned long mac_tx_in_pause;
162 unsigned long mac_tx_frame_ctrl_xfer;
163 unsigned long mac_tx_frame_ctrl_idle;
164 unsigned long mac_tx_frame_ctrl_wait;
165 unsigned long mac_tx_frame_ctrl_pause;
166 unsigned long mac_gmii_tx_proto_engine;
167 unsigned long mtl_rx_fifo_fill_level_full;
168 unsigned long mtl_rx_fifo_fill_above_thresh;
169 unsigned long mtl_rx_fifo_fill_below_thresh;
170 unsigned long mtl_rx_fifo_fill_level_empty;
171 unsigned long mtl_rx_fifo_read_ctrl_flush;
172 unsigned long mtl_rx_fifo_read_ctrl_read_data;
173 unsigned long mtl_rx_fifo_read_ctrl_status;
174 unsigned long mtl_rx_fifo_read_ctrl_idle;
175 unsigned long mtl_rx_fifo_ctrl_active;
176 unsigned long mac_rx_frame_ctrl_fifo;
177 unsigned long mac_gmii_rx_proto_engine;
179 unsigned long tx_tso_frames;
180 unsigned long tx_tso_nfrags;
183 /* Safety Feature statistics exposed by ethtool */
184 struct stmmac_safety_stats {
185 unsigned long mac_errors[32];
186 unsigned long mtl_errors[32];
187 unsigned long dma_errors[32];
190 /* Number of fields in Safety Stats */
191 #define STMMAC_SAFETY_FEAT_SIZE \
192 (sizeof(struct stmmac_safety_stats) / sizeof(unsigned long))
194 /* CSR Frequency Access Defines*/
195 #define CSR_F_35M 35000000
196 #define CSR_F_60M 60000000
197 #define CSR_F_100M 100000000
198 #define CSR_F_150M 150000000
199 #define CSR_F_250M 250000000
200 #define CSR_F_300M 300000000
202 #define MAC_CSR_H_FRQ_MASK 0x20
204 #define HASH_TABLE_SIZE 64
205 #define PAUSE_TIME 0xffff
207 /* Flow Control defines */
211 #define FLOW_AUTO (FLOW_TX | FLOW_RX)
214 #define STMMAC_PCS_RGMII (1 << 0)
215 #define STMMAC_PCS_SGMII (1 << 1)
216 #define STMMAC_PCS_TBI (1 << 2)
217 #define STMMAC_PCS_RTBI (1 << 3)
219 #define SF_DMA_MODE 1 /* DMA STORE-AND-FORWARD Operation Mode */
221 /* DAM HW feature register fields */
222 #define DMA_HW_FEAT_MIISEL 0x00000001 /* 10/100 Mbps Support */
223 #define DMA_HW_FEAT_GMIISEL 0x00000002 /* 1000 Mbps Support */
224 #define DMA_HW_FEAT_HDSEL 0x00000004 /* Half-Duplex Support */
225 #define DMA_HW_FEAT_EXTHASHEN 0x00000008 /* Expanded DA Hash Filter */
226 #define DMA_HW_FEAT_HASHSEL 0x00000010 /* HASH Filter */
227 #define DMA_HW_FEAT_ADDMAC 0x00000020 /* Multiple MAC Addr Reg */
228 #define DMA_HW_FEAT_PCSSEL 0x00000040 /* PCS registers */
229 #define DMA_HW_FEAT_L3L4FLTREN 0x00000080 /* Layer 3 & Layer 4 Feature */
230 #define DMA_HW_FEAT_SMASEL 0x00000100 /* SMA(MDIO) Interface */
231 #define DMA_HW_FEAT_RWKSEL 0x00000200 /* PMT Remote Wakeup */
232 #define DMA_HW_FEAT_MGKSEL 0x00000400 /* PMT Magic Packet */
233 #define DMA_HW_FEAT_MMCSEL 0x00000800 /* RMON Module */
234 #define DMA_HW_FEAT_TSVER1SEL 0x00001000 /* Only IEEE 1588-2002 */
235 #define DMA_HW_FEAT_TSVER2SEL 0x00002000 /* IEEE 1588-2008 PTPv2 */
236 #define DMA_HW_FEAT_EEESEL 0x00004000 /* Energy Efficient Ethernet */
237 #define DMA_HW_FEAT_AVSEL 0x00008000 /* AV Feature */
238 #define DMA_HW_FEAT_TXCOESEL 0x00010000 /* Checksum Offload in Tx */
239 #define DMA_HW_FEAT_RXTYP1COE 0x00020000 /* IP COE (Type 1) in Rx */
240 #define DMA_HW_FEAT_RXTYP2COE 0x00040000 /* IP COE (Type 2) in Rx */
241 #define DMA_HW_FEAT_RXFIFOSIZE 0x00080000 /* Rx FIFO > 2048 Bytes */
242 #define DMA_HW_FEAT_RXCHCNT 0x00300000 /* No. additional Rx Channels */
243 #define DMA_HW_FEAT_TXCHCNT 0x00c00000 /* No. additional Tx Channels */
244 #define DMA_HW_FEAT_ENHDESSEL 0x01000000 /* Alternate Descriptor */
245 /* Timestamping with Internal System Time */
246 #define DMA_HW_FEAT_INTTSEN 0x02000000
247 #define DMA_HW_FEAT_FLEXIPPSEN 0x04000000 /* Flexible PPS Output */
248 #define DMA_HW_FEAT_SAVLANINS 0x08000000 /* Source Addr or VLAN */
249 #define DMA_HW_FEAT_ACTPHYIF 0x70000000 /* Active/selected PHY iface */
250 #define DEFAULT_DMA_PBL 8
252 /* PCS status and mask defines */
253 #define PCS_ANE_IRQ BIT(2) /* PCS Auto-Negotiation */
254 #define PCS_LINK_IRQ BIT(1) /* PCS Link */
255 #define PCS_RGSMIIIS_IRQ BIT(0) /* RGMII or SMII Interrupt */
257 /* Max/Min RI Watchdog Timer count value */
258 #define MAX_DMA_RIWT 0xff
259 #define MIN_DMA_RIWT 0x20
260 /* Tx coalesce parameters */
261 #define STMMAC_COAL_TX_TIMER 1000
262 #define STMMAC_MAX_COAL_TX_TICK 100000
263 #define STMMAC_TX_MAX_FRAMES 256
264 #define STMMAC_TX_FRAMES 25
268 PACKET_AVCPQ = 0x1, /* AV Untagged Control packets */
269 PACKET_PTPQ = 0x2, /* PTP Packets */
270 PACKET_DCBCPQ = 0x3, /* DCB Control Packets */
271 PACKET_UPQ = 0x4, /* Untagged Packets */
272 PACKET_MCBCQ = 0x5, /* Multicast & Broadcast Packets */
276 enum rx_frame_status {
286 enum tx_frame_status {
293 enum dma_irq_status {
295 tx_hard_error_bump_tc = 0x2,
300 /* EEE and LPI defines */
301 #define CORE_IRQ_TX_PATH_IN_LPI_MODE (1 << 0)
302 #define CORE_IRQ_TX_PATH_EXIT_LPI_MODE (1 << 1)
303 #define CORE_IRQ_RX_PATH_IN_LPI_MODE (1 << 2)
304 #define CORE_IRQ_RX_PATH_EXIT_LPI_MODE (1 << 3)
306 #define CORE_IRQ_MTL_RX_OVERFLOW BIT(8)
308 /* Physical Coding Sublayer */
312 unsigned int lp_pause;
313 unsigned int lp_duplex;
316 #define STMMAC_PCS_PAUSE 1
317 #define STMMAC_PCS_ASYM_PAUSE 2
319 /* DMA HW capabilities */
320 struct dma_features {
321 unsigned int mbps_10_100;
322 unsigned int mbps_1000;
323 unsigned int half_duplex;
324 unsigned int hash_filter;
325 unsigned int multi_addr;
327 unsigned int sma_mdio;
328 unsigned int pmt_remote_wake_up;
329 unsigned int pmt_magic_frame;
332 unsigned int time_stamp;
334 unsigned int atime_stamp;
335 /* 802.3az - Energy-Efficient Ethernet (EEE) */
342 unsigned int rx_coe_type1;
343 unsigned int rx_coe_type2;
344 unsigned int rxfifo_over_2048;
345 /* TX and RX number of channels */
346 unsigned int number_rx_channel;
347 unsigned int number_tx_channel;
348 /* TX and RX number of queues */
349 unsigned int number_rx_queues;
350 unsigned int number_tx_queues;
352 unsigned int pps_out_num;
353 /* Alternate (enhanced) DESC mode */
354 unsigned int enh_desc;
355 /* TX and RX FIFO sizes */
356 unsigned int tx_fifo_size;
357 unsigned int rx_fifo_size;
358 /* Automotive Safety Package */
366 /* GMAC TX FIFO is 8K, Rx FIFO is 16K */
367 #define BUF_SIZE_16KiB 16384
368 /* RX Buffer size must be < 8191 and multiple of 4/8/16 bytes */
369 #define BUF_SIZE_8KiB 8188
370 #define BUF_SIZE_4KiB 4096
371 #define BUF_SIZE_2KiB 2048
373 /* Power Down and WOL */
374 #define PMT_NOT_SUPPORTED 0
375 #define PMT_SUPPORTED 1
377 /* Common MAC defines */
378 #define MAC_CTRL_REG 0x00000000 /* MAC Control */
379 #define MAC_ENABLE_TX 0x00000008 /* Transmitter Enable */
380 #define MAC_ENABLE_RX 0x00000004 /* Receiver Enable */
382 /* Default LPI timers */
383 #define STMMAC_DEFAULT_LIT_LS 0x3E8
384 #define STMMAC_DEFAULT_TWT_LS 0x1E
386 #define STMMAC_CHAIN_MODE 0x1
387 #define STMMAC_RING_MODE 0x2
389 #define JUMBO_LEN 9000
391 extern const struct stmmac_desc_ops enh_desc_ops;
392 extern const struct stmmac_desc_ops ndesc_ops;
394 struct mac_device_info;
396 extern const struct stmmac_hwtimestamp stmmac_ptp;
397 extern const struct stmmac_mode_ops dwmac4_ring_mode_ops;
410 unsigned int addr; /* MII Address */
411 unsigned int data; /* MII Data */
412 unsigned int addr_shift; /* MII address shift */
413 unsigned int reg_shift; /* MII reg shift */
414 unsigned int addr_mask; /* MII address mask */
415 unsigned int reg_mask; /* MII reg mask */
416 unsigned int clk_csr_shift;
417 unsigned int clk_csr_mask;
420 struct mac_device_info {
421 const struct stmmac_ops *mac;
422 const struct stmmac_desc_ops *desc;
423 const struct stmmac_dma_ops *dma;
424 const struct stmmac_mode_ops *mode;
425 const struct stmmac_hwtimestamp *ptp;
426 const struct stmmac_tc_ops *tc;
427 struct mii_regs mii; /* MII register Addresses */
428 struct mac_link link;
429 void __iomem *pcsr; /* vpointer to device CSRs */
430 int multicast_filter_bins;
431 int unicast_filter_entries;
433 unsigned int rx_csum;
439 struct stmmac_rx_routing {
444 int dwmac100_setup(struct stmmac_priv *priv);
445 int dwmac1000_setup(struct stmmac_priv *priv);
446 int dwmac4_setup(struct stmmac_priv *priv);
447 int dwxgmac2_setup(struct stmmac_priv *priv);
449 void stmmac_set_mac_addr(void __iomem *ioaddr, u8 addr[6],
450 unsigned int high, unsigned int low);
451 void stmmac_get_mac_addr(void __iomem *ioaddr, unsigned char *addr,
452 unsigned int high, unsigned int low);
453 void stmmac_set_mac(void __iomem *ioaddr, bool enable);
455 void stmmac_dwmac4_set_mac_addr(void __iomem *ioaddr, u8 addr[6],
456 unsigned int high, unsigned int low);
457 void stmmac_dwmac4_get_mac_addr(void __iomem *ioaddr, unsigned char *addr,
458 unsigned int high, unsigned int low);
459 void stmmac_dwmac4_set_mac(void __iomem *ioaddr, bool enable);
461 void dwmac_dma_flush_tx_fifo(void __iomem *ioaddr);
463 extern const struct stmmac_mode_ops ring_mode_ops;
464 extern const struct stmmac_mode_ops chain_mode_ops;
465 extern const struct stmmac_desc_ops dwmac4_desc_ops;
467 #endif /* __COMMON_H__ */