drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c

   1 /* Copyright Altera Corporation (C) 2014. All rights reserved.
   2  *
   3  * This program is free software; you can redistribute it and/or modify
   4  * it under the terms of the GNU General Public License, version 2,
   5  * as published by the Free Software Foundation.
   6  *
   7  * This program is distributed in the hope that it will be useful,
   8  * but WITHOUT ANY WARRANTY; without even the implied warranty of
   9  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  10  * GNU General Public License for more details.
  11  *
  12  * You should have received a copy of the GNU General Public License
  13  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  14  *
  15  * Adopted from dwmac-sti.c
  16  */
  17
  18 #include <linux/mfd/altera-sysmgr.h>
  19 #include <linux/of.h>
  20 #include <linux/of_address.h>
  21 #include <linux/of_net.h>
  22 #include <linux/phy.h>
  23 #include <linux/regmap.h>
  24 #include <linux/reset.h>
  25 #include <linux/stmmac.h>
  26
  27 #include "stmmac.h"
  28 #include "stmmac_platform.h"
  29
  30 #include "altr_tse_pcs.h"
  31
  32 #define SGMII_ADAPTER_CTRL_REG                          0x00
  33 #define SGMII_ADAPTER_DISABLE                           0x0001
  34
  35 #define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII 0x0
  36 #define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII 0x1
  37 #define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII 0x2
  38 #define SYSMGR_EMACGRP_CTRL_PHYSEL_WIDTH 2
  39 #define SYSMGR_EMACGRP_CTRL_PHYSEL_MASK 0x00000003
  40 #define SYSMGR_EMACGRP_CTRL_PTP_REF_CLK_MASK 0x00000010
  41
  42 #define SYSMGR_FPGAGRP_MODULE_REG  0x00000028
  43 #define SYSMGR_FPGAGRP_MODULE_EMAC 0x00000004
  44
  45 #define EMAC_SPLITTER_CTRL_REG                  0x0
  46 #define EMAC_SPLITTER_CTRL_SPEED_MASK           0x3
  47 #define EMAC_SPLITTER_CTRL_SPEED_10             0x2
  48 #define EMAC_SPLITTER_CTRL_SPEED_100            0x3
  49 #define EMAC_SPLITTER_CTRL_SPEED_1000           0x0
  50
  51 struct socfpga_dwmac {
  52         int     interface;
  53         u32     reg_offset;
  54         u32     reg_shift;
  55         struct  device *dev;
  56         struct regmap *sys_mgr_base_addr;
  57         struct reset_control *stmmac_rst;
  58         struct reset_control *stmmac_ocp_rst;
  59         void __iomem *splitter_base;
  60         bool f2h_ptp_ref_clk;
  61         struct tse_pcs pcs;
  62 };
  63
  64 static void socfpga_dwmac_fix_mac_speed(void *priv, unsigned int speed)
  65 {
  66         struct socfpga_dwmac *dwmac = (struct socfpga_dwmac *)priv;
  67         void __iomem *splitter_base = dwmac->splitter_base;
  68         void __iomem *tse_pcs_base = dwmac->pcs.tse_pcs_base;
  69         void __iomem *sgmii_adapter_base = dwmac->pcs.sgmii_adapter_base;
  70         struct device *dev = dwmac->dev;
  71         struct net_device *ndev = dev_get_drvdata(dev);
  72         struct phy_device *phy_dev = ndev->phydev;
  73         u32 val;
  74
  75         if ((tse_pcs_base) && (sgmii_adapter_base))
  76                 writew(SGMII_ADAPTER_DISABLE,
  77                        sgmii_adapter_base + SGMII_ADAPTER_CTRL_REG);
  78
  79         if (splitter_base) {
  80                 val = readl(splitter_base + EMAC_SPLITTER_CTRL_REG);
  81                 val &= ~EMAC_SPLITTER_CTRL_SPEED_MASK;
  82
  83                 switch (speed) {
  84                 case 1000:
  85                         val |= EMAC_SPLITTER_CTRL_SPEED_1000;
  86                         break;
  87                 case 100:
  88                         val |= EMAC_SPLITTER_CTRL_SPEED_100;
  89                         break;
  90                 case 10:
  91                         val |= EMAC_SPLITTER_CTRL_SPEED_10;
  92                         break;
  93                 default:
  94                         return;
  95                 }
  96                 writel(val, splitter_base + EMAC_SPLITTER_CTRL_REG);
  97         }
  98
  99         if (tse_pcs_base && sgmii_adapter_base)
 100                 tse_pcs_fix_mac_speed(&dwmac->pcs, phy_dev, speed);
 101 }
 102
 103 static int socfpga_dwmac_parse_data(struct socfpga_dwmac *dwmac, struct device *dev)
 104 {
 105         struct device_node *np = dev->of_node;
 106         struct regmap *sys_mgr_base_addr;
 107         u32 reg_offset, reg_shift;
 108         int ret, index;
 109         struct device_node *np_splitter = NULL;
 110         struct device_node *np_sgmii_adapter = NULL;
 111         struct resource res_splitter;
 112         struct resource res_tse_pcs;
 113         struct resource res_sgmii_adapter;
 114
 115         dwmac->interface = of_get_phy_mode(np);
 116
 117         sys_mgr_base_addr =
 118                 altr_sysmgr_regmap_lookup_by_phandle(np, "altr,sysmgr-syscon");
 119         if (IS_ERR(sys_mgr_base_addr)) {
 120                 dev_info(dev, "No sysmgr-syscon node found\n");
 121                 return PTR_ERR(sys_mgr_base_addr);
 122         }
 123
 124         ret = of_property_read_u32_index(np, "altr,sysmgr-syscon", 1, &reg_offset);
 125         if (ret) {
 126                 dev_info(dev, "Could not read reg_offset from sysmgr-syscon!\n");
 127                 return -EINVAL;
 128         }
 129
 130         ret = of_property_read_u32_index(np, "altr,sysmgr-syscon", 2, &reg_shift);
 131         if (ret) {
 132                 dev_info(dev, "Could not read reg_shift from sysmgr-syscon!\n");
 133                 return -EINVAL;
 134         }
 135
 136         dwmac->f2h_ptp_ref_clk = of_property_read_bool(np, "altr,f2h_ptp_ref_clk");
 137
 138         np_splitter = of_parse_phandle(np, "altr,emac-splitter", 0);
 139         if (np_splitter) {
 140                 ret = of_address_to_resource(np_splitter, 0, &res_splitter);
 141                 of_node_put(np_splitter);
 142                 if (ret) {
 143                         dev_info(dev, "Missing emac splitter address\n");
 144                         return -EINVAL;
 145                 }
 146
 147                 dwmac->splitter_base = devm_ioremap_resource(dev, &res_splitter);
 148                 if (IS_ERR(dwmac->splitter_base)) {
 149                         dev_info(dev, "Failed to mapping emac splitter\n");
 150                         return PTR_ERR(dwmac->splitter_base);
 151                 }
 152         }
 153
 154         np_sgmii_adapter = of_parse_phandle(np,
 155                                             "altr,gmii-to-sgmii-converter", 0);
 156         if (np_sgmii_adapter) {
 157                 index = of_property_match_string(np_sgmii_adapter, "reg-names",
 158                                                  "hps_emac_interface_splitter_avalon_slave");
 159
 160                 if (index >= 0) {
 161                         if (of_address_to_resource(np_sgmii_adapter, index,
 162                                                    &res_splitter)) {
 163                                 dev_err(dev,
 164                                         "%s: ERROR: missing emac splitter address\n",
 165                                         __func__);
 166                                 ret = -EINVAL;
 167                                 goto err_node_put;
 168                         }
 169
 170                         dwmac->splitter_base =
 171                             devm_ioremap_resource(dev, &res_splitter);
 172
 173                         if (IS_ERR(dwmac->splitter_base)) {
 174                                 ret = PTR_ERR(dwmac->splitter_base);
 175                                 goto err_node_put;
 176                         }
 177                 }
 178
 179                 index = of_property_match_string(np_sgmii_adapter, "reg-names",
 180                                                  "gmii_to_sgmii_adapter_avalon_slave");
 181
 182                 if (index >= 0) {
 183                         if (of_address_to_resource(np_sgmii_adapter, index,
 184                                                    &res_sgmii_adapter)) {
 185                                 dev_err(dev,
 186                                         "%s: ERROR: failed mapping adapter\n",
 187                                         __func__);
 188                                 ret = -EINVAL;
 189                                 goto err_node_put;
 190                         }
 191
 192                         dwmac->pcs.sgmii_adapter_base =
 193                             devm_ioremap_resource(dev, &res_sgmii_adapter);
 194
 195                         if (IS_ERR(dwmac->pcs.sgmii_adapter_base)) {
 196                                 ret = PTR_ERR(dwmac->pcs.sgmii_adapter_base);
 197                                 goto err_node_put;
 198                         }
 199                 }
 200
 201                 index = of_property_match_string(np_sgmii_adapter, "reg-names",
 202                                                  "eth_tse_control_port");
 203
 204                 if (index >= 0) {
 205                         if (of_address_to_resource(np_sgmii_adapter, index,
 206                                                    &res_tse_pcs)) {
 207                                 dev_err(dev,
 208                                         "%s: ERROR: failed mapping tse control port\n",
 209                                         __func__);
 210                                 ret = -EINVAL;
 211                                 goto err_node_put;
 212                         }
 213
 214                         dwmac->pcs.tse_pcs_base =
 215                             devm_ioremap_resource(dev, &res_tse_pcs);
 216
 217                         if (IS_ERR(dwmac->pcs.tse_pcs_base)) {
 218                                 ret = PTR_ERR(dwmac->pcs.tse_pcs_base);
 219                                 goto err_node_put;
 220                         }
 221                 }
 222         }
 223         dwmac->reg_offset = reg_offset;
 224         dwmac->reg_shift = reg_shift;
 225         dwmac->sys_mgr_base_addr = sys_mgr_base_addr;
 226         dwmac->dev = dev;
 227         of_node_put(np_sgmii_adapter);
 228
 229         return 0;
 230
 231 err_node_put:
 232         of_node_put(np_sgmii_adapter);
 233         return ret;
 234 }
 235
 236 static int socfpga_dwmac_set_phy_mode(struct socfpga_dwmac *dwmac)
 237 {
 238         struct regmap *sys_mgr_base_addr = dwmac->sys_mgr_base_addr;
 239         int phymode = dwmac->interface;
 240         u32 reg_offset = dwmac->reg_offset;
 241         u32 reg_shift = dwmac->reg_shift;
 242         u32 ctrl, val, module;
 243
 244         switch (phymode) {
 245         case PHY_INTERFACE_MODE_RGMII:
 246         case PHY_INTERFACE_MODE_RGMII_ID:
 247                 val = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII;
 248                 break;
 249         case PHY_INTERFACE_MODE_MII:
 250         case PHY_INTERFACE_MODE_GMII:
 251         case PHY_INTERFACE_MODE_SGMII:
 252                 val = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII;
 253                 break;
 254         default:
 255                 dev_err(dwmac->dev, "bad phy mode %d\n", phymode);
 256                 return -EINVAL;
 257         }
 258
 259         /* Overwrite val to GMII if splitter core is enabled. The phymode here
 260          * is the actual phy mode on phy hardware, but phy interface from
 261          * EMAC core is GMII.
 262          */
 263         if (dwmac->splitter_base)
 264                 val = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII;
 265
 266         /* Assert reset to the enet controller before changing the phy mode */
 267         reset_control_assert(dwmac->stmmac_ocp_rst);
 268         reset_control_assert(dwmac->stmmac_rst);
 269
 270         regmap_read(sys_mgr_base_addr, reg_offset, &ctrl);
 271         ctrl &= ~(SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << reg_shift);
 272         ctrl |= val << reg_shift;
 273
 274         if (dwmac->f2h_ptp_ref_clk ||
 275             phymode == PHY_INTERFACE_MODE_MII ||
 276             phymode == PHY_INTERFACE_MODE_GMII ||
 277             phymode == PHY_INTERFACE_MODE_SGMII) {
 278                 ctrl |= SYSMGR_EMACGRP_CTRL_PTP_REF_CLK_MASK << (reg_shift / 2);
 279                 regmap_read(sys_mgr_base_addr, SYSMGR_FPGAGRP_MODULE_REG,
 280                             &module);
 281                 module |= (SYSMGR_FPGAGRP_MODULE_EMAC << (reg_shift / 2));
 282                 regmap_write(sys_mgr_base_addr, SYSMGR_FPGAGRP_MODULE_REG,
 283                              module);
 284         } else {
 285                 ctrl &= ~(SYSMGR_EMACGRP_CTRL_PTP_REF_CLK_MASK << (reg_shift / 2));
 286         }
 287
 288         regmap_write(sys_mgr_base_addr, reg_offset, ctrl);
 289
 290         /* Deassert reset for the phy configuration to be sampled by
 291          * the enet controller, and operation to start in requested mode
 292          */
 293         reset_control_deassert(dwmac->stmmac_ocp_rst);
 294         reset_control_deassert(dwmac->stmmac_rst);
 295         if (phymode == PHY_INTERFACE_MODE_SGMII) {
 296                 if (tse_pcs_init(dwmac->pcs.tse_pcs_base, &dwmac->pcs) != 0) {
 297                         dev_err(dwmac->dev, "Unable to initialize TSE PCS");
 298                         return -EINVAL;
 299                 }
 300         }
 301
 302         return 0;
 303 }
 304
 305 static int socfpga_dwmac_probe(struct platform_device *pdev)
 306 {
 307         struct plat_stmmacenet_data *plat_dat;
 308         struct stmmac_resources stmmac_res;
 309         struct device           *dev = &pdev->dev;
 310         int                     ret;
 311         struct socfpga_dwmac    *dwmac;
 312         struct net_device       *ndev;
 313         struct stmmac_priv      *stpriv;
 314
 315         ret = stmmac_get_platform_resources(pdev, &stmmac_res);
 316         if (ret)
 317                 return ret;
 318
 319         plat_dat = stmmac_probe_config_dt(pdev, &stmmac_res.mac);
 320         if (IS_ERR(plat_dat))
 321                 return PTR_ERR(plat_dat);
 322
 323         dwmac = devm_kzalloc(dev, sizeof(*dwmac), GFP_KERNEL);
 324         if (!dwmac) {
 325                 ret = -ENOMEM;
 326                 goto err_remove_config_dt;
 327         }
 328
 329         dwmac->stmmac_ocp_rst = devm_reset_control_get_optional(dev, "stmmaceth-ocp");
 330         if (IS_ERR(dwmac->stmmac_ocp_rst)) {
 331                 ret = PTR_ERR(dwmac->stmmac_ocp_rst);
 332                 dev_err(dev, "error getting reset control of ocp %d\n", ret);
 333                 goto err_remove_config_dt;
 334         }
 335
 336         reset_control_deassert(dwmac->stmmac_ocp_rst);
 337
 338         ret = socfpga_dwmac_parse_data(dwmac, dev);
 339         if (ret) {
 340                 dev_err(dev, "Unable to parse OF data\n");
 341                 goto err_remove_config_dt;
 342         }
 343
 344         plat_dat->bsp_priv = dwmac;
 345         plat_dat->fix_mac_speed = socfpga_dwmac_fix_mac_speed;
 346
 347         ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res);
 348         if (ret)
 349                 goto err_remove_config_dt;
 350
 351         ndev = platform_get_drvdata(pdev);
 352         stpriv = netdev_priv(ndev);
 353
 354         /* The socfpga driver needs to control the stmmac reset to set the phy
 355          * mode. Create a copy of the core reset handle so it can be used by
 356          * the driver later.
 357          */
 358         dwmac->stmmac_rst = stpriv->plat->stmmac_rst;
 359
 360         ret = socfpga_dwmac_set_phy_mode(dwmac);
 361         if (ret)
 362                 goto err_dvr_remove;
 363
 364         return 0;
 365
 366 err_dvr_remove:
 367         stmmac_dvr_remove(&pdev->dev);
 368 err_remove_config_dt:
 369         stmmac_remove_config_dt(pdev, plat_dat);
 370
 371         return ret;
 372 }
 373
 374 #ifdef CONFIG_PM_SLEEP
 375 static int socfpga_dwmac_resume(struct device *dev)
 376 {
 377         struct net_device *ndev = dev_get_drvdata(dev);
 378         struct stmmac_priv *priv = netdev_priv(ndev);
 379
 380         socfpga_dwmac_set_phy_mode(priv->plat->bsp_priv);
 381
 382         /* Before the enet controller is suspended, the phy is suspended.
 383          * This causes the phy clock to be gated. The enet controller is
 384          * resumed before the phy, so the clock is still gated "off" when
 385          * the enet controller is resumed. This code makes sure the phy
 386          * is "resumed" before reinitializing the enet controller since
 387          * the enet controller depends on an active phy clock to complete
 388          * a DMA reset. A DMA reset will "time out" if executed
 389          * with no phy clock input on the Synopsys enet controller.
 390          * Verified through Synopsys Case #8000711656.
 391          *
 392          * Note that the phy clock is also gated when the phy is isolated.
 393          * Phy "suspend" and "isolate" controls are located in phy basic
 394          * control register 0, and can be modified by the phy driver
 395          * framework.
 396          */
 397         if (ndev->phydev)
 398                 phy_resume(ndev->phydev);
 399
 400         return stmmac_resume(dev);
 401 }
 402 #endif /* CONFIG_PM_SLEEP */
 403
 404 static SIMPLE_DEV_PM_OPS(socfpga_dwmac_pm_ops, stmmac_suspend,
 405                                                socfpga_dwmac_resume);
 406
 407 static const struct of_device_id socfpga_dwmac_match[] = {
 408         { .compatible = "altr,socfpga-stmmac" },
 409         { }
 410 };
 411 MODULE_DEVICE_TABLE(of, socfpga_dwmac_match);
 412
 413 static struct platform_driver socfpga_dwmac_driver = {
 414         .probe  = socfpga_dwmac_probe,
 415         .remove = stmmac_pltfr_remove,
 416         .driver = {
 417                 .name           = "socfpga-dwmac",
 418                 .pm             = &socfpga_dwmac_pm_ops,
 419                 .of_match_table = socfpga_dwmac_match,
 420         },
 421 };
 422 module_platform_driver(socfpga_dwmac_driver);
 423
 424 MODULE_LICENSE("GPL v2");