drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c

   1 /*******************************************************************************
   2   This is the driver for the GMAC on-chip Ethernet controller for ST SoCs.
   3   DWC Ether MAC 10/100/1000 Universal version 3.41a  has been used for
   4   developing this code.
   5
   6   This only implements the mac core functions for this chip.
   7
   8   Copyright (C) 2007-2009  STMicroelectronics Ltd
   9
  10   This program is free software; you can redistribute it and/or modify it
  11   under the terms and conditions of the GNU General Public License,
  12   version 2, as published by the Free Software Foundation.
  13
  14   This program is distributed in the hope it will be useful, but WITHOUT
  15   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  16   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  17   more details.
  18
  19   You should have received a copy of the GNU General Public License along with
  20   this program; if not, write to the Free Software Foundation, Inc.,
  21   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  22
  23   The full GNU General Public License is included in this distribution in
  24   the file called "COPYING".
  25
  26   Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
  27 *******************************************************************************/
  28
  29 #include <linux/crc32.h>
  30 #include <linux/slab.h>
  31 #include <linux/ethtool.h>
  32 #include <asm/io.h>
  33 #include "stmmac_pcs.h"
  34 #include "dwmac1000.h"
  35
  36 static void dwmac1000_core_init(struct mac_device_info *hw, int mtu)
  37 {
  38         void __iomem *ioaddr = hw->pcsr;
  39         u32 value = readl(ioaddr + GMAC_CONTROL);
  40
  41         /* Configure GMAC core */
  42         value |= GMAC_CORE_INIT;
  43
  44         if (mtu > 1500)
  45                 value |= GMAC_CONTROL_2K;
  46         if (mtu > 2000)
  47                 value |= GMAC_CONTROL_JE;
  48
  49         if (hw->ps) {
  50                 value |= GMAC_CONTROL_TE;
  51
  52                 if (hw->ps == SPEED_1000) {
  53                         value &= ~GMAC_CONTROL_PS;
  54                 } else {
  55                         value |= GMAC_CONTROL_PS;
  56
  57                         if (hw->ps == SPEED_10)
  58                                 value &= ~GMAC_CONTROL_FES;
  59                         else
  60                                 value |= GMAC_CONTROL_FES;
  61                 }
  62         }
  63
  64         writel(value, ioaddr + GMAC_CONTROL);
  65
  66         /* Mask GMAC interrupts */
  67         value = GMAC_INT_DEFAULT_MASK;
  68
  69         if (hw->pmt)
  70                 value &= ~GMAC_INT_DISABLE_PMT;
  71         if (hw->pcs)
  72                 value &= ~GMAC_INT_DISABLE_PCS;
  73
  74         writel(value, ioaddr + GMAC_INT_MASK);
  75
  76 #ifdef STMMAC_VLAN_TAG_USED
  77         /* Tag detection without filtering */
  78         writel(0x0, ioaddr + GMAC_VLAN_TAG);
  79 #endif
  80 }
  81
  82 static int dwmac1000_rx_ipc_enable(struct mac_device_info *hw)
  83 {
  84         void __iomem *ioaddr = hw->pcsr;
  85         u32 value = readl(ioaddr + GMAC_CONTROL);
  86
  87         if (hw->rx_csum)
  88                 value |= GMAC_CONTROL_IPC;
  89         else
  90                 value &= ~GMAC_CONTROL_IPC;
  91
  92         writel(value, ioaddr + GMAC_CONTROL);
  93
  94         value = readl(ioaddr + GMAC_CONTROL);
  95
  96         return !!(value & GMAC_CONTROL_IPC);
  97 }
  98
  99 static void dwmac1000_dump_regs(struct mac_device_info *hw)
 100 {
 101         void __iomem *ioaddr = hw->pcsr;
 102         int i;
 103         pr_info("\tDWMAC1000 regs (base addr = 0x%p)\n", ioaddr);
 104
 105         for (i = 0; i < 55; i++) {
 106                 int offset = i * 4;
 107                 pr_info("\tReg No. %d (offset 0x%x): 0x%08x\n", i,
 108                         offset, readl(ioaddr + offset));
 109         }
 110 }
 111
 112 static void dwmac1000_set_umac_addr(struct mac_device_info *hw,
 113                                     unsigned char *addr,
 114                                     unsigned int reg_n)
 115 {
 116         void __iomem *ioaddr = hw->pcsr;
 117         stmmac_set_mac_addr(ioaddr, addr, GMAC_ADDR_HIGH(reg_n),
 118                             GMAC_ADDR_LOW(reg_n));
 119 }
 120
 121 static void dwmac1000_get_umac_addr(struct mac_device_info *hw,
 122                                     unsigned char *addr,
 123                                     unsigned int reg_n)
 124 {
 125         void __iomem *ioaddr = hw->pcsr;
 126         stmmac_get_mac_addr(ioaddr, addr, GMAC_ADDR_HIGH(reg_n),
 127                             GMAC_ADDR_LOW(reg_n));
 128 }
 129
 130 static void dwmac1000_set_mchash(void __iomem *ioaddr, u32 *mcfilterbits,
 131                                  int mcbitslog2)
 132 {
 133         int numhashregs, regs;
 134
 135         switch (mcbitslog2) {
 136         case 6:
 137                 writel(mcfilterbits[0], ioaddr + GMAC_HASH_LOW);
 138                 writel(mcfilterbits[1], ioaddr + GMAC_HASH_HIGH);
 139                 return;
 140                 break;
 141         case 7:
 142                 numhashregs = 4;
 143                 break;
 144         case 8:
 145                 numhashregs = 8;
 146                 break;
 147         default:
 148                 pr_debug("STMMAC: err in setting multicast filter\n");
 149                 return;
 150                 break;
 151         }
 152         for (regs = 0; regs < numhashregs; regs++)
 153                 writel(mcfilterbits[regs],
 154                        ioaddr + GMAC_EXTHASH_BASE + regs * 4);
 155 }
 156
 157 static void dwmac1000_set_filter(struct mac_device_info *hw,
 158                                  struct net_device *dev)
 159 {
 160         void __iomem *ioaddr = (void __iomem *)dev->base_addr;
 161         unsigned int value = 0;
 162         unsigned int perfect_addr_number = hw->unicast_filter_entries;
 163         u32 mc_filter[8];
 164         int mcbitslog2 = hw->mcast_bits_log2;
 165
 166         pr_debug("%s: # mcasts %d, # unicast %d\n", __func__,
 167                  netdev_mc_count(dev), netdev_uc_count(dev));
 168
 169         memset(mc_filter, 0, sizeof(mc_filter));
 170
 171         if (dev->flags & IFF_PROMISC) {
 172                 value = GMAC_FRAME_FILTER_PR;
 173         } else if (dev->flags & IFF_ALLMULTI) {
 174                 value = GMAC_FRAME_FILTER_PM;   /* pass all multi */
 175         } else if (!netdev_mc_empty(dev)) {
 176                 struct netdev_hw_addr *ha;
 177
 178                 /* Hash filter for multicast */
 179                 value = GMAC_FRAME_FILTER_HMC;
 180
 181                 netdev_for_each_mc_addr(ha, dev) {
 182                         /* The upper n bits of the calculated CRC are used to
 183                          * index the contents of the hash table. The number of
 184                          * bits used depends on the hardware configuration
 185                          * selected at core configuration time.
 186                          */
 187                         int bit_nr = bitrev32(~crc32_le(~0, ha->addr,
 188                                               ETH_ALEN)) >>
 189                                               (32 - mcbitslog2);
 190                         /* The most significant bit determines the register to
 191                          * use (H/L) while the other 5 bits determine the bit
 192                          * within the register.
 193                          */
 194                         mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
 195                 }
 196         }
 197
 198         dwmac1000_set_mchash(ioaddr, mc_filter, mcbitslog2);
 199
 200         /* Handle multiple unicast addresses (perfect filtering) */
 201         if (netdev_uc_count(dev) > perfect_addr_number)
 202                 /* Switch to promiscuous mode if more than unicast
 203                  * addresses are requested than supported by hardware.
 204                  */
 205                 value |= GMAC_FRAME_FILTER_PR;
 206         else {
 207                 int reg = 1;
 208                 struct netdev_hw_addr *ha;
 209
 210                 netdev_for_each_uc_addr(ha, dev) {
 211                         stmmac_set_mac_addr(ioaddr, ha->addr,
 212                                             GMAC_ADDR_HIGH(reg),
 213                                             GMAC_ADDR_LOW(reg));
 214                         reg++;
 215                 }
 216         }
 217
 218 #ifdef FRAME_FILTER_DEBUG
 219         /* Enable Receive all mode (to debug filtering_fail errors) */
 220         value |= GMAC_FRAME_FILTER_RA;
 221 #endif
 222         writel(value, ioaddr + GMAC_FRAME_FILTER);
 223 }
 224
 225
 226 static void dwmac1000_flow_ctrl(struct mac_device_info *hw, unsigned int duplex,
 227                                 unsigned int fc, unsigned int pause_time)
 228 {
 229         void __iomem *ioaddr = hw->pcsr;
 230         /* Set flow such that DZPQ in Mac Register 6 is 0,
 231          * and unicast pause detect is enabled.
 232          */
 233         unsigned int flow = GMAC_FLOW_CTRL_UP;
 234
 235         pr_debug("GMAC Flow-Control:\n");
 236         if (fc & FLOW_RX) {
 237                 pr_debug("\tReceive Flow-Control ON\n");
 238                 flow |= GMAC_FLOW_CTRL_RFE;
 239         }
 240         if (fc & FLOW_TX) {
 241                 pr_debug("\tTransmit Flow-Control ON\n");
 242                 flow |= GMAC_FLOW_CTRL_TFE;
 243         }
 244
 245         if (duplex) {
 246                 pr_debug("\tduplex mode: PAUSE %d\n", pause_time);
 247                 flow |= (pause_time << GMAC_FLOW_CTRL_PT_SHIFT);
 248         }
 249
 250         writel(flow, ioaddr + GMAC_FLOW_CTRL);
 251 }
 252
 253 static void dwmac1000_pmt(struct mac_device_info *hw, unsigned long mode)
 254 {
 255         void __iomem *ioaddr = hw->pcsr;
 256         unsigned int pmt = 0;
 257
 258         if (mode & WAKE_MAGIC) {
 259                 pr_debug("GMAC: WOL Magic frame\n");
 260                 pmt |= power_down | magic_pkt_en;
 261         }
 262         if (mode & WAKE_UCAST) {
 263                 pr_debug("GMAC: WOL on global unicast\n");
 264                 pmt |= power_down | global_unicast | wake_up_frame_en;
 265         }
 266
 267         writel(pmt, ioaddr + GMAC_PMT);
 268 }
 269
 270 /* RGMII or SMII interface */
 271 static void dwmac1000_rgsmii(void __iomem *ioaddr, struct stmmac_extra_stats *x)
 272 {
 273         u32 status;
 274
 275         status = readl(ioaddr + GMAC_RGSMIIIS);
 276         x->irq_rgmii_n++;
 277
 278         /* Check the link status */
 279         if (status & GMAC_RGSMIIIS_LNKSTS) {
 280                 int speed_value;
 281
 282                 x->pcs_link = 1;
 283
 284                 speed_value = ((status & GMAC_RGSMIIIS_SPEED) >>
 285                                GMAC_RGSMIIIS_SPEED_SHIFT);
 286                 if (speed_value == GMAC_RGSMIIIS_SPEED_125)
 287                         x->pcs_speed = SPEED_1000;
 288                 else if (speed_value == GMAC_RGSMIIIS_SPEED_25)
 289                         x->pcs_speed = SPEED_100;
 290                 else
 291                         x->pcs_speed = SPEED_10;
 292
 293                 x->pcs_duplex = (status & GMAC_RGSMIIIS_LNKMOD_MASK);
 294
 295                 pr_info("Link is Up - %d/%s\n", (int)x->pcs_speed,
 296                         x->pcs_duplex ? "Full" : "Half");
 297         } else {
 298                 x->pcs_link = 0;
 299                 pr_info("Link is Down\n");
 300         }
 301 }
 302
 303 static int dwmac1000_irq_status(struct mac_device_info *hw,
 304                                 struct stmmac_extra_stats *x)
 305 {
 306         void __iomem *ioaddr = hw->pcsr;
 307         u32 intr_status = readl(ioaddr + GMAC_INT_STATUS);
 308         u32 intr_mask = readl(ioaddr + GMAC_INT_MASK);
 309         int ret = 0;
 310
 311         /* Discard masked bits */
 312         intr_status &= ~intr_mask;
 313
 314         /* Not used events (e.g. MMC interrupts) are not handled. */
 315         if ((intr_status & GMAC_INT_STATUS_MMCTIS))
 316                 x->mmc_tx_irq_n++;
 317         if (unlikely(intr_status & GMAC_INT_STATUS_MMCRIS))
 318                 x->mmc_rx_irq_n++;
 319         if (unlikely(intr_status & GMAC_INT_STATUS_MMCCSUM))
 320                 x->mmc_rx_csum_offload_irq_n++;
 321         if (unlikely(intr_status & GMAC_INT_DISABLE_PMT)) {
 322                 /* clear the PMT bits 5 and 6 by reading the PMT status reg */
 323                 readl(ioaddr + GMAC_PMT);
 324                 x->irq_receive_pmt_irq_n++;
 325         }
 326
 327         /* MAC tx/rx EEE LPI entry/exit interrupts */
 328         if (intr_status & GMAC_INT_STATUS_LPIIS) {
 329                 /* Clean LPI interrupt by reading the Reg 12 */
 330                 ret = readl(ioaddr + LPI_CTRL_STATUS);
 331
 332                 if (ret & LPI_CTRL_STATUS_TLPIEN)
 333                         x->irq_tx_path_in_lpi_mode_n++;
 334                 if (ret & LPI_CTRL_STATUS_TLPIEX)
 335                         x->irq_tx_path_exit_lpi_mode_n++;
 336                 if (ret & LPI_CTRL_STATUS_RLPIEN)
 337                         x->irq_rx_path_in_lpi_mode_n++;
 338                 if (ret & LPI_CTRL_STATUS_RLPIEX)
 339                         x->irq_rx_path_exit_lpi_mode_n++;
 340         }
 341
 342         dwmac_pcs_isr(ioaddr, GMAC_PCS_BASE, intr_status, x);
 343
 344         if (intr_status & PCS_RGSMIIIS_IRQ)
 345                 dwmac1000_rgsmii(ioaddr, x);
 346
 347         return ret;
 348 }
 349
 350 static void dwmac1000_set_eee_mode(struct mac_device_info *hw)
 351 {
 352         void __iomem *ioaddr = hw->pcsr;
 353         u32 value;
 354
 355         /* Enable the link status receive on RGMII, SGMII ore SMII
 356          * receive path and instruct the transmit to enter in LPI
 357          * state.
 358          */
 359         value = readl(ioaddr + LPI_CTRL_STATUS);
 360         value |= LPI_CTRL_STATUS_LPIEN | LPI_CTRL_STATUS_LPITXA;
 361         writel(value, ioaddr + LPI_CTRL_STATUS);
 362 }
 363
 364 static void dwmac1000_reset_eee_mode(struct mac_device_info *hw)
 365 {
 366         void __iomem *ioaddr = hw->pcsr;
 367         u32 value;
 368
 369         value = readl(ioaddr + LPI_CTRL_STATUS);
 370         value &= ~(LPI_CTRL_STATUS_LPIEN | LPI_CTRL_STATUS_LPITXA);
 371         writel(value, ioaddr + LPI_CTRL_STATUS);
 372 }
 373
 374 static void dwmac1000_set_eee_pls(struct mac_device_info *hw, int link)
 375 {
 376         void __iomem *ioaddr = hw->pcsr;
 377         u32 value;
 378
 379         value = readl(ioaddr + LPI_CTRL_STATUS);
 380
 381         if (link)
 382                 value |= LPI_CTRL_STATUS_PLS;
 383         else
 384                 value &= ~LPI_CTRL_STATUS_PLS;
 385
 386         writel(value, ioaddr + LPI_CTRL_STATUS);
 387 }
 388
 389 static void dwmac1000_set_eee_timer(struct mac_device_info *hw, int ls, int tw)
 390 {
 391         void __iomem *ioaddr = hw->pcsr;
 392         int value = ((tw & 0xffff)) | ((ls & 0x7ff) << 16);
 393
 394         /* Program the timers in the LPI timer control register:
 395          * LS: minimum time (ms) for which the link
 396          *  status from PHY should be ok before transmitting
 397          *  the LPI pattern.
 398          * TW: minimum time (us) for which the core waits
 399          *  after it has stopped transmitting the LPI pattern.
 400          */
 401         writel(value, ioaddr + LPI_TIMER_CTRL);
 402 }
 403
 404 static void dwmac1000_ctrl_ane(void __iomem *ioaddr, bool ane, bool srgmi_ral,
 405                                bool loopback)
 406 {
 407         dwmac_ctrl_ane(ioaddr, GMAC_PCS_BASE, ane, srgmi_ral, loopback);
 408 }
 409
 410 static void dwmac1000_rane(void __iomem *ioaddr, bool restart)
 411 {
 412         dwmac_rane(ioaddr, GMAC_PCS_BASE, restart);
 413 }
 414
 415 static void dwmac1000_get_adv_lp(void __iomem *ioaddr, struct rgmii_adv *adv)
 416 {
 417         dwmac_get_adv_lp(ioaddr, GMAC_PCS_BASE, adv);
 418 }
 419
 420 static void dwmac1000_debug(void __iomem *ioaddr, struct stmmac_extra_stats *x)
 421 {
 422         u32 value = readl(ioaddr + GMAC_DEBUG);
 423
 424         if (value & GMAC_DEBUG_TXSTSFSTS)
 425                 x->mtl_tx_status_fifo_full++;
 426         if (value & GMAC_DEBUG_TXFSTS)
 427                 x->mtl_tx_fifo_not_empty++;
 428         if (value & GMAC_DEBUG_TWCSTS)
 429                 x->mmtl_fifo_ctrl++;
 430         if (value & GMAC_DEBUG_TRCSTS_MASK) {
 431                 u32 trcsts = (value & GMAC_DEBUG_TRCSTS_MASK)
 432                              >> GMAC_DEBUG_TRCSTS_SHIFT;
 433                 if (trcsts == GMAC_DEBUG_TRCSTS_WRITE)
 434                         x->mtl_tx_fifo_read_ctrl_write++;
 435                 else if (trcsts == GMAC_DEBUG_TRCSTS_TXW)
 436                         x->mtl_tx_fifo_read_ctrl_wait++;
 437                 else if (trcsts == GMAC_DEBUG_TRCSTS_READ)
 438                         x->mtl_tx_fifo_read_ctrl_read++;
 439                 else
 440                         x->mtl_tx_fifo_read_ctrl_idle++;
 441         }
 442         if (value & GMAC_DEBUG_TXPAUSED)
 443                 x->mac_tx_in_pause++;
 444         if (value & GMAC_DEBUG_TFCSTS_MASK) {
 445                 u32 tfcsts = (value & GMAC_DEBUG_TFCSTS_MASK)
 446                               >> GMAC_DEBUG_TFCSTS_SHIFT;
 447
 448                 if (tfcsts == GMAC_DEBUG_TFCSTS_XFER)
 449                         x->mac_tx_frame_ctrl_xfer++;
 450                 else if (tfcsts == GMAC_DEBUG_TFCSTS_GEN_PAUSE)
 451                         x->mac_tx_frame_ctrl_pause++;
 452                 else if (tfcsts == GMAC_DEBUG_TFCSTS_WAIT)
 453                         x->mac_tx_frame_ctrl_wait++;
 454                 else
 455                         x->mac_tx_frame_ctrl_idle++;
 456         }
 457         if (value & GMAC_DEBUG_TPESTS)
 458                 x->mac_gmii_tx_proto_engine++;
 459         if (value & GMAC_DEBUG_RXFSTS_MASK) {
 460                 u32 rxfsts = (value & GMAC_DEBUG_RXFSTS_MASK)
 461                              >> GMAC_DEBUG_RRCSTS_SHIFT;
 462
 463                 if (rxfsts == GMAC_DEBUG_RXFSTS_FULL)
 464                         x->mtl_rx_fifo_fill_level_full++;
 465                 else if (rxfsts == GMAC_DEBUG_RXFSTS_AT)
 466                         x->mtl_rx_fifo_fill_above_thresh++;
 467                 else if (rxfsts == GMAC_DEBUG_RXFSTS_BT)
 468                         x->mtl_rx_fifo_fill_below_thresh++;
 469                 else
 470                         x->mtl_rx_fifo_fill_level_empty++;
 471         }
 472         if (value & GMAC_DEBUG_RRCSTS_MASK) {
 473                 u32 rrcsts = (value & GMAC_DEBUG_RRCSTS_MASK) >>
 474                              GMAC_DEBUG_RRCSTS_SHIFT;
 475
 476                 if (rrcsts == GMAC_DEBUG_RRCSTS_FLUSH)
 477                         x->mtl_rx_fifo_read_ctrl_flush++;
 478                 else if (rrcsts == GMAC_DEBUG_RRCSTS_RSTAT)
 479                         x->mtl_rx_fifo_read_ctrl_read_data++;
 480                 else if (rrcsts == GMAC_DEBUG_RRCSTS_RDATA)
 481                         x->mtl_rx_fifo_read_ctrl_status++;
 482                 else
 483                         x->mtl_rx_fifo_read_ctrl_idle++;
 484         }
 485         if (value & GMAC_DEBUG_RWCSTS)
 486                 x->mtl_rx_fifo_ctrl_active++;
 487         if (value & GMAC_DEBUG_RFCFCSTS_MASK)
 488                 x->mac_rx_frame_ctrl_fifo = (value & GMAC_DEBUG_RFCFCSTS_MASK)
 489                                             >> GMAC_DEBUG_RFCFCSTS_SHIFT;
 490         if (value & GMAC_DEBUG_RPESTS)
 491                 x->mac_gmii_rx_proto_engine++;
 492 }
 493
 494 static const struct stmmac_ops dwmac1000_ops = {
 495         .core_init = dwmac1000_core_init,
 496         .rx_ipc = dwmac1000_rx_ipc_enable,
 497         .dump_regs = dwmac1000_dump_regs,
 498         .host_irq_status = dwmac1000_irq_status,
 499         .set_filter = dwmac1000_set_filter,
 500         .flow_ctrl = dwmac1000_flow_ctrl,
 501         .pmt = dwmac1000_pmt,
 502         .set_umac_addr = dwmac1000_set_umac_addr,
 503         .get_umac_addr = dwmac1000_get_umac_addr,
 504         .set_eee_mode = dwmac1000_set_eee_mode,
 505         .reset_eee_mode = dwmac1000_reset_eee_mode,
 506         .set_eee_timer = dwmac1000_set_eee_timer,
 507         .set_eee_pls = dwmac1000_set_eee_pls,
 508         .debug = dwmac1000_debug,
 509         .pcs_ctrl_ane = dwmac1000_ctrl_ane,
 510         .pcs_rane = dwmac1000_rane,
 511         .pcs_get_adv_lp = dwmac1000_get_adv_lp,
 512 };
 513
 514 struct mac_device_info *dwmac1000_setup(void __iomem *ioaddr, int mcbins,
 515                                         int perfect_uc_entries,
 516                                         int *synopsys_id)
 517 {
 518         struct mac_device_info *mac;
 519         u32 hwid = readl(ioaddr + GMAC_VERSION);
 520
 521         mac = kzalloc(sizeof(const struct mac_device_info), GFP_KERNEL);
 522         if (!mac)
 523                 return NULL;
 524
 525         mac->pcsr = ioaddr;
 526         mac->multicast_filter_bins = mcbins;
 527         mac->unicast_filter_entries = perfect_uc_entries;
 528         mac->mcast_bits_log2 = 0;
 529
 530         if (mac->multicast_filter_bins)
 531                 mac->mcast_bits_log2 = ilog2(mac->multicast_filter_bins);
 532
 533         mac->mac = &dwmac1000_ops;
 534         mac->dma = &dwmac1000_dma_ops;
 535
 536         mac->link.port = GMAC_CONTROL_PS;
 537         mac->link.duplex = GMAC_CONTROL_DM;
 538         mac->link.speed = GMAC_CONTROL_FES;
 539         mac->mii.addr = GMAC_MII_ADDR;
 540         mac->mii.data = GMAC_MII_DATA;
 541         mac->mii.addr_shift = 11;
 542         mac->mii.addr_mask = 0x0000F800;
 543         mac->mii.reg_shift = 6;
 544         mac->mii.reg_mask = 0x000007C0;
 545         mac->mii.clk_csr_shift = 2;
 546         mac->mii.clk_csr_mask = GENMASK(5, 2);
 547
 548         /* Get and dump the chip ID */
 549         *synopsys_id = stmmac_get_synopsys_id(hwid);
 550
 551         return mac;
 552 }