1 /*******************************************************************************
2 This is the driver for the GMAC on-chip Ethernet controller for ST SoCs.
3 DWC Ether MAC 10/100/1000 Universal version 3.41a has been used for
6 This only implements the mac core functions for this chip.
8 Copyright (C) 2007-2009 STMicroelectronics Ltd
10 This program is free software; you can redistribute it and/or modify it
11 under the terms and conditions of the GNU General Public License,
12 version 2, as published by the Free Software Foundation.
14 This program is distributed in the hope it will be useful, but WITHOUT
15 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 You should have received a copy of the GNU General Public License along with
20 this program; if not, write to the Free Software Foundation, Inc.,
21 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
23 The full GNU General Public License is included in this distribution in
24 the file called "COPYING".
26 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
27 *******************************************************************************/
29 #include <linux/crc32.h>
30 #include <linux/slab.h>
31 #include <linux/ethtool.h>
33 #include "stmmac_pcs.h"
34 #include "dwmac1000.h"
36 static void dwmac1000_core_init(struct mac_device_info *hw, int mtu)
38 void __iomem *ioaddr = hw->pcsr;
39 u32 value = readl(ioaddr + GMAC_CONTROL);
41 /* Configure GMAC core */
42 value |= GMAC_CORE_INIT;
45 value |= GMAC_CONTROL_2K;
47 value |= GMAC_CONTROL_JE;
50 value |= GMAC_CONTROL_TE;
52 if (hw->ps == SPEED_1000) {
53 value &= ~GMAC_CONTROL_PS;
55 value |= GMAC_CONTROL_PS;
57 if (hw->ps == SPEED_10)
58 value &= ~GMAC_CONTROL_FES;
60 value |= GMAC_CONTROL_FES;
64 writel(value, ioaddr + GMAC_CONTROL);
66 /* Mask GMAC interrupts */
67 value = GMAC_INT_DEFAULT_MASK;
70 value &= ~GMAC_INT_DISABLE_PMT;
72 value &= ~GMAC_INT_DISABLE_PCS;
74 writel(value, ioaddr + GMAC_INT_MASK);
76 #ifdef STMMAC_VLAN_TAG_USED
77 /* Tag detection without filtering */
78 writel(0x0, ioaddr + GMAC_VLAN_TAG);
82 static int dwmac1000_rx_ipc_enable(struct mac_device_info *hw)
84 void __iomem *ioaddr = hw->pcsr;
85 u32 value = readl(ioaddr + GMAC_CONTROL);
88 value |= GMAC_CONTROL_IPC;
90 value &= ~GMAC_CONTROL_IPC;
92 writel(value, ioaddr + GMAC_CONTROL);
94 value = readl(ioaddr + GMAC_CONTROL);
96 return !!(value & GMAC_CONTROL_IPC);
99 static void dwmac1000_dump_regs(struct mac_device_info *hw)
101 void __iomem *ioaddr = hw->pcsr;
103 pr_info("\tDWMAC1000 regs (base addr = 0x%p)\n", ioaddr);
105 for (i = 0; i < 55; i++) {
107 pr_info("\tReg No. %d (offset 0x%x): 0x%08x\n", i,
108 offset, readl(ioaddr + offset));
112 static void dwmac1000_set_umac_addr(struct mac_device_info *hw,
116 void __iomem *ioaddr = hw->pcsr;
117 stmmac_set_mac_addr(ioaddr, addr, GMAC_ADDR_HIGH(reg_n),
118 GMAC_ADDR_LOW(reg_n));
121 static void dwmac1000_get_umac_addr(struct mac_device_info *hw,
125 void __iomem *ioaddr = hw->pcsr;
126 stmmac_get_mac_addr(ioaddr, addr, GMAC_ADDR_HIGH(reg_n),
127 GMAC_ADDR_LOW(reg_n));
130 static void dwmac1000_set_mchash(void __iomem *ioaddr, u32 *mcfilterbits,
133 int numhashregs, regs;
135 switch (mcbitslog2) {
137 writel(mcfilterbits[0], ioaddr + GMAC_HASH_LOW);
138 writel(mcfilterbits[1], ioaddr + GMAC_HASH_HIGH);
148 pr_debug("STMMAC: err in setting multicast filter\n");
152 for (regs = 0; regs < numhashregs; regs++)
153 writel(mcfilterbits[regs],
154 ioaddr + GMAC_EXTHASH_BASE + regs * 4);
157 static void dwmac1000_set_filter(struct mac_device_info *hw,
158 struct net_device *dev)
160 void __iomem *ioaddr = (void __iomem *)dev->base_addr;
161 unsigned int value = 0;
162 unsigned int perfect_addr_number = hw->unicast_filter_entries;
164 int mcbitslog2 = hw->mcast_bits_log2;
166 pr_debug("%s: # mcasts %d, # unicast %d\n", __func__,
167 netdev_mc_count(dev), netdev_uc_count(dev));
169 memset(mc_filter, 0, sizeof(mc_filter));
171 if (dev->flags & IFF_PROMISC) {
172 value = GMAC_FRAME_FILTER_PR;
173 } else if (dev->flags & IFF_ALLMULTI) {
174 value = GMAC_FRAME_FILTER_PM; /* pass all multi */
175 } else if (!netdev_mc_empty(dev)) {
176 struct netdev_hw_addr *ha;
178 /* Hash filter for multicast */
179 value = GMAC_FRAME_FILTER_HMC;
181 netdev_for_each_mc_addr(ha, dev) {
182 /* The upper n bits of the calculated CRC are used to
183 * index the contents of the hash table. The number of
184 * bits used depends on the hardware configuration
185 * selected at core configuration time.
187 int bit_nr = bitrev32(~crc32_le(~0, ha->addr,
190 /* The most significant bit determines the register to
191 * use (H/L) while the other 5 bits determine the bit
192 * within the register.
194 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
198 dwmac1000_set_mchash(ioaddr, mc_filter, mcbitslog2);
200 /* Handle multiple unicast addresses (perfect filtering) */
201 if (netdev_uc_count(dev) > perfect_addr_number)
202 /* Switch to promiscuous mode if more than unicast
203 * addresses are requested than supported by hardware.
205 value |= GMAC_FRAME_FILTER_PR;
208 struct netdev_hw_addr *ha;
210 netdev_for_each_uc_addr(ha, dev) {
211 stmmac_set_mac_addr(ioaddr, ha->addr,
218 #ifdef FRAME_FILTER_DEBUG
219 /* Enable Receive all mode (to debug filtering_fail errors) */
220 value |= GMAC_FRAME_FILTER_RA;
222 writel(value, ioaddr + GMAC_FRAME_FILTER);
226 static void dwmac1000_flow_ctrl(struct mac_device_info *hw, unsigned int duplex,
227 unsigned int fc, unsigned int pause_time)
229 void __iomem *ioaddr = hw->pcsr;
230 /* Set flow such that DZPQ in Mac Register 6 is 0,
231 * and unicast pause detect is enabled.
233 unsigned int flow = GMAC_FLOW_CTRL_UP;
235 pr_debug("GMAC Flow-Control:\n");
237 pr_debug("\tReceive Flow-Control ON\n");
238 flow |= GMAC_FLOW_CTRL_RFE;
241 pr_debug("\tTransmit Flow-Control ON\n");
242 flow |= GMAC_FLOW_CTRL_TFE;
246 pr_debug("\tduplex mode: PAUSE %d\n", pause_time);
247 flow |= (pause_time << GMAC_FLOW_CTRL_PT_SHIFT);
250 writel(flow, ioaddr + GMAC_FLOW_CTRL);
253 static void dwmac1000_pmt(struct mac_device_info *hw, unsigned long mode)
255 void __iomem *ioaddr = hw->pcsr;
256 unsigned int pmt = 0;
258 if (mode & WAKE_MAGIC) {
259 pr_debug("GMAC: WOL Magic frame\n");
260 pmt |= power_down | magic_pkt_en;
262 if (mode & WAKE_UCAST) {
263 pr_debug("GMAC: WOL on global unicast\n");
264 pmt |= power_down | global_unicast | wake_up_frame_en;
267 writel(pmt, ioaddr + GMAC_PMT);
270 /* RGMII or SMII interface */
271 static void dwmac1000_rgsmii(void __iomem *ioaddr, struct stmmac_extra_stats *x)
275 status = readl(ioaddr + GMAC_RGSMIIIS);
278 /* Check the link status */
279 if (status & GMAC_RGSMIIIS_LNKSTS) {
284 speed_value = ((status & GMAC_RGSMIIIS_SPEED) >>
285 GMAC_RGSMIIIS_SPEED_SHIFT);
286 if (speed_value == GMAC_RGSMIIIS_SPEED_125)
287 x->pcs_speed = SPEED_1000;
288 else if (speed_value == GMAC_RGSMIIIS_SPEED_25)
289 x->pcs_speed = SPEED_100;
291 x->pcs_speed = SPEED_10;
293 x->pcs_duplex = (status & GMAC_RGSMIIIS_LNKMOD_MASK);
295 pr_info("Link is Up - %d/%s\n", (int)x->pcs_speed,
296 x->pcs_duplex ? "Full" : "Half");
299 pr_info("Link is Down\n");
303 static int dwmac1000_irq_status(struct mac_device_info *hw,
304 struct stmmac_extra_stats *x)
306 void __iomem *ioaddr = hw->pcsr;
307 u32 intr_status = readl(ioaddr + GMAC_INT_STATUS);
308 u32 intr_mask = readl(ioaddr + GMAC_INT_MASK);
311 /* Discard masked bits */
312 intr_status &= ~intr_mask;
314 /* Not used events (e.g. MMC interrupts) are not handled. */
315 if ((intr_status & GMAC_INT_STATUS_MMCTIS))
317 if (unlikely(intr_status & GMAC_INT_STATUS_MMCRIS))
319 if (unlikely(intr_status & GMAC_INT_STATUS_MMCCSUM))
320 x->mmc_rx_csum_offload_irq_n++;
321 if (unlikely(intr_status & GMAC_INT_DISABLE_PMT)) {
322 /* clear the PMT bits 5 and 6 by reading the PMT status reg */
323 readl(ioaddr + GMAC_PMT);
324 x->irq_receive_pmt_irq_n++;
327 /* MAC tx/rx EEE LPI entry/exit interrupts */
328 if (intr_status & GMAC_INT_STATUS_LPIIS) {
329 /* Clean LPI interrupt by reading the Reg 12 */
330 ret = readl(ioaddr + LPI_CTRL_STATUS);
332 if (ret & LPI_CTRL_STATUS_TLPIEN)
333 x->irq_tx_path_in_lpi_mode_n++;
334 if (ret & LPI_CTRL_STATUS_TLPIEX)
335 x->irq_tx_path_exit_lpi_mode_n++;
336 if (ret & LPI_CTRL_STATUS_RLPIEN)
337 x->irq_rx_path_in_lpi_mode_n++;
338 if (ret & LPI_CTRL_STATUS_RLPIEX)
339 x->irq_rx_path_exit_lpi_mode_n++;
342 dwmac_pcs_isr(ioaddr, GMAC_PCS_BASE, intr_status, x);
344 if (intr_status & PCS_RGSMIIIS_IRQ)
345 dwmac1000_rgsmii(ioaddr, x);
350 static void dwmac1000_set_eee_mode(struct mac_device_info *hw)
352 void __iomem *ioaddr = hw->pcsr;
355 /* Enable the link status receive on RGMII, SGMII ore SMII
356 * receive path and instruct the transmit to enter in LPI
359 value = readl(ioaddr + LPI_CTRL_STATUS);
360 value |= LPI_CTRL_STATUS_LPIEN | LPI_CTRL_STATUS_LPITXA;
361 writel(value, ioaddr + LPI_CTRL_STATUS);
364 static void dwmac1000_reset_eee_mode(struct mac_device_info *hw)
366 void __iomem *ioaddr = hw->pcsr;
369 value = readl(ioaddr + LPI_CTRL_STATUS);
370 value &= ~(LPI_CTRL_STATUS_LPIEN | LPI_CTRL_STATUS_LPITXA);
371 writel(value, ioaddr + LPI_CTRL_STATUS);
374 static void dwmac1000_set_eee_pls(struct mac_device_info *hw, int link)
376 void __iomem *ioaddr = hw->pcsr;
379 value = readl(ioaddr + LPI_CTRL_STATUS);
382 value |= LPI_CTRL_STATUS_PLS;
384 value &= ~LPI_CTRL_STATUS_PLS;
386 writel(value, ioaddr + LPI_CTRL_STATUS);
389 static void dwmac1000_set_eee_timer(struct mac_device_info *hw, int ls, int tw)
391 void __iomem *ioaddr = hw->pcsr;
392 int value = ((tw & 0xffff)) | ((ls & 0x7ff) << 16);
394 /* Program the timers in the LPI timer control register:
395 * LS: minimum time (ms) for which the link
396 * status from PHY should be ok before transmitting
398 * TW: minimum time (us) for which the core waits
399 * after it has stopped transmitting the LPI pattern.
401 writel(value, ioaddr + LPI_TIMER_CTRL);
404 static void dwmac1000_ctrl_ane(void __iomem *ioaddr, bool ane, bool srgmi_ral,
407 dwmac_ctrl_ane(ioaddr, GMAC_PCS_BASE, ane, srgmi_ral, loopback);
410 static void dwmac1000_rane(void __iomem *ioaddr, bool restart)
412 dwmac_rane(ioaddr, GMAC_PCS_BASE, restart);
415 static void dwmac1000_get_adv_lp(void __iomem *ioaddr, struct rgmii_adv *adv)
417 dwmac_get_adv_lp(ioaddr, GMAC_PCS_BASE, adv);
420 static void dwmac1000_debug(void __iomem *ioaddr, struct stmmac_extra_stats *x)
422 u32 value = readl(ioaddr + GMAC_DEBUG);
424 if (value & GMAC_DEBUG_TXSTSFSTS)
425 x->mtl_tx_status_fifo_full++;
426 if (value & GMAC_DEBUG_TXFSTS)
427 x->mtl_tx_fifo_not_empty++;
428 if (value & GMAC_DEBUG_TWCSTS)
430 if (value & GMAC_DEBUG_TRCSTS_MASK) {
431 u32 trcsts = (value & GMAC_DEBUG_TRCSTS_MASK)
432 >> GMAC_DEBUG_TRCSTS_SHIFT;
433 if (trcsts == GMAC_DEBUG_TRCSTS_WRITE)
434 x->mtl_tx_fifo_read_ctrl_write++;
435 else if (trcsts == GMAC_DEBUG_TRCSTS_TXW)
436 x->mtl_tx_fifo_read_ctrl_wait++;
437 else if (trcsts == GMAC_DEBUG_TRCSTS_READ)
438 x->mtl_tx_fifo_read_ctrl_read++;
440 x->mtl_tx_fifo_read_ctrl_idle++;
442 if (value & GMAC_DEBUG_TXPAUSED)
443 x->mac_tx_in_pause++;
444 if (value & GMAC_DEBUG_TFCSTS_MASK) {
445 u32 tfcsts = (value & GMAC_DEBUG_TFCSTS_MASK)
446 >> GMAC_DEBUG_TFCSTS_SHIFT;
448 if (tfcsts == GMAC_DEBUG_TFCSTS_XFER)
449 x->mac_tx_frame_ctrl_xfer++;
450 else if (tfcsts == GMAC_DEBUG_TFCSTS_GEN_PAUSE)
451 x->mac_tx_frame_ctrl_pause++;
452 else if (tfcsts == GMAC_DEBUG_TFCSTS_WAIT)
453 x->mac_tx_frame_ctrl_wait++;
455 x->mac_tx_frame_ctrl_idle++;
457 if (value & GMAC_DEBUG_TPESTS)
458 x->mac_gmii_tx_proto_engine++;
459 if (value & GMAC_DEBUG_RXFSTS_MASK) {
460 u32 rxfsts = (value & GMAC_DEBUG_RXFSTS_MASK)
461 >> GMAC_DEBUG_RRCSTS_SHIFT;
463 if (rxfsts == GMAC_DEBUG_RXFSTS_FULL)
464 x->mtl_rx_fifo_fill_level_full++;
465 else if (rxfsts == GMAC_DEBUG_RXFSTS_AT)
466 x->mtl_rx_fifo_fill_above_thresh++;
467 else if (rxfsts == GMAC_DEBUG_RXFSTS_BT)
468 x->mtl_rx_fifo_fill_below_thresh++;
470 x->mtl_rx_fifo_fill_level_empty++;
472 if (value & GMAC_DEBUG_RRCSTS_MASK) {
473 u32 rrcsts = (value & GMAC_DEBUG_RRCSTS_MASK) >>
474 GMAC_DEBUG_RRCSTS_SHIFT;
476 if (rrcsts == GMAC_DEBUG_RRCSTS_FLUSH)
477 x->mtl_rx_fifo_read_ctrl_flush++;
478 else if (rrcsts == GMAC_DEBUG_RRCSTS_RSTAT)
479 x->mtl_rx_fifo_read_ctrl_read_data++;
480 else if (rrcsts == GMAC_DEBUG_RRCSTS_RDATA)
481 x->mtl_rx_fifo_read_ctrl_status++;
483 x->mtl_rx_fifo_read_ctrl_idle++;
485 if (value & GMAC_DEBUG_RWCSTS)
486 x->mtl_rx_fifo_ctrl_active++;
487 if (value & GMAC_DEBUG_RFCFCSTS_MASK)
488 x->mac_rx_frame_ctrl_fifo = (value & GMAC_DEBUG_RFCFCSTS_MASK)
489 >> GMAC_DEBUG_RFCFCSTS_SHIFT;
490 if (value & GMAC_DEBUG_RPESTS)
491 x->mac_gmii_rx_proto_engine++;
494 static const struct stmmac_ops dwmac1000_ops = {
495 .core_init = dwmac1000_core_init,
496 .rx_ipc = dwmac1000_rx_ipc_enable,
497 .dump_regs = dwmac1000_dump_regs,
498 .host_irq_status = dwmac1000_irq_status,
499 .set_filter = dwmac1000_set_filter,
500 .flow_ctrl = dwmac1000_flow_ctrl,
501 .pmt = dwmac1000_pmt,
502 .set_umac_addr = dwmac1000_set_umac_addr,
503 .get_umac_addr = dwmac1000_get_umac_addr,
504 .set_eee_mode = dwmac1000_set_eee_mode,
505 .reset_eee_mode = dwmac1000_reset_eee_mode,
506 .set_eee_timer = dwmac1000_set_eee_timer,
507 .set_eee_pls = dwmac1000_set_eee_pls,
508 .debug = dwmac1000_debug,
509 .pcs_ctrl_ane = dwmac1000_ctrl_ane,
510 .pcs_rane = dwmac1000_rane,
511 .pcs_get_adv_lp = dwmac1000_get_adv_lp,
514 struct mac_device_info *dwmac1000_setup(void __iomem *ioaddr, int mcbins,
515 int perfect_uc_entries,
518 struct mac_device_info *mac;
519 u32 hwid = readl(ioaddr + GMAC_VERSION);
521 mac = kzalloc(sizeof(const struct mac_device_info), GFP_KERNEL);
526 mac->multicast_filter_bins = mcbins;
527 mac->unicast_filter_entries = perfect_uc_entries;
528 mac->mcast_bits_log2 = 0;
530 if (mac->multicast_filter_bins)
531 mac->mcast_bits_log2 = ilog2(mac->multicast_filter_bins);
533 mac->mac = &dwmac1000_ops;
534 mac->dma = &dwmac1000_dma_ops;
536 mac->link.port = GMAC_CONTROL_PS;
537 mac->link.duplex = GMAC_CONTROL_DM;
538 mac->link.speed = GMAC_CONTROL_FES;
539 mac->mii.addr = GMAC_MII_ADDR;
540 mac->mii.data = GMAC_MII_DATA;
541 mac->mii.addr_shift = 11;
542 mac->mii.addr_mask = 0x0000F800;
543 mac->mii.reg_shift = 6;
544 mac->mii.reg_mask = 0x000007C0;
545 mac->mii.clk_csr_shift = 2;
546 mac->mii.clk_csr_mask = GENMASK(5, 2);
548 /* Get and dump the chip ID */
549 *synopsys_id = stmmac_get_synopsys_id(hwid);