drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*******************************************************************************
   3   This is the driver for the GMAC on-chip Ethernet controller for ST SoCs.
   4   DWC Ether MAC 10/100/1000 Universal version 3.41a  has been used for
   5   developing this code.
   6
   7   This only implements the mac core functions for this chip.
   8
   9   Copyright (C) 2007-2009  STMicroelectronics Ltd
  10
  11
  12   Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
  13 *******************************************************************************/
  14
  15 #include <linux/crc32.h>
  16 #include <linux/slab.h>
  17 #include <linux/ethtool.h>
  18 #include <net/dsa.h>
  19 #include <asm/io.h>
  20 #include "stmmac.h"
  21 #include "stmmac_pcs.h"
  22 #include "dwmac1000.h"
  23
  24 static void dwmac1000_core_init(struct mac_device_info *hw,
  25                                 struct net_device *dev)
  26 {
  27         struct stmmac_priv *priv = netdev_priv(dev);
  28         void __iomem *ioaddr = hw->pcsr;
  29         u32 value = readl(ioaddr + GMAC_CONTROL);
  30         int mtu = dev->mtu;
  31
  32         /* Configure GMAC core */
  33         value |= GMAC_CORE_INIT;
  34
  35         /* Clear ACS bit because Ethernet switch tagging formats such as
  36          * Broadcom tags can look like invalid LLC/SNAP packets and cause the
  37          * hardware to truncate packets on reception.
  38          */
  39         if (netdev_uses_dsa(dev) || !priv->plat->enh_desc)
  40                 value &= ~GMAC_CONTROL_ACS;
  41
  42         if (mtu > 1500)
  43                 value |= GMAC_CONTROL_2K;
  44         if (mtu > 2000)
  45                 value |= GMAC_CONTROL_JE;
  46
  47         if (hw->ps) {
  48                 value |= GMAC_CONTROL_TE;
  49
  50                 value &= ~hw->link.speed_mask;
  51                 switch (hw->ps) {
  52                 case SPEED_1000:
  53                         value |= hw->link.speed1000;
  54                         break;
  55                 case SPEED_100:
  56                         value |= hw->link.speed100;
  57                         break;
  58                 case SPEED_10:
  59                         value |= hw->link.speed10;
  60                         break;
  61                 }
  62         }
  63
  64         writel(value, ioaddr + GMAC_CONTROL);
  65
  66         /* Mask GMAC interrupts */
  67         value = GMAC_INT_DEFAULT_MASK;
  68
  69         if (hw->pcs)
  70                 value &= ~GMAC_INT_DISABLE_PCS;
  71
  72         writel(value, ioaddr + GMAC_INT_MASK);
  73
  74 #ifdef STMMAC_VLAN_TAG_USED
  75         /* Tag detection without filtering */
  76         writel(0x0, ioaddr + GMAC_VLAN_TAG);
  77 #endif
  78 }
  79
  80 static int dwmac1000_rx_ipc_enable(struct mac_device_info *hw)
  81 {
  82         void __iomem *ioaddr = hw->pcsr;
  83         u32 value = readl(ioaddr + GMAC_CONTROL);
  84
  85         if (hw->rx_csum)
  86                 value |= GMAC_CONTROL_IPC;
  87         else
  88                 value &= ~GMAC_CONTROL_IPC;
  89
  90         writel(value, ioaddr + GMAC_CONTROL);
  91
  92         value = readl(ioaddr + GMAC_CONTROL);
  93
  94         return !!(value & GMAC_CONTROL_IPC);
  95 }
  96
  97 static void dwmac1000_dump_regs(struct mac_device_info *hw, u32 *reg_space)
  98 {
  99         void __iomem *ioaddr = hw->pcsr;
 100         int i;
 101
 102         for (i = 0; i < 55; i++)
 103                 reg_space[i] = readl(ioaddr + i * 4);
 104 }
 105
 106 static void dwmac1000_set_umac_addr(struct mac_device_info *hw,
 107                                     unsigned char *addr,
 108                                     unsigned int reg_n)
 109 {
 110         void __iomem *ioaddr = hw->pcsr;
 111         stmmac_set_mac_addr(ioaddr, addr, GMAC_ADDR_HIGH(reg_n),
 112                             GMAC_ADDR_LOW(reg_n));
 113 }
 114
 115 static void dwmac1000_get_umac_addr(struct mac_device_info *hw,
 116                                     unsigned char *addr,
 117                                     unsigned int reg_n)
 118 {
 119         void __iomem *ioaddr = hw->pcsr;
 120         stmmac_get_mac_addr(ioaddr, addr, GMAC_ADDR_HIGH(reg_n),
 121                             GMAC_ADDR_LOW(reg_n));
 122 }
 123
 124 static void dwmac1000_set_mchash(void __iomem *ioaddr, u32 *mcfilterbits,
 125                                  int mcbitslog2)
 126 {
 127         int numhashregs, regs;
 128
 129         switch (mcbitslog2) {
 130         case 6:
 131                 writel(mcfilterbits[0], ioaddr + GMAC_HASH_LOW);
 132                 writel(mcfilterbits[1], ioaddr + GMAC_HASH_HIGH);
 133                 return;
 134         case 7:
 135                 numhashregs = 4;
 136                 break;
 137         case 8:
 138                 numhashregs = 8;
 139                 break;
 140         default:
 141                 pr_debug("STMMAC: err in setting multicast filter\n");
 142                 return;
 143         }
 144         for (regs = 0; regs < numhashregs; regs++)
 145                 writel(mcfilterbits[regs],
 146                        ioaddr + GMAC_EXTHASH_BASE + regs * 4);
 147 }
 148
 149 static void dwmac1000_set_filter(struct mac_device_info *hw,
 150                                  struct net_device *dev)
 151 {
 152         void __iomem *ioaddr = (void __iomem *)dev->base_addr;
 153         unsigned int value = 0;
 154         unsigned int perfect_addr_number = hw->unicast_filter_entries;
 155         u32 mc_filter[8];
 156         int mcbitslog2 = hw->mcast_bits_log2;
 157
 158         pr_debug("%s: # mcasts %d, # unicast %d\n", __func__,
 159                  netdev_mc_count(dev), netdev_uc_count(dev));
 160
 161         memset(mc_filter, 0, sizeof(mc_filter));
 162
 163         if (dev->flags & IFF_PROMISC) {
 164                 value = GMAC_FRAME_FILTER_PR | GMAC_FRAME_FILTER_PCF;
 165         } else if (dev->flags & IFF_ALLMULTI) {
 166                 value = GMAC_FRAME_FILTER_PM;   /* pass all multi */
 167         } else if (!netdev_mc_empty(dev)) {
 168                 struct netdev_hw_addr *ha;
 169
 170                 /* Hash filter for multicast */
 171                 value = GMAC_FRAME_FILTER_HMC;
 172
 173                 netdev_for_each_mc_addr(ha, dev) {
 174                         /* The upper n bits of the calculated CRC are used to
 175                          * index the contents of the hash table. The number of
 176                          * bits used depends on the hardware configuration
 177                          * selected at core configuration time.
 178                          */
 179                         int bit_nr = bitrev32(~crc32_le(~0, ha->addr,
 180                                               ETH_ALEN)) >>
 181                                               (32 - mcbitslog2);
 182                         /* The most significant bit determines the register to
 183                          * use (H/L) while the other 5 bits determine the bit
 184                          * within the register.
 185                          */
 186                         mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
 187                 }
 188         }
 189
 190         value |= GMAC_FRAME_FILTER_HPF;
 191         dwmac1000_set_mchash(ioaddr, mc_filter, mcbitslog2);
 192
 193         /* Handle multiple unicast addresses (perfect filtering) */
 194         if (netdev_uc_count(dev) > perfect_addr_number)
 195                 /* Switch to promiscuous mode if more than unicast
 196                  * addresses are requested than supported by hardware.
 197                  */
 198                 value |= GMAC_FRAME_FILTER_PR;
 199         else {
 200                 int reg = 1;
 201                 struct netdev_hw_addr *ha;
 202
 203                 netdev_for_each_uc_addr(ha, dev) {
 204                         stmmac_set_mac_addr(ioaddr, ha->addr,
 205                                             GMAC_ADDR_HIGH(reg),
 206                                             GMAC_ADDR_LOW(reg));
 207                         reg++;
 208                 }
 209
 210                 while (reg <= perfect_addr_number) {
 211                         writel(0, ioaddr + GMAC_ADDR_HIGH(reg));
 212                         writel(0, ioaddr + GMAC_ADDR_LOW(reg));
 213                         reg++;
 214                 }
 215         }
 216
 217 #ifdef FRAME_FILTER_DEBUG
 218         /* Enable Receive all mode (to debug filtering_fail errors) */
 219         value |= GMAC_FRAME_FILTER_RA;
 220 #endif
 221         writel(value, ioaddr + GMAC_FRAME_FILTER);
 222 }
 223
 224
 225 static void dwmac1000_flow_ctrl(struct mac_device_info *hw, unsigned int duplex,
 226                                 unsigned int fc, unsigned int pause_time,
 227                                 u32 tx_cnt)
 228 {
 229         void __iomem *ioaddr = hw->pcsr;
 230         /* Set flow such that DZPQ in Mac Register 6 is 0,
 231          * and unicast pause detect is enabled.
 232          */
 233         unsigned int flow = GMAC_FLOW_CTRL_UP;
 234
 235         pr_debug("GMAC Flow-Control:\n");
 236         if (fc & FLOW_RX) {
 237                 pr_debug("\tReceive Flow-Control ON\n");
 238                 flow |= GMAC_FLOW_CTRL_RFE;
 239         }
 240         if (fc & FLOW_TX) {
 241                 pr_debug("\tTransmit Flow-Control ON\n");
 242                 flow |= GMAC_FLOW_CTRL_TFE;
 243         }
 244
 245         if (duplex) {
 246                 pr_debug("\tduplex mode: PAUSE %d\n", pause_time);
 247                 flow |= (pause_time << GMAC_FLOW_CTRL_PT_SHIFT);
 248         }
 249
 250         writel(flow, ioaddr + GMAC_FLOW_CTRL);
 251 }
 252
 253 static void dwmac1000_pmt(struct mac_device_info *hw, unsigned long mode)
 254 {
 255         void __iomem *ioaddr = hw->pcsr;
 256         unsigned int pmt = 0;
 257
 258         if (mode & WAKE_MAGIC) {
 259                 pr_debug("GMAC: WOL Magic frame\n");
 260                 pmt |= power_down | magic_pkt_en;
 261         }
 262         if (mode & WAKE_UCAST) {
 263                 pr_debug("GMAC: WOL on global unicast\n");
 264                 pmt |= power_down | global_unicast | wake_up_frame_en;
 265         }
 266
 267         writel(pmt, ioaddr + GMAC_PMT);
 268 }
 269
 270 /* RGMII or SMII interface */
 271 static void dwmac1000_rgsmii(void __iomem *ioaddr, struct stmmac_extra_stats *x)
 272 {
 273         u32 status;
 274
 275         status = readl(ioaddr + GMAC_RGSMIIIS);
 276         x->irq_rgmii_n++;
 277
 278         /* Check the link status */
 279         if (status & GMAC_RGSMIIIS_LNKSTS) {
 280                 int speed_value;
 281
 282                 x->pcs_link = 1;
 283
 284                 speed_value = ((status & GMAC_RGSMIIIS_SPEED) >>
 285                                GMAC_RGSMIIIS_SPEED_SHIFT);
 286                 if (speed_value == GMAC_RGSMIIIS_SPEED_125)
 287                         x->pcs_speed = SPEED_1000;
 288                 else if (speed_value == GMAC_RGSMIIIS_SPEED_25)
 289                         x->pcs_speed = SPEED_100;
 290                 else
 291                         x->pcs_speed = SPEED_10;
 292
 293                 x->pcs_duplex = (status & GMAC_RGSMIIIS_LNKMOD_MASK);
 294
 295                 pr_info("Link is Up - %d/%s\n", (int)x->pcs_speed,
 296                         x->pcs_duplex ? "Full" : "Half");
 297         } else {
 298                 x->pcs_link = 0;
 299                 pr_info("Link is Down\n");
 300         }
 301 }
 302
 303 static int dwmac1000_irq_status(struct mac_device_info *hw,
 304                                 struct stmmac_extra_stats *x)
 305 {
 306         void __iomem *ioaddr = hw->pcsr;
 307         u32 intr_status = readl(ioaddr + GMAC_INT_STATUS);
 308         u32 intr_mask = readl(ioaddr + GMAC_INT_MASK);
 309         int ret = 0;
 310
 311         /* Discard masked bits */
 312         intr_status &= ~intr_mask;
 313
 314         /* Not used events (e.g. MMC interrupts) are not handled. */
 315         if ((intr_status & GMAC_INT_STATUS_MMCTIS))
 316                 x->mmc_tx_irq_n++;
 317         if (unlikely(intr_status & GMAC_INT_STATUS_MMCRIS))
 318                 x->mmc_rx_irq_n++;
 319         if (unlikely(intr_status & GMAC_INT_STATUS_MMCCSUM))
 320                 x->mmc_rx_csum_offload_irq_n++;
 321         if (unlikely(intr_status & GMAC_INT_DISABLE_PMT)) {
 322                 /* clear the PMT bits 5 and 6 by reading the PMT status reg */
 323                 readl(ioaddr + GMAC_PMT);
 324                 x->irq_receive_pmt_irq_n++;
 325         }
 326
 327         /* MAC tx/rx EEE LPI entry/exit interrupts */
 328         if (intr_status & GMAC_INT_STATUS_LPIIS) {
 329                 /* Clean LPI interrupt by reading the Reg 12 */
 330                 ret = readl(ioaddr + LPI_CTRL_STATUS);
 331
 332                 if (ret & LPI_CTRL_STATUS_TLPIEN)
 333                         x->irq_tx_path_in_lpi_mode_n++;
 334                 if (ret & LPI_CTRL_STATUS_TLPIEX)
 335                         x->irq_tx_path_exit_lpi_mode_n++;
 336                 if (ret & LPI_CTRL_STATUS_RLPIEN)
 337                         x->irq_rx_path_in_lpi_mode_n++;
 338                 if (ret & LPI_CTRL_STATUS_RLPIEX)
 339                         x->irq_rx_path_exit_lpi_mode_n++;
 340         }
 341
 342         dwmac_pcs_isr(ioaddr, GMAC_PCS_BASE, intr_status, x);
 343
 344         if (intr_status & PCS_RGSMIIIS_IRQ)
 345                 dwmac1000_rgsmii(ioaddr, x);
 346
 347         return ret;
 348 }
 349
 350 static void dwmac1000_set_eee_mode(struct mac_device_info *hw,
 351                                    bool en_tx_lpi_clockgating)
 352 {
 353         void __iomem *ioaddr = hw->pcsr;
 354         u32 value;
 355
 356         /*TODO - en_tx_lpi_clockgating treatment */
 357
 358         /* Enable the link status receive on RGMII, SGMII ore SMII
 359          * receive path and instruct the transmit to enter in LPI
 360          * state.
 361          */
 362         value = readl(ioaddr + LPI_CTRL_STATUS);
 363         value |= LPI_CTRL_STATUS_LPIEN | LPI_CTRL_STATUS_LPITXA;
 364         writel(value, ioaddr + LPI_CTRL_STATUS);
 365 }
 366
 367 static void dwmac1000_reset_eee_mode(struct mac_device_info *hw)
 368 {
 369         void __iomem *ioaddr = hw->pcsr;
 370         u32 value;
 371
 372         value = readl(ioaddr + LPI_CTRL_STATUS);
 373         value &= ~(LPI_CTRL_STATUS_LPIEN | LPI_CTRL_STATUS_LPITXA);
 374         writel(value, ioaddr + LPI_CTRL_STATUS);
 375 }
 376
 377 static void dwmac1000_set_eee_pls(struct mac_device_info *hw, int link)
 378 {
 379         void __iomem *ioaddr = hw->pcsr;
 380         u32 value;
 381
 382         value = readl(ioaddr + LPI_CTRL_STATUS);
 383
 384         if (link)
 385                 value |= LPI_CTRL_STATUS_PLS;
 386         else
 387                 value &= ~LPI_CTRL_STATUS_PLS;
 388
 389         writel(value, ioaddr + LPI_CTRL_STATUS);
 390 }
 391
 392 static void dwmac1000_set_eee_timer(struct mac_device_info *hw, int ls, int tw)
 393 {
 394         void __iomem *ioaddr = hw->pcsr;
 395         int value = ((tw & 0xffff)) | ((ls & 0x7ff) << 16);
 396
 397         /* Program the timers in the LPI timer control register:
 398          * LS: minimum time (ms) for which the link
 399          *  status from PHY should be ok before transmitting
 400          *  the LPI pattern.
 401          * TW: minimum time (us) for which the core waits
 402          *  after it has stopped transmitting the LPI pattern.
 403          */
 404         writel(value, ioaddr + LPI_TIMER_CTRL);
 405 }
 406
 407 static void dwmac1000_ctrl_ane(void __iomem *ioaddr, bool ane, bool srgmi_ral,
 408                                bool loopback)
 409 {
 410         dwmac_ctrl_ane(ioaddr, GMAC_PCS_BASE, ane, srgmi_ral, loopback);
 411 }
 412
 413 static void dwmac1000_rane(void __iomem *ioaddr, bool restart)
 414 {
 415         dwmac_rane(ioaddr, GMAC_PCS_BASE, restart);
 416 }
 417
 418 static void dwmac1000_get_adv_lp(void __iomem *ioaddr, struct rgmii_adv *adv)
 419 {
 420         dwmac_get_adv_lp(ioaddr, GMAC_PCS_BASE, adv);
 421 }
 422
 423 static void dwmac1000_debug(void __iomem *ioaddr, struct stmmac_extra_stats *x,
 424                             u32 rx_queues, u32 tx_queues)
 425 {
 426         u32 value = readl(ioaddr + GMAC_DEBUG);
 427
 428         if (value & GMAC_DEBUG_TXSTSFSTS)
 429                 x->mtl_tx_status_fifo_full++;
 430         if (value & GMAC_DEBUG_TXFSTS)
 431                 x->mtl_tx_fifo_not_empty++;
 432         if (value & GMAC_DEBUG_TWCSTS)
 433                 x->mmtl_fifo_ctrl++;
 434         if (value & GMAC_DEBUG_TRCSTS_MASK) {
 435                 u32 trcsts = (value & GMAC_DEBUG_TRCSTS_MASK)
 436                              >> GMAC_DEBUG_TRCSTS_SHIFT;
 437                 if (trcsts == GMAC_DEBUG_TRCSTS_WRITE)
 438                         x->mtl_tx_fifo_read_ctrl_write++;
 439                 else if (trcsts == GMAC_DEBUG_TRCSTS_TXW)
 440                         x->mtl_tx_fifo_read_ctrl_wait++;
 441                 else if (trcsts == GMAC_DEBUG_TRCSTS_READ)
 442                         x->mtl_tx_fifo_read_ctrl_read++;
 443                 else
 444                         x->mtl_tx_fifo_read_ctrl_idle++;
 445         }
 446         if (value & GMAC_DEBUG_TXPAUSED)
 447                 x->mac_tx_in_pause++;
 448         if (value & GMAC_DEBUG_TFCSTS_MASK) {
 449                 u32 tfcsts = (value & GMAC_DEBUG_TFCSTS_MASK)
 450                               >> GMAC_DEBUG_TFCSTS_SHIFT;
 451
 452                 if (tfcsts == GMAC_DEBUG_TFCSTS_XFER)
 453                         x->mac_tx_frame_ctrl_xfer++;
 454                 else if (tfcsts == GMAC_DEBUG_TFCSTS_GEN_PAUSE)
 455                         x->mac_tx_frame_ctrl_pause++;
 456                 else if (tfcsts == GMAC_DEBUG_TFCSTS_WAIT)
 457                         x->mac_tx_frame_ctrl_wait++;
 458                 else
 459                         x->mac_tx_frame_ctrl_idle++;
 460         }
 461         if (value & GMAC_DEBUG_TPESTS)
 462                 x->mac_gmii_tx_proto_engine++;
 463         if (value & GMAC_DEBUG_RXFSTS_MASK) {
 464                 u32 rxfsts = (value & GMAC_DEBUG_RXFSTS_MASK)
 465                              >> GMAC_DEBUG_RRCSTS_SHIFT;
 466
 467                 if (rxfsts == GMAC_DEBUG_RXFSTS_FULL)
 468                         x->mtl_rx_fifo_fill_level_full++;
 469                 else if (rxfsts == GMAC_DEBUG_RXFSTS_AT)
 470                         x->mtl_rx_fifo_fill_above_thresh++;
 471                 else if (rxfsts == GMAC_DEBUG_RXFSTS_BT)
 472                         x->mtl_rx_fifo_fill_below_thresh++;
 473                 else
 474                         x->mtl_rx_fifo_fill_level_empty++;
 475         }
 476         if (value & GMAC_DEBUG_RRCSTS_MASK) {
 477                 u32 rrcsts = (value & GMAC_DEBUG_RRCSTS_MASK) >>
 478                              GMAC_DEBUG_RRCSTS_SHIFT;
 479
 480                 if (rrcsts == GMAC_DEBUG_RRCSTS_FLUSH)
 481                         x->mtl_rx_fifo_read_ctrl_flush++;
 482                 else if (rrcsts == GMAC_DEBUG_RRCSTS_RSTAT)
 483                         x->mtl_rx_fifo_read_ctrl_read_data++;
 484                 else if (rrcsts == GMAC_DEBUG_RRCSTS_RDATA)
 485                         x->mtl_rx_fifo_read_ctrl_status++;
 486                 else
 487                         x->mtl_rx_fifo_read_ctrl_idle++;
 488         }
 489         if (value & GMAC_DEBUG_RWCSTS)
 490                 x->mtl_rx_fifo_ctrl_active++;
 491         if (value & GMAC_DEBUG_RFCFCSTS_MASK)
 492                 x->mac_rx_frame_ctrl_fifo = (value & GMAC_DEBUG_RFCFCSTS_MASK)
 493                                             >> GMAC_DEBUG_RFCFCSTS_SHIFT;
 494         if (value & GMAC_DEBUG_RPESTS)
 495                 x->mac_gmii_rx_proto_engine++;
 496 }
 497
 498 static void dwmac1000_set_mac_loopback(void __iomem *ioaddr, bool enable)
 499 {
 500         u32 value = readl(ioaddr + GMAC_CONTROL);
 501
 502         if (enable)
 503                 value |= GMAC_CONTROL_LM;
 504         else
 505                 value &= ~GMAC_CONTROL_LM;
 506
 507         writel(value, ioaddr + GMAC_CONTROL);
 508 }
 509
 510 const struct stmmac_ops dwmac1000_ops = {
 511         .core_init = dwmac1000_core_init,
 512         .set_mac = stmmac_set_mac,
 513         .rx_ipc = dwmac1000_rx_ipc_enable,
 514         .dump_regs = dwmac1000_dump_regs,
 515         .host_irq_status = dwmac1000_irq_status,
 516         .set_filter = dwmac1000_set_filter,
 517         .flow_ctrl = dwmac1000_flow_ctrl,
 518         .pmt = dwmac1000_pmt,
 519         .set_umac_addr = dwmac1000_set_umac_addr,
 520         .get_umac_addr = dwmac1000_get_umac_addr,
 521         .set_eee_mode = dwmac1000_set_eee_mode,
 522         .reset_eee_mode = dwmac1000_reset_eee_mode,
 523         .set_eee_timer = dwmac1000_set_eee_timer,
 524         .set_eee_pls = dwmac1000_set_eee_pls,
 525         .debug = dwmac1000_debug,
 526         .pcs_ctrl_ane = dwmac1000_ctrl_ane,
 527         .pcs_rane = dwmac1000_rane,
 528         .pcs_get_adv_lp = dwmac1000_get_adv_lp,
 529         .set_mac_loopback = dwmac1000_set_mac_loopback,
 530 };
 531
 532 int dwmac1000_setup(struct stmmac_priv *priv)
 533 {
 534         struct mac_device_info *mac = priv->hw;
 535
 536         dev_info(priv->device, "\tDWMAC1000\n");
 537
 538         priv->dev->priv_flags |= IFF_UNICAST_FLT;
 539         mac->pcsr = priv->ioaddr;
 540         mac->multicast_filter_bins = priv->plat->multicast_filter_bins;
 541         mac->unicast_filter_entries = priv->plat->unicast_filter_entries;
 542         mac->mcast_bits_log2 = 0;
 543
 544         if (mac->multicast_filter_bins)
 545                 mac->mcast_bits_log2 = ilog2(mac->multicast_filter_bins);
 546
 547         mac->link.duplex = GMAC_CONTROL_DM;
 548         mac->link.speed10 = GMAC_CONTROL_PS;
 549         mac->link.speed100 = GMAC_CONTROL_PS | GMAC_CONTROL_FES;
 550         mac->link.speed1000 = 0;
 551         mac->link.speed_mask = GMAC_CONTROL_PS | GMAC_CONTROL_FES;
 552         mac->mii.addr = GMAC_MII_ADDR;
 553         mac->mii.data = GMAC_MII_DATA;
 554         mac->mii.addr_shift = 11;
 555         mac->mii.addr_mask = 0x0000F800;
 556         mac->mii.reg_shift = 6;
 557         mac->mii.reg_mask = 0x000007C0;
 558         mac->mii.clk_csr_shift = 2;
 559         mac->mii.clk_csr_mask = GENMASK(5, 2);
 560
 561         return 0;
 562 }