drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * This contains the functions to handle the descriptors for DesignWare databook
   4  * 4.xx.
   5  *
   6  * Copyright (C) 2015  STMicroelectronics Ltd
   7  *
   8  * Author: Alexandre Torgue <alexandre.torgue@st.com>
   9  */
  10
  11 #include <linux/stmmac.h>
  12 #include "common.h"
  13 #include "dwmac4_descs.h"
  14
  15 static int dwmac4_wrback_get_tx_status(void *data, struct stmmac_extra_stats *x,
  16                                        struct dma_desc *p,
  17                                        void __iomem *ioaddr)
  18 {
  19         struct net_device_stats *stats = (struct net_device_stats *)data;
  20         unsigned int tdes3;
  21         int ret = tx_done;
  22
  23         tdes3 = le32_to_cpu(p->des3);
  24
  25         /* Get tx owner first */
  26         if (unlikely(tdes3 & TDES3_OWN))
  27                 return tx_dma_own;
  28
  29         /* Verify tx error by looking at the last segment. */
  30         if (likely(!(tdes3 & TDES3_LAST_DESCRIPTOR)))
  31                 return tx_not_ls;
  32
  33         if (unlikely(tdes3 & TDES3_ERROR_SUMMARY)) {
  34                 if (unlikely(tdes3 & TDES3_JABBER_TIMEOUT))
  35                         x->tx_jabber++;
  36                 if (unlikely(tdes3 & TDES3_PACKET_FLUSHED))
  37                         x->tx_frame_flushed++;
  38                 if (unlikely(tdes3 & TDES3_LOSS_CARRIER)) {
  39                         x->tx_losscarrier++;
  40                         stats->tx_carrier_errors++;
  41                 }
  42                 if (unlikely(tdes3 & TDES3_NO_CARRIER)) {
  43                         x->tx_carrier++;
  44                         stats->tx_carrier_errors++;
  45                 }
  46                 if (unlikely((tdes3 & TDES3_LATE_COLLISION) ||
  47                              (tdes3 & TDES3_EXCESSIVE_COLLISION)))
  48                         stats->collisions +=
  49                             (tdes3 & TDES3_COLLISION_COUNT_MASK)
  50                             >> TDES3_COLLISION_COUNT_SHIFT;
  51
  52                 if (unlikely(tdes3 & TDES3_EXCESSIVE_DEFERRAL))
  53                         x->tx_deferred++;
  54
  55                 if (unlikely(tdes3 & TDES3_UNDERFLOW_ERROR))
  56                         x->tx_underflow++;
  57
  58                 if (unlikely(tdes3 & TDES3_IP_HDR_ERROR))
  59                         x->tx_ip_header_error++;
  60
  61                 if (unlikely(tdes3 & TDES3_PAYLOAD_ERROR))
  62                         x->tx_payload_error++;
  63
  64                 ret = tx_err;
  65         }
  66
  67         if (unlikely(tdes3 & TDES3_DEFERRED))
  68                 x->tx_deferred++;
  69
  70         return ret;
  71 }
  72
  73 static int dwmac4_wrback_get_rx_status(void *data, struct stmmac_extra_stats *x,
  74                                        struct dma_desc *p)
  75 {
  76         struct net_device_stats *stats = (struct net_device_stats *)data;
  77         unsigned int rdes1 = le32_to_cpu(p->des1);
  78         unsigned int rdes2 = le32_to_cpu(p->des2);
  79         unsigned int rdes3 = le32_to_cpu(p->des3);
  80         int message_type;
  81         int ret = good_frame;
  82
  83         if (unlikely(rdes3 & RDES3_OWN))
  84                 return dma_own;
  85
  86         if (unlikely(rdes3 & RDES3_CONTEXT_DESCRIPTOR))
  87                 return discard_frame;
  88         if (likely(!(rdes3 & RDES3_LAST_DESCRIPTOR)))
  89                 return rx_not_ls;
  90
  91         if (unlikely(rdes3 & RDES3_ERROR_SUMMARY)) {
  92                 if (unlikely(rdes3 & RDES3_GIANT_PACKET))
  93                         stats->rx_length_errors++;
  94                 if (unlikely(rdes3 & RDES3_OVERFLOW_ERROR))
  95                         x->rx_gmac_overflow++;
  96
  97                 if (unlikely(rdes3 & RDES3_RECEIVE_WATCHDOG))
  98                         x->rx_watchdog++;
  99
 100                 if (unlikely(rdes3 & RDES3_RECEIVE_ERROR))
 101                         x->rx_mii++;
 102
 103                 if (unlikely(rdes3 & RDES3_CRC_ERROR)) {
 104                         x->rx_crc_errors++;
 105                         stats->rx_crc_errors++;
 106                 }
 107
 108                 if (unlikely(rdes3 & RDES3_DRIBBLE_ERROR))
 109                         x->dribbling_bit++;
 110
 111                 ret = discard_frame;
 112         }
 113
 114         message_type = (rdes1 & ERDES4_MSG_TYPE_MASK) >> 8;
 115
 116         if (rdes1 & RDES1_IP_HDR_ERROR)
 117                 x->ip_hdr_err++;
 118         if (rdes1 & RDES1_IP_CSUM_BYPASSED)
 119                 x->ip_csum_bypassed++;
 120         if (rdes1 & RDES1_IPV4_HEADER)
 121                 x->ipv4_pkt_rcvd++;
 122         if (rdes1 & RDES1_IPV6_HEADER)
 123                 x->ipv6_pkt_rcvd++;
 124
 125         if (message_type == RDES_EXT_NO_PTP)
 126                 x->no_ptp_rx_msg_type_ext++;
 127         else if (message_type == RDES_EXT_SYNC)
 128                 x->ptp_rx_msg_type_sync++;
 129         else if (message_type == RDES_EXT_FOLLOW_UP)
 130                 x->ptp_rx_msg_type_follow_up++;
 131         else if (message_type == RDES_EXT_DELAY_REQ)
 132                 x->ptp_rx_msg_type_delay_req++;
 133         else if (message_type == RDES_EXT_DELAY_RESP)
 134                 x->ptp_rx_msg_type_delay_resp++;
 135         else if (message_type == RDES_EXT_PDELAY_REQ)
 136                 x->ptp_rx_msg_type_pdelay_req++;
 137         else if (message_type == RDES_EXT_PDELAY_RESP)
 138                 x->ptp_rx_msg_type_pdelay_resp++;
 139         else if (message_type == RDES_EXT_PDELAY_FOLLOW_UP)
 140                 x->ptp_rx_msg_type_pdelay_follow_up++;
 141         else if (message_type == RDES_PTP_ANNOUNCE)
 142                 x->ptp_rx_msg_type_announce++;
 143         else if (message_type == RDES_PTP_MANAGEMENT)
 144                 x->ptp_rx_msg_type_management++;
 145         else if (message_type == RDES_PTP_PKT_RESERVED_TYPE)
 146                 x->ptp_rx_msg_pkt_reserved_type++;
 147
 148         if (rdes1 & RDES1_PTP_PACKET_TYPE)
 149                 x->ptp_frame_type++;
 150         if (rdes1 & RDES1_PTP_VER)
 151                 x->ptp_ver++;
 152         if (rdes1 & RDES1_TIMESTAMP_DROPPED)
 153                 x->timestamp_dropped++;
 154
 155         if (unlikely(rdes2 & RDES2_SA_FILTER_FAIL)) {
 156                 x->sa_rx_filter_fail++;
 157                 ret = discard_frame;
 158         }
 159         if (unlikely(rdes2 & RDES2_DA_FILTER_FAIL)) {
 160                 x->da_rx_filter_fail++;
 161                 ret = discard_frame;
 162         }
 163
 164         if (rdes2 & RDES2_L3_FILTER_MATCH)
 165                 x->l3_filter_match++;
 166         if (rdes2 & RDES2_L4_FILTER_MATCH)
 167                 x->l4_filter_match++;
 168         if ((rdes2 & RDES2_L3_L4_FILT_NB_MATCH_MASK)
 169             >> RDES2_L3_L4_FILT_NB_MATCH_SHIFT)
 170                 x->l3_l4_filter_no_match++;
 171
 172         return ret;
 173 }
 174
 175 static int dwmac4_rd_get_tx_len(struct dma_desc *p)
 176 {
 177         return (le32_to_cpu(p->des2) & TDES2_BUFFER1_SIZE_MASK);
 178 }
 179
 180 static int dwmac4_get_tx_owner(struct dma_desc *p)
 181 {
 182         return (le32_to_cpu(p->des3) & TDES3_OWN) >> TDES3_OWN_SHIFT;
 183 }
 184
 185 static void dwmac4_set_tx_owner(struct dma_desc *p)
 186 {
 187         p->des3 |= cpu_to_le32(TDES3_OWN);
 188 }
 189
 190 static void dwmac4_set_rx_owner(struct dma_desc *p, int disable_rx_ic)
 191 {
 192         p->des3 |= cpu_to_le32(RDES3_OWN | RDES3_BUFFER1_VALID_ADDR);
 193
 194         if (!disable_rx_ic)
 195                 p->des3 |= cpu_to_le32(RDES3_INT_ON_COMPLETION_EN);
 196 }
 197
 198 static int dwmac4_get_tx_ls(struct dma_desc *p)
 199 {
 200         return (le32_to_cpu(p->des3) & TDES3_LAST_DESCRIPTOR)
 201                 >> TDES3_LAST_DESCRIPTOR_SHIFT;
 202 }
 203
 204 static int dwmac4_wrback_get_rx_frame_len(struct dma_desc *p, int rx_coe)
 205 {
 206         return (le32_to_cpu(p->des3) & RDES3_PACKET_SIZE_MASK);
 207 }
 208
 209 static void dwmac4_rd_enable_tx_timestamp(struct dma_desc *p)
 210 {
 211         p->des2 |= cpu_to_le32(TDES2_TIMESTAMP_ENABLE);
 212 }
 213
 214 static int dwmac4_wrback_get_tx_timestamp_status(struct dma_desc *p)
 215 {
 216         /* Context type from W/B descriptor must be zero */
 217         if (le32_to_cpu(p->des3) & TDES3_CONTEXT_TYPE)
 218                 return 0;
 219
 220         /* Tx Timestamp Status is 1 so des0 and des1'll have valid values */
 221         if (le32_to_cpu(p->des3) & TDES3_TIMESTAMP_STATUS)
 222                 return 1;
 223
 224         return 0;
 225 }
 226
 227 static inline void dwmac4_get_timestamp(void *desc, u32 ats, u64 *ts)
 228 {
 229         struct dma_desc *p = (struct dma_desc *)desc;
 230         u64 ns;
 231
 232         ns = le32_to_cpu(p->des0);
 233         /* convert high/sec time stamp value to nanosecond */
 234         ns += le32_to_cpu(p->des1) * 1000000000ULL;
 235
 236         *ts = ns;
 237 }
 238
 239 static int dwmac4_rx_check_timestamp(void *desc)
 240 {
 241         struct dma_desc *p = (struct dma_desc *)desc;
 242         unsigned int rdes0 = le32_to_cpu(p->des0);
 243         unsigned int rdes1 = le32_to_cpu(p->des1);
 244         unsigned int rdes3 = le32_to_cpu(p->des3);
 245         u32 own, ctxt;
 246         int ret = 1;
 247
 248         own = rdes3 & RDES3_OWN;
 249         ctxt = ((rdes3 & RDES3_CONTEXT_DESCRIPTOR)
 250                 >> RDES3_CONTEXT_DESCRIPTOR_SHIFT);
 251
 252         if (likely(!own && ctxt)) {
 253                 if ((rdes0 == 0xffffffff) && (rdes1 == 0xffffffff))
 254                         /* Corrupted value */
 255                         ret = -EINVAL;
 256                 else
 257                         /* A valid Timestamp is ready to be read */
 258                         ret = 0;
 259         }
 260
 261         /* Timestamp not ready */
 262         return ret;
 263 }
 264
 265 static int dwmac4_wrback_get_rx_timestamp_status(void *desc, void *next_desc,
 266                                                  u32 ats)
 267 {
 268         struct dma_desc *p = (struct dma_desc *)desc;
 269         int ret = -EINVAL;
 270
 271         /* Get the status from normal w/b descriptor */
 272         if (likely(le32_to_cpu(p->des3) & RDES3_RDES1_VALID)) {
 273                 if (likely(le32_to_cpu(p->des1) & RDES1_TIMESTAMP_AVAILABLE)) {
 274                         int i = 0;
 275
 276                         /* Check if timestamp is OK from context descriptor */
 277                         do {
 278                                 ret = dwmac4_rx_check_timestamp(next_desc);
 279                                 if (ret < 0)
 280                                         goto exit;
 281                                 i++;
 282
 283                         } while ((ret == 1) && (i < 10));
 284
 285                         if (i == 10)
 286                                 ret = -EBUSY;
 287                 }
 288         }
 289 exit:
 290         if (likely(ret == 0))
 291                 return 1;
 292
 293         return 0;
 294 }
 295
 296 static void dwmac4_rd_init_rx_desc(struct dma_desc *p, int disable_rx_ic,
 297                                    int mode, int end, int bfsize)
 298 {
 299         dwmac4_set_rx_owner(p, disable_rx_ic);
 300 }
 301
 302 static void dwmac4_rd_init_tx_desc(struct dma_desc *p, int mode, int end)
 303 {
 304         p->des0 = 0;
 305         p->des1 = 0;
 306         p->des2 = 0;
 307         p->des3 = 0;
 308 }
 309
 310 static void dwmac4_rd_prepare_tx_desc(struct dma_desc *p, int is_fs, int len,
 311                                       bool csum_flag, int mode, bool tx_own,
 312                                       bool ls, unsigned int tot_pkt_len)
 313 {
 314         unsigned int tdes3 = le32_to_cpu(p->des3);
 315
 316         p->des2 |= cpu_to_le32(len & TDES2_BUFFER1_SIZE_MASK);
 317
 318         tdes3 |= tot_pkt_len & TDES3_PACKET_SIZE_MASK;
 319         if (is_fs)
 320                 tdes3 |= TDES3_FIRST_DESCRIPTOR;
 321         else
 322                 tdes3 &= ~TDES3_FIRST_DESCRIPTOR;
 323
 324         if (likely(csum_flag))
 325                 tdes3 |= (TX_CIC_FULL << TDES3_CHECKSUM_INSERTION_SHIFT);
 326         else
 327                 tdes3 &= ~(TX_CIC_FULL << TDES3_CHECKSUM_INSERTION_SHIFT);
 328
 329         if (ls)
 330                 tdes3 |= TDES3_LAST_DESCRIPTOR;
 331         else
 332                 tdes3 &= ~TDES3_LAST_DESCRIPTOR;
 333
 334         /* Finally set the OWN bit. Later the DMA will start! */
 335         if (tx_own)
 336                 tdes3 |= TDES3_OWN;
 337
 338         if (is_fs && tx_own)
 339                 /* When the own bit, for the first frame, has to be set, all
 340                  * descriptors for the same frame has to be set before, to
 341                  * avoid race condition.
 342                  */
 343                 dma_wmb();
 344
 345         p->des3 = cpu_to_le32(tdes3);
 346 }
 347
 348 static void dwmac4_rd_prepare_tso_tx_desc(struct dma_desc *p, int is_fs,
 349                                           int len1, int len2, bool tx_own,
 350                                           bool ls, unsigned int tcphdrlen,
 351                                           unsigned int tcppayloadlen)
 352 {
 353         unsigned int tdes3 = le32_to_cpu(p->des3);
 354
 355         if (len1)
 356                 p->des2 |= cpu_to_le32((len1 & TDES2_BUFFER1_SIZE_MASK));
 357
 358         if (len2)
 359                 p->des2 |= cpu_to_le32((len2 << TDES2_BUFFER2_SIZE_MASK_SHIFT)
 360                             & TDES2_BUFFER2_SIZE_MASK);
 361
 362         if (is_fs) {
 363                 tdes3 |= TDES3_FIRST_DESCRIPTOR |
 364                          TDES3_TCP_SEGMENTATION_ENABLE |
 365                          ((tcphdrlen << TDES3_HDR_LEN_SHIFT) &
 366                           TDES3_SLOT_NUMBER_MASK) |
 367                          ((tcppayloadlen & TDES3_TCP_PKT_PAYLOAD_MASK));
 368         } else {
 369                 tdes3 &= ~TDES3_FIRST_DESCRIPTOR;
 370         }
 371
 372         if (ls)
 373                 tdes3 |= TDES3_LAST_DESCRIPTOR;
 374         else
 375                 tdes3 &= ~TDES3_LAST_DESCRIPTOR;
 376
 377         /* Finally set the OWN bit. Later the DMA will start! */
 378         if (tx_own)
 379                 tdes3 |= TDES3_OWN;
 380
 381         if (is_fs && tx_own)
 382                 /* When the own bit, for the first frame, has to be set, all
 383                  * descriptors for the same frame has to be set before, to
 384                  * avoid race condition.
 385                  */
 386                 dma_wmb();
 387
 388         p->des3 = cpu_to_le32(tdes3);
 389 }
 390
 391 static void dwmac4_release_tx_desc(struct dma_desc *p, int mode)
 392 {
 393         p->des0 = 0;
 394         p->des1 = 0;
 395         p->des2 = 0;
 396         p->des3 = 0;
 397 }
 398
 399 static void dwmac4_rd_set_tx_ic(struct dma_desc *p)
 400 {
 401         p->des2 |= cpu_to_le32(TDES2_INTERRUPT_ON_COMPLETION);
 402 }
 403
 404 static void dwmac4_display_ring(void *head, unsigned int size, bool rx)
 405 {
 406         struct dma_desc *p = (struct dma_desc *)head;
 407         int i;
 408
 409         pr_info("%s descriptor ring:\n", rx ? "RX" : "TX");
 410
 411         for (i = 0; i < size; i++) {
 412                 pr_info("%03d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
 413                         i, (unsigned int)virt_to_phys(p),
 414                         le32_to_cpu(p->des0), le32_to_cpu(p->des1),
 415                         le32_to_cpu(p->des2), le32_to_cpu(p->des3));
 416                 p++;
 417         }
 418 }
 419
 420 static void dwmac4_set_mss_ctxt(struct dma_desc *p, unsigned int mss)
 421 {
 422         p->des0 = 0;
 423         p->des1 = 0;
 424         p->des2 = cpu_to_le32(mss);
 425         p->des3 = cpu_to_le32(TDES3_CONTEXT_TYPE | TDES3_CTXT_TCMSSV);
 426 }
 427
 428 static void dwmac4_get_addr(struct dma_desc *p, unsigned int *addr)
 429 {
 430         *addr = le32_to_cpu(p->des0);
 431 }
 432
 433 static void dwmac4_set_addr(struct dma_desc *p, dma_addr_t addr)
 434 {
 435         p->des0 = cpu_to_le32(lower_32_bits(addr));
 436         p->des1 = cpu_to_le32(upper_32_bits(addr));
 437 }
 438
 439 static void dwmac4_clear(struct dma_desc *p)
 440 {
 441         p->des0 = 0;
 442         p->des1 = 0;
 443         p->des2 = 0;
 444         p->des3 = 0;
 445 }
 446
 447 static void dwmac4_set_sarc(struct dma_desc *p, u32 sarc_type)
 448 {
 449         sarc_type <<= TDES3_SA_INSERT_CTRL_SHIFT;
 450
 451         p->des3 |= cpu_to_le32(sarc_type & TDES3_SA_INSERT_CTRL_MASK);
 452 }
 453
 454 static int set_16kib_bfsize(int mtu)
 455 {
 456         int ret = 0;
 457
 458         if (unlikely(mtu >= BUF_SIZE_8KiB))
 459                 ret = BUF_SIZE_16KiB;
 460         return ret;
 461 }
 462
 463 static void dwmac4_set_vlan_tag(struct dma_desc *p, u16 tag, u16 inner_tag,
 464                                 u32 inner_type)
 465 {
 466         p->des0 = 0;
 467         p->des1 = 0;
 468         p->des2 = 0;
 469         p->des3 = 0;
 470
 471         /* Inner VLAN */
 472         if (inner_type) {
 473                 u32 des = inner_tag << TDES2_IVT_SHIFT;
 474
 475                 des &= TDES2_IVT_MASK;
 476                 p->des2 = cpu_to_le32(des);
 477
 478                 des = inner_type << TDES3_IVTIR_SHIFT;
 479                 des &= TDES3_IVTIR_MASK;
 480                 p->des3 = cpu_to_le32(des | TDES3_IVLTV);
 481         }
 482
 483         /* Outer VLAN */
 484         p->des3 |= cpu_to_le32(tag & TDES3_VLAN_TAG);
 485         p->des3 |= cpu_to_le32(TDES3_VLTV);
 486
 487         p->des3 |= cpu_to_le32(TDES3_CONTEXT_TYPE);
 488 }
 489
 490 static void dwmac4_set_vlan(struct dma_desc *p, u32 type)
 491 {
 492         type <<= TDES2_VLAN_TAG_SHIFT;
 493         p->des2 |= cpu_to_le32(type & TDES2_VLAN_TAG_MASK);
 494 }
 495
 496 static int dwmac4_get_rx_header_len(struct dma_desc *p, unsigned int *len)
 497 {
 498         *len = le32_to_cpu(p->des2) & RDES2_HL;
 499         return 0;
 500 }
 501
 502 static void dwmac4_set_sec_addr(struct dma_desc *p, dma_addr_t addr)
 503 {
 504         p->des2 = cpu_to_le32(lower_32_bits(addr));
 505         p->des3 = cpu_to_le32(upper_32_bits(addr) | RDES3_BUFFER2_VALID_ADDR);
 506 }
 507
 508 const struct stmmac_desc_ops dwmac4_desc_ops = {
 509         .tx_status = dwmac4_wrback_get_tx_status,
 510         .rx_status = dwmac4_wrback_get_rx_status,
 511         .get_tx_len = dwmac4_rd_get_tx_len,
 512         .get_tx_owner = dwmac4_get_tx_owner,
 513         .set_tx_owner = dwmac4_set_tx_owner,
 514         .set_rx_owner = dwmac4_set_rx_owner,
 515         .get_tx_ls = dwmac4_get_tx_ls,
 516         .get_rx_frame_len = dwmac4_wrback_get_rx_frame_len,
 517         .enable_tx_timestamp = dwmac4_rd_enable_tx_timestamp,
 518         .get_tx_timestamp_status = dwmac4_wrback_get_tx_timestamp_status,
 519         .get_rx_timestamp_status = dwmac4_wrback_get_rx_timestamp_status,
 520         .get_timestamp = dwmac4_get_timestamp,
 521         .set_tx_ic = dwmac4_rd_set_tx_ic,
 522         .prepare_tx_desc = dwmac4_rd_prepare_tx_desc,
 523         .prepare_tso_tx_desc = dwmac4_rd_prepare_tso_tx_desc,
 524         .release_tx_desc = dwmac4_release_tx_desc,
 525         .init_rx_desc = dwmac4_rd_init_rx_desc,
 526         .init_tx_desc = dwmac4_rd_init_tx_desc,
 527         .display_ring = dwmac4_display_ring,
 528         .set_mss = dwmac4_set_mss_ctxt,
 529         .get_addr = dwmac4_get_addr,
 530         .set_addr = dwmac4_set_addr,
 531         .clear = dwmac4_clear,
 532         .set_sarc = dwmac4_set_sarc,
 533         .set_vlan_tag = dwmac4_set_vlan_tag,
 534         .set_vlan = dwmac4_set_vlan,
 535         .get_rx_header_len = dwmac4_get_rx_header_len,
 536         .set_sec_addr = dwmac4_set_sec_addr,
 537 };
 538
 539 const struct stmmac_mode_ops dwmac4_ring_mode_ops = {
 540         .set_16kib_bfsize = set_16kib_bfsize,
 541 };