1 // SPDX-License-Identifier: GPL-2.0-only
3 * This contains the functions to handle the descriptors for DesignWare databook
6 * Copyright (C) 2015 STMicroelectronics Ltd
8 * Author: Alexandre Torgue <alexandre.torgue@st.com>
11 #include <linux/stmmac.h>
13 #include "dwmac4_descs.h"
15 static int dwmac4_wrback_get_tx_status(void *data, struct stmmac_extra_stats *x,
19 struct net_device_stats *stats = (struct net_device_stats *)data;
23 tdes3 = le32_to_cpu(p->des3);
25 /* Get tx owner first */
26 if (unlikely(tdes3 & TDES3_OWN))
29 /* Verify tx error by looking at the last segment. */
30 if (likely(!(tdes3 & TDES3_LAST_DESCRIPTOR)))
33 if (unlikely(tdes3 & TDES3_ERROR_SUMMARY)) {
34 if (unlikely(tdes3 & TDES3_JABBER_TIMEOUT))
36 if (unlikely(tdes3 & TDES3_PACKET_FLUSHED))
37 x->tx_frame_flushed++;
38 if (unlikely(tdes3 & TDES3_LOSS_CARRIER)) {
40 stats->tx_carrier_errors++;
42 if (unlikely(tdes3 & TDES3_NO_CARRIER)) {
44 stats->tx_carrier_errors++;
46 if (unlikely((tdes3 & TDES3_LATE_COLLISION) ||
47 (tdes3 & TDES3_EXCESSIVE_COLLISION)))
49 (tdes3 & TDES3_COLLISION_COUNT_MASK)
50 >> TDES3_COLLISION_COUNT_SHIFT;
52 if (unlikely(tdes3 & TDES3_EXCESSIVE_DEFERRAL))
55 if (unlikely(tdes3 & TDES3_UNDERFLOW_ERROR))
58 if (unlikely(tdes3 & TDES3_IP_HDR_ERROR))
59 x->tx_ip_header_error++;
61 if (unlikely(tdes3 & TDES3_PAYLOAD_ERROR))
62 x->tx_payload_error++;
67 if (unlikely(tdes3 & TDES3_DEFERRED))
73 static int dwmac4_wrback_get_rx_status(void *data, struct stmmac_extra_stats *x,
76 struct net_device_stats *stats = (struct net_device_stats *)data;
77 unsigned int rdes1 = le32_to_cpu(p->des1);
78 unsigned int rdes2 = le32_to_cpu(p->des2);
79 unsigned int rdes3 = le32_to_cpu(p->des3);
83 if (unlikely(rdes3 & RDES3_OWN))
86 /* Verify rx error by looking at the last segment. */
87 if (likely(!(rdes3 & RDES3_LAST_DESCRIPTOR)))
90 if (unlikely(rdes3 & RDES3_ERROR_SUMMARY)) {
91 if (unlikely(rdes3 & RDES3_GIANT_PACKET))
92 stats->rx_length_errors++;
93 if (unlikely(rdes3 & RDES3_OVERFLOW_ERROR))
94 x->rx_gmac_overflow++;
96 if (unlikely(rdes3 & RDES3_RECEIVE_WATCHDOG))
99 if (unlikely(rdes3 & RDES3_RECEIVE_ERROR))
102 if (unlikely(rdes3 & RDES3_CRC_ERROR)) {
104 stats->rx_crc_errors++;
107 if (unlikely(rdes3 & RDES3_DRIBBLE_ERROR))
113 message_type = (rdes1 & ERDES4_MSG_TYPE_MASK) >> 8;
115 if (rdes1 & RDES1_IP_HDR_ERROR)
117 if (rdes1 & RDES1_IP_CSUM_BYPASSED)
118 x->ip_csum_bypassed++;
119 if (rdes1 & RDES1_IPV4_HEADER)
121 if (rdes1 & RDES1_IPV6_HEADER)
124 if (message_type == RDES_EXT_NO_PTP)
125 x->no_ptp_rx_msg_type_ext++;
126 else if (message_type == RDES_EXT_SYNC)
127 x->ptp_rx_msg_type_sync++;
128 else if (message_type == RDES_EXT_FOLLOW_UP)
129 x->ptp_rx_msg_type_follow_up++;
130 else if (message_type == RDES_EXT_DELAY_REQ)
131 x->ptp_rx_msg_type_delay_req++;
132 else if (message_type == RDES_EXT_DELAY_RESP)
133 x->ptp_rx_msg_type_delay_resp++;
134 else if (message_type == RDES_EXT_PDELAY_REQ)
135 x->ptp_rx_msg_type_pdelay_req++;
136 else if (message_type == RDES_EXT_PDELAY_RESP)
137 x->ptp_rx_msg_type_pdelay_resp++;
138 else if (message_type == RDES_EXT_PDELAY_FOLLOW_UP)
139 x->ptp_rx_msg_type_pdelay_follow_up++;
140 else if (message_type == RDES_PTP_ANNOUNCE)
141 x->ptp_rx_msg_type_announce++;
142 else if (message_type == RDES_PTP_MANAGEMENT)
143 x->ptp_rx_msg_type_management++;
144 else if (message_type == RDES_PTP_PKT_RESERVED_TYPE)
145 x->ptp_rx_msg_pkt_reserved_type++;
147 if (rdes1 & RDES1_PTP_PACKET_TYPE)
149 if (rdes1 & RDES1_PTP_VER)
151 if (rdes1 & RDES1_TIMESTAMP_DROPPED)
152 x->timestamp_dropped++;
154 if (unlikely(rdes2 & RDES2_SA_FILTER_FAIL)) {
155 x->sa_rx_filter_fail++;
158 if (unlikely(rdes2 & RDES2_DA_FILTER_FAIL)) {
159 x->da_rx_filter_fail++;
163 if (rdes2 & RDES2_L3_FILTER_MATCH)
164 x->l3_filter_match++;
165 if (rdes2 & RDES2_L4_FILTER_MATCH)
166 x->l4_filter_match++;
167 if ((rdes2 & RDES2_L3_L4_FILT_NB_MATCH_MASK)
168 >> RDES2_L3_L4_FILT_NB_MATCH_SHIFT)
169 x->l3_l4_filter_no_match++;
174 static int dwmac4_rd_get_tx_len(struct dma_desc *p)
176 return (le32_to_cpu(p->des2) & TDES2_BUFFER1_SIZE_MASK);
179 static int dwmac4_get_tx_owner(struct dma_desc *p)
181 return (le32_to_cpu(p->des3) & TDES3_OWN) >> TDES3_OWN_SHIFT;
184 static void dwmac4_set_tx_owner(struct dma_desc *p)
186 p->des3 |= cpu_to_le32(TDES3_OWN);
189 static void dwmac4_set_rx_owner(struct dma_desc *p, int disable_rx_ic)
191 p->des3 = cpu_to_le32(RDES3_OWN | RDES3_BUFFER1_VALID_ADDR);
194 p->des3 |= cpu_to_le32(RDES3_INT_ON_COMPLETION_EN);
197 static int dwmac4_get_tx_ls(struct dma_desc *p)
199 return (le32_to_cpu(p->des3) & TDES3_LAST_DESCRIPTOR)
200 >> TDES3_LAST_DESCRIPTOR_SHIFT;
203 static int dwmac4_wrback_get_rx_frame_len(struct dma_desc *p, int rx_coe)
205 return (le32_to_cpu(p->des3) & RDES3_PACKET_SIZE_MASK);
208 static void dwmac4_rd_enable_tx_timestamp(struct dma_desc *p)
210 p->des2 |= cpu_to_le32(TDES2_TIMESTAMP_ENABLE);
213 static int dwmac4_wrback_get_tx_timestamp_status(struct dma_desc *p)
215 /* Context type from W/B descriptor must be zero */
216 if (le32_to_cpu(p->des3) & TDES3_CONTEXT_TYPE)
219 /* Tx Timestamp Status is 1 so des0 and des1'll have valid values */
220 if (le32_to_cpu(p->des3) & TDES3_TIMESTAMP_STATUS)
226 static inline void dwmac4_get_timestamp(void *desc, u32 ats, u64 *ts)
228 struct dma_desc *p = (struct dma_desc *)desc;
231 ns = le32_to_cpu(p->des0);
232 /* convert high/sec time stamp value to nanosecond */
233 ns += le32_to_cpu(p->des1) * 1000000000ULL;
238 static int dwmac4_rx_check_timestamp(void *desc)
240 struct dma_desc *p = (struct dma_desc *)desc;
241 unsigned int rdes0 = le32_to_cpu(p->des0);
242 unsigned int rdes1 = le32_to_cpu(p->des1);
243 unsigned int rdes3 = le32_to_cpu(p->des3);
247 own = rdes3 & RDES3_OWN;
248 ctxt = ((rdes3 & RDES3_CONTEXT_DESCRIPTOR)
249 >> RDES3_CONTEXT_DESCRIPTOR_SHIFT);
251 if (likely(!own && ctxt)) {
252 if ((rdes0 == 0xffffffff) && (rdes1 == 0xffffffff))
253 /* Corrupted value */
256 /* A valid Timestamp is ready to be read */
260 /* Timestamp not ready */
264 static int dwmac4_wrback_get_rx_timestamp_status(void *desc, void *next_desc,
267 struct dma_desc *p = (struct dma_desc *)desc;
270 /* Get the status from normal w/b descriptor */
271 if (likely(le32_to_cpu(p->des3) & RDES3_RDES1_VALID)) {
272 if (likely(le32_to_cpu(p->des1) & RDES1_TIMESTAMP_AVAILABLE)) {
275 /* Check if timestamp is OK from context descriptor */
277 ret = dwmac4_rx_check_timestamp(next_desc);
282 } while ((ret == 1) && (i < 10));
289 if (likely(ret == 0))
295 static void dwmac4_rd_init_rx_desc(struct dma_desc *p, int disable_rx_ic,
296 int mode, int end, int bfsize)
298 dwmac4_set_rx_owner(p, disable_rx_ic);
301 static void dwmac4_rd_init_tx_desc(struct dma_desc *p, int mode, int end)
309 static void dwmac4_rd_prepare_tx_desc(struct dma_desc *p, int is_fs, int len,
310 bool csum_flag, int mode, bool tx_own,
311 bool ls, unsigned int tot_pkt_len)
313 unsigned int tdes3 = le32_to_cpu(p->des3);
315 p->des2 |= cpu_to_le32(len & TDES2_BUFFER1_SIZE_MASK);
317 tdes3 |= tot_pkt_len & TDES3_PACKET_SIZE_MASK;
319 tdes3 |= TDES3_FIRST_DESCRIPTOR;
321 tdes3 &= ~TDES3_FIRST_DESCRIPTOR;
323 if (likely(csum_flag))
324 tdes3 |= (TX_CIC_FULL << TDES3_CHECKSUM_INSERTION_SHIFT);
326 tdes3 &= ~(TX_CIC_FULL << TDES3_CHECKSUM_INSERTION_SHIFT);
329 tdes3 |= TDES3_LAST_DESCRIPTOR;
331 tdes3 &= ~TDES3_LAST_DESCRIPTOR;
333 /* Finally set the OWN bit. Later the DMA will start! */
338 /* When the own bit, for the first frame, has to be set, all
339 * descriptors for the same frame has to be set before, to
340 * avoid race condition.
344 p->des3 = cpu_to_le32(tdes3);
347 static void dwmac4_rd_prepare_tso_tx_desc(struct dma_desc *p, int is_fs,
348 int len1, int len2, bool tx_own,
349 bool ls, unsigned int tcphdrlen,
350 unsigned int tcppayloadlen)
352 unsigned int tdes3 = le32_to_cpu(p->des3);
355 p->des2 |= cpu_to_le32((len1 & TDES2_BUFFER1_SIZE_MASK));
358 p->des2 |= cpu_to_le32((len2 << TDES2_BUFFER2_SIZE_MASK_SHIFT)
359 & TDES2_BUFFER2_SIZE_MASK);
362 tdes3 |= TDES3_FIRST_DESCRIPTOR |
363 TDES3_TCP_SEGMENTATION_ENABLE |
364 ((tcphdrlen << TDES3_HDR_LEN_SHIFT) &
365 TDES3_SLOT_NUMBER_MASK) |
366 ((tcppayloadlen & TDES3_TCP_PKT_PAYLOAD_MASK));
368 tdes3 &= ~TDES3_FIRST_DESCRIPTOR;
372 tdes3 |= TDES3_LAST_DESCRIPTOR;
374 tdes3 &= ~TDES3_LAST_DESCRIPTOR;
376 /* Finally set the OWN bit. Later the DMA will start! */
381 /* When the own bit, for the first frame, has to be set, all
382 * descriptors for the same frame has to be set before, to
383 * avoid race condition.
387 p->des3 = cpu_to_le32(tdes3);
390 static void dwmac4_release_tx_desc(struct dma_desc *p, int mode)
398 static void dwmac4_rd_set_tx_ic(struct dma_desc *p)
400 p->des2 |= cpu_to_le32(TDES2_INTERRUPT_ON_COMPLETION);
403 static void dwmac4_display_ring(void *head, unsigned int size, bool rx)
405 struct dma_desc *p = (struct dma_desc *)head;
408 pr_info("%s descriptor ring:\n", rx ? "RX" : "TX");
410 for (i = 0; i < size; i++) {
411 pr_info("%03d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
412 i, (unsigned int)virt_to_phys(p),
413 le32_to_cpu(p->des0), le32_to_cpu(p->des1),
414 le32_to_cpu(p->des2), le32_to_cpu(p->des3));
419 static void dwmac4_set_mss_ctxt(struct dma_desc *p, unsigned int mss)
423 p->des2 = cpu_to_le32(mss);
424 p->des3 = cpu_to_le32(TDES3_CONTEXT_TYPE | TDES3_CTXT_TCMSSV);
427 static void dwmac4_get_addr(struct dma_desc *p, unsigned int *addr)
429 *addr = le32_to_cpu(p->des0);
432 static void dwmac4_set_addr(struct dma_desc *p, dma_addr_t addr)
434 p->des0 = cpu_to_le32(addr);
438 static void dwmac4_clear(struct dma_desc *p)
446 static void dwmac4_set_sarc(struct dma_desc *p, u32 sarc_type)
448 sarc_type <<= TDES3_SA_INSERT_CTRL_SHIFT;
450 p->des3 |= cpu_to_le32(sarc_type & TDES3_SA_INSERT_CTRL_MASK);
453 static int set_16kib_bfsize(int mtu)
457 if (unlikely(mtu >= BUF_SIZE_8KiB))
458 ret = BUF_SIZE_16KiB;
462 const struct stmmac_desc_ops dwmac4_desc_ops = {
463 .tx_status = dwmac4_wrback_get_tx_status,
464 .rx_status = dwmac4_wrback_get_rx_status,
465 .get_tx_len = dwmac4_rd_get_tx_len,
466 .get_tx_owner = dwmac4_get_tx_owner,
467 .set_tx_owner = dwmac4_set_tx_owner,
468 .set_rx_owner = dwmac4_set_rx_owner,
469 .get_tx_ls = dwmac4_get_tx_ls,
470 .get_rx_frame_len = dwmac4_wrback_get_rx_frame_len,
471 .enable_tx_timestamp = dwmac4_rd_enable_tx_timestamp,
472 .get_tx_timestamp_status = dwmac4_wrback_get_tx_timestamp_status,
473 .get_rx_timestamp_status = dwmac4_wrback_get_rx_timestamp_status,
474 .get_timestamp = dwmac4_get_timestamp,
475 .set_tx_ic = dwmac4_rd_set_tx_ic,
476 .prepare_tx_desc = dwmac4_rd_prepare_tx_desc,
477 .prepare_tso_tx_desc = dwmac4_rd_prepare_tso_tx_desc,
478 .release_tx_desc = dwmac4_release_tx_desc,
479 .init_rx_desc = dwmac4_rd_init_rx_desc,
480 .init_tx_desc = dwmac4_rd_init_tx_desc,
481 .display_ring = dwmac4_display_ring,
482 .set_mss = dwmac4_set_mss_ctxt,
483 .get_addr = dwmac4_get_addr,
484 .set_addr = dwmac4_set_addr,
485 .clear = dwmac4_clear,
486 .set_sarc = dwmac4_set_sarc,
489 const struct stmmac_mode_ops dwmac4_ring_mode_ops = {
490 .set_16kib_bfsize = set_16kib_bfsize,