drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c

   1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
   2 /*
   3  * Copyright (c) 2018 Synopsys, Inc. and/or its affiliates.
   4  * stmmac XGMAC support.
   5  */
   6
   7 #include <linux/iopoll.h>
   8 #include "stmmac.h"
   9 #include "dwxgmac2.h"
  10
  11 static int dwxgmac2_dma_reset(void __iomem *ioaddr)
  12 {
  13         u32 value = readl(ioaddr + XGMAC_DMA_MODE);
  14
  15         /* DMA SW reset */
  16         writel(value | XGMAC_SWR, ioaddr + XGMAC_DMA_MODE);
  17
  18         return readl_poll_timeout(ioaddr + XGMAC_DMA_MODE, value,
  19                                   !(value & XGMAC_SWR), 0, 100000);
  20 }
  21
  22 static void dwxgmac2_dma_init(void __iomem *ioaddr,
  23                               struct stmmac_dma_cfg *dma_cfg, int atds)
  24 {
  25         u32 value = readl(ioaddr + XGMAC_DMA_SYSBUS_MODE);
  26
  27         if (dma_cfg->aal)
  28                 value |= XGMAC_AAL;
  29
  30         writel(value, ioaddr + XGMAC_DMA_SYSBUS_MODE);
  31 }
  32
  33 static void dwxgmac2_dma_init_chan(void __iomem *ioaddr,
  34                                    struct stmmac_dma_cfg *dma_cfg, u32 chan)
  35 {
  36         u32 value = readl(ioaddr + XGMAC_DMA_CH_CONTROL(chan));
  37
  38         if (dma_cfg->pblx8)
  39                 value |= XGMAC_PBLx8;
  40
  41         writel(value, ioaddr + XGMAC_DMA_CH_CONTROL(chan));
  42         writel(XGMAC_DMA_INT_DEFAULT_EN, ioaddr + XGMAC_DMA_CH_INT_EN(chan));
  43 }
  44
  45 static void dwxgmac2_dma_init_rx_chan(void __iomem *ioaddr,
  46                                       struct stmmac_dma_cfg *dma_cfg,
  47                                       u32 dma_rx_phy, u32 chan)
  48 {
  49         u32 rxpbl = dma_cfg->rxpbl ?: dma_cfg->pbl;
  50         u32 value;
  51
  52         value = readl(ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan));
  53         value &= ~XGMAC_RxPBL;
  54         value |= (rxpbl << XGMAC_RxPBL_SHIFT) & XGMAC_RxPBL;
  55         writel(value, ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan));
  56
  57         writel(dma_rx_phy, ioaddr + XGMAC_DMA_CH_RxDESC_LADDR(chan));
  58 }
  59
  60 static void dwxgmac2_dma_init_tx_chan(void __iomem *ioaddr,
  61                                       struct stmmac_dma_cfg *dma_cfg,
  62                                       u32 dma_tx_phy, u32 chan)
  63 {
  64         u32 txpbl = dma_cfg->txpbl ?: dma_cfg->pbl;
  65         u32 value;
  66
  67         value = readl(ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan));
  68         value &= ~XGMAC_TxPBL;
  69         value |= (txpbl << XGMAC_TxPBL_SHIFT) & XGMAC_TxPBL;
  70         value |= XGMAC_OSP;
  71         writel(value, ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan));
  72
  73         writel(dma_tx_phy, ioaddr + XGMAC_DMA_CH_TxDESC_LADDR(chan));
  74 }
  75
  76 static void dwxgmac2_dma_axi(void __iomem *ioaddr, struct stmmac_axi *axi)
  77 {
  78         u32 value = readl(ioaddr + XGMAC_DMA_SYSBUS_MODE);
  79         int i;
  80
  81         if (axi->axi_lpi_en)
  82                 value |= XGMAC_EN_LPI;
  83         if (axi->axi_xit_frm)
  84                 value |= XGMAC_LPI_XIT_PKT;
  85
  86         value &= ~XGMAC_WR_OSR_LMT;
  87         value |= (axi->axi_wr_osr_lmt << XGMAC_WR_OSR_LMT_SHIFT) &
  88                 XGMAC_WR_OSR_LMT;
  89
  90         value &= ~XGMAC_RD_OSR_LMT;
  91         value |= (axi->axi_rd_osr_lmt << XGMAC_RD_OSR_LMT_SHIFT) &
  92                 XGMAC_RD_OSR_LMT;
  93
  94         value &= ~XGMAC_BLEN;
  95         for (i = 0; i < AXI_BLEN; i++) {
  96                 if (axi->axi_blen[i])
  97                         value &= ~XGMAC_UNDEF;
  98
  99                 switch (axi->axi_blen[i]) {
 100                 case 256:
 101                         value |= XGMAC_BLEN256;
 102                         break;
 103                 case 128:
 104                         value |= XGMAC_BLEN128;
 105                         break;
 106                 case 64:
 107                         value |= XGMAC_BLEN64;
 108                         break;
 109                 case 32:
 110                         value |= XGMAC_BLEN32;
 111                         break;
 112                 case 16:
 113                         value |= XGMAC_BLEN16;
 114                         break;
 115                 case 8:
 116                         value |= XGMAC_BLEN8;
 117                         break;
 118                 case 4:
 119                         value |= XGMAC_BLEN4;
 120                         break;
 121                 }
 122         }
 123
 124         writel(value, ioaddr + XGMAC_DMA_SYSBUS_MODE);
 125 }
 126
 127 static void dwxgmac2_dma_rx_mode(void __iomem *ioaddr, int mode,
 128                                  u32 channel, int fifosz, u8 qmode)
 129 {
 130         u32 value = readl(ioaddr + XGMAC_MTL_RXQ_OPMODE(channel));
 131         unsigned int rqs = fifosz / 256 - 1;
 132
 133         if (mode == SF_DMA_MODE) {
 134                 value |= XGMAC_RSF;
 135         } else {
 136                 value &= ~XGMAC_RSF;
 137                 value &= ~XGMAC_RTC;
 138
 139                 if (mode <= 64)
 140                         value |= 0x0 << XGMAC_RTC_SHIFT;
 141                 else if (mode <= 96)
 142                         value |= 0x2 << XGMAC_RTC_SHIFT;
 143                 else
 144                         value |= 0x3 << XGMAC_RTC_SHIFT;
 145         }
 146
 147         value &= ~XGMAC_RQS;
 148         value |= (rqs << XGMAC_RQS_SHIFT) & XGMAC_RQS;
 149
 150         if ((fifosz >= 4096) && (qmode != MTL_QUEUE_AVB)) {
 151                 u32 flow = readl(ioaddr + XGMAC_MTL_RXQ_FLOW_CONTROL(channel));
 152                 unsigned int rfd, rfa;
 153
 154                 value |= XGMAC_EHFC;
 155
 156                 /* Set Threshold for Activating Flow Control to min 2 frames,
 157                  * i.e. 1500 * 2 = 3000 bytes.
 158                  *
 159                  * Set Threshold for Deactivating Flow Control to min 1 frame,
 160                  * i.e. 1500 bytes.
 161                  */
 162                 switch (fifosz) {
 163                 case 4096:
 164                         /* This violates the above formula because of FIFO size
 165                          * limit therefore overflow may occur in spite of this.
 166                          */
 167                         rfd = 0x03; /* Full-2.5K */
 168                         rfa = 0x01; /* Full-1.5K */
 169                         break;
 170
 171                 case 8192:
 172                         rfd = 0x06; /* Full-4K */
 173                         rfa = 0x0a; /* Full-6K */
 174                         break;
 175
 176                 case 16384:
 177                         rfd = 0x06; /* Full-4K */
 178                         rfa = 0x12; /* Full-10K */
 179                         break;
 180
 181                 default:
 182                         rfd = 0x06; /* Full-4K */
 183                         rfa = 0x1e; /* Full-16K */
 184                         break;
 185                 }
 186
 187                 flow &= ~XGMAC_RFD;
 188                 flow |= rfd << XGMAC_RFD_SHIFT;
 189
 190                 flow &= ~XGMAC_RFA;
 191                 flow |= rfa << XGMAC_RFA_SHIFT;
 192
 193                 writel(flow, ioaddr + XGMAC_MTL_RXQ_FLOW_CONTROL(channel));
 194         }
 195
 196         writel(value, ioaddr + XGMAC_MTL_RXQ_OPMODE(channel));
 197
 198         /* Enable MTL RX overflow */
 199         value = readl(ioaddr + XGMAC_MTL_QINTEN(channel));
 200         writel(value | XGMAC_RXOIE, ioaddr + XGMAC_MTL_QINTEN(channel));
 201 }
 202
 203 static void dwxgmac2_dma_tx_mode(void __iomem *ioaddr, int mode,
 204                                  u32 channel, int fifosz, u8 qmode)
 205 {
 206         u32 value = readl(ioaddr + XGMAC_MTL_TXQ_OPMODE(channel));
 207         unsigned int tqs = fifosz / 256 - 1;
 208
 209         if (mode == SF_DMA_MODE) {
 210                 value |= XGMAC_TSF;
 211         } else {
 212                 value &= ~XGMAC_TSF;
 213                 value &= ~XGMAC_TTC;
 214
 215                 if (mode <= 64)
 216                         value |= 0x0 << XGMAC_TTC_SHIFT;
 217                 else if (mode <= 96)
 218                         value |= 0x2 << XGMAC_TTC_SHIFT;
 219                 else if (mode <= 128)
 220                         value |= 0x3 << XGMAC_TTC_SHIFT;
 221                 else if (mode <= 192)
 222                         value |= 0x4 << XGMAC_TTC_SHIFT;
 223                 else if (mode <= 256)
 224                         value |= 0x5 << XGMAC_TTC_SHIFT;
 225                 else if (mode <= 384)
 226                         value |= 0x6 << XGMAC_TTC_SHIFT;
 227                 else
 228                         value |= 0x7 << XGMAC_TTC_SHIFT;
 229         }
 230
 231         /* Use static TC to Queue mapping */
 232         value |= (channel << XGMAC_Q2TCMAP_SHIFT) & XGMAC_Q2TCMAP;
 233
 234         value &= ~XGMAC_TXQEN;
 235         if (qmode != MTL_QUEUE_AVB)
 236                 value |= 0x2 << XGMAC_TXQEN_SHIFT;
 237         else
 238                 value |= 0x1 << XGMAC_TXQEN_SHIFT;
 239
 240         value &= ~XGMAC_TQS;
 241         value |= (tqs << XGMAC_TQS_SHIFT) & XGMAC_TQS;
 242
 243         writel(value, ioaddr +  XGMAC_MTL_TXQ_OPMODE(channel));
 244 }
 245
 246 static void dwxgmac2_enable_dma_irq(void __iomem *ioaddr, u32 chan)
 247 {
 248         writel(XGMAC_DMA_INT_DEFAULT_EN, ioaddr + XGMAC_DMA_CH_INT_EN(chan));
 249 }
 250
 251 static void dwxgmac2_disable_dma_irq(void __iomem *ioaddr, u32 chan)
 252 {
 253         writel(0, ioaddr + XGMAC_DMA_CH_INT_EN(chan));
 254 }
 255
 256 static void dwxgmac2_dma_start_tx(void __iomem *ioaddr, u32 chan)
 257 {
 258         u32 value;
 259
 260         value = readl(ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan));
 261         value |= XGMAC_TXST;
 262         writel(value, ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan));
 263
 264         value = readl(ioaddr + XGMAC_TX_CONFIG);
 265         value |= XGMAC_CONFIG_TE;
 266         writel(value, ioaddr + XGMAC_TX_CONFIG);
 267 }
 268
 269 static void dwxgmac2_dma_stop_tx(void __iomem *ioaddr, u32 chan)
 270 {
 271         u32 value;
 272
 273         value = readl(ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan));
 274         value &= ~XGMAC_TXST;
 275         writel(value, ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan));
 276
 277         value = readl(ioaddr + XGMAC_TX_CONFIG);
 278         value &= ~XGMAC_CONFIG_TE;
 279         writel(value, ioaddr + XGMAC_TX_CONFIG);
 280 }
 281
 282 static void dwxgmac2_dma_start_rx(void __iomem *ioaddr, u32 chan)
 283 {
 284         u32 value;
 285
 286         value = readl(ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan));
 287         value |= XGMAC_RXST;
 288         writel(value, ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan));
 289
 290         value = readl(ioaddr + XGMAC_RX_CONFIG);
 291         value |= XGMAC_CONFIG_RE;
 292         writel(value, ioaddr + XGMAC_RX_CONFIG);
 293 }
 294
 295 static void dwxgmac2_dma_stop_rx(void __iomem *ioaddr, u32 chan)
 296 {
 297         u32 value;
 298
 299         value = readl(ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan));
 300         value &= ~XGMAC_RXST;
 301         writel(value, ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan));
 302
 303         value = readl(ioaddr + XGMAC_RX_CONFIG);
 304         value &= ~XGMAC_CONFIG_RE;
 305         writel(value, ioaddr + XGMAC_RX_CONFIG);
 306 }
 307
 308 static int dwxgmac2_dma_interrupt(void __iomem *ioaddr,
 309                                   struct stmmac_extra_stats *x, u32 chan)
 310 {
 311         u32 intr_status = readl(ioaddr + XGMAC_DMA_CH_STATUS(chan));
 312         u32 intr_en = readl(ioaddr + XGMAC_DMA_CH_INT_EN(chan));
 313         int ret = 0;
 314
 315         /* ABNORMAL interrupts */
 316         if (unlikely(intr_status & XGMAC_AIS)) {
 317                 if (unlikely(intr_status & XGMAC_TPS)) {
 318                         x->tx_process_stopped_irq++;
 319                         ret |= tx_hard_error;
 320                 }
 321                 if (unlikely(intr_status & XGMAC_FBE)) {
 322                         x->fatal_bus_error_irq++;
 323                         ret |= tx_hard_error;
 324                 }
 325         }
 326
 327         /* TX/RX NORMAL interrupts */
 328         if (likely(intr_status & XGMAC_NIS)) {
 329                 x->normal_irq_n++;
 330
 331                 if (likely(intr_status & XGMAC_RI)) {
 332                         x->rx_normal_irq_n++;
 333                         ret |= handle_rx;
 334                 }
 335                 if (likely(intr_status & (XGMAC_TI | XGMAC_TBU))) {
 336                         x->tx_normal_irq_n++;
 337                         ret |= handle_tx;
 338                 }
 339         }
 340
 341         /* Clear interrupts */
 342         writel(intr_en & intr_status, ioaddr + XGMAC_DMA_CH_STATUS(chan));
 343
 344         return ret;
 345 }
 346
 347 static void dwxgmac2_get_hw_feature(void __iomem *ioaddr,
 348                                     struct dma_features *dma_cap)
 349 {
 350         u32 hw_cap;
 351
 352         /*  MAC HW feature 0 */
 353         hw_cap = readl(ioaddr + XGMAC_HW_FEATURE0);
 354         dma_cap->rx_coe = (hw_cap & XGMAC_HWFEAT_RXCOESEL) >> 16;
 355         dma_cap->tx_coe = (hw_cap & XGMAC_HWFEAT_TXCOESEL) >> 14;
 356         dma_cap->atime_stamp = (hw_cap & XGMAC_HWFEAT_TSSEL) >> 12;
 357         dma_cap->av = (hw_cap & XGMAC_HWFEAT_AVSEL) >> 11;
 358         dma_cap->av &= (hw_cap & XGMAC_HWFEAT_RAVSEL) >> 10;
 359         dma_cap->pmt_magic_frame = (hw_cap & XGMAC_HWFEAT_MGKSEL) >> 7;
 360         dma_cap->pmt_remote_wake_up = (hw_cap & XGMAC_HWFEAT_RWKSEL) >> 6;
 361         dma_cap->mbps_1000 = (hw_cap & XGMAC_HWFEAT_GMIISEL) >> 1;
 362
 363         /* MAC HW feature 1 */
 364         hw_cap = readl(ioaddr + XGMAC_HW_FEATURE1);
 365         dma_cap->tsoen = (hw_cap & XGMAC_HWFEAT_TSOEN) >> 18;
 366         dma_cap->tx_fifo_size =
 367                 128 << ((hw_cap & XGMAC_HWFEAT_TXFIFOSIZE) >> 6);
 368         dma_cap->rx_fifo_size =
 369                 128 << ((hw_cap & XGMAC_HWFEAT_RXFIFOSIZE) >> 0);
 370
 371         /* MAC HW feature 2 */
 372         hw_cap = readl(ioaddr + XGMAC_HW_FEATURE2);
 373         dma_cap->pps_out_num = (hw_cap & XGMAC_HWFEAT_PPSOUTNUM) >> 24;
 374         dma_cap->number_tx_channel =
 375                 ((hw_cap & XGMAC_HWFEAT_TXCHCNT) >> 18) + 1;
 376         dma_cap->number_rx_channel =
 377                 ((hw_cap & XGMAC_HWFEAT_RXCHCNT) >> 12) + 1;
 378         dma_cap->number_tx_queues =
 379                 ((hw_cap & XGMAC_HWFEAT_TXQCNT) >> 6) + 1;
 380         dma_cap->number_rx_queues =
 381                 ((hw_cap & XGMAC_HWFEAT_RXQCNT) >> 0) + 1;
 382 }
 383
 384 static void dwxgmac2_rx_watchdog(void __iomem *ioaddr, u32 riwt, u32 nchan)
 385 {
 386         u32 i;
 387
 388         for (i = 0; i < nchan; i++)
 389                 writel(riwt & XGMAC_RWT, ioaddr + XGMAC_DMA_CH_Rx_WATCHDOG(i));
 390 }
 391
 392 static void dwxgmac2_set_rx_ring_len(void __iomem *ioaddr, u32 len, u32 chan)
 393 {
 394         writel(len, ioaddr + XGMAC_DMA_CH_RxDESC_RING_LEN(chan));
 395 }
 396
 397 static void dwxgmac2_set_tx_ring_len(void __iomem *ioaddr, u32 len, u32 chan)
 398 {
 399         writel(len, ioaddr + XGMAC_DMA_CH_TxDESC_RING_LEN(chan));
 400 }
 401
 402 static void dwxgmac2_set_rx_tail_ptr(void __iomem *ioaddr, u32 ptr, u32 chan)
 403 {
 404         writel(ptr, ioaddr + XGMAC_DMA_CH_RxDESC_TAIL_LPTR(chan));
 405 }
 406
 407 static void dwxgmac2_set_tx_tail_ptr(void __iomem *ioaddr, u32 ptr, u32 chan)
 408 {
 409         writel(ptr, ioaddr + XGMAC_DMA_CH_TxDESC_TAIL_LPTR(chan));
 410 }
 411
 412 static void dwxgmac2_enable_tso(void __iomem *ioaddr, bool en, u32 chan)
 413 {
 414         u32 value = readl(ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan));
 415
 416         if (en)
 417                 value |= XGMAC_TSE;
 418         else
 419                 value &= ~XGMAC_TSE;
 420
 421         writel(value, ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan));
 422 }
 423
 424 static void dwxgmac2_qmode(void __iomem *ioaddr, u32 channel, u8 qmode)
 425 {
 426         u32 value = readl(ioaddr + XGMAC_MTL_TXQ_OPMODE(channel));
 427
 428         value &= ~XGMAC_TXQEN;
 429         if (qmode != MTL_QUEUE_AVB) {
 430                 value |= 0x2 << XGMAC_TXQEN_SHIFT;
 431                 writel(0, ioaddr + XGMAC_MTL_TCx_ETS_CONTROL(channel));
 432         } else {
 433                 value |= 0x1 << XGMAC_TXQEN_SHIFT;
 434         }
 435
 436         writel(value, ioaddr +  XGMAC_MTL_TXQ_OPMODE(channel));
 437 }
 438
 439 static void dwxgmac2_set_bfsize(void __iomem *ioaddr, int bfsize, u32 chan)
 440 {
 441         u32 value;
 442
 443         value = readl(ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan));
 444         value |= bfsize << 1;
 445         writel(value, ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan));
 446 }
 447
 448 const struct stmmac_dma_ops dwxgmac210_dma_ops = {
 449         .reset = dwxgmac2_dma_reset,
 450         .init = dwxgmac2_dma_init,
 451         .init_chan = dwxgmac2_dma_init_chan,
 452         .init_rx_chan = dwxgmac2_dma_init_rx_chan,
 453         .init_tx_chan = dwxgmac2_dma_init_tx_chan,
 454         .axi = dwxgmac2_dma_axi,
 455         .dump_regs = NULL,
 456         .dma_rx_mode = dwxgmac2_dma_rx_mode,
 457         .dma_tx_mode = dwxgmac2_dma_tx_mode,
 458         .enable_dma_irq = dwxgmac2_enable_dma_irq,
 459         .disable_dma_irq = dwxgmac2_disable_dma_irq,
 460         .start_tx = dwxgmac2_dma_start_tx,
 461         .stop_tx = dwxgmac2_dma_stop_tx,
 462         .start_rx = dwxgmac2_dma_start_rx,
 463         .stop_rx = dwxgmac2_dma_stop_rx,
 464         .dma_interrupt = dwxgmac2_dma_interrupt,
 465         .get_hw_feature = dwxgmac2_get_hw_feature,
 466         .rx_watchdog = dwxgmac2_rx_watchdog,
 467         .set_rx_ring_len = dwxgmac2_set_rx_ring_len,
 468         .set_tx_ring_len = dwxgmac2_set_tx_ring_len,
 469         .set_rx_tail_ptr = dwxgmac2_set_rx_tail_ptr,
 470         .set_tx_tail_ptr = dwxgmac2_set_tx_tail_ptr,
 471         .enable_tso = dwxgmac2_enable_tso,
 472         .qmode = dwxgmac2_qmode,
 473         .set_bfsize = dwxgmac2_set_bfsize,
 474 };