drivers/net/ethernet/stmicro/stmmac/stmmac_main.c

   1 /*******************************************************************************
   2   This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers.
   3   ST Ethernet IPs are built around a Synopsys IP Core.
   4
   5         Copyright(C) 2007-2011 STMicroelectronics Ltd
   6
   7   This program is free software; you can redistribute it and/or modify it
   8   under the terms and conditions of the GNU General Public License,
   9   version 2, as published by the Free Software Foundation.
  10
  11   This program is distributed in the hope it will be useful, but WITHOUT
  12   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  14   more details.
  15
  16   You should have received a copy of the GNU General Public License along with
  17   this program; if not, write to the Free Software Foundation, Inc.,
  18   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  19
  20   The full GNU General Public License is included in this distribution in
  21   the file called "COPYING".
  22
  23   Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
  24
  25   Documentation available at:
  26         http://www.stlinux.com
  27   Support available at:
  28         https://bugzilla.stlinux.com/
  29 *******************************************************************************/
  30
  31 #include <linux/clk.h>
  32 #include <linux/kernel.h>
  33 #include <linux/interrupt.h>
  34 #include <linux/ip.h>
  35 #include <linux/tcp.h>
  36 #include <linux/skbuff.h>
  37 #include <linux/ethtool.h>
  38 #include <linux/if_ether.h>
  39 #include <linux/crc32.h>
  40 #include <linux/mii.h>
  41 #include <linux/if.h>
  42 #include <linux/if_vlan.h>
  43 #include <linux/dma-mapping.h>
  44 #include <linux/slab.h>
  45 #include <linux/prefetch.h>
  46 #include <linux/pinctrl/consumer.h>
  47 #ifdef CONFIG_DEBUG_FS
  48 #include <linux/debugfs.h>
  49 #include <linux/seq_file.h>
  50 #endif /* CONFIG_DEBUG_FS */
  51 #include <linux/net_tstamp.h>
  52 #include "stmmac_ptp.h"
  53 #include "stmmac.h"
  54 #include <linux/reset.h>
  55 #include <linux/of_mdio.h>
  56 #include "dwmac1000.h"
  57
  58 #define STMMAC_ALIGN(x) L1_CACHE_ALIGN(x)
  59 #define TSO_MAX_BUFF_SIZE       (SZ_16K - 1)
  60
  61 /* Module parameters */
  62 #define TX_TIMEO        5000
  63 static int watchdog = TX_TIMEO;
  64 module_param(watchdog, int, S_IRUGO | S_IWUSR);
  65 MODULE_PARM_DESC(watchdog, "Transmit timeout in milliseconds (default 5s)");
  66
  67 static int debug = -1;
  68 module_param(debug, int, S_IRUGO | S_IWUSR);
  69 MODULE_PARM_DESC(debug, "Message Level (-1: default, 0: no output, 16: all)");
  70
  71 static int phyaddr = -1;
  72 module_param(phyaddr, int, S_IRUGO);
  73 MODULE_PARM_DESC(phyaddr, "Physical device address");
  74
  75 #define STMMAC_TX_THRESH        (DMA_TX_SIZE / 4)
  76 #define STMMAC_RX_THRESH        (DMA_RX_SIZE / 4)
  77
  78 static int flow_ctrl = FLOW_OFF;
  79 module_param(flow_ctrl, int, S_IRUGO | S_IWUSR);
  80 MODULE_PARM_DESC(flow_ctrl, "Flow control ability [on/off]");
  81
  82 static int pause = PAUSE_TIME;
  83 module_param(pause, int, S_IRUGO | S_IWUSR);
  84 MODULE_PARM_DESC(pause, "Flow Control Pause Time");
  85
  86 #define TC_DEFAULT 64
  87 static int tc = TC_DEFAULT;
  88 module_param(tc, int, S_IRUGO | S_IWUSR);
  89 MODULE_PARM_DESC(tc, "DMA threshold control value");
  90
  91 #define DEFAULT_BUFSIZE 1536
  92 static int buf_sz = DEFAULT_BUFSIZE;
  93 module_param(buf_sz, int, S_IRUGO | S_IWUSR);
  94 MODULE_PARM_DESC(buf_sz, "DMA buffer size");
  95
  96 #define STMMAC_RX_COPYBREAK     256
  97
  98 static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE |
  99                                       NETIF_MSG_LINK | NETIF_MSG_IFUP |
 100                                       NETIF_MSG_IFDOWN | NETIF_MSG_TIMER);
 101
 102 #define STMMAC_DEFAULT_LPI_TIMER        1000
 103 static int eee_timer = STMMAC_DEFAULT_LPI_TIMER;
 104 module_param(eee_timer, int, S_IRUGO | S_IWUSR);
 105 MODULE_PARM_DESC(eee_timer, "LPI tx expiration time in msec");
 106 #define STMMAC_LPI_T(x) (jiffies + msecs_to_jiffies(x))
 107
 108 /* By default the driver will use the ring mode to manage tx and rx descriptors,
 109  * but allow user to force to use the chain instead of the ring
 110  */
 111 static unsigned int chain_mode;
 112 module_param(chain_mode, int, S_IRUGO);
 113 MODULE_PARM_DESC(chain_mode, "To use chain instead of ring mode");
 114
 115 static irqreturn_t stmmac_interrupt(int irq, void *dev_id);
 116
 117 #ifdef CONFIG_DEBUG_FS
 118 static int stmmac_init_fs(struct net_device *dev);
 119 static void stmmac_exit_fs(struct net_device *dev);
 120 #endif
 121
 122 #define STMMAC_COAL_TIMER(x) (jiffies + usecs_to_jiffies(x))
 123
 124 /**
 125  * stmmac_verify_args - verify the driver parameters.
 126  * Description: it checks the driver parameters and set a default in case of
 127  * errors.
 128  */
 129 static void stmmac_verify_args(void)
 130 {
 131         if (unlikely(watchdog < 0))
 132                 watchdog = TX_TIMEO;
 133         if (unlikely((buf_sz < DEFAULT_BUFSIZE) || (buf_sz > BUF_SIZE_16KiB)))
 134                 buf_sz = DEFAULT_BUFSIZE;
 135         if (unlikely(flow_ctrl > 1))
 136                 flow_ctrl = FLOW_AUTO;
 137         else if (likely(flow_ctrl < 0))
 138                 flow_ctrl = FLOW_OFF;
 139         if (unlikely((pause < 0) || (pause > 0xffff)))
 140                 pause = PAUSE_TIME;
 141         if (eee_timer < 0)
 142                 eee_timer = STMMAC_DEFAULT_LPI_TIMER;
 143 }
 144
 145 /**
 146  * stmmac_clk_csr_set - dynamically set the MDC clock
 147  * @priv: driver private structure
 148  * Description: this is to dynamically set the MDC clock according to the csr
 149  * clock input.
 150  * Note:
 151  *      If a specific clk_csr value is passed from the platform
 152  *      this means that the CSR Clock Range selection cannot be
 153  *      changed at run-time and it is fixed (as reported in the driver
 154  *      documentation). Viceversa the driver will try to set the MDC
 155  *      clock dynamically according to the actual clock input.
 156  */
 157 static void stmmac_clk_csr_set(struct stmmac_priv *priv)
 158 {
 159         u32 clk_rate;
 160
 161         clk_rate = clk_get_rate(priv->plat->stmmac_clk);
 162
 163         /* Platform provided default clk_csr would be assumed valid
 164          * for all other cases except for the below mentioned ones.
 165          * For values higher than the IEEE 802.3 specified frequency
 166          * we can not estimate the proper divider as it is not known
 167          * the frequency of clk_csr_i. So we do not change the default
 168          * divider.
 169          */
 170         if (!(priv->clk_csr & MAC_CSR_H_FRQ_MASK)) {
 171                 if (clk_rate < CSR_F_35M)
 172                         priv->clk_csr = STMMAC_CSR_20_35M;
 173                 else if ((clk_rate >= CSR_F_35M) && (clk_rate < CSR_F_60M))
 174                         priv->clk_csr = STMMAC_CSR_35_60M;
 175                 else if ((clk_rate >= CSR_F_60M) && (clk_rate < CSR_F_100M))
 176                         priv->clk_csr = STMMAC_CSR_60_100M;
 177                 else if ((clk_rate >= CSR_F_100M) && (clk_rate < CSR_F_150M))
 178                         priv->clk_csr = STMMAC_CSR_100_150M;
 179                 else if ((clk_rate >= CSR_F_150M) && (clk_rate < CSR_F_250M))
 180                         priv->clk_csr = STMMAC_CSR_150_250M;
 181                 else if ((clk_rate >= CSR_F_250M) && (clk_rate < CSR_F_300M))
 182                         priv->clk_csr = STMMAC_CSR_250_300M;
 183         }
 184 }
 185
 186 static void print_pkt(unsigned char *buf, int len)
 187 {
 188         pr_debug("len = %d byte, buf addr: 0x%p\n", len, buf);
 189         print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, buf, len);
 190 }
 191
 192 static inline u32 stmmac_tx_avail(struct stmmac_priv *priv)
 193 {
 194         unsigned avail;
 195
 196         if (priv->dirty_tx > priv->cur_tx)
 197                 avail = priv->dirty_tx - priv->cur_tx - 1;
 198         else
 199                 avail = DMA_TX_SIZE - priv->cur_tx + priv->dirty_tx - 1;
 200
 201         return avail;
 202 }
 203
 204 static inline u32 stmmac_rx_dirty(struct stmmac_priv *priv)
 205 {
 206         unsigned dirty;
 207
 208         if (priv->dirty_rx <= priv->cur_rx)
 209                 dirty = priv->cur_rx - priv->dirty_rx;
 210         else
 211                 dirty = DMA_RX_SIZE - priv->dirty_rx + priv->cur_rx;
 212
 213         return dirty;
 214 }
 215
 216 /**
 217  * stmmac_hw_fix_mac_speed - callback for speed selection
 218  * @priv: driver private structure
 219  * Description: on some platforms (e.g. ST), some HW system configuraton
 220  * registers have to be set according to the link speed negotiated.
 221  */
 222 static inline void stmmac_hw_fix_mac_speed(struct stmmac_priv *priv)
 223 {
 224         struct net_device *ndev = priv->dev;
 225         struct phy_device *phydev = ndev->phydev;
 226
 227         if (likely(priv->plat->fix_mac_speed))
 228                 priv->plat->fix_mac_speed(priv->plat->bsp_priv, phydev->speed);
 229 }
 230
 231 /**
 232  * stmmac_enable_eee_mode - check and enter in LPI mode
 233  * @priv: driver private structure
 234  * Description: this function is to verify and enter in LPI mode in case of
 235  * EEE.
 236  */
 237 static void stmmac_enable_eee_mode(struct stmmac_priv *priv)
 238 {
 239         /* Check and enter in LPI mode */
 240         if ((priv->dirty_tx == priv->cur_tx) &&
 241             (priv->tx_path_in_lpi_mode == false))
 242                 priv->hw->mac->set_eee_mode(priv->hw,
 243                                             priv->plat->en_tx_lpi_clockgating);
 244 }
 245
 246 /**
 247  * stmmac_disable_eee_mode - disable and exit from LPI mode
 248  * @priv: driver private structure
 249  * Description: this function is to exit and disable EEE in case of
 250  * LPI state is true. This is called by the xmit.
 251  */
 252 void stmmac_disable_eee_mode(struct stmmac_priv *priv)
 253 {
 254         priv->hw->mac->reset_eee_mode(priv->hw);
 255         del_timer_sync(&priv->eee_ctrl_timer);
 256         priv->tx_path_in_lpi_mode = false;
 257 }
 258
 259 /**
 260  * stmmac_eee_ctrl_timer - EEE TX SW timer.
 261  * @arg : data hook
 262  * Description:
 263  *  if there is no data transfer and if we are not in LPI state,
 264  *  then MAC Transmitter can be moved to LPI state.
 265  */
 266 static void stmmac_eee_ctrl_timer(unsigned long arg)
 267 {
 268         struct stmmac_priv *priv = (struct stmmac_priv *)arg;
 269
 270         stmmac_enable_eee_mode(priv);
 271         mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer));
 272 }
 273
 274 /**
 275  * stmmac_eee_init - init EEE
 276  * @priv: driver private structure
 277  * Description:
 278  *  if the GMAC supports the EEE (from the HW cap reg) and the phy device
 279  *  can also manage EEE, this function enable the LPI state and start related
 280  *  timer.
 281  */
 282 bool stmmac_eee_init(struct stmmac_priv *priv)
 283 {
 284         struct net_device *ndev = priv->dev;
 285         unsigned long flags;
 286         bool ret = false;
 287
 288         /* Using PCS we cannot dial with the phy registers at this stage
 289          * so we do not support extra feature like EEE.
 290          */
 291         if ((priv->hw->pcs == STMMAC_PCS_RGMII) ||
 292             (priv->hw->pcs == STMMAC_PCS_TBI) ||
 293             (priv->hw->pcs == STMMAC_PCS_RTBI))
 294                 goto out;
 295
 296         /* MAC core supports the EEE feature. */
 297         if (priv->dma_cap.eee) {
 298                 int tx_lpi_timer = priv->tx_lpi_timer;
 299
 300                 /* Check if the PHY supports EEE */
 301                 if (phy_init_eee(ndev->phydev, 1)) {
 302                         /* To manage at run-time if the EEE cannot be supported
 303                          * anymore (for example because the lp caps have been
 304                          * changed).
 305                          * In that case the driver disable own timers.
 306                          */
 307                         spin_lock_irqsave(&priv->lock, flags);
 308                         if (priv->eee_active) {
 309                                 netdev_dbg(priv->dev, "disable EEE\n");
 310                                 del_timer_sync(&priv->eee_ctrl_timer);
 311                                 priv->hw->mac->set_eee_timer(priv->hw, 0,
 312                                                              tx_lpi_timer);
 313                         }
 314                         priv->eee_active = 0;
 315                         spin_unlock_irqrestore(&priv->lock, flags);
 316                         goto out;
 317                 }
 318                 /* Activate the EEE and start timers */
 319                 spin_lock_irqsave(&priv->lock, flags);
 320                 if (!priv->eee_active) {
 321                         priv->eee_active = 1;
 322                         setup_timer(&priv->eee_ctrl_timer,
 323                                     stmmac_eee_ctrl_timer,
 324                                     (unsigned long)priv);
 325                         mod_timer(&priv->eee_ctrl_timer,
 326                                   STMMAC_LPI_T(eee_timer));
 327
 328                         priv->hw->mac->set_eee_timer(priv->hw,
 329                                                      STMMAC_DEFAULT_LIT_LS,
 330                                                      tx_lpi_timer);
 331                 }
 332                 /* Set HW EEE according to the speed */
 333                 priv->hw->mac->set_eee_pls(priv->hw, ndev->phydev->link);
 334
 335                 ret = true;
 336                 spin_unlock_irqrestore(&priv->lock, flags);
 337
 338                 netdev_dbg(priv->dev, "Energy-Efficient Ethernet initialized\n");
 339         }
 340 out:
 341         return ret;
 342 }
 343
 344 /* stmmac_get_tx_hwtstamp - get HW TX timestamps
 345  * @priv: driver private structure
 346  * @p : descriptor pointer
 347  * @skb : the socket buffer
 348  * Description :
 349  * This function will read timestamp from the descriptor & pass it to stack.
 350  * and also perform some sanity checks.
 351  */
 352 static void stmmac_get_tx_hwtstamp(struct stmmac_priv *priv,
 353                                    struct dma_desc *p, struct sk_buff *skb)
 354 {
 355         struct skb_shared_hwtstamps shhwtstamp;
 356         u64 ns;
 357
 358         if (!priv->hwts_tx_en)
 359                 return;
 360
 361         /* exit if skb doesn't support hw tstamp */
 362         if (likely(!skb || !(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)))
 363                 return;
 364
 365         /* check tx tstamp status */
 366         if (!priv->hw->desc->get_tx_timestamp_status(p)) {
 367                 /* get the valid tstamp */
 368                 ns = priv->hw->desc->get_timestamp(p, priv->adv_ts);
 369
 370                 memset(&shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps));
 371                 shhwtstamp.hwtstamp = ns_to_ktime(ns);
 372
 373                 netdev_info(priv->dev, "get valid TX hw timestamp %llu\n", ns);
 374                 /* pass tstamp to stack */
 375                 skb_tstamp_tx(skb, &shhwtstamp);
 376         }
 377
 378         return;
 379 }
 380
 381 /* stmmac_get_rx_hwtstamp - get HW RX timestamps
 382  * @priv: driver private structure
 383  * @p : descriptor pointer
 384  * @np : next descriptor pointer
 385  * @skb : the socket buffer
 386  * Description :
 387  * This function will read received packet's timestamp from the descriptor
 388  * and pass it to stack. It also perform some sanity checks.
 389  */
 390 static void stmmac_get_rx_hwtstamp(struct stmmac_priv *priv, struct dma_desc *p,
 391                                    struct dma_desc *np, struct sk_buff *skb)
 392 {
 393         struct skb_shared_hwtstamps *shhwtstamp = NULL;
 394         u64 ns;
 395
 396         if (!priv->hwts_rx_en)
 397                 return;
 398
 399         /* Check if timestamp is available */
 400         if (!priv->hw->desc->get_rx_timestamp_status(p, priv->adv_ts)) {
 401                 /* For GMAC4, the valid timestamp is from CTX next desc. */
 402                 if (priv->plat->has_gmac4)
 403                         ns = priv->hw->desc->get_timestamp(np, priv->adv_ts);
 404                 else
 405                         ns = priv->hw->desc->get_timestamp(p, priv->adv_ts);
 406
 407                 netdev_info(priv->dev, "get valid RX hw timestamp %llu\n", ns);
 408                 shhwtstamp = skb_hwtstamps(skb);
 409                 memset(shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps));
 410                 shhwtstamp->hwtstamp = ns_to_ktime(ns);
 411         } else  {
 412                 netdev_err(priv->dev, "cannot get RX hw timestamp\n");
 413         }
 414 }
 415
 416 /**
 417  *  stmmac_hwtstamp_ioctl - control hardware timestamping.
 418  *  @dev: device pointer.
 419  *  @ifr: An IOCTL specefic structure, that can contain a pointer to
 420  *  a proprietary structure used to pass information to the driver.
 421  *  Description:
 422  *  This function configures the MAC to enable/disable both outgoing(TX)
 423  *  and incoming(RX) packets time stamping based on user input.
 424  *  Return Value:
 425  *  0 on success and an appropriate -ve integer on failure.
 426  */
 427 static int stmmac_hwtstamp_ioctl(struct net_device *dev, struct ifreq *ifr)
 428 {
 429         struct stmmac_priv *priv = netdev_priv(dev);
 430         struct hwtstamp_config config;
 431         struct timespec64 now;
 432         u64 temp = 0;
 433         u32 ptp_v2 = 0;
 434         u32 tstamp_all = 0;
 435         u32 ptp_over_ipv4_udp = 0;
 436         u32 ptp_over_ipv6_udp = 0;
 437         u32 ptp_over_ethernet = 0;
 438         u32 snap_type_sel = 0;
 439         u32 ts_master_en = 0;
 440         u32 ts_event_en = 0;
 441         u32 value = 0;
 442         u32 sec_inc;
 443
 444         if (!(priv->dma_cap.time_stamp || priv->adv_ts)) {
 445                 netdev_alert(priv->dev, "No support for HW time stamping\n");
 446                 priv->hwts_tx_en = 0;
 447                 priv->hwts_rx_en = 0;
 448
 449                 return -EOPNOTSUPP;
 450         }
 451
 452         if (copy_from_user(&config, ifr->ifr_data,
 453                            sizeof(struct hwtstamp_config)))
 454                 return -EFAULT;
 455
 456         netdev_dbg(priv->dev, "%s config flags:0x%x, tx_type:0x%x, rx_filter:0x%x\n",
 457                    __func__, config.flags, config.tx_type, config.rx_filter);
 458
 459         /* reserved for future extensions */
 460         if (config.flags)
 461                 return -EINVAL;
 462
 463         if (config.tx_type != HWTSTAMP_TX_OFF &&
 464             config.tx_type != HWTSTAMP_TX_ON)
 465                 return -ERANGE;
 466
 467         if (priv->adv_ts) {
 468                 switch (config.rx_filter) {
 469                 case HWTSTAMP_FILTER_NONE:
 470                         /* time stamp no incoming packet at all */
 471                         config.rx_filter = HWTSTAMP_FILTER_NONE;
 472                         break;
 473
 474                 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
 475                         /* PTP v1, UDP, any kind of event packet */
 476                         config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
 477                         /* take time stamp for all event messages */
 478                         snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
 479
 480                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 481                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 482                         break;
 483
 484                 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
 485                         /* PTP v1, UDP, Sync packet */
 486                         config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_SYNC;
 487                         /* take time stamp for SYNC messages only */
 488                         ts_event_en = PTP_TCR_TSEVNTENA;
 489
 490                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 491                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 492                         break;
 493
 494                 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
 495                         /* PTP v1, UDP, Delay_req packet */
 496                         config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ;
 497                         /* take time stamp for Delay_Req messages only */
 498                         ts_master_en = PTP_TCR_TSMSTRENA;
 499                         ts_event_en = PTP_TCR_TSEVNTENA;
 500
 501                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 502                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 503                         break;
 504
 505                 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
 506                         /* PTP v2, UDP, any kind of event packet */
 507                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
 508                         ptp_v2 = PTP_TCR_TSVER2ENA;
 509                         /* take time stamp for all event messages */
 510                         snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
 511
 512                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 513                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 514                         break;
 515
 516                 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
 517                         /* PTP v2, UDP, Sync packet */
 518                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_SYNC;
 519                         ptp_v2 = PTP_TCR_TSVER2ENA;
 520                         /* take time stamp for SYNC messages only */
 521                         ts_event_en = PTP_TCR_TSEVNTENA;
 522
 523                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 524                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 525                         break;
 526
 527                 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
 528                         /* PTP v2, UDP, Delay_req packet */
 529                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ;
 530                         ptp_v2 = PTP_TCR_TSVER2ENA;
 531                         /* take time stamp for Delay_Req messages only */
 532                         ts_master_en = PTP_TCR_TSMSTRENA;
 533                         ts_event_en = PTP_TCR_TSEVNTENA;
 534
 535                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 536                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 537                         break;
 538
 539                 case HWTSTAMP_FILTER_PTP_V2_EVENT:
 540                         /* PTP v2/802.AS1 any layer, any kind of event packet */
 541                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
 542                         ptp_v2 = PTP_TCR_TSVER2ENA;
 543                         /* take time stamp for all event messages */
 544                         snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
 545
 546                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 547                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 548                         ptp_over_ethernet = PTP_TCR_TSIPENA;
 549                         break;
 550
 551                 case HWTSTAMP_FILTER_PTP_V2_SYNC:
 552                         /* PTP v2/802.AS1, any layer, Sync packet */
 553                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_SYNC;
 554                         ptp_v2 = PTP_TCR_TSVER2ENA;
 555                         /* take time stamp for SYNC messages only */
 556                         ts_event_en = PTP_TCR_TSEVNTENA;
 557
 558                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 559                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 560                         ptp_over_ethernet = PTP_TCR_TSIPENA;
 561                         break;
 562
 563                 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
 564                         /* PTP v2/802.AS1, any layer, Delay_req packet */
 565                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_DELAY_REQ;
 566                         ptp_v2 = PTP_TCR_TSVER2ENA;
 567                         /* take time stamp for Delay_Req messages only */
 568                         ts_master_en = PTP_TCR_TSMSTRENA;
 569                         ts_event_en = PTP_TCR_TSEVNTENA;
 570
 571                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 572                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 573                         ptp_over_ethernet = PTP_TCR_TSIPENA;
 574                         break;
 575
 576                 case HWTSTAMP_FILTER_ALL:
 577                         /* time stamp any incoming packet */
 578                         config.rx_filter = HWTSTAMP_FILTER_ALL;
 579                         tstamp_all = PTP_TCR_TSENALL;
 580                         break;
 581
 582                 default:
 583                         return -ERANGE;
 584                 }
 585         } else {
 586                 switch (config.rx_filter) {
 587                 case HWTSTAMP_FILTER_NONE:
 588                         config.rx_filter = HWTSTAMP_FILTER_NONE;
 589                         break;
 590                 default:
 591                         /* PTP v1, UDP, any kind of event packet */
 592                         config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
 593                         break;
 594                 }
 595         }
 596         priv->hwts_rx_en = ((config.rx_filter == HWTSTAMP_FILTER_NONE) ? 0 : 1);
 597         priv->hwts_tx_en = config.tx_type == HWTSTAMP_TX_ON;
 598
 599         if (!priv->hwts_tx_en && !priv->hwts_rx_en)
 600                 priv->hw->ptp->config_hw_tstamping(priv->ptpaddr, 0);
 601         else {
 602                 value = (PTP_TCR_TSENA | PTP_TCR_TSCFUPDT | PTP_TCR_TSCTRLSSR |
 603                          tstamp_all | ptp_v2 | ptp_over_ethernet |
 604                          ptp_over_ipv6_udp | ptp_over_ipv4_udp | ts_event_en |
 605                          ts_master_en | snap_type_sel);
 606                 priv->hw->ptp->config_hw_tstamping(priv->ptpaddr, value);
 607
 608                 /* program Sub Second Increment reg */
 609                 sec_inc = priv->hw->ptp->config_sub_second_increment(
 610                         priv->ptpaddr, priv->plat->clk_ptp_rate,
 611                         priv->plat->has_gmac4);
 612                 temp = div_u64(1000000000ULL, sec_inc);
 613
 614                 /* calculate default added value:
 615                  * formula is :
 616                  * addend = (2^32)/freq_div_ratio;
 617                  * where, freq_div_ratio = 1e9ns/sec_inc
 618                  */
 619                 temp = (u64)(temp << 32);
 620                 priv->default_addend = div_u64(temp, priv->plat->clk_ptp_rate);
 621                 priv->hw->ptp->config_addend(priv->ptpaddr,
 622                                              priv->default_addend);
 623
 624                 /* initialize system time */
 625                 ktime_get_real_ts64(&now);
 626
 627                 /* lower 32 bits of tv_sec are safe until y2106 */
 628                 priv->hw->ptp->init_systime(priv->ptpaddr, (u32)now.tv_sec,
 629                                             now.tv_nsec);
 630         }
 631
 632         return copy_to_user(ifr->ifr_data, &config,
 633                             sizeof(struct hwtstamp_config)) ? -EFAULT : 0;
 634 }
 635
 636 /**
 637  * stmmac_init_ptp - init PTP
 638  * @priv: driver private structure
 639  * Description: this is to verify if the HW supports the PTPv1 or PTPv2.
 640  * This is done by looking at the HW cap. register.
 641  * This function also registers the ptp driver.
 642  */
 643 static int stmmac_init_ptp(struct stmmac_priv *priv)
 644 {
 645         if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp))
 646                 return -EOPNOTSUPP;
 647
 648         priv->adv_ts = 0;
 649         /* Check if adv_ts can be enabled for dwmac 4.x core */
 650         if (priv->plat->has_gmac4 && priv->dma_cap.atime_stamp)
 651                 priv->adv_ts = 1;
 652         /* Dwmac 3.x core with extend_desc can support adv_ts */
 653         else if (priv->extend_desc && priv->dma_cap.atime_stamp)
 654                 priv->adv_ts = 1;
 655
 656         if (priv->dma_cap.time_stamp)
 657                 netdev_info(priv->dev, "IEEE 1588-2002 Timestamp supported\n");
 658
 659         if (priv->adv_ts)
 660                 netdev_info(priv->dev,
 661                             "IEEE 1588-2008 Advanced Timestamp supported\n");
 662
 663         priv->hw->ptp = &stmmac_ptp;
 664         priv->hwts_tx_en = 0;
 665         priv->hwts_rx_en = 0;
 666
 667         stmmac_ptp_register(priv);
 668
 669         return 0;
 670 }
 671
 672 static void stmmac_release_ptp(struct stmmac_priv *priv)
 673 {
 674         if (priv->plat->clk_ptp_ref)
 675                 clk_disable_unprepare(priv->plat->clk_ptp_ref);
 676         stmmac_ptp_unregister(priv);
 677 }
 678
 679 /**
 680  * stmmac_adjust_link - adjusts the link parameters
 681  * @dev: net device structure
 682  * Description: this is the helper called by the physical abstraction layer
 683  * drivers to communicate the phy link status. According the speed and duplex
 684  * this driver can invoke registered glue-logic as well.
 685  * It also invoke the eee initialization because it could happen when switch
 686  * on different networks (that are eee capable).
 687  */
 688 static void stmmac_adjust_link(struct net_device *dev)
 689 {
 690         struct stmmac_priv *priv = netdev_priv(dev);
 691         struct phy_device *phydev = dev->phydev;
 692         unsigned long flags;
 693         int new_state = 0;
 694         unsigned int fc = priv->flow_ctrl, pause_time = priv->pause;
 695
 696         if (phydev == NULL)
 697                 return;
 698
 699         spin_lock_irqsave(&priv->lock, flags);
 700
 701         if (phydev->link) {
 702                 u32 ctrl = readl(priv->ioaddr + MAC_CTRL_REG);
 703
 704                 /* Now we make sure that we can be in full duplex mode.
 705                  * If not, we operate in half-duplex mode. */
 706                 if (phydev->duplex != priv->oldduplex) {
 707                         new_state = 1;
 708                         if (!(phydev->duplex))
 709                                 ctrl &= ~priv->hw->link.duplex;
 710                         else
 711                                 ctrl |= priv->hw->link.duplex;
 712                         priv->oldduplex = phydev->duplex;
 713                 }
 714                 /* Flow Control operation */
 715                 if (phydev->pause)
 716                         priv->hw->mac->flow_ctrl(priv->hw, phydev->duplex,
 717                                                  fc, pause_time);
 718
 719                 if (phydev->speed != priv->speed) {
 720                         new_state = 1;
 721                         switch (phydev->speed) {
 722                         case 1000:
 723                                 if (likely((priv->plat->has_gmac) ||
 724                                            (priv->plat->has_gmac4)))
 725                                         ctrl &= ~priv->hw->link.port;
 726                                 stmmac_hw_fix_mac_speed(priv);
 727                                 break;
 728                         case 100:
 729                         case 10:
 730                                 if (likely((priv->plat->has_gmac) ||
 731                                            (priv->plat->has_gmac4))) {
 732                                         ctrl |= priv->hw->link.port;
 733                                         if (phydev->speed == SPEED_100) {
 734                                                 ctrl |= priv->hw->link.speed;
 735                                         } else {
 736                                                 ctrl &= ~(priv->hw->link.speed);
 737                                         }
 738                                 } else {
 739                                         ctrl &= ~priv->hw->link.port;
 740                                 }
 741                                 stmmac_hw_fix_mac_speed(priv);
 742                                 break;
 743                         default:
 744                                 netif_warn(priv, link, priv->dev,
 745                                            "Speed (%d) not 10/100\n",
 746                                            phydev->speed);
 747                                 break;
 748                         }
 749
 750                         priv->speed = phydev->speed;
 751                 }
 752
 753                 writel(ctrl, priv->ioaddr + MAC_CTRL_REG);
 754
 755                 if (!priv->oldlink) {
 756                         new_state = 1;
 757                         priv->oldlink = 1;
 758                 }
 759         } else if (priv->oldlink) {
 760                 new_state = 1;
 761                 priv->oldlink = 0;
 762                 priv->speed = 0;
 763                 priv->oldduplex = -1;
 764         }
 765
 766         if (new_state && netif_msg_link(priv))
 767                 phy_print_status(phydev);
 768
 769         spin_unlock_irqrestore(&priv->lock, flags);
 770
 771         if (phydev->is_pseudo_fixed_link)
 772                 /* Stop PHY layer to call the hook to adjust the link in case
 773                  * of a switch is attached to the stmmac driver.
 774                  */
 775                 phydev->irq = PHY_IGNORE_INTERRUPT;
 776         else
 777                 /* At this stage, init the EEE if supported.
 778                  * Never called in case of fixed_link.
 779                  */
 780                 priv->eee_enabled = stmmac_eee_init(priv);
 781 }
 782
 783 /**
 784  * stmmac_check_pcs_mode - verify if RGMII/SGMII is supported
 785  * @priv: driver private structure
 786  * Description: this is to verify if the HW supports the PCS.
 787  * Physical Coding Sublayer (PCS) interface that can be used when the MAC is
 788  * configured for the TBI, RTBI, or SGMII PHY interface.
 789  */
 790 static void stmmac_check_pcs_mode(struct stmmac_priv *priv)
 791 {
 792         int interface = priv->plat->interface;
 793
 794         if (priv->dma_cap.pcs) {
 795                 if ((interface == PHY_INTERFACE_MODE_RGMII) ||
 796                     (interface == PHY_INTERFACE_MODE_RGMII_ID) ||
 797                     (interface == PHY_INTERFACE_MODE_RGMII_RXID) ||
 798                     (interface == PHY_INTERFACE_MODE_RGMII_TXID)) {
 799                         netdev_dbg(priv->dev, "PCS RGMII support enabled\n");
 800                         priv->hw->pcs = STMMAC_PCS_RGMII;
 801                 } else if (interface == PHY_INTERFACE_MODE_SGMII) {
 802                         netdev_dbg(priv->dev, "PCS SGMII support enabled\n");
 803                         priv->hw->pcs = STMMAC_PCS_SGMII;
 804                 }
 805         }
 806 }
 807
 808 /**
 809  * stmmac_init_phy - PHY initialization
 810  * @dev: net device structure
 811  * Description: it initializes the driver's PHY state, and attaches the PHY
 812  * to the mac driver.
 813  *  Return value:
 814  *  0 on success
 815  */
 816 static int stmmac_init_phy(struct net_device *dev)
 817 {
 818         struct stmmac_priv *priv = netdev_priv(dev);
 819         struct phy_device *phydev;
 820         char phy_id_fmt[MII_BUS_ID_SIZE + 3];
 821         char bus_id[MII_BUS_ID_SIZE];
 822         int interface = priv->plat->interface;
 823         int max_speed = priv->plat->max_speed;
 824         priv->oldlink = 0;
 825         priv->speed = 0;
 826         priv->oldduplex = -1;
 827
 828         if (priv->plat->phy_node) {
 829                 phydev = of_phy_connect(dev, priv->plat->phy_node,
 830                                         &stmmac_adjust_link, 0, interface);
 831         } else {
 832                 snprintf(bus_id, MII_BUS_ID_SIZE, "stmmac-%x",
 833                          priv->plat->bus_id);
 834
 835                 snprintf(phy_id_fmt, MII_BUS_ID_SIZE + 3, PHY_ID_FMT, bus_id,
 836                          priv->plat->phy_addr);
 837                 netdev_dbg(priv->dev, "%s: trying to attach to %s\n", __func__,
 838                            phy_id_fmt);
 839
 840                 phydev = phy_connect(dev, phy_id_fmt, &stmmac_adjust_link,
 841                                      interface);
 842         }
 843
 844         if (IS_ERR_OR_NULL(phydev)) {
 845                 netdev_err(priv->dev, "Could not attach to PHY\n");
 846                 if (!phydev)
 847                         return -ENODEV;
 848
 849                 return PTR_ERR(phydev);
 850         }
 851
 852         /* Stop Advertising 1000BASE Capability if interface is not GMII */
 853         if ((interface == PHY_INTERFACE_MODE_MII) ||
 854             (interface == PHY_INTERFACE_MODE_RMII) ||
 855                 (max_speed < 1000 && max_speed > 0))
 856                 phydev->advertising &= ~(SUPPORTED_1000baseT_Half |
 857                                          SUPPORTED_1000baseT_Full);
 858
 859         /*
 860          * Broken HW is sometimes missing the pull-up resistor on the
 861          * MDIO line, which results in reads to non-existent devices returning
 862          * 0 rather than 0xffff. Catch this here and treat 0 as a non-existent
 863          * device as well.
 864          * Note: phydev->phy_id is the result of reading the UID PHY registers.
 865          */
 866         if (!priv->plat->phy_node && phydev->phy_id == 0) {
 867                 phy_disconnect(phydev);
 868                 return -ENODEV;
 869         }
 870
 871         /* stmmac_adjust_link will change this to PHY_IGNORE_INTERRUPT to avoid
 872          * subsequent PHY polling, make sure we force a link transition if
 873          * we have a UP/DOWN/UP transition
 874          */
 875         if (phydev->is_pseudo_fixed_link)
 876                 phydev->irq = PHY_POLL;
 877
 878         netdev_dbg(priv->dev, "%s: attached to PHY (UID 0x%x) Link = %d\n",
 879                    __func__, phydev->phy_id, phydev->link);
 880
 881         return 0;
 882 }
 883
 884 static void stmmac_display_rings(struct stmmac_priv *priv)
 885 {
 886         void *head_rx, *head_tx;
 887
 888         if (priv->extend_desc) {
 889                 head_rx = (void *)priv->dma_erx;
 890                 head_tx = (void *)priv->dma_etx;
 891         } else {
 892                 head_rx = (void *)priv->dma_rx;
 893                 head_tx = (void *)priv->dma_tx;
 894         }
 895
 896         /* Display Rx ring */
 897         priv->hw->desc->display_ring(head_rx, DMA_RX_SIZE, true);
 898         /* Display Tx ring */
 899         priv->hw->desc->display_ring(head_tx, DMA_TX_SIZE, false);
 900 }
 901
 902 static int stmmac_set_bfsize(int mtu, int bufsize)
 903 {
 904         int ret = bufsize;
 905
 906         if (mtu >= BUF_SIZE_4KiB)
 907                 ret = BUF_SIZE_8KiB;
 908         else if (mtu >= BUF_SIZE_2KiB)
 909                 ret = BUF_SIZE_4KiB;
 910         else if (mtu > DEFAULT_BUFSIZE)
 911                 ret = BUF_SIZE_2KiB;
 912         else
 913                 ret = DEFAULT_BUFSIZE;
 914
 915         return ret;
 916 }
 917
 918 /**
 919  * stmmac_clear_descriptors - clear descriptors
 920  * @priv: driver private structure
 921  * Description: this function is called to clear the tx and rx descriptors
 922  * in case of both basic and extended descriptors are used.
 923  */
 924 static void stmmac_clear_descriptors(struct stmmac_priv *priv)
 925 {
 926         int i;
 927
 928         /* Clear the Rx/Tx descriptors */
 929         for (i = 0; i < DMA_RX_SIZE; i++)
 930                 if (priv->extend_desc)
 931                         priv->hw->desc->init_rx_desc(&priv->dma_erx[i].basic,
 932                                                      priv->use_riwt, priv->mode,
 933                                                      (i == DMA_RX_SIZE - 1));
 934                 else
 935                         priv->hw->desc->init_rx_desc(&priv->dma_rx[i],
 936                                                      priv->use_riwt, priv->mode,
 937                                                      (i == DMA_RX_SIZE - 1));
 938         for (i = 0; i < DMA_TX_SIZE; i++)
 939                 if (priv->extend_desc)
 940                         priv->hw->desc->init_tx_desc(&priv->dma_etx[i].basic,
 941                                                      priv->mode,
 942                                                      (i == DMA_TX_SIZE - 1));
 943                 else
 944                         priv->hw->desc->init_tx_desc(&priv->dma_tx[i],
 945                                                      priv->mode,
 946                                                      (i == DMA_TX_SIZE - 1));
 947 }
 948
 949 /**
 950  * stmmac_init_rx_buffers - init the RX descriptor buffer.
 951  * @priv: driver private structure
 952  * @p: descriptor pointer
 953  * @i: descriptor index
 954  * @flags: gfp flag.
 955  * Description: this function is called to allocate a receive buffer, perform
 956  * the DMA mapping and init the descriptor.
 957  */
 958 static int stmmac_init_rx_buffers(struct stmmac_priv *priv, struct dma_desc *p,
 959                                   int i, gfp_t flags)
 960 {
 961         struct sk_buff *skb;
 962
 963         skb = __netdev_alloc_skb_ip_align(priv->dev, priv->dma_buf_sz, flags);
 964         if (!skb) {
 965                 netdev_err(priv->dev,
 966                            "%s: Rx init fails; skb is NULL\n", __func__);
 967                 return -ENOMEM;
 968         }
 969         priv->rx_skbuff[i] = skb;
 970         priv->rx_skbuff_dma[i] = dma_map_single(priv->device, skb->data,
 971                                                 priv->dma_buf_sz,
 972                                                 DMA_FROM_DEVICE);
 973         if (dma_mapping_error(priv->device, priv->rx_skbuff_dma[i])) {
 974                 netdev_err(priv->dev, "%s: DMA mapping error\n", __func__);
 975                 dev_kfree_skb_any(skb);
 976                 return -EINVAL;
 977         }
 978
 979         if (priv->synopsys_id >= DWMAC_CORE_4_00)
 980                 p->des0 = cpu_to_le32(priv->rx_skbuff_dma[i]);
 981         else
 982                 p->des2 = cpu_to_le32(priv->rx_skbuff_dma[i]);
 983
 984         if ((priv->hw->mode->init_desc3) &&
 985             (priv->dma_buf_sz == BUF_SIZE_16KiB))
 986                 priv->hw->mode->init_desc3(p);
 987
 988         return 0;
 989 }
 990
 991 static void stmmac_free_rx_buffers(struct stmmac_priv *priv, int i)
 992 {
 993         if (priv->rx_skbuff[i]) {
 994                 dma_unmap_single(priv->device, priv->rx_skbuff_dma[i],
 995                                  priv->dma_buf_sz, DMA_FROM_DEVICE);
 996                 dev_kfree_skb_any(priv->rx_skbuff[i]);
 997         }
 998         priv->rx_skbuff[i] = NULL;
 999 }
1000
1001 /**
1002  * init_dma_desc_rings - init the RX/TX descriptor rings
1003  * @dev: net device structure
1004  * @flags: gfp flag.
1005  * Description: this function initializes the DMA RX/TX descriptors
1006  * and allocates the socket buffers. It suppors the chained and ring
1007  * modes.
1008  */
1009 static int init_dma_desc_rings(struct net_device *dev, gfp_t flags)
1010 {
1011         int i;
1012         struct stmmac_priv *priv = netdev_priv(dev);
1013         unsigned int bfsize = 0;
1014         int ret = -ENOMEM;
1015
1016         if (priv->hw->mode->set_16kib_bfsize)
1017                 bfsize = priv->hw->mode->set_16kib_bfsize(dev->mtu);
1018
1019         if (bfsize < BUF_SIZE_16KiB)
1020                 bfsize = stmmac_set_bfsize(dev->mtu, priv->dma_buf_sz);
1021
1022         priv->dma_buf_sz = bfsize;
1023
1024         netif_dbg(priv, probe, priv->dev,
1025                   "(%s) dma_rx_phy=0x%08x dma_tx_phy=0x%08x\n",
1026                   __func__, (u32)priv->dma_rx_phy, (u32)priv->dma_tx_phy);
1027
1028         /* RX INITIALIZATION */
1029         netif_dbg(priv, probe, priv->dev,
1030                   "SKB addresses:\nskb\t\tskb data\tdma data\n");
1031
1032         for (i = 0; i < DMA_RX_SIZE; i++) {
1033                 struct dma_desc *p;
1034                 if (priv->extend_desc)
1035                         p = &((priv->dma_erx + i)->basic);
1036                 else
1037                         p = priv->dma_rx + i;
1038
1039                 ret = stmmac_init_rx_buffers(priv, p, i, flags);
1040                 if (ret)
1041                         goto err_init_rx_buffers;
1042
1043                 netif_dbg(priv, probe, priv->dev, "[%p]\t[%p]\t[%x]\n",
1044                           priv->rx_skbuff[i], priv->rx_skbuff[i]->data,
1045                           (unsigned int)priv->rx_skbuff_dma[i]);
1046         }
1047         priv->cur_rx = 0;
1048         priv->dirty_rx = (unsigned int)(i - DMA_RX_SIZE);
1049         buf_sz = bfsize;
1050
1051         /* Setup the chained descriptor addresses */
1052         if (priv->mode == STMMAC_CHAIN_MODE) {
1053                 if (priv->extend_desc) {
1054                         priv->hw->mode->init(priv->dma_erx, priv->dma_rx_phy,
1055                                              DMA_RX_SIZE, 1);
1056                         priv->hw->mode->init(priv->dma_etx, priv->dma_tx_phy,
1057                                              DMA_TX_SIZE, 1);
1058                 } else {
1059                         priv->hw->mode->init(priv->dma_rx, priv->dma_rx_phy,
1060                                              DMA_RX_SIZE, 0);
1061                         priv->hw->mode->init(priv->dma_tx, priv->dma_tx_phy,
1062                                              DMA_TX_SIZE, 0);
1063                 }
1064         }
1065
1066         /* TX INITIALIZATION */
1067         for (i = 0; i < DMA_TX_SIZE; i++) {
1068                 struct dma_desc *p;
1069                 if (priv->extend_desc)
1070                         p = &((priv->dma_etx + i)->basic);
1071                 else
1072                         p = priv->dma_tx + i;
1073
1074                 if (priv->synopsys_id >= DWMAC_CORE_4_00) {
1075                         p->des0 = 0;
1076                         p->des1 = 0;
1077                         p->des2 = 0;
1078                         p->des3 = 0;
1079                 } else {
1080                         p->des2 = 0;
1081                 }
1082
1083                 priv->tx_skbuff_dma[i].buf = 0;
1084                 priv->tx_skbuff_dma[i].map_as_page = false;
1085                 priv->tx_skbuff_dma[i].len = 0;
1086                 priv->tx_skbuff_dma[i].last_segment = false;
1087                 priv->tx_skbuff[i] = NULL;
1088         }
1089
1090         priv->dirty_tx = 0;
1091         priv->cur_tx = 0;
1092         netdev_reset_queue(priv->dev);
1093
1094         stmmac_clear_descriptors(priv);
1095
1096         if (netif_msg_hw(priv))
1097                 stmmac_display_rings(priv);
1098
1099         return 0;
1100 err_init_rx_buffers:
1101         while (--i >= 0)
1102                 stmmac_free_rx_buffers(priv, i);
1103         return ret;
1104 }
1105
1106 static void dma_free_rx_skbufs(struct stmmac_priv *priv)
1107 {
1108         int i;
1109
1110         for (i = 0; i < DMA_RX_SIZE; i++)
1111                 stmmac_free_rx_buffers(priv, i);
1112 }
1113
1114 static void dma_free_tx_skbufs(struct stmmac_priv *priv)
1115 {
1116         int i;
1117
1118         for (i = 0; i < DMA_TX_SIZE; i++) {
1119                 struct dma_desc *p;
1120
1121                 if (priv->extend_desc)
1122                         p = &((priv->dma_etx + i)->basic);
1123                 else
1124                         p = priv->dma_tx + i;
1125
1126                 if (priv->tx_skbuff_dma[i].buf) {
1127                         if (priv->tx_skbuff_dma[i].map_as_page)
1128                                 dma_unmap_page(priv->device,
1129                                                priv->tx_skbuff_dma[i].buf,
1130                                                priv->tx_skbuff_dma[i].len,
1131                                                DMA_TO_DEVICE);
1132                         else
1133                                 dma_unmap_single(priv->device,
1134                                                  priv->tx_skbuff_dma[i].buf,
1135                                                  priv->tx_skbuff_dma[i].len,
1136                                                  DMA_TO_DEVICE);
1137                 }
1138
1139                 if (priv->tx_skbuff[i] != NULL) {
1140                         dev_kfree_skb_any(priv->tx_skbuff[i]);
1141                         priv->tx_skbuff[i] = NULL;
1142                         priv->tx_skbuff_dma[i].buf = 0;
1143                         priv->tx_skbuff_dma[i].map_as_page = false;
1144                 }
1145         }
1146 }
1147
1148 /**
1149  * alloc_dma_desc_resources - alloc TX/RX resources.
1150  * @priv: private structure
1151  * Description: according to which descriptor can be used (extend or basic)
1152  * this function allocates the resources for TX and RX paths. In case of
1153  * reception, for example, it pre-allocated the RX socket buffer in order to
1154  * allow zero-copy mechanism.
1155  */
1156 static int alloc_dma_desc_resources(struct stmmac_priv *priv)
1157 {
1158         int ret = -ENOMEM;
1159
1160         priv->rx_skbuff_dma = kmalloc_array(DMA_RX_SIZE, sizeof(dma_addr_t),
1161                                             GFP_KERNEL);
1162         if (!priv->rx_skbuff_dma)
1163                 return -ENOMEM;
1164
1165         priv->rx_skbuff = kmalloc_array(DMA_RX_SIZE, sizeof(struct sk_buff *),
1166                                         GFP_KERNEL);
1167         if (!priv->rx_skbuff)
1168                 goto err_rx_skbuff;
1169
1170         priv->tx_skbuff_dma = kmalloc_array(DMA_TX_SIZE,
1171                                             sizeof(*priv->tx_skbuff_dma),
1172                                             GFP_KERNEL);
1173         if (!priv->tx_skbuff_dma)
1174                 goto err_tx_skbuff_dma;
1175
1176         priv->tx_skbuff = kmalloc_array(DMA_TX_SIZE, sizeof(struct sk_buff *),
1177                                         GFP_KERNEL);
1178         if (!priv->tx_skbuff)
1179                 goto err_tx_skbuff;
1180
1181         if (priv->extend_desc) {
1182                 priv->dma_erx = dma_zalloc_coherent(priv->device, DMA_RX_SIZE *
1183                                                     sizeof(struct
1184                                                            dma_extended_desc),
1185                                                     &priv->dma_rx_phy,
1186                                                     GFP_KERNEL);
1187                 if (!priv->dma_erx)
1188                         goto err_dma;
1189
1190                 priv->dma_etx = dma_zalloc_coherent(priv->device, DMA_TX_SIZE *
1191                                                     sizeof(struct
1192                                                            dma_extended_desc),
1193                                                     &priv->dma_tx_phy,
1194                                                     GFP_KERNEL);
1195                 if (!priv->dma_etx) {
1196                         dma_free_coherent(priv->device, DMA_RX_SIZE *
1197                                           sizeof(struct dma_extended_desc),
1198                                           priv->dma_erx, priv->dma_rx_phy);
1199                         goto err_dma;
1200                 }
1201         } else {
1202                 priv->dma_rx = dma_zalloc_coherent(priv->device, DMA_RX_SIZE *
1203                                                    sizeof(struct dma_desc),
1204                                                    &priv->dma_rx_phy,
1205                                                    GFP_KERNEL);
1206                 if (!priv->dma_rx)
1207                         goto err_dma;
1208
1209                 priv->dma_tx = dma_zalloc_coherent(priv->device, DMA_TX_SIZE *
1210                                                    sizeof(struct dma_desc),
1211                                                    &priv->dma_tx_phy,
1212                                                    GFP_KERNEL);
1213                 if (!priv->dma_tx) {
1214                         dma_free_coherent(priv->device, DMA_RX_SIZE *
1215                                           sizeof(struct dma_desc),
1216                                           priv->dma_rx, priv->dma_rx_phy);
1217                         goto err_dma;
1218                 }
1219         }
1220
1221         return 0;
1222
1223 err_dma:
1224         kfree(priv->tx_skbuff);
1225 err_tx_skbuff:
1226         kfree(priv->tx_skbuff_dma);
1227 err_tx_skbuff_dma:
1228         kfree(priv->rx_skbuff);
1229 err_rx_skbuff:
1230         kfree(priv->rx_skbuff_dma);
1231         return ret;
1232 }
1233
1234 static void free_dma_desc_resources(struct stmmac_priv *priv)
1235 {
1236         /* Release the DMA TX/RX socket buffers */
1237         dma_free_rx_skbufs(priv);
1238         dma_free_tx_skbufs(priv);
1239
1240         /* Free DMA regions of consistent memory previously allocated */
1241         if (!priv->extend_desc) {
1242                 dma_free_coherent(priv->device,
1243                                   DMA_TX_SIZE * sizeof(struct dma_desc),
1244                                   priv->dma_tx, priv->dma_tx_phy);
1245                 dma_free_coherent(priv->device,
1246                                   DMA_RX_SIZE * sizeof(struct dma_desc),
1247                                   priv->dma_rx, priv->dma_rx_phy);
1248         } else {
1249                 dma_free_coherent(priv->device, DMA_TX_SIZE *
1250                                   sizeof(struct dma_extended_desc),
1251                                   priv->dma_etx, priv->dma_tx_phy);
1252                 dma_free_coherent(priv->device, DMA_RX_SIZE *
1253                                   sizeof(struct dma_extended_desc),
1254                                   priv->dma_erx, priv->dma_rx_phy);
1255         }
1256         kfree(priv->rx_skbuff_dma);
1257         kfree(priv->rx_skbuff);
1258         kfree(priv->tx_skbuff_dma);
1259         kfree(priv->tx_skbuff);
1260 }
1261
1262 /**
1263  *  stmmac_mac_enable_rx_queues - Enable MAC rx queues
1264  *  @priv: driver private structure
1265  *  Description: It is used for enabling the rx queues in the MAC
1266  */
1267 static void stmmac_mac_enable_rx_queues(struct stmmac_priv *priv)
1268 {
1269         int rx_count = priv->dma_cap.number_rx_queues;
1270         int queue = 0;
1271
1272         /* If GMAC does not have multiple queues, then this is not necessary*/
1273         if (rx_count == 1)
1274                 return;
1275
1276         /**
1277          *  If the core is synthesized with multiple rx queues / multiple
1278          *  dma channels, then rx queues will be disabled by default.
1279          *  For now only rx queue 0 is enabled.
1280          */
1281         priv->hw->mac->rx_queue_enable(priv->hw, queue);
1282 }
1283
1284 /**
1285  *  stmmac_dma_operation_mode - HW DMA operation mode
1286  *  @priv: driver private structure
1287  *  Description: it is used for configuring the DMA operation mode register in
1288  *  order to program the tx/rx DMA thresholds or Store-And-Forward mode.
1289  */
1290 static void stmmac_dma_operation_mode(struct stmmac_priv *priv)
1291 {
1292         int rxfifosz = priv->plat->rx_fifo_size;
1293
1294         if (priv->plat->force_thresh_dma_mode)
1295                 priv->hw->dma->dma_mode(priv->ioaddr, tc, tc, rxfifosz);
1296         else if (priv->plat->force_sf_dma_mode || priv->plat->tx_coe) {
1297                 /*
1298                  * In case of GMAC, SF mode can be enabled
1299                  * to perform the TX COE in HW. This depends on:
1300                  * 1) TX COE if actually supported
1301                  * 2) There is no bugged Jumbo frame support
1302                  *    that needs to not insert csum in the TDES.
1303                  */
1304                 priv->hw->dma->dma_mode(priv->ioaddr, SF_DMA_MODE, SF_DMA_MODE,
1305                                         rxfifosz);
1306                 priv->xstats.threshold = SF_DMA_MODE;
1307         } else
1308                 priv->hw->dma->dma_mode(priv->ioaddr, tc, SF_DMA_MODE,
1309                                         rxfifosz);
1310 }
1311
1312 /**
1313  * stmmac_tx_clean - to manage the transmission completion
1314  * @priv: driver private structure
1315  * Description: it reclaims the transmit resources after transmission completes.
1316  */
1317 static void stmmac_tx_clean(struct stmmac_priv *priv)
1318 {
1319         unsigned int bytes_compl = 0, pkts_compl = 0;
1320         unsigned int entry = priv->dirty_tx;
1321
1322         netif_tx_lock(priv->dev);
1323
1324         priv->xstats.tx_clean++;
1325
1326         while (entry != priv->cur_tx) {
1327                 struct sk_buff *skb = priv->tx_skbuff[entry];
1328                 struct dma_desc *p;
1329                 int status;
1330
1331                 if (priv->extend_desc)
1332                         p = (struct dma_desc *)(priv->dma_etx + entry);
1333                 else
1334                         p = priv->dma_tx + entry;
1335
1336                 status = priv->hw->desc->tx_status(&priv->dev->stats,
1337                                                       &priv->xstats, p,
1338                                                       priv->ioaddr);
1339                 /* Check if the descriptor is owned by the DMA */
1340                 if (unlikely(status & tx_dma_own))
1341                         break;
1342
1343                 /* Just consider the last segment and ...*/
1344                 if (likely(!(status & tx_not_ls))) {
1345                         /* ... verify the status error condition */
1346                         if (unlikely(status & tx_err)) {
1347                                 priv->dev->stats.tx_errors++;
1348                         } else {
1349                                 priv->dev->stats.tx_packets++;
1350                                 priv->xstats.tx_pkt_n++;
1351                         }
1352                         stmmac_get_tx_hwtstamp(priv, p, skb);
1353                 }
1354
1355                 if (likely(priv->tx_skbuff_dma[entry].buf)) {
1356                         if (priv->tx_skbuff_dma[entry].map_as_page)
1357                                 dma_unmap_page(priv->device,
1358                                                priv->tx_skbuff_dma[entry].buf,
1359                                                priv->tx_skbuff_dma[entry].len,
1360                                                DMA_TO_DEVICE);
1361                         else
1362                                 dma_unmap_single(priv->device,
1363                                                  priv->tx_skbuff_dma[entry].buf,
1364                                                  priv->tx_skbuff_dma[entry].len,
1365                                                  DMA_TO_DEVICE);
1366                         priv->tx_skbuff_dma[entry].buf = 0;
1367                         priv->tx_skbuff_dma[entry].len = 0;
1368                         priv->tx_skbuff_dma[entry].map_as_page = false;
1369                 }
1370
1371                 if (priv->hw->mode->clean_desc3)
1372                         priv->hw->mode->clean_desc3(priv, p);
1373
1374                 priv->tx_skbuff_dma[entry].last_segment = false;
1375                 priv->tx_skbuff_dma[entry].is_jumbo = false;
1376
1377                 if (likely(skb != NULL)) {
1378                         pkts_compl++;
1379                         bytes_compl += skb->len;
1380                         dev_consume_skb_any(skb);
1381                         priv->tx_skbuff[entry] = NULL;
1382                 }
1383
1384                 priv->hw->desc->release_tx_desc(p, priv->mode);
1385
1386                 entry = STMMAC_GET_ENTRY(entry, DMA_TX_SIZE);
1387         }
1388         priv->dirty_tx = entry;
1389
1390         netdev_completed_queue(priv->dev, pkts_compl, bytes_compl);
1391
1392         if (unlikely(netif_queue_stopped(priv->dev) &&
1393             stmmac_tx_avail(priv) > STMMAC_TX_THRESH)) {
1394                 netif_dbg(priv, tx_done, priv->dev,
1395                           "%s: restart transmit\n", __func__);
1396                 netif_wake_queue(priv->dev);
1397         }
1398
1399         if ((priv->eee_enabled) && (!priv->tx_path_in_lpi_mode)) {
1400                 stmmac_enable_eee_mode(priv);
1401                 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer));
1402         }
1403         netif_tx_unlock(priv->dev);
1404 }
1405
1406 static inline void stmmac_enable_dma_irq(struct stmmac_priv *priv)
1407 {
1408         priv->hw->dma->enable_dma_irq(priv->ioaddr);
1409 }
1410
1411 static inline void stmmac_disable_dma_irq(struct stmmac_priv *priv)
1412 {
1413         priv->hw->dma->disable_dma_irq(priv->ioaddr);
1414 }
1415
1416 /**
1417  * stmmac_tx_err - to manage the tx error
1418  * @priv: driver private structure
1419  * Description: it cleans the descriptors and restarts the transmission
1420  * in case of transmission errors.
1421  */
1422 static void stmmac_tx_err(struct stmmac_priv *priv)
1423 {
1424         int i;
1425         netif_stop_queue(priv->dev);
1426
1427         priv->hw->dma->stop_tx(priv->ioaddr);
1428         dma_free_tx_skbufs(priv);
1429         for (i = 0; i < DMA_TX_SIZE; i++)
1430                 if (priv->extend_desc)
1431                         priv->hw->desc->init_tx_desc(&priv->dma_etx[i].basic,
1432                                                      priv->mode,
1433                                                      (i == DMA_TX_SIZE - 1));
1434                 else
1435                         priv->hw->desc->init_tx_desc(&priv->dma_tx[i],
1436                                                      priv->mode,
1437                                                      (i == DMA_TX_SIZE - 1));
1438         priv->dirty_tx = 0;
1439         priv->cur_tx = 0;
1440         netdev_reset_queue(priv->dev);
1441         priv->hw->dma->start_tx(priv->ioaddr);
1442
1443         priv->dev->stats.tx_errors++;
1444         netif_wake_queue(priv->dev);
1445 }
1446
1447 /**
1448  * stmmac_dma_interrupt - DMA ISR
1449  * @priv: driver private structure
1450  * Description: this is the DMA ISR. It is called by the main ISR.
1451  * It calls the dwmac dma routine and schedule poll method in case of some
1452  * work can be done.
1453  */
1454 static void stmmac_dma_interrupt(struct stmmac_priv *priv)
1455 {
1456         int status;
1457         int rxfifosz = priv->plat->rx_fifo_size;
1458
1459         status = priv->hw->dma->dma_interrupt(priv->ioaddr, &priv->xstats);
1460         if (likely((status & handle_rx)) || (status & handle_tx)) {
1461                 if (likely(napi_schedule_prep(&priv->napi))) {
1462                         stmmac_disable_dma_irq(priv);
1463                         __napi_schedule(&priv->napi);
1464                 }
1465         }
1466         if (unlikely(status & tx_hard_error_bump_tc)) {
1467                 /* Try to bump up the dma threshold on this failure */
1468                 if (unlikely(priv->xstats.threshold != SF_DMA_MODE) &&
1469                     (tc <= 256)) {
1470                         tc += 64;
1471                         if (priv->plat->force_thresh_dma_mode)
1472                                 priv->hw->dma->dma_mode(priv->ioaddr, tc, tc,
1473                                                         rxfifosz);
1474                         else
1475                                 priv->hw->dma->dma_mode(priv->ioaddr, tc,
1476                                                         SF_DMA_MODE, rxfifosz);
1477                         priv->xstats.threshold = tc;
1478                 }
1479         } else if (unlikely(status == tx_hard_error))
1480                 stmmac_tx_err(priv);
1481 }
1482
1483 /**
1484  * stmmac_mmc_setup: setup the Mac Management Counters (MMC)
1485  * @priv: driver private structure
1486  * Description: this masks the MMC irq, in fact, the counters are managed in SW.
1487  */
1488 static void stmmac_mmc_setup(struct stmmac_priv *priv)
1489 {
1490         unsigned int mode = MMC_CNTRL_RESET_ON_READ | MMC_CNTRL_COUNTER_RESET |
1491                             MMC_CNTRL_PRESET | MMC_CNTRL_FULL_HALF_PRESET;
1492
1493         if (priv->synopsys_id >= DWMAC_CORE_4_00) {
1494                 priv->ptpaddr = priv->ioaddr + PTP_GMAC4_OFFSET;
1495                 priv->mmcaddr = priv->ioaddr + MMC_GMAC4_OFFSET;
1496         } else {
1497                 priv->ptpaddr = priv->ioaddr + PTP_GMAC3_X_OFFSET;
1498                 priv->mmcaddr = priv->ioaddr + MMC_GMAC3_X_OFFSET;
1499         }
1500
1501         dwmac_mmc_intr_all_mask(priv->mmcaddr);
1502
1503         if (priv->dma_cap.rmon) {
1504                 dwmac_mmc_ctrl(priv->mmcaddr, mode);
1505                 memset(&priv->mmc, 0, sizeof(struct stmmac_counters));
1506         } else
1507                 netdev_info(priv->dev, "No MAC Management Counters available\n");
1508 }
1509
1510 /**
1511  * stmmac_selec_desc_mode - to select among: normal/alternate/extend descriptors
1512  * @priv: driver private structure
1513  * Description: select the Enhanced/Alternate or Normal descriptors.
1514  * In case of Enhanced/Alternate, it checks if the extended descriptors are
1515  * supported by the HW capability register.
1516  */
1517 static void stmmac_selec_desc_mode(struct stmmac_priv *priv)
1518 {
1519         if (priv->plat->enh_desc) {
1520                 dev_info(priv->device, "Enhanced/Alternate descriptors\n");
1521
1522                 /* GMAC older than 3.50 has no extended descriptors */
1523                 if (priv->synopsys_id >= DWMAC_CORE_3_50) {
1524                         dev_info(priv->device, "Enabled extended descriptors\n");
1525                         priv->extend_desc = 1;
1526                 } else
1527                         dev_warn(priv->device, "Extended descriptors not supported\n");
1528
1529                 priv->hw->desc = &enh_desc_ops;
1530         } else {
1531                 dev_info(priv->device, "Normal descriptors\n");
1532                 priv->hw->desc = &ndesc_ops;
1533         }
1534 }
1535
1536 /**
1537  * stmmac_get_hw_features - get MAC capabilities from the HW cap. register.
1538  * @priv: driver private structure
1539  * Description:
1540  *  new GMAC chip generations have a new register to indicate the
1541  *  presence of the optional feature/functions.
1542  *  This can be also used to override the value passed through the
1543  *  platform and necessary for old MAC10/100 and GMAC chips.
1544  */
1545 static int stmmac_get_hw_features(struct stmmac_priv *priv)
1546 {
1547         u32 ret = 0;
1548
1549         if (priv->hw->dma->get_hw_feature) {
1550                 priv->hw->dma->get_hw_feature(priv->ioaddr,
1551                                               &priv->dma_cap);
1552                 ret = 1;
1553         }
1554
1555         return ret;
1556 }
1557
1558 /**
1559  * stmmac_check_ether_addr - check if the MAC addr is valid
1560  * @priv: driver private structure
1561  * Description:
1562  * it is to verify if the MAC address is valid, in case of failures it
1563  * generates a random MAC address
1564  */
1565 static void stmmac_check_ether_addr(struct stmmac_priv *priv)
1566 {
1567         if (!is_valid_ether_addr(priv->dev->dev_addr)) {
1568                 priv->hw->mac->get_umac_addr(priv->hw,
1569                                              priv->dev->dev_addr, 0);
1570                 if (!is_valid_ether_addr(priv->dev->dev_addr))
1571                         eth_hw_addr_random(priv->dev);
1572                 netdev_info(priv->dev, "device MAC address %pM\n",
1573                             priv->dev->dev_addr);
1574         }
1575 }
1576
1577 /**
1578  * stmmac_init_dma_engine - DMA init.
1579  * @priv: driver private structure
1580  * Description:
1581  * It inits the DMA invoking the specific MAC/GMAC callback.
1582  * Some DMA parameters can be passed from the platform;
1583  * in case of these are not passed a default is kept for the MAC or GMAC.
1584  */
1585 static int stmmac_init_dma_engine(struct stmmac_priv *priv)
1586 {
1587         int atds = 0;
1588         int ret = 0;
1589
1590         if (!priv->plat->dma_cfg || !priv->plat->dma_cfg->pbl) {
1591                 dev_err(priv->device, "Invalid DMA configuration\n");
1592                 return -EINVAL;
1593         }
1594
1595         if (priv->extend_desc && (priv->mode == STMMAC_RING_MODE))
1596                 atds = 1;
1597
1598         ret = priv->hw->dma->reset(priv->ioaddr);
1599         if (ret) {
1600                 dev_err(priv->device, "Failed to reset the dma\n");
1601                 return ret;
1602         }
1603
1604         priv->hw->dma->init(priv->ioaddr, priv->plat->dma_cfg,
1605                             priv->dma_tx_phy, priv->dma_rx_phy, atds);
1606
1607         if (priv->synopsys_id >= DWMAC_CORE_4_00) {
1608                 priv->rx_tail_addr = priv->dma_rx_phy +
1609                             (DMA_RX_SIZE * sizeof(struct dma_desc));
1610                 priv->hw->dma->set_rx_tail_ptr(priv->ioaddr, priv->rx_tail_addr,
1611                                                STMMAC_CHAN0);
1612
1613                 priv->tx_tail_addr = priv->dma_tx_phy +
1614                             (DMA_TX_SIZE * sizeof(struct dma_desc));
1615                 priv->hw->dma->set_tx_tail_ptr(priv->ioaddr, priv->tx_tail_addr,
1616                                                STMMAC_CHAN0);
1617         }
1618
1619         if (priv->plat->axi && priv->hw->dma->axi)
1620                 priv->hw->dma->axi(priv->ioaddr, priv->plat->axi);
1621
1622         return ret;
1623 }
1624
1625 /**
1626  * stmmac_tx_timer - mitigation sw timer for tx.
1627  * @data: data pointer
1628  * Description:
1629  * This is the timer handler to directly invoke the stmmac_tx_clean.
1630  */
1631 static void stmmac_tx_timer(unsigned long data)
1632 {
1633         struct stmmac_priv *priv = (struct stmmac_priv *)data;
1634
1635         stmmac_tx_clean(priv);
1636 }
1637
1638 /**
1639  * stmmac_init_tx_coalesce - init tx mitigation options.
1640  * @priv: driver private structure
1641  * Description:
1642  * This inits the transmit coalesce parameters: i.e. timer rate,
1643  * timer handler and default threshold used for enabling the
1644  * interrupt on completion bit.
1645  */
1646 static void stmmac_init_tx_coalesce(struct stmmac_priv *priv)
1647 {
1648         priv->tx_coal_frames = STMMAC_TX_FRAMES;
1649         priv->tx_coal_timer = STMMAC_COAL_TX_TIMER;
1650         init_timer(&priv->txtimer);
1651         priv->txtimer.expires = STMMAC_COAL_TIMER(priv->tx_coal_timer);
1652         priv->txtimer.data = (unsigned long)priv;
1653         priv->txtimer.function = stmmac_tx_timer;
1654         add_timer(&priv->txtimer);
1655 }
1656
1657 /**
1658  * stmmac_hw_setup - setup mac in a usable state.
1659  *  @dev : pointer to the device structure.
1660  *  Description:
1661  *  this is the main function to setup the HW in a usable state because the
1662  *  dma engine is reset, the core registers are configured (e.g. AXI,
1663  *  Checksum features, timers). The DMA is ready to start receiving and
1664  *  transmitting.
1665  *  Return value:
1666  *  0 on success and an appropriate (-)ve integer as defined in errno.h
1667  *  file on failure.
1668  */
1669 static int stmmac_hw_setup(struct net_device *dev, bool init_ptp)
1670 {
1671         struct stmmac_priv *priv = netdev_priv(dev);
1672         int ret;
1673
1674         /* DMA initialization and SW reset */
1675         ret = stmmac_init_dma_engine(priv);
1676         if (ret < 0) {
1677                 netdev_err(priv->dev, "%s: DMA engine initialization failed\n",
1678                            __func__);
1679                 return ret;
1680         }
1681
1682         /* Copy the MAC addr into the HW  */
1683         priv->hw->mac->set_umac_addr(priv->hw, dev->dev_addr, 0);
1684
1685         /* If required, perform hw setup of the bus. */
1686         if (priv->plat->bus_setup)
1687                 priv->plat->bus_setup(priv->ioaddr);
1688
1689         /* PS and related bits will be programmed according to the speed */
1690         if (priv->hw->pcs) {
1691                 int speed = priv->plat->mac_port_sel_speed;
1692
1693                 if ((speed == SPEED_10) || (speed == SPEED_100) ||
1694                     (speed == SPEED_1000)) {
1695                         priv->hw->ps = speed;
1696                 } else {
1697                         dev_warn(priv->device, "invalid port speed\n");
1698                         priv->hw->ps = 0;
1699                 }
1700         }
1701
1702         /* Initialize the MAC Core */
1703         priv->hw->mac->core_init(priv->hw, dev->mtu);
1704
1705         /* Initialize MAC RX Queues */
1706         if (priv->hw->mac->rx_queue_enable)
1707                 stmmac_mac_enable_rx_queues(priv);
1708
1709         ret = priv->hw->mac->rx_ipc(priv->hw);
1710         if (!ret) {
1711                 netdev_warn(priv->dev, "RX IPC Checksum Offload disabled\n");
1712                 priv->plat->rx_coe = STMMAC_RX_COE_NONE;
1713                 priv->hw->rx_csum = 0;
1714         }
1715
1716         /* Enable the MAC Rx/Tx */
1717         if (priv->synopsys_id >= DWMAC_CORE_4_00)
1718                 stmmac_dwmac4_set_mac(priv->ioaddr, true);
1719         else
1720                 stmmac_set_mac(priv->ioaddr, true);
1721
1722         /* Set the HW DMA mode and the COE */
1723         stmmac_dma_operation_mode(priv);
1724
1725         stmmac_mmc_setup(priv);
1726
1727         if (init_ptp) {
1728                 ret = stmmac_init_ptp(priv);
1729                 if (ret)
1730                         netdev_warn(priv->dev, "fail to init PTP.\n");
1731         }
1732
1733 #ifdef CONFIG_DEBUG_FS
1734         ret = stmmac_init_fs(dev);
1735         if (ret < 0)
1736                 netdev_warn(priv->dev, "%s: failed debugFS registration\n",
1737                             __func__);
1738 #endif
1739         /* Start the ball rolling... */
1740         netdev_dbg(priv->dev, "DMA RX/TX processes started...\n");
1741         priv->hw->dma->start_tx(priv->ioaddr);
1742         priv->hw->dma->start_rx(priv->ioaddr);
1743
1744         /* Dump DMA/MAC registers */
1745         if (netif_msg_hw(priv)) {
1746                 priv->hw->mac->dump_regs(priv->hw);
1747                 priv->hw->dma->dump_regs(priv->ioaddr);
1748         }
1749         priv->tx_lpi_timer = STMMAC_DEFAULT_TWT_LS;
1750
1751         if ((priv->use_riwt) && (priv->hw->dma->rx_watchdog)) {
1752                 priv->rx_riwt = MAX_DMA_RIWT;
1753                 priv->hw->dma->rx_watchdog(priv->ioaddr, MAX_DMA_RIWT);
1754         }
1755
1756         if (priv->hw->pcs && priv->hw->mac->pcs_ctrl_ane)
1757                 priv->hw->mac->pcs_ctrl_ane(priv->hw, 1, priv->hw->ps, 0);
1758
1759         /*  set TX ring length */
1760         if (priv->hw->dma->set_tx_ring_len)
1761                 priv->hw->dma->set_tx_ring_len(priv->ioaddr,
1762                                                (DMA_TX_SIZE - 1));
1763         /*  set RX ring length */
1764         if (priv->hw->dma->set_rx_ring_len)
1765                 priv->hw->dma->set_rx_ring_len(priv->ioaddr,
1766                                                (DMA_RX_SIZE - 1));
1767         /* Enable TSO */
1768         if (priv->tso)
1769                 priv->hw->dma->enable_tso(priv->ioaddr, 1, STMMAC_CHAN0);
1770
1771         return 0;
1772 }
1773
1774 /**
1775  *  stmmac_open - open entry point of the driver
1776  *  @dev : pointer to the device structure.
1777  *  Description:
1778  *  This function is the open entry point of the driver.
1779  *  Return value:
1780  *  0 on success and an appropriate (-)ve integer as defined in errno.h
1781  *  file on failure.
1782  */
1783 static int stmmac_open(struct net_device *dev)
1784 {
1785         struct stmmac_priv *priv = netdev_priv(dev);
1786         int ret;
1787
1788         stmmac_check_ether_addr(priv);
1789
1790         if (priv->hw->pcs != STMMAC_PCS_RGMII &&
1791             priv->hw->pcs != STMMAC_PCS_TBI &&
1792             priv->hw->pcs != STMMAC_PCS_RTBI) {
1793                 ret = stmmac_init_phy(dev);
1794                 if (ret) {
1795                         netdev_err(priv->dev,
1796                                    "%s: Cannot attach to PHY (error: %d)\n",
1797                                    __func__, ret);
1798                         return ret;
1799                 }
1800         }
1801
1802         /* Extra statistics */
1803         memset(&priv->xstats, 0, sizeof(struct stmmac_extra_stats));
1804         priv->xstats.threshold = tc;
1805
1806         priv->dma_buf_sz = STMMAC_ALIGN(buf_sz);
1807         priv->rx_copybreak = STMMAC_RX_COPYBREAK;
1808
1809         ret = alloc_dma_desc_resources(priv);
1810         if (ret < 0) {
1811                 netdev_err(priv->dev, "%s: DMA descriptors allocation failed\n",
1812                            __func__);
1813                 goto dma_desc_error;
1814         }
1815
1816         ret = init_dma_desc_rings(dev, GFP_KERNEL);
1817         if (ret < 0) {
1818                 netdev_err(priv->dev, "%s: DMA descriptors initialization failed\n",
1819                            __func__);
1820                 goto init_error;
1821         }
1822
1823         ret = stmmac_hw_setup(dev, true);
1824         if (ret < 0) {
1825                 netdev_err(priv->dev, "%s: Hw setup failed\n", __func__);
1826                 goto init_error;
1827         }
1828
1829         stmmac_init_tx_coalesce(priv);
1830
1831         if (dev->phydev)
1832                 phy_start(dev->phydev);
1833
1834         /* Request the IRQ lines */
1835         ret = request_irq(dev->irq, stmmac_interrupt,
1836                           IRQF_SHARED, dev->name, dev);
1837         if (unlikely(ret < 0)) {
1838                 netdev_err(priv->dev,
1839                            "%s: ERROR: allocating the IRQ %d (error: %d)\n",
1840                            __func__, dev->irq, ret);
1841                 goto init_error;
1842         }
1843
1844         /* Request the Wake IRQ in case of another line is used for WoL */
1845         if (priv->wol_irq != dev->irq) {
1846                 ret = request_irq(priv->wol_irq, stmmac_interrupt,
1847                                   IRQF_SHARED, dev->name, dev);
1848                 if (unlikely(ret < 0)) {
1849                         netdev_err(priv->dev,
1850                                    "%s: ERROR: allocating the WoL IRQ %d (%d)\n",
1851                                    __func__, priv->wol_irq, ret);
1852                         goto wolirq_error;
1853                 }
1854         }
1855
1856         /* Request the IRQ lines */
1857         if (priv->lpi_irq > 0) {
1858                 ret = request_irq(priv->lpi_irq, stmmac_interrupt, IRQF_SHARED,
1859                                   dev->name, dev);
1860                 if (unlikely(ret < 0)) {
1861                         netdev_err(priv->dev,
1862                                    "%s: ERROR: allocating the LPI IRQ %d (%d)\n",
1863                                    __func__, priv->lpi_irq, ret);
1864                         goto lpiirq_error;
1865                 }
1866         }
1867
1868         napi_enable(&priv->napi);
1869         netif_start_queue(dev);
1870
1871         return 0;
1872
1873 lpiirq_error:
1874         if (priv->wol_irq != dev->irq)
1875                 free_irq(priv->wol_irq, dev);
1876 wolirq_error:
1877         free_irq(dev->irq, dev);
1878
1879 init_error:
1880         free_dma_desc_resources(priv);
1881 dma_desc_error:
1882         if (dev->phydev)
1883                 phy_disconnect(dev->phydev);
1884
1885         return ret;
1886 }
1887
1888 /**
1889  *  stmmac_release - close entry point of the driver
1890  *  @dev : device pointer.
1891  *  Description:
1892  *  This is the stop entry point of the driver.
1893  */
1894 static int stmmac_release(struct net_device *dev)
1895 {
1896         struct stmmac_priv *priv = netdev_priv(dev);
1897
1898         if (priv->eee_enabled)
1899                 del_timer_sync(&priv->eee_ctrl_timer);
1900
1901         /* Stop and disconnect the PHY */
1902         if (dev->phydev) {
1903                 phy_stop(dev->phydev);
1904                 phy_disconnect(dev->phydev);
1905         }
1906
1907         netif_stop_queue(dev);
1908
1909         napi_disable(&priv->napi);
1910
1911         del_timer_sync(&priv->txtimer);
1912
1913         /* Free the IRQ lines */
1914         free_irq(dev->irq, dev);
1915         if (priv->wol_irq != dev->irq)
1916                 free_irq(priv->wol_irq, dev);
1917         if (priv->lpi_irq > 0)
1918                 free_irq(priv->lpi_irq, dev);
1919
1920         /* Stop TX/RX DMA and clear the descriptors */
1921         priv->hw->dma->stop_tx(priv->ioaddr);
1922         priv->hw->dma->stop_rx(priv->ioaddr);
1923
1924         /* Release and free the Rx/Tx resources */
1925         free_dma_desc_resources(priv);
1926
1927         /* Disable the MAC Rx/Tx */
1928         stmmac_set_mac(priv->ioaddr, false);
1929
1930         netif_carrier_off(dev);
1931
1932 #ifdef CONFIG_DEBUG_FS
1933         stmmac_exit_fs(dev);
1934 #endif
1935
1936         stmmac_release_ptp(priv);
1937
1938         return 0;
1939 }
1940
1941 /**
1942  *  stmmac_tso_allocator - close entry point of the driver
1943  *  @priv: driver private structure
1944  *  @des: buffer start address
1945  *  @total_len: total length to fill in descriptors
1946  *  @last_segmant: condition for the last descriptor
1947  *  Description:
1948  *  This function fills descriptor and request new descriptors according to
1949  *  buffer length to fill
1950  */
1951 static void stmmac_tso_allocator(struct stmmac_priv *priv, unsigned int des,
1952                                  int total_len, bool last_segment)
1953 {
1954         struct dma_desc *desc;
1955         int tmp_len;
1956         u32 buff_size;
1957
1958         tmp_len = total_len;
1959
1960         while (tmp_len > 0) {
1961                 priv->cur_tx = STMMAC_GET_ENTRY(priv->cur_tx, DMA_TX_SIZE);
1962                 desc = priv->dma_tx + priv->cur_tx;
1963
1964                 desc->des0 = cpu_to_le32(des + (total_len - tmp_len));
1965                 buff_size = tmp_len >= TSO_MAX_BUFF_SIZE ?
1966                             TSO_MAX_BUFF_SIZE : tmp_len;
1967
1968                 priv->hw->desc->prepare_tso_tx_desc(desc, 0, buff_size,
1969                         0, 1,
1970                         (last_segment) && (buff_size < TSO_MAX_BUFF_SIZE),
1971                         0, 0);
1972
1973                 tmp_len -= TSO_MAX_BUFF_SIZE;
1974         }
1975 }
1976
1977 /**
1978  *  stmmac_tso_xmit - Tx entry point of the driver for oversized frames (TSO)
1979  *  @skb : the socket buffer
1980  *  @dev : device pointer
1981  *  Description: this is the transmit function that is called on TSO frames
1982  *  (support available on GMAC4 and newer chips).
1983  *  Diagram below show the ring programming in case of TSO frames:
1984  *
1985  *  First Descriptor
1986  *   --------
1987  *   | DES0 |---> buffer1 = L2/L3/L4 header
1988  *   | DES1 |---> TCP Payload (can continue on next descr...)
1989  *   | DES2 |---> buffer 1 and 2 len
1990  *   | DES3 |---> must set TSE, TCP hdr len-> [22:19]. TCP payload len [17:0]
1991  *   --------
1992  *      |
1993  *     ...
1994  *      |
1995  *   --------
1996  *   | DES0 | --| Split TCP Payload on Buffers 1 and 2
1997  *   | DES1 | --|
1998  *   | DES2 | --> buffer 1 and 2 len
1999  *   | DES3 |
2000  *   --------
2001  *
2002  * mss is fixed when enable tso, so w/o programming the TDES3 ctx field.
2003  */
2004 static netdev_tx_t stmmac_tso_xmit(struct sk_buff *skb, struct net_device *dev)
2005 {
2006         u32 pay_len, mss;
2007         int tmp_pay_len = 0;
2008         struct stmmac_priv *priv = netdev_priv(dev);
2009         int nfrags = skb_shinfo(skb)->nr_frags;
2010         unsigned int first_entry, des;
2011         struct dma_desc *desc, *first, *mss_desc = NULL;
2012         u8 proto_hdr_len;
2013         int i;
2014
2015         /* Compute header lengths */
2016         proto_hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
2017
2018         /* Desc availability based on threshold should be enough safe */
2019         if (unlikely(stmmac_tx_avail(priv) <
2020                 (((skb->len - proto_hdr_len) / TSO_MAX_BUFF_SIZE + 1)))) {
2021                 if (!netif_queue_stopped(dev)) {
2022                         netif_stop_queue(dev);
2023                         /* This is a hard error, log it. */
2024                         netdev_err(priv->dev,
2025                                    "%s: Tx Ring full when queue awake\n",
2026                                    __func__);
2027                 }
2028                 return NETDEV_TX_BUSY;
2029         }
2030
2031         pay_len = skb_headlen(skb) - proto_hdr_len; /* no frags */
2032
2033         mss = skb_shinfo(skb)->gso_size;
2034
2035         /* set new MSS value if needed */
2036         if (mss != priv->mss) {
2037                 mss_desc = priv->dma_tx + priv->cur_tx;
2038                 priv->hw->desc->set_mss(mss_desc, mss);
2039                 priv->mss = mss;
2040                 priv->cur_tx = STMMAC_GET_ENTRY(priv->cur_tx, DMA_TX_SIZE);
2041         }
2042
2043         if (netif_msg_tx_queued(priv)) {
2044                 pr_info("%s: tcphdrlen %d, hdr_len %d, pay_len %d, mss %d\n",
2045                         __func__, tcp_hdrlen(skb), proto_hdr_len, pay_len, mss);
2046                 pr_info("\tskb->len %d, skb->data_len %d\n", skb->len,
2047                         skb->data_len);
2048         }
2049
2050         first_entry = priv->cur_tx;
2051
2052         desc = priv->dma_tx + first_entry;
2053         first = desc;
2054
2055         /* first descriptor: fill Headers on Buf1 */
2056         des = dma_map_single(priv->device, skb->data, skb_headlen(skb),
2057                              DMA_TO_DEVICE);
2058         if (dma_mapping_error(priv->device, des))
2059                 goto dma_map_err;
2060
2061         priv->tx_skbuff_dma[first_entry].buf = des;
2062         priv->tx_skbuff_dma[first_entry].len = skb_headlen(skb);
2063         priv->tx_skbuff[first_entry] = skb;
2064
2065         first->des0 = cpu_to_le32(des);
2066
2067         /* Fill start of payload in buff2 of first descriptor */
2068         if (pay_len)
2069                 first->des1 = cpu_to_le32(des + proto_hdr_len);
2070
2071         /* If needed take extra descriptors to fill the remaining payload */
2072         tmp_pay_len = pay_len - TSO_MAX_BUFF_SIZE;
2073
2074         stmmac_tso_allocator(priv, des, tmp_pay_len, (nfrags == 0));
2075
2076         /* Prepare fragments */
2077         for (i = 0; i < nfrags; i++) {
2078                 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2079
2080                 des = skb_frag_dma_map(priv->device, frag, 0,
2081                                        skb_frag_size(frag),
2082                                        DMA_TO_DEVICE);
2083
2084                 stmmac_tso_allocator(priv, des, skb_frag_size(frag),
2085                                      (i == nfrags - 1));
2086
2087                 priv->tx_skbuff_dma[priv->cur_tx].buf = des;
2088                 priv->tx_skbuff_dma[priv->cur_tx].len = skb_frag_size(frag);
2089                 priv->tx_skbuff[priv->cur_tx] = NULL;
2090                 priv->tx_skbuff_dma[priv->cur_tx].map_as_page = true;
2091         }
2092
2093         priv->tx_skbuff_dma[priv->cur_tx].last_segment = true;
2094
2095         priv->cur_tx = STMMAC_GET_ENTRY(priv->cur_tx, DMA_TX_SIZE);
2096
2097         if (unlikely(stmmac_tx_avail(priv) <= (MAX_SKB_FRAGS + 1))) {
2098                 netif_dbg(priv, hw, priv->dev, "%s: stop transmitted packets\n",
2099                           __func__);
2100                 netif_stop_queue(dev);
2101         }
2102
2103         dev->stats.tx_bytes += skb->len;
2104         priv->xstats.tx_tso_frames++;
2105         priv->xstats.tx_tso_nfrags += nfrags;
2106
2107         /* Manage tx mitigation */
2108         priv->tx_count_frames += nfrags + 1;
2109         if (likely(priv->tx_coal_frames > priv->tx_count_frames)) {
2110                 mod_timer(&priv->txtimer,
2111                           STMMAC_COAL_TIMER(priv->tx_coal_timer));
2112         } else {
2113                 priv->tx_count_frames = 0;
2114                 priv->hw->desc->set_tx_ic(desc);
2115                 priv->xstats.tx_set_ic_bit++;
2116         }
2117
2118         if (!priv->hwts_tx_en)
2119                 skb_tx_timestamp(skb);
2120
2121         if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
2122                      priv->hwts_tx_en)) {
2123                 /* declare that device is doing timestamping */
2124                 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
2125                 priv->hw->desc->enable_tx_timestamp(first);
2126         }
2127
2128         /* Complete the first descriptor before granting the DMA */
2129         priv->hw->desc->prepare_tso_tx_desc(first, 1,
2130                         proto_hdr_len,
2131                         pay_len,
2132                         1, priv->tx_skbuff_dma[first_entry].last_segment,
2133                         tcp_hdrlen(skb) / 4, (skb->len - proto_hdr_len));
2134
2135         /* If context desc is used to change MSS */
2136         if (mss_desc)
2137                 priv->hw->desc->set_tx_owner(mss_desc);
2138
2139         /* The own bit must be the latest setting done when prepare the
2140          * descriptor and then barrier is needed to make sure that
2141          * all is coherent before granting the DMA engine.
2142          */
2143         dma_wmb();
2144
2145         if (netif_msg_pktdata(priv)) {
2146                 pr_info("%s: curr=%d dirty=%d f=%d, e=%d, f_p=%p, nfrags %d\n",
2147                         __func__, priv->cur_tx, priv->dirty_tx, first_entry,
2148                         priv->cur_tx, first, nfrags);
2149
2150                 priv->hw->desc->display_ring((void *)priv->dma_tx, DMA_TX_SIZE,
2151                                              0);
2152
2153                 pr_info(">>> frame to be transmitted: ");
2154                 print_pkt(skb->data, skb_headlen(skb));
2155         }
2156
2157         netdev_sent_queue(dev, skb->len);
2158
2159         priv->hw->dma->set_tx_tail_ptr(priv->ioaddr, priv->tx_tail_addr,
2160                                        STMMAC_CHAN0);
2161
2162         return NETDEV_TX_OK;
2163
2164 dma_map_err:
2165         dev_err(priv->device, "Tx dma map failed\n");
2166         dev_kfree_skb(skb);
2167         priv->dev->stats.tx_dropped++;
2168         return NETDEV_TX_OK;
2169 }
2170
2171 /**
2172  *  stmmac_xmit - Tx entry point of the driver
2173  *  @skb : the socket buffer
2174  *  @dev : device pointer
2175  *  Description : this is the tx entry point of the driver.
2176  *  It programs the chain or the ring and supports oversized frames
2177  *  and SG feature.
2178  */
2179 static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev)
2180 {
2181         struct stmmac_priv *priv = netdev_priv(dev);
2182         unsigned int nopaged_len = skb_headlen(skb);
2183         int i, csum_insertion = 0, is_jumbo = 0;
2184         int nfrags = skb_shinfo(skb)->nr_frags;
2185         unsigned int entry, first_entry;
2186         struct dma_desc *desc, *first;
2187         unsigned int enh_desc;
2188         unsigned int des;
2189
2190         /* Manage oversized TCP frames for GMAC4 device */
2191         if (skb_is_gso(skb) && priv->tso) {
2192                 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
2193                         return stmmac_tso_xmit(skb, dev);
2194         }
2195
2196         if (unlikely(stmmac_tx_avail(priv) < nfrags + 1)) {
2197                 if (!netif_queue_stopped(dev)) {
2198                         netif_stop_queue(dev);
2199                         /* This is a hard error, log it. */
2200                         netdev_err(priv->dev,
2201                                    "%s: Tx Ring full when queue awake\n",
2202                                    __func__);
2203                 }
2204                 return NETDEV_TX_BUSY;
2205         }
2206
2207         if (priv->tx_path_in_lpi_mode)
2208                 stmmac_disable_eee_mode(priv);
2209
2210         entry = priv->cur_tx;
2211         first_entry = entry;
2212
2213         csum_insertion = (skb->ip_summed == CHECKSUM_PARTIAL);
2214
2215         if (likely(priv->extend_desc))
2216                 desc = (struct dma_desc *)(priv->dma_etx + entry);
2217         else
2218                 desc = priv->dma_tx + entry;
2219
2220         first = desc;
2221
2222         priv->tx_skbuff[first_entry] = skb;
2223
2224         enh_desc = priv->plat->enh_desc;
2225         /* To program the descriptors according to the size of the frame */
2226         if (enh_desc)
2227                 is_jumbo = priv->hw->mode->is_jumbo_frm(skb->len, enh_desc);
2228
2229         if (unlikely(is_jumbo) && likely(priv->synopsys_id <
2230                                          DWMAC_CORE_4_00)) {
2231                 entry = priv->hw->mode->jumbo_frm(priv, skb, csum_insertion);
2232                 if (unlikely(entry < 0))
2233                         goto dma_map_err;
2234         }
2235
2236         for (i = 0; i < nfrags; i++) {
2237                 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2238                 int len = skb_frag_size(frag);
2239                 bool last_segment = (i == (nfrags - 1));
2240
2241                 entry = STMMAC_GET_ENTRY(entry, DMA_TX_SIZE);
2242
2243                 if (likely(priv->extend_desc))
2244                         desc = (struct dma_desc *)(priv->dma_etx + entry);
2245                 else
2246                         desc = priv->dma_tx + entry;
2247
2248                 des = skb_frag_dma_map(priv->device, frag, 0, len,
2249                                        DMA_TO_DEVICE);
2250                 if (dma_mapping_error(priv->device, des))
2251                         goto dma_map_err; /* should reuse desc w/o issues */
2252
2253                 priv->tx_skbuff[entry] = NULL;
2254
2255                 priv->tx_skbuff_dma[entry].buf = des;
2256                 if (unlikely(priv->synopsys_id >= DWMAC_CORE_4_00))
2257                         desc->des0 = cpu_to_le32(des);
2258                 else
2259                         desc->des2 = cpu_to_le32(des);
2260
2261                 priv->tx_skbuff_dma[entry].map_as_page = true;
2262                 priv->tx_skbuff_dma[entry].len = len;
2263                 priv->tx_skbuff_dma[entry].last_segment = last_segment;
2264
2265                 /* Prepare the descriptor and set the own bit too */
2266                 priv->hw->desc->prepare_tx_desc(desc, 0, len, csum_insertion,
2267                                                 priv->mode, 1, last_segment);
2268         }
2269
2270         entry = STMMAC_GET_ENTRY(entry, DMA_TX_SIZE);
2271
2272         priv->cur_tx = entry;
2273
2274         if (netif_msg_pktdata(priv)) {
2275                 void *tx_head;
2276
2277                 netdev_dbg(priv->dev,
2278                            "%s: curr=%d dirty=%d f=%d, e=%d, first=%p, nfrags=%d",
2279                            __func__, priv->cur_tx, priv->dirty_tx, first_entry,
2280                            entry, first, nfrags);
2281
2282                 if (priv->extend_desc)
2283                         tx_head = (void *)priv->dma_etx;
2284                 else
2285                         tx_head = (void *)priv->dma_tx;
2286
2287                 priv->hw->desc->display_ring(tx_head, DMA_TX_SIZE, false);
2288
2289                 netdev_dbg(priv->dev, ">>> frame to be transmitted: ");
2290                 print_pkt(skb->data, skb->len);
2291         }
2292
2293         if (unlikely(stmmac_tx_avail(priv) <= (MAX_SKB_FRAGS + 1))) {
2294                 netif_dbg(priv, hw, priv->dev, "%s: stop transmitted packets\n",
2295                           __func__);
2296                 netif_stop_queue(dev);
2297         }
2298
2299         dev->stats.tx_bytes += skb->len;
2300
2301         /* According to the coalesce parameter the IC bit for the latest
2302          * segment is reset and the timer re-started to clean the tx status.
2303          * This approach takes care about the fragments: desc is the first
2304          * element in case of no SG.
2305          */
2306         priv->tx_count_frames += nfrags + 1;
2307         if (likely(priv->tx_coal_frames > priv->tx_count_frames)) {
2308                 mod_timer(&priv->txtimer,
2309                           STMMAC_COAL_TIMER(priv->tx_coal_timer));
2310         } else {
2311                 priv->tx_count_frames = 0;
2312                 priv->hw->desc->set_tx_ic(desc);
2313                 priv->xstats.tx_set_ic_bit++;
2314         }
2315
2316         if (!priv->hwts_tx_en)
2317                 skb_tx_timestamp(skb);
2318
2319         /* Ready to fill the first descriptor and set the OWN bit w/o any
2320          * problems because all the descriptors are actually ready to be
2321          * passed to the DMA engine.
2322          */
2323         if (likely(!is_jumbo)) {
2324                 bool last_segment = (nfrags == 0);
2325
2326                 des = dma_map_single(priv->device, skb->data,
2327                                      nopaged_len, DMA_TO_DEVICE);
2328                 if (dma_mapping_error(priv->device, des))
2329                         goto dma_map_err;
2330
2331                 priv->tx_skbuff_dma[first_entry].buf = des;
2332                 if (unlikely(priv->synopsys_id >= DWMAC_CORE_4_00))
2333                         first->des0 = cpu_to_le32(des);
2334                 else
2335                         first->des2 = cpu_to_le32(des);
2336
2337                 priv->tx_skbuff_dma[first_entry].len = nopaged_len;
2338                 priv->tx_skbuff_dma[first_entry].last_segment = last_segment;
2339
2340                 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
2341                              priv->hwts_tx_en)) {
2342                         /* declare that device is doing timestamping */
2343                         skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
2344                         priv->hw->desc->enable_tx_timestamp(first);
2345                 }
2346
2347                 /* Prepare the first descriptor setting the OWN bit too */
2348                 priv->hw->desc->prepare_tx_desc(first, 1, nopaged_len,
2349                                                 csum_insertion, priv->mode, 1,
2350                                                 last_segment);
2351
2352                 /* The own bit must be the latest setting done when prepare the
2353                  * descriptor and then barrier is needed to make sure that
2354                  * all is coherent before granting the DMA engine.
2355                  */
2356                 dma_wmb();
2357         }
2358
2359         netdev_sent_queue(dev, skb->len);
2360
2361         if (priv->synopsys_id < DWMAC_CORE_4_00)
2362                 priv->hw->dma->enable_dma_transmission(priv->ioaddr);
2363         else
2364                 priv->hw->dma->set_tx_tail_ptr(priv->ioaddr, priv->tx_tail_addr,
2365                                                STMMAC_CHAN0);
2366
2367         return NETDEV_TX_OK;
2368
2369 dma_map_err:
2370         netdev_err(priv->dev, "Tx DMA map failed\n");
2371         dev_kfree_skb(skb);
2372         priv->dev->stats.tx_dropped++;
2373         return NETDEV_TX_OK;
2374 }
2375
2376 static void stmmac_rx_vlan(struct net_device *dev, struct sk_buff *skb)
2377 {
2378         struct ethhdr *ehdr;
2379         u16 vlanid;
2380
2381         if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) ==
2382             NETIF_F_HW_VLAN_CTAG_RX &&
2383             !__vlan_get_tag(skb, &vlanid)) {
2384                 /* pop the vlan tag */
2385                 ehdr = (struct ethhdr *)skb->data;
2386                 memmove(skb->data + VLAN_HLEN, ehdr, ETH_ALEN * 2);
2387                 skb_pull(skb, VLAN_HLEN);
2388                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlanid);
2389         }
2390 }
2391
2392
2393 static inline int stmmac_rx_threshold_count(struct stmmac_priv *priv)
2394 {
2395         if (priv->rx_zeroc_thresh < STMMAC_RX_THRESH)
2396                 return 0;
2397
2398         return 1;
2399 }
2400
2401 /**
2402  * stmmac_rx_refill - refill used skb preallocated buffers
2403  * @priv: driver private structure
2404  * Description : this is to reallocate the skb for the reception process
2405  * that is based on zero-copy.
2406  */
2407 static inline void stmmac_rx_refill(struct stmmac_priv *priv)
2408 {
2409         int bfsize = priv->dma_buf_sz;
2410         unsigned int entry = priv->dirty_rx;
2411         int dirty = stmmac_rx_dirty(priv);
2412
2413         while (dirty-- > 0) {
2414                 struct dma_desc *p;
2415
2416                 if (priv->extend_desc)
2417                         p = (struct dma_desc *)(priv->dma_erx + entry);
2418                 else
2419                         p = priv->dma_rx + entry;
2420
2421                 if (likely(priv->rx_skbuff[entry] == NULL)) {
2422                         struct sk_buff *skb;
2423
2424                         skb = netdev_alloc_skb_ip_align(priv->dev, bfsize);
2425                         if (unlikely(!skb)) {
2426                                 /* so for a while no zero-copy! */
2427                                 priv->rx_zeroc_thresh = STMMAC_RX_THRESH;
2428                                 if (unlikely(net_ratelimit()))
2429                                         dev_err(priv->device,
2430                                                 "fail to alloc skb entry %d\n",
2431                                                 entry);
2432                                 break;
2433                         }
2434
2435                         priv->rx_skbuff[entry] = skb;
2436                         priv->rx_skbuff_dma[entry] =
2437                             dma_map_single(priv->device, skb->data, bfsize,
2438                                            DMA_FROM_DEVICE);
2439                         if (dma_mapping_error(priv->device,
2440                                               priv->rx_skbuff_dma[entry])) {
2441                                 netdev_err(priv->dev, "Rx DMA map failed\n");
2442                                 dev_kfree_skb(skb);
2443                                 break;
2444                         }
2445
2446                         if (unlikely(priv->synopsys_id >= DWMAC_CORE_4_00)) {
2447                                 p->des0 = cpu_to_le32(priv->rx_skbuff_dma[entry]);
2448                                 p->des1 = 0;
2449                         } else {
2450                                 p->des2 = cpu_to_le32(priv->rx_skbuff_dma[entry]);
2451                         }
2452                         if (priv->hw->mode->refill_desc3)
2453                                 priv->hw->mode->refill_desc3(priv, p);
2454
2455                         if (priv->rx_zeroc_thresh > 0)
2456                                 priv->rx_zeroc_thresh--;
2457
2458                         netif_dbg(priv, rx_status, priv->dev,
2459                                   "refill entry #%d\n", entry);
2460                 }
2461                 dma_wmb();
2462
2463                 if (unlikely(priv->synopsys_id >= DWMAC_CORE_4_00))
2464                         priv->hw->desc->init_rx_desc(p, priv->use_riwt, 0, 0);
2465                 else
2466                         priv->hw->desc->set_rx_owner(p);
2467
2468                 dma_wmb();
2469
2470                 entry = STMMAC_GET_ENTRY(entry, DMA_RX_SIZE);
2471         }
2472         priv->dirty_rx = entry;
2473 }
2474
2475 /**
2476  * stmmac_rx - manage the receive process
2477  * @priv: driver private structure
2478  * @limit: napi bugget.
2479  * Description :  this the function called by the napi poll method.
2480  * It gets all the frames inside the ring.
2481  */
2482 static int stmmac_rx(struct stmmac_priv *priv, int limit)
2483 {
2484         unsigned int entry = priv->cur_rx;
2485         unsigned int next_entry;
2486         unsigned int count = 0;
2487         int coe = priv->hw->rx_csum;
2488
2489         if (netif_msg_rx_status(priv)) {
2490                 void *rx_head;
2491
2492                 netdev_dbg(priv->dev, "%s: descriptor ring:\n", __func__);
2493                 if (priv->extend_desc)
2494                         rx_head = (void *)priv->dma_erx;
2495                 else
2496                         rx_head = (void *)priv->dma_rx;
2497
2498                 priv->hw->desc->display_ring(rx_head, DMA_RX_SIZE, true);
2499         }
2500         while (count < limit) {
2501                 int status;
2502                 struct dma_desc *p;
2503                 struct dma_desc *np;
2504
2505                 if (priv->extend_desc)
2506                         p = (struct dma_desc *)(priv->dma_erx + entry);
2507                 else
2508                         p = priv->dma_rx + entry;
2509
2510                 /* read the status of the incoming frame */
2511                 status = priv->hw->desc->rx_status(&priv->dev->stats,
2512                                                    &priv->xstats, p);
2513                 /* check if managed by the DMA otherwise go ahead */
2514                 if (unlikely(status & dma_own))
2515                         break;
2516
2517                 count++;
2518
2519                 priv->cur_rx = STMMAC_GET_ENTRY(priv->cur_rx, DMA_RX_SIZE);
2520                 next_entry = priv->cur_rx;
2521
2522                 if (priv->extend_desc)
2523                         np = (struct dma_desc *)(priv->dma_erx + next_entry);
2524                 else
2525                         np = priv->dma_rx + next_entry;
2526
2527                 prefetch(np);
2528
2529                 if ((priv->extend_desc) && (priv->hw->desc->rx_extended_status))
2530                         priv->hw->desc->rx_extended_status(&priv->dev->stats,
2531                                                            &priv->xstats,
2532                                                            priv->dma_erx +
2533                                                            entry);
2534                 if (unlikely(status == discard_frame)) {
2535                         priv->dev->stats.rx_errors++;
2536                         if (priv->hwts_rx_en && !priv->extend_desc) {
2537                                 /* DESC2 & DESC3 will be overwitten by device
2538                                  * with timestamp value, hence reinitialize
2539                                  * them in stmmac_rx_refill() function so that
2540                                  * device can reuse it.
2541                                  */
2542                                 priv->rx_skbuff[entry] = NULL;
2543                                 dma_unmap_single(priv->device,
2544                                                  priv->rx_skbuff_dma[entry],
2545                                                  priv->dma_buf_sz,
2546                                                  DMA_FROM_DEVICE);
2547                         }
2548                 } else {
2549                         struct sk_buff *skb;
2550                         int frame_len;
2551                         unsigned int des;
2552
2553                         if (unlikely(priv->synopsys_id >= DWMAC_CORE_4_00))
2554                                 des = le32_to_cpu(p->des0);
2555                         else
2556                                 des = le32_to_cpu(p->des2);
2557
2558                         frame_len = priv->hw->desc->get_rx_frame_len(p, coe);
2559
2560                         /*  If frame length is greather than skb buffer size
2561                          *  (preallocated during init) then the packet is
2562                          *  ignored
2563                          */
2564                         if (frame_len > priv->dma_buf_sz) {
2565                                 netdev_err(priv->dev,
2566                                            "len %d larger than size (%d)\n",
2567                                            frame_len, priv->dma_buf_sz);
2568                                 priv->dev->stats.rx_length_errors++;
2569                                 break;
2570                         }
2571
2572                         /* ACS is set; GMAC core strips PAD/FCS for IEEE 802.3
2573                          * Type frames (LLC/LLC-SNAP)
2574                          */
2575                         if (unlikely(status != llc_snap))
2576                                 frame_len -= ETH_FCS_LEN;
2577
2578                         if (netif_msg_rx_status(priv)) {
2579                                 netdev_dbg(priv->dev, "\tdesc: %p [entry %d] buff=0x%x\n",
2580                                            p, entry, des);
2581                                 if (frame_len > ETH_FRAME_LEN)
2582                                         netdev_dbg(priv->dev, "frame size %d, COE: %d\n",
2583                                                    frame_len, status);
2584                         }
2585
2586                         /* The zero-copy is always used for all the sizes
2587                          * in case of GMAC4 because it needs
2588                          * to refill the used descriptors, always.
2589                          */
2590                         if (unlikely(!priv->plat->has_gmac4 &&
2591                                      ((frame_len < priv->rx_copybreak) ||
2592                                      stmmac_rx_threshold_count(priv)))) {
2593                                 skb = netdev_alloc_skb_ip_align(priv->dev,
2594                                                                 frame_len);
2595                                 if (unlikely(!skb)) {
2596                                         if (net_ratelimit())
2597                                                 dev_warn(priv->device,
2598                                                          "packet dropped\n");
2599                                         priv->dev->stats.rx_dropped++;
2600                                         break;
2601                                 }
2602
2603                                 dma_sync_single_for_cpu(priv->device,
2604                                                         priv->rx_skbuff_dma
2605                                                         [entry], frame_len,
2606                                                         DMA_FROM_DEVICE);
2607                                 skb_copy_to_linear_data(skb,
2608                                                         priv->
2609                                                         rx_skbuff[entry]->data,
2610                                                         frame_len);
2611
2612                                 skb_put(skb, frame_len);
2613                                 dma_sync_single_for_device(priv->device,
2614                                                            priv->rx_skbuff_dma
2615                                                            [entry], frame_len,
2616                                                            DMA_FROM_DEVICE);
2617                         } else {
2618                                 skb = priv->rx_skbuff[entry];
2619                                 if (unlikely(!skb)) {
2620                                         netdev_err(priv->dev,
2621                                                    "%s: Inconsistent Rx chain\n",
2622                                                    priv->dev->name);
2623                                         priv->dev->stats.rx_dropped++;
2624                                         break;
2625                                 }
2626                                 prefetch(skb->data - NET_IP_ALIGN);
2627                                 priv->rx_skbuff[entry] = NULL;
2628                                 priv->rx_zeroc_thresh++;
2629
2630                                 skb_put(skb, frame_len);
2631                                 dma_unmap_single(priv->device,
2632                                                  priv->rx_skbuff_dma[entry],
2633                                                  priv->dma_buf_sz,
2634                                                  DMA_FROM_DEVICE);
2635                         }
2636
2637                         if (netif_msg_pktdata(priv)) {
2638                                 netdev_dbg(priv->dev, "frame received (%dbytes)",
2639                                            frame_len);
2640                                 print_pkt(skb->data, frame_len);
2641                         }
2642
2643                         stmmac_get_rx_hwtstamp(priv, p, np, skb);
2644
2645                         stmmac_rx_vlan(priv->dev, skb);
2646
2647                         skb->protocol = eth_type_trans(skb, priv->dev);
2648
2649                         if (unlikely(!coe))
2650                                 skb_checksum_none_assert(skb);
2651                         else
2652                                 skb->ip_summed = CHECKSUM_UNNECESSARY;
2653
2654                         napi_gro_receive(&priv->napi, skb);
2655
2656                         priv->dev->stats.rx_packets++;
2657                         priv->dev->stats.rx_bytes += frame_len;
2658                 }
2659                 entry = next_entry;
2660         }
2661
2662         stmmac_rx_refill(priv);
2663
2664         priv->xstats.rx_pkt_n += count;
2665
2666         return count;
2667 }
2668
2669 /**
2670  *  stmmac_poll - stmmac poll method (NAPI)
2671  *  @napi : pointer to the napi structure.
2672  *  @budget : maximum number of packets that the current CPU can receive from
2673  *            all interfaces.
2674  *  Description :
2675  *  To look at the incoming frames and clear the tx resources.
2676  */
2677 static int stmmac_poll(struct napi_struct *napi, int budget)
2678 {
2679         struct stmmac_priv *priv = container_of(napi, struct stmmac_priv, napi);
2680         int work_done = 0;
2681
2682         priv->xstats.napi_poll++;
2683         stmmac_tx_clean(priv);
2684
2685         work_done = stmmac_rx(priv, budget);
2686         if (work_done < budget) {
2687                 napi_complete(napi);
2688                 stmmac_enable_dma_irq(priv);
2689         }
2690         return work_done;
2691 }
2692
2693 /**
2694  *  stmmac_tx_timeout
2695  *  @dev : Pointer to net device structure
2696  *  Description: this function is called when a packet transmission fails to
2697  *   complete within a reasonable time. The driver will mark the error in the
2698  *   netdev structure and arrange for the device to be reset to a sane state
2699  *   in order to transmit a new packet.
2700  */
2701 static void stmmac_tx_timeout(struct net_device *dev)
2702 {
2703         struct stmmac_priv *priv = netdev_priv(dev);
2704
2705         /* Clear Tx resources and restart transmitting again */
2706         stmmac_tx_err(priv);
2707 }
2708
2709 /**
2710  *  stmmac_set_rx_mode - entry point for multicast addressing
2711  *  @dev : pointer to the device structure
2712  *  Description:
2713  *  This function is a driver entry point which gets called by the kernel
2714  *  whenever multicast addresses must be enabled/disabled.
2715  *  Return value:
2716  *  void.
2717  */
2718 static void stmmac_set_rx_mode(struct net_device *dev)
2719 {
2720         struct stmmac_priv *priv = netdev_priv(dev);
2721
2722         priv->hw->mac->set_filter(priv->hw, dev);
2723 }
2724
2725 /**
2726  *  stmmac_change_mtu - entry point to change MTU size for the device.
2727  *  @dev : device pointer.
2728  *  @new_mtu : the new MTU size for the device.
2729  *  Description: the Maximum Transfer Unit (MTU) is used by the network layer
2730  *  to drive packet transmission. Ethernet has an MTU of 1500 octets
2731  *  (ETH_DATA_LEN). This value can be changed with ifconfig.
2732  *  Return value:
2733  *  0 on success and an appropriate (-)ve integer as defined in errno.h
2734  *  file on failure.
2735  */
2736 static int stmmac_change_mtu(struct net_device *dev, int new_mtu)
2737 {
2738         struct stmmac_priv *priv = netdev_priv(dev);
2739
2740         if (netif_running(dev)) {
2741                 netdev_err(priv->dev, "must be stopped to change its MTU\n");
2742                 return -EBUSY;
2743         }
2744
2745         dev->mtu = new_mtu;
2746
2747         netdev_update_features(dev);
2748
2749         return 0;
2750 }
2751
2752 static netdev_features_t stmmac_fix_features(struct net_device *dev,
2753                                              netdev_features_t features)
2754 {
2755         struct stmmac_priv *priv = netdev_priv(dev);
2756
2757         if (priv->plat->rx_coe == STMMAC_RX_COE_NONE)
2758                 features &= ~NETIF_F_RXCSUM;
2759
2760         if (!priv->plat->tx_coe)
2761                 features &= ~NETIF_F_CSUM_MASK;
2762
2763         /* Some GMAC devices have a bugged Jumbo frame support that
2764          * needs to have the Tx COE disabled for oversized frames
2765          * (due to limited buffer sizes). In this case we disable
2766          * the TX csum insertionin the TDES and not use SF.
2767          */
2768         if (priv->plat->bugged_jumbo && (dev->mtu > ETH_DATA_LEN))
2769                 features &= ~NETIF_F_CSUM_MASK;
2770
2771         /* Disable tso if asked by ethtool */
2772         if ((priv->plat->tso_en) && (priv->dma_cap.tsoen)) {
2773                 if (features & NETIF_F_TSO)
2774                         priv->tso = true;
2775                 else
2776                         priv->tso = false;
2777         }
2778
2779         return features;
2780 }
2781
2782 static int stmmac_set_features(struct net_device *netdev,
2783                                netdev_features_t features)
2784 {
2785         struct stmmac_priv *priv = netdev_priv(netdev);
2786
2787         /* Keep the COE Type in case of csum is supporting */
2788         if (features & NETIF_F_RXCSUM)
2789                 priv->hw->rx_csum = priv->plat->rx_coe;
2790         else
2791                 priv->hw->rx_csum = 0;
2792         /* No check needed because rx_coe has been set before and it will be
2793          * fixed in case of issue.
2794          */
2795         priv->hw->mac->rx_ipc(priv->hw);
2796
2797         return 0;
2798 }
2799
2800 /**
2801  *  stmmac_interrupt - main ISR
2802  *  @irq: interrupt number.
2803  *  @dev_id: to pass the net device pointer.
2804  *  Description: this is the main driver interrupt service routine.
2805  *  It can call:
2806  *  o DMA service routine (to manage incoming frame reception and transmission
2807  *    status)
2808  *  o Core interrupts to manage: remote wake-up, management counter, LPI
2809  *    interrupts.
2810  */
2811 static irqreturn_t stmmac_interrupt(int irq, void *dev_id)
2812 {
2813         struct net_device *dev = (struct net_device *)dev_id;
2814         struct stmmac_priv *priv = netdev_priv(dev);
2815
2816         if (priv->irq_wake)
2817                 pm_wakeup_event(priv->device, 0);
2818
2819         if (unlikely(!dev)) {
2820                 netdev_err(priv->dev, "%s: invalid dev pointer\n", __func__);
2821                 return IRQ_NONE;
2822         }
2823
2824         /* To handle GMAC own interrupts */
2825         if ((priv->plat->has_gmac) || (priv->plat->has_gmac4)) {
2826                 int status = priv->hw->mac->host_irq_status(priv->hw,
2827                                                             &priv->xstats);
2828                 if (unlikely(status)) {
2829                         /* For LPI we need to save the tx status */
2830                         if (status & CORE_IRQ_TX_PATH_IN_LPI_MODE)
2831                                 priv->tx_path_in_lpi_mode = true;
2832                         if (status & CORE_IRQ_TX_PATH_EXIT_LPI_MODE)
2833                                 priv->tx_path_in_lpi_mode = false;
2834                         if (status & CORE_IRQ_MTL_RX_OVERFLOW && priv->hw->dma->set_rx_tail_ptr)
2835                                 priv->hw->dma->set_rx_tail_ptr(priv->ioaddr,
2836                                                         priv->rx_tail_addr,
2837                                                         STMMAC_CHAN0);
2838                 }
2839
2840                 /* PCS link status */
2841                 if (priv->hw->pcs) {
2842                         if (priv->xstats.pcs_link)
2843                                 netif_carrier_on(dev);
2844                         else
2845                                 netif_carrier_off(dev);
2846                 }
2847         }
2848
2849         /* To handle DMA interrupts */
2850         stmmac_dma_interrupt(priv);
2851
2852         return IRQ_HANDLED;
2853 }
2854
2855 #ifdef CONFIG_NET_POLL_CONTROLLER
2856 /* Polling receive - used by NETCONSOLE and other diagnostic tools
2857  * to allow network I/O with interrupts disabled.
2858  */
2859 static void stmmac_poll_controller(struct net_device *dev)
2860 {
2861         disable_irq(dev->irq);
2862         stmmac_interrupt(dev->irq, dev);
2863         enable_irq(dev->irq);
2864 }
2865 #endif
2866
2867 /**
2868  *  stmmac_ioctl - Entry point for the Ioctl
2869  *  @dev: Device pointer.
2870  *  @rq: An IOCTL specefic structure, that can contain a pointer to
2871  *  a proprietary structure used to pass information to the driver.
2872  *  @cmd: IOCTL command
2873  *  Description:
2874  *  Currently it supports the phy_mii_ioctl(...) and HW time stamping.
2875  */
2876 static int stmmac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2877 {
2878         int ret = -EOPNOTSUPP;
2879
2880         if (!netif_running(dev))
2881                 return -EINVAL;
2882
2883         switch (cmd) {
2884         case SIOCGMIIPHY:
2885         case SIOCGMIIREG:
2886         case SIOCSMIIREG:
2887                 if (!dev->phydev)
2888                         return -EINVAL;
2889                 ret = phy_mii_ioctl(dev->phydev, rq, cmd);
2890                 break;
2891         case SIOCSHWTSTAMP:
2892                 ret = stmmac_hwtstamp_ioctl(dev, rq);
2893                 break;
2894         default:
2895                 break;
2896         }
2897
2898         return ret;
2899 }
2900
2901 #ifdef CONFIG_DEBUG_FS
2902 static struct dentry *stmmac_fs_dir;
2903
2904 static void sysfs_display_ring(void *head, int size, int extend_desc,
2905                                struct seq_file *seq)
2906 {
2907         int i;
2908         struct dma_extended_desc *ep = (struct dma_extended_desc *)head;
2909         struct dma_desc *p = (struct dma_desc *)head;
2910
2911         for (i = 0; i < size; i++) {
2912                 u64 x;
2913                 if (extend_desc) {
2914                         x = *(u64 *) ep;
2915                         seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
2916                                    i, (unsigned int)virt_to_phys(ep),
2917                                    le32_to_cpu(ep->basic.des0),
2918                                    le32_to_cpu(ep->basic.des1),
2919                                    le32_to_cpu(ep->basic.des2),
2920                                    le32_to_cpu(ep->basic.des3));
2921                         ep++;
2922                 } else {
2923                         x = *(u64 *) p;
2924                         seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
2925                                    i, (unsigned int)virt_to_phys(ep),
2926                                    le32_to_cpu(p->des0), le32_to_cpu(p->des1),
2927                                    le32_to_cpu(p->des2), le32_to_cpu(p->des3));
2928                         p++;
2929                 }
2930                 seq_printf(seq, "\n");
2931         }
2932 }
2933
2934 static int stmmac_sysfs_ring_read(struct seq_file *seq, void *v)
2935 {
2936         struct net_device *dev = seq->private;
2937         struct stmmac_priv *priv = netdev_priv(dev);
2938
2939         if (priv->extend_desc) {
2940                 seq_printf(seq, "Extended RX descriptor ring:\n");
2941                 sysfs_display_ring((void *)priv->dma_erx, DMA_RX_SIZE, 1, seq);
2942                 seq_printf(seq, "Extended TX descriptor ring:\n");
2943                 sysfs_display_ring((void *)priv->dma_etx, DMA_TX_SIZE, 1, seq);
2944         } else {
2945                 seq_printf(seq, "RX descriptor ring:\n");
2946                 sysfs_display_ring((void *)priv->dma_rx, DMA_RX_SIZE, 0, seq);
2947                 seq_printf(seq, "TX descriptor ring:\n");
2948                 sysfs_display_ring((void *)priv->dma_tx, DMA_TX_SIZE, 0, seq);
2949         }
2950
2951         return 0;
2952 }
2953
2954 static int stmmac_sysfs_ring_open(struct inode *inode, struct file *file)
2955 {
2956         return single_open(file, stmmac_sysfs_ring_read, inode->i_private);
2957 }
2958
2959 /* Debugfs files, should appear in /sys/kernel/debug/stmmaceth/eth0 */
2960
2961 static const struct file_operations stmmac_rings_status_fops = {
2962         .owner = THIS_MODULE,
2963         .open = stmmac_sysfs_ring_open,
2964         .read = seq_read,
2965         .llseek = seq_lseek,
2966         .release = single_release,
2967 };
2968
2969 static int stmmac_sysfs_dma_cap_read(struct seq_file *seq, void *v)
2970 {
2971         struct net_device *dev = seq->private;
2972         struct stmmac_priv *priv = netdev_priv(dev);
2973
2974         if (!priv->hw_cap_support) {
2975                 seq_printf(seq, "DMA HW features not supported\n");
2976                 return 0;
2977         }
2978
2979         seq_printf(seq, "==============================\n");
2980         seq_printf(seq, "\tDMA HW features\n");
2981         seq_printf(seq, "==============================\n");
2982
2983         seq_printf(seq, "\t10/100 Mbps: %s\n",
2984                    (priv->dma_cap.mbps_10_100) ? "Y" : "N");
2985         seq_printf(seq, "\t1000 Mbps: %s\n",
2986                    (priv->dma_cap.mbps_1000) ? "Y" : "N");
2987         seq_printf(seq, "\tHalf duplex: %s\n",
2988                    (priv->dma_cap.half_duplex) ? "Y" : "N");
2989         seq_printf(seq, "\tHash Filter: %s\n",
2990                    (priv->dma_cap.hash_filter) ? "Y" : "N");
2991         seq_printf(seq, "\tMultiple MAC address registers: %s\n",
2992                    (priv->dma_cap.multi_addr) ? "Y" : "N");
2993         seq_printf(seq, "\tPCS (TBI/SGMII/RTBI PHY interfatces): %s\n",
2994                    (priv->dma_cap.pcs) ? "Y" : "N");
2995         seq_printf(seq, "\tSMA (MDIO) Interface: %s\n",
2996                    (priv->dma_cap.sma_mdio) ? "Y" : "N");
2997         seq_printf(seq, "\tPMT Remote wake up: %s\n",
2998                    (priv->dma_cap.pmt_remote_wake_up) ? "Y" : "N");
2999         seq_printf(seq, "\tPMT Magic Frame: %s\n",
3000                    (priv->dma_cap.pmt_magic_frame) ? "Y" : "N");
3001         seq_printf(seq, "\tRMON module: %s\n",
3002                    (priv->dma_cap.rmon) ? "Y" : "N");
3003         seq_printf(seq, "\tIEEE 1588-2002 Time Stamp: %s\n",
3004                    (priv->dma_cap.time_stamp) ? "Y" : "N");
3005         seq_printf(seq, "\tIEEE 1588-2008 Advanced Time Stamp: %s\n",
3006                    (priv->dma_cap.atime_stamp) ? "Y" : "N");
3007         seq_printf(seq, "\t802.3az - Energy-Efficient Ethernet (EEE): %s\n",
3008                    (priv->dma_cap.eee) ? "Y" : "N");
3009         seq_printf(seq, "\tAV features: %s\n", (priv->dma_cap.av) ? "Y" : "N");
3010         seq_printf(seq, "\tChecksum Offload in TX: %s\n",
3011                    (priv->dma_cap.tx_coe) ? "Y" : "N");
3012         if (priv->synopsys_id >= DWMAC_CORE_4_00) {
3013                 seq_printf(seq, "\tIP Checksum Offload in RX: %s\n",
3014                            (priv->dma_cap.rx_coe) ? "Y" : "N");
3015         } else {
3016                 seq_printf(seq, "\tIP Checksum Offload (type1) in RX: %s\n",
3017                            (priv->dma_cap.rx_coe_type1) ? "Y" : "N");
3018                 seq_printf(seq, "\tIP Checksum Offload (type2) in RX: %s\n",
3019                            (priv->dma_cap.rx_coe_type2) ? "Y" : "N");
3020         }
3021         seq_printf(seq, "\tRXFIFO > 2048bytes: %s\n",
3022                    (priv->dma_cap.rxfifo_over_2048) ? "Y" : "N");
3023         seq_printf(seq, "\tNumber of Additional RX channel: %d\n",
3024                    priv->dma_cap.number_rx_channel);
3025         seq_printf(seq, "\tNumber of Additional TX channel: %d\n",
3026                    priv->dma_cap.number_tx_channel);
3027         seq_printf(seq, "\tEnhanced descriptors: %s\n",
3028                    (priv->dma_cap.enh_desc) ? "Y" : "N");
3029
3030         return 0;
3031 }
3032
3033 static int stmmac_sysfs_dma_cap_open(struct inode *inode, struct file *file)
3034 {
3035         return single_open(file, stmmac_sysfs_dma_cap_read, inode->i_private);
3036 }
3037
3038 static const struct file_operations stmmac_dma_cap_fops = {
3039         .owner = THIS_MODULE,
3040         .open = stmmac_sysfs_dma_cap_open,
3041         .read = seq_read,
3042         .llseek = seq_lseek,
3043         .release = single_release,
3044 };
3045
3046 static int stmmac_init_fs(struct net_device *dev)
3047 {
3048         struct stmmac_priv *priv = netdev_priv(dev);
3049
3050         /* Create per netdev entries */
3051         priv->dbgfs_dir = debugfs_create_dir(dev->name, stmmac_fs_dir);
3052
3053         if (!priv->dbgfs_dir || IS_ERR(priv->dbgfs_dir)) {
3054                 netdev_err(priv->dev, "ERROR failed to create debugfs directory\n");
3055
3056                 return -ENOMEM;
3057         }
3058
3059         /* Entry to report DMA RX/TX rings */
3060         priv->dbgfs_rings_status =
3061                 debugfs_create_file("descriptors_status", S_IRUGO,
3062                                     priv->dbgfs_dir, dev,
3063                                     &stmmac_rings_status_fops);
3064
3065         if (!priv->dbgfs_rings_status || IS_ERR(priv->dbgfs_rings_status)) {
3066                 netdev_err(priv->dev, "ERROR creating stmmac ring debugfs file\n");
3067                 debugfs_remove_recursive(priv->dbgfs_dir);
3068
3069                 return -ENOMEM;
3070         }
3071
3072         /* Entry to report the DMA HW features */
3073         priv->dbgfs_dma_cap = debugfs_create_file("dma_cap", S_IRUGO,
3074                                             priv->dbgfs_dir,
3075                                             dev, &stmmac_dma_cap_fops);
3076
3077         if (!priv->dbgfs_dma_cap || IS_ERR(priv->dbgfs_dma_cap)) {
3078                 netdev_err(priv->dev, "ERROR creating stmmac MMC debugfs file\n");
3079                 debugfs_remove_recursive(priv->dbgfs_dir);
3080
3081                 return -ENOMEM;
3082         }
3083
3084         return 0;
3085 }
3086
3087 static void stmmac_exit_fs(struct net_device *dev)
3088 {
3089         struct stmmac_priv *priv = netdev_priv(dev);
3090
3091         debugfs_remove_recursive(priv->dbgfs_dir);
3092 }
3093 #endif /* CONFIG_DEBUG_FS */
3094
3095 static const struct net_device_ops stmmac_netdev_ops = {
3096         .ndo_open = stmmac_open,
3097         .ndo_start_xmit = stmmac_xmit,
3098         .ndo_stop = stmmac_release,
3099         .ndo_change_mtu = stmmac_change_mtu,
3100         .ndo_fix_features = stmmac_fix_features,
3101         .ndo_set_features = stmmac_set_features,
3102         .ndo_set_rx_mode = stmmac_set_rx_mode,
3103         .ndo_tx_timeout = stmmac_tx_timeout,
3104         .ndo_do_ioctl = stmmac_ioctl,
3105 #ifdef CONFIG_NET_POLL_CONTROLLER
3106         .ndo_poll_controller = stmmac_poll_controller,
3107 #endif
3108         .ndo_set_mac_address = eth_mac_addr,
3109 };
3110
3111 /**
3112  *  stmmac_hw_init - Init the MAC device
3113  *  @priv: driver private structure
3114  *  Description: this function is to configure the MAC device according to
3115  *  some platform parameters or the HW capability register. It prepares the
3116  *  driver to use either ring or chain modes and to setup either enhanced or
3117  *  normal descriptors.
3118  */
3119 static int stmmac_hw_init(struct stmmac_priv *priv)
3120 {
3121         struct mac_device_info *mac;
3122
3123         /* Identify the MAC HW device */
3124         if (priv->plat->has_gmac) {
3125                 priv->dev->priv_flags |= IFF_UNICAST_FLT;
3126                 mac = dwmac1000_setup(priv->ioaddr,
3127                                       priv->plat->multicast_filter_bins,
3128                                       priv->plat->unicast_filter_entries,
3129                                       &priv->synopsys_id);
3130         } else if (priv->plat->has_gmac4) {
3131                 priv->dev->priv_flags |= IFF_UNICAST_FLT;
3132                 mac = dwmac4_setup(priv->ioaddr,
3133                                    priv->plat->multicast_filter_bins,
3134                                    priv->plat->unicast_filter_entries,
3135                                    &priv->synopsys_id);
3136         } else {
3137                 mac = dwmac100_setup(priv->ioaddr, &priv->synopsys_id);
3138         }
3139         if (!mac)
3140                 return -ENOMEM;
3141
3142         priv->hw = mac;
3143
3144         /* To use the chained or ring mode */
3145         if (priv->synopsys_id >= DWMAC_CORE_4_00) {
3146                 priv->hw->mode = &dwmac4_ring_mode_ops;
3147         } else {
3148                 if (chain_mode) {
3149                         priv->hw->mode = &chain_mode_ops;
3150                         dev_info(priv->device, "Chain mode enabled\n");
3151                         priv->mode = STMMAC_CHAIN_MODE;
3152                 } else {
3153                         priv->hw->mode = &ring_mode_ops;
3154                         dev_info(priv->device, "Ring mode enabled\n");
3155                         priv->mode = STMMAC_RING_MODE;
3156                 }
3157         }
3158
3159         /* Get the HW capability (new GMAC newer than 3.50a) */
3160         priv->hw_cap_support = stmmac_get_hw_features(priv);
3161         if (priv->hw_cap_support) {
3162                 dev_info(priv->device, "DMA HW capability register supported\n");
3163
3164                 /* We can override some gmac/dma configuration fields: e.g.
3165                  * enh_desc, tx_coe (e.g. that are passed through the
3166                  * platform) with the values from the HW capability
3167                  * register (if supported).
3168                  */
3169                 priv->plat->enh_desc = priv->dma_cap.enh_desc;
3170                 priv->plat->pmt = priv->dma_cap.pmt_remote_wake_up;
3171                 priv->hw->pmt = priv->plat->pmt;
3172
3173                 /* TXCOE doesn't work in thresh DMA mode */
3174                 if (priv->plat->force_thresh_dma_mode)
3175                         priv->plat->tx_coe = 0;
3176                 else
3177                         priv->plat->tx_coe = priv->dma_cap.tx_coe;
3178
3179                 /* In case of GMAC4 rx_coe is from HW cap register. */
3180                 priv->plat->rx_coe = priv->dma_cap.rx_coe;
3181
3182                 if (priv->dma_cap.rx_coe_type2)
3183                         priv->plat->rx_coe = STMMAC_RX_COE_TYPE2;
3184                 else if (priv->dma_cap.rx_coe_type1)
3185                         priv->plat->rx_coe = STMMAC_RX_COE_TYPE1;
3186
3187         } else {
3188                 dev_info(priv->device, "No HW DMA feature register supported\n");
3189         }
3190
3191         /* To use alternate (extended), normal or GMAC4 descriptor structures */
3192         if (priv->synopsys_id >= DWMAC_CORE_4_00)
3193                 priv->hw->desc = &dwmac4_desc_ops;
3194         else
3195                 stmmac_selec_desc_mode(priv);
3196
3197         if (priv->plat->rx_coe) {
3198                 priv->hw->rx_csum = priv->plat->rx_coe;
3199                 dev_info(priv->device, "RX Checksum Offload Engine supported\n");
3200                 if (priv->synopsys_id < DWMAC_CORE_4_00)
3201                         dev_info(priv->device, "COE Type %d\n", priv->hw->rx_csum);
3202         }
3203         if (priv->plat->tx_coe)
3204                 dev_info(priv->device, "TX Checksum insertion supported\n");
3205
3206         if (priv->plat->pmt) {
3207                 dev_info(priv->device, "Wake-Up On Lan supported\n");
3208                 device_set_wakeup_capable(priv->device, 1);
3209         }
3210
3211         if (priv->dma_cap.tsoen)
3212                 dev_info(priv->device, "TSO supported\n");
3213
3214         return 0;
3215 }
3216
3217 /**
3218  * stmmac_dvr_probe
3219  * @device: device pointer
3220  * @plat_dat: platform data pointer
3221  * @res: stmmac resource pointer
3222  * Description: this is the main probe function used to
3223  * call the alloc_etherdev, allocate the priv structure.
3224  * Return:
3225  * returns 0 on success, otherwise errno.
3226  */
3227 int stmmac_dvr_probe(struct device *device,
3228                      struct plat_stmmacenet_data *plat_dat,
3229                      struct stmmac_resources *res)
3230 {
3231         int ret = 0;
3232         struct net_device *ndev = NULL;
3233         struct stmmac_priv *priv;
3234
3235         ndev = alloc_etherdev(sizeof(struct stmmac_priv));
3236         if (!ndev)
3237                 return -ENOMEM;
3238
3239         SET_NETDEV_DEV(ndev, device);
3240
3241         priv = netdev_priv(ndev);
3242         priv->device = device;
3243         priv->dev = ndev;
3244
3245         stmmac_set_ethtool_ops(ndev);
3246         priv->pause = pause;
3247         priv->plat = plat_dat;
3248         priv->ioaddr = res->addr;
3249         priv->dev->base_addr = (unsigned long)res->addr;
3250
3251         priv->dev->irq = res->irq;
3252         priv->wol_irq = res->wol_irq;
3253         priv->lpi_irq = res->lpi_irq;
3254
3255         if (res->mac)
3256                 memcpy(priv->dev->dev_addr, res->mac, ETH_ALEN);
3257
3258         dev_set_drvdata(device, priv->dev);
3259
3260         /* Verify driver arguments */
3261         stmmac_verify_args();
3262
3263         /* Override with kernel parameters if supplied XXX CRS XXX
3264          * this needs to have multiple instances
3265          */
3266         if ((phyaddr >= 0) && (phyaddr <= 31))
3267                 priv->plat->phy_addr = phyaddr;
3268
3269         if (priv->plat->stmmac_rst)
3270                 reset_control_deassert(priv->plat->stmmac_rst);
3271
3272         /* Init MAC and get the capabilities */
3273         ret = stmmac_hw_init(priv);
3274         if (ret)
3275                 goto error_hw_init;
3276
3277         ndev->netdev_ops = &stmmac_netdev_ops;
3278
3279         ndev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
3280                             NETIF_F_RXCSUM;
3281
3282         if ((priv->plat->tso_en) && (priv->dma_cap.tsoen)) {
3283                 ndev->hw_features |= NETIF_F_TSO;
3284                 priv->tso = true;
3285                 dev_info(priv->device, "TSO feature enabled\n");
3286         }
3287         ndev->features |= ndev->hw_features | NETIF_F_HIGHDMA;
3288         ndev->watchdog_timeo = msecs_to_jiffies(watchdog);
3289 #ifdef STMMAC_VLAN_TAG_USED
3290         /* Both mac100 and gmac support receive VLAN tag detection */
3291         ndev->features |= NETIF_F_HW_VLAN_CTAG_RX;
3292 #endif
3293         priv->msg_enable = netif_msg_init(debug, default_msg_level);
3294
3295         /* MTU range: 46 - hw-specific max */
3296         ndev->min_mtu = ETH_ZLEN - ETH_HLEN;
3297         if ((priv->plat->enh_desc) || (priv->synopsys_id >= DWMAC_CORE_4_00))
3298                 ndev->max_mtu = JUMBO_LEN;
3299         else
3300                 ndev->max_mtu = SKB_MAX_HEAD(NET_SKB_PAD + NET_IP_ALIGN);
3301         /* Will not overwrite ndev->max_mtu if plat->maxmtu > ndev->max_mtu
3302          * as well as plat->maxmtu < ndev->min_mtu which is a invalid range.
3303          */
3304         if ((priv->plat->maxmtu < ndev->max_mtu) &&
3305             (priv->plat->maxmtu >= ndev->min_mtu))
3306                 ndev->max_mtu = priv->plat->maxmtu;
3307         else if (priv->plat->maxmtu < ndev->min_mtu)
3308                 dev_warn(priv->device,
3309                          "%s: warning: maxmtu having invalid value (%d)\n",
3310                          __func__, priv->plat->maxmtu);
3311
3312         if (flow_ctrl)
3313                 priv->flow_ctrl = FLOW_AUTO;    /* RX/TX pause on */
3314
3315         /* Rx Watchdog is available in the COREs newer than the 3.40.
3316          * In some case, for example on bugged HW this feature
3317          * has to be disable and this can be done by passing the
3318          * riwt_off field from the platform.
3319          */
3320         if ((priv->synopsys_id >= DWMAC_CORE_3_50) && (!priv->plat->riwt_off)) {
3321                 priv->use_riwt = 1;
3322                 dev_info(priv->device,
3323                          "Enable RX Mitigation via HW Watchdog Timer\n");
3324         }
3325
3326         netif_napi_add(ndev, &priv->napi, stmmac_poll, 64);
3327
3328         spin_lock_init(&priv->lock);
3329
3330         /* If a specific clk_csr value is passed from the platform
3331          * this means that the CSR Clock Range selection cannot be
3332          * changed at run-time and it is fixed. Viceversa the driver'll try to
3333          * set the MDC clock dynamically according to the csr actual
3334          * clock input.
3335          */
3336         if (!priv->plat->clk_csr)
3337                 stmmac_clk_csr_set(priv);
3338         else
3339                 priv->clk_csr = priv->plat->clk_csr;
3340
3341         stmmac_check_pcs_mode(priv);
3342
3343         if (priv->hw->pcs != STMMAC_PCS_RGMII  &&
3344             priv->hw->pcs != STMMAC_PCS_TBI &&
3345             priv->hw->pcs != STMMAC_PCS_RTBI) {
3346                 /* MDIO bus Registration */
3347                 ret = stmmac_mdio_register(ndev);
3348                 if (ret < 0) {
3349                         dev_err(priv->device,
3350                                 "%s: MDIO bus (id: %d) registration failed",
3351                                 __func__, priv->plat->bus_id);
3352                         goto error_mdio_register;
3353                 }
3354         }
3355
3356         ret = register_netdev(ndev);
3357         if (ret) {
3358                 dev_err(priv->device, "%s: ERROR %i registering the device\n",
3359                         __func__, ret);
3360                 goto error_netdev_register;
3361         }
3362
3363         return ret;
3364
3365 error_netdev_register:
3366         if (priv->hw->pcs != STMMAC_PCS_RGMII &&
3367             priv->hw->pcs != STMMAC_PCS_TBI &&
3368             priv->hw->pcs != STMMAC_PCS_RTBI)
3369                 stmmac_mdio_unregister(ndev);
3370 error_mdio_register:
3371         netif_napi_del(&priv->napi);
3372 error_hw_init:
3373         free_netdev(ndev);
3374
3375         return ret;
3376 }
3377 EXPORT_SYMBOL_GPL(stmmac_dvr_probe);
3378
3379 /**
3380  * stmmac_dvr_remove
3381  * @dev: device pointer
3382  * Description: this function resets the TX/RX processes, disables the MAC RX/TX
3383  * changes the link status, releases the DMA descriptor rings.
3384  */
3385 int stmmac_dvr_remove(struct device *dev)
3386 {
3387         struct net_device *ndev = dev_get_drvdata(dev);
3388         struct stmmac_priv *priv = netdev_priv(ndev);
3389
3390         netdev_info(priv->dev, "%s: removing driver", __func__);
3391
3392         priv->hw->dma->stop_rx(priv->ioaddr);
3393         priv->hw->dma->stop_tx(priv->ioaddr);
3394
3395         stmmac_set_mac(priv->ioaddr, false);
3396         netif_carrier_off(ndev);
3397         unregister_netdev(ndev);
3398         if (priv->plat->stmmac_rst)
3399                 reset_control_assert(priv->plat->stmmac_rst);
3400         clk_disable_unprepare(priv->plat->pclk);
3401         clk_disable_unprepare(priv->plat->stmmac_clk);
3402         if (priv->hw->pcs != STMMAC_PCS_RGMII &&
3403             priv->hw->pcs != STMMAC_PCS_TBI &&
3404             priv->hw->pcs != STMMAC_PCS_RTBI)
3405                 stmmac_mdio_unregister(ndev);
3406         free_netdev(ndev);
3407
3408         return 0;
3409 }
3410 EXPORT_SYMBOL_GPL(stmmac_dvr_remove);
3411
3412 /**
3413  * stmmac_suspend - suspend callback
3414  * @dev: device pointer
3415  * Description: this is the function to suspend the device and it is called
3416  * by the platform driver to stop the network queue, release the resources,
3417  * program the PMT register (for WoL), clean and release driver resources.
3418  */
3419 int stmmac_suspend(struct device *dev)
3420 {
3421         struct net_device *ndev = dev_get_drvdata(dev);
3422         struct stmmac_priv *priv = netdev_priv(ndev);
3423         unsigned long flags;
3424
3425         if (!ndev || !netif_running(ndev))
3426                 return 0;
3427
3428         if (ndev->phydev)
3429                 phy_stop(ndev->phydev);
3430
3431         spin_lock_irqsave(&priv->lock, flags);
3432
3433         netif_device_detach(ndev);
3434         netif_stop_queue(ndev);
3435
3436         napi_disable(&priv->napi);
3437
3438         /* Stop TX/RX DMA */
3439         priv->hw->dma->stop_tx(priv->ioaddr);
3440         priv->hw->dma->stop_rx(priv->ioaddr);
3441
3442         /* Enable Power down mode by programming the PMT regs */
3443         if (device_may_wakeup(priv->device)) {
3444                 priv->hw->mac->pmt(priv->hw, priv->wolopts);
3445                 priv->irq_wake = 1;
3446         } else {
3447                 stmmac_set_mac(priv->ioaddr, false);
3448                 pinctrl_pm_select_sleep_state(priv->device);
3449                 /* Disable clock in case of PWM is off */
3450                 clk_disable(priv->plat->pclk);
3451                 clk_disable(priv->plat->stmmac_clk);
3452         }
3453         spin_unlock_irqrestore(&priv->lock, flags);
3454
3455         priv->oldlink = 0;
3456         priv->speed = 0;
3457         priv->oldduplex = -1;
3458         return 0;
3459 }
3460 EXPORT_SYMBOL_GPL(stmmac_suspend);
3461
3462 /**
3463  * stmmac_resume - resume callback
3464  * @dev: device pointer
3465  * Description: when resume this function is invoked to setup the DMA and CORE
3466  * in a usable state.
3467  */
3468 int stmmac_resume(struct device *dev)
3469 {
3470         struct net_device *ndev = dev_get_drvdata(dev);
3471         struct stmmac_priv *priv = netdev_priv(ndev);
3472         unsigned long flags;
3473
3474         if (!netif_running(ndev))
3475                 return 0;
3476
3477         /* Power Down bit, into the PM register, is cleared
3478          * automatically as soon as a magic packet or a Wake-up frame
3479          * is received. Anyway, it's better to manually clear
3480          * this bit because it can generate problems while resuming
3481          * from another devices (e.g. serial console).
3482          */
3483         if (device_may_wakeup(priv->device)) {
3484                 spin_lock_irqsave(&priv->lock, flags);
3485                 priv->hw->mac->pmt(priv->hw, 0);
3486                 spin_unlock_irqrestore(&priv->lock, flags);
3487                 priv->irq_wake = 0;
3488         } else {
3489                 pinctrl_pm_select_default_state(priv->device);
3490                 /* enable the clk prevously disabled */
3491                 clk_enable(priv->plat->stmmac_clk);
3492                 clk_enable(priv->plat->pclk);
3493                 /* reset the phy so that it's ready */
3494                 if (priv->mii)
3495                         stmmac_mdio_reset(priv->mii);
3496         }
3497
3498         netif_device_attach(ndev);
3499
3500         spin_lock_irqsave(&priv->lock, flags);
3501
3502         priv->cur_rx = 0;
3503         priv->dirty_rx = 0;
3504         priv->dirty_tx = 0;
3505         priv->cur_tx = 0;
3506         /* reset private mss value to force mss context settings at
3507          * next tso xmit (only used for gmac4).
3508          */
3509         priv->mss = 0;
3510
3511         stmmac_clear_descriptors(priv);
3512
3513         stmmac_hw_setup(ndev, false);
3514         stmmac_init_tx_coalesce(priv);
3515         stmmac_set_rx_mode(ndev);
3516
3517         napi_enable(&priv->napi);
3518
3519         netif_start_queue(ndev);
3520
3521         spin_unlock_irqrestore(&priv->lock, flags);
3522
3523         if (ndev->phydev)
3524                 phy_start(ndev->phydev);
3525
3526         return 0;
3527 }
3528 EXPORT_SYMBOL_GPL(stmmac_resume);
3529
3530 #ifndef MODULE
3531 static int __init stmmac_cmdline_opt(char *str)
3532 {
3533         char *opt;
3534
3535         if (!str || !*str)
3536                 return -EINVAL;
3537         while ((opt = strsep(&str, ",")) != NULL) {
3538                 if (!strncmp(opt, "debug:", 6)) {
3539                         if (kstrtoint(opt + 6, 0, &debug))
3540                                 goto err;
3541                 } else if (!strncmp(opt, "phyaddr:", 8)) {
3542                         if (kstrtoint(opt + 8, 0, &phyaddr))
3543                                 goto err;
3544                 } else if (!strncmp(opt, "buf_sz:", 7)) {
3545                         if (kstrtoint(opt + 7, 0, &buf_sz))
3546                                 goto err;
3547                 } else if (!strncmp(opt, "tc:", 3)) {
3548                         if (kstrtoint(opt + 3, 0, &tc))
3549                                 goto err;
3550                 } else if (!strncmp(opt, "watchdog:", 9)) {
3551                         if (kstrtoint(opt + 9, 0, &watchdog))
3552                                 goto err;
3553                 } else if (!strncmp(opt, "flow_ctrl:", 10)) {
3554                         if (kstrtoint(opt + 10, 0, &flow_ctrl))
3555                                 goto err;
3556                 } else if (!strncmp(opt, "pause:", 6)) {
3557                         if (kstrtoint(opt + 6, 0, &pause))
3558                                 goto err;
3559                 } else if (!strncmp(opt, "eee_timer:", 10)) {
3560                         if (kstrtoint(opt + 10, 0, &eee_timer))
3561                                 goto err;
3562                 } else if (!strncmp(opt, "chain_mode:", 11)) {
3563                         if (kstrtoint(opt + 11, 0, &chain_mode))
3564                                 goto err;
3565                 }
3566         }
3567         return 0;
3568
3569 err:
3570         pr_err("%s: ERROR broken module parameter conversion", __func__);
3571         return -EINVAL;
3572 }
3573
3574 __setup("stmmaceth=", stmmac_cmdline_opt);
3575 #endif /* MODULE */
3576
3577 static int __init stmmac_init(void)
3578 {
3579 #ifdef CONFIG_DEBUG_FS
3580         /* Create debugfs main directory if it doesn't exist yet */
3581         if (!stmmac_fs_dir) {
3582                 stmmac_fs_dir = debugfs_create_dir(STMMAC_RESOURCE_NAME, NULL);
3583
3584                 if (!stmmac_fs_dir || IS_ERR(stmmac_fs_dir)) {
3585                         pr_err("ERROR %s, debugfs create directory failed\n",
3586                                STMMAC_RESOURCE_NAME);
3587
3588                         return -ENOMEM;
3589                 }
3590         }
3591 #endif
3592
3593         return 0;
3594 }
3595
3596 static void __exit stmmac_exit(void)
3597 {
3598 #ifdef CONFIG_DEBUG_FS
3599         debugfs_remove_recursive(stmmac_fs_dir);
3600 #endif
3601 }
3602
3603 module_init(stmmac_init)
3604 module_exit(stmmac_exit)
3605
3606 MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet device driver");
3607 MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>");
3608 MODULE_LICENSE("GPL");