1 /*******************************************************************************
2 This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers.
3 ST Ethernet IPs are built around a Synopsys IP Core.
5 Copyright(C) 2007-2011 STMicroelectronics Ltd
7 This program is free software; you can redistribute it and/or modify it
8 under the terms and conditions of the GNU General Public License,
9 version 2, as published by the Free Software Foundation.
11 This program is distributed in the hope it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 The full GNU General Public License is included in this distribution in
17 the file called "COPYING".
19 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
21 Documentation available at:
22 http://www.stlinux.com
24 https://bugzilla.stlinux.com/
25 *******************************************************************************/
27 #include <linux/clk.h>
28 #include <linux/kernel.h>
29 #include <linux/interrupt.h>
31 #include <linux/tcp.h>
32 #include <linux/skbuff.h>
33 #include <linux/ethtool.h>
34 #include <linux/if_ether.h>
35 #include <linux/crc32.h>
36 #include <linux/mii.h>
38 #include <linux/if_vlan.h>
39 #include <linux/dma-mapping.h>
40 #include <linux/slab.h>
41 #include <linux/prefetch.h>
42 #include <linux/pinctrl/consumer.h>
43 #ifdef CONFIG_DEBUG_FS
44 #include <linux/debugfs.h>
45 #include <linux/seq_file.h>
46 #endif /* CONFIG_DEBUG_FS */
47 #include <linux/net_tstamp.h>
48 #include <net/pkt_cls.h>
49 #include "stmmac_ptp.h"
51 #include <linux/reset.h>
52 #include <linux/of_mdio.h>
53 #include "dwmac1000.h"
56 #define STMMAC_ALIGN(x) L1_CACHE_ALIGN(x)
57 #define TSO_MAX_BUFF_SIZE (SZ_16K - 1)
59 /* Module parameters */
61 static int watchdog = TX_TIMEO;
62 module_param(watchdog, int, 0644);
63 MODULE_PARM_DESC(watchdog, "Transmit timeout in milliseconds (default 5s)");
65 static int debug = -1;
66 module_param(debug, int, 0644);
67 MODULE_PARM_DESC(debug, "Message Level (-1: default, 0: no output, 16: all)");
69 static int phyaddr = -1;
70 module_param(phyaddr, int, 0444);
71 MODULE_PARM_DESC(phyaddr, "Physical device address");
73 #define STMMAC_TX_THRESH (DMA_TX_SIZE / 4)
74 #define STMMAC_RX_THRESH (DMA_RX_SIZE / 4)
76 static int flow_ctrl = FLOW_OFF;
77 module_param(flow_ctrl, int, 0644);
78 MODULE_PARM_DESC(flow_ctrl, "Flow control ability [on/off]");
80 static int pause = PAUSE_TIME;
81 module_param(pause, int, 0644);
82 MODULE_PARM_DESC(pause, "Flow Control Pause Time");
85 static int tc = TC_DEFAULT;
86 module_param(tc, int, 0644);
87 MODULE_PARM_DESC(tc, "DMA threshold control value");
89 #define DEFAULT_BUFSIZE 1536
90 static int buf_sz = DEFAULT_BUFSIZE;
91 module_param(buf_sz, int, 0644);
92 MODULE_PARM_DESC(buf_sz, "DMA buffer size");
94 #define STMMAC_RX_COPYBREAK 256
96 static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE |
97 NETIF_MSG_LINK | NETIF_MSG_IFUP |
98 NETIF_MSG_IFDOWN | NETIF_MSG_TIMER);
100 #define STMMAC_DEFAULT_LPI_TIMER 1000
101 static int eee_timer = STMMAC_DEFAULT_LPI_TIMER;
102 module_param(eee_timer, int, 0644);
103 MODULE_PARM_DESC(eee_timer, "LPI tx expiration time in msec");
104 #define STMMAC_LPI_T(x) (jiffies + msecs_to_jiffies(x))
106 /* By default the driver will use the ring mode to manage tx and rx descriptors,
107 * but allow user to force to use the chain instead of the ring
109 static unsigned int chain_mode;
110 module_param(chain_mode, int, 0444);
111 MODULE_PARM_DESC(chain_mode, "To use chain instead of ring mode");
113 static irqreturn_t stmmac_interrupt(int irq, void *dev_id);
115 #ifdef CONFIG_DEBUG_FS
116 static int stmmac_init_fs(struct net_device *dev);
117 static void stmmac_exit_fs(struct net_device *dev);
120 #define STMMAC_COAL_TIMER(x) (jiffies + usecs_to_jiffies(x))
123 * stmmac_verify_args - verify the driver parameters.
124 * Description: it checks the driver parameters and set a default in case of
127 static void stmmac_verify_args(void)
129 if (unlikely(watchdog < 0))
131 if (unlikely((buf_sz < DEFAULT_BUFSIZE) || (buf_sz > BUF_SIZE_16KiB)))
132 buf_sz = DEFAULT_BUFSIZE;
133 if (unlikely(flow_ctrl > 1))
134 flow_ctrl = FLOW_AUTO;
135 else if (likely(flow_ctrl < 0))
136 flow_ctrl = FLOW_OFF;
137 if (unlikely((pause < 0) || (pause > 0xffff)))
140 eee_timer = STMMAC_DEFAULT_LPI_TIMER;
144 * stmmac_disable_all_queues - Disable all queues
145 * @priv: driver private structure
147 static void stmmac_disable_all_queues(struct stmmac_priv *priv)
149 u32 rx_queues_cnt = priv->plat->rx_queues_to_use;
152 for (queue = 0; queue < rx_queues_cnt; queue++) {
153 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
155 napi_disable(&rx_q->napi);
160 * stmmac_enable_all_queues - Enable all queues
161 * @priv: driver private structure
163 static void stmmac_enable_all_queues(struct stmmac_priv *priv)
165 u32 rx_queues_cnt = priv->plat->rx_queues_to_use;
168 for (queue = 0; queue < rx_queues_cnt; queue++) {
169 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
171 napi_enable(&rx_q->napi);
176 * stmmac_stop_all_queues - Stop all queues
177 * @priv: driver private structure
179 static void stmmac_stop_all_queues(struct stmmac_priv *priv)
181 u32 tx_queues_cnt = priv->plat->tx_queues_to_use;
184 for (queue = 0; queue < tx_queues_cnt; queue++)
185 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, queue));
189 * stmmac_start_all_queues - Start all queues
190 * @priv: driver private structure
192 static void stmmac_start_all_queues(struct stmmac_priv *priv)
194 u32 tx_queues_cnt = priv->plat->tx_queues_to_use;
197 for (queue = 0; queue < tx_queues_cnt; queue++)
198 netif_tx_start_queue(netdev_get_tx_queue(priv->dev, queue));
201 static void stmmac_service_event_schedule(struct stmmac_priv *priv)
203 if (!test_bit(STMMAC_DOWN, &priv->state) &&
204 !test_and_set_bit(STMMAC_SERVICE_SCHED, &priv->state))
205 queue_work(priv->wq, &priv->service_task);
208 static void stmmac_global_err(struct stmmac_priv *priv)
210 netif_carrier_off(priv->dev);
211 set_bit(STMMAC_RESET_REQUESTED, &priv->state);
212 stmmac_service_event_schedule(priv);
216 * stmmac_clk_csr_set - dynamically set the MDC clock
217 * @priv: driver private structure
218 * Description: this is to dynamically set the MDC clock according to the csr
221 * If a specific clk_csr value is passed from the platform
222 * this means that the CSR Clock Range selection cannot be
223 * changed at run-time and it is fixed (as reported in the driver
224 * documentation). Viceversa the driver will try to set the MDC
225 * clock dynamically according to the actual clock input.
227 static void stmmac_clk_csr_set(struct stmmac_priv *priv)
231 clk_rate = clk_get_rate(priv->plat->stmmac_clk);
233 /* Platform provided default clk_csr would be assumed valid
234 * for all other cases except for the below mentioned ones.
235 * For values higher than the IEEE 802.3 specified frequency
236 * we can not estimate the proper divider as it is not known
237 * the frequency of clk_csr_i. So we do not change the default
240 if (!(priv->clk_csr & MAC_CSR_H_FRQ_MASK)) {
241 if (clk_rate < CSR_F_35M)
242 priv->clk_csr = STMMAC_CSR_20_35M;
243 else if ((clk_rate >= CSR_F_35M) && (clk_rate < CSR_F_60M))
244 priv->clk_csr = STMMAC_CSR_35_60M;
245 else if ((clk_rate >= CSR_F_60M) && (clk_rate < CSR_F_100M))
246 priv->clk_csr = STMMAC_CSR_60_100M;
247 else if ((clk_rate >= CSR_F_100M) && (clk_rate < CSR_F_150M))
248 priv->clk_csr = STMMAC_CSR_100_150M;
249 else if ((clk_rate >= CSR_F_150M) && (clk_rate < CSR_F_250M))
250 priv->clk_csr = STMMAC_CSR_150_250M;
251 else if ((clk_rate >= CSR_F_250M) && (clk_rate < CSR_F_300M))
252 priv->clk_csr = STMMAC_CSR_250_300M;
255 if (priv->plat->has_sun8i) {
256 if (clk_rate > 160000000)
257 priv->clk_csr = 0x03;
258 else if (clk_rate > 80000000)
259 priv->clk_csr = 0x02;
260 else if (clk_rate > 40000000)
261 priv->clk_csr = 0x01;
267 static void print_pkt(unsigned char *buf, int len)
269 pr_debug("len = %d byte, buf addr: 0x%p\n", len, buf);
270 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, buf, len);
273 static inline u32 stmmac_tx_avail(struct stmmac_priv *priv, u32 queue)
275 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
278 if (tx_q->dirty_tx > tx_q->cur_tx)
279 avail = tx_q->dirty_tx - tx_q->cur_tx - 1;
281 avail = DMA_TX_SIZE - tx_q->cur_tx + tx_q->dirty_tx - 1;
287 * stmmac_rx_dirty - Get RX queue dirty
288 * @priv: driver private structure
289 * @queue: RX queue index
291 static inline u32 stmmac_rx_dirty(struct stmmac_priv *priv, u32 queue)
293 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
296 if (rx_q->dirty_rx <= rx_q->cur_rx)
297 dirty = rx_q->cur_rx - rx_q->dirty_rx;
299 dirty = DMA_RX_SIZE - rx_q->dirty_rx + rx_q->cur_rx;
305 * stmmac_hw_fix_mac_speed - callback for speed selection
306 * @priv: driver private structure
307 * Description: on some platforms (e.g. ST), some HW system configuration
308 * registers have to be set according to the link speed negotiated.
310 static inline void stmmac_hw_fix_mac_speed(struct stmmac_priv *priv)
312 struct net_device *ndev = priv->dev;
313 struct phy_device *phydev = ndev->phydev;
315 if (likely(priv->plat->fix_mac_speed))
316 priv->plat->fix_mac_speed(priv->plat->bsp_priv, phydev->speed);
320 * stmmac_enable_eee_mode - check and enter in LPI mode
321 * @priv: driver private structure
322 * Description: this function is to verify and enter in LPI mode in case of
325 static void stmmac_enable_eee_mode(struct stmmac_priv *priv)
327 u32 tx_cnt = priv->plat->tx_queues_to_use;
330 /* check if all TX queues have the work finished */
331 for (queue = 0; queue < tx_cnt; queue++) {
332 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
334 if (tx_q->dirty_tx != tx_q->cur_tx)
335 return; /* still unfinished work */
338 /* Check and enter in LPI mode */
339 if (!priv->tx_path_in_lpi_mode)
340 stmmac_set_eee_mode(priv, priv->hw,
341 priv->plat->en_tx_lpi_clockgating);
345 * stmmac_disable_eee_mode - disable and exit from LPI mode
346 * @priv: driver private structure
347 * Description: this function is to exit and disable EEE in case of
348 * LPI state is true. This is called by the xmit.
350 void stmmac_disable_eee_mode(struct stmmac_priv *priv)
352 stmmac_reset_eee_mode(priv, priv->hw);
353 del_timer_sync(&priv->eee_ctrl_timer);
354 priv->tx_path_in_lpi_mode = false;
358 * stmmac_eee_ctrl_timer - EEE TX SW timer.
361 * if there is no data transfer and if we are not in LPI state,
362 * then MAC Transmitter can be moved to LPI state.
364 static void stmmac_eee_ctrl_timer(struct timer_list *t)
366 struct stmmac_priv *priv = from_timer(priv, t, eee_ctrl_timer);
368 stmmac_enable_eee_mode(priv);
369 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer));
373 * stmmac_eee_init - init EEE
374 * @priv: driver private structure
376 * if the GMAC supports the EEE (from the HW cap reg) and the phy device
377 * can also manage EEE, this function enable the LPI state and start related
380 bool stmmac_eee_init(struct stmmac_priv *priv)
382 struct net_device *ndev = priv->dev;
383 int interface = priv->plat->interface;
386 if ((interface != PHY_INTERFACE_MODE_MII) &&
387 (interface != PHY_INTERFACE_MODE_GMII) &&
388 !phy_interface_mode_is_rgmii(interface))
391 /* Using PCS we cannot dial with the phy registers at this stage
392 * so we do not support extra feature like EEE.
394 if ((priv->hw->pcs == STMMAC_PCS_RGMII) ||
395 (priv->hw->pcs == STMMAC_PCS_TBI) ||
396 (priv->hw->pcs == STMMAC_PCS_RTBI))
399 /* MAC core supports the EEE feature. */
400 if (priv->dma_cap.eee) {
401 int tx_lpi_timer = priv->tx_lpi_timer;
403 /* Check if the PHY supports EEE */
404 if (phy_init_eee(ndev->phydev, 1)) {
405 /* To manage at run-time if the EEE cannot be supported
406 * anymore (for example because the lp caps have been
408 * In that case the driver disable own timers.
410 mutex_lock(&priv->lock);
411 if (priv->eee_active) {
412 netdev_dbg(priv->dev, "disable EEE\n");
413 del_timer_sync(&priv->eee_ctrl_timer);
414 stmmac_set_eee_timer(priv, priv->hw, 0,
417 priv->eee_active = 0;
418 mutex_unlock(&priv->lock);
421 /* Activate the EEE and start timers */
422 mutex_lock(&priv->lock);
423 if (!priv->eee_active) {
424 priv->eee_active = 1;
425 timer_setup(&priv->eee_ctrl_timer,
426 stmmac_eee_ctrl_timer, 0);
427 mod_timer(&priv->eee_ctrl_timer,
428 STMMAC_LPI_T(eee_timer));
430 stmmac_set_eee_timer(priv, priv->hw,
431 STMMAC_DEFAULT_LIT_LS, tx_lpi_timer);
433 /* Set HW EEE according to the speed */
434 stmmac_set_eee_pls(priv, priv->hw, ndev->phydev->link);
437 mutex_unlock(&priv->lock);
439 netdev_dbg(priv->dev, "Energy-Efficient Ethernet initialized\n");
445 /* stmmac_get_tx_hwtstamp - get HW TX timestamps
446 * @priv: driver private structure
447 * @p : descriptor pointer
448 * @skb : the socket buffer
450 * This function will read timestamp from the descriptor & pass it to stack.
451 * and also perform some sanity checks.
453 static void stmmac_get_tx_hwtstamp(struct stmmac_priv *priv,
454 struct dma_desc *p, struct sk_buff *skb)
456 struct skb_shared_hwtstamps shhwtstamp;
459 if (!priv->hwts_tx_en)
462 /* exit if skb doesn't support hw tstamp */
463 if (likely(!skb || !(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)))
466 /* check tx tstamp status */
467 if (stmmac_get_tx_timestamp_status(priv, p)) {
468 /* get the valid tstamp */
469 stmmac_get_timestamp(priv, p, priv->adv_ts, &ns);
471 memset(&shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps));
472 shhwtstamp.hwtstamp = ns_to_ktime(ns);
474 netdev_dbg(priv->dev, "get valid TX hw timestamp %llu\n", ns);
475 /* pass tstamp to stack */
476 skb_tstamp_tx(skb, &shhwtstamp);
482 /* stmmac_get_rx_hwtstamp - get HW RX timestamps
483 * @priv: driver private structure
484 * @p : descriptor pointer
485 * @np : next descriptor pointer
486 * @skb : the socket buffer
488 * This function will read received packet's timestamp from the descriptor
489 * and pass it to stack. It also perform some sanity checks.
491 static void stmmac_get_rx_hwtstamp(struct stmmac_priv *priv, struct dma_desc *p,
492 struct dma_desc *np, struct sk_buff *skb)
494 struct skb_shared_hwtstamps *shhwtstamp = NULL;
495 struct dma_desc *desc = p;
498 if (!priv->hwts_rx_en)
500 /* For GMAC4, the valid timestamp is from CTX next desc. */
501 if (priv->plat->has_gmac4)
504 /* Check if timestamp is available */
505 if (stmmac_get_rx_timestamp_status(priv, p, np, priv->adv_ts)) {
506 stmmac_get_timestamp(priv, desc, priv->adv_ts, &ns);
507 netdev_dbg(priv->dev, "get valid RX hw timestamp %llu\n", ns);
508 shhwtstamp = skb_hwtstamps(skb);
509 memset(shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps));
510 shhwtstamp->hwtstamp = ns_to_ktime(ns);
512 netdev_dbg(priv->dev, "cannot get RX hw timestamp\n");
517 * stmmac_hwtstamp_ioctl - control hardware timestamping.
518 * @dev: device pointer.
519 * @ifr: An IOCTL specific structure, that can contain a pointer to
520 * a proprietary structure used to pass information to the driver.
522 * This function configures the MAC to enable/disable both outgoing(TX)
523 * and incoming(RX) packets time stamping based on user input.
525 * 0 on success and an appropriate -ve integer on failure.
527 static int stmmac_hwtstamp_ioctl(struct net_device *dev, struct ifreq *ifr)
529 struct stmmac_priv *priv = netdev_priv(dev);
530 struct hwtstamp_config config;
531 struct timespec64 now;
535 u32 ptp_over_ipv4_udp = 0;
536 u32 ptp_over_ipv6_udp = 0;
537 u32 ptp_over_ethernet = 0;
538 u32 snap_type_sel = 0;
539 u32 ts_master_en = 0;
544 if (!(priv->dma_cap.time_stamp || priv->adv_ts)) {
545 netdev_alert(priv->dev, "No support for HW time stamping\n");
546 priv->hwts_tx_en = 0;
547 priv->hwts_rx_en = 0;
552 if (copy_from_user(&config, ifr->ifr_data,
553 sizeof(struct hwtstamp_config)))
556 netdev_dbg(priv->dev, "%s config flags:0x%x, tx_type:0x%x, rx_filter:0x%x\n",
557 __func__, config.flags, config.tx_type, config.rx_filter);
559 /* reserved for future extensions */
563 if (config.tx_type != HWTSTAMP_TX_OFF &&
564 config.tx_type != HWTSTAMP_TX_ON)
568 switch (config.rx_filter) {
569 case HWTSTAMP_FILTER_NONE:
570 /* time stamp no incoming packet at all */
571 config.rx_filter = HWTSTAMP_FILTER_NONE;
574 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
575 /* PTP v1, UDP, any kind of event packet */
576 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
577 /* take time stamp for all event messages */
578 if (priv->plat->has_gmac4)
579 snap_type_sel = PTP_GMAC4_TCR_SNAPTYPSEL_1;
581 snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
583 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
584 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
587 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
588 /* PTP v1, UDP, Sync packet */
589 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_SYNC;
590 /* take time stamp for SYNC messages only */
591 ts_event_en = PTP_TCR_TSEVNTENA;
593 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
594 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
597 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
598 /* PTP v1, UDP, Delay_req packet */
599 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ;
600 /* take time stamp for Delay_Req messages only */
601 ts_master_en = PTP_TCR_TSMSTRENA;
602 ts_event_en = PTP_TCR_TSEVNTENA;
604 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
605 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
608 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
609 /* PTP v2, UDP, any kind of event packet */
610 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
611 ptp_v2 = PTP_TCR_TSVER2ENA;
612 /* take time stamp for all event messages */
613 if (priv->plat->has_gmac4)
614 snap_type_sel = PTP_GMAC4_TCR_SNAPTYPSEL_1;
616 snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
618 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
619 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
622 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
623 /* PTP v2, UDP, Sync packet */
624 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_SYNC;
625 ptp_v2 = PTP_TCR_TSVER2ENA;
626 /* take time stamp for SYNC messages only */
627 ts_event_en = PTP_TCR_TSEVNTENA;
629 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
630 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
633 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
634 /* PTP v2, UDP, Delay_req packet */
635 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ;
636 ptp_v2 = PTP_TCR_TSVER2ENA;
637 /* take time stamp for Delay_Req messages only */
638 ts_master_en = PTP_TCR_TSMSTRENA;
639 ts_event_en = PTP_TCR_TSEVNTENA;
641 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
642 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
645 case HWTSTAMP_FILTER_PTP_V2_EVENT:
646 /* PTP v2/802.AS1 any layer, any kind of event packet */
647 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
648 ptp_v2 = PTP_TCR_TSVER2ENA;
649 /* take time stamp for all event messages */
650 if (priv->plat->has_gmac4)
651 snap_type_sel = PTP_GMAC4_TCR_SNAPTYPSEL_1;
653 snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
655 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
656 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
657 ptp_over_ethernet = PTP_TCR_TSIPENA;
660 case HWTSTAMP_FILTER_PTP_V2_SYNC:
661 /* PTP v2/802.AS1, any layer, Sync packet */
662 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_SYNC;
663 ptp_v2 = PTP_TCR_TSVER2ENA;
664 /* take time stamp for SYNC messages only */
665 ts_event_en = PTP_TCR_TSEVNTENA;
667 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
668 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
669 ptp_over_ethernet = PTP_TCR_TSIPENA;
672 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
673 /* PTP v2/802.AS1, any layer, Delay_req packet */
674 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_DELAY_REQ;
675 ptp_v2 = PTP_TCR_TSVER2ENA;
676 /* take time stamp for Delay_Req messages only */
677 ts_master_en = PTP_TCR_TSMSTRENA;
678 ts_event_en = PTP_TCR_TSEVNTENA;
680 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
681 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
682 ptp_over_ethernet = PTP_TCR_TSIPENA;
685 case HWTSTAMP_FILTER_NTP_ALL:
686 case HWTSTAMP_FILTER_ALL:
687 /* time stamp any incoming packet */
688 config.rx_filter = HWTSTAMP_FILTER_ALL;
689 tstamp_all = PTP_TCR_TSENALL;
696 switch (config.rx_filter) {
697 case HWTSTAMP_FILTER_NONE:
698 config.rx_filter = HWTSTAMP_FILTER_NONE;
701 /* PTP v1, UDP, any kind of event packet */
702 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
706 priv->hwts_rx_en = ((config.rx_filter == HWTSTAMP_FILTER_NONE) ? 0 : 1);
707 priv->hwts_tx_en = config.tx_type == HWTSTAMP_TX_ON;
709 if (!priv->hwts_tx_en && !priv->hwts_rx_en)
710 stmmac_config_hw_tstamping(priv, priv->ptpaddr, 0);
712 value = (PTP_TCR_TSENA | PTP_TCR_TSCFUPDT | PTP_TCR_TSCTRLSSR |
713 tstamp_all | ptp_v2 | ptp_over_ethernet |
714 ptp_over_ipv6_udp | ptp_over_ipv4_udp | ts_event_en |
715 ts_master_en | snap_type_sel);
716 stmmac_config_hw_tstamping(priv, priv->ptpaddr, value);
718 /* program Sub Second Increment reg */
719 stmmac_config_sub_second_increment(priv,
720 priv->ptpaddr, priv->plat->clk_ptp_rate,
721 priv->plat->has_gmac4, &sec_inc);
722 temp = div_u64(1000000000ULL, sec_inc);
724 /* Store sub second increment and flags for later use */
725 priv->sub_second_inc = sec_inc;
726 priv->systime_flags = value;
728 /* calculate default added value:
730 * addend = (2^32)/freq_div_ratio;
731 * where, freq_div_ratio = 1e9ns/sec_inc
733 temp = (u64)(temp << 32);
734 priv->default_addend = div_u64(temp, priv->plat->clk_ptp_rate);
735 stmmac_config_addend(priv, priv->ptpaddr, priv->default_addend);
737 /* initialize system time */
738 ktime_get_real_ts64(&now);
740 /* lower 32 bits of tv_sec are safe until y2106 */
741 stmmac_init_systime(priv, priv->ptpaddr,
742 (u32)now.tv_sec, now.tv_nsec);
745 return copy_to_user(ifr->ifr_data, &config,
746 sizeof(struct hwtstamp_config)) ? -EFAULT : 0;
750 * stmmac_init_ptp - init PTP
751 * @priv: driver private structure
752 * Description: this is to verify if the HW supports the PTPv1 or PTPv2.
753 * This is done by looking at the HW cap. register.
754 * This function also registers the ptp driver.
756 static int stmmac_init_ptp(struct stmmac_priv *priv)
758 if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp))
762 /* Check if adv_ts can be enabled for dwmac 4.x core */
763 if (priv->plat->has_gmac4 && priv->dma_cap.atime_stamp)
765 /* Dwmac 3.x core with extend_desc can support adv_ts */
766 else if (priv->extend_desc && priv->dma_cap.atime_stamp)
769 if (priv->dma_cap.time_stamp)
770 netdev_info(priv->dev, "IEEE 1588-2002 Timestamp supported\n");
773 netdev_info(priv->dev,
774 "IEEE 1588-2008 Advanced Timestamp supported\n");
776 priv->hwts_tx_en = 0;
777 priv->hwts_rx_en = 0;
779 stmmac_ptp_register(priv);
784 static void stmmac_release_ptp(struct stmmac_priv *priv)
786 if (priv->plat->clk_ptp_ref)
787 clk_disable_unprepare(priv->plat->clk_ptp_ref);
788 stmmac_ptp_unregister(priv);
792 * stmmac_mac_flow_ctrl - Configure flow control in all queues
793 * @priv: driver private structure
794 * Description: It is used for configuring the flow control in all queues
796 static void stmmac_mac_flow_ctrl(struct stmmac_priv *priv, u32 duplex)
798 u32 tx_cnt = priv->plat->tx_queues_to_use;
800 stmmac_flow_ctrl(priv, priv->hw, duplex, priv->flow_ctrl,
801 priv->pause, tx_cnt);
805 * stmmac_adjust_link - adjusts the link parameters
806 * @dev: net device structure
807 * Description: this is the helper called by the physical abstraction layer
808 * drivers to communicate the phy link status. According the speed and duplex
809 * this driver can invoke registered glue-logic as well.
810 * It also invoke the eee initialization because it could happen when switch
811 * on different networks (that are eee capable).
813 static void stmmac_adjust_link(struct net_device *dev)
815 struct stmmac_priv *priv = netdev_priv(dev);
816 struct phy_device *phydev = dev->phydev;
817 bool new_state = false;
822 mutex_lock(&priv->lock);
825 u32 ctrl = readl(priv->ioaddr + MAC_CTRL_REG);
827 /* Now we make sure that we can be in full duplex mode.
828 * If not, we operate in half-duplex mode. */
829 if (phydev->duplex != priv->oldduplex) {
832 ctrl &= ~priv->hw->link.duplex;
834 ctrl |= priv->hw->link.duplex;
835 priv->oldduplex = phydev->duplex;
837 /* Flow Control operation */
839 stmmac_mac_flow_ctrl(priv, phydev->duplex);
841 if (phydev->speed != priv->speed) {
843 ctrl &= ~priv->hw->link.speed_mask;
844 switch (phydev->speed) {
846 ctrl |= priv->hw->link.speed1000;
849 ctrl |= priv->hw->link.speed100;
852 ctrl |= priv->hw->link.speed10;
855 netif_warn(priv, link, priv->dev,
856 "broken speed: %d\n", phydev->speed);
857 phydev->speed = SPEED_UNKNOWN;
860 if (phydev->speed != SPEED_UNKNOWN)
861 stmmac_hw_fix_mac_speed(priv);
862 priv->speed = phydev->speed;
865 writel(ctrl, priv->ioaddr + MAC_CTRL_REG);
867 if (!priv->oldlink) {
869 priv->oldlink = true;
871 } else if (priv->oldlink) {
873 priv->oldlink = false;
874 priv->speed = SPEED_UNKNOWN;
875 priv->oldduplex = DUPLEX_UNKNOWN;
878 if (new_state && netif_msg_link(priv))
879 phy_print_status(phydev);
881 mutex_unlock(&priv->lock);
883 if (phydev->is_pseudo_fixed_link)
884 /* Stop PHY layer to call the hook to adjust the link in case
885 * of a switch is attached to the stmmac driver.
887 phydev->irq = PHY_IGNORE_INTERRUPT;
889 /* At this stage, init the EEE if supported.
890 * Never called in case of fixed_link.
892 priv->eee_enabled = stmmac_eee_init(priv);
896 * stmmac_check_pcs_mode - verify if RGMII/SGMII is supported
897 * @priv: driver private structure
898 * Description: this is to verify if the HW supports the PCS.
899 * Physical Coding Sublayer (PCS) interface that can be used when the MAC is
900 * configured for the TBI, RTBI, or SGMII PHY interface.
902 static void stmmac_check_pcs_mode(struct stmmac_priv *priv)
904 int interface = priv->plat->interface;
906 if (priv->dma_cap.pcs) {
907 if ((interface == PHY_INTERFACE_MODE_RGMII) ||
908 (interface == PHY_INTERFACE_MODE_RGMII_ID) ||
909 (interface == PHY_INTERFACE_MODE_RGMII_RXID) ||
910 (interface == PHY_INTERFACE_MODE_RGMII_TXID)) {
911 netdev_dbg(priv->dev, "PCS RGMII support enabled\n");
912 priv->hw->pcs = STMMAC_PCS_RGMII;
913 } else if (interface == PHY_INTERFACE_MODE_SGMII) {
914 netdev_dbg(priv->dev, "PCS SGMII support enabled\n");
915 priv->hw->pcs = STMMAC_PCS_SGMII;
921 * stmmac_init_phy - PHY initialization
922 * @dev: net device structure
923 * Description: it initializes the driver's PHY state, and attaches the PHY
928 static int stmmac_init_phy(struct net_device *dev)
930 struct stmmac_priv *priv = netdev_priv(dev);
931 u32 tx_cnt = priv->plat->tx_queues_to_use;
932 struct phy_device *phydev;
933 char phy_id_fmt[MII_BUS_ID_SIZE + 3];
934 char bus_id[MII_BUS_ID_SIZE];
935 int interface = priv->plat->interface;
936 int max_speed = priv->plat->max_speed;
937 priv->oldlink = false;
938 priv->speed = SPEED_UNKNOWN;
939 priv->oldduplex = DUPLEX_UNKNOWN;
941 if (priv->plat->phy_node) {
942 phydev = of_phy_connect(dev, priv->plat->phy_node,
943 &stmmac_adjust_link, 0, interface);
945 snprintf(bus_id, MII_BUS_ID_SIZE, "stmmac-%x",
948 snprintf(phy_id_fmt, MII_BUS_ID_SIZE + 3, PHY_ID_FMT, bus_id,
949 priv->plat->phy_addr);
950 netdev_dbg(priv->dev, "%s: trying to attach to %s\n", __func__,
953 phydev = phy_connect(dev, phy_id_fmt, &stmmac_adjust_link,
957 if (IS_ERR_OR_NULL(phydev)) {
958 netdev_err(priv->dev, "Could not attach to PHY\n");
962 return PTR_ERR(phydev);
965 /* Stop Advertising 1000BASE Capability if interface is not GMII */
966 if ((interface == PHY_INTERFACE_MODE_MII) ||
967 (interface == PHY_INTERFACE_MODE_RMII) ||
968 (max_speed < 1000 && max_speed > 0))
969 phydev->advertising &= ~(SUPPORTED_1000baseT_Half |
970 SUPPORTED_1000baseT_Full);
973 * Half-duplex mode not supported with multiqueue
974 * half-duplex can only works with single queue
977 phydev->supported &= ~(SUPPORTED_1000baseT_Half |
978 SUPPORTED_100baseT_Half |
979 SUPPORTED_10baseT_Half);
982 * Broken HW is sometimes missing the pull-up resistor on the
983 * MDIO line, which results in reads to non-existent devices returning
984 * 0 rather than 0xffff. Catch this here and treat 0 as a non-existent
986 * Note: phydev->phy_id is the result of reading the UID PHY registers.
988 if (!priv->plat->phy_node && phydev->phy_id == 0) {
989 phy_disconnect(phydev);
993 /* stmmac_adjust_link will change this to PHY_IGNORE_INTERRUPT to avoid
994 * subsequent PHY polling, make sure we force a link transition if
995 * we have a UP/DOWN/UP transition
997 if (phydev->is_pseudo_fixed_link)
998 phydev->irq = PHY_POLL;
1000 phy_attached_info(phydev);
1004 static void stmmac_display_rx_rings(struct stmmac_priv *priv)
1006 u32 rx_cnt = priv->plat->rx_queues_to_use;
1010 /* Display RX rings */
1011 for (queue = 0; queue < rx_cnt; queue++) {
1012 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1014 pr_info("\tRX Queue %u rings\n", queue);
1016 if (priv->extend_desc)
1017 head_rx = (void *)rx_q->dma_erx;
1019 head_rx = (void *)rx_q->dma_rx;
1021 /* Display RX ring */
1022 stmmac_display_ring(priv, head_rx, DMA_RX_SIZE, true);
1026 static void stmmac_display_tx_rings(struct stmmac_priv *priv)
1028 u32 tx_cnt = priv->plat->tx_queues_to_use;
1032 /* Display TX rings */
1033 for (queue = 0; queue < tx_cnt; queue++) {
1034 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1036 pr_info("\tTX Queue %d rings\n", queue);
1038 if (priv->extend_desc)
1039 head_tx = (void *)tx_q->dma_etx;
1041 head_tx = (void *)tx_q->dma_tx;
1043 stmmac_display_ring(priv, head_tx, DMA_TX_SIZE, false);
1047 static void stmmac_display_rings(struct stmmac_priv *priv)
1049 /* Display RX ring */
1050 stmmac_display_rx_rings(priv);
1052 /* Display TX ring */
1053 stmmac_display_tx_rings(priv);
1056 static int stmmac_set_bfsize(int mtu, int bufsize)
1060 if (mtu >= BUF_SIZE_4KiB)
1061 ret = BUF_SIZE_8KiB;
1062 else if (mtu >= BUF_SIZE_2KiB)
1063 ret = BUF_SIZE_4KiB;
1064 else if (mtu > DEFAULT_BUFSIZE)
1065 ret = BUF_SIZE_2KiB;
1067 ret = DEFAULT_BUFSIZE;
1073 * stmmac_clear_rx_descriptors - clear RX descriptors
1074 * @priv: driver private structure
1075 * @queue: RX queue index
1076 * Description: this function is called to clear the RX descriptors
1077 * in case of both basic and extended descriptors are used.
1079 static void stmmac_clear_rx_descriptors(struct stmmac_priv *priv, u32 queue)
1081 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1084 /* Clear the RX descriptors */
1085 for (i = 0; i < DMA_RX_SIZE; i++)
1086 if (priv->extend_desc)
1087 stmmac_init_rx_desc(priv, &rx_q->dma_erx[i].basic,
1088 priv->use_riwt, priv->mode,
1089 (i == DMA_RX_SIZE - 1));
1091 stmmac_init_rx_desc(priv, &rx_q->dma_rx[i],
1092 priv->use_riwt, priv->mode,
1093 (i == DMA_RX_SIZE - 1));
1097 * stmmac_clear_tx_descriptors - clear tx descriptors
1098 * @priv: driver private structure
1099 * @queue: TX queue index.
1100 * Description: this function is called to clear the TX descriptors
1101 * in case of both basic and extended descriptors are used.
1103 static void stmmac_clear_tx_descriptors(struct stmmac_priv *priv, u32 queue)
1105 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1108 /* Clear the TX descriptors */
1109 for (i = 0; i < DMA_TX_SIZE; i++)
1110 if (priv->extend_desc)
1111 stmmac_init_tx_desc(priv, &tx_q->dma_etx[i].basic,
1112 priv->mode, (i == DMA_TX_SIZE - 1));
1114 stmmac_init_tx_desc(priv, &tx_q->dma_tx[i],
1115 priv->mode, (i == DMA_TX_SIZE - 1));
1119 * stmmac_clear_descriptors - clear descriptors
1120 * @priv: driver private structure
1121 * Description: this function is called to clear the TX and RX descriptors
1122 * in case of both basic and extended descriptors are used.
1124 static void stmmac_clear_descriptors(struct stmmac_priv *priv)
1126 u32 rx_queue_cnt = priv->plat->rx_queues_to_use;
1127 u32 tx_queue_cnt = priv->plat->tx_queues_to_use;
1130 /* Clear the RX descriptors */
1131 for (queue = 0; queue < rx_queue_cnt; queue++)
1132 stmmac_clear_rx_descriptors(priv, queue);
1134 /* Clear the TX descriptors */
1135 for (queue = 0; queue < tx_queue_cnt; queue++)
1136 stmmac_clear_tx_descriptors(priv, queue);
1140 * stmmac_init_rx_buffers - init the RX descriptor buffer.
1141 * @priv: driver private structure
1142 * @p: descriptor pointer
1143 * @i: descriptor index
1145 * @queue: RX queue index
1146 * Description: this function is called to allocate a receive buffer, perform
1147 * the DMA mapping and init the descriptor.
1149 static int stmmac_init_rx_buffers(struct stmmac_priv *priv, struct dma_desc *p,
1150 int i, gfp_t flags, u32 queue)
1152 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1153 struct sk_buff *skb;
1155 skb = __netdev_alloc_skb_ip_align(priv->dev, priv->dma_buf_sz, flags);
1157 netdev_err(priv->dev,
1158 "%s: Rx init fails; skb is NULL\n", __func__);
1161 rx_q->rx_skbuff[i] = skb;
1162 rx_q->rx_skbuff_dma[i] = dma_map_single(priv->device, skb->data,
1165 if (dma_mapping_error(priv->device, rx_q->rx_skbuff_dma[i])) {
1166 netdev_err(priv->dev, "%s: DMA mapping error\n", __func__);
1167 dev_kfree_skb_any(skb);
1171 stmmac_set_desc_addr(priv, p, rx_q->rx_skbuff_dma[i]);
1173 if (priv->dma_buf_sz == BUF_SIZE_16KiB)
1174 stmmac_init_desc3(priv, p);
1180 * stmmac_free_rx_buffer - free RX dma buffers
1181 * @priv: private structure
1182 * @queue: RX queue index
1185 static void stmmac_free_rx_buffer(struct stmmac_priv *priv, u32 queue, int i)
1187 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1189 if (rx_q->rx_skbuff[i]) {
1190 dma_unmap_single(priv->device, rx_q->rx_skbuff_dma[i],
1191 priv->dma_buf_sz, DMA_FROM_DEVICE);
1192 dev_kfree_skb_any(rx_q->rx_skbuff[i]);
1194 rx_q->rx_skbuff[i] = NULL;
1198 * stmmac_free_tx_buffer - free RX dma buffers
1199 * @priv: private structure
1200 * @queue: RX queue index
1203 static void stmmac_free_tx_buffer(struct stmmac_priv *priv, u32 queue, int i)
1205 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1207 if (tx_q->tx_skbuff_dma[i].buf) {
1208 if (tx_q->tx_skbuff_dma[i].map_as_page)
1209 dma_unmap_page(priv->device,
1210 tx_q->tx_skbuff_dma[i].buf,
1211 tx_q->tx_skbuff_dma[i].len,
1214 dma_unmap_single(priv->device,
1215 tx_q->tx_skbuff_dma[i].buf,
1216 tx_q->tx_skbuff_dma[i].len,
1220 if (tx_q->tx_skbuff[i]) {
1221 dev_kfree_skb_any(tx_q->tx_skbuff[i]);
1222 tx_q->tx_skbuff[i] = NULL;
1223 tx_q->tx_skbuff_dma[i].buf = 0;
1224 tx_q->tx_skbuff_dma[i].map_as_page = false;
1229 * init_dma_rx_desc_rings - init the RX descriptor rings
1230 * @dev: net device structure
1232 * Description: this function initializes the DMA RX descriptors
1233 * and allocates the socket buffers. It supports the chained and ring
1236 static int init_dma_rx_desc_rings(struct net_device *dev, gfp_t flags)
1238 struct stmmac_priv *priv = netdev_priv(dev);
1239 u32 rx_count = priv->plat->rx_queues_to_use;
1245 bfsize = stmmac_set_16kib_bfsize(priv, dev->mtu);
1249 if (bfsize < BUF_SIZE_16KiB)
1250 bfsize = stmmac_set_bfsize(dev->mtu, priv->dma_buf_sz);
1252 priv->dma_buf_sz = bfsize;
1254 /* RX INITIALIZATION */
1255 netif_dbg(priv, probe, priv->dev,
1256 "SKB addresses:\nskb\t\tskb data\tdma data\n");
1258 for (queue = 0; queue < rx_count; queue++) {
1259 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1261 netif_dbg(priv, probe, priv->dev,
1262 "(%s) dma_rx_phy=0x%08x\n", __func__,
1263 (u32)rx_q->dma_rx_phy);
1265 for (i = 0; i < DMA_RX_SIZE; i++) {
1268 if (priv->extend_desc)
1269 p = &((rx_q->dma_erx + i)->basic);
1271 p = rx_q->dma_rx + i;
1273 ret = stmmac_init_rx_buffers(priv, p, i, flags,
1276 goto err_init_rx_buffers;
1278 netif_dbg(priv, probe, priv->dev, "[%p]\t[%p]\t[%x]\n",
1279 rx_q->rx_skbuff[i], rx_q->rx_skbuff[i]->data,
1280 (unsigned int)rx_q->rx_skbuff_dma[i]);
1284 rx_q->dirty_rx = (unsigned int)(i - DMA_RX_SIZE);
1286 stmmac_clear_rx_descriptors(priv, queue);
1288 /* Setup the chained descriptor addresses */
1289 if (priv->mode == STMMAC_CHAIN_MODE) {
1290 if (priv->extend_desc)
1291 stmmac_mode_init(priv, rx_q->dma_erx,
1292 rx_q->dma_rx_phy, DMA_RX_SIZE, 1);
1294 stmmac_mode_init(priv, rx_q->dma_rx,
1295 rx_q->dma_rx_phy, DMA_RX_SIZE, 0);
1303 err_init_rx_buffers:
1304 while (queue >= 0) {
1306 stmmac_free_rx_buffer(priv, queue, i);
1319 * init_dma_tx_desc_rings - init the TX descriptor rings
1320 * @dev: net device structure.
1321 * Description: this function initializes the DMA TX descriptors
1322 * and allocates the socket buffers. It supports the chained and ring
1325 static int init_dma_tx_desc_rings(struct net_device *dev)
1327 struct stmmac_priv *priv = netdev_priv(dev);
1328 u32 tx_queue_cnt = priv->plat->tx_queues_to_use;
1332 for (queue = 0; queue < tx_queue_cnt; queue++) {
1333 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1335 netif_dbg(priv, probe, priv->dev,
1336 "(%s) dma_tx_phy=0x%08x\n", __func__,
1337 (u32)tx_q->dma_tx_phy);
1339 /* Setup the chained descriptor addresses */
1340 if (priv->mode == STMMAC_CHAIN_MODE) {
1341 if (priv->extend_desc)
1342 stmmac_mode_init(priv, tx_q->dma_etx,
1343 tx_q->dma_tx_phy, DMA_TX_SIZE, 1);
1345 stmmac_mode_init(priv, tx_q->dma_tx,
1346 tx_q->dma_tx_phy, DMA_TX_SIZE, 0);
1349 for (i = 0; i < DMA_TX_SIZE; i++) {
1351 if (priv->extend_desc)
1352 p = &((tx_q->dma_etx + i)->basic);
1354 p = tx_q->dma_tx + i;
1356 stmmac_clear_desc(priv, p);
1358 tx_q->tx_skbuff_dma[i].buf = 0;
1359 tx_q->tx_skbuff_dma[i].map_as_page = false;
1360 tx_q->tx_skbuff_dma[i].len = 0;
1361 tx_q->tx_skbuff_dma[i].last_segment = false;
1362 tx_q->tx_skbuff[i] = NULL;
1369 netdev_tx_reset_queue(netdev_get_tx_queue(priv->dev, queue));
1376 * init_dma_desc_rings - init the RX/TX descriptor rings
1377 * @dev: net device structure
1379 * Description: this function initializes the DMA RX/TX descriptors
1380 * and allocates the socket buffers. It supports the chained and ring
1383 static int init_dma_desc_rings(struct net_device *dev, gfp_t flags)
1385 struct stmmac_priv *priv = netdev_priv(dev);
1388 ret = init_dma_rx_desc_rings(dev, flags);
1392 ret = init_dma_tx_desc_rings(dev);
1394 stmmac_clear_descriptors(priv);
1396 if (netif_msg_hw(priv))
1397 stmmac_display_rings(priv);
1403 * dma_free_rx_skbufs - free RX dma buffers
1404 * @priv: private structure
1405 * @queue: RX queue index
1407 static void dma_free_rx_skbufs(struct stmmac_priv *priv, u32 queue)
1411 for (i = 0; i < DMA_RX_SIZE; i++)
1412 stmmac_free_rx_buffer(priv, queue, i);
1416 * dma_free_tx_skbufs - free TX dma buffers
1417 * @priv: private structure
1418 * @queue: TX queue index
1420 static void dma_free_tx_skbufs(struct stmmac_priv *priv, u32 queue)
1424 for (i = 0; i < DMA_TX_SIZE; i++)
1425 stmmac_free_tx_buffer(priv, queue, i);
1429 * free_dma_rx_desc_resources - free RX dma desc resources
1430 * @priv: private structure
1432 static void free_dma_rx_desc_resources(struct stmmac_priv *priv)
1434 u32 rx_count = priv->plat->rx_queues_to_use;
1437 /* Free RX queue resources */
1438 for (queue = 0; queue < rx_count; queue++) {
1439 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1441 /* Release the DMA RX socket buffers */
1442 dma_free_rx_skbufs(priv, queue);
1444 /* Free DMA regions of consistent memory previously allocated */
1445 if (!priv->extend_desc)
1446 dma_free_coherent(priv->device,
1447 DMA_RX_SIZE * sizeof(struct dma_desc),
1448 rx_q->dma_rx, rx_q->dma_rx_phy);
1450 dma_free_coherent(priv->device, DMA_RX_SIZE *
1451 sizeof(struct dma_extended_desc),
1452 rx_q->dma_erx, rx_q->dma_rx_phy);
1454 kfree(rx_q->rx_skbuff_dma);
1455 kfree(rx_q->rx_skbuff);
1460 * free_dma_tx_desc_resources - free TX dma desc resources
1461 * @priv: private structure
1463 static void free_dma_tx_desc_resources(struct stmmac_priv *priv)
1465 u32 tx_count = priv->plat->tx_queues_to_use;
1468 /* Free TX queue resources */
1469 for (queue = 0; queue < tx_count; queue++) {
1470 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1472 /* Release the DMA TX socket buffers */
1473 dma_free_tx_skbufs(priv, queue);
1475 /* Free DMA regions of consistent memory previously allocated */
1476 if (!priv->extend_desc)
1477 dma_free_coherent(priv->device,
1478 DMA_TX_SIZE * sizeof(struct dma_desc),
1479 tx_q->dma_tx, tx_q->dma_tx_phy);
1481 dma_free_coherent(priv->device, DMA_TX_SIZE *
1482 sizeof(struct dma_extended_desc),
1483 tx_q->dma_etx, tx_q->dma_tx_phy);
1485 kfree(tx_q->tx_skbuff_dma);
1486 kfree(tx_q->tx_skbuff);
1491 * alloc_dma_rx_desc_resources - alloc RX resources.
1492 * @priv: private structure
1493 * Description: according to which descriptor can be used (extend or basic)
1494 * this function allocates the resources for TX and RX paths. In case of
1495 * reception, for example, it pre-allocated the RX socket buffer in order to
1496 * allow zero-copy mechanism.
1498 static int alloc_dma_rx_desc_resources(struct stmmac_priv *priv)
1500 u32 rx_count = priv->plat->rx_queues_to_use;
1504 /* RX queues buffers and DMA */
1505 for (queue = 0; queue < rx_count; queue++) {
1506 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1508 rx_q->queue_index = queue;
1509 rx_q->priv_data = priv;
1511 rx_q->rx_skbuff_dma = kmalloc_array(DMA_RX_SIZE,
1514 if (!rx_q->rx_skbuff_dma)
1517 rx_q->rx_skbuff = kmalloc_array(DMA_RX_SIZE,
1518 sizeof(struct sk_buff *),
1520 if (!rx_q->rx_skbuff)
1523 if (priv->extend_desc) {
1524 rx_q->dma_erx = dma_zalloc_coherent(priv->device,
1534 rx_q->dma_rx = dma_zalloc_coherent(priv->device,
1548 free_dma_rx_desc_resources(priv);
1554 * alloc_dma_tx_desc_resources - alloc TX resources.
1555 * @priv: private structure
1556 * Description: according to which descriptor can be used (extend or basic)
1557 * this function allocates the resources for TX and RX paths. In case of
1558 * reception, for example, it pre-allocated the RX socket buffer in order to
1559 * allow zero-copy mechanism.
1561 static int alloc_dma_tx_desc_resources(struct stmmac_priv *priv)
1563 u32 tx_count = priv->plat->tx_queues_to_use;
1567 /* TX queues buffers and DMA */
1568 for (queue = 0; queue < tx_count; queue++) {
1569 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1571 tx_q->queue_index = queue;
1572 tx_q->priv_data = priv;
1574 tx_q->tx_skbuff_dma = kmalloc_array(DMA_TX_SIZE,
1575 sizeof(*tx_q->tx_skbuff_dma),
1577 if (!tx_q->tx_skbuff_dma)
1580 tx_q->tx_skbuff = kmalloc_array(DMA_TX_SIZE,
1581 sizeof(struct sk_buff *),
1583 if (!tx_q->tx_skbuff)
1586 if (priv->extend_desc) {
1587 tx_q->dma_etx = dma_zalloc_coherent(priv->device,
1596 tx_q->dma_tx = dma_zalloc_coherent(priv->device,
1610 free_dma_tx_desc_resources(priv);
1616 * alloc_dma_desc_resources - alloc TX/RX resources.
1617 * @priv: private structure
1618 * Description: according to which descriptor can be used (extend or basic)
1619 * this function allocates the resources for TX and RX paths. In case of
1620 * reception, for example, it pre-allocated the RX socket buffer in order to
1621 * allow zero-copy mechanism.
1623 static int alloc_dma_desc_resources(struct stmmac_priv *priv)
1626 int ret = alloc_dma_rx_desc_resources(priv);
1631 ret = alloc_dma_tx_desc_resources(priv);
1637 * free_dma_desc_resources - free dma desc resources
1638 * @priv: private structure
1640 static void free_dma_desc_resources(struct stmmac_priv *priv)
1642 /* Release the DMA RX socket buffers */
1643 free_dma_rx_desc_resources(priv);
1645 /* Release the DMA TX socket buffers */
1646 free_dma_tx_desc_resources(priv);
1650 * stmmac_mac_enable_rx_queues - Enable MAC rx queues
1651 * @priv: driver private structure
1652 * Description: It is used for enabling the rx queues in the MAC
1654 static void stmmac_mac_enable_rx_queues(struct stmmac_priv *priv)
1656 u32 rx_queues_count = priv->plat->rx_queues_to_use;
1660 for (queue = 0; queue < rx_queues_count; queue++) {
1661 mode = priv->plat->rx_queues_cfg[queue].mode_to_use;
1662 stmmac_rx_queue_enable(priv, priv->hw, mode, queue);
1667 * stmmac_start_rx_dma - start RX DMA channel
1668 * @priv: driver private structure
1669 * @chan: RX channel index
1671 * This starts a RX DMA channel
1673 static void stmmac_start_rx_dma(struct stmmac_priv *priv, u32 chan)
1675 netdev_dbg(priv->dev, "DMA RX processes started in channel %d\n", chan);
1676 stmmac_start_rx(priv, priv->ioaddr, chan);
1680 * stmmac_start_tx_dma - start TX DMA channel
1681 * @priv: driver private structure
1682 * @chan: TX channel index
1684 * This starts a TX DMA channel
1686 static void stmmac_start_tx_dma(struct stmmac_priv *priv, u32 chan)
1688 netdev_dbg(priv->dev, "DMA TX processes started in channel %d\n", chan);
1689 stmmac_start_tx(priv, priv->ioaddr, chan);
1693 * stmmac_stop_rx_dma - stop RX DMA channel
1694 * @priv: driver private structure
1695 * @chan: RX channel index
1697 * This stops a RX DMA channel
1699 static void stmmac_stop_rx_dma(struct stmmac_priv *priv, u32 chan)
1701 netdev_dbg(priv->dev, "DMA RX processes stopped in channel %d\n", chan);
1702 stmmac_stop_rx(priv, priv->ioaddr, chan);
1706 * stmmac_stop_tx_dma - stop TX DMA channel
1707 * @priv: driver private structure
1708 * @chan: TX channel index
1710 * This stops a TX DMA channel
1712 static void stmmac_stop_tx_dma(struct stmmac_priv *priv, u32 chan)
1714 netdev_dbg(priv->dev, "DMA TX processes stopped in channel %d\n", chan);
1715 stmmac_stop_tx(priv, priv->ioaddr, chan);
1719 * stmmac_start_all_dma - start all RX and TX DMA channels
1720 * @priv: driver private structure
1722 * This starts all the RX and TX DMA channels
1724 static void stmmac_start_all_dma(struct stmmac_priv *priv)
1726 u32 rx_channels_count = priv->plat->rx_queues_to_use;
1727 u32 tx_channels_count = priv->plat->tx_queues_to_use;
1730 for (chan = 0; chan < rx_channels_count; chan++)
1731 stmmac_start_rx_dma(priv, chan);
1733 for (chan = 0; chan < tx_channels_count; chan++)
1734 stmmac_start_tx_dma(priv, chan);
1738 * stmmac_stop_all_dma - stop all RX and TX DMA channels
1739 * @priv: driver private structure
1741 * This stops the RX and TX DMA channels
1743 static void stmmac_stop_all_dma(struct stmmac_priv *priv)
1745 u32 rx_channels_count = priv->plat->rx_queues_to_use;
1746 u32 tx_channels_count = priv->plat->tx_queues_to_use;
1749 for (chan = 0; chan < rx_channels_count; chan++)
1750 stmmac_stop_rx_dma(priv, chan);
1752 for (chan = 0; chan < tx_channels_count; chan++)
1753 stmmac_stop_tx_dma(priv, chan);
1757 * stmmac_dma_operation_mode - HW DMA operation mode
1758 * @priv: driver private structure
1759 * Description: it is used for configuring the DMA operation mode register in
1760 * order to program the tx/rx DMA thresholds or Store-And-Forward mode.
1762 static void stmmac_dma_operation_mode(struct stmmac_priv *priv)
1764 u32 rx_channels_count = priv->plat->rx_queues_to_use;
1765 u32 tx_channels_count = priv->plat->tx_queues_to_use;
1766 int rxfifosz = priv->plat->rx_fifo_size;
1767 int txfifosz = priv->plat->tx_fifo_size;
1774 rxfifosz = priv->dma_cap.rx_fifo_size;
1776 txfifosz = priv->dma_cap.tx_fifo_size;
1778 /* Adjust for real per queue fifo size */
1779 rxfifosz /= rx_channels_count;
1780 txfifosz /= tx_channels_count;
1782 if (priv->plat->force_thresh_dma_mode) {
1785 } else if (priv->plat->force_sf_dma_mode || priv->plat->tx_coe) {
1787 * In case of GMAC, SF mode can be enabled
1788 * to perform the TX COE in HW. This depends on:
1789 * 1) TX COE if actually supported
1790 * 2) There is no bugged Jumbo frame support
1791 * that needs to not insert csum in the TDES.
1793 txmode = SF_DMA_MODE;
1794 rxmode = SF_DMA_MODE;
1795 priv->xstats.threshold = SF_DMA_MODE;
1798 rxmode = SF_DMA_MODE;
1801 /* configure all channels */
1802 for (chan = 0; chan < rx_channels_count; chan++) {
1803 qmode = priv->plat->rx_queues_cfg[chan].mode_to_use;
1805 stmmac_dma_rx_mode(priv, priv->ioaddr, rxmode, chan,
1809 for (chan = 0; chan < tx_channels_count; chan++) {
1810 qmode = priv->plat->tx_queues_cfg[chan].mode_to_use;
1812 stmmac_dma_tx_mode(priv, priv->ioaddr, txmode, chan,
1818 * stmmac_tx_clean - to manage the transmission completion
1819 * @priv: driver private structure
1820 * @queue: TX queue index
1821 * Description: it reclaims the transmit resources after transmission completes.
1823 static void stmmac_tx_clean(struct stmmac_priv *priv, u32 queue)
1825 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1826 unsigned int bytes_compl = 0, pkts_compl = 0;
1829 netif_tx_lock(priv->dev);
1831 priv->xstats.tx_clean++;
1833 entry = tx_q->dirty_tx;
1834 while (entry != tx_q->cur_tx) {
1835 struct sk_buff *skb = tx_q->tx_skbuff[entry];
1839 if (priv->extend_desc)
1840 p = (struct dma_desc *)(tx_q->dma_etx + entry);
1842 p = tx_q->dma_tx + entry;
1844 status = stmmac_tx_status(priv, &priv->dev->stats,
1845 &priv->xstats, p, priv->ioaddr);
1846 /* Check if the descriptor is owned by the DMA */
1847 if (unlikely(status & tx_dma_own))
1850 /* Make sure descriptor fields are read after reading
1855 /* Just consider the last segment and ...*/
1856 if (likely(!(status & tx_not_ls))) {
1857 /* ... verify the status error condition */
1858 if (unlikely(status & tx_err)) {
1859 priv->dev->stats.tx_errors++;
1861 priv->dev->stats.tx_packets++;
1862 priv->xstats.tx_pkt_n++;
1864 stmmac_get_tx_hwtstamp(priv, p, skb);
1867 if (likely(tx_q->tx_skbuff_dma[entry].buf)) {
1868 if (tx_q->tx_skbuff_dma[entry].map_as_page)
1869 dma_unmap_page(priv->device,
1870 tx_q->tx_skbuff_dma[entry].buf,
1871 tx_q->tx_skbuff_dma[entry].len,
1874 dma_unmap_single(priv->device,
1875 tx_q->tx_skbuff_dma[entry].buf,
1876 tx_q->tx_skbuff_dma[entry].len,
1878 tx_q->tx_skbuff_dma[entry].buf = 0;
1879 tx_q->tx_skbuff_dma[entry].len = 0;
1880 tx_q->tx_skbuff_dma[entry].map_as_page = false;
1883 stmmac_clean_desc3(priv, tx_q, p);
1885 tx_q->tx_skbuff_dma[entry].last_segment = false;
1886 tx_q->tx_skbuff_dma[entry].is_jumbo = false;
1888 if (likely(skb != NULL)) {
1890 bytes_compl += skb->len;
1891 dev_consume_skb_any(skb);
1892 tx_q->tx_skbuff[entry] = NULL;
1895 stmmac_release_tx_desc(priv, p, priv->mode);
1897 entry = STMMAC_GET_ENTRY(entry, DMA_TX_SIZE);
1899 tx_q->dirty_tx = entry;
1901 netdev_tx_completed_queue(netdev_get_tx_queue(priv->dev, queue),
1902 pkts_compl, bytes_compl);
1904 if (unlikely(netif_tx_queue_stopped(netdev_get_tx_queue(priv->dev,
1906 stmmac_tx_avail(priv, queue) > STMMAC_TX_THRESH) {
1908 netif_dbg(priv, tx_done, priv->dev,
1909 "%s: restart transmit\n", __func__);
1910 netif_tx_wake_queue(netdev_get_tx_queue(priv->dev, queue));
1913 if ((priv->eee_enabled) && (!priv->tx_path_in_lpi_mode)) {
1914 stmmac_enable_eee_mode(priv);
1915 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer));
1917 netif_tx_unlock(priv->dev);
1921 * stmmac_tx_err - to manage the tx error
1922 * @priv: driver private structure
1923 * @chan: channel index
1924 * Description: it cleans the descriptors and restarts the transmission
1925 * in case of transmission errors.
1927 static void stmmac_tx_err(struct stmmac_priv *priv, u32 chan)
1929 struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan];
1932 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, chan));
1934 stmmac_stop_tx_dma(priv, chan);
1935 dma_free_tx_skbufs(priv, chan);
1936 for (i = 0; i < DMA_TX_SIZE; i++)
1937 if (priv->extend_desc)
1938 stmmac_init_tx_desc(priv, &tx_q->dma_etx[i].basic,
1939 priv->mode, (i == DMA_TX_SIZE - 1));
1941 stmmac_init_tx_desc(priv, &tx_q->dma_tx[i],
1942 priv->mode, (i == DMA_TX_SIZE - 1));
1946 netdev_tx_reset_queue(netdev_get_tx_queue(priv->dev, chan));
1947 stmmac_start_tx_dma(priv, chan);
1949 priv->dev->stats.tx_errors++;
1950 netif_tx_wake_queue(netdev_get_tx_queue(priv->dev, chan));
1954 * stmmac_set_dma_operation_mode - Set DMA operation mode by channel
1955 * @priv: driver private structure
1956 * @txmode: TX operating mode
1957 * @rxmode: RX operating mode
1958 * @chan: channel index
1959 * Description: it is used for configuring of the DMA operation mode in
1960 * runtime in order to program the tx/rx DMA thresholds or Store-And-Forward
1963 static void stmmac_set_dma_operation_mode(struct stmmac_priv *priv, u32 txmode,
1964 u32 rxmode, u32 chan)
1966 u8 rxqmode = priv->plat->rx_queues_cfg[chan].mode_to_use;
1967 u8 txqmode = priv->plat->tx_queues_cfg[chan].mode_to_use;
1968 u32 rx_channels_count = priv->plat->rx_queues_to_use;
1969 u32 tx_channels_count = priv->plat->tx_queues_to_use;
1970 int rxfifosz = priv->plat->rx_fifo_size;
1971 int txfifosz = priv->plat->tx_fifo_size;
1974 rxfifosz = priv->dma_cap.rx_fifo_size;
1976 txfifosz = priv->dma_cap.tx_fifo_size;
1978 /* Adjust for real per queue fifo size */
1979 rxfifosz /= rx_channels_count;
1980 txfifosz /= tx_channels_count;
1982 stmmac_dma_rx_mode(priv, priv->ioaddr, rxmode, chan, rxfifosz, rxqmode);
1983 stmmac_dma_tx_mode(priv, priv->ioaddr, txmode, chan, txfifosz, txqmode);
1986 static bool stmmac_safety_feat_interrupt(struct stmmac_priv *priv)
1990 ret = stmmac_safety_feat_irq_status(priv, priv->dev,
1991 priv->ioaddr, priv->dma_cap.asp, &priv->sstats);
1992 if (ret && (ret != -EINVAL)) {
1993 stmmac_global_err(priv);
2001 * stmmac_dma_interrupt - DMA ISR
2002 * @priv: driver private structure
2003 * Description: this is the DMA ISR. It is called by the main ISR.
2004 * It calls the dwmac dma routine and schedule poll method in case of some
2007 static void stmmac_dma_interrupt(struct stmmac_priv *priv)
2009 u32 tx_channel_count = priv->plat->tx_queues_to_use;
2010 u32 rx_channel_count = priv->plat->rx_queues_to_use;
2011 u32 channels_to_check = tx_channel_count > rx_channel_count ?
2012 tx_channel_count : rx_channel_count;
2014 bool poll_scheduled = false;
2015 int status[max_t(u32, MTL_MAX_TX_QUEUES, MTL_MAX_RX_QUEUES)];
2017 /* Make sure we never check beyond our status buffer. */
2018 if (WARN_ON_ONCE(channels_to_check > ARRAY_SIZE(status)))
2019 channels_to_check = ARRAY_SIZE(status);
2021 /* Each DMA channel can be used for rx and tx simultaneously, yet
2022 * napi_struct is embedded in struct stmmac_rx_queue rather than in a
2023 * stmmac_channel struct.
2024 * Because of this, stmmac_poll currently checks (and possibly wakes)
2025 * all tx queues rather than just a single tx queue.
2027 for (chan = 0; chan < channels_to_check; chan++)
2028 status[chan] = stmmac_dma_interrupt_status(priv, priv->ioaddr,
2029 &priv->xstats, chan);
2031 for (chan = 0; chan < rx_channel_count; chan++) {
2032 if (likely(status[chan] & handle_rx)) {
2033 struct stmmac_rx_queue *rx_q = &priv->rx_queue[chan];
2035 if (likely(napi_schedule_prep(&rx_q->napi))) {
2036 stmmac_disable_dma_irq(priv, priv->ioaddr, chan);
2037 __napi_schedule(&rx_q->napi);
2038 poll_scheduled = true;
2043 /* If we scheduled poll, we already know that tx queues will be checked.
2044 * If we didn't schedule poll, see if any DMA channel (used by tx) has a
2045 * completed transmission, if so, call stmmac_poll (once).
2047 if (!poll_scheduled) {
2048 for (chan = 0; chan < tx_channel_count; chan++) {
2049 if (status[chan] & handle_tx) {
2050 /* It doesn't matter what rx queue we choose
2051 * here. We use 0 since it always exists.
2053 struct stmmac_rx_queue *rx_q =
2056 if (likely(napi_schedule_prep(&rx_q->napi))) {
2057 stmmac_disable_dma_irq(priv,
2058 priv->ioaddr, chan);
2059 __napi_schedule(&rx_q->napi);
2066 for (chan = 0; chan < tx_channel_count; chan++) {
2067 if (unlikely(status[chan] & tx_hard_error_bump_tc)) {
2068 /* Try to bump up the dma threshold on this failure */
2069 if (unlikely(priv->xstats.threshold != SF_DMA_MODE) &&
2072 if (priv->plat->force_thresh_dma_mode)
2073 stmmac_set_dma_operation_mode(priv,
2078 stmmac_set_dma_operation_mode(priv,
2082 priv->xstats.threshold = tc;
2084 } else if (unlikely(status[chan] == tx_hard_error)) {
2085 stmmac_tx_err(priv, chan);
2091 * stmmac_mmc_setup: setup the Mac Management Counters (MMC)
2092 * @priv: driver private structure
2093 * Description: this masks the MMC irq, in fact, the counters are managed in SW.
2095 static void stmmac_mmc_setup(struct stmmac_priv *priv)
2097 unsigned int mode = MMC_CNTRL_RESET_ON_READ | MMC_CNTRL_COUNTER_RESET |
2098 MMC_CNTRL_PRESET | MMC_CNTRL_FULL_HALF_PRESET;
2100 dwmac_mmc_intr_all_mask(priv->mmcaddr);
2102 if (priv->dma_cap.rmon) {
2103 dwmac_mmc_ctrl(priv->mmcaddr, mode);
2104 memset(&priv->mmc, 0, sizeof(struct stmmac_counters));
2106 netdev_info(priv->dev, "No MAC Management Counters available\n");
2110 * stmmac_get_hw_features - get MAC capabilities from the HW cap. register.
2111 * @priv: driver private structure
2113 * new GMAC chip generations have a new register to indicate the
2114 * presence of the optional feature/functions.
2115 * This can be also used to override the value passed through the
2116 * platform and necessary for old MAC10/100 and GMAC chips.
2118 static int stmmac_get_hw_features(struct stmmac_priv *priv)
2120 return stmmac_get_hw_feature(priv, priv->ioaddr, &priv->dma_cap) == 0;
2124 * stmmac_check_ether_addr - check if the MAC addr is valid
2125 * @priv: driver private structure
2127 * it is to verify if the MAC address is valid, in case of failures it
2128 * generates a random MAC address
2130 static void stmmac_check_ether_addr(struct stmmac_priv *priv)
2132 if (!is_valid_ether_addr(priv->dev->dev_addr)) {
2133 stmmac_get_umac_addr(priv, priv->hw, priv->dev->dev_addr, 0);
2134 if (!is_valid_ether_addr(priv->dev->dev_addr))
2135 eth_hw_addr_random(priv->dev);
2136 netdev_info(priv->dev, "device MAC address %pM\n",
2137 priv->dev->dev_addr);
2142 * stmmac_init_dma_engine - DMA init.
2143 * @priv: driver private structure
2145 * It inits the DMA invoking the specific MAC/GMAC callback.
2146 * Some DMA parameters can be passed from the platform;
2147 * in case of these are not passed a default is kept for the MAC or GMAC.
2149 static int stmmac_init_dma_engine(struct stmmac_priv *priv)
2151 u32 rx_channels_count = priv->plat->rx_queues_to_use;
2152 u32 tx_channels_count = priv->plat->tx_queues_to_use;
2153 u32 dma_csr_ch = max(rx_channels_count, tx_channels_count);
2154 struct stmmac_rx_queue *rx_q;
2155 struct stmmac_tx_queue *tx_q;
2160 if (!priv->plat->dma_cfg || !priv->plat->dma_cfg->pbl) {
2161 dev_err(priv->device, "Invalid DMA configuration\n");
2165 if (priv->extend_desc && (priv->mode == STMMAC_RING_MODE))
2168 ret = stmmac_reset(priv, priv->ioaddr);
2170 dev_err(priv->device, "Failed to reset the dma\n");
2174 /* DMA RX Channel Configuration */
2175 for (chan = 0; chan < rx_channels_count; chan++) {
2176 rx_q = &priv->rx_queue[chan];
2178 stmmac_init_rx_chan(priv, priv->ioaddr, priv->plat->dma_cfg,
2179 rx_q->dma_rx_phy, chan);
2181 rx_q->rx_tail_addr = rx_q->dma_rx_phy +
2182 (DMA_RX_SIZE * sizeof(struct dma_desc));
2183 stmmac_set_rx_tail_ptr(priv, priv->ioaddr,
2184 rx_q->rx_tail_addr, chan);
2187 /* DMA TX Channel Configuration */
2188 for (chan = 0; chan < tx_channels_count; chan++) {
2189 tx_q = &priv->tx_queue[chan];
2191 stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg,
2192 tx_q->dma_tx_phy, chan);
2194 tx_q->tx_tail_addr = tx_q->dma_tx_phy +
2195 (DMA_TX_SIZE * sizeof(struct dma_desc));
2196 stmmac_set_tx_tail_ptr(priv, priv->ioaddr,
2197 tx_q->tx_tail_addr, chan);
2200 /* DMA CSR Channel configuration */
2201 for (chan = 0; chan < dma_csr_ch; chan++)
2202 stmmac_init_chan(priv, priv->ioaddr, priv->plat->dma_cfg, chan);
2204 /* DMA Configuration */
2205 stmmac_dma_init(priv, priv->ioaddr, priv->plat->dma_cfg, atds);
2207 if (priv->plat->axi)
2208 stmmac_axi(priv, priv->ioaddr, priv->plat->axi);
2214 * stmmac_tx_timer - mitigation sw timer for tx.
2215 * @data: data pointer
2217 * This is the timer handler to directly invoke the stmmac_tx_clean.
2219 static void stmmac_tx_timer(struct timer_list *t)
2221 struct stmmac_priv *priv = from_timer(priv, t, txtimer);
2222 u32 tx_queues_count = priv->plat->tx_queues_to_use;
2225 /* let's scan all the tx queues */
2226 for (queue = 0; queue < tx_queues_count; queue++)
2227 stmmac_tx_clean(priv, queue);
2231 * stmmac_init_tx_coalesce - init tx mitigation options.
2232 * @priv: driver private structure
2234 * This inits the transmit coalesce parameters: i.e. timer rate,
2235 * timer handler and default threshold used for enabling the
2236 * interrupt on completion bit.
2238 static void stmmac_init_tx_coalesce(struct stmmac_priv *priv)
2240 priv->tx_coal_frames = STMMAC_TX_FRAMES;
2241 priv->tx_coal_timer = STMMAC_COAL_TX_TIMER;
2242 timer_setup(&priv->txtimer, stmmac_tx_timer, 0);
2243 priv->txtimer.expires = STMMAC_COAL_TIMER(priv->tx_coal_timer);
2244 add_timer(&priv->txtimer);
2247 static void stmmac_set_rings_length(struct stmmac_priv *priv)
2249 u32 rx_channels_count = priv->plat->rx_queues_to_use;
2250 u32 tx_channels_count = priv->plat->tx_queues_to_use;
2253 /* set TX ring length */
2254 for (chan = 0; chan < tx_channels_count; chan++)
2255 stmmac_set_tx_ring_len(priv, priv->ioaddr,
2256 (DMA_TX_SIZE - 1), chan);
2258 /* set RX ring length */
2259 for (chan = 0; chan < rx_channels_count; chan++)
2260 stmmac_set_rx_ring_len(priv, priv->ioaddr,
2261 (DMA_RX_SIZE - 1), chan);
2265 * stmmac_set_tx_queue_weight - Set TX queue weight
2266 * @priv: driver private structure
2267 * Description: It is used for setting TX queues weight
2269 static void stmmac_set_tx_queue_weight(struct stmmac_priv *priv)
2271 u32 tx_queues_count = priv->plat->tx_queues_to_use;
2275 for (queue = 0; queue < tx_queues_count; queue++) {
2276 weight = priv->plat->tx_queues_cfg[queue].weight;
2277 stmmac_set_mtl_tx_queue_weight(priv, priv->hw, weight, queue);
2282 * stmmac_configure_cbs - Configure CBS in TX queue
2283 * @priv: driver private structure
2284 * Description: It is used for configuring CBS in AVB TX queues
2286 static void stmmac_configure_cbs(struct stmmac_priv *priv)
2288 u32 tx_queues_count = priv->plat->tx_queues_to_use;
2292 /* queue 0 is reserved for legacy traffic */
2293 for (queue = 1; queue < tx_queues_count; queue++) {
2294 mode_to_use = priv->plat->tx_queues_cfg[queue].mode_to_use;
2295 if (mode_to_use == MTL_QUEUE_DCB)
2298 stmmac_config_cbs(priv, priv->hw,
2299 priv->plat->tx_queues_cfg[queue].send_slope,
2300 priv->plat->tx_queues_cfg[queue].idle_slope,
2301 priv->plat->tx_queues_cfg[queue].high_credit,
2302 priv->plat->tx_queues_cfg[queue].low_credit,
2308 * stmmac_rx_queue_dma_chan_map - Map RX queue to RX dma channel
2309 * @priv: driver private structure
2310 * Description: It is used for mapping RX queues to RX dma channels
2312 static void stmmac_rx_queue_dma_chan_map(struct stmmac_priv *priv)
2314 u32 rx_queues_count = priv->plat->rx_queues_to_use;
2318 for (queue = 0; queue < rx_queues_count; queue++) {
2319 chan = priv->plat->rx_queues_cfg[queue].chan;
2320 stmmac_map_mtl_to_dma(priv, priv->hw, queue, chan);
2325 * stmmac_mac_config_rx_queues_prio - Configure RX Queue priority
2326 * @priv: driver private structure
2327 * Description: It is used for configuring the RX Queue Priority
2329 static void stmmac_mac_config_rx_queues_prio(struct stmmac_priv *priv)
2331 u32 rx_queues_count = priv->plat->rx_queues_to_use;
2335 for (queue = 0; queue < rx_queues_count; queue++) {
2336 if (!priv->plat->rx_queues_cfg[queue].use_prio)
2339 prio = priv->plat->rx_queues_cfg[queue].prio;
2340 stmmac_rx_queue_prio(priv, priv->hw, prio, queue);
2345 * stmmac_mac_config_tx_queues_prio - Configure TX Queue priority
2346 * @priv: driver private structure
2347 * Description: It is used for configuring the TX Queue Priority
2349 static void stmmac_mac_config_tx_queues_prio(struct stmmac_priv *priv)
2351 u32 tx_queues_count = priv->plat->tx_queues_to_use;
2355 for (queue = 0; queue < tx_queues_count; queue++) {
2356 if (!priv->plat->tx_queues_cfg[queue].use_prio)
2359 prio = priv->plat->tx_queues_cfg[queue].prio;
2360 stmmac_tx_queue_prio(priv, priv->hw, prio, queue);
2365 * stmmac_mac_config_rx_queues_routing - Configure RX Queue Routing
2366 * @priv: driver private structure
2367 * Description: It is used for configuring the RX queue routing
2369 static void stmmac_mac_config_rx_queues_routing(struct stmmac_priv *priv)
2371 u32 rx_queues_count = priv->plat->rx_queues_to_use;
2375 for (queue = 0; queue < rx_queues_count; queue++) {
2376 /* no specific packet type routing specified for the queue */
2377 if (priv->plat->rx_queues_cfg[queue].pkt_route == 0x0)
2380 packet = priv->plat->rx_queues_cfg[queue].pkt_route;
2381 stmmac_rx_queue_routing(priv, priv->hw, packet, queue);
2386 * stmmac_mtl_configuration - Configure MTL
2387 * @priv: driver private structure
2388 * Description: It is used for configurring MTL
2390 static void stmmac_mtl_configuration(struct stmmac_priv *priv)
2392 u32 rx_queues_count = priv->plat->rx_queues_to_use;
2393 u32 tx_queues_count = priv->plat->tx_queues_to_use;
2395 if (tx_queues_count > 1)
2396 stmmac_set_tx_queue_weight(priv);
2398 /* Configure MTL RX algorithms */
2399 if (rx_queues_count > 1)
2400 stmmac_prog_mtl_rx_algorithms(priv, priv->hw,
2401 priv->plat->rx_sched_algorithm);
2403 /* Configure MTL TX algorithms */
2404 if (tx_queues_count > 1)
2405 stmmac_prog_mtl_tx_algorithms(priv, priv->hw,
2406 priv->plat->tx_sched_algorithm);
2408 /* Configure CBS in AVB TX queues */
2409 if (tx_queues_count > 1)
2410 stmmac_configure_cbs(priv);
2412 /* Map RX MTL to DMA channels */
2413 stmmac_rx_queue_dma_chan_map(priv);
2415 /* Enable MAC RX Queues */
2416 stmmac_mac_enable_rx_queues(priv);
2418 /* Set RX priorities */
2419 if (rx_queues_count > 1)
2420 stmmac_mac_config_rx_queues_prio(priv);
2422 /* Set TX priorities */
2423 if (tx_queues_count > 1)
2424 stmmac_mac_config_tx_queues_prio(priv);
2426 /* Set RX routing */
2427 if (rx_queues_count > 1)
2428 stmmac_mac_config_rx_queues_routing(priv);
2431 static void stmmac_safety_feat_configuration(struct stmmac_priv *priv)
2433 if (priv->dma_cap.asp) {
2434 netdev_info(priv->dev, "Enabling Safety Features\n");
2435 stmmac_safety_feat_config(priv, priv->ioaddr, priv->dma_cap.asp);
2437 netdev_info(priv->dev, "No Safety Features support found\n");
2442 * stmmac_hw_setup - setup mac in a usable state.
2443 * @dev : pointer to the device structure.
2445 * this is the main function to setup the HW in a usable state because the
2446 * dma engine is reset, the core registers are configured (e.g. AXI,
2447 * Checksum features, timers). The DMA is ready to start receiving and
2450 * 0 on success and an appropriate (-)ve integer as defined in errno.h
2453 static int stmmac_hw_setup(struct net_device *dev, bool init_ptp)
2455 struct stmmac_priv *priv = netdev_priv(dev);
2456 u32 rx_cnt = priv->plat->rx_queues_to_use;
2457 u32 tx_cnt = priv->plat->tx_queues_to_use;
2461 /* DMA initialization and SW reset */
2462 ret = stmmac_init_dma_engine(priv);
2464 netdev_err(priv->dev, "%s: DMA engine initialization failed\n",
2469 /* Copy the MAC addr into the HW */
2470 stmmac_set_umac_addr(priv, priv->hw, dev->dev_addr, 0);
2472 /* PS and related bits will be programmed according to the speed */
2473 if (priv->hw->pcs) {
2474 int speed = priv->plat->mac_port_sel_speed;
2476 if ((speed == SPEED_10) || (speed == SPEED_100) ||
2477 (speed == SPEED_1000)) {
2478 priv->hw->ps = speed;
2480 dev_warn(priv->device, "invalid port speed\n");
2485 /* Initialize the MAC Core */
2486 stmmac_core_init(priv, priv->hw, dev);
2489 stmmac_mtl_configuration(priv);
2491 /* Initialize Safety Features */
2492 stmmac_safety_feat_configuration(priv);
2494 ret = stmmac_rx_ipc(priv, priv->hw);
2496 netdev_warn(priv->dev, "RX IPC Checksum Offload disabled\n");
2497 priv->plat->rx_coe = STMMAC_RX_COE_NONE;
2498 priv->hw->rx_csum = 0;
2501 /* Enable the MAC Rx/Tx */
2502 stmmac_mac_set(priv, priv->ioaddr, true);
2504 /* Set the HW DMA mode and the COE */
2505 stmmac_dma_operation_mode(priv);
2507 stmmac_mmc_setup(priv);
2510 ret = clk_prepare_enable(priv->plat->clk_ptp_ref);
2512 netdev_warn(priv->dev, "failed to enable PTP reference clock: %d\n", ret);
2514 ret = stmmac_init_ptp(priv);
2515 if (ret == -EOPNOTSUPP)
2516 netdev_warn(priv->dev, "PTP not supported by HW\n");
2518 netdev_warn(priv->dev, "PTP init failed\n");
2521 #ifdef CONFIG_DEBUG_FS
2522 ret = stmmac_init_fs(dev);
2524 netdev_warn(priv->dev, "%s: failed debugFS registration\n",
2527 /* Start the ball rolling... */
2528 stmmac_start_all_dma(priv);
2530 priv->tx_lpi_timer = STMMAC_DEFAULT_TWT_LS;
2532 if (priv->use_riwt) {
2533 ret = stmmac_rx_watchdog(priv, priv->ioaddr, MAX_DMA_RIWT, rx_cnt);
2535 priv->rx_riwt = MAX_DMA_RIWT;
2539 stmmac_pcs_ctrl_ane(priv, priv->hw, 1, priv->hw->ps, 0);
2541 /* set TX and RX rings length */
2542 stmmac_set_rings_length(priv);
2546 for (chan = 0; chan < tx_cnt; chan++)
2547 stmmac_enable_tso(priv, priv->ioaddr, 1, chan);
2553 static void stmmac_hw_teardown(struct net_device *dev)
2555 struct stmmac_priv *priv = netdev_priv(dev);
2557 clk_disable_unprepare(priv->plat->clk_ptp_ref);
2561 * stmmac_open - open entry point of the driver
2562 * @dev : pointer to the device structure.
2564 * This function is the open entry point of the driver.
2566 * 0 on success and an appropriate (-)ve integer as defined in errno.h
2569 static int stmmac_open(struct net_device *dev)
2571 struct stmmac_priv *priv = netdev_priv(dev);
2574 stmmac_check_ether_addr(priv);
2576 if (priv->hw->pcs != STMMAC_PCS_RGMII &&
2577 priv->hw->pcs != STMMAC_PCS_TBI &&
2578 priv->hw->pcs != STMMAC_PCS_RTBI) {
2579 ret = stmmac_init_phy(dev);
2581 netdev_err(priv->dev,
2582 "%s: Cannot attach to PHY (error: %d)\n",
2588 /* Extra statistics */
2589 memset(&priv->xstats, 0, sizeof(struct stmmac_extra_stats));
2590 priv->xstats.threshold = tc;
2592 priv->dma_buf_sz = STMMAC_ALIGN(buf_sz);
2593 priv->rx_copybreak = STMMAC_RX_COPYBREAK;
2595 ret = alloc_dma_desc_resources(priv);
2597 netdev_err(priv->dev, "%s: DMA descriptors allocation failed\n",
2599 goto dma_desc_error;
2602 ret = init_dma_desc_rings(dev, GFP_KERNEL);
2604 netdev_err(priv->dev, "%s: DMA descriptors initialization failed\n",
2609 ret = stmmac_hw_setup(dev, true);
2611 netdev_err(priv->dev, "%s: Hw setup failed\n", __func__);
2615 stmmac_init_tx_coalesce(priv);
2618 phy_start(dev->phydev);
2620 /* Request the IRQ lines */
2621 ret = request_irq(dev->irq, stmmac_interrupt,
2622 IRQF_SHARED, dev->name, dev);
2623 if (unlikely(ret < 0)) {
2624 netdev_err(priv->dev,
2625 "%s: ERROR: allocating the IRQ %d (error: %d)\n",
2626 __func__, dev->irq, ret);
2630 /* Request the Wake IRQ in case of another line is used for WoL */
2631 if (priv->wol_irq != dev->irq) {
2632 ret = request_irq(priv->wol_irq, stmmac_interrupt,
2633 IRQF_SHARED, dev->name, dev);
2634 if (unlikely(ret < 0)) {
2635 netdev_err(priv->dev,
2636 "%s: ERROR: allocating the WoL IRQ %d (%d)\n",
2637 __func__, priv->wol_irq, ret);
2642 /* Request the IRQ lines */
2643 if (priv->lpi_irq > 0) {
2644 ret = request_irq(priv->lpi_irq, stmmac_interrupt, IRQF_SHARED,
2646 if (unlikely(ret < 0)) {
2647 netdev_err(priv->dev,
2648 "%s: ERROR: allocating the LPI IRQ %d (%d)\n",
2649 __func__, priv->lpi_irq, ret);
2654 stmmac_enable_all_queues(priv);
2655 stmmac_start_all_queues(priv);
2660 if (priv->wol_irq != dev->irq)
2661 free_irq(priv->wol_irq, dev);
2663 free_irq(dev->irq, dev);
2666 phy_stop(dev->phydev);
2668 del_timer_sync(&priv->txtimer);
2669 stmmac_hw_teardown(dev);
2671 free_dma_desc_resources(priv);
2674 phy_disconnect(dev->phydev);
2680 * stmmac_release - close entry point of the driver
2681 * @dev : device pointer.
2683 * This is the stop entry point of the driver.
2685 static int stmmac_release(struct net_device *dev)
2687 struct stmmac_priv *priv = netdev_priv(dev);
2689 if (priv->eee_enabled)
2690 del_timer_sync(&priv->eee_ctrl_timer);
2692 /* Stop and disconnect the PHY */
2694 phy_stop(dev->phydev);
2695 phy_disconnect(dev->phydev);
2698 stmmac_stop_all_queues(priv);
2700 stmmac_disable_all_queues(priv);
2702 del_timer_sync(&priv->txtimer);
2704 /* Free the IRQ lines */
2705 free_irq(dev->irq, dev);
2706 if (priv->wol_irq != dev->irq)
2707 free_irq(priv->wol_irq, dev);
2708 if (priv->lpi_irq > 0)
2709 free_irq(priv->lpi_irq, dev);
2711 /* Stop TX/RX DMA and clear the descriptors */
2712 stmmac_stop_all_dma(priv);
2714 /* Release and free the Rx/Tx resources */
2715 free_dma_desc_resources(priv);
2717 /* Disable the MAC Rx/Tx */
2718 stmmac_mac_set(priv, priv->ioaddr, false);
2720 netif_carrier_off(dev);
2722 #ifdef CONFIG_DEBUG_FS
2723 stmmac_exit_fs(dev);
2726 stmmac_release_ptp(priv);
2732 * stmmac_tso_allocator - close entry point of the driver
2733 * @priv: driver private structure
2734 * @des: buffer start address
2735 * @total_len: total length to fill in descriptors
2736 * @last_segmant: condition for the last descriptor
2737 * @queue: TX queue index
2739 * This function fills descriptor and request new descriptors according to
2740 * buffer length to fill
2742 static void stmmac_tso_allocator(struct stmmac_priv *priv, unsigned int des,
2743 int total_len, bool last_segment, u32 queue)
2745 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
2746 struct dma_desc *desc;
2750 tmp_len = total_len;
2752 while (tmp_len > 0) {
2753 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, DMA_TX_SIZE);
2754 WARN_ON(tx_q->tx_skbuff[tx_q->cur_tx]);
2755 desc = tx_q->dma_tx + tx_q->cur_tx;
2757 desc->des0 = cpu_to_le32(des + (total_len - tmp_len));
2758 buff_size = tmp_len >= TSO_MAX_BUFF_SIZE ?
2759 TSO_MAX_BUFF_SIZE : tmp_len;
2761 stmmac_prepare_tso_tx_desc(priv, desc, 0, buff_size,
2763 (last_segment) && (tmp_len <= TSO_MAX_BUFF_SIZE),
2766 tmp_len -= TSO_MAX_BUFF_SIZE;
2771 * stmmac_tso_xmit - Tx entry point of the driver for oversized frames (TSO)
2772 * @skb : the socket buffer
2773 * @dev : device pointer
2774 * Description: this is the transmit function that is called on TSO frames
2775 * (support available on GMAC4 and newer chips).
2776 * Diagram below show the ring programming in case of TSO frames:
2780 * | DES0 |---> buffer1 = L2/L3/L4 header
2781 * | DES1 |---> TCP Payload (can continue on next descr...)
2782 * | DES2 |---> buffer 1 and 2 len
2783 * | DES3 |---> must set TSE, TCP hdr len-> [22:19]. TCP payload len [17:0]
2789 * | DES0 | --| Split TCP Payload on Buffers 1 and 2
2791 * | DES2 | --> buffer 1 and 2 len
2795 * mss is fixed when enable tso, so w/o programming the TDES3 ctx field.
2797 static netdev_tx_t stmmac_tso_xmit(struct sk_buff *skb, struct net_device *dev)
2799 struct dma_desc *desc, *first, *mss_desc = NULL;
2800 struct stmmac_priv *priv = netdev_priv(dev);
2801 int nfrags = skb_shinfo(skb)->nr_frags;
2802 u32 queue = skb_get_queue_mapping(skb);
2803 unsigned int first_entry, des;
2804 struct stmmac_tx_queue *tx_q;
2805 int tmp_pay_len = 0;
2810 tx_q = &priv->tx_queue[queue];
2812 /* Compute header lengths */
2813 proto_hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
2815 /* Desc availability based on threshold should be enough safe */
2816 if (unlikely(stmmac_tx_avail(priv, queue) <
2817 (((skb->len - proto_hdr_len) / TSO_MAX_BUFF_SIZE + 1)))) {
2818 if (!netif_tx_queue_stopped(netdev_get_tx_queue(dev, queue))) {
2819 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev,
2821 /* This is a hard error, log it. */
2822 netdev_err(priv->dev,
2823 "%s: Tx Ring full when queue awake\n",
2826 return NETDEV_TX_BUSY;
2829 pay_len = skb_headlen(skb) - proto_hdr_len; /* no frags */
2831 mss = skb_shinfo(skb)->gso_size;
2833 /* set new MSS value if needed */
2834 if (mss != tx_q->mss) {
2835 mss_desc = tx_q->dma_tx + tx_q->cur_tx;
2836 stmmac_set_mss(priv, mss_desc, mss);
2838 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, DMA_TX_SIZE);
2839 WARN_ON(tx_q->tx_skbuff[tx_q->cur_tx]);
2842 if (netif_msg_tx_queued(priv)) {
2843 pr_info("%s: tcphdrlen %d, hdr_len %d, pay_len %d, mss %d\n",
2844 __func__, tcp_hdrlen(skb), proto_hdr_len, pay_len, mss);
2845 pr_info("\tskb->len %d, skb->data_len %d\n", skb->len,
2849 first_entry = tx_q->cur_tx;
2850 WARN_ON(tx_q->tx_skbuff[first_entry]);
2852 desc = tx_q->dma_tx + first_entry;
2855 /* first descriptor: fill Headers on Buf1 */
2856 des = dma_map_single(priv->device, skb->data, skb_headlen(skb),
2858 if (dma_mapping_error(priv->device, des))
2861 tx_q->tx_skbuff_dma[first_entry].buf = des;
2862 tx_q->tx_skbuff_dma[first_entry].len = skb_headlen(skb);
2864 first->des0 = cpu_to_le32(des);
2866 /* Fill start of payload in buff2 of first descriptor */
2868 first->des1 = cpu_to_le32(des + proto_hdr_len);
2870 /* If needed take extra descriptors to fill the remaining payload */
2871 tmp_pay_len = pay_len - TSO_MAX_BUFF_SIZE;
2873 stmmac_tso_allocator(priv, des, tmp_pay_len, (nfrags == 0), queue);
2875 /* Prepare fragments */
2876 for (i = 0; i < nfrags; i++) {
2877 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2879 des = skb_frag_dma_map(priv->device, frag, 0,
2880 skb_frag_size(frag),
2882 if (dma_mapping_error(priv->device, des))
2885 stmmac_tso_allocator(priv, des, skb_frag_size(frag),
2886 (i == nfrags - 1), queue);
2888 tx_q->tx_skbuff_dma[tx_q->cur_tx].buf = des;
2889 tx_q->tx_skbuff_dma[tx_q->cur_tx].len = skb_frag_size(frag);
2890 tx_q->tx_skbuff_dma[tx_q->cur_tx].map_as_page = true;
2893 tx_q->tx_skbuff_dma[tx_q->cur_tx].last_segment = true;
2895 /* Only the last descriptor gets to point to the skb. */
2896 tx_q->tx_skbuff[tx_q->cur_tx] = skb;
2898 /* We've used all descriptors we need for this skb, however,
2899 * advance cur_tx so that it references a fresh descriptor.
2900 * ndo_start_xmit will fill this descriptor the next time it's
2901 * called and stmmac_tx_clean may clean up to this descriptor.
2903 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, DMA_TX_SIZE);
2905 if (unlikely(stmmac_tx_avail(priv, queue) <= (MAX_SKB_FRAGS + 1))) {
2906 netif_dbg(priv, hw, priv->dev, "%s: stop transmitted packets\n",
2908 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, queue));
2911 dev->stats.tx_bytes += skb->len;
2912 priv->xstats.tx_tso_frames++;
2913 priv->xstats.tx_tso_nfrags += nfrags;
2915 /* Manage tx mitigation */
2916 priv->tx_count_frames += nfrags + 1;
2917 if (likely(priv->tx_coal_frames > priv->tx_count_frames)) {
2918 mod_timer(&priv->txtimer,
2919 STMMAC_COAL_TIMER(priv->tx_coal_timer));
2921 priv->tx_count_frames = 0;
2922 stmmac_set_tx_ic(priv, desc);
2923 priv->xstats.tx_set_ic_bit++;
2926 skb_tx_timestamp(skb);
2928 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
2929 priv->hwts_tx_en)) {
2930 /* declare that device is doing timestamping */
2931 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
2932 stmmac_enable_tx_timestamp(priv, first);
2935 /* Complete the first descriptor before granting the DMA */
2936 stmmac_prepare_tso_tx_desc(priv, first, 1,
2939 1, tx_q->tx_skbuff_dma[first_entry].last_segment,
2940 tcp_hdrlen(skb) / 4, (skb->len - proto_hdr_len));
2942 /* If context desc is used to change MSS */
2944 /* Make sure that first descriptor has been completely
2945 * written, including its own bit. This is because MSS is
2946 * actually before first descriptor, so we need to make
2947 * sure that MSS's own bit is the last thing written.
2950 stmmac_set_tx_owner(priv, mss_desc);
2953 /* The own bit must be the latest setting done when prepare the
2954 * descriptor and then barrier is needed to make sure that
2955 * all is coherent before granting the DMA engine.
2959 if (netif_msg_pktdata(priv)) {
2960 pr_info("%s: curr=%d dirty=%d f=%d, e=%d, f_p=%p, nfrags %d\n",
2961 __func__, tx_q->cur_tx, tx_q->dirty_tx, first_entry,
2962 tx_q->cur_tx, first, nfrags);
2964 stmmac_display_ring(priv, (void *)tx_q->dma_tx, DMA_TX_SIZE, 0);
2966 pr_info(">>> frame to be transmitted: ");
2967 print_pkt(skb->data, skb_headlen(skb));
2970 netdev_tx_sent_queue(netdev_get_tx_queue(dev, queue), skb->len);
2972 stmmac_set_tx_tail_ptr(priv, priv->ioaddr, tx_q->tx_tail_addr, queue);
2974 return NETDEV_TX_OK;
2977 dev_err(priv->device, "Tx dma map failed\n");
2979 priv->dev->stats.tx_dropped++;
2980 return NETDEV_TX_OK;
2984 * stmmac_xmit - Tx entry point of the driver
2985 * @skb : the socket buffer
2986 * @dev : device pointer
2987 * Description : this is the tx entry point of the driver.
2988 * It programs the chain or the ring and supports oversized frames
2991 static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev)
2993 struct stmmac_priv *priv = netdev_priv(dev);
2994 unsigned int nopaged_len = skb_headlen(skb);
2995 int i, csum_insertion = 0, is_jumbo = 0;
2996 u32 queue = skb_get_queue_mapping(skb);
2997 int nfrags = skb_shinfo(skb)->nr_frags;
2999 unsigned int first_entry;
3000 struct dma_desc *desc, *first;
3001 struct stmmac_tx_queue *tx_q;
3002 unsigned int enh_desc;
3005 tx_q = &priv->tx_queue[queue];
3007 /* Manage oversized TCP frames for GMAC4 device */
3008 if (skb_is_gso(skb) && priv->tso) {
3009 if (skb_shinfo(skb)->gso_type & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6))
3010 return stmmac_tso_xmit(skb, dev);
3013 if (unlikely(stmmac_tx_avail(priv, queue) < nfrags + 1)) {
3014 if (!netif_tx_queue_stopped(netdev_get_tx_queue(dev, queue))) {
3015 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev,
3017 /* This is a hard error, log it. */
3018 netdev_err(priv->dev,
3019 "%s: Tx Ring full when queue awake\n",
3022 return NETDEV_TX_BUSY;
3025 if (priv->tx_path_in_lpi_mode)
3026 stmmac_disable_eee_mode(priv);
3028 entry = tx_q->cur_tx;
3029 first_entry = entry;
3030 WARN_ON(tx_q->tx_skbuff[first_entry]);
3032 csum_insertion = (skb->ip_summed == CHECKSUM_PARTIAL);
3034 if (likely(priv->extend_desc))
3035 desc = (struct dma_desc *)(tx_q->dma_etx + entry);
3037 desc = tx_q->dma_tx + entry;
3041 enh_desc = priv->plat->enh_desc;
3042 /* To program the descriptors according to the size of the frame */
3044 is_jumbo = stmmac_is_jumbo_frm(priv, skb->len, enh_desc);
3046 if (unlikely(is_jumbo)) {
3047 entry = stmmac_jumbo_frm(priv, tx_q, skb, csum_insertion);
3048 if (unlikely(entry < 0) && (entry != -EINVAL))
3052 for (i = 0; i < nfrags; i++) {
3053 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
3054 int len = skb_frag_size(frag);
3055 bool last_segment = (i == (nfrags - 1));
3057 entry = STMMAC_GET_ENTRY(entry, DMA_TX_SIZE);
3058 WARN_ON(tx_q->tx_skbuff[entry]);
3060 if (likely(priv->extend_desc))
3061 desc = (struct dma_desc *)(tx_q->dma_etx + entry);
3063 desc = tx_q->dma_tx + entry;
3065 des = skb_frag_dma_map(priv->device, frag, 0, len,
3067 if (dma_mapping_error(priv->device, des))
3068 goto dma_map_err; /* should reuse desc w/o issues */
3070 tx_q->tx_skbuff_dma[entry].buf = des;
3072 stmmac_set_desc_addr(priv, desc, des);
3074 tx_q->tx_skbuff_dma[entry].map_as_page = true;
3075 tx_q->tx_skbuff_dma[entry].len = len;
3076 tx_q->tx_skbuff_dma[entry].last_segment = last_segment;
3078 /* Prepare the descriptor and set the own bit too */
3079 stmmac_prepare_tx_desc(priv, desc, 0, len, csum_insertion,
3080 priv->mode, 1, last_segment, skb->len);
3083 /* Only the last descriptor gets to point to the skb. */
3084 tx_q->tx_skbuff[entry] = skb;
3086 /* We've used all descriptors we need for this skb, however,
3087 * advance cur_tx so that it references a fresh descriptor.
3088 * ndo_start_xmit will fill this descriptor the next time it's
3089 * called and stmmac_tx_clean may clean up to this descriptor.
3091 entry = STMMAC_GET_ENTRY(entry, DMA_TX_SIZE);
3092 tx_q->cur_tx = entry;
3094 if (netif_msg_pktdata(priv)) {
3097 netdev_dbg(priv->dev,
3098 "%s: curr=%d dirty=%d f=%d, e=%d, first=%p, nfrags=%d",
3099 __func__, tx_q->cur_tx, tx_q->dirty_tx, first_entry,
3100 entry, first, nfrags);
3102 if (priv->extend_desc)
3103 tx_head = (void *)tx_q->dma_etx;
3105 tx_head = (void *)tx_q->dma_tx;
3107 stmmac_display_ring(priv, tx_head, DMA_TX_SIZE, false);
3109 netdev_dbg(priv->dev, ">>> frame to be transmitted: ");
3110 print_pkt(skb->data, skb->len);
3113 if (unlikely(stmmac_tx_avail(priv, queue) <= (MAX_SKB_FRAGS + 1))) {
3114 netif_dbg(priv, hw, priv->dev, "%s: stop transmitted packets\n",
3116 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, queue));
3119 dev->stats.tx_bytes += skb->len;
3121 /* According to the coalesce parameter the IC bit for the latest
3122 * segment is reset and the timer re-started to clean the tx status.
3123 * This approach takes care about the fragments: desc is the first
3124 * element in case of no SG.
3126 priv->tx_count_frames += nfrags + 1;
3127 if (likely(priv->tx_coal_frames > priv->tx_count_frames) &&
3128 !priv->tx_timer_armed) {
3129 mod_timer(&priv->txtimer,
3130 STMMAC_COAL_TIMER(priv->tx_coal_timer));
3131 priv->tx_timer_armed = true;
3133 priv->tx_count_frames = 0;
3134 stmmac_set_tx_ic(priv, desc);
3135 priv->xstats.tx_set_ic_bit++;
3136 priv->tx_timer_armed = false;
3139 skb_tx_timestamp(skb);
3141 /* Ready to fill the first descriptor and set the OWN bit w/o any
3142 * problems because all the descriptors are actually ready to be
3143 * passed to the DMA engine.
3145 if (likely(!is_jumbo)) {
3146 bool last_segment = (nfrags == 0);
3148 des = dma_map_single(priv->device, skb->data,
3149 nopaged_len, DMA_TO_DEVICE);
3150 if (dma_mapping_error(priv->device, des))
3153 tx_q->tx_skbuff_dma[first_entry].buf = des;
3155 stmmac_set_desc_addr(priv, first, des);
3157 tx_q->tx_skbuff_dma[first_entry].len = nopaged_len;
3158 tx_q->tx_skbuff_dma[first_entry].last_segment = last_segment;
3160 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
3161 priv->hwts_tx_en)) {
3162 /* declare that device is doing timestamping */
3163 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
3164 stmmac_enable_tx_timestamp(priv, first);
3167 /* Prepare the first descriptor setting the OWN bit too */
3168 stmmac_prepare_tx_desc(priv, first, 1, nopaged_len,
3169 csum_insertion, priv->mode, 1, last_segment,
3172 /* The own bit must be the latest setting done when prepare the
3173 * descriptor and then barrier is needed to make sure that
3174 * all is coherent before granting the DMA engine.
3179 netdev_tx_sent_queue(netdev_get_tx_queue(dev, queue), skb->len);
3181 stmmac_enable_dma_transmission(priv, priv->ioaddr);
3182 stmmac_set_tx_tail_ptr(priv, priv->ioaddr, tx_q->tx_tail_addr, queue);
3184 return NETDEV_TX_OK;
3187 netdev_err(priv->dev, "Tx DMA map failed\n");
3189 priv->dev->stats.tx_dropped++;
3190 return NETDEV_TX_OK;
3193 static void stmmac_rx_vlan(struct net_device *dev, struct sk_buff *skb)
3195 struct vlan_ethhdr *veth;
3199 veth = (struct vlan_ethhdr *)skb->data;
3200 vlan_proto = veth->h_vlan_proto;
3202 if ((vlan_proto == htons(ETH_P_8021Q) &&
3203 dev->features & NETIF_F_HW_VLAN_CTAG_RX) ||
3204 (vlan_proto == htons(ETH_P_8021AD) &&
3205 dev->features & NETIF_F_HW_VLAN_STAG_RX)) {
3206 /* pop the vlan tag */
3207 vlanid = ntohs(veth->h_vlan_TCI);
3208 memmove(skb->data + VLAN_HLEN, veth, ETH_ALEN * 2);
3209 skb_pull(skb, VLAN_HLEN);
3210 __vlan_hwaccel_put_tag(skb, vlan_proto, vlanid);
3215 static inline int stmmac_rx_threshold_count(struct stmmac_rx_queue *rx_q)
3217 if (rx_q->rx_zeroc_thresh < STMMAC_RX_THRESH)
3224 * stmmac_rx_refill - refill used skb preallocated buffers
3225 * @priv: driver private structure
3226 * @queue: RX queue index
3227 * Description : this is to reallocate the skb for the reception process
3228 * that is based on zero-copy.
3230 static inline void stmmac_rx_refill(struct stmmac_priv *priv, u32 queue)
3232 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
3233 int dirty = stmmac_rx_dirty(priv, queue);
3234 unsigned int entry = rx_q->dirty_rx;
3236 int bfsize = priv->dma_buf_sz;
3238 while (dirty-- > 0) {
3241 if (priv->extend_desc)
3242 p = (struct dma_desc *)(rx_q->dma_erx + entry);
3244 p = rx_q->dma_rx + entry;
3246 if (likely(!rx_q->rx_skbuff[entry])) {
3247 struct sk_buff *skb;
3249 skb = netdev_alloc_skb_ip_align(priv->dev, bfsize);
3250 if (unlikely(!skb)) {
3251 /* so for a while no zero-copy! */
3252 rx_q->rx_zeroc_thresh = STMMAC_RX_THRESH;
3253 if (unlikely(net_ratelimit()))
3254 dev_err(priv->device,
3255 "fail to alloc skb entry %d\n",
3260 rx_q->rx_skbuff[entry] = skb;
3261 rx_q->rx_skbuff_dma[entry] =
3262 dma_map_single(priv->device, skb->data, bfsize,
3264 if (dma_mapping_error(priv->device,
3265 rx_q->rx_skbuff_dma[entry])) {
3266 netdev_err(priv->dev, "Rx DMA map failed\n");
3271 stmmac_set_desc_addr(priv, p, rx_q->rx_skbuff_dma[entry]);
3272 stmmac_refill_desc3(priv, rx_q, p);
3274 if (rx_q->rx_zeroc_thresh > 0)
3275 rx_q->rx_zeroc_thresh--;
3277 netif_dbg(priv, rx_status, priv->dev,
3278 "refill entry #%d\n", entry);
3282 stmmac_set_rx_owner(priv, p, priv->use_riwt);
3286 entry = STMMAC_GET_ENTRY(entry, DMA_RX_SIZE);
3288 rx_q->dirty_rx = entry;
3292 * stmmac_rx - manage the receive process
3293 * @priv: driver private structure
3294 * @limit: napi bugget
3295 * @queue: RX queue index.
3296 * Description : this the function called by the napi poll method.
3297 * It gets all the frames inside the ring.
3299 static int stmmac_rx(struct stmmac_priv *priv, int limit, u32 queue)
3301 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
3302 unsigned int entry = rx_q->cur_rx;
3303 int coe = priv->hw->rx_csum;
3304 unsigned int next_entry;
3305 unsigned int count = 0;
3307 if (netif_msg_rx_status(priv)) {
3310 netdev_dbg(priv->dev, "%s: descriptor ring:\n", __func__);
3311 if (priv->extend_desc)
3312 rx_head = (void *)rx_q->dma_erx;
3314 rx_head = (void *)rx_q->dma_rx;
3316 stmmac_display_ring(priv, rx_head, DMA_RX_SIZE, true);
3318 while (count < limit) {
3321 struct dma_desc *np;
3323 if (priv->extend_desc)
3324 p = (struct dma_desc *)(rx_q->dma_erx + entry);
3326 p = rx_q->dma_rx + entry;
3328 /* read the status of the incoming frame */
3329 status = stmmac_rx_status(priv, &priv->dev->stats,
3331 /* check if managed by the DMA otherwise go ahead */
3332 if (unlikely(status & dma_own))
3337 rx_q->cur_rx = STMMAC_GET_ENTRY(rx_q->cur_rx, DMA_RX_SIZE);
3338 next_entry = rx_q->cur_rx;
3340 if (priv->extend_desc)
3341 np = (struct dma_desc *)(rx_q->dma_erx + next_entry);
3343 np = rx_q->dma_rx + next_entry;
3347 if (priv->extend_desc)
3348 stmmac_rx_extended_status(priv, &priv->dev->stats,
3349 &priv->xstats, rx_q->dma_erx + entry);
3350 if (unlikely(status == discard_frame)) {
3351 priv->dev->stats.rx_errors++;
3352 if (priv->hwts_rx_en && !priv->extend_desc) {
3353 /* DESC2 & DESC3 will be overwritten by device
3354 * with timestamp value, hence reinitialize
3355 * them in stmmac_rx_refill() function so that
3356 * device can reuse it.
3358 dev_kfree_skb_any(rx_q->rx_skbuff[entry]);
3359 rx_q->rx_skbuff[entry] = NULL;
3360 dma_unmap_single(priv->device,
3361 rx_q->rx_skbuff_dma[entry],
3366 struct sk_buff *skb;
3370 stmmac_get_desc_addr(priv, p, &des);
3371 frame_len = stmmac_get_rx_frame_len(priv, p, coe);
3373 /* If frame length is greater than skb buffer size
3374 * (preallocated during init) then the packet is
3377 if (frame_len > priv->dma_buf_sz) {
3378 netdev_err(priv->dev,
3379 "len %d larger than size (%d)\n",
3380 frame_len, priv->dma_buf_sz);
3381 priv->dev->stats.rx_length_errors++;
3385 /* ACS is set; GMAC core strips PAD/FCS for IEEE 802.3
3386 * Type frames (LLC/LLC-SNAP)
3388 * llc_snap is never checked in GMAC >= 4, so this ACS
3389 * feature is always disabled and packets need to be
3390 * stripped manually.
3392 if (unlikely(priv->synopsys_id >= DWMAC_CORE_4_00) ||
3393 unlikely(status != llc_snap))
3394 frame_len -= ETH_FCS_LEN;
3396 if (netif_msg_rx_status(priv)) {
3397 netdev_dbg(priv->dev, "\tdesc: %p [entry %d] buff=0x%x\n",
3399 netdev_dbg(priv->dev, "frame size %d, COE: %d\n",
3403 /* The zero-copy is always used for all the sizes
3404 * in case of GMAC4 because it needs
3405 * to refill the used descriptors, always.
3407 if (unlikely(!priv->plat->has_gmac4 &&
3408 ((frame_len < priv->rx_copybreak) ||
3409 stmmac_rx_threshold_count(rx_q)))) {
3410 skb = netdev_alloc_skb_ip_align(priv->dev,
3412 if (unlikely(!skb)) {
3413 if (net_ratelimit())
3414 dev_warn(priv->device,
3415 "packet dropped\n");
3416 priv->dev->stats.rx_dropped++;
3420 dma_sync_single_for_cpu(priv->device,
3424 skb_copy_to_linear_data(skb,
3426 rx_skbuff[entry]->data,
3429 skb_put(skb, frame_len);
3430 dma_sync_single_for_device(priv->device,
3435 skb = rx_q->rx_skbuff[entry];
3436 if (unlikely(!skb)) {
3437 netdev_err(priv->dev,
3438 "%s: Inconsistent Rx chain\n",
3440 priv->dev->stats.rx_dropped++;
3443 prefetch(skb->data - NET_IP_ALIGN);
3444 rx_q->rx_skbuff[entry] = NULL;
3445 rx_q->rx_zeroc_thresh++;
3447 skb_put(skb, frame_len);
3448 dma_unmap_single(priv->device,
3449 rx_q->rx_skbuff_dma[entry],
3454 if (netif_msg_pktdata(priv)) {
3455 netdev_dbg(priv->dev, "frame received (%dbytes)",
3457 print_pkt(skb->data, frame_len);
3460 stmmac_get_rx_hwtstamp(priv, p, np, skb);
3462 stmmac_rx_vlan(priv->dev, skb);
3464 skb->protocol = eth_type_trans(skb, priv->dev);
3467 skb_checksum_none_assert(skb);
3469 skb->ip_summed = CHECKSUM_UNNECESSARY;
3471 napi_gro_receive(&rx_q->napi, skb);
3473 priv->dev->stats.rx_packets++;
3474 priv->dev->stats.rx_bytes += frame_len;
3479 stmmac_rx_refill(priv, queue);
3481 priv->xstats.rx_pkt_n += count;
3487 * stmmac_poll - stmmac poll method (NAPI)
3488 * @napi : pointer to the napi structure.
3489 * @budget : maximum number of packets that the current CPU can receive from
3492 * To look at the incoming frames and clear the tx resources.
3494 static int stmmac_poll(struct napi_struct *napi, int budget)
3496 struct stmmac_rx_queue *rx_q =
3497 container_of(napi, struct stmmac_rx_queue, napi);
3498 struct stmmac_priv *priv = rx_q->priv_data;
3499 u32 tx_count = priv->plat->tx_queues_to_use;
3500 u32 chan = rx_q->queue_index;
3504 priv->xstats.napi_poll++;
3506 /* check all the queues */
3507 for (queue = 0; queue < tx_count; queue++)
3508 stmmac_tx_clean(priv, queue);
3510 work_done = stmmac_rx(priv, budget, rx_q->queue_index);
3511 if (work_done < budget) {
3512 napi_complete_done(napi, work_done);
3513 stmmac_enable_dma_irq(priv, priv->ioaddr, chan);
3520 * @dev : Pointer to net device structure
3521 * Description: this function is called when a packet transmission fails to
3522 * complete within a reasonable time. The driver will mark the error in the
3523 * netdev structure and arrange for the device to be reset to a sane state
3524 * in order to transmit a new packet.
3526 static void stmmac_tx_timeout(struct net_device *dev)
3528 struct stmmac_priv *priv = netdev_priv(dev);
3530 stmmac_global_err(priv);
3534 * stmmac_set_rx_mode - entry point for multicast addressing
3535 * @dev : pointer to the device structure
3537 * This function is a driver entry point which gets called by the kernel
3538 * whenever multicast addresses must be enabled/disabled.
3542 static void stmmac_set_rx_mode(struct net_device *dev)
3544 struct stmmac_priv *priv = netdev_priv(dev);
3546 stmmac_set_filter(priv, priv->hw, dev);
3550 * stmmac_change_mtu - entry point to change MTU size for the device.
3551 * @dev : device pointer.
3552 * @new_mtu : the new MTU size for the device.
3553 * Description: the Maximum Transfer Unit (MTU) is used by the network layer
3554 * to drive packet transmission. Ethernet has an MTU of 1500 octets
3555 * (ETH_DATA_LEN). This value can be changed with ifconfig.
3557 * 0 on success and an appropriate (-)ve integer as defined in errno.h
3560 static int stmmac_change_mtu(struct net_device *dev, int new_mtu)
3562 struct stmmac_priv *priv = netdev_priv(dev);
3564 if (netif_running(dev)) {
3565 netdev_err(priv->dev, "must be stopped to change its MTU\n");
3571 netdev_update_features(dev);
3576 static netdev_features_t stmmac_fix_features(struct net_device *dev,
3577 netdev_features_t features)
3579 struct stmmac_priv *priv = netdev_priv(dev);
3581 if (priv->plat->rx_coe == STMMAC_RX_COE_NONE)
3582 features &= ~NETIF_F_RXCSUM;
3584 if (!priv->plat->tx_coe)
3585 features &= ~NETIF_F_CSUM_MASK;
3587 /* Some GMAC devices have a bugged Jumbo frame support that
3588 * needs to have the Tx COE disabled for oversized frames
3589 * (due to limited buffer sizes). In this case we disable
3590 * the TX csum insertion in the TDES and not use SF.
3592 if (priv->plat->bugged_jumbo && (dev->mtu > ETH_DATA_LEN))
3593 features &= ~NETIF_F_CSUM_MASK;
3595 /* Disable tso if asked by ethtool */
3596 if ((priv->plat->tso_en) && (priv->dma_cap.tsoen)) {
3597 if (features & NETIF_F_TSO)
3606 static int stmmac_set_features(struct net_device *netdev,
3607 netdev_features_t features)
3609 struct stmmac_priv *priv = netdev_priv(netdev);
3611 /* Keep the COE Type in case of csum is supporting */
3612 if (features & NETIF_F_RXCSUM)
3613 priv->hw->rx_csum = priv->plat->rx_coe;
3615 priv->hw->rx_csum = 0;
3616 /* No check needed because rx_coe has been set before and it will be
3617 * fixed in case of issue.
3619 stmmac_rx_ipc(priv, priv->hw);
3625 * stmmac_interrupt - main ISR
3626 * @irq: interrupt number.
3627 * @dev_id: to pass the net device pointer.
3628 * Description: this is the main driver interrupt service routine.
3630 * o DMA service routine (to manage incoming frame reception and transmission
3632 * o Core interrupts to manage: remote wake-up, management counter, LPI
3635 static irqreturn_t stmmac_interrupt(int irq, void *dev_id)
3637 struct net_device *dev = (struct net_device *)dev_id;
3638 struct stmmac_priv *priv = netdev_priv(dev);
3639 u32 rx_cnt = priv->plat->rx_queues_to_use;
3640 u32 tx_cnt = priv->plat->tx_queues_to_use;
3644 queues_count = (rx_cnt > tx_cnt) ? rx_cnt : tx_cnt;
3647 pm_wakeup_event(priv->device, 0);
3649 if (unlikely(!dev)) {
3650 netdev_err(priv->dev, "%s: invalid dev pointer\n", __func__);
3654 /* Check if adapter is up */
3655 if (test_bit(STMMAC_DOWN, &priv->state))
3657 /* Check if a fatal error happened */
3658 if (stmmac_safety_feat_interrupt(priv))
3661 /* To handle GMAC own interrupts */
3662 if ((priv->plat->has_gmac) || (priv->plat->has_gmac4)) {
3663 int status = stmmac_host_irq_status(priv, priv->hw, &priv->xstats);
3666 if (unlikely(status)) {
3667 /* For LPI we need to save the tx status */
3668 if (status & CORE_IRQ_TX_PATH_IN_LPI_MODE)
3669 priv->tx_path_in_lpi_mode = true;
3670 if (status & CORE_IRQ_TX_PATH_EXIT_LPI_MODE)
3671 priv->tx_path_in_lpi_mode = false;
3674 for (queue = 0; queue < queues_count; queue++) {
3675 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
3677 mtl_status = stmmac_host_mtl_irq_status(priv, priv->hw,
3679 if (mtl_status != -EINVAL)
3680 status |= mtl_status;
3682 if (status & CORE_IRQ_MTL_RX_OVERFLOW)
3683 stmmac_set_rx_tail_ptr(priv, priv->ioaddr,
3688 /* PCS link status */
3689 if (priv->hw->pcs) {
3690 if (priv->xstats.pcs_link)
3691 netif_carrier_on(dev);
3693 netif_carrier_off(dev);
3697 /* To handle DMA interrupts */
3698 stmmac_dma_interrupt(priv);
3703 #ifdef CONFIG_NET_POLL_CONTROLLER
3704 /* Polling receive - used by NETCONSOLE and other diagnostic tools
3705 * to allow network I/O with interrupts disabled.
3707 static void stmmac_poll_controller(struct net_device *dev)
3709 disable_irq(dev->irq);
3710 stmmac_interrupt(dev->irq, dev);
3711 enable_irq(dev->irq);
3716 * stmmac_ioctl - Entry point for the Ioctl
3717 * @dev: Device pointer.
3718 * @rq: An IOCTL specefic structure, that can contain a pointer to
3719 * a proprietary structure used to pass information to the driver.
3720 * @cmd: IOCTL command
3722 * Currently it supports the phy_mii_ioctl(...) and HW time stamping.
3724 static int stmmac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
3726 int ret = -EOPNOTSUPP;
3728 if (!netif_running(dev))
3737 ret = phy_mii_ioctl(dev->phydev, rq, cmd);
3740 ret = stmmac_hwtstamp_ioctl(dev, rq);
3749 static int stmmac_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
3752 struct stmmac_priv *priv = cb_priv;
3753 int ret = -EOPNOTSUPP;
3755 stmmac_disable_all_queues(priv);
3758 case TC_SETUP_CLSU32:
3759 if (tc_cls_can_offload_and_chain0(priv->dev, type_data))
3760 ret = stmmac_tc_setup_cls_u32(priv, priv, type_data);
3766 stmmac_enable_all_queues(priv);
3770 static int stmmac_setup_tc_block(struct stmmac_priv *priv,
3771 struct tc_block_offload *f)
3773 if (f->binder_type != TCF_BLOCK_BINDER_TYPE_CLSACT_INGRESS)
3776 switch (f->command) {
3778 return tcf_block_cb_register(f->block, stmmac_setup_tc_block_cb,
3779 priv, priv, f->extack);
3780 case TC_BLOCK_UNBIND:
3781 tcf_block_cb_unregister(f->block, stmmac_setup_tc_block_cb, priv);
3788 static int stmmac_setup_tc(struct net_device *ndev, enum tc_setup_type type,
3791 struct stmmac_priv *priv = netdev_priv(ndev);
3794 case TC_SETUP_BLOCK:
3795 return stmmac_setup_tc_block(priv, type_data);
3796 case TC_SETUP_QDISC_CBS:
3797 return stmmac_tc_setup_cbs(priv, priv, type_data);
3803 static int stmmac_set_mac_address(struct net_device *ndev, void *addr)
3805 struct stmmac_priv *priv = netdev_priv(ndev);
3808 ret = eth_mac_addr(ndev, addr);
3812 stmmac_set_umac_addr(priv, priv->hw, ndev->dev_addr, 0);
3817 #ifdef CONFIG_DEBUG_FS
3818 static struct dentry *stmmac_fs_dir;
3820 static void sysfs_display_ring(void *head, int size, int extend_desc,
3821 struct seq_file *seq)
3824 struct dma_extended_desc *ep = (struct dma_extended_desc *)head;
3825 struct dma_desc *p = (struct dma_desc *)head;
3827 for (i = 0; i < size; i++) {
3829 seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
3830 i, (unsigned int)virt_to_phys(ep),
3831 le32_to_cpu(ep->basic.des0),
3832 le32_to_cpu(ep->basic.des1),
3833 le32_to_cpu(ep->basic.des2),
3834 le32_to_cpu(ep->basic.des3));
3837 seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
3838 i, (unsigned int)virt_to_phys(p),
3839 le32_to_cpu(p->des0), le32_to_cpu(p->des1),
3840 le32_to_cpu(p->des2), le32_to_cpu(p->des3));
3843 seq_printf(seq, "\n");
3847 static int stmmac_sysfs_ring_read(struct seq_file *seq, void *v)
3849 struct net_device *dev = seq->private;
3850 struct stmmac_priv *priv = netdev_priv(dev);
3851 u32 rx_count = priv->plat->rx_queues_to_use;
3852 u32 tx_count = priv->plat->tx_queues_to_use;
3855 for (queue = 0; queue < rx_count; queue++) {
3856 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
3858 seq_printf(seq, "RX Queue %d:\n", queue);
3860 if (priv->extend_desc) {
3861 seq_printf(seq, "Extended descriptor ring:\n");
3862 sysfs_display_ring((void *)rx_q->dma_erx,
3863 DMA_RX_SIZE, 1, seq);
3865 seq_printf(seq, "Descriptor ring:\n");
3866 sysfs_display_ring((void *)rx_q->dma_rx,
3867 DMA_RX_SIZE, 0, seq);
3871 for (queue = 0; queue < tx_count; queue++) {
3872 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
3874 seq_printf(seq, "TX Queue %d:\n", queue);
3876 if (priv->extend_desc) {
3877 seq_printf(seq, "Extended descriptor ring:\n");
3878 sysfs_display_ring((void *)tx_q->dma_etx,
3879 DMA_TX_SIZE, 1, seq);
3881 seq_printf(seq, "Descriptor ring:\n");
3882 sysfs_display_ring((void *)tx_q->dma_tx,
3883 DMA_TX_SIZE, 0, seq);
3890 static int stmmac_sysfs_ring_open(struct inode *inode, struct file *file)
3892 return single_open(file, stmmac_sysfs_ring_read, inode->i_private);
3895 /* Debugfs files, should appear in /sys/kernel/debug/stmmaceth/eth0 */
3897 static const struct file_operations stmmac_rings_status_fops = {
3898 .owner = THIS_MODULE,
3899 .open = stmmac_sysfs_ring_open,
3901 .llseek = seq_lseek,
3902 .release = single_release,
3905 static int stmmac_sysfs_dma_cap_read(struct seq_file *seq, void *v)
3907 struct net_device *dev = seq->private;
3908 struct stmmac_priv *priv = netdev_priv(dev);
3910 if (!priv->hw_cap_support) {
3911 seq_printf(seq, "DMA HW features not supported\n");
3915 seq_printf(seq, "==============================\n");
3916 seq_printf(seq, "\tDMA HW features\n");
3917 seq_printf(seq, "==============================\n");
3919 seq_printf(seq, "\t10/100 Mbps: %s\n",
3920 (priv->dma_cap.mbps_10_100) ? "Y" : "N");
3921 seq_printf(seq, "\t1000 Mbps: %s\n",
3922 (priv->dma_cap.mbps_1000) ? "Y" : "N");
3923 seq_printf(seq, "\tHalf duplex: %s\n",
3924 (priv->dma_cap.half_duplex) ? "Y" : "N");
3925 seq_printf(seq, "\tHash Filter: %s\n",
3926 (priv->dma_cap.hash_filter) ? "Y" : "N");
3927 seq_printf(seq, "\tMultiple MAC address registers: %s\n",
3928 (priv->dma_cap.multi_addr) ? "Y" : "N");
3929 seq_printf(seq, "\tPCS (TBI/SGMII/RTBI PHY interfaces): %s\n",
3930 (priv->dma_cap.pcs) ? "Y" : "N");
3931 seq_printf(seq, "\tSMA (MDIO) Interface: %s\n",
3932 (priv->dma_cap.sma_mdio) ? "Y" : "N");
3933 seq_printf(seq, "\tPMT Remote wake up: %s\n",
3934 (priv->dma_cap.pmt_remote_wake_up) ? "Y" : "N");
3935 seq_printf(seq, "\tPMT Magic Frame: %s\n",
3936 (priv->dma_cap.pmt_magic_frame) ? "Y" : "N");
3937 seq_printf(seq, "\tRMON module: %s\n",
3938 (priv->dma_cap.rmon) ? "Y" : "N");
3939 seq_printf(seq, "\tIEEE 1588-2002 Time Stamp: %s\n",
3940 (priv->dma_cap.time_stamp) ? "Y" : "N");
3941 seq_printf(seq, "\tIEEE 1588-2008 Advanced Time Stamp: %s\n",
3942 (priv->dma_cap.atime_stamp) ? "Y" : "N");
3943 seq_printf(seq, "\t802.3az - Energy-Efficient Ethernet (EEE): %s\n",
3944 (priv->dma_cap.eee) ? "Y" : "N");
3945 seq_printf(seq, "\tAV features: %s\n", (priv->dma_cap.av) ? "Y" : "N");
3946 seq_printf(seq, "\tChecksum Offload in TX: %s\n",
3947 (priv->dma_cap.tx_coe) ? "Y" : "N");
3948 if (priv->synopsys_id >= DWMAC_CORE_4_00) {
3949 seq_printf(seq, "\tIP Checksum Offload in RX: %s\n",
3950 (priv->dma_cap.rx_coe) ? "Y" : "N");
3952 seq_printf(seq, "\tIP Checksum Offload (type1) in RX: %s\n",
3953 (priv->dma_cap.rx_coe_type1) ? "Y" : "N");
3954 seq_printf(seq, "\tIP Checksum Offload (type2) in RX: %s\n",
3955 (priv->dma_cap.rx_coe_type2) ? "Y" : "N");
3957 seq_printf(seq, "\tRXFIFO > 2048bytes: %s\n",
3958 (priv->dma_cap.rxfifo_over_2048) ? "Y" : "N");
3959 seq_printf(seq, "\tNumber of Additional RX channel: %d\n",
3960 priv->dma_cap.number_rx_channel);
3961 seq_printf(seq, "\tNumber of Additional TX channel: %d\n",
3962 priv->dma_cap.number_tx_channel);
3963 seq_printf(seq, "\tEnhanced descriptors: %s\n",
3964 (priv->dma_cap.enh_desc) ? "Y" : "N");
3969 static int stmmac_sysfs_dma_cap_open(struct inode *inode, struct file *file)
3971 return single_open(file, stmmac_sysfs_dma_cap_read, inode->i_private);
3974 static const struct file_operations stmmac_dma_cap_fops = {
3975 .owner = THIS_MODULE,
3976 .open = stmmac_sysfs_dma_cap_open,
3978 .llseek = seq_lseek,
3979 .release = single_release,
3982 static int stmmac_init_fs(struct net_device *dev)
3984 struct stmmac_priv *priv = netdev_priv(dev);
3986 /* Create per netdev entries */
3987 priv->dbgfs_dir = debugfs_create_dir(dev->name, stmmac_fs_dir);
3989 if (!priv->dbgfs_dir || IS_ERR(priv->dbgfs_dir)) {
3990 netdev_err(priv->dev, "ERROR failed to create debugfs directory\n");
3995 /* Entry to report DMA RX/TX rings */
3996 priv->dbgfs_rings_status =
3997 debugfs_create_file("descriptors_status", 0444,
3998 priv->dbgfs_dir, dev,
3999 &stmmac_rings_status_fops);
4001 if (!priv->dbgfs_rings_status || IS_ERR(priv->dbgfs_rings_status)) {
4002 netdev_err(priv->dev, "ERROR creating stmmac ring debugfs file\n");
4003 debugfs_remove_recursive(priv->dbgfs_dir);
4008 /* Entry to report the DMA HW features */
4009 priv->dbgfs_dma_cap = debugfs_create_file("dma_cap", 0444,
4011 dev, &stmmac_dma_cap_fops);
4013 if (!priv->dbgfs_dma_cap || IS_ERR(priv->dbgfs_dma_cap)) {
4014 netdev_err(priv->dev, "ERROR creating stmmac MMC debugfs file\n");
4015 debugfs_remove_recursive(priv->dbgfs_dir);
4023 static void stmmac_exit_fs(struct net_device *dev)
4025 struct stmmac_priv *priv = netdev_priv(dev);
4027 debugfs_remove_recursive(priv->dbgfs_dir);
4029 #endif /* CONFIG_DEBUG_FS */
4031 static const struct net_device_ops stmmac_netdev_ops = {
4032 .ndo_open = stmmac_open,
4033 .ndo_start_xmit = stmmac_xmit,
4034 .ndo_stop = stmmac_release,
4035 .ndo_change_mtu = stmmac_change_mtu,
4036 .ndo_fix_features = stmmac_fix_features,
4037 .ndo_set_features = stmmac_set_features,
4038 .ndo_set_rx_mode = stmmac_set_rx_mode,
4039 .ndo_tx_timeout = stmmac_tx_timeout,
4040 .ndo_do_ioctl = stmmac_ioctl,
4041 .ndo_setup_tc = stmmac_setup_tc,
4042 #ifdef CONFIG_NET_POLL_CONTROLLER
4043 .ndo_poll_controller = stmmac_poll_controller,
4045 .ndo_set_mac_address = stmmac_set_mac_address,
4048 static void stmmac_reset_subtask(struct stmmac_priv *priv)
4050 if (!test_and_clear_bit(STMMAC_RESET_REQUESTED, &priv->state))
4052 if (test_bit(STMMAC_DOWN, &priv->state))
4055 netdev_err(priv->dev, "Reset adapter.\n");
4058 netif_trans_update(priv->dev);
4059 while (test_and_set_bit(STMMAC_RESETING, &priv->state))
4060 usleep_range(1000, 2000);
4062 set_bit(STMMAC_DOWN, &priv->state);
4063 dev_close(priv->dev);
4064 dev_open(priv->dev);
4065 clear_bit(STMMAC_DOWN, &priv->state);
4066 clear_bit(STMMAC_RESETING, &priv->state);
4070 static void stmmac_service_task(struct work_struct *work)
4072 struct stmmac_priv *priv = container_of(work, struct stmmac_priv,
4075 stmmac_reset_subtask(priv);
4076 clear_bit(STMMAC_SERVICE_SCHED, &priv->state);
4080 * stmmac_hw_init - Init the MAC device
4081 * @priv: driver private structure
4082 * Description: this function is to configure the MAC device according to
4083 * some platform parameters or the HW capability register. It prepares the
4084 * driver to use either ring or chain modes and to setup either enhanced or
4085 * normal descriptors.
4087 static int stmmac_hw_init(struct stmmac_priv *priv)
4091 /* dwmac-sun8i only work in chain mode */
4092 if (priv->plat->has_sun8i)
4094 priv->chain_mode = chain_mode;
4096 /* Initialize HW Interface */
4097 ret = stmmac_hwif_init(priv);
4101 /* Get the HW capability (new GMAC newer than 3.50a) */
4102 priv->hw_cap_support = stmmac_get_hw_features(priv);
4103 if (priv->hw_cap_support) {
4104 dev_info(priv->device, "DMA HW capability register supported\n");
4106 /* We can override some gmac/dma configuration fields: e.g.
4107 * enh_desc, tx_coe (e.g. that are passed through the
4108 * platform) with the values from the HW capability
4109 * register (if supported).
4111 priv->plat->enh_desc = priv->dma_cap.enh_desc;
4112 priv->plat->pmt = priv->dma_cap.pmt_remote_wake_up;
4113 priv->hw->pmt = priv->plat->pmt;
4115 /* TXCOE doesn't work in thresh DMA mode */
4116 if (priv->plat->force_thresh_dma_mode)
4117 priv->plat->tx_coe = 0;
4119 priv->plat->tx_coe = priv->dma_cap.tx_coe;
4121 /* In case of GMAC4 rx_coe is from HW cap register. */
4122 priv->plat->rx_coe = priv->dma_cap.rx_coe;
4124 if (priv->dma_cap.rx_coe_type2)
4125 priv->plat->rx_coe = STMMAC_RX_COE_TYPE2;
4126 else if (priv->dma_cap.rx_coe_type1)
4127 priv->plat->rx_coe = STMMAC_RX_COE_TYPE1;
4130 dev_info(priv->device, "No HW DMA feature register supported\n");
4133 if (priv->plat->rx_coe) {
4134 priv->hw->rx_csum = priv->plat->rx_coe;
4135 dev_info(priv->device, "RX Checksum Offload Engine supported\n");
4136 if (priv->synopsys_id < DWMAC_CORE_4_00)
4137 dev_info(priv->device, "COE Type %d\n", priv->hw->rx_csum);
4139 if (priv->plat->tx_coe)
4140 dev_info(priv->device, "TX Checksum insertion supported\n");
4142 if (priv->plat->pmt) {
4143 dev_info(priv->device, "Wake-Up On Lan supported\n");
4144 device_set_wakeup_capable(priv->device, 1);
4147 if (priv->dma_cap.tsoen)
4148 dev_info(priv->device, "TSO supported\n");
4150 /* Run HW quirks, if any */
4151 if (priv->hwif_quirks) {
4152 ret = priv->hwif_quirks(priv);
4162 * @device: device pointer
4163 * @plat_dat: platform data pointer
4164 * @res: stmmac resource pointer
4165 * Description: this is the main probe function used to
4166 * call the alloc_etherdev, allocate the priv structure.
4168 * returns 0 on success, otherwise errno.
4170 int stmmac_dvr_probe(struct device *device,
4171 struct plat_stmmacenet_data *plat_dat,
4172 struct stmmac_resources *res)
4174 struct net_device *ndev = NULL;
4175 struct stmmac_priv *priv;
4179 ndev = alloc_etherdev_mqs(sizeof(struct stmmac_priv),
4185 SET_NETDEV_DEV(ndev, device);
4187 priv = netdev_priv(ndev);
4188 priv->device = device;
4191 stmmac_set_ethtool_ops(ndev);
4192 priv->pause = pause;
4193 priv->plat = plat_dat;
4194 priv->ioaddr = res->addr;
4195 priv->dev->base_addr = (unsigned long)res->addr;
4197 priv->dev->irq = res->irq;
4198 priv->wol_irq = res->wol_irq;
4199 priv->lpi_irq = res->lpi_irq;
4202 memcpy(priv->dev->dev_addr, res->mac, ETH_ALEN);
4204 dev_set_drvdata(device, priv->dev);
4206 /* Verify driver arguments */
4207 stmmac_verify_args();
4209 /* Allocate workqueue */
4210 priv->wq = create_singlethread_workqueue("stmmac_wq");
4212 dev_err(priv->device, "failed to create workqueue\n");
4216 INIT_WORK(&priv->service_task, stmmac_service_task);
4218 /* Override with kernel parameters if supplied XXX CRS XXX
4219 * this needs to have multiple instances
4221 if ((phyaddr >= 0) && (phyaddr <= 31))
4222 priv->plat->phy_addr = phyaddr;
4224 if (priv->plat->stmmac_rst) {
4225 ret = reset_control_assert(priv->plat->stmmac_rst);
4226 reset_control_deassert(priv->plat->stmmac_rst);
4227 /* Some reset controllers have only reset callback instead of
4228 * assert + deassert callbacks pair.
4230 if (ret == -ENOTSUPP)
4231 reset_control_reset(priv->plat->stmmac_rst);
4234 /* Init MAC and get the capabilities */
4235 ret = stmmac_hw_init(priv);
4239 /* Configure real RX and TX queues */
4240 netif_set_real_num_rx_queues(ndev, priv->plat->rx_queues_to_use);
4241 netif_set_real_num_tx_queues(ndev, priv->plat->tx_queues_to_use);
4243 ndev->netdev_ops = &stmmac_netdev_ops;
4245 ndev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
4248 ret = stmmac_tc_init(priv, priv);
4250 ndev->hw_features |= NETIF_F_HW_TC;
4253 if ((priv->plat->tso_en) && (priv->dma_cap.tsoen)) {
4254 ndev->hw_features |= NETIF_F_TSO | NETIF_F_TSO6;
4256 dev_info(priv->device, "TSO feature enabled\n");
4258 ndev->features |= ndev->hw_features | NETIF_F_HIGHDMA;
4259 ndev->watchdog_timeo = msecs_to_jiffies(watchdog);
4260 #ifdef STMMAC_VLAN_TAG_USED
4261 /* Both mac100 and gmac support receive VLAN tag detection */
4262 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX;
4264 priv->msg_enable = netif_msg_init(debug, default_msg_level);
4266 /* MTU range: 46 - hw-specific max */
4267 ndev->min_mtu = ETH_ZLEN - ETH_HLEN;
4268 if ((priv->plat->enh_desc) || (priv->synopsys_id >= DWMAC_CORE_4_00))
4269 ndev->max_mtu = JUMBO_LEN;
4271 ndev->max_mtu = SKB_MAX_HEAD(NET_SKB_PAD + NET_IP_ALIGN);
4272 /* Will not overwrite ndev->max_mtu if plat->maxmtu > ndev->max_mtu
4273 * as well as plat->maxmtu < ndev->min_mtu which is a invalid range.
4275 if ((priv->plat->maxmtu < ndev->max_mtu) &&
4276 (priv->plat->maxmtu >= ndev->min_mtu))
4277 ndev->max_mtu = priv->plat->maxmtu;
4278 else if (priv->plat->maxmtu < ndev->min_mtu)
4279 dev_warn(priv->device,
4280 "%s: warning: maxmtu having invalid value (%d)\n",
4281 __func__, priv->plat->maxmtu);
4284 priv->flow_ctrl = FLOW_AUTO; /* RX/TX pause on */
4286 /* Rx Watchdog is available in the COREs newer than the 3.40.
4287 * In some case, for example on bugged HW this feature
4288 * has to be disable and this can be done by passing the
4289 * riwt_off field from the platform.
4291 if ((priv->synopsys_id >= DWMAC_CORE_3_50) && (!priv->plat->riwt_off)) {
4293 dev_info(priv->device,
4294 "Enable RX Mitigation via HW Watchdog Timer\n");
4297 for (queue = 0; queue < priv->plat->rx_queues_to_use; queue++) {
4298 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
4300 netif_napi_add(ndev, &rx_q->napi, stmmac_poll,
4301 (8 * priv->plat->rx_queues_to_use));
4304 mutex_init(&priv->lock);
4306 /* If a specific clk_csr value is passed from the platform
4307 * this means that the CSR Clock Range selection cannot be
4308 * changed at run-time and it is fixed. Viceversa the driver'll try to
4309 * set the MDC clock dynamically according to the csr actual
4312 if (!priv->plat->clk_csr)
4313 stmmac_clk_csr_set(priv);
4315 priv->clk_csr = priv->plat->clk_csr;
4317 stmmac_check_pcs_mode(priv);
4319 if (priv->hw->pcs != STMMAC_PCS_RGMII &&
4320 priv->hw->pcs != STMMAC_PCS_TBI &&
4321 priv->hw->pcs != STMMAC_PCS_RTBI) {
4322 /* MDIO bus Registration */
4323 ret = stmmac_mdio_register(ndev);
4325 dev_err(priv->device,
4326 "%s: MDIO bus (id: %d) registration failed",
4327 __func__, priv->plat->bus_id);
4328 goto error_mdio_register;
4332 ret = register_netdev(ndev);
4334 dev_err(priv->device, "%s: ERROR %i registering the device\n",
4336 goto error_netdev_register;
4341 error_netdev_register:
4342 if (priv->hw->pcs != STMMAC_PCS_RGMII &&
4343 priv->hw->pcs != STMMAC_PCS_TBI &&
4344 priv->hw->pcs != STMMAC_PCS_RTBI)
4345 stmmac_mdio_unregister(ndev);
4346 error_mdio_register:
4347 for (queue = 0; queue < priv->plat->rx_queues_to_use; queue++) {
4348 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
4350 netif_napi_del(&rx_q->napi);
4353 destroy_workqueue(priv->wq);
4359 EXPORT_SYMBOL_GPL(stmmac_dvr_probe);
4363 * @dev: device pointer
4364 * Description: this function resets the TX/RX processes, disables the MAC RX/TX
4365 * changes the link status, releases the DMA descriptor rings.
4367 int stmmac_dvr_remove(struct device *dev)
4369 struct net_device *ndev = dev_get_drvdata(dev);
4370 struct stmmac_priv *priv = netdev_priv(ndev);
4372 netdev_info(priv->dev, "%s: removing driver", __func__);
4374 stmmac_stop_all_dma(priv);
4376 stmmac_mac_set(priv, priv->ioaddr, false);
4377 netif_carrier_off(ndev);
4378 unregister_netdev(ndev);
4379 if (priv->plat->stmmac_rst)
4380 reset_control_assert(priv->plat->stmmac_rst);
4381 clk_disable_unprepare(priv->plat->pclk);
4382 clk_disable_unprepare(priv->plat->stmmac_clk);
4383 if (priv->hw->pcs != STMMAC_PCS_RGMII &&
4384 priv->hw->pcs != STMMAC_PCS_TBI &&
4385 priv->hw->pcs != STMMAC_PCS_RTBI)
4386 stmmac_mdio_unregister(ndev);
4387 destroy_workqueue(priv->wq);
4388 mutex_destroy(&priv->lock);
4393 EXPORT_SYMBOL_GPL(stmmac_dvr_remove);
4396 * stmmac_suspend - suspend callback
4397 * @dev: device pointer
4398 * Description: this is the function to suspend the device and it is called
4399 * by the platform driver to stop the network queue, release the resources,
4400 * program the PMT register (for WoL), clean and release driver resources.
4402 int stmmac_suspend(struct device *dev)
4404 struct net_device *ndev = dev_get_drvdata(dev);
4405 struct stmmac_priv *priv = netdev_priv(ndev);
4407 if (!ndev || !netif_running(ndev))
4411 phy_stop(ndev->phydev);
4413 mutex_lock(&priv->lock);
4415 netif_device_detach(ndev);
4416 stmmac_stop_all_queues(priv);
4418 stmmac_disable_all_queues(priv);
4420 /* Stop TX/RX DMA */
4421 stmmac_stop_all_dma(priv);
4423 /* Enable Power down mode by programming the PMT regs */
4424 if (device_may_wakeup(priv->device)) {
4425 stmmac_pmt(priv, priv->hw, priv->wolopts);
4428 stmmac_mac_set(priv, priv->ioaddr, false);
4429 pinctrl_pm_select_sleep_state(priv->device);
4430 /* Disable clock in case of PWM is off */
4431 clk_disable(priv->plat->pclk);
4432 clk_disable(priv->plat->stmmac_clk);
4434 mutex_unlock(&priv->lock);
4436 priv->oldlink = false;
4437 priv->speed = SPEED_UNKNOWN;
4438 priv->oldduplex = DUPLEX_UNKNOWN;
4441 EXPORT_SYMBOL_GPL(stmmac_suspend);
4444 * stmmac_reset_queues_param - reset queue parameters
4445 * @dev: device pointer
4447 static void stmmac_reset_queues_param(struct stmmac_priv *priv)
4449 u32 rx_cnt = priv->plat->rx_queues_to_use;
4450 u32 tx_cnt = priv->plat->tx_queues_to_use;
4453 for (queue = 0; queue < rx_cnt; queue++) {
4454 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
4460 for (queue = 0; queue < tx_cnt; queue++) {
4461 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
4470 * stmmac_resume - resume callback
4471 * @dev: device pointer
4472 * Description: when resume this function is invoked to setup the DMA and CORE
4473 * in a usable state.
4475 int stmmac_resume(struct device *dev)
4477 struct net_device *ndev = dev_get_drvdata(dev);
4478 struct stmmac_priv *priv = netdev_priv(ndev);
4480 if (!netif_running(ndev))
4483 /* Power Down bit, into the PM register, is cleared
4484 * automatically as soon as a magic packet or a Wake-up frame
4485 * is received. Anyway, it's better to manually clear
4486 * this bit because it can generate problems while resuming
4487 * from another devices (e.g. serial console).
4489 if (device_may_wakeup(priv->device)) {
4490 mutex_lock(&priv->lock);
4491 stmmac_pmt(priv, priv->hw, 0);
4492 mutex_unlock(&priv->lock);
4495 pinctrl_pm_select_default_state(priv->device);
4496 /* enable the clk previously disabled */
4497 clk_enable(priv->plat->stmmac_clk);
4498 clk_enable(priv->plat->pclk);
4499 /* reset the phy so that it's ready */
4501 stmmac_mdio_reset(priv->mii);
4504 netif_device_attach(ndev);
4506 mutex_lock(&priv->lock);
4508 stmmac_reset_queues_param(priv);
4510 stmmac_clear_descriptors(priv);
4512 stmmac_hw_setup(ndev, false);
4513 stmmac_init_tx_coalesce(priv);
4514 stmmac_set_rx_mode(ndev);
4516 stmmac_enable_all_queues(priv);
4518 stmmac_start_all_queues(priv);
4520 mutex_unlock(&priv->lock);
4523 phy_start(ndev->phydev);
4527 EXPORT_SYMBOL_GPL(stmmac_resume);
4530 static int __init stmmac_cmdline_opt(char *str)
4536 while ((opt = strsep(&str, ",")) != NULL) {
4537 if (!strncmp(opt, "debug:", 6)) {
4538 if (kstrtoint(opt + 6, 0, &debug))
4540 } else if (!strncmp(opt, "phyaddr:", 8)) {
4541 if (kstrtoint(opt + 8, 0, &phyaddr))
4543 } else if (!strncmp(opt, "buf_sz:", 7)) {
4544 if (kstrtoint(opt + 7, 0, &buf_sz))
4546 } else if (!strncmp(opt, "tc:", 3)) {
4547 if (kstrtoint(opt + 3, 0, &tc))
4549 } else if (!strncmp(opt, "watchdog:", 9)) {
4550 if (kstrtoint(opt + 9, 0, &watchdog))
4552 } else if (!strncmp(opt, "flow_ctrl:", 10)) {
4553 if (kstrtoint(opt + 10, 0, &flow_ctrl))
4555 } else if (!strncmp(opt, "pause:", 6)) {
4556 if (kstrtoint(opt + 6, 0, &pause))
4558 } else if (!strncmp(opt, "eee_timer:", 10)) {
4559 if (kstrtoint(opt + 10, 0, &eee_timer))
4561 } else if (!strncmp(opt, "chain_mode:", 11)) {
4562 if (kstrtoint(opt + 11, 0, &chain_mode))
4569 pr_err("%s: ERROR broken module parameter conversion", __func__);
4573 __setup("stmmaceth=", stmmac_cmdline_opt);
4576 static int __init stmmac_init(void)
4578 #ifdef CONFIG_DEBUG_FS
4579 /* Create debugfs main directory if it doesn't exist yet */
4580 if (!stmmac_fs_dir) {
4581 stmmac_fs_dir = debugfs_create_dir(STMMAC_RESOURCE_NAME, NULL);
4583 if (!stmmac_fs_dir || IS_ERR(stmmac_fs_dir)) {
4584 pr_err("ERROR %s, debugfs create directory failed\n",
4585 STMMAC_RESOURCE_NAME);
4595 static void __exit stmmac_exit(void)
4597 #ifdef CONFIG_DEBUG_FS
4598 debugfs_remove_recursive(stmmac_fs_dir);
4602 module_init(stmmac_init)
4603 module_exit(stmmac_exit)
4605 MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet device driver");
4606 MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>");
4607 MODULE_LICENSE("GPL");