1 /*******************************************************************************
2 STMMAC Ethernet Driver -- MDIO bus implementation
3 Provides Bus interface for MII registers
5 Copyright (C) 2007-2009 STMicroelectronics Ltd
7 This program is free software; you can redistribute it and/or modify it
8 under the terms and conditions of the GNU General Public License,
9 version 2, as published by the Free Software Foundation.
11 This program is distributed in the hope it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 You should have received a copy of the GNU General Public License along with
17 this program; if not, write to the Free Software Foundation, Inc.,
18 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
20 The full GNU General Public License is included in this distribution in
21 the file called "COPYING".
23 Author: Carl Shaw <carl.shaw@st.com>
24 Maintainer: Giuseppe Cavallaro <peppe.cavallaro@st.com>
25 *******************************************************************************/
27 #include <linux/mii.h>
28 #include <linux/phy.h>
29 #include <linux/slab.h>
31 #include <linux/of_gpio.h>
32 #include <linux/of_mdio.h>
37 #define MII_BUSY 0x00000001
38 #define MII_WRITE 0x00000002
41 #define MII_GMAC4_GOC_SHIFT 2
42 #define MII_GMAC4_WRITE (1 << MII_GMAC4_GOC_SHIFT)
43 #define MII_GMAC4_READ (3 << MII_GMAC4_GOC_SHIFT)
45 #define MII_PHY_ADDR_GMAC4_SHIFT 21
46 #define MII_PHY_ADDR_GMAC4_MASK GENMASK(25, 21)
47 #define MII_PHY_REG_GMAC4_SHIFT 16
48 #define MII_PHY_REG_GMAC4_MASK GENMASK(20, 16)
49 #define MII_CSR_CLK_GMAC4_SHIFT 8
50 #define MII_CSR_CLK_GMAC4_MASK GENMASK(11, 8)
52 static int stmmac_mdio_busy_wait(void __iomem *ioaddr, unsigned int mii_addr)
55 unsigned long finish = jiffies + 3 * HZ;
59 if (readl(ioaddr + mii_addr) & MII_BUSY)
63 } while (!time_after_eq(curr, finish));
70 * @bus: points to the mii_bus structure
71 * @phyaddr: MII addr reg bits 15-11
72 * @phyreg: MII addr reg bits 10-6
73 * Description: it reads data from the MII register from within the phy device.
74 * For the 7111 GMAC, we must set the bit 0 in the MII address register while
75 * accessing the PHY registers.
76 * Fortunately, it seems this has no drawback for the 7109 MAC.
78 static int stmmac_mdio_read(struct mii_bus *bus, int phyaddr, int phyreg)
80 struct net_device *ndev = bus->priv;
81 struct stmmac_priv *priv = netdev_priv(ndev);
82 unsigned int mii_address = priv->hw->mii.addr;
83 unsigned int mii_data = priv->hw->mii.data;
86 u16 regValue = (((phyaddr << 11) & (0x0000F800)) |
87 ((phyreg << 6) & (0x000007C0)));
88 regValue |= MII_BUSY | ((priv->clk_csr & 0xF) << 2);
90 if (stmmac_mdio_busy_wait(priv->ioaddr, mii_address))
93 writel(regValue, priv->ioaddr + mii_address);
95 if (stmmac_mdio_busy_wait(priv->ioaddr, mii_address))
98 /* Read the data from the MII data register */
99 data = (int)readl(priv->ioaddr + mii_data);
106 * @bus: points to the mii_bus structure
107 * @phyaddr: MII addr reg bits 15-11
108 * @phyreg: MII addr reg bits 10-6
110 * Description: it writes the data into the MII register from within the device.
112 static int stmmac_mdio_write(struct mii_bus *bus, int phyaddr, int phyreg,
115 struct net_device *ndev = bus->priv;
116 struct stmmac_priv *priv = netdev_priv(ndev);
117 unsigned int mii_address = priv->hw->mii.addr;
118 unsigned int mii_data = priv->hw->mii.data;
121 (((phyaddr << 11) & (0x0000F800)) | ((phyreg << 6) & (0x000007C0)))
124 value |= MII_BUSY | ((priv->clk_csr & 0xF) << 2);
126 /* Wait until any existing MII operation is complete */
127 if (stmmac_mdio_busy_wait(priv->ioaddr, mii_address))
130 /* Set the MII address register to write */
131 writel(phydata, priv->ioaddr + mii_data);
132 writel(value, priv->ioaddr + mii_address);
134 /* Wait until any existing MII operation is complete */
135 return stmmac_mdio_busy_wait(priv->ioaddr, mii_address);
139 * stmmac_mdio_read_gmac4
140 * @bus: points to the mii_bus structure
141 * @phyaddr: MII addr reg bits 25-21
142 * @phyreg: MII addr reg bits 20-16
143 * Description: it reads data from the MII register of GMAC4 from within
146 static int stmmac_mdio_read_gmac4(struct mii_bus *bus, int phyaddr, int phyreg)
148 struct net_device *ndev = bus->priv;
149 struct stmmac_priv *priv = netdev_priv(ndev);
150 unsigned int mii_address = priv->hw->mii.addr;
151 unsigned int mii_data = priv->hw->mii.data;
153 u32 value = (((phyaddr << MII_PHY_ADDR_GMAC4_SHIFT) &
154 (MII_PHY_ADDR_GMAC4_MASK)) |
155 ((phyreg << MII_PHY_REG_GMAC4_SHIFT) &
156 (MII_PHY_REG_GMAC4_MASK))) | MII_GMAC4_READ;
158 value |= MII_BUSY | ((priv->clk_csr & MII_CSR_CLK_GMAC4_MASK)
159 << MII_CSR_CLK_GMAC4_SHIFT);
161 if (stmmac_mdio_busy_wait(priv->ioaddr, mii_address))
164 writel(value, priv->ioaddr + mii_address);
166 if (stmmac_mdio_busy_wait(priv->ioaddr, mii_address))
169 /* Read the data from the MII data register */
170 data = (int)readl(priv->ioaddr + mii_data);
176 * stmmac_mdio_write_gmac4
177 * @bus: points to the mii_bus structure
178 * @phyaddr: MII addr reg bits 25-21
179 * @phyreg: MII addr reg bits 20-16
181 * Description: it writes the data into the MII register of GMAC4 from within
184 static int stmmac_mdio_write_gmac4(struct mii_bus *bus, int phyaddr, int phyreg,
187 struct net_device *ndev = bus->priv;
188 struct stmmac_priv *priv = netdev_priv(ndev);
189 unsigned int mii_address = priv->hw->mii.addr;
190 unsigned int mii_data = priv->hw->mii.data;
192 u32 value = (((phyaddr << MII_PHY_ADDR_GMAC4_SHIFT) &
193 (MII_PHY_ADDR_GMAC4_MASK)) |
194 ((phyreg << MII_PHY_REG_GMAC4_SHIFT) &
195 (MII_PHY_REG_GMAC4_MASK))) | MII_GMAC4_WRITE;
197 value |= MII_BUSY | ((priv->clk_csr & MII_CSR_CLK_GMAC4_MASK)
198 << MII_CSR_CLK_GMAC4_SHIFT);
200 /* Wait until any existing MII operation is complete */
201 if (stmmac_mdio_busy_wait(priv->ioaddr, mii_address))
204 /* Set the MII address register to write */
205 writel(phydata, priv->ioaddr + mii_data);
206 writel(value, priv->ioaddr + mii_address);
208 /* Wait until any existing MII operation is complete */
209 return stmmac_mdio_busy_wait(priv->ioaddr, mii_address);
214 * @bus: points to the mii_bus structure
215 * Description: reset the MII bus
217 int stmmac_mdio_reset(struct mii_bus *bus)
219 #if defined(CONFIG_STMMAC_PLATFORM)
220 struct net_device *ndev = bus->priv;
221 struct stmmac_priv *priv = netdev_priv(ndev);
222 unsigned int mii_address = priv->hw->mii.addr;
223 struct stmmac_mdio_bus_data *data = priv->plat->mdio_bus_data;
226 if (priv->device->of_node) {
228 if (data->reset_gpio < 0) {
229 struct device_node *np = priv->device->of_node;
233 data->reset_gpio = of_get_named_gpio(np,
234 "snps,reset-gpio", 0);
235 if (data->reset_gpio < 0)
238 data->active_low = of_property_read_bool(np,
239 "snps,reset-active-low");
240 of_property_read_u32_array(np,
241 "snps,reset-delays-us", data->delays, 3);
243 if (gpio_request(data->reset_gpio, "mdio-reset"))
247 gpio_direction_output(data->reset_gpio,
248 data->active_low ? 1 : 0);
250 msleep(DIV_ROUND_UP(data->delays[0], 1000));
252 gpio_set_value(data->reset_gpio, data->active_low ? 0 : 1);
254 msleep(DIV_ROUND_UP(data->delays[1], 1000));
256 gpio_set_value(data->reset_gpio, data->active_low ? 1 : 0);
258 msleep(DIV_ROUND_UP(data->delays[2], 1000));
262 if (data->phy_reset) {
263 pr_debug("stmmac_mdio_reset: calling phy_reset\n");
264 data->phy_reset(priv->plat->bsp_priv);
267 /* This is a workaround for problems with the STE101P PHY.
268 * It doesn't complete its reset until at least one clock cycle
269 * on MDC, so perform a dummy mdio read. To be upadted for GMAC4
272 if (!priv->plat->has_gmac4)
273 writel(0, priv->ioaddr + mii_address);
279 * stmmac_mdio_register
280 * @ndev: net device structure
281 * Description: it registers the MII bus
283 int stmmac_mdio_register(struct net_device *ndev)
286 struct mii_bus *new_bus;
287 struct stmmac_priv *priv = netdev_priv(ndev);
288 struct stmmac_mdio_bus_data *mdio_bus_data = priv->plat->mdio_bus_data;
289 struct device_node *mdio_node = priv->plat->mdio_node;
295 new_bus = mdiobus_alloc();
299 if (mdio_bus_data->irqs)
300 memcpy(new_bus->irq, mdio_bus_data->irqs, sizeof(new_bus->irq));
303 if (priv->device->of_node)
304 mdio_bus_data->reset_gpio = -1;
307 new_bus->name = "stmmac";
308 if (priv->plat->has_gmac4) {
309 new_bus->read = &stmmac_mdio_read_gmac4;
310 new_bus->write = &stmmac_mdio_write_gmac4;
312 new_bus->read = &stmmac_mdio_read;
313 new_bus->write = &stmmac_mdio_write;
316 new_bus->reset = &stmmac_mdio_reset;
317 snprintf(new_bus->id, MII_BUS_ID_SIZE, "%s-%x",
318 new_bus->name, priv->plat->bus_id);
319 new_bus->priv = ndev;
320 new_bus->phy_mask = mdio_bus_data->phy_mask;
321 new_bus->parent = priv->device;
324 err = of_mdiobus_register(new_bus, mdio_node);
326 err = mdiobus_register(new_bus);
328 pr_err("%s: Cannot register as MDIO bus\n", new_bus->name);
329 goto bus_register_fail;
332 if (priv->plat->phy_node || mdio_node)
333 goto bus_register_done;
336 for (addr = 0; addr < PHY_MAX_ADDR; addr++) {
337 struct phy_device *phydev = mdiobus_get_phy(new_bus, addr);
344 * If an IRQ was provided to be assigned after
345 * the bus probe, do it here.
347 if ((mdio_bus_data->irqs == NULL) &&
348 (mdio_bus_data->probed_phy_irq > 0)) {
350 mdio_bus_data->probed_phy_irq;
351 phydev->irq = mdio_bus_data->probed_phy_irq;
355 * If we're going to bind the MAC to this PHY bus,
356 * and no PHY number was provided to the MAC,
357 * use the one probed here.
359 if (priv->plat->phy_addr == -1)
360 priv->plat->phy_addr = addr;
362 act = (priv->plat->phy_addr == addr);
363 switch (phydev->irq) {
367 case PHY_IGNORE_INTERRUPT:
371 sprintf(irq_num, "%d", phydev->irq);
375 pr_info("%s: PHY ID %08x at %d IRQ %s (%s)%s\n",
376 ndev->name, phydev->phy_id, addr,
377 irq_str, phydev_name(phydev),
378 act ? " active" : "");
383 if (!found && !mdio_node) {
384 pr_warn("%s: No PHY found\n", ndev->name);
385 mdiobus_unregister(new_bus);
386 mdiobus_free(new_bus);
396 mdiobus_free(new_bus);
401 * stmmac_mdio_unregister
402 * @ndev: net device structure
403 * Description: it unregisters the MII bus
405 int stmmac_mdio_unregister(struct net_device *ndev)
407 struct stmmac_priv *priv = netdev_priv(ndev);
412 mdiobus_unregister(priv->mii);
413 priv->mii->priv = NULL;
414 mdiobus_free(priv->mii);