1 // SPDX-License-Identifier: GPL-2.0-only
2 /*******************************************************************************
3 This contains the functions to handle the pci driver.
5 Copyright (C) 2011-2012 Vayavya Labs Pvt Ltd
8 Author: Rayagond Kokatanur <rayagond@vayavyalabs.com>
9 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
10 *******************************************************************************/
12 #include <linux/clk-provider.h>
13 #include <linux/pci.h>
14 #include <linux/dmi.h>
19 * This struct is used to associate PCI Function of MAC controller on a board,
20 * discovered via DMI, with the address of PHY connected to the MAC. The
21 * negative value of the address means that MAC controller is not connected
24 struct stmmac_pci_func_data {
29 struct stmmac_pci_dmi_data {
30 const struct stmmac_pci_func_data *func;
34 struct stmmac_pci_info {
35 int (*setup)(struct pci_dev *pdev, struct plat_stmmacenet_data *plat);
38 static int stmmac_pci_find_phy_addr(struct pci_dev *pdev,
39 const struct dmi_system_id *dmi_list)
41 const struct stmmac_pci_func_data *func_data;
42 const struct stmmac_pci_dmi_data *dmi_data;
43 const struct dmi_system_id *dmi_id;
44 int func = PCI_FUNC(pdev->devfn);
47 dmi_id = dmi_first_match(dmi_list);
51 dmi_data = dmi_id->driver_data;
52 func_data = dmi_data->func;
54 for (n = 0; n < dmi_data->nfuncs; n++, func_data++)
55 if (func_data->func == func)
56 return func_data->phy_addr;
61 static void common_default_data(struct plat_stmmacenet_data *plat)
63 plat->clk_csr = 2; /* clk_csr_i = 20-35MHz & MDC = clk_csr_i/16 */
65 plat->force_sf_dma_mode = 1;
67 plat->mdio_bus_data->needs_reset = true;
69 /* Set default value for multicast hash bins */
70 plat->multicast_filter_bins = HASH_TABLE_SIZE;
72 /* Set default value for unicast filter entries */
73 plat->unicast_filter_entries = 1;
75 /* Set the maxmtu to a default of JUMBO_LEN */
76 plat->maxmtu = JUMBO_LEN;
78 /* Set default number of RX and TX queues to use */
79 plat->tx_queues_to_use = 1;
80 plat->rx_queues_to_use = 1;
82 /* Disable Priority config by default */
83 plat->tx_queues_cfg[0].use_prio = false;
84 plat->rx_queues_cfg[0].use_prio = false;
86 /* Disable RX queues routing by default */
87 plat->rx_queues_cfg[0].pkt_route = 0x0;
90 static int stmmac_default_data(struct pci_dev *pdev,
91 struct plat_stmmacenet_data *plat)
93 /* Set common default data first */
94 common_default_data(plat);
98 plat->phy_interface = PHY_INTERFACE_MODE_GMII;
100 plat->dma_cfg->pbl = 32;
101 plat->dma_cfg->pblx8 = true;
107 static const struct stmmac_pci_info stmmac_pci_info = {
108 .setup = stmmac_default_data,
111 static int intel_mgbe_common_data(struct pci_dev *pdev,
112 struct plat_stmmacenet_data *plat)
119 plat->force_sf_dma_mode = 0;
122 plat->rx_sched_algorithm = MTL_RX_ALGORITHM_SP;
124 for (i = 0; i < plat->rx_queues_to_use; i++) {
125 plat->rx_queues_cfg[i].mode_to_use = MTL_QUEUE_DCB;
126 plat->rx_queues_cfg[i].chan = i;
128 /* Disable Priority config by default */
129 plat->rx_queues_cfg[i].use_prio = false;
131 /* Disable RX queues routing by default */
132 plat->rx_queues_cfg[i].pkt_route = 0x0;
135 for (i = 0; i < plat->tx_queues_to_use; i++) {
136 plat->tx_queues_cfg[i].mode_to_use = MTL_QUEUE_DCB;
138 /* Disable Priority config by default */
139 plat->tx_queues_cfg[i].use_prio = false;
142 /* FIFO size is 4096 bytes for 1 tx/rx queue */
143 plat->tx_fifo_size = plat->tx_queues_to_use * 4096;
144 plat->rx_fifo_size = plat->rx_queues_to_use * 4096;
146 plat->tx_sched_algorithm = MTL_TX_ALGORITHM_WRR;
147 plat->tx_queues_cfg[0].weight = 0x09;
148 plat->tx_queues_cfg[1].weight = 0x0A;
149 plat->tx_queues_cfg[2].weight = 0x0B;
150 plat->tx_queues_cfg[3].weight = 0x0C;
151 plat->tx_queues_cfg[4].weight = 0x0D;
152 plat->tx_queues_cfg[5].weight = 0x0E;
153 plat->tx_queues_cfg[6].weight = 0x0F;
154 plat->tx_queues_cfg[7].weight = 0x10;
156 plat->dma_cfg->pbl = 32;
157 plat->dma_cfg->pblx8 = true;
158 plat->dma_cfg->fixed_burst = 0;
159 plat->dma_cfg->mixed_burst = 0;
160 plat->dma_cfg->aal = 0;
162 plat->axi = devm_kzalloc(&pdev->dev, sizeof(*plat->axi),
167 plat->axi->axi_lpi_en = 0;
168 plat->axi->axi_xit_frm = 0;
169 plat->axi->axi_wr_osr_lmt = 1;
170 plat->axi->axi_rd_osr_lmt = 1;
171 plat->axi->axi_blen[0] = 4;
172 plat->axi->axi_blen[1] = 8;
173 plat->axi->axi_blen[2] = 16;
175 plat->ptp_max_adj = plat->clk_ptp_rate;
177 /* Set system clock */
178 plat->stmmac_clk = clk_register_fixed_rate(&pdev->dev,
179 "stmmac-clk", NULL, 0,
182 if (IS_ERR(plat->stmmac_clk)) {
183 dev_warn(&pdev->dev, "Fail to register stmmac-clk\n");
184 plat->stmmac_clk = NULL;
186 clk_prepare_enable(plat->stmmac_clk);
188 /* Set default value for multicast hash bins */
189 plat->multicast_filter_bins = HASH_TABLE_SIZE;
191 /* Set default value for unicast filter entries */
192 plat->unicast_filter_entries = 1;
194 /* Set the maxmtu to a default of JUMBO_LEN */
195 plat->maxmtu = JUMBO_LEN;
200 static int ehl_common_data(struct pci_dev *pdev,
201 struct plat_stmmacenet_data *plat)
205 plat->rx_queues_to_use = 8;
206 plat->tx_queues_to_use = 8;
207 plat->clk_ptp_rate = 200000000;
208 ret = intel_mgbe_common_data(pdev, plat);
215 static int ehl_sgmii_data(struct pci_dev *pdev,
216 struct plat_stmmacenet_data *plat)
220 plat->phy_interface = PHY_INTERFACE_MODE_SGMII;
222 return ehl_common_data(pdev, plat);
225 static struct stmmac_pci_info ehl_sgmii1g_pci_info = {
226 .setup = ehl_sgmii_data,
229 static int ehl_rgmii_data(struct pci_dev *pdev,
230 struct plat_stmmacenet_data *plat)
234 plat->phy_interface = PHY_INTERFACE_MODE_RGMII;
236 return ehl_common_data(pdev, plat);
239 static struct stmmac_pci_info ehl_rgmii1g_pci_info = {
240 .setup = ehl_rgmii_data,
243 static int tgl_common_data(struct pci_dev *pdev,
244 struct plat_stmmacenet_data *plat)
248 plat->rx_queues_to_use = 6;
249 plat->tx_queues_to_use = 4;
250 plat->clk_ptp_rate = 200000000;
251 ret = intel_mgbe_common_data(pdev, plat);
258 static int tgl_sgmii_data(struct pci_dev *pdev,
259 struct plat_stmmacenet_data *plat)
263 plat->phy_interface = PHY_INTERFACE_MODE_SGMII;
264 return tgl_common_data(pdev, plat);
267 static struct stmmac_pci_info tgl_sgmii1g_pci_info = {
268 .setup = tgl_sgmii_data,
271 static const struct stmmac_pci_func_data galileo_stmmac_func_data[] = {
278 static const struct stmmac_pci_dmi_data galileo_stmmac_dmi_data = {
279 .func = galileo_stmmac_func_data,
280 .nfuncs = ARRAY_SIZE(galileo_stmmac_func_data),
283 static const struct stmmac_pci_func_data iot2040_stmmac_func_data[] = {
294 static const struct stmmac_pci_dmi_data iot2040_stmmac_dmi_data = {
295 .func = iot2040_stmmac_func_data,
296 .nfuncs = ARRAY_SIZE(iot2040_stmmac_func_data),
299 static const struct dmi_system_id quark_pci_dmi[] = {
302 DMI_EXACT_MATCH(DMI_BOARD_NAME, "Galileo"),
304 .driver_data = (void *)&galileo_stmmac_dmi_data,
308 DMI_EXACT_MATCH(DMI_BOARD_NAME, "GalileoGen2"),
310 .driver_data = (void *)&galileo_stmmac_dmi_data,
313 * There are 2 types of SIMATIC IOT2000: IOT2020 and IOT2040.
314 * The asset tag "6ES7647-0AA00-0YA2" is only for IOT2020 which
315 * has only one pci network device while other asset tags are
316 * for IOT2040 which has two.
320 DMI_EXACT_MATCH(DMI_BOARD_NAME, "SIMATIC IOT2000"),
321 DMI_EXACT_MATCH(DMI_BOARD_ASSET_TAG,
322 "6ES7647-0AA00-0YA2"),
324 .driver_data = (void *)&galileo_stmmac_dmi_data,
328 DMI_EXACT_MATCH(DMI_BOARD_NAME, "SIMATIC IOT2000"),
330 .driver_data = (void *)&iot2040_stmmac_dmi_data,
335 static int quark_default_data(struct pci_dev *pdev,
336 struct plat_stmmacenet_data *plat)
340 /* Set common default data first */
341 common_default_data(plat);
344 * Refuse to load the driver and register net device if MAC controller
345 * does not connect to any PHY interface.
347 ret = stmmac_pci_find_phy_addr(pdev, quark_pci_dmi);
349 /* Return error to the caller on DMI enabled boards. */
350 if (dmi_get_system_info(DMI_BOARD_NAME))
354 * Galileo boards with old firmware don't support DMI. We always
355 * use 1 here as PHY address, so at least the first found MAC
356 * controller would be probed.
361 plat->bus_id = pci_dev_id(pdev);
362 plat->phy_addr = ret;
363 plat->phy_interface = PHY_INTERFACE_MODE_RMII;
365 plat->dma_cfg->pbl = 16;
366 plat->dma_cfg->pblx8 = true;
367 plat->dma_cfg->fixed_burst = 1;
373 static const struct stmmac_pci_info quark_pci_info = {
374 .setup = quark_default_data,
377 static int snps_gmac5_default_data(struct pci_dev *pdev,
378 struct plat_stmmacenet_data *plat)
384 plat->force_sf_dma_mode = 1;
388 /* Set default value for multicast hash bins */
389 plat->multicast_filter_bins = HASH_TABLE_SIZE;
391 /* Set default value for unicast filter entries */
392 plat->unicast_filter_entries = 1;
394 /* Set the maxmtu to a default of JUMBO_LEN */
395 plat->maxmtu = JUMBO_LEN;
397 /* Set default number of RX and TX queues to use */
398 plat->tx_queues_to_use = 4;
399 plat->rx_queues_to_use = 4;
401 plat->tx_sched_algorithm = MTL_TX_ALGORITHM_WRR;
402 for (i = 0; i < plat->tx_queues_to_use; i++) {
403 plat->tx_queues_cfg[i].use_prio = false;
404 plat->tx_queues_cfg[i].mode_to_use = MTL_QUEUE_DCB;
405 plat->tx_queues_cfg[i].weight = 25;
407 plat->tx_queues_cfg[i].tbs_en = 1;
410 plat->rx_sched_algorithm = MTL_RX_ALGORITHM_SP;
411 for (i = 0; i < plat->rx_queues_to_use; i++) {
412 plat->rx_queues_cfg[i].use_prio = false;
413 plat->rx_queues_cfg[i].mode_to_use = MTL_QUEUE_DCB;
414 plat->rx_queues_cfg[i].pkt_route = 0x0;
415 plat->rx_queues_cfg[i].chan = i;
420 plat->phy_interface = PHY_INTERFACE_MODE_GMII;
422 plat->dma_cfg->pbl = 32;
423 plat->dma_cfg->pblx8 = true;
425 /* Axi Configuration */
426 plat->axi = devm_kzalloc(&pdev->dev, sizeof(*plat->axi), GFP_KERNEL);
430 plat->axi->axi_wr_osr_lmt = 31;
431 plat->axi->axi_rd_osr_lmt = 31;
433 plat->axi->axi_fb = false;
434 plat->axi->axi_blen[0] = 4;
435 plat->axi->axi_blen[1] = 8;
436 plat->axi->axi_blen[2] = 16;
437 plat->axi->axi_blen[3] = 32;
442 static const struct stmmac_pci_info snps_gmac5_pci_info = {
443 .setup = snps_gmac5_default_data,
449 * @pdev: pci device pointer
450 * @id: pointer to table of device id/id's.
452 * Description: This probing function gets called for all PCI devices which
453 * match the ID table and are not "owned" by other driver yet. This function
454 * gets passed a "struct pci_dev *" for each device whose entry in the ID table
455 * matches the device. The probe functions returns zero when the driver choose
456 * to take "ownership" of the device or an error code(-ve no) otherwise.
458 static int stmmac_pci_probe(struct pci_dev *pdev,
459 const struct pci_device_id *id)
461 struct stmmac_pci_info *info = (struct stmmac_pci_info *)id->driver_data;
462 struct plat_stmmacenet_data *plat;
463 struct stmmac_resources res;
467 plat = devm_kzalloc(&pdev->dev, sizeof(*plat), GFP_KERNEL);
471 plat->mdio_bus_data = devm_kzalloc(&pdev->dev,
472 sizeof(*plat->mdio_bus_data),
474 if (!plat->mdio_bus_data)
477 plat->dma_cfg = devm_kzalloc(&pdev->dev, sizeof(*plat->dma_cfg),
482 /* Enable pci device */
483 ret = pci_enable_device(pdev);
485 dev_err(&pdev->dev, "%s: ERROR: failed to enable device\n",
490 /* Get the base address of device */
491 for (i = 0; i < PCI_STD_NUM_BARS; i++) {
492 if (pci_resource_len(pdev, i) == 0)
494 ret = pcim_iomap_regions(pdev, BIT(i), pci_name(pdev));
500 pci_set_master(pdev);
502 ret = info->setup(pdev, plat);
506 pci_enable_msi(pdev);
508 memset(&res, 0, sizeof(res));
509 res.addr = pcim_iomap_table(pdev)[i];
510 res.wol_irq = pdev->irq;
513 return stmmac_dvr_probe(&pdev->dev, plat, &res);
519 * @pdev: platform device pointer
520 * Description: this function calls the main to free the net resources
521 * and releases the PCI resources.
523 static void stmmac_pci_remove(struct pci_dev *pdev)
525 struct net_device *ndev = dev_get_drvdata(&pdev->dev);
526 struct stmmac_priv *priv = netdev_priv(ndev);
529 stmmac_dvr_remove(&pdev->dev);
531 if (priv->plat->stmmac_clk)
532 clk_unregister_fixed_rate(priv->plat->stmmac_clk);
534 for (i = 0; i < PCI_STD_NUM_BARS; i++) {
535 if (pci_resource_len(pdev, i) == 0)
537 pcim_iounmap_regions(pdev, BIT(i));
541 pci_disable_device(pdev);
544 static int __maybe_unused stmmac_pci_suspend(struct device *dev)
546 struct pci_dev *pdev = to_pci_dev(dev);
549 ret = stmmac_suspend(dev);
553 ret = pci_save_state(pdev);
557 pci_disable_device(pdev);
558 pci_wake_from_d3(pdev, true);
562 static int __maybe_unused stmmac_pci_resume(struct device *dev)
564 struct pci_dev *pdev = to_pci_dev(dev);
567 pci_restore_state(pdev);
568 pci_set_power_state(pdev, PCI_D0);
570 ret = pci_enable_device(pdev);
574 pci_set_master(pdev);
576 return stmmac_resume(dev);
579 static SIMPLE_DEV_PM_OPS(stmmac_pm_ops, stmmac_pci_suspend, stmmac_pci_resume);
581 /* synthetic ID, no official vendor */
582 #define PCI_VENDOR_ID_STMMAC 0x700
584 #define STMMAC_QUARK_ID 0x0937
585 #define STMMAC_DEVICE_ID 0x1108
586 #define STMMAC_EHL_RGMII1G_ID 0x4b30
587 #define STMMAC_EHL_SGMII1G_ID 0x4b31
588 #define STMMAC_TGL_SGMII1G_ID 0xa0ac
589 #define STMMAC_GMAC5_ID 0x7102
591 #define STMMAC_DEVICE(vendor_id, dev_id, info) { \
592 PCI_VDEVICE(vendor_id, dev_id), \
593 .driver_data = (kernel_ulong_t)&info \
596 static const struct pci_device_id stmmac_id_table[] = {
597 STMMAC_DEVICE(STMMAC, STMMAC_DEVICE_ID, stmmac_pci_info),
598 STMMAC_DEVICE(STMICRO, PCI_DEVICE_ID_STMICRO_MAC, stmmac_pci_info),
599 STMMAC_DEVICE(INTEL, STMMAC_QUARK_ID, quark_pci_info),
600 STMMAC_DEVICE(INTEL, STMMAC_EHL_RGMII1G_ID, ehl_rgmii1g_pci_info),
601 STMMAC_DEVICE(INTEL, STMMAC_EHL_SGMII1G_ID, ehl_sgmii1g_pci_info),
602 STMMAC_DEVICE(INTEL, STMMAC_TGL_SGMII1G_ID, tgl_sgmii1g_pci_info),
603 STMMAC_DEVICE(SYNOPSYS, STMMAC_GMAC5_ID, snps_gmac5_pci_info),
607 MODULE_DEVICE_TABLE(pci, stmmac_id_table);
609 static struct pci_driver stmmac_pci_driver = {
610 .name = STMMAC_RESOURCE_NAME,
611 .id_table = stmmac_id_table,
612 .probe = stmmac_pci_probe,
613 .remove = stmmac_pci_remove,
615 .pm = &stmmac_pm_ops,
619 module_pci_driver(stmmac_pci_driver);
621 MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet PCI driver");
622 MODULE_AUTHOR("Rayagond Kokatanur <rayagond.kokatanur@vayavyalabs.com>");
623 MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>");
624 MODULE_LICENSE("GPL");