drivers/net/ethernet/ti/netcp_ethss.c

   1 /*
   2  * Keystone GBE and XGBE subsystem code
   3  *
   4  * Copyright (C) 2014 Texas Instruments Incorporated
   5  * Authors:     Sandeep Nair <sandeep_n@ti.com>
   6  *              Sandeep Paulraj <s-paulraj@ti.com>
   7  *              Cyril Chemparathy <cyril@ti.com>
   8  *              Santosh Shilimkar <santosh.shilimkar@ti.com>
   9  *              Wingman Kwok <w-kwok2@ti.com>
  10  *
  11  * This program is free software; you can redistribute it and/or
  12  * modify it under the terms of the GNU General Public License as
  13  * published by the Free Software Foundation version 2.
  14  *
  15  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  16  * kind, whether express or implied; without even the implied warranty
  17  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  */
  20
  21 #include <linux/io.h>
  22 #include <linux/module.h>
  23 #include <linux/of_mdio.h>
  24 #include <linux/of_address.h>
  25 #include <linux/if_vlan.h>
  26 #include <linux/ptp_classify.h>
  27 #include <linux/net_tstamp.h>
  28 #include <linux/ethtool.h>
  29
  30 #include "cpsw.h"
  31 #include "cpsw_ale.h"
  32 #include "netcp.h"
  33 #include "cpts.h"
  34
  35 #define NETCP_DRIVER_NAME               "TI KeyStone Ethernet Driver"
  36 #define NETCP_DRIVER_VERSION            "v1.0"
  37
  38 #define GBE_IDENT(reg)                  ((reg >> 16) & 0xffff)
  39 #define GBE_MAJOR_VERSION(reg)          (reg >> 8 & 0x7)
  40 #define GBE_MINOR_VERSION(reg)          (reg & 0xff)
  41 #define GBE_RTL_VERSION(reg)            ((reg >> 11) & 0x1f)
  42
  43 /* 1G Ethernet SS defines */
  44 #define GBE_MODULE_NAME                 "netcp-gbe"
  45 #define GBE_SS_VERSION_14               0x4ed2
  46
  47 #define GBE_SS_REG_INDEX                0
  48 #define GBE_SGMII34_REG_INDEX           1
  49 #define GBE_SM_REG_INDEX                2
  50 /* offset relative to base of GBE_SS_REG_INDEX */
  51 #define GBE13_SGMII_MODULE_OFFSET       0x100
  52 /* offset relative to base of GBE_SM_REG_INDEX */
  53 #define GBE13_HOST_PORT_OFFSET          0x34
  54 #define GBE13_SLAVE_PORT_OFFSET         0x60
  55 #define GBE13_EMAC_OFFSET               0x100
  56 #define GBE13_SLAVE_PORT2_OFFSET        0x200
  57 #define GBE13_HW_STATS_OFFSET           0x300
  58 #define GBE13_CPTS_OFFSET               0x500
  59 #define GBE13_ALE_OFFSET                0x600
  60 #define GBE13_HOST_PORT_NUM             0
  61 #define GBE13_NUM_ALE_ENTRIES           1024
  62
  63 /* 1G Ethernet NU SS defines */
  64 #define GBENU_MODULE_NAME               "netcp-gbenu"
  65 #define GBE_SS_ID_NU                    0x4ee6
  66 #define GBE_SS_ID_2U                    0x4ee8
  67
  68 #define IS_SS_ID_MU(d) \
  69         ((GBE_IDENT((d)->ss_version) == GBE_SS_ID_NU) || \
  70          (GBE_IDENT((d)->ss_version) == GBE_SS_ID_2U))
  71
  72 #define IS_SS_ID_NU(d) \
  73         (GBE_IDENT((d)->ss_version) == GBE_SS_ID_NU)
  74
  75 #define IS_SS_ID_VER_14(d) \
  76         (GBE_IDENT((d)->ss_version) == GBE_SS_VERSION_14)
  77 #define IS_SS_ID_2U(d) \
  78         (GBE_IDENT((d)->ss_version) == GBE_SS_ID_2U)
  79
  80 #define GBENU_SS_REG_INDEX              0
  81 #define GBENU_SM_REG_INDEX              1
  82 #define GBENU_SGMII_MODULE_OFFSET       0x100
  83 #define GBENU_HOST_PORT_OFFSET          0x1000
  84 #define GBENU_SLAVE_PORT_OFFSET         0x2000
  85 #define GBENU_EMAC_OFFSET               0x2330
  86 #define GBENU_HW_STATS_OFFSET           0x1a000
  87 #define GBENU_CPTS_OFFSET               0x1d000
  88 #define GBENU_ALE_OFFSET                0x1e000
  89 #define GBENU_HOST_PORT_NUM             0
  90 #define GBENU_SGMII_MODULE_SIZE         0x100
  91
  92 /* 10G Ethernet SS defines */
  93 #define XGBE_MODULE_NAME                "netcp-xgbe"
  94 #define XGBE_SS_VERSION_10              0x4ee4
  95
  96 #define XGBE_SS_REG_INDEX               0
  97 #define XGBE_SM_REG_INDEX               1
  98 #define XGBE_SERDES_REG_INDEX           2
  99
 100 /* offset relative to base of XGBE_SS_REG_INDEX */
 101 #define XGBE10_SGMII_MODULE_OFFSET      0x100
 102 #define IS_SS_ID_XGBE(d)                ((d)->ss_version == XGBE_SS_VERSION_10)
 103 /* offset relative to base of XGBE_SM_REG_INDEX */
 104 #define XGBE10_HOST_PORT_OFFSET         0x34
 105 #define XGBE10_SLAVE_PORT_OFFSET        0x64
 106 #define XGBE10_EMAC_OFFSET              0x400
 107 #define XGBE10_CPTS_OFFSET              0x600
 108 #define XGBE10_ALE_OFFSET               0x700
 109 #define XGBE10_HW_STATS_OFFSET          0x800
 110 #define XGBE10_HOST_PORT_NUM            0
 111 #define XGBE10_NUM_ALE_ENTRIES          2048
 112
 113 #define GBE_TIMER_INTERVAL                      (HZ / 2)
 114
 115 /* Soft reset register values */
 116 #define SOFT_RESET_MASK                         BIT(0)
 117 #define SOFT_RESET                              BIT(0)
 118 #define DEVICE_EMACSL_RESET_POLL_COUNT          100
 119 #define GMACSL_RET_WARN_RESET_INCOMPLETE        -2
 120
 121 #define MACSL_RX_ENABLE_CSF                     BIT(23)
 122 #define MACSL_ENABLE_EXT_CTL                    BIT(18)
 123 #define MACSL_XGMII_ENABLE                      BIT(13)
 124 #define MACSL_XGIG_MODE                         BIT(8)
 125 #define MACSL_GIG_MODE                          BIT(7)
 126 #define MACSL_GMII_ENABLE                       BIT(5)
 127 #define MACSL_FULLDUPLEX                        BIT(0)
 128
 129 #define GBE_CTL_P0_ENABLE                       BIT(2)
 130 #define ETH_SW_CTL_P0_TX_CRC_REMOVE             BIT(13)
 131 #define GBE13_REG_VAL_STAT_ENABLE_ALL           0xff
 132 #define XGBE_REG_VAL_STAT_ENABLE_ALL            0xf
 133 #define GBE_STATS_CD_SEL                        BIT(28)
 134
 135 #define GBE_PORT_MASK(x)                        (BIT(x) - 1)
 136 #define GBE_MASK_NO_PORTS                       0
 137
 138 #define GBE_DEF_1G_MAC_CONTROL                                  \
 139                 (MACSL_GIG_MODE | MACSL_GMII_ENABLE |           \
 140                  MACSL_ENABLE_EXT_CTL | MACSL_RX_ENABLE_CSF)
 141
 142 #define GBE_DEF_10G_MAC_CONTROL                         \
 143                 (MACSL_XGIG_MODE | MACSL_XGMII_ENABLE |         \
 144                  MACSL_ENABLE_EXT_CTL | MACSL_RX_ENABLE_CSF)
 145
 146 #define GBE_STATSA_MODULE                       0
 147 #define GBE_STATSB_MODULE                       1
 148 #define GBE_STATSC_MODULE                       2
 149 #define GBE_STATSD_MODULE                       3
 150
 151 #define GBENU_STATS0_MODULE                     0
 152 #define GBENU_STATS1_MODULE                     1
 153 #define GBENU_STATS2_MODULE                     2
 154 #define GBENU_STATS3_MODULE                     3
 155 #define GBENU_STATS4_MODULE                     4
 156 #define GBENU_STATS5_MODULE                     5
 157 #define GBENU_STATS6_MODULE                     6
 158 #define GBENU_STATS7_MODULE                     7
 159 #define GBENU_STATS8_MODULE                     8
 160
 161 #define XGBE_STATS0_MODULE                      0
 162 #define XGBE_STATS1_MODULE                      1
 163 #define XGBE_STATS2_MODULE                      2
 164
 165 /* s: 0-based slave_port */
 166 #define SGMII_BASE(d, s) \
 167         (((s) < 2) ? (d)->sgmii_port_regs : (d)->sgmii_port34_regs)
 168
 169 #define GBE_TX_QUEUE                            648
 170 #define GBE_TXHOOK_ORDER                        0
 171 #define GBE_RXHOOK_ORDER                        0
 172 #define GBE_DEFAULT_ALE_AGEOUT                  30
 173 #define SLAVE_LINK_IS_XGMII(s) ((s)->link_interface >= XGMII_LINK_MAC_PHY)
 174 #define SLAVE_LINK_IS_RGMII(s) \
 175         (((s)->link_interface >= RGMII_LINK_MAC_PHY) && \
 176          ((s)->link_interface <= RGMII_LINK_MAC_PHY_NO_MDIO))
 177 #define SLAVE_LINK_IS_SGMII(s) \
 178         ((s)->link_interface <= SGMII_LINK_MAC_PHY_NO_MDIO)
 179 #define NETCP_LINK_STATE_INVALID                -1
 180
 181 #define GBE_SET_REG_OFS(p, rb, rn) p->rb##_ofs.rn = \
 182                 offsetof(struct gbe##_##rb, rn)
 183 #define GBENU_SET_REG_OFS(p, rb, rn) p->rb##_ofs.rn = \
 184                 offsetof(struct gbenu##_##rb, rn)
 185 #define XGBE_SET_REG_OFS(p, rb, rn) p->rb##_ofs.rn = \
 186                 offsetof(struct xgbe##_##rb, rn)
 187 #define GBE_REG_ADDR(p, rb, rn) (p->rb + p->rb##_ofs.rn)
 188
 189 #define HOST_TX_PRI_MAP_DEFAULT                 0x00000000
 190
 191 #if IS_ENABLED(CONFIG_TI_CPTS)
 192 /* Px_TS_CTL register fields */
 193 #define TS_RX_ANX_F_EN                          BIT(0)
 194 #define TS_RX_VLAN_LT1_EN                       BIT(1)
 195 #define TS_RX_VLAN_LT2_EN                       BIT(2)
 196 #define TS_RX_ANX_D_EN                          BIT(3)
 197 #define TS_TX_ANX_F_EN                          BIT(4)
 198 #define TS_TX_VLAN_LT1_EN                       BIT(5)
 199 #define TS_TX_VLAN_LT2_EN                       BIT(6)
 200 #define TS_TX_ANX_D_EN                          BIT(7)
 201 #define TS_LT2_EN                               BIT(8)
 202 #define TS_RX_ANX_E_EN                          BIT(9)
 203 #define TS_TX_ANX_E_EN                          BIT(10)
 204 #define TS_MSG_TYPE_EN_SHIFT                    16
 205 #define TS_MSG_TYPE_EN_MASK                     0xffff
 206
 207 /* Px_TS_SEQ_LTYPE register fields */
 208 #define TS_SEQ_ID_OFS_SHIFT                     16
 209 #define TS_SEQ_ID_OFS_MASK                      0x3f
 210
 211 /* Px_TS_CTL_LTYPE2 register fields */
 212 #define TS_107                                  BIT(16)
 213 #define TS_129                                  BIT(17)
 214 #define TS_130                                  BIT(18)
 215 #define TS_131                                  BIT(19)
 216 #define TS_132                                  BIT(20)
 217 #define TS_319                                  BIT(21)
 218 #define TS_320                                  BIT(22)
 219 #define TS_TTL_NONZERO                          BIT(23)
 220 #define TS_UNI_EN                               BIT(24)
 221 #define TS_UNI_EN_SHIFT                         24
 222
 223 #define TS_TX_ANX_ALL_EN         \
 224         (TS_TX_ANX_D_EN | TS_TX_ANX_E_EN | TS_TX_ANX_F_EN)
 225
 226 #define TS_RX_ANX_ALL_EN         \
 227         (TS_RX_ANX_D_EN | TS_RX_ANX_E_EN | TS_RX_ANX_F_EN)
 228
 229 #define TS_CTL_DST_PORT                         TS_319
 230 #define TS_CTL_DST_PORT_SHIFT                   21
 231
 232 #define TS_CTL_MADDR_ALL        \
 233         (TS_107 | TS_129 | TS_130 | TS_131 | TS_132)
 234
 235 #define TS_CTL_MADDR_SHIFT                      16
 236
 237 /* The PTP event messages - Sync, Delay_Req, Pdelay_Req, and Pdelay_Resp. */
 238 #define EVENT_MSG_BITS (BIT(0) | BIT(1) | BIT(2) | BIT(3))
 239 #endif /* CONFIG_TI_CPTS */
 240
 241 struct xgbe_ss_regs {
 242         u32     id_ver;
 243         u32     synce_count;
 244         u32     synce_mux;
 245         u32     control;
 246 };
 247
 248 struct xgbe_switch_regs {
 249         u32     id_ver;
 250         u32     control;
 251         u32     emcontrol;
 252         u32     stat_port_en;
 253         u32     ptype;
 254         u32     soft_idle;
 255         u32     thru_rate;
 256         u32     gap_thresh;
 257         u32     tx_start_wds;
 258         u32     flow_control;
 259         u32     cppi_thresh;
 260 };
 261
 262 struct xgbe_port_regs {
 263         u32     blk_cnt;
 264         u32     port_vlan;
 265         u32     tx_pri_map;
 266         u32     sa_lo;
 267         u32     sa_hi;
 268         u32     ts_ctl;
 269         u32     ts_seq_ltype;
 270         u32     ts_vlan;
 271         u32     ts_ctl_ltype2;
 272         u32     ts_ctl2;
 273         u32     control;
 274 };
 275
 276 struct xgbe_host_port_regs {
 277         u32     blk_cnt;
 278         u32     port_vlan;
 279         u32     tx_pri_map;
 280         u32     src_id;
 281         u32     rx_pri_map;
 282         u32     rx_maxlen;
 283 };
 284
 285 struct xgbe_emac_regs {
 286         u32     id_ver;
 287         u32     mac_control;
 288         u32     mac_status;
 289         u32     soft_reset;
 290         u32     rx_maxlen;
 291         u32     __reserved_0;
 292         u32     rx_pause;
 293         u32     tx_pause;
 294         u32     em_control;
 295         u32     __reserved_1;
 296         u32     tx_gap;
 297         u32     rsvd[4];
 298 };
 299
 300 struct xgbe_host_hw_stats {
 301         u32     rx_good_frames;
 302         u32     rx_broadcast_frames;
 303         u32     rx_multicast_frames;
 304         u32     __rsvd_0[3];
 305         u32     rx_oversized_frames;
 306         u32     __rsvd_1;
 307         u32     rx_undersized_frames;
 308         u32     __rsvd_2;
 309         u32     overrun_type4;
 310         u32     overrun_type5;
 311         u32     rx_bytes;
 312         u32     tx_good_frames;
 313         u32     tx_broadcast_frames;
 314         u32     tx_multicast_frames;
 315         u32     __rsvd_3[9];
 316         u32     tx_bytes;
 317         u32     tx_64byte_frames;
 318         u32     tx_65_to_127byte_frames;
 319         u32     tx_128_to_255byte_frames;
 320         u32     tx_256_to_511byte_frames;
 321         u32     tx_512_to_1023byte_frames;
 322         u32     tx_1024byte_frames;
 323         u32     net_bytes;
 324         u32     rx_sof_overruns;
 325         u32     rx_mof_overruns;
 326         u32     rx_dma_overruns;
 327 };
 328
 329 struct xgbe_hw_stats {
 330         u32     rx_good_frames;
 331         u32     rx_broadcast_frames;
 332         u32     rx_multicast_frames;
 333         u32     rx_pause_frames;
 334         u32     rx_crc_errors;
 335         u32     rx_align_code_errors;
 336         u32     rx_oversized_frames;
 337         u32     rx_jabber_frames;
 338         u32     rx_undersized_frames;
 339         u32     rx_fragments;
 340         u32     overrun_type4;
 341         u32     overrun_type5;
 342         u32     rx_bytes;
 343         u32     tx_good_frames;
 344         u32     tx_broadcast_frames;
 345         u32     tx_multicast_frames;
 346         u32     tx_pause_frames;
 347         u32     tx_deferred_frames;
 348         u32     tx_collision_frames;
 349         u32     tx_single_coll_frames;
 350         u32     tx_mult_coll_frames;
 351         u32     tx_excessive_collisions;
 352         u32     tx_late_collisions;
 353         u32     tx_underrun;
 354         u32     tx_carrier_sense_errors;
 355         u32     tx_bytes;
 356         u32     tx_64byte_frames;
 357         u32     tx_65_to_127byte_frames;
 358         u32     tx_128_to_255byte_frames;
 359         u32     tx_256_to_511byte_frames;
 360         u32     tx_512_to_1023byte_frames;
 361         u32     tx_1024byte_frames;
 362         u32     net_bytes;
 363         u32     rx_sof_overruns;
 364         u32     rx_mof_overruns;
 365         u32     rx_dma_overruns;
 366 };
 367
 368 struct gbenu_ss_regs {
 369         u32     id_ver;
 370         u32     synce_count;            /* NU */
 371         u32     synce_mux;              /* NU */
 372         u32     control;                /* 2U */
 373         u32     __rsvd_0[2];            /* 2U */
 374         u32     rgmii_status;           /* 2U */
 375         u32     ss_status;              /* 2U */
 376 };
 377
 378 struct gbenu_switch_regs {
 379         u32     id_ver;
 380         u32     control;
 381         u32     __rsvd_0[2];
 382         u32     emcontrol;
 383         u32     stat_port_en;
 384         u32     ptype;                  /* NU */
 385         u32     soft_idle;
 386         u32     thru_rate;              /* NU */
 387         u32     gap_thresh;             /* NU */
 388         u32     tx_start_wds;           /* NU */
 389         u32     eee_prescale;           /* 2U */
 390         u32     tx_g_oflow_thresh_set;  /* NU */
 391         u32     tx_g_oflow_thresh_clr;  /* NU */
 392         u32     tx_g_buf_thresh_set_l;  /* NU */
 393         u32     tx_g_buf_thresh_set_h;  /* NU */
 394         u32     tx_g_buf_thresh_clr_l;  /* NU */
 395         u32     tx_g_buf_thresh_clr_h;  /* NU */
 396 };
 397
 398 struct gbenu_port_regs {
 399         u32     __rsvd_0;
 400         u32     control;
 401         u32     max_blks;               /* 2U */
 402         u32     mem_align1;
 403         u32     blk_cnt;
 404         u32     port_vlan;
 405         u32     tx_pri_map;             /* NU */
 406         u32     pri_ctl;                /* 2U */
 407         u32     rx_pri_map;
 408         u32     rx_maxlen;
 409         u32     tx_blks_pri;            /* NU */
 410         u32     __rsvd_1;
 411         u32     idle2lpi;               /* 2U */
 412         u32     lpi2idle;               /* 2U */
 413         u32     eee_status;             /* 2U */
 414         u32     __rsvd_2;
 415         u32     __rsvd_3[176];          /* NU: more to add */
 416         u32     __rsvd_4[2];
 417         u32     sa_lo;
 418         u32     sa_hi;
 419         u32     ts_ctl;
 420         u32     ts_seq_ltype;
 421         u32     ts_vlan;
 422         u32     ts_ctl_ltype2;
 423         u32     ts_ctl2;
 424 };
 425
 426 struct gbenu_host_port_regs {
 427         u32     __rsvd_0;
 428         u32     control;
 429         u32     flow_id_offset;         /* 2U */
 430         u32     __rsvd_1;
 431         u32     blk_cnt;
 432         u32     port_vlan;
 433         u32     tx_pri_map;             /* NU */
 434         u32     pri_ctl;
 435         u32     rx_pri_map;
 436         u32     rx_maxlen;
 437         u32     tx_blks_pri;            /* NU */
 438         u32     __rsvd_2;
 439         u32     idle2lpi;               /* 2U */
 440         u32     lpi2wake;               /* 2U */
 441         u32     eee_status;             /* 2U */
 442         u32     __rsvd_3;
 443         u32     __rsvd_4[184];          /* NU */
 444         u32     host_blks_pri;          /* NU */
 445 };
 446
 447 struct gbenu_emac_regs {
 448         u32     mac_control;
 449         u32     mac_status;
 450         u32     soft_reset;
 451         u32     boff_test;
 452         u32     rx_pause;
 453         u32     __rsvd_0[11];           /* NU */
 454         u32     tx_pause;
 455         u32     __rsvd_1[11];           /* NU */
 456         u32     em_control;
 457         u32     tx_gap;
 458 };
 459
 460 /* Some hw stat regs are applicable to slave port only.
 461  * This is handled by gbenu_et_stats struct.  Also some
 462  * are for SS version NU and some are for 2U.
 463  */
 464 struct gbenu_hw_stats {
 465         u32     rx_good_frames;
 466         u32     rx_broadcast_frames;
 467         u32     rx_multicast_frames;
 468         u32     rx_pause_frames;                /* slave */
 469         u32     rx_crc_errors;
 470         u32     rx_align_code_errors;           /* slave */
 471         u32     rx_oversized_frames;
 472         u32     rx_jabber_frames;               /* slave */
 473         u32     rx_undersized_frames;
 474         u32     rx_fragments;                   /* slave */
 475         u32     ale_drop;
 476         u32     ale_overrun_drop;
 477         u32     rx_bytes;
 478         u32     tx_good_frames;
 479         u32     tx_broadcast_frames;
 480         u32     tx_multicast_frames;
 481         u32     tx_pause_frames;                /* slave */
 482         u32     tx_deferred_frames;             /* slave */
 483         u32     tx_collision_frames;            /* slave */
 484         u32     tx_single_coll_frames;          /* slave */
 485         u32     tx_mult_coll_frames;            /* slave */
 486         u32     tx_excessive_collisions;        /* slave */
 487         u32     tx_late_collisions;             /* slave */
 488         u32     rx_ipg_error;                   /* slave 10G only */
 489         u32     tx_carrier_sense_errors;        /* slave */
 490         u32     tx_bytes;
 491         u32     tx_64B_frames;
 492         u32     tx_65_to_127B_frames;
 493         u32     tx_128_to_255B_frames;
 494         u32     tx_256_to_511B_frames;
 495         u32     tx_512_to_1023B_frames;
 496         u32     tx_1024B_frames;
 497         u32     net_bytes;
 498         u32     rx_bottom_fifo_drop;
 499         u32     rx_port_mask_drop;
 500         u32     rx_top_fifo_drop;
 501         u32     ale_rate_limit_drop;
 502         u32     ale_vid_ingress_drop;
 503         u32     ale_da_eq_sa_drop;
 504         u32     __rsvd_0[3];
 505         u32     ale_unknown_ucast;
 506         u32     ale_unknown_ucast_bytes;
 507         u32     ale_unknown_mcast;
 508         u32     ale_unknown_mcast_bytes;
 509         u32     ale_unknown_bcast;
 510         u32     ale_unknown_bcast_bytes;
 511         u32     ale_pol_match;
 512         u32     ale_pol_match_red;              /* NU */
 513         u32     ale_pol_match_yellow;           /* NU */
 514         u32     __rsvd_1[44];
 515         u32     tx_mem_protect_err;
 516         /* following NU only */
 517         u32     tx_pri0;
 518         u32     tx_pri1;
 519         u32     tx_pri2;
 520         u32     tx_pri3;
 521         u32     tx_pri4;
 522         u32     tx_pri5;
 523         u32     tx_pri6;
 524         u32     tx_pri7;
 525         u32     tx_pri0_bcnt;
 526         u32     tx_pri1_bcnt;
 527         u32     tx_pri2_bcnt;
 528         u32     tx_pri3_bcnt;
 529         u32     tx_pri4_bcnt;
 530         u32     tx_pri5_bcnt;
 531         u32     tx_pri6_bcnt;
 532         u32     tx_pri7_bcnt;
 533         u32     tx_pri0_drop;
 534         u32     tx_pri1_drop;
 535         u32     tx_pri2_drop;
 536         u32     tx_pri3_drop;
 537         u32     tx_pri4_drop;
 538         u32     tx_pri5_drop;
 539         u32     tx_pri6_drop;
 540         u32     tx_pri7_drop;
 541         u32     tx_pri0_drop_bcnt;
 542         u32     tx_pri1_drop_bcnt;
 543         u32     tx_pri2_drop_bcnt;
 544         u32     tx_pri3_drop_bcnt;
 545         u32     tx_pri4_drop_bcnt;
 546         u32     tx_pri5_drop_bcnt;
 547         u32     tx_pri6_drop_bcnt;
 548         u32     tx_pri7_drop_bcnt;
 549 };
 550
 551 #define GBENU_HW_STATS_REG_MAP_SZ       0x200
 552
 553 struct gbe_ss_regs {
 554         u32     id_ver;
 555         u32     synce_count;
 556         u32     synce_mux;
 557 };
 558
 559 struct gbe_ss_regs_ofs {
 560         u16     id_ver;
 561         u16     control;
 562         u16     rgmii_status; /* 2U */
 563 };
 564
 565 struct gbe_switch_regs {
 566         u32     id_ver;
 567         u32     control;
 568         u32     soft_reset;
 569         u32     stat_port_en;
 570         u32     ptype;
 571         u32     soft_idle;
 572         u32     thru_rate;
 573         u32     gap_thresh;
 574         u32     tx_start_wds;
 575         u32     flow_control;
 576 };
 577
 578 struct gbe_switch_regs_ofs {
 579         u16     id_ver;
 580         u16     control;
 581         u16     soft_reset;
 582         u16     emcontrol;
 583         u16     stat_port_en;
 584         u16     ptype;
 585         u16     flow_control;
 586 };
 587
 588 struct gbe_port_regs {
 589         u32     max_blks;
 590         u32     blk_cnt;
 591         u32     port_vlan;
 592         u32     tx_pri_map;
 593         u32     sa_lo;
 594         u32     sa_hi;
 595         u32     ts_ctl;
 596         u32     ts_seq_ltype;
 597         u32     ts_vlan;
 598         u32     ts_ctl_ltype2;
 599         u32     ts_ctl2;
 600 };
 601
 602 struct gbe_port_regs_ofs {
 603         u16     port_vlan;
 604         u16     tx_pri_map;
 605         u16     rx_pri_map;
 606         u16     sa_lo;
 607         u16     sa_hi;
 608         u16     ts_ctl;
 609         u16     ts_seq_ltype;
 610         u16     ts_vlan;
 611         u16     ts_ctl_ltype2;
 612         u16     ts_ctl2;
 613         u16     rx_maxlen;      /* 2U, NU */
 614 };
 615
 616 struct gbe_host_port_regs {
 617         u32     src_id;
 618         u32     port_vlan;
 619         u32     rx_pri_map;
 620         u32     rx_maxlen;
 621 };
 622
 623 struct gbe_host_port_regs_ofs {
 624         u16     port_vlan;
 625         u16     tx_pri_map;
 626         u16     rx_maxlen;
 627 };
 628
 629 struct gbe_emac_regs {
 630         u32     id_ver;
 631         u32     mac_control;
 632         u32     mac_status;
 633         u32     soft_reset;
 634         u32     rx_maxlen;
 635         u32     __reserved_0;
 636         u32     rx_pause;
 637         u32     tx_pause;
 638         u32     __reserved_1;
 639         u32     rx_pri_map;
 640         u32     rsvd[6];
 641 };
 642
 643 struct gbe_emac_regs_ofs {
 644         u16     mac_control;
 645         u16     soft_reset;
 646         u16     rx_maxlen;
 647 };
 648
 649 struct gbe_hw_stats {
 650         u32     rx_good_frames;
 651         u32     rx_broadcast_frames;
 652         u32     rx_multicast_frames;
 653         u32     rx_pause_frames;
 654         u32     rx_crc_errors;
 655         u32     rx_align_code_errors;
 656         u32     rx_oversized_frames;
 657         u32     rx_jabber_frames;
 658         u32     rx_undersized_frames;
 659         u32     rx_fragments;
 660         u32     __pad_0[2];
 661         u32     rx_bytes;
 662         u32     tx_good_frames;
 663         u32     tx_broadcast_frames;
 664         u32     tx_multicast_frames;
 665         u32     tx_pause_frames;
 666         u32     tx_deferred_frames;
 667         u32     tx_collision_frames;
 668         u32     tx_single_coll_frames;
 669         u32     tx_mult_coll_frames;
 670         u32     tx_excessive_collisions;
 671         u32     tx_late_collisions;
 672         u32     tx_underrun;
 673         u32     tx_carrier_sense_errors;
 674         u32     tx_bytes;
 675         u32     tx_64byte_frames;
 676         u32     tx_65_to_127byte_frames;
 677         u32     tx_128_to_255byte_frames;
 678         u32     tx_256_to_511byte_frames;
 679         u32     tx_512_to_1023byte_frames;
 680         u32     tx_1024byte_frames;
 681         u32     net_bytes;
 682         u32     rx_sof_overruns;
 683         u32     rx_mof_overruns;
 684         u32     rx_dma_overruns;
 685 };
 686
 687 #define GBE_MAX_HW_STAT_MODS                    9
 688 #define GBE_HW_STATS_REG_MAP_SZ                 0x100
 689
 690 struct ts_ctl {
 691         int     uni;
 692         u8      dst_port_map;
 693         u8      maddr_map;
 694         u8      ts_mcast_type;
 695 };
 696
 697 struct gbe_slave {
 698         void __iomem                    *port_regs;
 699         void __iomem                    *emac_regs;
 700         struct gbe_port_regs_ofs        port_regs_ofs;
 701         struct gbe_emac_regs_ofs        emac_regs_ofs;
 702         int                             slave_num; /* 0 based logical number */
 703         int                             port_num;  /* actual port number */
 704         atomic_t                        link_state;
 705         bool                            open;
 706         struct phy_device               *phy;
 707         u32                             link_interface;
 708         u32                             mac_control;
 709         u8                              phy_port_t;
 710         struct device_node              *phy_node;
 711         struct ts_ctl                   ts_ctl;
 712         struct list_head                slave_list;
 713 };
 714
 715 struct gbe_priv {
 716         struct device                   *dev;
 717         struct netcp_device             *netcp_device;
 718         struct timer_list               timer;
 719         u32                             num_slaves;
 720         u32                             ale_entries;
 721         u32                             ale_ports;
 722         bool                            enable_ale;
 723         u8                              max_num_slaves;
 724         u8                              max_num_ports; /* max_num_slaves + 1 */
 725         u8                              num_stats_mods;
 726         struct netcp_tx_pipe            tx_pipe;
 727
 728         int                             host_port;
 729         u32                             rx_packet_max;
 730         u32                             ss_version;
 731         u32                             stats_en_mask;
 732
 733         void __iomem                    *ss_regs;
 734         void __iomem                    *switch_regs;
 735         void __iomem                    *host_port_regs;
 736         void __iomem                    *ale_reg;
 737         void __iomem                    *cpts_reg;
 738         void __iomem                    *sgmii_port_regs;
 739         void __iomem                    *sgmii_port34_regs;
 740         void __iomem                    *xgbe_serdes_regs;
 741         void __iomem                    *hw_stats_regs[GBE_MAX_HW_STAT_MODS];
 742
 743         struct gbe_ss_regs_ofs          ss_regs_ofs;
 744         struct gbe_switch_regs_ofs      switch_regs_ofs;
 745         struct gbe_host_port_regs_ofs   host_port_regs_ofs;
 746
 747         struct cpsw_ale                 *ale;
 748         unsigned int                    tx_queue_id;
 749         const char                      *dma_chan_name;
 750
 751         struct list_head                gbe_intf_head;
 752         struct list_head                secondary_slaves;
 753         struct net_device               *dummy_ndev;
 754
 755         u64                             *hw_stats;
 756         u32                             *hw_stats_prev;
 757         const struct netcp_ethtool_stat *et_stats;
 758         int                             num_et_stats;
 759         /*  Lock for updating the hwstats */
 760         spinlock_t                      hw_stats_lock;
 761
 762         int                             cpts_registered;
 763         struct cpts                     *cpts;
 764 };
 765
 766 struct gbe_intf {
 767         struct net_device       *ndev;
 768         struct device           *dev;
 769         struct gbe_priv         *gbe_dev;
 770         struct netcp_tx_pipe    tx_pipe;
 771         struct gbe_slave        *slave;
 772         struct list_head        gbe_intf_list;
 773         unsigned long           active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
 774 };
 775
 776 static struct netcp_module gbe_module;
 777 static struct netcp_module xgbe_module;
 778
 779 /* Statistic management */
 780 struct netcp_ethtool_stat {
 781         char desc[ETH_GSTRING_LEN];
 782         int type;
 783         u32 size;
 784         int offset;
 785 };
 786
 787 #define GBE_STATSA_INFO(field)                                          \
 788 {                                                                       \
 789         "GBE_A:"#field, GBE_STATSA_MODULE,                              \
 790         FIELD_SIZEOF(struct gbe_hw_stats, field),                       \
 791         offsetof(struct gbe_hw_stats, field)                            \
 792 }
 793
 794 #define GBE_STATSB_INFO(field)                                          \
 795 {                                                                       \
 796         "GBE_B:"#field, GBE_STATSB_MODULE,                              \
 797         FIELD_SIZEOF(struct gbe_hw_stats, field),                       \
 798         offsetof(struct gbe_hw_stats, field)                            \
 799 }
 800
 801 #define GBE_STATSC_INFO(field)                                          \
 802 {                                                                       \
 803         "GBE_C:"#field, GBE_STATSC_MODULE,                              \
 804         FIELD_SIZEOF(struct gbe_hw_stats, field),                       \
 805         offsetof(struct gbe_hw_stats, field)                            \
 806 }
 807
 808 #define GBE_STATSD_INFO(field)                                          \
 809 {                                                                       \
 810         "GBE_D:"#field, GBE_STATSD_MODULE,                              \
 811         FIELD_SIZEOF(struct gbe_hw_stats, field),                       \
 812         offsetof(struct gbe_hw_stats, field)                            \
 813 }
 814
 815 static const struct netcp_ethtool_stat gbe13_et_stats[] = {
 816         /* GBE module A */
 817         GBE_STATSA_INFO(rx_good_frames),
 818         GBE_STATSA_INFO(rx_broadcast_frames),
 819         GBE_STATSA_INFO(rx_multicast_frames),
 820         GBE_STATSA_INFO(rx_pause_frames),
 821         GBE_STATSA_INFO(rx_crc_errors),
 822         GBE_STATSA_INFO(rx_align_code_errors),
 823         GBE_STATSA_INFO(rx_oversized_frames),
 824         GBE_STATSA_INFO(rx_jabber_frames),
 825         GBE_STATSA_INFO(rx_undersized_frames),
 826         GBE_STATSA_INFO(rx_fragments),
 827         GBE_STATSA_INFO(rx_bytes),
 828         GBE_STATSA_INFO(tx_good_frames),
 829         GBE_STATSA_INFO(tx_broadcast_frames),
 830         GBE_STATSA_INFO(tx_multicast_frames),
 831         GBE_STATSA_INFO(tx_pause_frames),
 832         GBE_STATSA_INFO(tx_deferred_frames),
 833         GBE_STATSA_INFO(tx_collision_frames),
 834         GBE_STATSA_INFO(tx_single_coll_frames),
 835         GBE_STATSA_INFO(tx_mult_coll_frames),
 836         GBE_STATSA_INFO(tx_excessive_collisions),
 837         GBE_STATSA_INFO(tx_late_collisions),
 838         GBE_STATSA_INFO(tx_underrun),
 839         GBE_STATSA_INFO(tx_carrier_sense_errors),
 840         GBE_STATSA_INFO(tx_bytes),
 841         GBE_STATSA_INFO(tx_64byte_frames),
 842         GBE_STATSA_INFO(tx_65_to_127byte_frames),
 843         GBE_STATSA_INFO(tx_128_to_255byte_frames),
 844         GBE_STATSA_INFO(tx_256_to_511byte_frames),
 845         GBE_STATSA_INFO(tx_512_to_1023byte_frames),
 846         GBE_STATSA_INFO(tx_1024byte_frames),
 847         GBE_STATSA_INFO(net_bytes),
 848         GBE_STATSA_INFO(rx_sof_overruns),
 849         GBE_STATSA_INFO(rx_mof_overruns),
 850         GBE_STATSA_INFO(rx_dma_overruns),
 851         /* GBE module B */
 852         GBE_STATSB_INFO(rx_good_frames),
 853         GBE_STATSB_INFO(rx_broadcast_frames),
 854         GBE_STATSB_INFO(rx_multicast_frames),
 855         GBE_STATSB_INFO(rx_pause_frames),
 856         GBE_STATSB_INFO(rx_crc_errors),
 857         GBE_STATSB_INFO(rx_align_code_errors),
 858         GBE_STATSB_INFO(rx_oversized_frames),
 859         GBE_STATSB_INFO(rx_jabber_frames),
 860         GBE_STATSB_INFO(rx_undersized_frames),
 861         GBE_STATSB_INFO(rx_fragments),
 862         GBE_STATSB_INFO(rx_bytes),
 863         GBE_STATSB_INFO(tx_good_frames),
 864         GBE_STATSB_INFO(tx_broadcast_frames),
 865         GBE_STATSB_INFO(tx_multicast_frames),
 866         GBE_STATSB_INFO(tx_pause_frames),
 867         GBE_STATSB_INFO(tx_deferred_frames),
 868         GBE_STATSB_INFO(tx_collision_frames),
 869         GBE_STATSB_INFO(tx_single_coll_frames),
 870         GBE_STATSB_INFO(tx_mult_coll_frames),
 871         GBE_STATSB_INFO(tx_excessive_collisions),
 872         GBE_STATSB_INFO(tx_late_collisions),
 873         GBE_STATSB_INFO(tx_underrun),
 874         GBE_STATSB_INFO(tx_carrier_sense_errors),
 875         GBE_STATSB_INFO(tx_bytes),
 876         GBE_STATSB_INFO(tx_64byte_frames),
 877         GBE_STATSB_INFO(tx_65_to_127byte_frames),
 878         GBE_STATSB_INFO(tx_128_to_255byte_frames),
 879         GBE_STATSB_INFO(tx_256_to_511byte_frames),
 880         GBE_STATSB_INFO(tx_512_to_1023byte_frames),
 881         GBE_STATSB_INFO(tx_1024byte_frames),
 882         GBE_STATSB_INFO(net_bytes),
 883         GBE_STATSB_INFO(rx_sof_overruns),
 884         GBE_STATSB_INFO(rx_mof_overruns),
 885         GBE_STATSB_INFO(rx_dma_overruns),
 886         /* GBE module C */
 887         GBE_STATSC_INFO(rx_good_frames),
 888         GBE_STATSC_INFO(rx_broadcast_frames),
 889         GBE_STATSC_INFO(rx_multicast_frames),
 890         GBE_STATSC_INFO(rx_pause_frames),
 891         GBE_STATSC_INFO(rx_crc_errors),
 892         GBE_STATSC_INFO(rx_align_code_errors),
 893         GBE_STATSC_INFO(rx_oversized_frames),
 894         GBE_STATSC_INFO(rx_jabber_frames),
 895         GBE_STATSC_INFO(rx_undersized_frames),
 896         GBE_STATSC_INFO(rx_fragments),
 897         GBE_STATSC_INFO(rx_bytes),
 898         GBE_STATSC_INFO(tx_good_frames),
 899         GBE_STATSC_INFO(tx_broadcast_frames),
 900         GBE_STATSC_INFO(tx_multicast_frames),
 901         GBE_STATSC_INFO(tx_pause_frames),
 902         GBE_STATSC_INFO(tx_deferred_frames),
 903         GBE_STATSC_INFO(tx_collision_frames),
 904         GBE_STATSC_INFO(tx_single_coll_frames),
 905         GBE_STATSC_INFO(tx_mult_coll_frames),
 906         GBE_STATSC_INFO(tx_excessive_collisions),
 907         GBE_STATSC_INFO(tx_late_collisions),
 908         GBE_STATSC_INFO(tx_underrun),
 909         GBE_STATSC_INFO(tx_carrier_sense_errors),
 910         GBE_STATSC_INFO(tx_bytes),
 911         GBE_STATSC_INFO(tx_64byte_frames),
 912         GBE_STATSC_INFO(tx_65_to_127byte_frames),
 913         GBE_STATSC_INFO(tx_128_to_255byte_frames),
 914         GBE_STATSC_INFO(tx_256_to_511byte_frames),
 915         GBE_STATSC_INFO(tx_512_to_1023byte_frames),
 916         GBE_STATSC_INFO(tx_1024byte_frames),
 917         GBE_STATSC_INFO(net_bytes),
 918         GBE_STATSC_INFO(rx_sof_overruns),
 919         GBE_STATSC_INFO(rx_mof_overruns),
 920         GBE_STATSC_INFO(rx_dma_overruns),
 921         /* GBE module D */
 922         GBE_STATSD_INFO(rx_good_frames),
 923         GBE_STATSD_INFO(rx_broadcast_frames),
 924         GBE_STATSD_INFO(rx_multicast_frames),
 925         GBE_STATSD_INFO(rx_pause_frames),
 926         GBE_STATSD_INFO(rx_crc_errors),
 927         GBE_STATSD_INFO(rx_align_code_errors),
 928         GBE_STATSD_INFO(rx_oversized_frames),
 929         GBE_STATSD_INFO(rx_jabber_frames),
 930         GBE_STATSD_INFO(rx_undersized_frames),
 931         GBE_STATSD_INFO(rx_fragments),
 932         GBE_STATSD_INFO(rx_bytes),
 933         GBE_STATSD_INFO(tx_good_frames),
 934         GBE_STATSD_INFO(tx_broadcast_frames),
 935         GBE_STATSD_INFO(tx_multicast_frames),
 936         GBE_STATSD_INFO(tx_pause_frames),
 937         GBE_STATSD_INFO(tx_deferred_frames),
 938         GBE_STATSD_INFO(tx_collision_frames),
 939         GBE_STATSD_INFO(tx_single_coll_frames),
 940         GBE_STATSD_INFO(tx_mult_coll_frames),
 941         GBE_STATSD_INFO(tx_excessive_collisions),
 942         GBE_STATSD_INFO(tx_late_collisions),
 943         GBE_STATSD_INFO(tx_underrun),
 944         GBE_STATSD_INFO(tx_carrier_sense_errors),
 945         GBE_STATSD_INFO(tx_bytes),
 946         GBE_STATSD_INFO(tx_64byte_frames),
 947         GBE_STATSD_INFO(tx_65_to_127byte_frames),
 948         GBE_STATSD_INFO(tx_128_to_255byte_frames),
 949         GBE_STATSD_INFO(tx_256_to_511byte_frames),
 950         GBE_STATSD_INFO(tx_512_to_1023byte_frames),
 951         GBE_STATSD_INFO(tx_1024byte_frames),
 952         GBE_STATSD_INFO(net_bytes),
 953         GBE_STATSD_INFO(rx_sof_overruns),
 954         GBE_STATSD_INFO(rx_mof_overruns),
 955         GBE_STATSD_INFO(rx_dma_overruns),
 956 };
 957
 958 /* This is the size of entries in GBENU_STATS_HOST */
 959 #define GBENU_ET_STATS_HOST_SIZE        52
 960
 961 #define GBENU_STATS_HOST(field)                                 \
 962 {                                                               \
 963         "GBE_HOST:"#field, GBENU_STATS0_MODULE,                 \
 964         FIELD_SIZEOF(struct gbenu_hw_stats, field),             \
 965         offsetof(struct gbenu_hw_stats, field)                  \
 966 }
 967
 968 /* This is the size of entries in GBENU_STATS_PORT */
 969 #define GBENU_ET_STATS_PORT_SIZE        65
 970
 971 #define GBENU_STATS_P1(field)                                   \
 972 {                                                               \
 973         "GBE_P1:"#field, GBENU_STATS1_MODULE,                   \
 974         FIELD_SIZEOF(struct gbenu_hw_stats, field),             \
 975         offsetof(struct gbenu_hw_stats, field)                  \
 976 }
 977
 978 #define GBENU_STATS_P2(field)                                   \
 979 {                                                               \
 980         "GBE_P2:"#field, GBENU_STATS2_MODULE,                   \
 981         FIELD_SIZEOF(struct gbenu_hw_stats, field),             \
 982         offsetof(struct gbenu_hw_stats, field)                  \
 983 }
 984
 985 #define GBENU_STATS_P3(field)                                   \
 986 {                                                               \
 987         "GBE_P3:"#field, GBENU_STATS3_MODULE,                   \
 988         FIELD_SIZEOF(struct gbenu_hw_stats, field),             \
 989         offsetof(struct gbenu_hw_stats, field)                  \
 990 }
 991
 992 #define GBENU_STATS_P4(field)                                   \
 993 {                                                               \
 994         "GBE_P4:"#field, GBENU_STATS4_MODULE,                   \
 995         FIELD_SIZEOF(struct gbenu_hw_stats, field),             \
 996         offsetof(struct gbenu_hw_stats, field)                  \
 997 }
 998
 999 #define GBENU_STATS_P5(field)                                   \
1000 {                                                               \
1001         "GBE_P5:"#field, GBENU_STATS5_MODULE,                   \
1002         FIELD_SIZEOF(struct gbenu_hw_stats, field),             \
1003         offsetof(struct gbenu_hw_stats, field)                  \
1004 }
1005
1006 #define GBENU_STATS_P6(field)                                   \
1007 {                                                               \
1008         "GBE_P6:"#field, GBENU_STATS6_MODULE,                   \
1009         FIELD_SIZEOF(struct gbenu_hw_stats, field),             \
1010         offsetof(struct gbenu_hw_stats, field)                  \
1011 }
1012
1013 #define GBENU_STATS_P7(field)                                   \
1014 {                                                               \
1015         "GBE_P7:"#field, GBENU_STATS7_MODULE,                   \
1016         FIELD_SIZEOF(struct gbenu_hw_stats, field),             \
1017         offsetof(struct gbenu_hw_stats, field)                  \
1018 }
1019
1020 #define GBENU_STATS_P8(field)                                   \
1021 {                                                               \
1022         "GBE_P8:"#field, GBENU_STATS8_MODULE,                   \
1023         FIELD_SIZEOF(struct gbenu_hw_stats, field),             \
1024         offsetof(struct gbenu_hw_stats, field)                  \
1025 }
1026
1027 static const struct netcp_ethtool_stat gbenu_et_stats[] = {
1028         /* GBENU Host Module */
1029         GBENU_STATS_HOST(rx_good_frames),
1030         GBENU_STATS_HOST(rx_broadcast_frames),
1031         GBENU_STATS_HOST(rx_multicast_frames),
1032         GBENU_STATS_HOST(rx_crc_errors),
1033         GBENU_STATS_HOST(rx_oversized_frames),
1034         GBENU_STATS_HOST(rx_undersized_frames),
1035         GBENU_STATS_HOST(ale_drop),
1036         GBENU_STATS_HOST(ale_overrun_drop),
1037         GBENU_STATS_HOST(rx_bytes),
1038         GBENU_STATS_HOST(tx_good_frames),
1039         GBENU_STATS_HOST(tx_broadcast_frames),
1040         GBENU_STATS_HOST(tx_multicast_frames),
1041         GBENU_STATS_HOST(tx_bytes),
1042         GBENU_STATS_HOST(tx_64B_frames),
1043         GBENU_STATS_HOST(tx_65_to_127B_frames),
1044         GBENU_STATS_HOST(tx_128_to_255B_frames),
1045         GBENU_STATS_HOST(tx_256_to_511B_frames),
1046         GBENU_STATS_HOST(tx_512_to_1023B_frames),
1047         GBENU_STATS_HOST(tx_1024B_frames),
1048         GBENU_STATS_HOST(net_bytes),
1049         GBENU_STATS_HOST(rx_bottom_fifo_drop),
1050         GBENU_STATS_HOST(rx_port_mask_drop),
1051         GBENU_STATS_HOST(rx_top_fifo_drop),
1052         GBENU_STATS_HOST(ale_rate_limit_drop),
1053         GBENU_STATS_HOST(ale_vid_ingress_drop),
1054         GBENU_STATS_HOST(ale_da_eq_sa_drop),
1055         GBENU_STATS_HOST(ale_unknown_ucast),
1056         GBENU_STATS_HOST(ale_unknown_ucast_bytes),
1057         GBENU_STATS_HOST(ale_unknown_mcast),
1058         GBENU_STATS_HOST(ale_unknown_mcast_bytes),
1059         GBENU_STATS_HOST(ale_unknown_bcast),
1060         GBENU_STATS_HOST(ale_unknown_bcast_bytes),
1061         GBENU_STATS_HOST(ale_pol_match),
1062         GBENU_STATS_HOST(ale_pol_match_red),
1063         GBENU_STATS_HOST(ale_pol_match_yellow),
1064         GBENU_STATS_HOST(tx_mem_protect_err),
1065         GBENU_STATS_HOST(tx_pri0_drop),
1066         GBENU_STATS_HOST(tx_pri1_drop),
1067         GBENU_STATS_HOST(tx_pri2_drop),
1068         GBENU_STATS_HOST(tx_pri3_drop),
1069         GBENU_STATS_HOST(tx_pri4_drop),
1070         GBENU_STATS_HOST(tx_pri5_drop),
1071         GBENU_STATS_HOST(tx_pri6_drop),
1072         GBENU_STATS_HOST(tx_pri7_drop),
1073         GBENU_STATS_HOST(tx_pri0_drop_bcnt),
1074         GBENU_STATS_HOST(tx_pri1_drop_bcnt),
1075         GBENU_STATS_HOST(tx_pri2_drop_bcnt),
1076         GBENU_STATS_HOST(tx_pri3_drop_bcnt),
1077         GBENU_STATS_HOST(tx_pri4_drop_bcnt),
1078         GBENU_STATS_HOST(tx_pri5_drop_bcnt),
1079         GBENU_STATS_HOST(tx_pri6_drop_bcnt),
1080         GBENU_STATS_HOST(tx_pri7_drop_bcnt),
1081         /* GBENU Module 1 */
1082         GBENU_STATS_P1(rx_good_frames),
1083         GBENU_STATS_P1(rx_broadcast_frames),
1084         GBENU_STATS_P1(rx_multicast_frames),
1085         GBENU_STATS_P1(rx_pause_frames),
1086         GBENU_STATS_P1(rx_crc_errors),
1087         GBENU_STATS_P1(rx_align_code_errors),
1088         GBENU_STATS_P1(rx_oversized_frames),
1089         GBENU_STATS_P1(rx_jabber_frames),
1090         GBENU_STATS_P1(rx_undersized_frames),
1091         GBENU_STATS_P1(rx_fragments),
1092         GBENU_STATS_P1(ale_drop),
1093         GBENU_STATS_P1(ale_overrun_drop),
1094         GBENU_STATS_P1(rx_bytes),
1095         GBENU_STATS_P1(tx_good_frames),
1096         GBENU_STATS_P1(tx_broadcast_frames),
1097         GBENU_STATS_P1(tx_multicast_frames),
1098         GBENU_STATS_P1(tx_pause_frames),
1099         GBENU_STATS_P1(tx_deferred_frames),
1100         GBENU_STATS_P1(tx_collision_frames),
1101         GBENU_STATS_P1(tx_single_coll_frames),
1102         GBENU_STATS_P1(tx_mult_coll_frames),
1103         GBENU_STATS_P1(tx_excessive_collisions),
1104         GBENU_STATS_P1(tx_late_collisions),
1105         GBENU_STATS_P1(rx_ipg_error),
1106         GBENU_STATS_P1(tx_carrier_sense_errors),
1107         GBENU_STATS_P1(tx_bytes),
1108         GBENU_STATS_P1(tx_64B_frames),
1109         GBENU_STATS_P1(tx_65_to_127B_frames),
1110         GBENU_STATS_P1(tx_128_to_255B_frames),
1111         GBENU_STATS_P1(tx_256_to_511B_frames),
1112         GBENU_STATS_P1(tx_512_to_1023B_frames),
1113         GBENU_STATS_P1(tx_1024B_frames),
1114         GBENU_STATS_P1(net_bytes),
1115         GBENU_STATS_P1(rx_bottom_fifo_drop),
1116         GBENU_STATS_P1(rx_port_mask_drop),
1117         GBENU_STATS_P1(rx_top_fifo_drop),
1118         GBENU_STATS_P1(ale_rate_limit_drop),
1119         GBENU_STATS_P1(ale_vid_ingress_drop),
1120         GBENU_STATS_P1(ale_da_eq_sa_drop),
1121         GBENU_STATS_P1(ale_unknown_ucast),
1122         GBENU_STATS_P1(ale_unknown_ucast_bytes),
1123         GBENU_STATS_P1(ale_unknown_mcast),
1124         GBENU_STATS_P1(ale_unknown_mcast_bytes),
1125         GBENU_STATS_P1(ale_unknown_bcast),
1126         GBENU_STATS_P1(ale_unknown_bcast_bytes),
1127         GBENU_STATS_P1(ale_pol_match),
1128         GBENU_STATS_P1(ale_pol_match_red),
1129         GBENU_STATS_P1(ale_pol_match_yellow),
1130         GBENU_STATS_P1(tx_mem_protect_err),
1131         GBENU_STATS_P1(tx_pri0_drop),
1132         GBENU_STATS_P1(tx_pri1_drop),
1133         GBENU_STATS_P1(tx_pri2_drop),
1134         GBENU_STATS_P1(tx_pri3_drop),
1135         GBENU_STATS_P1(tx_pri4_drop),
1136         GBENU_STATS_P1(tx_pri5_drop),
1137         GBENU_STATS_P1(tx_pri6_drop),
1138         GBENU_STATS_P1(tx_pri7_drop),
1139         GBENU_STATS_P1(tx_pri0_drop_bcnt),
1140         GBENU_STATS_P1(tx_pri1_drop_bcnt),
1141         GBENU_STATS_P1(tx_pri2_drop_bcnt),
1142         GBENU_STATS_P1(tx_pri3_drop_bcnt),
1143         GBENU_STATS_P1(tx_pri4_drop_bcnt),
1144         GBENU_STATS_P1(tx_pri5_drop_bcnt),
1145         GBENU_STATS_P1(tx_pri6_drop_bcnt),
1146         GBENU_STATS_P1(tx_pri7_drop_bcnt),
1147         /* GBENU Module 2 */
1148         GBENU_STATS_P2(rx_good_frames),
1149         GBENU_STATS_P2(rx_broadcast_frames),
1150         GBENU_STATS_P2(rx_multicast_frames),
1151         GBENU_STATS_P2(rx_pause_frames),
1152         GBENU_STATS_P2(rx_crc_errors),
1153         GBENU_STATS_P2(rx_align_code_errors),
1154         GBENU_STATS_P2(rx_oversized_frames),
1155         GBENU_STATS_P2(rx_jabber_frames),
1156         GBENU_STATS_P2(rx_undersized_frames),
1157         GBENU_STATS_P2(rx_fragments),
1158         GBENU_STATS_P2(ale_drop),
1159         GBENU_STATS_P2(ale_overrun_drop),
1160         GBENU_STATS_P2(rx_bytes),
1161         GBENU_STATS_P2(tx_good_frames),
1162         GBENU_STATS_P2(tx_broadcast_frames),
1163         GBENU_STATS_P2(tx_multicast_frames),
1164         GBENU_STATS_P2(tx_pause_frames),
1165         GBENU_STATS_P2(tx_deferred_frames),
1166         GBENU_STATS_P2(tx_collision_frames),
1167         GBENU_STATS_P2(tx_single_coll_frames),
1168         GBENU_STATS_P2(tx_mult_coll_frames),
1169         GBENU_STATS_P2(tx_excessive_collisions),
1170         GBENU_STATS_P2(tx_late_collisions),
1171         GBENU_STATS_P2(rx_ipg_error),
1172         GBENU_STATS_P2(tx_carrier_sense_errors),
1173         GBENU_STATS_P2(tx_bytes),
1174         GBENU_STATS_P2(tx_64B_frames),
1175         GBENU_STATS_P2(tx_65_to_127B_frames),
1176         GBENU_STATS_P2(tx_128_to_255B_frames),
1177         GBENU_STATS_P2(tx_256_to_511B_frames),
1178         GBENU_STATS_P2(tx_512_to_1023B_frames),
1179         GBENU_STATS_P2(tx_1024B_frames),
1180         GBENU_STATS_P2(net_bytes),
1181         GBENU_STATS_P2(rx_bottom_fifo_drop),
1182         GBENU_STATS_P2(rx_port_mask_drop),
1183         GBENU_STATS_P2(rx_top_fifo_drop),
1184         GBENU_STATS_P2(ale_rate_limit_drop),
1185         GBENU_STATS_P2(ale_vid_ingress_drop),
1186         GBENU_STATS_P2(ale_da_eq_sa_drop),
1187         GBENU_STATS_P2(ale_unknown_ucast),
1188         GBENU_STATS_P2(ale_unknown_ucast_bytes),
1189         GBENU_STATS_P2(ale_unknown_mcast),
1190         GBENU_STATS_P2(ale_unknown_mcast_bytes),
1191         GBENU_STATS_P2(ale_unknown_bcast),
1192         GBENU_STATS_P2(ale_unknown_bcast_bytes),
1193         GBENU_STATS_P2(ale_pol_match),
1194         GBENU_STATS_P2(ale_pol_match_red),
1195         GBENU_STATS_P2(ale_pol_match_yellow),
1196         GBENU_STATS_P2(tx_mem_protect_err),
1197         GBENU_STATS_P2(tx_pri0_drop),
1198         GBENU_STATS_P2(tx_pri1_drop),
1199         GBENU_STATS_P2(tx_pri2_drop),
1200         GBENU_STATS_P2(tx_pri3_drop),
1201         GBENU_STATS_P2(tx_pri4_drop),
1202         GBENU_STATS_P2(tx_pri5_drop),
1203         GBENU_STATS_P2(tx_pri6_drop),
1204         GBENU_STATS_P2(tx_pri7_drop),
1205         GBENU_STATS_P2(tx_pri0_drop_bcnt),
1206         GBENU_STATS_P2(tx_pri1_drop_bcnt),
1207         GBENU_STATS_P2(tx_pri2_drop_bcnt),
1208         GBENU_STATS_P2(tx_pri3_drop_bcnt),
1209         GBENU_STATS_P2(tx_pri4_drop_bcnt),
1210         GBENU_STATS_P2(tx_pri5_drop_bcnt),
1211         GBENU_STATS_P2(tx_pri6_drop_bcnt),
1212         GBENU_STATS_P2(tx_pri7_drop_bcnt),
1213         /* GBENU Module 3 */
1214         GBENU_STATS_P3(rx_good_frames),
1215         GBENU_STATS_P3(rx_broadcast_frames),
1216         GBENU_STATS_P3(rx_multicast_frames),
1217         GBENU_STATS_P3(rx_pause_frames),
1218         GBENU_STATS_P3(rx_crc_errors),
1219         GBENU_STATS_P3(rx_align_code_errors),
1220         GBENU_STATS_P3(rx_oversized_frames),
1221         GBENU_STATS_P3(rx_jabber_frames),
1222         GBENU_STATS_P3(rx_undersized_frames),
1223         GBENU_STATS_P3(rx_fragments),
1224         GBENU_STATS_P3(ale_drop),
1225         GBENU_STATS_P3(ale_overrun_drop),
1226         GBENU_STATS_P3(rx_bytes),
1227         GBENU_STATS_P3(tx_good_frames),
1228         GBENU_STATS_P3(tx_broadcast_frames),
1229         GBENU_STATS_P3(tx_multicast_frames),
1230         GBENU_STATS_P3(tx_pause_frames),
1231         GBENU_STATS_P3(tx_deferred_frames),
1232         GBENU_STATS_P3(tx_collision_frames),
1233         GBENU_STATS_P3(tx_single_coll_frames),
1234         GBENU_STATS_P3(tx_mult_coll_frames),
1235         GBENU_STATS_P3(tx_excessive_collisions),
1236         GBENU_STATS_P3(tx_late_collisions),
1237         GBENU_STATS_P3(rx_ipg_error),
1238         GBENU_STATS_P3(tx_carrier_sense_errors),
1239         GBENU_STATS_P3(tx_bytes),
1240         GBENU_STATS_P3(tx_64B_frames),
1241         GBENU_STATS_P3(tx_65_to_127B_frames),
1242         GBENU_STATS_P3(tx_128_to_255B_frames),
1243         GBENU_STATS_P3(tx_256_to_511B_frames),
1244         GBENU_STATS_P3(tx_512_to_1023B_frames),
1245         GBENU_STATS_P3(tx_1024B_frames),
1246         GBENU_STATS_P3(net_bytes),
1247         GBENU_STATS_P3(rx_bottom_fifo_drop),
1248         GBENU_STATS_P3(rx_port_mask_drop),
1249         GBENU_STATS_P3(rx_top_fifo_drop),
1250         GBENU_STATS_P3(ale_rate_limit_drop),
1251         GBENU_STATS_P3(ale_vid_ingress_drop),
1252         GBENU_STATS_P3(ale_da_eq_sa_drop),
1253         GBENU_STATS_P3(ale_unknown_ucast),
1254         GBENU_STATS_P3(ale_unknown_ucast_bytes),
1255         GBENU_STATS_P3(ale_unknown_mcast),
1256         GBENU_STATS_P3(ale_unknown_mcast_bytes),
1257         GBENU_STATS_P3(ale_unknown_bcast),
1258         GBENU_STATS_P3(ale_unknown_bcast_bytes),
1259         GBENU_STATS_P3(ale_pol_match),
1260         GBENU_STATS_P3(ale_pol_match_red),
1261         GBENU_STATS_P3(ale_pol_match_yellow),
1262         GBENU_STATS_P3(tx_mem_protect_err),
1263         GBENU_STATS_P3(tx_pri0_drop),
1264         GBENU_STATS_P3(tx_pri1_drop),
1265         GBENU_STATS_P3(tx_pri2_drop),
1266         GBENU_STATS_P3(tx_pri3_drop),
1267         GBENU_STATS_P3(tx_pri4_drop),
1268         GBENU_STATS_P3(tx_pri5_drop),
1269         GBENU_STATS_P3(tx_pri6_drop),
1270         GBENU_STATS_P3(tx_pri7_drop),
1271         GBENU_STATS_P3(tx_pri0_drop_bcnt),
1272         GBENU_STATS_P3(tx_pri1_drop_bcnt),
1273         GBENU_STATS_P3(tx_pri2_drop_bcnt),
1274         GBENU_STATS_P3(tx_pri3_drop_bcnt),
1275         GBENU_STATS_P3(tx_pri4_drop_bcnt),
1276         GBENU_STATS_P3(tx_pri5_drop_bcnt),
1277         GBENU_STATS_P3(tx_pri6_drop_bcnt),
1278         GBENU_STATS_P3(tx_pri7_drop_bcnt),
1279         /* GBENU Module 4 */
1280         GBENU_STATS_P4(rx_good_frames),
1281         GBENU_STATS_P4(rx_broadcast_frames),
1282         GBENU_STATS_P4(rx_multicast_frames),
1283         GBENU_STATS_P4(rx_pause_frames),
1284         GBENU_STATS_P4(rx_crc_errors),
1285         GBENU_STATS_P4(rx_align_code_errors),
1286         GBENU_STATS_P4(rx_oversized_frames),
1287         GBENU_STATS_P4(rx_jabber_frames),
1288         GBENU_STATS_P4(rx_undersized_frames),
1289         GBENU_STATS_P4(rx_fragments),
1290         GBENU_STATS_P4(ale_drop),
1291         GBENU_STATS_P4(ale_overrun_drop),
1292         GBENU_STATS_P4(rx_bytes),
1293         GBENU_STATS_P4(tx_good_frames),
1294         GBENU_STATS_P4(tx_broadcast_frames),
1295         GBENU_STATS_P4(tx_multicast_frames),
1296         GBENU_STATS_P4(tx_pause_frames),
1297         GBENU_STATS_P4(tx_deferred_frames),
1298         GBENU_STATS_P4(tx_collision_frames),
1299         GBENU_STATS_P4(tx_single_coll_frames),
1300         GBENU_STATS_P4(tx_mult_coll_frames),
1301         GBENU_STATS_P4(tx_excessive_collisions),
1302         GBENU_STATS_P4(tx_late_collisions),
1303         GBENU_STATS_P4(rx_ipg_error),
1304         GBENU_STATS_P4(tx_carrier_sense_errors),
1305         GBENU_STATS_P4(tx_bytes),
1306         GBENU_STATS_P4(tx_64B_frames),
1307         GBENU_STATS_P4(tx_65_to_127B_frames),
1308         GBENU_STATS_P4(tx_128_to_255B_frames),
1309         GBENU_STATS_P4(tx_256_to_511B_frames),
1310         GBENU_STATS_P4(tx_512_to_1023B_frames),
1311         GBENU_STATS_P4(tx_1024B_frames),
1312         GBENU_STATS_P4(net_bytes),
1313         GBENU_STATS_P4(rx_bottom_fifo_drop),
1314         GBENU_STATS_P4(rx_port_mask_drop),
1315         GBENU_STATS_P4(rx_top_fifo_drop),
1316         GBENU_STATS_P4(ale_rate_limit_drop),
1317         GBENU_STATS_P4(ale_vid_ingress_drop),
1318         GBENU_STATS_P4(ale_da_eq_sa_drop),
1319         GBENU_STATS_P4(ale_unknown_ucast),
1320         GBENU_STATS_P4(ale_unknown_ucast_bytes),
1321         GBENU_STATS_P4(ale_unknown_mcast),
1322         GBENU_STATS_P4(ale_unknown_mcast_bytes),
1323         GBENU_STATS_P4(ale_unknown_bcast),
1324         GBENU_STATS_P4(ale_unknown_bcast_bytes),
1325         GBENU_STATS_P4(ale_pol_match),
1326         GBENU_STATS_P4(ale_pol_match_red),
1327         GBENU_STATS_P4(ale_pol_match_yellow),
1328         GBENU_STATS_P4(tx_mem_protect_err),
1329         GBENU_STATS_P4(tx_pri0_drop),
1330         GBENU_STATS_P4(tx_pri1_drop),
1331         GBENU_STATS_P4(tx_pri2_drop),
1332         GBENU_STATS_P4(tx_pri3_drop),
1333         GBENU_STATS_P4(tx_pri4_drop),
1334         GBENU_STATS_P4(tx_pri5_drop),
1335         GBENU_STATS_P4(tx_pri6_drop),
1336         GBENU_STATS_P4(tx_pri7_drop),
1337         GBENU_STATS_P4(tx_pri0_drop_bcnt),
1338         GBENU_STATS_P4(tx_pri1_drop_bcnt),
1339         GBENU_STATS_P4(tx_pri2_drop_bcnt),
1340         GBENU_STATS_P4(tx_pri3_drop_bcnt),
1341         GBENU_STATS_P4(tx_pri4_drop_bcnt),
1342         GBENU_STATS_P4(tx_pri5_drop_bcnt),
1343         GBENU_STATS_P4(tx_pri6_drop_bcnt),
1344         GBENU_STATS_P4(tx_pri7_drop_bcnt),
1345         /* GBENU Module 5 */
1346         GBENU_STATS_P5(rx_good_frames),
1347         GBENU_STATS_P5(rx_broadcast_frames),
1348         GBENU_STATS_P5(rx_multicast_frames),
1349         GBENU_STATS_P5(rx_pause_frames),
1350         GBENU_STATS_P5(rx_crc_errors),
1351         GBENU_STATS_P5(rx_align_code_errors),
1352         GBENU_STATS_P5(rx_oversized_frames),
1353         GBENU_STATS_P5(rx_jabber_frames),
1354         GBENU_STATS_P5(rx_undersized_frames),
1355         GBENU_STATS_P5(rx_fragments),
1356         GBENU_STATS_P5(ale_drop),
1357         GBENU_STATS_P5(ale_overrun_drop),
1358         GBENU_STATS_P5(rx_bytes),
1359         GBENU_STATS_P5(tx_good_frames),
1360         GBENU_STATS_P5(tx_broadcast_frames),
1361         GBENU_STATS_P5(tx_multicast_frames),
1362         GBENU_STATS_P5(tx_pause_frames),
1363         GBENU_STATS_P5(tx_deferred_frames),
1364         GBENU_STATS_P5(tx_collision_frames),
1365         GBENU_STATS_P5(tx_single_coll_frames),
1366         GBENU_STATS_P5(tx_mult_coll_frames),
1367         GBENU_STATS_P5(tx_excessive_collisions),
1368         GBENU_STATS_P5(tx_late_collisions),
1369         GBENU_STATS_P5(rx_ipg_error),
1370         GBENU_STATS_P5(tx_carrier_sense_errors),
1371         GBENU_STATS_P5(tx_bytes),
1372         GBENU_STATS_P5(tx_64B_frames),
1373         GBENU_STATS_P5(tx_65_to_127B_frames),
1374         GBENU_STATS_P5(tx_128_to_255B_frames),
1375         GBENU_STATS_P5(tx_256_to_511B_frames),
1376         GBENU_STATS_P5(tx_512_to_1023B_frames),
1377         GBENU_STATS_P5(tx_1024B_frames),
1378         GBENU_STATS_P5(net_bytes),
1379         GBENU_STATS_P5(rx_bottom_fifo_drop),
1380         GBENU_STATS_P5(rx_port_mask_drop),
1381         GBENU_STATS_P5(rx_top_fifo_drop),
1382         GBENU_STATS_P5(ale_rate_limit_drop),
1383         GBENU_STATS_P5(ale_vid_ingress_drop),
1384         GBENU_STATS_P5(ale_da_eq_sa_drop),
1385         GBENU_STATS_P5(ale_unknown_ucast),
1386         GBENU_STATS_P5(ale_unknown_ucast_bytes),
1387         GBENU_STATS_P5(ale_unknown_mcast),
1388         GBENU_STATS_P5(ale_unknown_mcast_bytes),
1389         GBENU_STATS_P5(ale_unknown_bcast),
1390         GBENU_STATS_P5(ale_unknown_bcast_bytes),
1391         GBENU_STATS_P5(ale_pol_match),
1392         GBENU_STATS_P5(ale_pol_match_red),
1393         GBENU_STATS_P5(ale_pol_match_yellow),
1394         GBENU_STATS_P5(tx_mem_protect_err),
1395         GBENU_STATS_P5(tx_pri0_drop),
1396         GBENU_STATS_P5(tx_pri1_drop),
1397         GBENU_STATS_P5(tx_pri2_drop),
1398         GBENU_STATS_P5(tx_pri3_drop),
1399         GBENU_STATS_P5(tx_pri4_drop),
1400         GBENU_STATS_P5(tx_pri5_drop),
1401         GBENU_STATS_P5(tx_pri6_drop),
1402         GBENU_STATS_P5(tx_pri7_drop),
1403         GBENU_STATS_P5(tx_pri0_drop_bcnt),
1404         GBENU_STATS_P5(tx_pri1_drop_bcnt),
1405         GBENU_STATS_P5(tx_pri2_drop_bcnt),
1406         GBENU_STATS_P5(tx_pri3_drop_bcnt),
1407         GBENU_STATS_P5(tx_pri4_drop_bcnt),
1408         GBENU_STATS_P5(tx_pri5_drop_bcnt),
1409         GBENU_STATS_P5(tx_pri6_drop_bcnt),
1410         GBENU_STATS_P5(tx_pri7_drop_bcnt),
1411         /* GBENU Module 6 */
1412         GBENU_STATS_P6(rx_good_frames),
1413         GBENU_STATS_P6(rx_broadcast_frames),
1414         GBENU_STATS_P6(rx_multicast_frames),
1415         GBENU_STATS_P6(rx_pause_frames),
1416         GBENU_STATS_P6(rx_crc_errors),
1417         GBENU_STATS_P6(rx_align_code_errors),
1418         GBENU_STATS_P6(rx_oversized_frames),
1419         GBENU_STATS_P6(rx_jabber_frames),
1420         GBENU_STATS_P6(rx_undersized_frames),
1421         GBENU_STATS_P6(rx_fragments),
1422         GBENU_STATS_P6(ale_drop),
1423         GBENU_STATS_P6(ale_overrun_drop),
1424         GBENU_STATS_P6(rx_bytes),
1425         GBENU_STATS_P6(tx_good_frames),
1426         GBENU_STATS_P6(tx_broadcast_frames),
1427         GBENU_STATS_P6(tx_multicast_frames),
1428         GBENU_STATS_P6(tx_pause_frames),
1429         GBENU_STATS_P6(tx_deferred_frames),
1430         GBENU_STATS_P6(tx_collision_frames),
1431         GBENU_STATS_P6(tx_single_coll_frames),
1432         GBENU_STATS_P6(tx_mult_coll_frames),
1433         GBENU_STATS_P6(tx_excessive_collisions),
1434         GBENU_STATS_P6(tx_late_collisions),
1435         GBENU_STATS_P6(rx_ipg_error),
1436         GBENU_STATS_P6(tx_carrier_sense_errors),
1437         GBENU_STATS_P6(tx_bytes),
1438         GBENU_STATS_P6(tx_64B_frames),
1439         GBENU_STATS_P6(tx_65_to_127B_frames),
1440         GBENU_STATS_P6(tx_128_to_255B_frames),
1441         GBENU_STATS_P6(tx_256_to_511B_frames),
1442         GBENU_STATS_P6(tx_512_to_1023B_frames),
1443         GBENU_STATS_P6(tx_1024B_frames),
1444         GBENU_STATS_P6(net_bytes),
1445         GBENU_STATS_P6(rx_bottom_fifo_drop),
1446         GBENU_STATS_P6(rx_port_mask_drop),
1447         GBENU_STATS_P6(rx_top_fifo_drop),
1448         GBENU_STATS_P6(ale_rate_limit_drop),
1449         GBENU_STATS_P6(ale_vid_ingress_drop),
1450         GBENU_STATS_P6(ale_da_eq_sa_drop),
1451         GBENU_STATS_P6(ale_unknown_ucast),
1452         GBENU_STATS_P6(ale_unknown_ucast_bytes),
1453         GBENU_STATS_P6(ale_unknown_mcast),
1454         GBENU_STATS_P6(ale_unknown_mcast_bytes),
1455         GBENU_STATS_P6(ale_unknown_bcast),
1456         GBENU_STATS_P6(ale_unknown_bcast_bytes),
1457         GBENU_STATS_P6(ale_pol_match),
1458         GBENU_STATS_P6(ale_pol_match_red),
1459         GBENU_STATS_P6(ale_pol_match_yellow),
1460         GBENU_STATS_P6(tx_mem_protect_err),
1461         GBENU_STATS_P6(tx_pri0_drop),
1462         GBENU_STATS_P6(tx_pri1_drop),
1463         GBENU_STATS_P6(tx_pri2_drop),
1464         GBENU_STATS_P6(tx_pri3_drop),
1465         GBENU_STATS_P6(tx_pri4_drop),
1466         GBENU_STATS_P6(tx_pri5_drop),
1467         GBENU_STATS_P6(tx_pri6_drop),
1468         GBENU_STATS_P6(tx_pri7_drop),
1469         GBENU_STATS_P6(tx_pri0_drop_bcnt),
1470         GBENU_STATS_P6(tx_pri1_drop_bcnt),
1471         GBENU_STATS_P6(tx_pri2_drop_bcnt),
1472         GBENU_STATS_P6(tx_pri3_drop_bcnt),
1473         GBENU_STATS_P6(tx_pri4_drop_bcnt),
1474         GBENU_STATS_P6(tx_pri5_drop_bcnt),
1475         GBENU_STATS_P6(tx_pri6_drop_bcnt),
1476         GBENU_STATS_P6(tx_pri7_drop_bcnt),
1477         /* GBENU Module 7 */
1478         GBENU_STATS_P7(rx_good_frames),
1479         GBENU_STATS_P7(rx_broadcast_frames),
1480         GBENU_STATS_P7(rx_multicast_frames),
1481         GBENU_STATS_P7(rx_pause_frames),
1482         GBENU_STATS_P7(rx_crc_errors),
1483         GBENU_STATS_P7(rx_align_code_errors),
1484         GBENU_STATS_P7(rx_oversized_frames),
1485         GBENU_STATS_P7(rx_jabber_frames),
1486         GBENU_STATS_P7(rx_undersized_frames),
1487         GBENU_STATS_P7(rx_fragments),
1488         GBENU_STATS_P7(ale_drop),
1489         GBENU_STATS_P7(ale_overrun_drop),
1490         GBENU_STATS_P7(rx_bytes),
1491         GBENU_STATS_P7(tx_good_frames),
1492         GBENU_STATS_P7(tx_broadcast_frames),
1493         GBENU_STATS_P7(tx_multicast_frames),
1494         GBENU_STATS_P7(tx_pause_frames),
1495         GBENU_STATS_P7(tx_deferred_frames),
1496         GBENU_STATS_P7(tx_collision_frames),
1497         GBENU_STATS_P7(tx_single_coll_frames),
1498         GBENU_STATS_P7(tx_mult_coll_frames),
1499         GBENU_STATS_P7(tx_excessive_collisions),
1500         GBENU_STATS_P7(tx_late_collisions),
1501         GBENU_STATS_P7(rx_ipg_error),
1502         GBENU_STATS_P7(tx_carrier_sense_errors),
1503         GBENU_STATS_P7(tx_bytes),
1504         GBENU_STATS_P7(tx_64B_frames),
1505         GBENU_STATS_P7(tx_65_to_127B_frames),
1506         GBENU_STATS_P7(tx_128_to_255B_frames),
1507         GBENU_STATS_P7(tx_256_to_511B_frames),
1508         GBENU_STATS_P7(tx_512_to_1023B_frames),
1509         GBENU_STATS_P7(tx_1024B_frames),
1510         GBENU_STATS_P7(net_bytes),
1511         GBENU_STATS_P7(rx_bottom_fifo_drop),
1512         GBENU_STATS_P7(rx_port_mask_drop),
1513         GBENU_STATS_P7(rx_top_fifo_drop),
1514         GBENU_STATS_P7(ale_rate_limit_drop),
1515         GBENU_STATS_P7(ale_vid_ingress_drop),
1516         GBENU_STATS_P7(ale_da_eq_sa_drop),
1517         GBENU_STATS_P7(ale_unknown_ucast),
1518         GBENU_STATS_P7(ale_unknown_ucast_bytes),
1519         GBENU_STATS_P7(ale_unknown_mcast),
1520         GBENU_STATS_P7(ale_unknown_mcast_bytes),
1521         GBENU_STATS_P7(ale_unknown_bcast),
1522         GBENU_STATS_P7(ale_unknown_bcast_bytes),
1523         GBENU_STATS_P7(ale_pol_match),
1524         GBENU_STATS_P7(ale_pol_match_red),
1525         GBENU_STATS_P7(ale_pol_match_yellow),
1526         GBENU_STATS_P7(tx_mem_protect_err),
1527         GBENU_STATS_P7(tx_pri0_drop),
1528         GBENU_STATS_P7(tx_pri1_drop),
1529         GBENU_STATS_P7(tx_pri2_drop),
1530         GBENU_STATS_P7(tx_pri3_drop),
1531         GBENU_STATS_P7(tx_pri4_drop),
1532         GBENU_STATS_P7(tx_pri5_drop),
1533         GBENU_STATS_P7(tx_pri6_drop),
1534         GBENU_STATS_P7(tx_pri7_drop),
1535         GBENU_STATS_P7(tx_pri0_drop_bcnt),
1536         GBENU_STATS_P7(tx_pri1_drop_bcnt),
1537         GBENU_STATS_P7(tx_pri2_drop_bcnt),
1538         GBENU_STATS_P7(tx_pri3_drop_bcnt),
1539         GBENU_STATS_P7(tx_pri4_drop_bcnt),
1540         GBENU_STATS_P7(tx_pri5_drop_bcnt),
1541         GBENU_STATS_P7(tx_pri6_drop_bcnt),
1542         GBENU_STATS_P7(tx_pri7_drop_bcnt),
1543         /* GBENU Module 8 */
1544         GBENU_STATS_P8(rx_good_frames),
1545         GBENU_STATS_P8(rx_broadcast_frames),
1546         GBENU_STATS_P8(rx_multicast_frames),
1547         GBENU_STATS_P8(rx_pause_frames),
1548         GBENU_STATS_P8(rx_crc_errors),
1549         GBENU_STATS_P8(rx_align_code_errors),
1550         GBENU_STATS_P8(rx_oversized_frames),
1551         GBENU_STATS_P8(rx_jabber_frames),
1552         GBENU_STATS_P8(rx_undersized_frames),
1553         GBENU_STATS_P8(rx_fragments),
1554         GBENU_STATS_P8(ale_drop),
1555         GBENU_STATS_P8(ale_overrun_drop),
1556         GBENU_STATS_P8(rx_bytes),
1557         GBENU_STATS_P8(tx_good_frames),
1558         GBENU_STATS_P8(tx_broadcast_frames),
1559         GBENU_STATS_P8(tx_multicast_frames),
1560         GBENU_STATS_P8(tx_pause_frames),
1561         GBENU_STATS_P8(tx_deferred_frames),
1562         GBENU_STATS_P8(tx_collision_frames),
1563         GBENU_STATS_P8(tx_single_coll_frames),
1564         GBENU_STATS_P8(tx_mult_coll_frames),
1565         GBENU_STATS_P8(tx_excessive_collisions),
1566         GBENU_STATS_P8(tx_late_collisions),
1567         GBENU_STATS_P8(rx_ipg_error),
1568         GBENU_STATS_P8(tx_carrier_sense_errors),
1569         GBENU_STATS_P8(tx_bytes),
1570         GBENU_STATS_P8(tx_64B_frames),
1571         GBENU_STATS_P8(tx_65_to_127B_frames),
1572         GBENU_STATS_P8(tx_128_to_255B_frames),
1573         GBENU_STATS_P8(tx_256_to_511B_frames),
1574         GBENU_STATS_P8(tx_512_to_1023B_frames),
1575         GBENU_STATS_P8(tx_1024B_frames),
1576         GBENU_STATS_P8(net_bytes),
1577         GBENU_STATS_P8(rx_bottom_fifo_drop),
1578         GBENU_STATS_P8(rx_port_mask_drop),
1579         GBENU_STATS_P8(rx_top_fifo_drop),
1580         GBENU_STATS_P8(ale_rate_limit_drop),
1581         GBENU_STATS_P8(ale_vid_ingress_drop),
1582         GBENU_STATS_P8(ale_da_eq_sa_drop),
1583         GBENU_STATS_P8(ale_unknown_ucast),
1584         GBENU_STATS_P8(ale_unknown_ucast_bytes),
1585         GBENU_STATS_P8(ale_unknown_mcast),
1586         GBENU_STATS_P8(ale_unknown_mcast_bytes),
1587         GBENU_STATS_P8(ale_unknown_bcast),
1588         GBENU_STATS_P8(ale_unknown_bcast_bytes),
1589         GBENU_STATS_P8(ale_pol_match),
1590         GBENU_STATS_P8(ale_pol_match_red),
1591         GBENU_STATS_P8(ale_pol_match_yellow),
1592         GBENU_STATS_P8(tx_mem_protect_err),
1593         GBENU_STATS_P8(tx_pri0_drop),
1594         GBENU_STATS_P8(tx_pri1_drop),
1595         GBENU_STATS_P8(tx_pri2_drop),
1596         GBENU_STATS_P8(tx_pri3_drop),
1597         GBENU_STATS_P8(tx_pri4_drop),
1598         GBENU_STATS_P8(tx_pri5_drop),
1599         GBENU_STATS_P8(tx_pri6_drop),
1600         GBENU_STATS_P8(tx_pri7_drop),
1601         GBENU_STATS_P8(tx_pri0_drop_bcnt),
1602         GBENU_STATS_P8(tx_pri1_drop_bcnt),
1603         GBENU_STATS_P8(tx_pri2_drop_bcnt),
1604         GBENU_STATS_P8(tx_pri3_drop_bcnt),
1605         GBENU_STATS_P8(tx_pri4_drop_bcnt),
1606         GBENU_STATS_P8(tx_pri5_drop_bcnt),
1607         GBENU_STATS_P8(tx_pri6_drop_bcnt),
1608         GBENU_STATS_P8(tx_pri7_drop_bcnt),
1609 };
1610
1611 #define XGBE_STATS0_INFO(field)                         \
1612 {                                                       \
1613         "GBE_0:"#field, XGBE_STATS0_MODULE,             \
1614         FIELD_SIZEOF(struct xgbe_hw_stats, field),      \
1615         offsetof(struct xgbe_hw_stats, field)           \
1616 }
1617
1618 #define XGBE_STATS1_INFO(field)                         \
1619 {                                                       \
1620         "GBE_1:"#field, XGBE_STATS1_MODULE,             \
1621         FIELD_SIZEOF(struct xgbe_hw_stats, field),      \
1622         offsetof(struct xgbe_hw_stats, field)           \
1623 }
1624
1625 #define XGBE_STATS2_INFO(field)                         \
1626 {                                                       \
1627         "GBE_2:"#field, XGBE_STATS2_MODULE,             \
1628         FIELD_SIZEOF(struct xgbe_hw_stats, field),      \
1629         offsetof(struct xgbe_hw_stats, field)           \
1630 }
1631
1632 static const struct netcp_ethtool_stat xgbe10_et_stats[] = {
1633         /* GBE module 0 */
1634         XGBE_STATS0_INFO(rx_good_frames),
1635         XGBE_STATS0_INFO(rx_broadcast_frames),
1636         XGBE_STATS0_INFO(rx_multicast_frames),
1637         XGBE_STATS0_INFO(rx_oversized_frames),
1638         XGBE_STATS0_INFO(rx_undersized_frames),
1639         XGBE_STATS0_INFO(overrun_type4),
1640         XGBE_STATS0_INFO(overrun_type5),
1641         XGBE_STATS0_INFO(rx_bytes),
1642         XGBE_STATS0_INFO(tx_good_frames),
1643         XGBE_STATS0_INFO(tx_broadcast_frames),
1644         XGBE_STATS0_INFO(tx_multicast_frames),
1645         XGBE_STATS0_INFO(tx_bytes),
1646         XGBE_STATS0_INFO(tx_64byte_frames),
1647         XGBE_STATS0_INFO(tx_65_to_127byte_frames),
1648         XGBE_STATS0_INFO(tx_128_to_255byte_frames),
1649         XGBE_STATS0_INFO(tx_256_to_511byte_frames),
1650         XGBE_STATS0_INFO(tx_512_to_1023byte_frames),
1651         XGBE_STATS0_INFO(tx_1024byte_frames),
1652         XGBE_STATS0_INFO(net_bytes),
1653         XGBE_STATS0_INFO(rx_sof_overruns),
1654         XGBE_STATS0_INFO(rx_mof_overruns),
1655         XGBE_STATS0_INFO(rx_dma_overruns),
1656         /* XGBE module 1 */
1657         XGBE_STATS1_INFO(rx_good_frames),
1658         XGBE_STATS1_INFO(rx_broadcast_frames),
1659         XGBE_STATS1_INFO(rx_multicast_frames),
1660         XGBE_STATS1_INFO(rx_pause_frames),
1661         XGBE_STATS1_INFO(rx_crc_errors),
1662         XGBE_STATS1_INFO(rx_align_code_errors),
1663         XGBE_STATS1_INFO(rx_oversized_frames),
1664         XGBE_STATS1_INFO(rx_jabber_frames),
1665         XGBE_STATS1_INFO(rx_undersized_frames),
1666         XGBE_STATS1_INFO(rx_fragments),
1667         XGBE_STATS1_INFO(overrun_type4),
1668         XGBE_STATS1_INFO(overrun_type5),
1669         XGBE_STATS1_INFO(rx_bytes),
1670         XGBE_STATS1_INFO(tx_good_frames),
1671         XGBE_STATS1_INFO(tx_broadcast_frames),
1672         XGBE_STATS1_INFO(tx_multicast_frames),
1673         XGBE_STATS1_INFO(tx_pause_frames),
1674         XGBE_STATS1_INFO(tx_deferred_frames),
1675         XGBE_STATS1_INFO(tx_collision_frames),
1676         XGBE_STATS1_INFO(tx_single_coll_frames),
1677         XGBE_STATS1_INFO(tx_mult_coll_frames),
1678         XGBE_STATS1_INFO(tx_excessive_collisions),
1679         XGBE_STATS1_INFO(tx_late_collisions),
1680         XGBE_STATS1_INFO(tx_underrun),
1681         XGBE_STATS1_INFO(tx_carrier_sense_errors),
1682         XGBE_STATS1_INFO(tx_bytes),
1683         XGBE_STATS1_INFO(tx_64byte_frames),
1684         XGBE_STATS1_INFO(tx_65_to_127byte_frames),
1685         XGBE_STATS1_INFO(tx_128_to_255byte_frames),
1686         XGBE_STATS1_INFO(tx_256_to_511byte_frames),
1687         XGBE_STATS1_INFO(tx_512_to_1023byte_frames),
1688         XGBE_STATS1_INFO(tx_1024byte_frames),
1689         XGBE_STATS1_INFO(net_bytes),
1690         XGBE_STATS1_INFO(rx_sof_overruns),
1691         XGBE_STATS1_INFO(rx_mof_overruns),
1692         XGBE_STATS1_INFO(rx_dma_overruns),
1693         /* XGBE module 2 */
1694         XGBE_STATS2_INFO(rx_good_frames),
1695         XGBE_STATS2_INFO(rx_broadcast_frames),
1696         XGBE_STATS2_INFO(rx_multicast_frames),
1697         XGBE_STATS2_INFO(rx_pause_frames),
1698         XGBE_STATS2_INFO(rx_crc_errors),
1699         XGBE_STATS2_INFO(rx_align_code_errors),
1700         XGBE_STATS2_INFO(rx_oversized_frames),
1701         XGBE_STATS2_INFO(rx_jabber_frames),
1702         XGBE_STATS2_INFO(rx_undersized_frames),
1703         XGBE_STATS2_INFO(rx_fragments),
1704         XGBE_STATS2_INFO(overrun_type4),
1705         XGBE_STATS2_INFO(overrun_type5),
1706         XGBE_STATS2_INFO(rx_bytes),
1707         XGBE_STATS2_INFO(tx_good_frames),
1708         XGBE_STATS2_INFO(tx_broadcast_frames),
1709         XGBE_STATS2_INFO(tx_multicast_frames),
1710         XGBE_STATS2_INFO(tx_pause_frames),
1711         XGBE_STATS2_INFO(tx_deferred_frames),
1712         XGBE_STATS2_INFO(tx_collision_frames),
1713         XGBE_STATS2_INFO(tx_single_coll_frames),
1714         XGBE_STATS2_INFO(tx_mult_coll_frames),
1715         XGBE_STATS2_INFO(tx_excessive_collisions),
1716         XGBE_STATS2_INFO(tx_late_collisions),
1717         XGBE_STATS2_INFO(tx_underrun),
1718         XGBE_STATS2_INFO(tx_carrier_sense_errors),
1719         XGBE_STATS2_INFO(tx_bytes),
1720         XGBE_STATS2_INFO(tx_64byte_frames),
1721         XGBE_STATS2_INFO(tx_65_to_127byte_frames),
1722         XGBE_STATS2_INFO(tx_128_to_255byte_frames),
1723         XGBE_STATS2_INFO(tx_256_to_511byte_frames),
1724         XGBE_STATS2_INFO(tx_512_to_1023byte_frames),
1725         XGBE_STATS2_INFO(tx_1024byte_frames),
1726         XGBE_STATS2_INFO(net_bytes),
1727         XGBE_STATS2_INFO(rx_sof_overruns),
1728         XGBE_STATS2_INFO(rx_mof_overruns),
1729         XGBE_STATS2_INFO(rx_dma_overruns),
1730 };
1731
1732 #define for_each_intf(i, priv) \
1733         list_for_each_entry((i), &(priv)->gbe_intf_head, gbe_intf_list)
1734
1735 #define for_each_sec_slave(slave, priv) \
1736         list_for_each_entry((slave), &(priv)->secondary_slaves, slave_list)
1737
1738 #define first_sec_slave(priv)                                   \
1739         list_first_entry(&priv->secondary_slaves, \
1740                         struct gbe_slave, slave_list)
1741
1742 static void keystone_get_drvinfo(struct net_device *ndev,
1743                                  struct ethtool_drvinfo *info)
1744 {
1745         strncpy(info->driver, NETCP_DRIVER_NAME, sizeof(info->driver));
1746         strncpy(info->version, NETCP_DRIVER_VERSION, sizeof(info->version));
1747 }
1748
1749 static u32 keystone_get_msglevel(struct net_device *ndev)
1750 {
1751         struct netcp_intf *netcp = netdev_priv(ndev);
1752
1753         return netcp->msg_enable;
1754 }
1755
1756 static void keystone_set_msglevel(struct net_device *ndev, u32 value)
1757 {
1758         struct netcp_intf *netcp = netdev_priv(ndev);
1759
1760         netcp->msg_enable = value;
1761 }
1762
1763 static struct gbe_intf *keystone_get_intf_data(struct netcp_intf *netcp)
1764 {
1765         struct gbe_intf *gbe_intf;
1766
1767         gbe_intf = netcp_module_get_intf_data(&gbe_module, netcp);
1768         if (!gbe_intf)
1769                 gbe_intf = netcp_module_get_intf_data(&xgbe_module, netcp);
1770
1771         return gbe_intf;
1772 }
1773
1774 static void keystone_get_stat_strings(struct net_device *ndev,
1775                                       uint32_t stringset, uint8_t *data)
1776 {
1777         struct netcp_intf *netcp = netdev_priv(ndev);
1778         struct gbe_intf *gbe_intf;
1779         struct gbe_priv *gbe_dev;
1780         int i;
1781
1782         gbe_intf = keystone_get_intf_data(netcp);
1783         if (!gbe_intf)
1784                 return;
1785         gbe_dev = gbe_intf->gbe_dev;
1786
1787         switch (stringset) {
1788         case ETH_SS_STATS:
1789                 for (i = 0; i < gbe_dev->num_et_stats; i++) {
1790                         memcpy(data, gbe_dev->et_stats[i].desc,
1791                                ETH_GSTRING_LEN);
1792                         data += ETH_GSTRING_LEN;
1793                 }
1794                 break;
1795         case ETH_SS_TEST:
1796                 break;
1797         }
1798 }
1799
1800 static int keystone_get_sset_count(struct net_device *ndev, int stringset)
1801 {
1802         struct netcp_intf *netcp = netdev_priv(ndev);
1803         struct gbe_intf *gbe_intf;
1804         struct gbe_priv *gbe_dev;
1805
1806         gbe_intf = keystone_get_intf_data(netcp);
1807         if (!gbe_intf)
1808                 return -EINVAL;
1809         gbe_dev = gbe_intf->gbe_dev;
1810
1811         switch (stringset) {
1812         case ETH_SS_TEST:
1813                 return 0;
1814         case ETH_SS_STATS:
1815                 return gbe_dev->num_et_stats;
1816         default:
1817                 return -EINVAL;
1818         }
1819 }
1820
1821 static void gbe_reset_mod_stats(struct gbe_priv *gbe_dev, int stats_mod)
1822 {
1823         void __iomem *base = gbe_dev->hw_stats_regs[stats_mod];
1824         u32  __iomem *p_stats_entry;
1825         int i;
1826
1827         for (i = 0; i < gbe_dev->num_et_stats; i++) {
1828                 if (gbe_dev->et_stats[i].type == stats_mod) {
1829                         p_stats_entry = base + gbe_dev->et_stats[i].offset;
1830                         gbe_dev->hw_stats[i] = 0;
1831                         gbe_dev->hw_stats_prev[i] = readl(p_stats_entry);
1832                 }
1833         }
1834 }
1835
1836 static inline void gbe_update_hw_stats_entry(struct gbe_priv *gbe_dev,
1837                                              int et_stats_entry)
1838 {
1839         void __iomem *base = NULL;
1840         u32  __iomem *p_stats_entry;
1841         u32 curr, delta;
1842
1843         /* The hw_stats_regs pointers are already
1844          * properly set to point to the right base:
1845          */
1846         base = gbe_dev->hw_stats_regs[gbe_dev->et_stats[et_stats_entry].type];
1847         p_stats_entry = base + gbe_dev->et_stats[et_stats_entry].offset;
1848         curr = readl(p_stats_entry);
1849         delta = curr - gbe_dev->hw_stats_prev[et_stats_entry];
1850         gbe_dev->hw_stats_prev[et_stats_entry] = curr;
1851         gbe_dev->hw_stats[et_stats_entry] += delta;
1852 }
1853
1854 static void gbe_update_stats(struct gbe_priv *gbe_dev, uint64_t *data)
1855 {
1856         int i;
1857
1858         for (i = 0; i < gbe_dev->num_et_stats; i++) {
1859                 gbe_update_hw_stats_entry(gbe_dev, i);
1860
1861                 if (data)
1862                         data[i] = gbe_dev->hw_stats[i];
1863         }
1864 }
1865
1866 static inline void gbe_stats_mod_visible_ver14(struct gbe_priv *gbe_dev,
1867                                                int stats_mod)
1868 {
1869         u32 val;
1870
1871         val = readl(GBE_REG_ADDR(gbe_dev, switch_regs, stat_port_en));
1872
1873         switch (stats_mod) {
1874         case GBE_STATSA_MODULE:
1875         case GBE_STATSB_MODULE:
1876                 val &= ~GBE_STATS_CD_SEL;
1877                 break;
1878         case GBE_STATSC_MODULE:
1879         case GBE_STATSD_MODULE:
1880                 val |= GBE_STATS_CD_SEL;
1881                 break;
1882         default:
1883                 return;
1884         }
1885
1886         /* make the stat module visible */
1887         writel(val, GBE_REG_ADDR(gbe_dev, switch_regs, stat_port_en));
1888 }
1889
1890 static void gbe_reset_mod_stats_ver14(struct gbe_priv *gbe_dev, int stats_mod)
1891 {
1892         gbe_stats_mod_visible_ver14(gbe_dev, stats_mod);
1893         gbe_reset_mod_stats(gbe_dev, stats_mod);
1894 }
1895
1896 static void gbe_update_stats_ver14(struct gbe_priv *gbe_dev, uint64_t *data)
1897 {
1898         u32 half_num_et_stats = (gbe_dev->num_et_stats / 2);
1899         int et_entry, j, pair;
1900
1901         for (pair = 0; pair < 2; pair++) {
1902                 gbe_stats_mod_visible_ver14(gbe_dev, (pair ?
1903                                                       GBE_STATSC_MODULE :
1904                                                       GBE_STATSA_MODULE));
1905
1906                 for (j = 0; j < half_num_et_stats; j++) {
1907                         et_entry = pair * half_num_et_stats + j;
1908                         gbe_update_hw_stats_entry(gbe_dev, et_entry);
1909
1910                         if (data)
1911                                 data[et_entry] = gbe_dev->hw_stats[et_entry];
1912                 }
1913         }
1914 }
1915
1916 static void keystone_get_ethtool_stats(struct net_device *ndev,
1917                                        struct ethtool_stats *stats,
1918                                        uint64_t *data)
1919 {
1920         struct netcp_intf *netcp = netdev_priv(ndev);
1921         struct gbe_intf *gbe_intf;
1922         struct gbe_priv *gbe_dev;
1923
1924         gbe_intf = keystone_get_intf_data(netcp);
1925         if (!gbe_intf)
1926                 return;
1927
1928         gbe_dev = gbe_intf->gbe_dev;
1929         spin_lock_bh(&gbe_dev->hw_stats_lock);
1930         if (IS_SS_ID_VER_14(gbe_dev))
1931                 gbe_update_stats_ver14(gbe_dev, data);
1932         else
1933                 gbe_update_stats(gbe_dev, data);
1934         spin_unlock_bh(&gbe_dev->hw_stats_lock);
1935 }
1936
1937 static int keystone_get_link_ksettings(struct net_device *ndev,
1938                                        struct ethtool_link_ksettings *cmd)
1939 {
1940         struct netcp_intf *netcp = netdev_priv(ndev);
1941         struct phy_device *phy = ndev->phydev;
1942         struct gbe_intf *gbe_intf;
1943
1944         if (!phy)
1945                 return -EINVAL;
1946
1947         gbe_intf = keystone_get_intf_data(netcp);
1948         if (!gbe_intf)
1949                 return -EINVAL;
1950
1951         if (!gbe_intf->slave)
1952                 return -EINVAL;
1953
1954         phy_ethtool_ksettings_get(phy, cmd);
1955         cmd->base.port = gbe_intf->slave->phy_port_t;
1956
1957         return 0;
1958 }
1959
1960 static int keystone_set_link_ksettings(struct net_device *ndev,
1961                                        const struct ethtool_link_ksettings *cmd)
1962 {
1963         struct netcp_intf *netcp = netdev_priv(ndev);
1964         struct phy_device *phy = ndev->phydev;
1965         struct gbe_intf *gbe_intf;
1966         u8 port = cmd->base.port;
1967         u32 advertising, supported;
1968         u32 features;
1969
1970         ethtool_convert_link_mode_to_legacy_u32(&advertising,
1971                                                 cmd->link_modes.advertising);
1972         ethtool_convert_link_mode_to_legacy_u32(&supported,
1973                                                 cmd->link_modes.supported);
1974         features = advertising & supported;
1975
1976         if (!phy)
1977                 return -EINVAL;
1978
1979         gbe_intf = keystone_get_intf_data(netcp);
1980         if (!gbe_intf)
1981                 return -EINVAL;
1982
1983         if (!gbe_intf->slave)
1984                 return -EINVAL;
1985
1986         if (port != gbe_intf->slave->phy_port_t) {
1987                 if ((port == PORT_TP) && !(features & ADVERTISED_TP))
1988                         return -EINVAL;
1989
1990                 if ((port == PORT_AUI) && !(features & ADVERTISED_AUI))
1991                         return -EINVAL;
1992
1993                 if ((port == PORT_BNC) && !(features & ADVERTISED_BNC))
1994                         return -EINVAL;
1995
1996                 if ((port == PORT_MII) && !(features & ADVERTISED_MII))
1997                         return -EINVAL;
1998
1999                 if ((port == PORT_FIBRE) && !(features & ADVERTISED_FIBRE))
2000                         return -EINVAL;
2001         }
2002
2003         gbe_intf->slave->phy_port_t = port;
2004         return phy_ethtool_ksettings_set(phy, cmd);
2005 }
2006
2007 #if IS_ENABLED(CONFIG_TI_CPTS)
2008 static int keystone_get_ts_info(struct net_device *ndev,
2009                                 struct ethtool_ts_info *info)
2010 {
2011         struct netcp_intf *netcp = netdev_priv(ndev);
2012         struct gbe_intf *gbe_intf;
2013
2014         gbe_intf = netcp_module_get_intf_data(&gbe_module, netcp);
2015         if (!gbe_intf || !gbe_intf->gbe_dev->cpts)
2016                 return -EINVAL;
2017
2018         info->so_timestamping =
2019                 SOF_TIMESTAMPING_TX_HARDWARE |
2020                 SOF_TIMESTAMPING_TX_SOFTWARE |
2021                 SOF_TIMESTAMPING_RX_HARDWARE |
2022                 SOF_TIMESTAMPING_RX_SOFTWARE |
2023                 SOF_TIMESTAMPING_SOFTWARE |
2024                 SOF_TIMESTAMPING_RAW_HARDWARE;
2025         info->phc_index = gbe_intf->gbe_dev->cpts->phc_index;
2026         info->tx_types =
2027                 (1 << HWTSTAMP_TX_OFF) |
2028                 (1 << HWTSTAMP_TX_ON);
2029         info->rx_filters =
2030                 (1 << HWTSTAMP_FILTER_NONE) |
2031                 (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) |
2032                 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT);
2033         return 0;
2034 }
2035 #else
2036 static int keystone_get_ts_info(struct net_device *ndev,
2037                                 struct ethtool_ts_info *info)
2038 {
2039         info->so_timestamping =
2040                 SOF_TIMESTAMPING_TX_SOFTWARE |
2041                 SOF_TIMESTAMPING_RX_SOFTWARE |
2042                 SOF_TIMESTAMPING_SOFTWARE;
2043         info->phc_index = -1;
2044         info->tx_types = 0;
2045         info->rx_filters = 0;
2046         return 0;
2047 }
2048 #endif /* CONFIG_TI_CPTS */
2049
2050 static const struct ethtool_ops keystone_ethtool_ops = {
2051         .get_drvinfo            = keystone_get_drvinfo,
2052         .get_link               = ethtool_op_get_link,
2053         .get_msglevel           = keystone_get_msglevel,
2054         .set_msglevel           = keystone_set_msglevel,
2055         .get_strings            = keystone_get_stat_strings,
2056         .get_sset_count         = keystone_get_sset_count,
2057         .get_ethtool_stats      = keystone_get_ethtool_stats,
2058         .get_link_ksettings     = keystone_get_link_ksettings,
2059         .set_link_ksettings     = keystone_set_link_ksettings,
2060         .get_ts_info            = keystone_get_ts_info,
2061 };
2062
2063 static void gbe_set_slave_mac(struct gbe_slave *slave,
2064                               struct gbe_intf *gbe_intf)
2065 {
2066         struct net_device *ndev = gbe_intf->ndev;
2067
2068         writel(mac_hi(ndev->dev_addr), GBE_REG_ADDR(slave, port_regs, sa_hi));
2069         writel(mac_lo(ndev->dev_addr), GBE_REG_ADDR(slave, port_regs, sa_lo));
2070 }
2071
2072 static int gbe_get_slave_port(struct gbe_priv *priv, u32 slave_num)
2073 {
2074         if (priv->host_port == 0)
2075                 return slave_num + 1;
2076
2077         return slave_num;
2078 }
2079
2080 static void netcp_ethss_link_state_action(struct gbe_priv *gbe_dev,
2081                                           struct net_device *ndev,
2082                                           struct gbe_slave *slave,
2083                                           int up)
2084 {
2085         struct phy_device *phy = slave->phy;
2086         u32 mac_control = 0;
2087
2088         if (up) {
2089                 mac_control = slave->mac_control;
2090                 if (phy && (phy->speed == SPEED_1000)) {
2091                         mac_control |= MACSL_GIG_MODE;
2092                         mac_control &= ~MACSL_XGIG_MODE;
2093                 } else if (phy && (phy->speed == SPEED_10000)) {
2094                         mac_control |= MACSL_XGIG_MODE;
2095                         mac_control &= ~MACSL_GIG_MODE;
2096                 }
2097
2098                 writel(mac_control, GBE_REG_ADDR(slave, emac_regs,
2099                                                  mac_control));
2100
2101                 cpsw_ale_control_set(gbe_dev->ale, slave->port_num,
2102                                      ALE_PORT_STATE,
2103                                      ALE_PORT_STATE_FORWARD);
2104
2105                 if (ndev && slave->open &&
2106                     ((slave->link_interface != SGMII_LINK_MAC_PHY) &&
2107                     (slave->link_interface != RGMII_LINK_MAC_PHY) &&
2108                     (slave->link_interface != XGMII_LINK_MAC_PHY)))
2109                         netif_carrier_on(ndev);
2110         } else {
2111                 writel(mac_control, GBE_REG_ADDR(slave, emac_regs,
2112                                                  mac_control));
2113                 cpsw_ale_control_set(gbe_dev->ale, slave->port_num,
2114                                      ALE_PORT_STATE,
2115                                      ALE_PORT_STATE_DISABLE);
2116                 if (ndev &&
2117                     ((slave->link_interface != SGMII_LINK_MAC_PHY) &&
2118                     (slave->link_interface != RGMII_LINK_MAC_PHY) &&
2119                     (slave->link_interface != XGMII_LINK_MAC_PHY)))
2120                         netif_carrier_off(ndev);
2121         }
2122
2123         if (phy)
2124                 phy_print_status(phy);
2125 }
2126
2127 static bool gbe_phy_link_status(struct gbe_slave *slave)
2128 {
2129          return !slave->phy || slave->phy->link;
2130 }
2131
2132 #define RGMII_REG_STATUS_LINK   BIT(0)
2133
2134 static void netcp_2u_rgmii_get_port_link(struct gbe_priv *gbe_dev, bool *status)
2135 {
2136         u32 val = 0;
2137
2138         val = readl(GBE_REG_ADDR(gbe_dev, ss_regs, rgmii_status));
2139         *status = !!(val & RGMII_REG_STATUS_LINK);
2140 }
2141
2142 static void netcp_ethss_update_link_state(struct gbe_priv *gbe_dev,
2143                                           struct gbe_slave *slave,
2144                                           struct net_device *ndev)
2145 {
2146         bool sw_link_state = true, phy_link_state;
2147         int sp = slave->slave_num, link_state;
2148
2149         if (!slave->open)
2150                 return;
2151
2152         if (SLAVE_LINK_IS_RGMII(slave))
2153                 netcp_2u_rgmii_get_port_link(gbe_dev,
2154                                              &sw_link_state);
2155         if (SLAVE_LINK_IS_SGMII(slave))
2156                 sw_link_state =
2157                 netcp_sgmii_get_port_link(SGMII_BASE(gbe_dev, sp), sp);
2158
2159         phy_link_state = gbe_phy_link_status(slave);
2160         link_state = phy_link_state & sw_link_state;
2161
2162         if (atomic_xchg(&slave->link_state, link_state) != link_state)
2163                 netcp_ethss_link_state_action(gbe_dev, ndev, slave,
2164                                               link_state);
2165 }
2166
2167 static void xgbe_adjust_link(struct net_device *ndev)
2168 {
2169         struct netcp_intf *netcp = netdev_priv(ndev);
2170         struct gbe_intf *gbe_intf;
2171
2172         gbe_intf = netcp_module_get_intf_data(&xgbe_module, netcp);
2173         if (!gbe_intf)
2174                 return;
2175
2176         netcp_ethss_update_link_state(gbe_intf->gbe_dev, gbe_intf->slave,
2177                                       ndev);
2178 }
2179
2180 static void gbe_adjust_link(struct net_device *ndev)
2181 {
2182         struct netcp_intf *netcp = netdev_priv(ndev);
2183         struct gbe_intf *gbe_intf;
2184
2185         gbe_intf = netcp_module_get_intf_data(&gbe_module, netcp);
2186         if (!gbe_intf)
2187                 return;
2188
2189         netcp_ethss_update_link_state(gbe_intf->gbe_dev, gbe_intf->slave,
2190                                       ndev);
2191 }
2192
2193 static void gbe_adjust_link_sec_slaves(struct net_device *ndev)
2194 {
2195         struct gbe_priv *gbe_dev = netdev_priv(ndev);
2196         struct gbe_slave *slave;
2197
2198         for_each_sec_slave(slave, gbe_dev)
2199                 netcp_ethss_update_link_state(gbe_dev, slave, NULL);
2200 }
2201
2202 /* Reset EMAC
2203  * Soft reset is set and polled until clear, or until a timeout occurs
2204  */
2205 static int gbe_port_reset(struct gbe_slave *slave)
2206 {
2207         u32 i, v;
2208
2209         /* Set the soft reset bit */
2210         writel(SOFT_RESET, GBE_REG_ADDR(slave, emac_regs, soft_reset));
2211
2212         /* Wait for the bit to clear */
2213         for (i = 0; i < DEVICE_EMACSL_RESET_POLL_COUNT; i++) {
2214                 v = readl(GBE_REG_ADDR(slave, emac_regs, soft_reset));
2215                 if ((v & SOFT_RESET_MASK) != SOFT_RESET)
2216                         return 0;
2217         }
2218
2219         /* Timeout on the reset */
2220         return GMACSL_RET_WARN_RESET_INCOMPLETE;
2221 }
2222
2223 /* Configure EMAC */
2224 static void gbe_port_config(struct gbe_priv *gbe_dev, struct gbe_slave *slave,
2225                             int max_rx_len)
2226 {
2227         void __iomem *rx_maxlen_reg;
2228         u32 xgmii_mode;
2229
2230         if (max_rx_len > NETCP_MAX_FRAME_SIZE)
2231                 max_rx_len = NETCP_MAX_FRAME_SIZE;
2232
2233         /* Enable correct MII mode at SS level */
2234         if (IS_SS_ID_XGBE(gbe_dev) &&
2235             (slave->link_interface >= XGMII_LINK_MAC_PHY)) {
2236                 xgmii_mode = readl(GBE_REG_ADDR(gbe_dev, ss_regs, control));
2237                 xgmii_mode |= (1 << slave->slave_num);
2238                 writel(xgmii_mode, GBE_REG_ADDR(gbe_dev, ss_regs, control));
2239         }
2240
2241         if (IS_SS_ID_MU(gbe_dev))
2242                 rx_maxlen_reg = GBE_REG_ADDR(slave, port_regs, rx_maxlen);
2243         else
2244                 rx_maxlen_reg = GBE_REG_ADDR(slave, emac_regs, rx_maxlen);
2245
2246         writel(max_rx_len, rx_maxlen_reg);
2247         writel(slave->mac_control, GBE_REG_ADDR(slave, emac_regs, mac_control));
2248 }
2249
2250 static void gbe_sgmii_rtreset(struct gbe_priv *priv,
2251                               struct gbe_slave *slave, bool set)
2252 {
2253         if (SLAVE_LINK_IS_XGMII(slave))
2254                 return;
2255
2256         netcp_sgmii_rtreset(SGMII_BASE(priv, slave->slave_num),
2257                             slave->slave_num, set);
2258 }
2259
2260 static void gbe_slave_stop(struct gbe_intf *intf)
2261 {
2262         struct gbe_priv *gbe_dev = intf->gbe_dev;
2263         struct gbe_slave *slave = intf->slave;
2264
2265         if (!IS_SS_ID_2U(gbe_dev))
2266                 gbe_sgmii_rtreset(gbe_dev, slave, true);
2267         gbe_port_reset(slave);
2268         /* Disable forwarding */
2269         cpsw_ale_control_set(gbe_dev->ale, slave->port_num,
2270                              ALE_PORT_STATE, ALE_PORT_STATE_DISABLE);
2271         cpsw_ale_del_mcast(gbe_dev->ale, intf->ndev->broadcast,
2272                            1 << slave->port_num, 0, 0);
2273
2274         if (!slave->phy)
2275                 return;
2276
2277         phy_stop(slave->phy);
2278         phy_disconnect(slave->phy);
2279         slave->phy = NULL;
2280 }
2281
2282 static void gbe_sgmii_config(struct gbe_priv *priv, struct gbe_slave *slave)
2283 {
2284         if (SLAVE_LINK_IS_XGMII(slave))
2285                 return;
2286
2287         netcp_sgmii_reset(SGMII_BASE(priv, slave->slave_num), slave->slave_num);
2288         netcp_sgmii_config(SGMII_BASE(priv, slave->slave_num), slave->slave_num,
2289                            slave->link_interface);
2290 }
2291
2292 static int gbe_slave_open(struct gbe_intf *gbe_intf)
2293 {
2294         struct gbe_priv *priv = gbe_intf->gbe_dev;
2295         struct gbe_slave *slave = gbe_intf->slave;
2296         phy_interface_t phy_mode;
2297         bool has_phy = false;
2298
2299         void (*hndlr)(struct net_device *) = gbe_adjust_link;
2300
2301         if (!IS_SS_ID_2U(priv))
2302                 gbe_sgmii_config(priv, slave);
2303         gbe_port_reset(slave);
2304         if (!IS_SS_ID_2U(priv))
2305                 gbe_sgmii_rtreset(priv, slave, false);
2306         gbe_port_config(priv, slave, priv->rx_packet_max);
2307         gbe_set_slave_mac(slave, gbe_intf);
2308         /* For NU & 2U switch, map the vlan priorities to zero
2309          * as we only configure to use priority 0
2310          */
2311         if (IS_SS_ID_MU(priv))
2312                 writel(HOST_TX_PRI_MAP_DEFAULT,
2313                        GBE_REG_ADDR(slave, port_regs, rx_pri_map));
2314
2315         /* enable forwarding */
2316         cpsw_ale_control_set(priv->ale, slave->port_num,
2317                              ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
2318         cpsw_ale_add_mcast(priv->ale, gbe_intf->ndev->broadcast,
2319                            1 << slave->port_num, 0, 0, ALE_MCAST_FWD_2);
2320
2321         if (slave->link_interface == SGMII_LINK_MAC_PHY) {
2322                 has_phy = true;
2323                 phy_mode = PHY_INTERFACE_MODE_SGMII;
2324                 slave->phy_port_t = PORT_MII;
2325         } else if (slave->link_interface == XGMII_LINK_MAC_PHY) {
2326                 has_phy = true;
2327                 phy_mode = PHY_INTERFACE_MODE_NA;
2328                 slave->phy_port_t = PORT_FIBRE;
2329         }
2330
2331         if (has_phy) {
2332                 if (IS_SS_ID_XGBE(priv))
2333                         hndlr = xgbe_adjust_link;
2334
2335                 slave->phy = of_phy_connect(gbe_intf->ndev,
2336                                             slave->phy_node,
2337                                             hndlr, 0,
2338                                             phy_mode);
2339                 if (!slave->phy) {
2340                         dev_err(priv->dev, "phy not found on slave %d\n",
2341                                 slave->slave_num);
2342                         return -ENODEV;
2343                 }
2344                 dev_dbg(priv->dev, "phy found: id is: 0x%s\n",
2345                         phydev_name(slave->phy));
2346                 phy_start(slave->phy);
2347         }
2348         return 0;
2349 }
2350
2351 static void gbe_init_host_port(struct gbe_priv *priv)
2352 {
2353         int bypass_en = 1;
2354
2355         /* Host Tx Pri */
2356         if (IS_SS_ID_NU(priv) || IS_SS_ID_XGBE(priv))
2357                 writel(HOST_TX_PRI_MAP_DEFAULT,
2358                        GBE_REG_ADDR(priv, host_port_regs, tx_pri_map));
2359
2360         /* Max length register */
2361         writel(NETCP_MAX_FRAME_SIZE, GBE_REG_ADDR(priv, host_port_regs,
2362                                                   rx_maxlen));
2363
2364         cpsw_ale_start(priv->ale);
2365
2366         if (priv->enable_ale)
2367                 bypass_en = 0;
2368
2369         cpsw_ale_control_set(priv->ale, 0, ALE_BYPASS, bypass_en);
2370
2371         cpsw_ale_control_set(priv->ale, 0, ALE_NO_PORT_VLAN, 1);
2372
2373         cpsw_ale_control_set(priv->ale, priv->host_port,
2374                              ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
2375
2376         cpsw_ale_control_set(priv->ale, 0,
2377                              ALE_PORT_UNKNOWN_VLAN_MEMBER,
2378                              GBE_PORT_MASK(priv->ale_ports));
2379
2380         cpsw_ale_control_set(priv->ale, 0,
2381                              ALE_PORT_UNKNOWN_MCAST_FLOOD,
2382                              GBE_PORT_MASK(priv->ale_ports - 1));
2383
2384         cpsw_ale_control_set(priv->ale, 0,
2385                              ALE_PORT_UNKNOWN_REG_MCAST_FLOOD,
2386                              GBE_PORT_MASK(priv->ale_ports));
2387
2388         cpsw_ale_control_set(priv->ale, 0,
2389                              ALE_PORT_UNTAGGED_EGRESS,
2390                              GBE_PORT_MASK(priv->ale_ports));
2391 }
2392
2393 static void gbe_add_mcast_addr(struct gbe_intf *gbe_intf, u8 *addr)
2394 {
2395         struct gbe_priv *gbe_dev = gbe_intf->gbe_dev;
2396         u16 vlan_id;
2397
2398         cpsw_ale_add_mcast(gbe_dev->ale, addr,
2399                            GBE_PORT_MASK(gbe_dev->ale_ports), 0, 0,
2400                            ALE_MCAST_FWD_2);
2401         for_each_set_bit(vlan_id, gbe_intf->active_vlans, VLAN_N_VID) {
2402                 cpsw_ale_add_mcast(gbe_dev->ale, addr,
2403                                    GBE_PORT_MASK(gbe_dev->ale_ports),
2404                                    ALE_VLAN, vlan_id, ALE_MCAST_FWD_2);
2405         }
2406 }
2407
2408 static void gbe_add_ucast_addr(struct gbe_intf *gbe_intf, u8 *addr)
2409 {
2410         struct gbe_priv *gbe_dev = gbe_intf->gbe_dev;
2411         u16 vlan_id;
2412
2413         cpsw_ale_add_ucast(gbe_dev->ale, addr, gbe_dev->host_port, 0, 0);
2414
2415         for_each_set_bit(vlan_id, gbe_intf->active_vlans, VLAN_N_VID)
2416                 cpsw_ale_add_ucast(gbe_dev->ale, addr, gbe_dev->host_port,
2417                                    ALE_VLAN, vlan_id);
2418 }
2419
2420 static void gbe_del_mcast_addr(struct gbe_intf *gbe_intf, u8 *addr)
2421 {
2422         struct gbe_priv *gbe_dev = gbe_intf->gbe_dev;
2423         u16 vlan_id;
2424
2425         cpsw_ale_del_mcast(gbe_dev->ale, addr, 0, 0, 0);
2426
2427         for_each_set_bit(vlan_id, gbe_intf->active_vlans, VLAN_N_VID) {
2428                 cpsw_ale_del_mcast(gbe_dev->ale, addr, 0, ALE_VLAN, vlan_id);
2429         }
2430 }
2431
2432 static void gbe_del_ucast_addr(struct gbe_intf *gbe_intf, u8 *addr)
2433 {
2434         struct gbe_priv *gbe_dev = gbe_intf->gbe_dev;
2435         u16 vlan_id;
2436
2437         cpsw_ale_del_ucast(gbe_dev->ale, addr, gbe_dev->host_port, 0, 0);
2438
2439         for_each_set_bit(vlan_id, gbe_intf->active_vlans, VLAN_N_VID) {
2440                 cpsw_ale_del_ucast(gbe_dev->ale, addr, gbe_dev->host_port,
2441                                    ALE_VLAN, vlan_id);
2442         }
2443 }
2444
2445 static int gbe_add_addr(void *intf_priv, struct netcp_addr *naddr)
2446 {
2447         struct gbe_intf *gbe_intf = intf_priv;
2448         struct gbe_priv *gbe_dev = gbe_intf->gbe_dev;
2449
2450         dev_dbg(gbe_dev->dev, "ethss adding address %pM, type %d\n",
2451                 naddr->addr, naddr->type);
2452
2453         switch (naddr->type) {
2454         case ADDR_MCAST:
2455         case ADDR_BCAST:
2456                 gbe_add_mcast_addr(gbe_intf, naddr->addr);
2457                 break;
2458         case ADDR_UCAST:
2459         case ADDR_DEV:
2460                 gbe_add_ucast_addr(gbe_intf, naddr->addr);
2461                 break;
2462         case ADDR_ANY:
2463                 /* nothing to do for promiscuous */
2464         default:
2465                 break;
2466         }
2467
2468         return 0;
2469 }
2470
2471 static int gbe_del_addr(void *intf_priv, struct netcp_addr *naddr)
2472 {
2473         struct gbe_intf *gbe_intf = intf_priv;
2474         struct gbe_priv *gbe_dev = gbe_intf->gbe_dev;
2475
2476         dev_dbg(gbe_dev->dev, "ethss deleting address %pM, type %d\n",
2477                 naddr->addr, naddr->type);
2478
2479         switch (naddr->type) {
2480         case ADDR_MCAST:
2481         case ADDR_BCAST:
2482                 gbe_del_mcast_addr(gbe_intf, naddr->addr);
2483                 break;
2484         case ADDR_UCAST:
2485         case ADDR_DEV:
2486                 gbe_del_ucast_addr(gbe_intf, naddr->addr);
2487                 break;
2488         case ADDR_ANY:
2489                 /* nothing to do for promiscuous */
2490         default:
2491                 break;
2492         }
2493
2494         return 0;
2495 }
2496
2497 static int gbe_add_vid(void *intf_priv, int vid)
2498 {
2499         struct gbe_intf *gbe_intf = intf_priv;
2500         struct gbe_priv *gbe_dev = gbe_intf->gbe_dev;
2501
2502         set_bit(vid, gbe_intf->active_vlans);
2503
2504         cpsw_ale_add_vlan(gbe_dev->ale, vid,
2505                           GBE_PORT_MASK(gbe_dev->ale_ports),
2506                           GBE_MASK_NO_PORTS,
2507                           GBE_PORT_MASK(gbe_dev->ale_ports),
2508                           GBE_PORT_MASK(gbe_dev->ale_ports - 1));
2509
2510         return 0;
2511 }
2512
2513 static int gbe_del_vid(void *intf_priv, int vid)
2514 {
2515         struct gbe_intf *gbe_intf = intf_priv;
2516         struct gbe_priv *gbe_dev = gbe_intf->gbe_dev;
2517
2518         cpsw_ale_del_vlan(gbe_dev->ale, vid, 0);
2519         clear_bit(vid, gbe_intf->active_vlans);
2520         return 0;
2521 }
2522
2523 #if IS_ENABLED(CONFIG_TI_CPTS)
2524 #define HAS_PHY_TXTSTAMP(p) ((p)->drv && (p)->drv->txtstamp)
2525 #define HAS_PHY_RXTSTAMP(p) ((p)->drv && (p)->drv->rxtstamp)
2526
2527 static void gbe_txtstamp(void *context, struct sk_buff *skb)
2528 {
2529         struct gbe_intf *gbe_intf = context;
2530         struct gbe_priv *gbe_dev = gbe_intf->gbe_dev;
2531
2532         cpts_tx_timestamp(gbe_dev->cpts, skb);
2533 }
2534
2535 static bool gbe_need_txtstamp(struct gbe_intf *gbe_intf,
2536                               const struct netcp_packet *p_info)
2537 {
2538         struct sk_buff *skb = p_info->skb;
2539
2540         return cpts_can_timestamp(gbe_intf->gbe_dev->cpts, skb);
2541 }
2542
2543 static int gbe_txtstamp_mark_pkt(struct gbe_intf *gbe_intf,
2544                                  struct netcp_packet *p_info)
2545 {
2546         struct phy_device *phydev = p_info->skb->dev->phydev;
2547         struct gbe_priv *gbe_dev = gbe_intf->gbe_dev;
2548
2549         if (!(skb_shinfo(p_info->skb)->tx_flags & SKBTX_HW_TSTAMP) ||
2550             !cpts_is_tx_enabled(gbe_dev->cpts))
2551                 return 0;
2552
2553         /* If phy has the txtstamp api, assume it will do it.
2554          * We mark it here because skb_tx_timestamp() is called
2555          * after all the txhooks are called.
2556          */
2557         if (phydev && HAS_PHY_TXTSTAMP(phydev)) {
2558                 skb_shinfo(p_info->skb)->tx_flags |= SKBTX_IN_PROGRESS;
2559                 return 0;
2560         }
2561
2562         if (gbe_need_txtstamp(gbe_intf, p_info)) {
2563                 p_info->txtstamp = gbe_txtstamp;
2564                 p_info->ts_context = (void *)gbe_intf;
2565                 skb_shinfo(p_info->skb)->tx_flags |= SKBTX_IN_PROGRESS;
2566         }
2567
2568         return 0;
2569 }
2570
2571 static int gbe_rxtstamp(struct gbe_intf *gbe_intf, struct netcp_packet *p_info)
2572 {
2573         struct phy_device *phydev = p_info->skb->dev->phydev;
2574         struct gbe_priv *gbe_dev = gbe_intf->gbe_dev;
2575
2576         if (p_info->rxtstamp_complete)
2577                 return 0;
2578
2579         if (phydev && HAS_PHY_RXTSTAMP(phydev)) {
2580                 p_info->rxtstamp_complete = true;
2581                 return 0;
2582         }
2583
2584         cpts_rx_timestamp(gbe_dev->cpts, p_info->skb);
2585         p_info->rxtstamp_complete = true;
2586
2587         return 0;
2588 }
2589
2590 static int gbe_hwtstamp_get(struct gbe_intf *gbe_intf, struct ifreq *ifr)
2591 {
2592         struct gbe_priv *gbe_dev = gbe_intf->gbe_dev;
2593         struct cpts *cpts = gbe_dev->cpts;
2594         struct hwtstamp_config cfg;
2595
2596         if (!cpts)
2597                 return -EOPNOTSUPP;
2598
2599         cfg.flags = 0;
2600         cfg.tx_type = cpts_is_tx_enabled(cpts) ?
2601                       HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF;
2602         cfg.rx_filter = (cpts_is_rx_enabled(cpts) ?
2603                          cpts->rx_enable : HWTSTAMP_FILTER_NONE);
2604
2605         return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
2606 }
2607
2608 static void gbe_hwtstamp(struct gbe_intf *gbe_intf)
2609 {
2610         struct gbe_priv *gbe_dev = gbe_intf->gbe_dev;
2611         struct gbe_slave *slave = gbe_intf->slave;
2612         u32 ts_en, seq_id, ctl;
2613
2614         if (!cpts_is_rx_enabled(gbe_dev->cpts) &&
2615             !cpts_is_tx_enabled(gbe_dev->cpts)) {
2616                 writel(0, GBE_REG_ADDR(slave, port_regs, ts_ctl));
2617                 return;
2618         }
2619
2620         seq_id = (30 << TS_SEQ_ID_OFS_SHIFT) | ETH_P_1588;
2621         ts_en = EVENT_MSG_BITS << TS_MSG_TYPE_EN_SHIFT;
2622         ctl = ETH_P_1588 | TS_TTL_NONZERO |
2623                 (slave->ts_ctl.dst_port_map << TS_CTL_DST_PORT_SHIFT) |
2624                 (slave->ts_ctl.uni ?  TS_UNI_EN :
2625                         slave->ts_ctl.maddr_map << TS_CTL_MADDR_SHIFT);
2626
2627         if (cpts_is_tx_enabled(gbe_dev->cpts))
2628                 ts_en |= (TS_TX_ANX_ALL_EN | TS_TX_VLAN_LT1_EN);
2629
2630         if (cpts_is_rx_enabled(gbe_dev->cpts))
2631                 ts_en |= (TS_RX_ANX_ALL_EN | TS_RX_VLAN_LT1_EN);
2632
2633         writel(ts_en,  GBE_REG_ADDR(slave, port_regs, ts_ctl));
2634         writel(seq_id, GBE_REG_ADDR(slave, port_regs, ts_seq_ltype));
2635         writel(ctl,    GBE_REG_ADDR(slave, port_regs, ts_ctl_ltype2));
2636 }
2637
2638 static int gbe_hwtstamp_set(struct gbe_intf *gbe_intf, struct ifreq *ifr)
2639 {
2640         struct gbe_priv *gbe_dev = gbe_intf->gbe_dev;
2641         struct cpts *cpts = gbe_dev->cpts;
2642         struct hwtstamp_config cfg;
2643
2644         if (!cpts)
2645                 return -EOPNOTSUPP;
2646
2647         if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg)))
2648                 return -EFAULT;
2649
2650         /* reserved for future extensions */
2651         if (cfg.flags)
2652                 return -EINVAL;
2653
2654         switch (cfg.tx_type) {
2655         case HWTSTAMP_TX_OFF:
2656                 cpts_tx_enable(cpts, 0);
2657                 break;
2658         case HWTSTAMP_TX_ON:
2659                 cpts_tx_enable(cpts, 1);
2660                 break;
2661         default:
2662                 return -ERANGE;
2663         }
2664
2665         switch (cfg.rx_filter) {
2666         case HWTSTAMP_FILTER_NONE:
2667                 cpts_rx_enable(cpts, 0);
2668                 break;
2669         case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
2670         case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
2671         case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
2672                 cpts_rx_enable(cpts, HWTSTAMP_FILTER_PTP_V1_L4_EVENT);
2673                 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
2674                 break;
2675         case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
2676         case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
2677         case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
2678         case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
2679         case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
2680         case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
2681         case HWTSTAMP_FILTER_PTP_V2_EVENT:
2682         case HWTSTAMP_FILTER_PTP_V2_SYNC:
2683         case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
2684                 cpts_rx_enable(cpts, HWTSTAMP_FILTER_PTP_V2_EVENT);
2685                 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
2686                 break;
2687         default:
2688                 return -ERANGE;
2689         }
2690
2691         gbe_hwtstamp(gbe_intf);
2692
2693         return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
2694 }
2695
2696 static void gbe_register_cpts(struct gbe_priv *gbe_dev)
2697 {
2698         if (!gbe_dev->cpts)
2699                 return;
2700
2701         if (gbe_dev->cpts_registered > 0)
2702                 goto done;
2703
2704         if (cpts_register(gbe_dev->cpts)) {
2705                 dev_err(gbe_dev->dev, "error registering cpts device\n");
2706                 return;
2707         }
2708
2709 done:
2710         ++gbe_dev->cpts_registered;
2711 }
2712
2713 static void gbe_unregister_cpts(struct gbe_priv *gbe_dev)
2714 {
2715         if (!gbe_dev->cpts || (gbe_dev->cpts_registered <= 0))
2716                 return;
2717
2718         if (--gbe_dev->cpts_registered)
2719                 return;
2720
2721         cpts_unregister(gbe_dev->cpts);
2722 }
2723 #else
2724 static inline int gbe_txtstamp_mark_pkt(struct gbe_intf *gbe_intf,
2725                                         struct netcp_packet *p_info)
2726 {
2727         return 0;
2728 }
2729
2730 static inline int gbe_rxtstamp(struct gbe_intf *gbe_intf,
2731                                struct netcp_packet *p_info)
2732 {
2733         return 0;
2734 }
2735
2736 static inline int gbe_hwtstamp(struct gbe_intf *gbe_intf,
2737                                struct ifreq *ifr, int cmd)
2738 {
2739         return -EOPNOTSUPP;
2740 }
2741
2742 static inline void gbe_register_cpts(struct gbe_priv *gbe_dev)
2743 {
2744 }
2745
2746 static inline void gbe_unregister_cpts(struct gbe_priv *gbe_dev)
2747 {
2748 }
2749
2750 static inline int gbe_hwtstamp_get(struct gbe_intf *gbe_intf, struct ifreq *req)
2751 {
2752         return -EOPNOTSUPP;
2753 }
2754
2755 static inline int gbe_hwtstamp_set(struct gbe_intf *gbe_intf, struct ifreq *req)
2756 {
2757         return -EOPNOTSUPP;
2758 }
2759 #endif /* CONFIG_TI_CPTS */
2760
2761 static int gbe_ioctl(void *intf_priv, struct ifreq *req, int cmd)
2762 {
2763         struct gbe_intf *gbe_intf = intf_priv;
2764         struct phy_device *phy = gbe_intf->slave->phy;
2765
2766         if (!phy || !phy->drv->hwtstamp) {
2767                 switch (cmd) {
2768                 case SIOCGHWTSTAMP:
2769                         return gbe_hwtstamp_get(gbe_intf, req);
2770                 case SIOCSHWTSTAMP:
2771                         return gbe_hwtstamp_set(gbe_intf, req);
2772                 }
2773         }
2774
2775         if (phy)
2776                 return phy_mii_ioctl(phy, req, cmd);
2777
2778         return -EOPNOTSUPP;
2779 }
2780
2781 static void netcp_ethss_timer(struct timer_list *t)
2782 {
2783         struct gbe_priv *gbe_dev = from_timer(gbe_dev, t, timer);
2784         struct gbe_intf *gbe_intf;
2785         struct gbe_slave *slave;
2786
2787         /* Check & update SGMII link state of interfaces */
2788         for_each_intf(gbe_intf, gbe_dev) {
2789                 if (!gbe_intf->slave->open)
2790                         continue;
2791                 netcp_ethss_update_link_state(gbe_dev, gbe_intf->slave,
2792                                               gbe_intf->ndev);
2793         }
2794
2795         /* Check & update SGMII link state of secondary ports */
2796         for_each_sec_slave(slave, gbe_dev) {
2797                 netcp_ethss_update_link_state(gbe_dev, slave, NULL);
2798         }
2799
2800         /* A timer runs as a BH, no need to block them */
2801         spin_lock(&gbe_dev->hw_stats_lock);
2802
2803         if (IS_SS_ID_VER_14(gbe_dev))
2804                 gbe_update_stats_ver14(gbe_dev, NULL);
2805         else
2806                 gbe_update_stats(gbe_dev, NULL);
2807
2808         spin_unlock(&gbe_dev->hw_stats_lock);
2809
2810         gbe_dev->timer.expires  = jiffies + GBE_TIMER_INTERVAL;
2811         add_timer(&gbe_dev->timer);
2812 }
2813
2814 static int gbe_txhook(int order, void *data, struct netcp_packet *p_info)
2815 {
2816         struct gbe_intf *gbe_intf = data;
2817
2818         p_info->tx_pipe = &gbe_intf->tx_pipe;
2819
2820         return gbe_txtstamp_mark_pkt(gbe_intf, p_info);
2821 }
2822
2823 static int gbe_rxhook(int order, void *data, struct netcp_packet *p_info)
2824 {
2825         struct gbe_intf *gbe_intf = data;
2826
2827         return gbe_rxtstamp(gbe_intf, p_info);
2828 }
2829
2830 static int gbe_open(void *intf_priv, struct net_device *ndev)
2831 {
2832         struct gbe_intf *gbe_intf = intf_priv;
2833         struct gbe_priv *gbe_dev = gbe_intf->gbe_dev;
2834         struct netcp_intf *netcp = netdev_priv(ndev);
2835         struct gbe_slave *slave = gbe_intf->slave;
2836         int port_num = slave->port_num;
2837         u32 reg, val;
2838         int ret;
2839
2840         reg = readl(GBE_REG_ADDR(gbe_dev, switch_regs, id_ver));
2841         dev_dbg(gbe_dev->dev, "initializing gbe version %d.%d (%d) GBE identification value 0x%x\n",
2842                 GBE_MAJOR_VERSION(reg), GBE_MINOR_VERSION(reg),
2843                 GBE_RTL_VERSION(reg), GBE_IDENT(reg));
2844
2845         /* For 10G and on NetCP 1.5, use directed to port */
2846         if (IS_SS_ID_XGBE(gbe_dev) || IS_SS_ID_MU(gbe_dev))
2847                 gbe_intf->tx_pipe.flags = SWITCH_TO_PORT_IN_TAGINFO;
2848
2849         if (gbe_dev->enable_ale)
2850                 gbe_intf->tx_pipe.switch_to_port = 0;
2851         else
2852                 gbe_intf->tx_pipe.switch_to_port = port_num;
2853
2854         dev_dbg(gbe_dev->dev,
2855                 "opened TX channel %s: %p with to port %d, flags %d\n",
2856                 gbe_intf->tx_pipe.dma_chan_name,
2857                 gbe_intf->tx_pipe.dma_channel,
2858                 gbe_intf->tx_pipe.switch_to_port,
2859                 gbe_intf->tx_pipe.flags);
2860
2861         gbe_slave_stop(gbe_intf);
2862
2863         /* disable priority elevation and enable statistics on all ports */
2864         writel(0, GBE_REG_ADDR(gbe_dev, switch_regs, ptype));
2865
2866         /* Control register */
2867         val = GBE_CTL_P0_ENABLE;
2868         if (IS_SS_ID_MU(gbe_dev)) {
2869                 val |= ETH_SW_CTL_P0_TX_CRC_REMOVE;
2870                 netcp->hw_cap = ETH_SW_CAN_REMOVE_ETH_FCS;
2871         }
2872         writel(val, GBE_REG_ADDR(gbe_dev, switch_regs, control));
2873
2874         /* All statistics enabled and STAT AB visible by default */
2875         writel(gbe_dev->stats_en_mask, GBE_REG_ADDR(gbe_dev, switch_regs,
2876                                                     stat_port_en));
2877
2878         ret = gbe_slave_open(gbe_intf);
2879         if (ret)
2880                 goto fail;
2881
2882         netcp_register_txhook(netcp, GBE_TXHOOK_ORDER, gbe_txhook, gbe_intf);
2883         netcp_register_rxhook(netcp, GBE_RXHOOK_ORDER, gbe_rxhook, gbe_intf);
2884
2885         slave->open = true;
2886         netcp_ethss_update_link_state(gbe_dev, slave, ndev);
2887
2888         gbe_register_cpts(gbe_dev);
2889
2890         return 0;
2891
2892 fail:
2893         gbe_slave_stop(gbe_intf);
2894         return ret;
2895 }
2896
2897 static int gbe_close(void *intf_priv, struct net_device *ndev)
2898 {
2899         struct gbe_intf *gbe_intf = intf_priv;
2900         struct netcp_intf *netcp = netdev_priv(ndev);
2901         struct gbe_priv *gbe_dev = gbe_intf->gbe_dev;
2902
2903         gbe_unregister_cpts(gbe_dev);
2904
2905         gbe_slave_stop(gbe_intf);
2906
2907         netcp_unregister_rxhook(netcp, GBE_RXHOOK_ORDER, gbe_rxhook, gbe_intf);
2908         netcp_unregister_txhook(netcp, GBE_TXHOOK_ORDER, gbe_txhook, gbe_intf);
2909
2910         gbe_intf->slave->open = false;
2911         atomic_set(&gbe_intf->slave->link_state, NETCP_LINK_STATE_INVALID);
2912         return 0;
2913 }
2914
2915 #if IS_ENABLED(CONFIG_TI_CPTS)
2916 static void init_slave_ts_ctl(struct gbe_slave *slave)
2917 {
2918         slave->ts_ctl.uni = 1;
2919         slave->ts_ctl.dst_port_map =
2920                 (TS_CTL_DST_PORT >> TS_CTL_DST_PORT_SHIFT) & 0x3;
2921         slave->ts_ctl.maddr_map =
2922                 (TS_CTL_MADDR_ALL >> TS_CTL_MADDR_SHIFT) & 0x1f;
2923 }
2924
2925 #else
2926 static void init_slave_ts_ctl(struct gbe_slave *slave)
2927 {
2928 }
2929 #endif /* CONFIG_TI_CPTS */
2930
2931 static int init_slave(struct gbe_priv *gbe_dev, struct gbe_slave *slave,
2932                       struct device_node *node)
2933 {
2934         int port_reg_num;
2935         u32 port_reg_ofs, emac_reg_ofs;
2936         u32 port_reg_blk_sz, emac_reg_blk_sz;
2937
2938         if (of_property_read_u32(node, "slave-port", &slave->slave_num)) {
2939                 dev_err(gbe_dev->dev, "missing slave-port parameter\n");
2940                 return -EINVAL;
2941         }
2942
2943         if (of_property_read_u32(node, "link-interface",
2944                                  &slave->link_interface)) {
2945                 dev_warn(gbe_dev->dev,
2946                          "missing link-interface value defaulting to 1G mac-phy link\n");
2947                 slave->link_interface = SGMII_LINK_MAC_PHY;
2948         }
2949
2950         slave->open = false;
2951         if ((slave->link_interface == SGMII_LINK_MAC_PHY) ||
2952             (slave->link_interface == RGMII_LINK_MAC_PHY) ||
2953             (slave->link_interface == XGMII_LINK_MAC_PHY))
2954                 slave->phy_node = of_parse_phandle(node, "phy-handle", 0);
2955         slave->port_num = gbe_get_slave_port(gbe_dev, slave->slave_num);
2956
2957         if (slave->link_interface >= XGMII_LINK_MAC_PHY)
2958                 slave->mac_control = GBE_DEF_10G_MAC_CONTROL;
2959         else
2960                 slave->mac_control = GBE_DEF_1G_MAC_CONTROL;
2961
2962         /* Emac regs memmap are contiguous but port regs are not */
2963         port_reg_num = slave->slave_num;
2964         if (IS_SS_ID_VER_14(gbe_dev)) {
2965                 if (slave->slave_num > 1) {
2966                         port_reg_ofs = GBE13_SLAVE_PORT2_OFFSET;
2967                         port_reg_num -= 2;
2968                 } else {
2969                         port_reg_ofs = GBE13_SLAVE_PORT_OFFSET;
2970                 }
2971                 emac_reg_ofs = GBE13_EMAC_OFFSET;
2972                 port_reg_blk_sz = 0x30;
2973                 emac_reg_blk_sz = 0x40;
2974         } else if (IS_SS_ID_MU(gbe_dev)) {
2975                 port_reg_ofs = GBENU_SLAVE_PORT_OFFSET;
2976                 emac_reg_ofs = GBENU_EMAC_OFFSET;
2977                 port_reg_blk_sz = 0x1000;
2978                 emac_reg_blk_sz = 0x1000;
2979         } else if (IS_SS_ID_XGBE(gbe_dev)) {
2980                 port_reg_ofs = XGBE10_SLAVE_PORT_OFFSET;
2981                 emac_reg_ofs = XGBE10_EMAC_OFFSET;
2982                 port_reg_blk_sz = 0x30;
2983                 emac_reg_blk_sz = 0x40;
2984         } else {
2985                 dev_err(gbe_dev->dev, "unknown ethss(0x%x)\n",
2986                         gbe_dev->ss_version);
2987                 return -EINVAL;
2988         }
2989
2990         slave->port_regs = gbe_dev->switch_regs + port_reg_ofs +
2991                                 (port_reg_blk_sz * port_reg_num);
2992         slave->emac_regs = gbe_dev->switch_regs + emac_reg_ofs +
2993                                 (emac_reg_blk_sz * slave->slave_num);
2994
2995         if (IS_SS_ID_VER_14(gbe_dev)) {
2996                 /* Initialize  slave port register offsets */
2997                 GBE_SET_REG_OFS(slave, port_regs, port_vlan);
2998                 GBE_SET_REG_OFS(slave, port_regs, tx_pri_map);
2999                 GBE_SET_REG_OFS(slave, port_regs, sa_lo);
3000                 GBE_SET_REG_OFS(slave, port_regs, sa_hi);
3001                 GBE_SET_REG_OFS(slave, port_regs, ts_ctl);
3002                 GBE_SET_REG_OFS(slave, port_regs, ts_seq_ltype);
3003                 GBE_SET_REG_OFS(slave, port_regs, ts_vlan);
3004                 GBE_SET_REG_OFS(slave, port_regs, ts_ctl_ltype2);
3005                 GBE_SET_REG_OFS(slave, port_regs, ts_ctl2);
3006
3007                 /* Initialize EMAC register offsets */
3008                 GBE_SET_REG_OFS(slave, emac_regs, mac_control);
3009                 GBE_SET_REG_OFS(slave, emac_regs, soft_reset);
3010                 GBE_SET_REG_OFS(slave, emac_regs, rx_maxlen);
3011
3012         } else if (IS_SS_ID_MU(gbe_dev)) {
3013                 /* Initialize  slave port register offsets */
3014                 GBENU_SET_REG_OFS(slave, port_regs, port_vlan);
3015                 GBENU_SET_REG_OFS(slave, port_regs, tx_pri_map);
3016                 GBENU_SET_REG_OFS(slave, port_regs, rx_pri_map);
3017                 GBENU_SET_REG_OFS(slave, port_regs, sa_lo);
3018                 GBENU_SET_REG_OFS(slave, port_regs, sa_hi);
3019                 GBENU_SET_REG_OFS(slave, port_regs, ts_ctl);
3020                 GBENU_SET_REG_OFS(slave, port_regs, ts_seq_ltype);
3021                 GBENU_SET_REG_OFS(slave, port_regs, ts_vlan);
3022                 GBENU_SET_REG_OFS(slave, port_regs, ts_ctl_ltype2);
3023                 GBENU_SET_REG_OFS(slave, port_regs, ts_ctl2);
3024                 GBENU_SET_REG_OFS(slave, port_regs, rx_maxlen);
3025
3026                 /* Initialize EMAC register offsets */
3027                 GBENU_SET_REG_OFS(slave, emac_regs, mac_control);
3028                 GBENU_SET_REG_OFS(slave, emac_regs, soft_reset);
3029
3030         } else if (IS_SS_ID_XGBE(gbe_dev)) {
3031                 /* Initialize  slave port register offsets */
3032                 XGBE_SET_REG_OFS(slave, port_regs, port_vlan);
3033                 XGBE_SET_REG_OFS(slave, port_regs, tx_pri_map);
3034                 XGBE_SET_REG_OFS(slave, port_regs, sa_lo);
3035                 XGBE_SET_REG_OFS(slave, port_regs, sa_hi);
3036                 XGBE_SET_REG_OFS(slave, port_regs, ts_ctl);
3037                 XGBE_SET_REG_OFS(slave, port_regs, ts_seq_ltype);
3038                 XGBE_SET_REG_OFS(slave, port_regs, ts_vlan);
3039                 XGBE_SET_REG_OFS(slave, port_regs, ts_ctl_ltype2);
3040                 XGBE_SET_REG_OFS(slave, port_regs, ts_ctl2);
3041
3042                 /* Initialize EMAC register offsets */
3043                 XGBE_SET_REG_OFS(slave, emac_regs, mac_control);
3044                 XGBE_SET_REG_OFS(slave, emac_regs, soft_reset);
3045                 XGBE_SET_REG_OFS(slave, emac_regs, rx_maxlen);
3046         }
3047
3048         atomic_set(&slave->link_state, NETCP_LINK_STATE_INVALID);
3049
3050         init_slave_ts_ctl(slave);
3051         return 0;
3052 }
3053
3054 static void init_secondary_ports(struct gbe_priv *gbe_dev,
3055                                  struct device_node *node)
3056 {
3057         struct device *dev = gbe_dev->dev;
3058         phy_interface_t phy_mode;
3059         struct gbe_priv **priv;
3060         struct device_node *port;
3061         struct gbe_slave *slave;
3062         bool mac_phy_link = false;
3063
3064         for_each_child_of_node(node, port) {
3065                 slave = devm_kzalloc(dev, sizeof(*slave), GFP_KERNEL);
3066                 if (!slave) {
3067                         dev_err(dev, "memory alloc failed for secondary port(%s), skipping...\n",
3068                                 port->name);
3069                         continue;
3070                 }
3071
3072                 if (init_slave(gbe_dev, slave, port)) {
3073                         dev_err(dev,
3074                                 "Failed to initialize secondary port(%s), skipping...\n",
3075                                 port->name);
3076                         devm_kfree(dev, slave);
3077                         continue;
3078                 }
3079
3080                 if (!IS_SS_ID_2U(gbe_dev))
3081                         gbe_sgmii_config(gbe_dev, slave);
3082                 gbe_port_reset(slave);
3083                 gbe_port_config(gbe_dev, slave, gbe_dev->rx_packet_max);
3084                 list_add_tail(&slave->slave_list, &gbe_dev->secondary_slaves);
3085                 gbe_dev->num_slaves++;
3086                 if ((slave->link_interface == SGMII_LINK_MAC_PHY) ||
3087                     (slave->link_interface == XGMII_LINK_MAC_PHY))
3088                         mac_phy_link = true;
3089
3090                 slave->open = true;
3091                 if (gbe_dev->num_slaves >= gbe_dev->max_num_slaves) {
3092                         of_node_put(port);
3093                         break;
3094                 }
3095         }
3096
3097         /* of_phy_connect() is needed only for MAC-PHY interface */
3098         if (!mac_phy_link)
3099                 return;
3100
3101         /* Allocate dummy netdev device for attaching to phy device */
3102         gbe_dev->dummy_ndev = alloc_netdev(sizeof(gbe_dev), "dummy",
3103                                         NET_NAME_UNKNOWN, ether_setup);
3104         if (!gbe_dev->dummy_ndev) {
3105                 dev_err(dev,
3106                         "Failed to allocate dummy netdev for secondary ports, skipping phy_connect()...\n");
3107                 return;
3108         }
3109         priv = netdev_priv(gbe_dev->dummy_ndev);
3110         *priv = gbe_dev;
3111
3112         if (slave->link_interface == SGMII_LINK_MAC_PHY) {
3113                 phy_mode = PHY_INTERFACE_MODE_SGMII;
3114                 slave->phy_port_t = PORT_MII;
3115         } else if (slave->link_interface == RGMII_LINK_MAC_PHY) {
3116                 phy_mode = PHY_INTERFACE_MODE_RGMII;
3117                 slave->phy_port_t = PORT_MII;
3118         } else {
3119                 phy_mode = PHY_INTERFACE_MODE_NA;
3120                 slave->phy_port_t = PORT_FIBRE;
3121         }
3122
3123         for_each_sec_slave(slave, gbe_dev) {
3124                 if ((slave->link_interface != SGMII_LINK_MAC_PHY) &&
3125                     (slave->link_interface != RGMII_LINK_MAC_PHY) &&
3126                     (slave->link_interface != XGMII_LINK_MAC_PHY))
3127                         continue;
3128                 slave->phy =
3129                         of_phy_connect(gbe_dev->dummy_ndev,
3130                                        slave->phy_node,
3131                                        gbe_adjust_link_sec_slaves,
3132                                        0, phy_mode);
3133                 if (!slave->phy) {
3134                         dev_err(dev, "phy not found for slave %d\n",
3135                                 slave->slave_num);
3136                         slave->phy = NULL;
3137                 } else {
3138                         dev_dbg(dev, "phy found: id is: 0x%s\n",
3139                                 phydev_name(slave->phy));
3140                         phy_start(slave->phy);
3141                 }
3142         }
3143 }
3144
3145 static void free_secondary_ports(struct gbe_priv *gbe_dev)
3146 {
3147         struct gbe_slave *slave;
3148
3149         while (!list_empty(&gbe_dev->secondary_slaves)) {
3150                 slave = first_sec_slave(gbe_dev);
3151
3152                 if (slave->phy)
3153                         phy_disconnect(slave->phy);
3154                 list_del(&slave->slave_list);
3155         }
3156         if (gbe_dev->dummy_ndev)
3157                 free_netdev(gbe_dev->dummy_ndev);
3158 }
3159
3160 static int set_xgbe_ethss10_priv(struct gbe_priv *gbe_dev,
3161                                  struct device_node *node)
3162 {
3163         struct resource res;
3164         void __iomem *regs;
3165         int ret, i;
3166
3167         ret = of_address_to_resource(node, XGBE_SS_REG_INDEX, &res);
3168         if (ret) {
3169                 dev_err(gbe_dev->dev,
3170                         "Can't xlate xgbe of node(%s) ss address at %d\n",
3171                         node->name, XGBE_SS_REG_INDEX);
3172                 return ret;
3173         }
3174
3175         regs = devm_ioremap_resource(gbe_dev->dev, &res);
3176         if (IS_ERR(regs)) {
3177                 dev_err(gbe_dev->dev, "Failed to map xgbe ss register base\n");
3178                 return PTR_ERR(regs);
3179         }
3180         gbe_dev->ss_regs = regs;
3181
3182         ret = of_address_to_resource(node, XGBE_SM_REG_INDEX, &res);
3183         if (ret) {
3184                 dev_err(gbe_dev->dev,
3185                         "Can't xlate xgbe of node(%s) sm address at %d\n",
3186                         node->name, XGBE_SM_REG_INDEX);
3187                 return ret;
3188         }
3189
3190         regs = devm_ioremap_resource(gbe_dev->dev, &res);
3191         if (IS_ERR(regs)) {
3192                 dev_err(gbe_dev->dev, "Failed to map xgbe sm register base\n");
3193                 return PTR_ERR(regs);
3194         }
3195         gbe_dev->switch_regs = regs;
3196
3197         ret = of_address_to_resource(node, XGBE_SERDES_REG_INDEX, &res);
3198         if (ret) {
3199                 dev_err(gbe_dev->dev,
3200                         "Can't xlate xgbe serdes of node(%s) address at %d\n",
3201                         node->name, XGBE_SERDES_REG_INDEX);
3202                 return ret;
3203         }
3204
3205         regs = devm_ioremap_resource(gbe_dev->dev, &res);
3206         if (IS_ERR(regs)) {
3207                 dev_err(gbe_dev->dev, "Failed to map xgbe serdes register base\n");
3208                 return PTR_ERR(regs);
3209         }
3210         gbe_dev->xgbe_serdes_regs = regs;
3211
3212         gbe_dev->num_stats_mods = gbe_dev->max_num_ports;
3213         gbe_dev->et_stats = xgbe10_et_stats;
3214         gbe_dev->num_et_stats = ARRAY_SIZE(xgbe10_et_stats);
3215
3216         gbe_dev->hw_stats = devm_kzalloc(gbe_dev->dev,
3217                                          gbe_dev->num_et_stats * sizeof(u64),
3218                                          GFP_KERNEL);
3219         if (!gbe_dev->hw_stats) {
3220                 dev_err(gbe_dev->dev, "hw_stats memory allocation failed\n");
3221                 return -ENOMEM;
3222         }
3223
3224         gbe_dev->hw_stats_prev =
3225                 devm_kzalloc(gbe_dev->dev,
3226                              gbe_dev->num_et_stats * sizeof(u32),
3227                              GFP_KERNEL);
3228         if (!gbe_dev->hw_stats_prev) {
3229                 dev_err(gbe_dev->dev,
3230                         "hw_stats_prev memory allocation failed\n");
3231                 return -ENOMEM;
3232         }
3233
3234         gbe_dev->ss_version = XGBE_SS_VERSION_10;
3235         gbe_dev->sgmii_port_regs = gbe_dev->ss_regs +
3236                                         XGBE10_SGMII_MODULE_OFFSET;
3237         gbe_dev->host_port_regs = gbe_dev->ss_regs + XGBE10_HOST_PORT_OFFSET;
3238
3239         for (i = 0; i < gbe_dev->max_num_ports; i++)
3240                 gbe_dev->hw_stats_regs[i] = gbe_dev->switch_regs +
3241                         XGBE10_HW_STATS_OFFSET + (GBE_HW_STATS_REG_MAP_SZ * i);
3242
3243         gbe_dev->ale_reg = gbe_dev->switch_regs + XGBE10_ALE_OFFSET;
3244         gbe_dev->cpts_reg = gbe_dev->switch_regs + XGBE10_CPTS_OFFSET;
3245         gbe_dev->ale_ports = gbe_dev->max_num_ports;
3246         gbe_dev->host_port = XGBE10_HOST_PORT_NUM;
3247         gbe_dev->ale_entries = XGBE10_NUM_ALE_ENTRIES;
3248         gbe_dev->stats_en_mask = (1 << (gbe_dev->max_num_ports)) - 1;
3249
3250         /* Subsystem registers */
3251         XGBE_SET_REG_OFS(gbe_dev, ss_regs, id_ver);
3252         XGBE_SET_REG_OFS(gbe_dev, ss_regs, control);
3253
3254         /* Switch module registers */
3255         XGBE_SET_REG_OFS(gbe_dev, switch_regs, id_ver);
3256         XGBE_SET_REG_OFS(gbe_dev, switch_regs, control);
3257         XGBE_SET_REG_OFS(gbe_dev, switch_regs, ptype);
3258         XGBE_SET_REG_OFS(gbe_dev, switch_regs, stat_port_en);
3259         XGBE_SET_REG_OFS(gbe_dev, switch_regs, flow_control);
3260
3261         /* Host port registers */
3262         XGBE_SET_REG_OFS(gbe_dev, host_port_regs, port_vlan);
3263         XGBE_SET_REG_OFS(gbe_dev, host_port_regs, tx_pri_map);
3264         XGBE_SET_REG_OFS(gbe_dev, host_port_regs, rx_maxlen);
3265         return 0;
3266 }
3267
3268 static int get_gbe_resource_version(struct gbe_priv *gbe_dev,
3269                                     struct device_node *node)
3270 {
3271         struct resource res;
3272         void __iomem *regs;
3273         int ret;
3274
3275         ret = of_address_to_resource(node, GBE_SS_REG_INDEX, &res);
3276         if (ret) {
3277                 dev_err(gbe_dev->dev,
3278                         "Can't translate of node(%s) of gbe ss address at %d\n",
3279                         node->name, GBE_SS_REG_INDEX);
3280                 return ret;
3281         }
3282
3283         regs = devm_ioremap_resource(gbe_dev->dev, &res);
3284         if (IS_ERR(regs)) {
3285                 dev_err(gbe_dev->dev, "Failed to map gbe register base\n");
3286                 return PTR_ERR(regs);
3287         }
3288         gbe_dev->ss_regs = regs;
3289         gbe_dev->ss_version = readl(gbe_dev->ss_regs);
3290         return 0;
3291 }
3292
3293 static int set_gbe_ethss14_priv(struct gbe_priv *gbe_dev,
3294                                 struct device_node *node)
3295 {
3296         struct resource res;
3297         void __iomem *regs;
3298         int i, ret;
3299
3300         ret = of_address_to_resource(node, GBE_SGMII34_REG_INDEX, &res);
3301         if (ret) {
3302                 dev_err(gbe_dev->dev,
3303                         "Can't translate of gbe node(%s) address at index %d\n",
3304                         node->name, GBE_SGMII34_REG_INDEX);
3305                 return ret;
3306         }
3307
3308         regs = devm_ioremap_resource(gbe_dev->dev, &res);
3309         if (IS_ERR(regs)) {
3310                 dev_err(gbe_dev->dev,
3311                         "Failed to map gbe sgmii port34 register base\n");
3312                 return PTR_ERR(regs);
3313         }
3314         gbe_dev->sgmii_port34_regs = regs;
3315
3316         ret = of_address_to_resource(node, GBE_SM_REG_INDEX, &res);
3317         if (ret) {
3318                 dev_err(gbe_dev->dev,
3319                         "Can't translate of gbe node(%s) address at index %d\n",
3320                         node->name, GBE_SM_REG_INDEX);
3321                 return ret;
3322         }
3323
3324         regs = devm_ioremap_resource(gbe_dev->dev, &res);
3325         if (IS_ERR(regs)) {
3326                 dev_err(gbe_dev->dev,
3327                         "Failed to map gbe switch module register base\n");
3328                 return PTR_ERR(regs);
3329         }
3330         gbe_dev->switch_regs = regs;
3331
3332         gbe_dev->num_stats_mods = gbe_dev->max_num_slaves;
3333         gbe_dev->et_stats = gbe13_et_stats;
3334         gbe_dev->num_et_stats = ARRAY_SIZE(gbe13_et_stats);
3335
3336         gbe_dev->hw_stats = devm_kzalloc(gbe_dev->dev,
3337                                          gbe_dev->num_et_stats * sizeof(u64),
3338                                          GFP_KERNEL);
3339         if (!gbe_dev->hw_stats) {
3340                 dev_err(gbe_dev->dev, "hw_stats memory allocation failed\n");
3341                 return -ENOMEM;
3342         }
3343
3344         gbe_dev->hw_stats_prev =
3345                 devm_kzalloc(gbe_dev->dev,
3346                              gbe_dev->num_et_stats * sizeof(u32),
3347                              GFP_KERNEL);
3348         if (!gbe_dev->hw_stats_prev) {
3349                 dev_err(gbe_dev->dev,
3350                         "hw_stats_prev memory allocation failed\n");
3351                 return -ENOMEM;
3352         }
3353
3354         gbe_dev->sgmii_port_regs = gbe_dev->ss_regs + GBE13_SGMII_MODULE_OFFSET;
3355         gbe_dev->host_port_regs = gbe_dev->switch_regs + GBE13_HOST_PORT_OFFSET;
3356
3357         /* K2HK has only 2 hw stats modules visible at a time, so
3358          * module 0 & 2 points to one base and
3359          * module 1 & 3 points to the other base
3360          */
3361         for (i = 0; i < gbe_dev->max_num_slaves; i++) {
3362                 gbe_dev->hw_stats_regs[i] =
3363                         gbe_dev->switch_regs + GBE13_HW_STATS_OFFSET +
3364                         (GBE_HW_STATS_REG_MAP_SZ * (i & 0x1));
3365         }
3366
3367         gbe_dev->cpts_reg = gbe_dev->switch_regs + GBE13_CPTS_OFFSET;
3368         gbe_dev->ale_reg = gbe_dev->switch_regs + GBE13_ALE_OFFSET;
3369         gbe_dev->ale_ports = gbe_dev->max_num_ports;
3370         gbe_dev->host_port = GBE13_HOST_PORT_NUM;
3371         gbe_dev->ale_entries = GBE13_NUM_ALE_ENTRIES;
3372         gbe_dev->stats_en_mask = GBE13_REG_VAL_STAT_ENABLE_ALL;
3373
3374         /* Subsystem registers */
3375         GBE_SET_REG_OFS(gbe_dev, ss_regs, id_ver);
3376
3377         /* Switch module registers */
3378         GBE_SET_REG_OFS(gbe_dev, switch_regs, id_ver);
3379         GBE_SET_REG_OFS(gbe_dev, switch_regs, control);
3380         GBE_SET_REG_OFS(gbe_dev, switch_regs, soft_reset);
3381         GBE_SET_REG_OFS(gbe_dev, switch_regs, stat_port_en);
3382         GBE_SET_REG_OFS(gbe_dev, switch_regs, ptype);
3383         GBE_SET_REG_OFS(gbe_dev, switch_regs, flow_control);
3384
3385         /* Host port registers */
3386         GBE_SET_REG_OFS(gbe_dev, host_port_regs, port_vlan);
3387         GBE_SET_REG_OFS(gbe_dev, host_port_regs, rx_maxlen);
3388         return 0;
3389 }
3390
3391 static int set_gbenu_ethss_priv(struct gbe_priv *gbe_dev,
3392                                 struct device_node *node)
3393 {
3394         struct resource res;
3395         void __iomem *regs;
3396         int i, ret;
3397
3398         gbe_dev->num_stats_mods = gbe_dev->max_num_ports;
3399         gbe_dev->et_stats = gbenu_et_stats;
3400
3401         if (IS_SS_ID_NU(gbe_dev))
3402                 gbe_dev->num_et_stats = GBENU_ET_STATS_HOST_SIZE +
3403                         (gbe_dev->max_num_slaves * GBENU_ET_STATS_PORT_SIZE);
3404         else
3405                 gbe_dev->num_et_stats = GBENU_ET_STATS_HOST_SIZE +
3406                                         GBENU_ET_STATS_PORT_SIZE;
3407
3408         gbe_dev->hw_stats = devm_kzalloc(gbe_dev->dev,
3409                                          gbe_dev->num_et_stats * sizeof(u64),
3410                                          GFP_KERNEL);
3411         if (!gbe_dev->hw_stats) {
3412                 dev_err(gbe_dev->dev, "hw_stats memory allocation failed\n");
3413                 return -ENOMEM;
3414         }
3415
3416         gbe_dev->hw_stats_prev =
3417                 devm_kzalloc(gbe_dev->dev,
3418                              gbe_dev->num_et_stats * sizeof(u32),
3419                              GFP_KERNEL);
3420         if (!gbe_dev->hw_stats_prev) {
3421                 dev_err(gbe_dev->dev,
3422                         "hw_stats_prev memory allocation failed\n");
3423                 return -ENOMEM;
3424         }
3425
3426         ret = of_address_to_resource(node, GBENU_SM_REG_INDEX, &res);
3427         if (ret) {
3428                 dev_err(gbe_dev->dev,
3429                         "Can't translate of gbenu node(%s) addr at index %d\n",
3430                         node->name, GBENU_SM_REG_INDEX);
3431                 return ret;
3432         }
3433
3434         regs = devm_ioremap_resource(gbe_dev->dev, &res);
3435         if (IS_ERR(regs)) {
3436                 dev_err(gbe_dev->dev,
3437                         "Failed to map gbenu switch module register base\n");
3438                 return PTR_ERR(regs);
3439         }
3440         gbe_dev->switch_regs = regs;
3441
3442         if (!IS_SS_ID_2U(gbe_dev))
3443                 gbe_dev->sgmii_port_regs =
3444                        gbe_dev->ss_regs + GBENU_SGMII_MODULE_OFFSET;
3445
3446         /* Although sgmii modules are mem mapped to one contiguous
3447          * region on GBENU devices, setting sgmii_port34_regs allows
3448          * consistent code when accessing sgmii api
3449          */
3450         gbe_dev->sgmii_port34_regs = gbe_dev->sgmii_port_regs +
3451                                      (2 * GBENU_SGMII_MODULE_SIZE);
3452
3453         gbe_dev->host_port_regs = gbe_dev->switch_regs + GBENU_HOST_PORT_OFFSET;
3454
3455         for (i = 0; i < (gbe_dev->max_num_ports); i++)
3456                 gbe_dev->hw_stats_regs[i] = gbe_dev->switch_regs +
3457                         GBENU_HW_STATS_OFFSET + (GBENU_HW_STATS_REG_MAP_SZ * i);
3458
3459         gbe_dev->cpts_reg = gbe_dev->switch_regs + GBENU_CPTS_OFFSET;
3460         gbe_dev->ale_reg = gbe_dev->switch_regs + GBENU_ALE_OFFSET;
3461         gbe_dev->ale_ports = gbe_dev->max_num_ports;
3462         gbe_dev->host_port = GBENU_HOST_PORT_NUM;
3463         gbe_dev->stats_en_mask = (1 << (gbe_dev->max_num_ports)) - 1;
3464
3465         /* Subsystem registers */
3466         GBENU_SET_REG_OFS(gbe_dev, ss_regs, id_ver);
3467         /* ok to set for MU, but used by 2U only */
3468         GBENU_SET_REG_OFS(gbe_dev, ss_regs, rgmii_status);
3469
3470         /* Switch module registers */
3471         GBENU_SET_REG_OFS(gbe_dev, switch_regs, id_ver);
3472         GBENU_SET_REG_OFS(gbe_dev, switch_regs, control);
3473         GBENU_SET_REG_OFS(gbe_dev, switch_regs, stat_port_en);
3474         GBENU_SET_REG_OFS(gbe_dev, switch_regs, ptype);
3475
3476         /* Host port registers */
3477         GBENU_SET_REG_OFS(gbe_dev, host_port_regs, port_vlan);
3478         GBENU_SET_REG_OFS(gbe_dev, host_port_regs, rx_maxlen);
3479
3480         /* For NU only.  2U does not need tx_pri_map.
3481          * NU cppi port 0 tx pkt streaming interface has (n-1)*8 egress threads
3482          * while 2U has only 1 such thread
3483          */
3484         GBENU_SET_REG_OFS(gbe_dev, host_port_regs, tx_pri_map);
3485         return 0;
3486 }
3487
3488 static int gbe_probe(struct netcp_device *netcp_device, struct device *dev,
3489                      struct device_node *node, void **inst_priv)
3490 {
3491         struct device_node *interfaces, *interface;
3492         struct device_node *secondary_ports;
3493         struct cpsw_ale_params ale_params;
3494         struct gbe_priv *gbe_dev;
3495         u32 slave_num;
3496         int i, ret = 0;
3497
3498         if (!node) {
3499                 dev_err(dev, "device tree info unavailable\n");
3500                 return -ENODEV;
3501         }
3502
3503         gbe_dev = devm_kzalloc(dev, sizeof(struct gbe_priv), GFP_KERNEL);
3504         if (!gbe_dev)
3505                 return -ENOMEM;
3506
3507         if (of_device_is_compatible(node, "ti,netcp-gbe-5") ||
3508             of_device_is_compatible(node, "ti,netcp-gbe")) {
3509                 gbe_dev->max_num_slaves = 4;
3510         } else if (of_device_is_compatible(node, "ti,netcp-gbe-9")) {
3511                 gbe_dev->max_num_slaves = 8;
3512         } else if (of_device_is_compatible(node, "ti,netcp-gbe-2")) {
3513                 gbe_dev->max_num_slaves = 1;
3514         } else if (of_device_is_compatible(node, "ti,netcp-xgbe")) {
3515                 gbe_dev->max_num_slaves = 2;
3516         } else {
3517                 dev_err(dev, "device tree node for unknown device\n");
3518                 return -EINVAL;
3519         }
3520         gbe_dev->max_num_ports = gbe_dev->max_num_slaves + 1;
3521
3522         gbe_dev->dev = dev;
3523         gbe_dev->netcp_device = netcp_device;
3524         gbe_dev->rx_packet_max = NETCP_MAX_FRAME_SIZE;
3525
3526         /* init the hw stats lock */
3527         spin_lock_init(&gbe_dev->hw_stats_lock);
3528
3529         if (of_find_property(node, "enable-ale", NULL)) {
3530                 gbe_dev->enable_ale = true;
3531                 dev_info(dev, "ALE enabled\n");
3532         } else {
3533                 gbe_dev->enable_ale = false;
3534                 dev_dbg(dev, "ALE bypass enabled*\n");
3535         }
3536
3537         ret = of_property_read_u32(node, "tx-queue",
3538                                    &gbe_dev->tx_queue_id);
3539         if (ret < 0) {
3540                 dev_err(dev, "missing tx_queue parameter\n");
3541                 gbe_dev->tx_queue_id = GBE_TX_QUEUE;
3542         }
3543
3544         ret = of_property_read_string(node, "tx-channel",
3545                                       &gbe_dev->dma_chan_name);
3546         if (ret < 0) {
3547                 dev_err(dev, "missing \"tx-channel\" parameter\n");
3548                 return -EINVAL;
3549         }
3550
3551         if (!strcmp(node->name, "gbe")) {
3552                 ret = get_gbe_resource_version(gbe_dev, node);
3553                 if (ret)
3554                         return ret;
3555
3556                 dev_dbg(dev, "ss_version: 0x%08x\n", gbe_dev->ss_version);
3557
3558                 if (IS_SS_ID_VER_14(gbe_dev))
3559                         ret = set_gbe_ethss14_priv(gbe_dev, node);
3560                 else if (IS_SS_ID_MU(gbe_dev))
3561                         ret = set_gbenu_ethss_priv(gbe_dev, node);
3562                 else
3563                         ret = -ENODEV;
3564
3565         } else if (!strcmp(node->name, "xgbe")) {
3566                 ret = set_xgbe_ethss10_priv(gbe_dev, node);
3567                 if (ret)
3568                         return ret;
3569                 ret = netcp_xgbe_serdes_init(gbe_dev->xgbe_serdes_regs,
3570                                              gbe_dev->ss_regs);
3571         } else {
3572                 dev_err(dev, "unknown GBE node(%s)\n", node->name);
3573                 ret = -ENODEV;
3574         }
3575
3576         if (ret)
3577                 return ret;
3578
3579         interfaces = of_get_child_by_name(node, "interfaces");
3580         if (!interfaces)
3581                 dev_err(dev, "could not find interfaces\n");
3582
3583         ret = netcp_txpipe_init(&gbe_dev->tx_pipe, netcp_device,
3584                                 gbe_dev->dma_chan_name, gbe_dev->tx_queue_id);
3585         if (ret)
3586                 return ret;
3587
3588         ret = netcp_txpipe_open(&gbe_dev->tx_pipe);
3589         if (ret)
3590                 return ret;
3591
3592         /* Create network interfaces */
3593         INIT_LIST_HEAD(&gbe_dev->gbe_intf_head);
3594         for_each_child_of_node(interfaces, interface) {
3595                 ret = of_property_read_u32(interface, "slave-port", &slave_num);
3596                 if (ret) {
3597                         dev_err(dev, "missing slave-port parameter, skipping interface configuration for %s\n",
3598                                 interface->name);
3599                         continue;
3600                 }
3601                 gbe_dev->num_slaves++;
3602                 if (gbe_dev->num_slaves >= gbe_dev->max_num_slaves) {
3603                         of_node_put(interface);
3604                         break;
3605                 }
3606         }
3607         of_node_put(interfaces);
3608
3609         if (!gbe_dev->num_slaves)
3610                 dev_warn(dev, "No network interface configured\n");
3611
3612         /* Initialize Secondary slave ports */
3613         secondary_ports = of_get_child_by_name(node, "secondary-slave-ports");
3614         INIT_LIST_HEAD(&gbe_dev->secondary_slaves);
3615         if (secondary_ports && (gbe_dev->num_slaves <  gbe_dev->max_num_slaves))
3616                 init_secondary_ports(gbe_dev, secondary_ports);
3617         of_node_put(secondary_ports);
3618
3619         if (!gbe_dev->num_slaves) {
3620                 dev_err(dev,
3621                         "No network interface or secondary ports configured\n");
3622                 ret = -ENODEV;
3623                 goto free_sec_ports;
3624         }
3625
3626         memset(&ale_params, 0, sizeof(ale_params));
3627         ale_params.dev          = gbe_dev->dev;
3628         ale_params.ale_regs     = gbe_dev->ale_reg;
3629         ale_params.ale_ageout   = GBE_DEFAULT_ALE_AGEOUT;
3630         ale_params.ale_entries  = gbe_dev->ale_entries;
3631         ale_params.ale_ports    = gbe_dev->ale_ports;
3632         if (IS_SS_ID_MU(gbe_dev)) {
3633                 ale_params.major_ver_mask = 0x7;
3634                 ale_params.nu_switch_ale = true;
3635         }
3636         gbe_dev->ale = cpsw_ale_create(&ale_params);
3637         if (!gbe_dev->ale) {
3638                 dev_err(gbe_dev->dev, "error initializing ale engine\n");
3639                 ret = -ENODEV;
3640                 goto free_sec_ports;
3641         } else {
3642                 dev_dbg(gbe_dev->dev, "Created a gbe ale engine\n");
3643         }
3644
3645         gbe_dev->cpts = cpts_create(gbe_dev->dev, gbe_dev->cpts_reg, node);
3646         if (IS_ENABLED(CONFIG_TI_CPTS) && IS_ERR(gbe_dev->cpts)) {
3647                 ret = PTR_ERR(gbe_dev->cpts);
3648                 goto free_sec_ports;
3649         }
3650
3651         /* initialize host port */
3652         gbe_init_host_port(gbe_dev);
3653
3654         spin_lock_bh(&gbe_dev->hw_stats_lock);
3655         for (i = 0; i < gbe_dev->num_stats_mods; i++) {
3656                 if (IS_SS_ID_VER_14(gbe_dev))
3657                         gbe_reset_mod_stats_ver14(gbe_dev, i);
3658                 else
3659                         gbe_reset_mod_stats(gbe_dev, i);
3660         }
3661         spin_unlock_bh(&gbe_dev->hw_stats_lock);
3662
3663         timer_setup(&gbe_dev->timer, netcp_ethss_timer, 0);
3664         gbe_dev->timer.expires   = jiffies + GBE_TIMER_INTERVAL;
3665         add_timer(&gbe_dev->timer);
3666         *inst_priv = gbe_dev;
3667         return 0;
3668
3669 free_sec_ports:
3670         free_secondary_ports(gbe_dev);
3671         return ret;
3672 }
3673
3674 static int gbe_attach(void *inst_priv, struct net_device *ndev,
3675                       struct device_node *node, void **intf_priv)
3676 {
3677         struct gbe_priv *gbe_dev = inst_priv;
3678         struct gbe_intf *gbe_intf;
3679         int ret;
3680
3681         if (!node) {
3682                 dev_err(gbe_dev->dev, "interface node not available\n");
3683                 return -ENODEV;
3684         }
3685
3686         gbe_intf = devm_kzalloc(gbe_dev->dev, sizeof(*gbe_intf), GFP_KERNEL);
3687         if (!gbe_intf)
3688                 return -ENOMEM;
3689
3690         gbe_intf->ndev = ndev;
3691         gbe_intf->dev = gbe_dev->dev;
3692         gbe_intf->gbe_dev = gbe_dev;
3693
3694         gbe_intf->slave = devm_kzalloc(gbe_dev->dev,
3695                                         sizeof(*gbe_intf->slave),
3696                                         GFP_KERNEL);
3697         if (!gbe_intf->slave) {
3698                 ret = -ENOMEM;
3699                 goto fail;
3700         }
3701
3702         if (init_slave(gbe_dev, gbe_intf->slave, node)) {
3703                 ret = -ENODEV;
3704                 goto fail;
3705         }
3706
3707         gbe_intf->tx_pipe = gbe_dev->tx_pipe;
3708         ndev->ethtool_ops = &keystone_ethtool_ops;
3709         list_add_tail(&gbe_intf->gbe_intf_list, &gbe_dev->gbe_intf_head);
3710         *intf_priv = gbe_intf;
3711         return 0;
3712
3713 fail:
3714         if (gbe_intf->slave)
3715                 devm_kfree(gbe_dev->dev, gbe_intf->slave);
3716         if (gbe_intf)
3717                 devm_kfree(gbe_dev->dev, gbe_intf);
3718         return ret;
3719 }
3720
3721 static int gbe_release(void *intf_priv)
3722 {
3723         struct gbe_intf *gbe_intf = intf_priv;
3724
3725         gbe_intf->ndev->ethtool_ops = NULL;
3726         list_del(&gbe_intf->gbe_intf_list);
3727         devm_kfree(gbe_intf->dev, gbe_intf->slave);
3728         devm_kfree(gbe_intf->dev, gbe_intf);
3729         return 0;
3730 }
3731
3732 static int gbe_remove(struct netcp_device *netcp_device, void *inst_priv)
3733 {
3734         struct gbe_priv *gbe_dev = inst_priv;
3735
3736         del_timer_sync(&gbe_dev->timer);
3737         cpts_release(gbe_dev->cpts);
3738         cpsw_ale_stop(gbe_dev->ale);
3739         netcp_txpipe_close(&gbe_dev->tx_pipe);
3740         free_secondary_ports(gbe_dev);
3741
3742         if (!list_empty(&gbe_dev->gbe_intf_head))
3743                 dev_alert(gbe_dev->dev,
3744                           "unreleased ethss interfaces present\n");
3745
3746         return 0;
3747 }
3748
3749 static struct netcp_module gbe_module = {
3750         .name           = GBE_MODULE_NAME,
3751         .owner          = THIS_MODULE,
3752         .primary        = true,
3753         .probe          = gbe_probe,
3754         .open           = gbe_open,
3755         .close          = gbe_close,
3756         .remove         = gbe_remove,
3757         .attach         = gbe_attach,
3758         .release        = gbe_release,
3759         .add_addr       = gbe_add_addr,
3760         .del_addr       = gbe_del_addr,
3761         .add_vid        = gbe_add_vid,
3762         .del_vid        = gbe_del_vid,
3763         .ioctl          = gbe_ioctl,
3764 };
3765
3766 static struct netcp_module xgbe_module = {
3767         .name           = XGBE_MODULE_NAME,
3768         .owner          = THIS_MODULE,
3769         .primary        = true,
3770         .probe          = gbe_probe,
3771         .open           = gbe_open,
3772         .close          = gbe_close,
3773         .remove         = gbe_remove,
3774         .attach         = gbe_attach,
3775         .release        = gbe_release,
3776         .add_addr       = gbe_add_addr,
3777         .del_addr       = gbe_del_addr,
3778         .add_vid        = gbe_add_vid,
3779         .del_vid        = gbe_del_vid,
3780         .ioctl          = gbe_ioctl,
3781 };
3782
3783 static int __init keystone_gbe_init(void)
3784 {
3785         int ret;
3786
3787         ret = netcp_register_module(&gbe_module);
3788         if (ret)
3789                 return ret;
3790
3791         ret = netcp_register_module(&xgbe_module);
3792         if (ret)
3793                 return ret;
3794
3795         return 0;
3796 }
3797 module_init(keystone_gbe_init);
3798
3799 static void __exit keystone_gbe_exit(void)
3800 {
3801         netcp_unregister_module(&gbe_module);
3802         netcp_unregister_module(&xgbe_module);
3803 }
3804 module_exit(keystone_gbe_exit);
3805
3806 MODULE_LICENSE("GPL v2");
3807 MODULE_DESCRIPTION("TI NETCP ETHSS driver for Keystone SOCs");
3808 MODULE_AUTHOR("Sandeep Nair <sandeep_n@ti.com");