2 * Driver for Xilinx TEMAC Ethernet device
4 * Copyright (c) 2008 Nissin Systems Co., Ltd., Yoshio Kashiwagi
5 * Copyright (c) 2005-2008 DLA Systems, David H. Lynch Jr. <dhlii@dlasys.net>
6 * Copyright (c) 2008-2009 Secret Lab Technologies Ltd.
8 * This is a driver for the Xilinx ll_temac ipcore which is often used
9 * in the Virtex and Spartan series of chips.
12 * - The ll_temac hardware uses indirect access for many of the TEMAC
13 * registers, include the MDIO bus. However, indirect access to MDIO
14 * registers take considerably more clock cycles than to TEMAC registers.
15 * MDIO accesses are long, so threads doing them should probably sleep
16 * rather than busywait. However, since only one indirect access can be
17 * in progress at any given time, that means that *all* indirect accesses
18 * could end up sleeping (to wait for an MDIO access to complete).
19 * Fortunately none of the indirect accesses are on the 'hot' path for tx
20 * or rx, so this should be okay.
23 * - Factor out locallink DMA code into separate driver
24 * - Fix multicast assignment.
25 * - Fix support for hardware checksumming.
26 * - Testing. Lots and lots of testing.
30 #include <linux/delay.h>
31 #include <linux/etherdevice.h>
32 #include <linux/mii.h>
33 #include <linux/module.h>
34 #include <linux/mutex.h>
35 #include <linux/netdevice.h>
37 #include <linux/of_device.h>
38 #include <linux/of_irq.h>
39 #include <linux/of_mdio.h>
40 #include <linux/of_net.h>
41 #include <linux/of_platform.h>
42 #include <linux/of_address.h>
43 #include <linux/skbuff.h>
44 #include <linux/spinlock.h>
45 #include <linux/tcp.h> /* needed for sizeof(tcphdr) */
46 #include <linux/udp.h> /* needed for sizeof(udphdr) */
47 #include <linux/phy.h>
51 #include <linux/slab.h>
52 #include <linux/interrupt.h>
53 #include <linux/dma-mapping.h>
60 /* ---------------------------------------------------------------------
61 * Low level register access functions
64 u32 temac_ior(struct temac_local *lp, int offset)
66 return in_be32(lp->regs + offset);
69 void temac_iow(struct temac_local *lp, int offset, u32 value)
71 out_be32(lp->regs + offset, value);
74 int temac_indirect_busywait(struct temac_local *lp)
76 unsigned long end = jiffies + 2;
78 while (!(temac_ior(lp, XTE_RDY0_OFFSET) & XTE_RDY0_HARD_ACS_RDY_MASK)) {
79 if (time_before_eq(end, jiffies)) {
91 * lp->indirect_mutex must be held when calling this function
93 u32 temac_indirect_in32(struct temac_local *lp, int reg)
97 if (temac_indirect_busywait(lp))
99 temac_iow(lp, XTE_CTL0_OFFSET, reg);
100 if (temac_indirect_busywait(lp))
102 val = temac_ior(lp, XTE_LSW0_OFFSET);
108 * temac_indirect_out32
110 * lp->indirect_mutex must be held when calling this function
112 void temac_indirect_out32(struct temac_local *lp, int reg, u32 value)
114 if (temac_indirect_busywait(lp))
116 temac_iow(lp, XTE_LSW0_OFFSET, value);
117 temac_iow(lp, XTE_CTL0_OFFSET, CNTLREG_WRITE_ENABLE_MASK | reg);
118 temac_indirect_busywait(lp);
122 * temac_dma_in32 - Memory mapped DMA read, this function expects a
123 * register input that is based on DCR word addresses which
124 * are then converted to memory mapped byte addresses
126 static u32 temac_dma_in32(struct temac_local *lp, int reg)
128 return in_be32(lp->sdma_regs + (reg << 2));
132 * temac_dma_out32 - Memory mapped DMA read, this function expects a
133 * register input that is based on DCR word addresses which
134 * are then converted to memory mapped byte addresses
136 static void temac_dma_out32(struct temac_local *lp, int reg, u32 value)
138 out_be32(lp->sdma_regs + (reg << 2), value);
141 /* DMA register access functions can be DCR based or memory mapped.
142 * The PowerPC 440 is DCR based, the PowerPC 405 and MicroBlaze are both
145 #ifdef CONFIG_PPC_DCR
148 * temac_dma_dcr_in32 - DCR based DMA read
150 static u32 temac_dma_dcr_in(struct temac_local *lp, int reg)
152 return dcr_read(lp->sdma_dcrs, reg);
156 * temac_dma_dcr_out32 - DCR based DMA write
158 static void temac_dma_dcr_out(struct temac_local *lp, int reg, u32 value)
160 dcr_write(lp->sdma_dcrs, reg, value);
164 * temac_dcr_setup - If the DMA is DCR based, then setup the address and
167 static int temac_dcr_setup(struct temac_local *lp, struct platform_device *op,
168 struct device_node *np)
172 /* setup the dcr address mapping if it's in the device tree */
174 dcrs = dcr_resource_start(np, 0);
176 lp->sdma_dcrs = dcr_map(np, dcrs, dcr_resource_len(np, 0));
177 lp->dma_in = temac_dma_dcr_in;
178 lp->dma_out = temac_dma_dcr_out;
179 dev_dbg(&op->dev, "DCR base: %x\n", dcrs);
182 /* no DCR in the device tree, indicate a failure */
189 * temac_dcr_setup - This is a stub for when DCR is not supported,
190 * such as with MicroBlaze
192 static int temac_dcr_setup(struct temac_local *lp, struct platform_device *op,
193 struct device_node *np)
201 * temac_dma_bd_release - Release buffer descriptor rings
203 static void temac_dma_bd_release(struct net_device *ndev)
205 struct temac_local *lp = netdev_priv(ndev);
208 /* Reset Local Link (DMA) */
209 lp->dma_out(lp, DMA_CONTROL_REG, DMA_CONTROL_RST);
211 for (i = 0; i < RX_BD_NUM; i++) {
215 dma_unmap_single(ndev->dev.parent, lp->rx_bd_v[i].phys,
216 XTE_MAX_JUMBO_FRAME_SIZE, DMA_FROM_DEVICE);
217 dev_kfree_skb(lp->rx_skb[i]);
221 dma_free_coherent(ndev->dev.parent,
222 sizeof(*lp->rx_bd_v) * RX_BD_NUM,
223 lp->rx_bd_v, lp->rx_bd_p);
225 dma_free_coherent(ndev->dev.parent,
226 sizeof(*lp->tx_bd_v) * TX_BD_NUM,
227 lp->tx_bd_v, lp->tx_bd_p);
232 * temac_dma_bd_init - Setup buffer descriptor rings
234 static int temac_dma_bd_init(struct net_device *ndev)
236 struct temac_local *lp = netdev_priv(ndev);
240 lp->rx_skb = kcalloc(RX_BD_NUM, sizeof(*lp->rx_skb), GFP_KERNEL);
244 /* allocate the tx and rx ring buffer descriptors. */
245 /* returns a virtual address and a physical address. */
246 lp->tx_bd_v = dma_zalloc_coherent(ndev->dev.parent,
247 sizeof(*lp->tx_bd_v) * TX_BD_NUM,
248 &lp->tx_bd_p, GFP_KERNEL);
252 lp->rx_bd_v = dma_zalloc_coherent(ndev->dev.parent,
253 sizeof(*lp->rx_bd_v) * RX_BD_NUM,
254 &lp->rx_bd_p, GFP_KERNEL);
258 for (i = 0; i < TX_BD_NUM; i++) {
259 lp->tx_bd_v[i].next = lp->tx_bd_p +
260 sizeof(*lp->tx_bd_v) * ((i + 1) % TX_BD_NUM);
263 for (i = 0; i < RX_BD_NUM; i++) {
264 lp->rx_bd_v[i].next = lp->rx_bd_p +
265 sizeof(*lp->rx_bd_v) * ((i + 1) % RX_BD_NUM);
267 skb = netdev_alloc_skb_ip_align(ndev,
268 XTE_MAX_JUMBO_FRAME_SIZE);
273 /* returns physical address of skb->data */
274 lp->rx_bd_v[i].phys = dma_map_single(ndev->dev.parent,
276 XTE_MAX_JUMBO_FRAME_SIZE,
278 lp->rx_bd_v[i].len = XTE_MAX_JUMBO_FRAME_SIZE;
279 lp->rx_bd_v[i].app0 = STS_CTRL_APP0_IRQONEND;
282 lp->dma_out(lp, TX_CHNL_CTRL, 0x10220400 |
284 CHNL_CTRL_IRQ_DLY_EN |
285 CHNL_CTRL_IRQ_COAL_EN);
288 lp->dma_out(lp, RX_CHNL_CTRL, 0xff070000 |
290 CHNL_CTRL_IRQ_DLY_EN |
291 CHNL_CTRL_IRQ_COAL_EN |
295 lp->dma_out(lp, RX_CURDESC_PTR, lp->rx_bd_p);
296 lp->dma_out(lp, RX_TAILDESC_PTR,
297 lp->rx_bd_p + (sizeof(*lp->rx_bd_v) * (RX_BD_NUM - 1)));
298 lp->dma_out(lp, TX_CURDESC_PTR, lp->tx_bd_p);
300 /* Init descriptor indexes */
309 temac_dma_bd_release(ndev);
313 /* ---------------------------------------------------------------------
317 static void temac_do_set_mac_address(struct net_device *ndev)
319 struct temac_local *lp = netdev_priv(ndev);
321 /* set up unicast MAC address filter set its mac address */
322 mutex_lock(&lp->indirect_mutex);
323 temac_indirect_out32(lp, XTE_UAW0_OFFSET,
324 (ndev->dev_addr[0]) |
325 (ndev->dev_addr[1] << 8) |
326 (ndev->dev_addr[2] << 16) |
327 (ndev->dev_addr[3] << 24));
328 /* There are reserved bits in EUAW1
329 * so don't affect them Set MAC bits [47:32] in EUAW1 */
330 temac_indirect_out32(lp, XTE_UAW1_OFFSET,
331 (ndev->dev_addr[4] & 0x000000ff) |
332 (ndev->dev_addr[5] << 8));
333 mutex_unlock(&lp->indirect_mutex);
336 static int temac_init_mac_address(struct net_device *ndev, const void *address)
338 memcpy(ndev->dev_addr, address, ETH_ALEN);
339 if (!is_valid_ether_addr(ndev->dev_addr))
340 eth_hw_addr_random(ndev);
341 temac_do_set_mac_address(ndev);
345 static int temac_set_mac_address(struct net_device *ndev, void *p)
347 struct sockaddr *addr = p;
349 if (!is_valid_ether_addr(addr->sa_data))
350 return -EADDRNOTAVAIL;
351 memcpy(ndev->dev_addr, addr->sa_data, ETH_ALEN);
352 temac_do_set_mac_address(ndev);
356 static void temac_set_multicast_list(struct net_device *ndev)
358 struct temac_local *lp = netdev_priv(ndev);
359 u32 multi_addr_msw, multi_addr_lsw, val;
362 mutex_lock(&lp->indirect_mutex);
363 if (ndev->flags & (IFF_ALLMULTI | IFF_PROMISC) ||
364 netdev_mc_count(ndev) > MULTICAST_CAM_TABLE_NUM) {
366 * We must make the kernel realise we had to move
367 * into promisc mode or we start all out war on
368 * the cable. If it was a promisc request the
369 * flag is already set. If not we assert it.
371 ndev->flags |= IFF_PROMISC;
372 temac_indirect_out32(lp, XTE_AFM_OFFSET, XTE_AFM_EPPRM_MASK);
373 dev_info(&ndev->dev, "Promiscuous mode enabled.\n");
374 } else if (!netdev_mc_empty(ndev)) {
375 struct netdev_hw_addr *ha;
378 netdev_for_each_mc_addr(ha, ndev) {
379 if (i >= MULTICAST_CAM_TABLE_NUM)
381 multi_addr_msw = ((ha->addr[3] << 24) |
382 (ha->addr[2] << 16) |
385 temac_indirect_out32(lp, XTE_MAW0_OFFSET,
387 multi_addr_lsw = ((ha->addr[5] << 8) |
388 (ha->addr[4]) | (i << 16));
389 temac_indirect_out32(lp, XTE_MAW1_OFFSET,
394 val = temac_indirect_in32(lp, XTE_AFM_OFFSET);
395 temac_indirect_out32(lp, XTE_AFM_OFFSET,
396 val & ~XTE_AFM_EPPRM_MASK);
397 temac_indirect_out32(lp, XTE_MAW0_OFFSET, 0);
398 temac_indirect_out32(lp, XTE_MAW1_OFFSET, 0);
399 dev_info(&ndev->dev, "Promiscuous mode disabled.\n");
401 mutex_unlock(&lp->indirect_mutex);
404 static struct temac_option {
410 } temac_options[] = {
411 /* Turn on jumbo packet support for both Rx and Tx */
413 .opt = XTE_OPTION_JUMBO,
414 .reg = XTE_TXC_OFFSET,
415 .m_or = XTE_TXC_TXJMBO_MASK,
418 .opt = XTE_OPTION_JUMBO,
419 .reg = XTE_RXC1_OFFSET,
420 .m_or =XTE_RXC1_RXJMBO_MASK,
422 /* Turn on VLAN packet support for both Rx and Tx */
424 .opt = XTE_OPTION_VLAN,
425 .reg = XTE_TXC_OFFSET,
426 .m_or =XTE_TXC_TXVLAN_MASK,
429 .opt = XTE_OPTION_VLAN,
430 .reg = XTE_RXC1_OFFSET,
431 .m_or =XTE_RXC1_RXVLAN_MASK,
433 /* Turn on FCS stripping on receive packets */
435 .opt = XTE_OPTION_FCS_STRIP,
436 .reg = XTE_RXC1_OFFSET,
437 .m_or =XTE_RXC1_RXFCS_MASK,
439 /* Turn on FCS insertion on transmit packets */
441 .opt = XTE_OPTION_FCS_INSERT,
442 .reg = XTE_TXC_OFFSET,
443 .m_or =XTE_TXC_TXFCS_MASK,
445 /* Turn on length/type field checking on receive packets */
447 .opt = XTE_OPTION_LENTYPE_ERR,
448 .reg = XTE_RXC1_OFFSET,
449 .m_or =XTE_RXC1_RXLT_MASK,
451 /* Turn on flow control */
453 .opt = XTE_OPTION_FLOW_CONTROL,
454 .reg = XTE_FCC_OFFSET,
455 .m_or =XTE_FCC_RXFLO_MASK,
457 /* Turn on flow control */
459 .opt = XTE_OPTION_FLOW_CONTROL,
460 .reg = XTE_FCC_OFFSET,
461 .m_or =XTE_FCC_TXFLO_MASK,
463 /* Turn on promiscuous frame filtering (all frames are received ) */
465 .opt = XTE_OPTION_PROMISC,
466 .reg = XTE_AFM_OFFSET,
467 .m_or =XTE_AFM_EPPRM_MASK,
469 /* Enable transmitter if not already enabled */
471 .opt = XTE_OPTION_TXEN,
472 .reg = XTE_TXC_OFFSET,
473 .m_or =XTE_TXC_TXEN_MASK,
475 /* Enable receiver? */
477 .opt = XTE_OPTION_RXEN,
478 .reg = XTE_RXC1_OFFSET,
479 .m_or =XTE_RXC1_RXEN_MASK,
487 static u32 temac_setoptions(struct net_device *ndev, u32 options)
489 struct temac_local *lp = netdev_priv(ndev);
490 struct temac_option *tp = &temac_options[0];
493 mutex_lock(&lp->indirect_mutex);
495 reg = temac_indirect_in32(lp, tp->reg) & ~tp->m_or;
496 if (options & tp->opt)
498 temac_indirect_out32(lp, tp->reg, reg);
501 lp->options |= options;
502 mutex_unlock(&lp->indirect_mutex);
507 /* Initialize temac */
508 static void temac_device_reset(struct net_device *ndev)
510 struct temac_local *lp = netdev_priv(ndev);
514 /* Perform a software reset */
516 /* 0x300 host enable bit ? */
517 /* reset PHY through control register ?:1 */
519 dev_dbg(&ndev->dev, "%s()\n", __func__);
521 mutex_lock(&lp->indirect_mutex);
522 /* Reset the receiver and wait for it to finish reset */
523 temac_indirect_out32(lp, XTE_RXC1_OFFSET, XTE_RXC1_RXRST_MASK);
525 while (temac_indirect_in32(lp, XTE_RXC1_OFFSET) & XTE_RXC1_RXRST_MASK) {
527 if (--timeout == 0) {
529 "temac_device_reset RX reset timeout!!\n");
534 /* Reset the transmitter and wait for it to finish reset */
535 temac_indirect_out32(lp, XTE_TXC_OFFSET, XTE_TXC_TXRST_MASK);
537 while (temac_indirect_in32(lp, XTE_TXC_OFFSET) & XTE_TXC_TXRST_MASK) {
539 if (--timeout == 0) {
541 "temac_device_reset TX reset timeout!!\n");
546 /* Disable the receiver */
547 val = temac_indirect_in32(lp, XTE_RXC1_OFFSET);
548 temac_indirect_out32(lp, XTE_RXC1_OFFSET, val & ~XTE_RXC1_RXEN_MASK);
550 /* Reset Local Link (DMA) */
551 lp->dma_out(lp, DMA_CONTROL_REG, DMA_CONTROL_RST);
553 while (lp->dma_in(lp, DMA_CONTROL_REG) & DMA_CONTROL_RST) {
555 if (--timeout == 0) {
557 "temac_device_reset DMA reset timeout!!\n");
561 lp->dma_out(lp, DMA_CONTROL_REG, DMA_TAIL_ENABLE);
563 if (temac_dma_bd_init(ndev)) {
565 "temac_device_reset descriptor allocation failed\n");
568 temac_indirect_out32(lp, XTE_RXC0_OFFSET, 0);
569 temac_indirect_out32(lp, XTE_RXC1_OFFSET, 0);
570 temac_indirect_out32(lp, XTE_TXC_OFFSET, 0);
571 temac_indirect_out32(lp, XTE_FCC_OFFSET, XTE_FCC_RXFLO_MASK);
573 mutex_unlock(&lp->indirect_mutex);
575 /* Sync default options with HW
576 * but leave receiver and transmitter disabled. */
577 temac_setoptions(ndev,
578 lp->options & ~(XTE_OPTION_TXEN | XTE_OPTION_RXEN));
580 temac_do_set_mac_address(ndev);
582 /* Set address filter table */
583 temac_set_multicast_list(ndev);
584 if (temac_setoptions(ndev, lp->options))
585 dev_err(&ndev->dev, "Error setting TEMAC options\n");
587 /* Init Driver variable */
588 netif_trans_update(ndev); /* prevent tx timeout */
591 static void temac_adjust_link(struct net_device *ndev)
593 struct temac_local *lp = netdev_priv(ndev);
594 struct phy_device *phy = ndev->phydev;
598 /* hash together the state values to decide if something has changed */
599 link_state = phy->speed | (phy->duplex << 1) | phy->link;
601 mutex_lock(&lp->indirect_mutex);
602 if (lp->last_link != link_state) {
603 mii_speed = temac_indirect_in32(lp, XTE_EMCFG_OFFSET);
604 mii_speed &= ~XTE_EMCFG_LINKSPD_MASK;
606 switch (phy->speed) {
607 case SPEED_1000: mii_speed |= XTE_EMCFG_LINKSPD_1000; break;
608 case SPEED_100: mii_speed |= XTE_EMCFG_LINKSPD_100; break;
609 case SPEED_10: mii_speed |= XTE_EMCFG_LINKSPD_10; break;
612 /* Write new speed setting out to TEMAC */
613 temac_indirect_out32(lp, XTE_EMCFG_OFFSET, mii_speed);
614 lp->last_link = link_state;
615 phy_print_status(phy);
617 mutex_unlock(&lp->indirect_mutex);
620 static void temac_start_xmit_done(struct net_device *ndev)
622 struct temac_local *lp = netdev_priv(ndev);
623 struct cdmac_bd *cur_p;
624 unsigned int stat = 0;
626 cur_p = &lp->tx_bd_v[lp->tx_bd_ci];
629 while (stat & STS_CTRL_APP0_CMPLT) {
630 dma_unmap_single(ndev->dev.parent, cur_p->phys, cur_p->len,
633 dev_kfree_skb_irq((struct sk_buff *)cur_p->app4);
640 ndev->stats.tx_packets++;
641 ndev->stats.tx_bytes += cur_p->len;
644 if (lp->tx_bd_ci >= TX_BD_NUM)
647 cur_p = &lp->tx_bd_v[lp->tx_bd_ci];
651 netif_wake_queue(ndev);
654 static inline int temac_check_tx_bd_space(struct temac_local *lp, int num_frag)
656 struct cdmac_bd *cur_p;
659 tail = lp->tx_bd_tail;
660 cur_p = &lp->tx_bd_v[tail];
664 return NETDEV_TX_BUSY;
667 if (tail >= TX_BD_NUM)
670 cur_p = &lp->tx_bd_v[tail];
672 } while (num_frag >= 0);
678 temac_start_xmit(struct sk_buff *skb, struct net_device *ndev)
680 struct temac_local *lp = netdev_priv(ndev);
681 struct cdmac_bd *cur_p;
682 dma_addr_t start_p, tail_p;
684 unsigned long num_frag;
687 num_frag = skb_shinfo(skb)->nr_frags;
688 frag = &skb_shinfo(skb)->frags[0];
689 start_p = lp->tx_bd_p + sizeof(*lp->tx_bd_v) * lp->tx_bd_tail;
690 cur_p = &lp->tx_bd_v[lp->tx_bd_tail];
692 if (temac_check_tx_bd_space(lp, num_frag)) {
693 if (!netif_queue_stopped(ndev))
694 netif_stop_queue(ndev);
695 return NETDEV_TX_BUSY;
699 if (skb->ip_summed == CHECKSUM_PARTIAL) {
700 unsigned int csum_start_off = skb_checksum_start_offset(skb);
701 unsigned int csum_index_off = csum_start_off + skb->csum_offset;
703 cur_p->app0 |= 1; /* TX Checksum Enabled */
704 cur_p->app1 = (csum_start_off << 16) | csum_index_off;
705 cur_p->app2 = 0; /* initial checksum seed */
708 cur_p->app0 |= STS_CTRL_APP0_SOP;
709 cur_p->len = skb_headlen(skb);
710 cur_p->phys = dma_map_single(ndev->dev.parent, skb->data,
711 skb_headlen(skb), DMA_TO_DEVICE);
712 cur_p->app4 = (unsigned long)skb;
714 for (ii = 0; ii < num_frag; ii++) {
716 if (lp->tx_bd_tail >= TX_BD_NUM)
719 cur_p = &lp->tx_bd_v[lp->tx_bd_tail];
720 cur_p->phys = dma_map_single(ndev->dev.parent,
721 skb_frag_address(frag),
722 skb_frag_size(frag), DMA_TO_DEVICE);
723 cur_p->len = skb_frag_size(frag);
727 cur_p->app0 |= STS_CTRL_APP0_EOP;
729 tail_p = lp->tx_bd_p + sizeof(*lp->tx_bd_v) * lp->tx_bd_tail;
731 if (lp->tx_bd_tail >= TX_BD_NUM)
734 skb_tx_timestamp(skb);
736 /* Kick off the transfer */
737 lp->dma_out(lp, TX_TAILDESC_PTR, tail_p); /* DMA start */
743 static void ll_temac_recv(struct net_device *ndev)
745 struct temac_local *lp = netdev_priv(ndev);
746 struct sk_buff *skb, *new_skb;
748 struct cdmac_bd *cur_p;
753 spin_lock_irqsave(&lp->rx_lock, flags);
755 tail_p = lp->rx_bd_p + sizeof(*lp->rx_bd_v) * lp->rx_bd_ci;
756 cur_p = &lp->rx_bd_v[lp->rx_bd_ci];
758 bdstat = cur_p->app0;
759 while ((bdstat & STS_CTRL_APP0_CMPLT)) {
761 skb = lp->rx_skb[lp->rx_bd_ci];
762 length = cur_p->app4 & 0x3FFF;
764 dma_unmap_single(ndev->dev.parent, cur_p->phys, length,
767 skb_put(skb, length);
768 skb->protocol = eth_type_trans(skb, ndev);
769 skb_checksum_none_assert(skb);
771 /* if we're doing rx csum offload, set it up */
772 if (((lp->temac_features & TEMAC_FEATURE_RX_CSUM) != 0) &&
773 (skb->protocol == htons(ETH_P_IP)) &&
776 skb->csum = cur_p->app3 & 0xFFFF;
777 skb->ip_summed = CHECKSUM_COMPLETE;
780 if (!skb_defer_rx_timestamp(skb))
783 ndev->stats.rx_packets++;
784 ndev->stats.rx_bytes += length;
786 new_skb = netdev_alloc_skb_ip_align(ndev,
787 XTE_MAX_JUMBO_FRAME_SIZE);
789 spin_unlock_irqrestore(&lp->rx_lock, flags);
793 cur_p->app0 = STS_CTRL_APP0_IRQONEND;
794 cur_p->phys = dma_map_single(ndev->dev.parent, new_skb->data,
795 XTE_MAX_JUMBO_FRAME_SIZE,
797 cur_p->len = XTE_MAX_JUMBO_FRAME_SIZE;
798 lp->rx_skb[lp->rx_bd_ci] = new_skb;
801 if (lp->rx_bd_ci >= RX_BD_NUM)
804 cur_p = &lp->rx_bd_v[lp->rx_bd_ci];
805 bdstat = cur_p->app0;
807 lp->dma_out(lp, RX_TAILDESC_PTR, tail_p);
809 spin_unlock_irqrestore(&lp->rx_lock, flags);
812 static irqreturn_t ll_temac_tx_irq(int irq, void *_ndev)
814 struct net_device *ndev = _ndev;
815 struct temac_local *lp = netdev_priv(ndev);
818 status = lp->dma_in(lp, TX_IRQ_REG);
819 lp->dma_out(lp, TX_IRQ_REG, status);
821 if (status & (IRQ_COAL | IRQ_DLY))
822 temac_start_xmit_done(lp->ndev);
824 dev_err(&ndev->dev, "DMA error 0x%x\n", status);
829 static irqreturn_t ll_temac_rx_irq(int irq, void *_ndev)
831 struct net_device *ndev = _ndev;
832 struct temac_local *lp = netdev_priv(ndev);
835 /* Read and clear the status registers */
836 status = lp->dma_in(lp, RX_IRQ_REG);
837 lp->dma_out(lp, RX_IRQ_REG, status);
839 if (status & (IRQ_COAL | IRQ_DLY))
840 ll_temac_recv(lp->ndev);
845 static int temac_open(struct net_device *ndev)
847 struct temac_local *lp = netdev_priv(ndev);
848 struct phy_device *phydev = NULL;
851 dev_dbg(&ndev->dev, "temac_open()\n");
854 phydev = of_phy_connect(lp->ndev, lp->phy_node,
855 temac_adjust_link, 0, 0);
857 dev_err(lp->dev, "of_phy_connect() failed\n");
864 temac_device_reset(ndev);
866 rc = request_irq(lp->tx_irq, ll_temac_tx_irq, 0, ndev->name, ndev);
869 rc = request_irq(lp->rx_irq, ll_temac_rx_irq, 0, ndev->name, ndev);
876 free_irq(lp->tx_irq, ndev);
879 phy_disconnect(phydev);
880 dev_err(lp->dev, "request_irq() failed\n");
884 static int temac_stop(struct net_device *ndev)
886 struct temac_local *lp = netdev_priv(ndev);
887 struct phy_device *phydev = ndev->phydev;
889 dev_dbg(&ndev->dev, "temac_close()\n");
891 free_irq(lp->tx_irq, ndev);
892 free_irq(lp->rx_irq, ndev);
895 phy_disconnect(phydev);
897 temac_dma_bd_release(ndev);
902 #ifdef CONFIG_NET_POLL_CONTROLLER
904 temac_poll_controller(struct net_device *ndev)
906 struct temac_local *lp = netdev_priv(ndev);
908 disable_irq(lp->tx_irq);
909 disable_irq(lp->rx_irq);
911 ll_temac_rx_irq(lp->tx_irq, ndev);
912 ll_temac_tx_irq(lp->rx_irq, ndev);
914 enable_irq(lp->tx_irq);
915 enable_irq(lp->rx_irq);
919 static int temac_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
921 if (!netif_running(ndev))
927 return phy_mii_ioctl(ndev->phydev, rq, cmd);
930 static const struct net_device_ops temac_netdev_ops = {
931 .ndo_open = temac_open,
932 .ndo_stop = temac_stop,
933 .ndo_start_xmit = temac_start_xmit,
934 .ndo_set_mac_address = temac_set_mac_address,
935 .ndo_validate_addr = eth_validate_addr,
936 .ndo_do_ioctl = temac_ioctl,
937 #ifdef CONFIG_NET_POLL_CONTROLLER
938 .ndo_poll_controller = temac_poll_controller,
942 /* ---------------------------------------------------------------------
943 * SYSFS device attributes
945 static ssize_t temac_show_llink_regs(struct device *dev,
946 struct device_attribute *attr, char *buf)
948 struct net_device *ndev = dev_get_drvdata(dev);
949 struct temac_local *lp = netdev_priv(ndev);
952 for (i = 0; i < 0x11; i++)
953 len += sprintf(buf + len, "%.8x%s", lp->dma_in(lp, i),
954 (i % 8) == 7 ? "\n" : " ");
955 len += sprintf(buf + len, "\n");
960 static DEVICE_ATTR(llink_regs, 0440, temac_show_llink_regs, NULL);
962 static struct attribute *temac_device_attrs[] = {
963 &dev_attr_llink_regs.attr,
967 static const struct attribute_group temac_attr_group = {
968 .attrs = temac_device_attrs,
971 /* ethtool support */
972 static const struct ethtool_ops temac_ethtool_ops = {
973 .nway_reset = phy_ethtool_nway_reset,
974 .get_link = ethtool_op_get_link,
975 .get_ts_info = ethtool_op_get_ts_info,
976 .get_link_ksettings = phy_ethtool_get_link_ksettings,
977 .set_link_ksettings = phy_ethtool_set_link_ksettings,
980 static int temac_of_probe(struct platform_device *op)
982 struct device_node *np;
983 struct temac_local *lp;
984 struct net_device *ndev;
989 /* Init network device structure */
990 ndev = alloc_etherdev(sizeof(*lp));
994 platform_set_drvdata(op, ndev);
995 SET_NETDEV_DEV(ndev, &op->dev);
996 ndev->flags &= ~IFF_MULTICAST; /* clear multicast */
997 ndev->features = NETIF_F_SG;
998 ndev->netdev_ops = &temac_netdev_ops;
999 ndev->ethtool_ops = &temac_ethtool_ops;
1001 ndev->features |= NETIF_F_IP_CSUM; /* Can checksum TCP/UDP over IPv4. */
1002 ndev->features |= NETIF_F_HW_CSUM; /* Can checksum all the packets. */
1003 ndev->features |= NETIF_F_IPV6_CSUM; /* Can checksum IPV6 TCP/UDP */
1004 ndev->features |= NETIF_F_HIGHDMA; /* Can DMA to high memory. */
1005 ndev->features |= NETIF_F_HW_VLAN_CTAG_TX; /* Transmit VLAN hw accel */
1006 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX; /* Receive VLAN hw acceleration */
1007 ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER; /* Receive VLAN filtering */
1008 ndev->features |= NETIF_F_VLAN_CHALLENGED; /* cannot handle VLAN pkts */
1009 ndev->features |= NETIF_F_GSO; /* Enable software GSO. */
1010 ndev->features |= NETIF_F_MULTI_QUEUE; /* Has multiple TX/RX queues */
1011 ndev->features |= NETIF_F_LRO; /* large receive offload */
1014 /* setup temac private info structure */
1015 lp = netdev_priv(ndev);
1018 lp->options = XTE_OPTION_DEFAULTS;
1019 spin_lock_init(&lp->rx_lock);
1020 mutex_init(&lp->indirect_mutex);
1022 /* map device registers */
1023 lp->regs = of_iomap(op->dev.of_node, 0);
1025 dev_err(&op->dev, "could not map temac regs.\n");
1030 /* Setup checksum offload, but default to off if not specified */
1031 lp->temac_features = 0;
1032 p = (__be32 *)of_get_property(op->dev.of_node, "xlnx,txcsum", NULL);
1033 if (p && be32_to_cpu(*p)) {
1034 lp->temac_features |= TEMAC_FEATURE_TX_CSUM;
1035 /* Can checksum TCP/UDP over IPv4. */
1036 ndev->features |= NETIF_F_IP_CSUM;
1038 p = (__be32 *)of_get_property(op->dev.of_node, "xlnx,rxcsum", NULL);
1039 if (p && be32_to_cpu(*p))
1040 lp->temac_features |= TEMAC_FEATURE_RX_CSUM;
1042 /* Find the DMA node, map the DMA registers, and decode the DMA IRQs */
1043 np = of_parse_phandle(op->dev.of_node, "llink-connected", 0);
1045 dev_err(&op->dev, "could not find DMA node\n");
1050 /* Setup the DMA register accesses, could be DCR or memory mapped */
1051 if (temac_dcr_setup(lp, op, np)) {
1053 /* no DCR in the device tree, try non-DCR */
1054 lp->sdma_regs = of_iomap(np, 0);
1055 if (lp->sdma_regs) {
1056 lp->dma_in = temac_dma_in32;
1057 lp->dma_out = temac_dma_out32;
1058 dev_dbg(&op->dev, "MEM base: %p\n", lp->sdma_regs);
1060 dev_err(&op->dev, "unable to map DMA registers\n");
1066 lp->rx_irq = irq_of_parse_and_map(np, 0);
1067 lp->tx_irq = irq_of_parse_and_map(np, 1);
1069 of_node_put(np); /* Finished with the DMA node; drop the reference */
1071 if (!lp->rx_irq || !lp->tx_irq) {
1072 dev_err(&op->dev, "could not determine irqs\n");
1078 /* Retrieve the MAC address */
1079 addr = of_get_mac_address(op->dev.of_node);
1081 dev_err(&op->dev, "could not find MAC address\n");
1085 temac_init_mac_address(ndev, addr);
1087 rc = temac_mdio_setup(lp, op->dev.of_node);
1089 dev_warn(&op->dev, "error registering MDIO bus\n");
1091 lp->phy_node = of_parse_phandle(op->dev.of_node, "phy-handle", 0);
1093 dev_dbg(lp->dev, "using PHY node %pOF (%p)\n", np, np);
1095 /* Add the device attributes */
1096 rc = sysfs_create_group(&lp->dev->kobj, &temac_attr_group);
1098 dev_err(lp->dev, "Error creating sysfs files\n");
1102 rc = register_netdev(lp->ndev);
1104 dev_err(lp->dev, "register_netdev() error (%i)\n", rc);
1105 goto err_register_ndev;
1111 sysfs_remove_group(&lp->dev->kobj, &temac_attr_group);
1114 iounmap(lp->sdma_regs);
1123 static int temac_of_remove(struct platform_device *op)
1125 struct net_device *ndev = platform_get_drvdata(op);
1126 struct temac_local *lp = netdev_priv(ndev);
1128 temac_mdio_teardown(lp);
1129 unregister_netdev(ndev);
1130 sysfs_remove_group(&lp->dev->kobj, &temac_attr_group);
1131 of_node_put(lp->phy_node);
1132 lp->phy_node = NULL;
1135 iounmap(lp->sdma_regs);
1140 static const struct of_device_id temac_of_match[] = {
1141 { .compatible = "xlnx,xps-ll-temac-1.01.b", },
1142 { .compatible = "xlnx,xps-ll-temac-2.00.a", },
1143 { .compatible = "xlnx,xps-ll-temac-2.02.a", },
1144 { .compatible = "xlnx,xps-ll-temac-2.03.a", },
1147 MODULE_DEVICE_TABLE(of, temac_of_match);
1149 static struct platform_driver temac_of_driver = {
1150 .probe = temac_of_probe,
1151 .remove = temac_of_remove,
1153 .name = "xilinx_temac",
1154 .of_match_table = temac_of_match,
1158 module_platform_driver(temac_of_driver);
1160 MODULE_DESCRIPTION("Xilinx LL_TEMAC Ethernet driver");
1161 MODULE_AUTHOR("Yoshio Kashiwagi");
1162 MODULE_LICENSE("GPL");