drivers/net/ethernet/xscale/ixp4xx_eth.c

   1 /*
   2  * Intel IXP4xx Ethernet driver for Linux
   3  *
   4  * Copyright (C) 2007 Krzysztof Halasa <khc@pm.waw.pl>
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms of version 2 of the GNU General Public License
   8  * as published by the Free Software Foundation.
   9  *
  10  * Ethernet port config (0x00 is not present on IXP42X):
  11  *
  12  * logical port         0x00            0x10            0x20
  13  * NPE                  0 (NPE-A)       1 (NPE-B)       2 (NPE-C)
  14  * physical PortId      2               0               1
  15  * TX queue             23              24              25
  16  * RX-free queue        26              27              28
  17  * TX-done queue is always 31, per-port RX and TX-ready queues are configurable
  18  *
  19  *
  20  * Queue entries:
  21  * bits 0 -> 1  - NPE ID (RX and TX-done)
  22  * bits 0 -> 2  - priority (TX, per 802.1D)
  23  * bits 3 -> 4  - port ID (user-set?)
  24  * bits 5 -> 31 - physical descriptor address
  25  */
  26
  27 #include <linux/delay.h>
  28 #include <linux/dma-mapping.h>
  29 #include <linux/dmapool.h>
  30 #include <linux/etherdevice.h>
  31 #include <linux/io.h>
  32 #include <linux/kernel.h>
  33 #include <linux/net_tstamp.h>
  34 #include <linux/phy.h>
  35 #include <linux/platform_device.h>
  36 #include <linux/ptp_classify.h>
  37 #include <linux/slab.h>
  38 #include <linux/module.h>
  39 #include <mach/ixp46x_ts.h>
  40 #include <mach/npe.h>
  41 #include <mach/qmgr.h>
  42
  43 #define DEBUG_DESC              0
  44 #define DEBUG_RX                0
  45 #define DEBUG_TX                0
  46 #define DEBUG_PKT_BYTES         0
  47 #define DEBUG_MDIO              0
  48 #define DEBUG_CLOSE             0
  49
  50 #define DRV_NAME                "ixp4xx_eth"
  51
  52 #define MAX_NPES                3
  53
  54 #define RX_DESCS                64 /* also length of all RX queues */
  55 #define TX_DESCS                16 /* also length of all TX queues */
  56 #define TXDONE_QUEUE_LEN        64 /* dwords */
  57
  58 #define POOL_ALLOC_SIZE         (sizeof(struct desc) * (RX_DESCS + TX_DESCS))
  59 #define REGS_SIZE               0x1000
  60 #define MAX_MRU                 1536 /* 0x600 */
  61 #define RX_BUFF_SIZE            ALIGN((NET_IP_ALIGN) + MAX_MRU, 4)
  62
  63 #define NAPI_WEIGHT             16
  64 #define MDIO_INTERVAL           (3 * HZ)
  65 #define MAX_MDIO_RETRIES        100 /* microseconds, typically 30 cycles */
  66 #define MAX_CLOSE_WAIT          1000 /* microseconds, typically 2-3 cycles */
  67
  68 #define NPE_ID(port_id)         ((port_id) >> 4)
  69 #define PHYSICAL_ID(port_id)    ((NPE_ID(port_id) + 2) % 3)
  70 #define TX_QUEUE(port_id)       (NPE_ID(port_id) + 23)
  71 #define RXFREE_QUEUE(port_id)   (NPE_ID(port_id) + 26)
  72 #define TXDONE_QUEUE            31
  73
  74 #define PTP_SLAVE_MODE          1
  75 #define PTP_MASTER_MODE         2
  76 #define PORT2CHANNEL(p)         NPE_ID(p->id)
  77
  78 /* TX Control Registers */
  79 #define TX_CNTRL0_TX_EN         0x01
  80 #define TX_CNTRL0_HALFDUPLEX    0x02
  81 #define TX_CNTRL0_RETRY         0x04
  82 #define TX_CNTRL0_PAD_EN        0x08
  83 #define TX_CNTRL0_APPEND_FCS    0x10
  84 #define TX_CNTRL0_2DEFER        0x20
  85 #define TX_CNTRL0_RMII          0x40 /* reduced MII */
  86 #define TX_CNTRL1_RETRIES       0x0F /* 4 bits */
  87
  88 /* RX Control Registers */
  89 #define RX_CNTRL0_RX_EN         0x01
  90 #define RX_CNTRL0_PADSTRIP_EN   0x02
  91 #define RX_CNTRL0_SEND_FCS      0x04
  92 #define RX_CNTRL0_PAUSE_EN      0x08
  93 #define RX_CNTRL0_LOOP_EN       0x10
  94 #define RX_CNTRL0_ADDR_FLTR_EN  0x20
  95 #define RX_CNTRL0_RX_RUNT_EN    0x40
  96 #define RX_CNTRL0_BCAST_DIS     0x80
  97 #define RX_CNTRL1_DEFER_EN      0x01
  98
  99 /* Core Control Register */
 100 #define CORE_RESET              0x01
 101 #define CORE_RX_FIFO_FLUSH      0x02
 102 #define CORE_TX_FIFO_FLUSH      0x04
 103 #define CORE_SEND_JAM           0x08
 104 #define CORE_MDC_EN             0x10 /* MDIO using NPE-B ETH-0 only */
 105
 106 #define DEFAULT_TX_CNTRL0       (TX_CNTRL0_TX_EN | TX_CNTRL0_RETRY |    \
 107                                  TX_CNTRL0_PAD_EN | TX_CNTRL0_APPEND_FCS | \
 108                                  TX_CNTRL0_2DEFER)
 109 #define DEFAULT_RX_CNTRL0       RX_CNTRL0_RX_EN
 110 #define DEFAULT_CORE_CNTRL      CORE_MDC_EN
 111
 112
 113 /* NPE message codes */
 114 #define NPE_GETSTATUS                   0x00
 115 #define NPE_EDB_SETPORTADDRESS          0x01
 116 #define NPE_EDB_GETMACADDRESSDATABASE   0x02
 117 #define NPE_EDB_SETMACADDRESSSDATABASE  0x03
 118 #define NPE_GETSTATS                    0x04
 119 #define NPE_RESETSTATS                  0x05
 120 #define NPE_SETMAXFRAMELENGTHS          0x06
 121 #define NPE_VLAN_SETRXTAGMODE           0x07
 122 #define NPE_VLAN_SETDEFAULTRXVID        0x08
 123 #define NPE_VLAN_SETPORTVLANTABLEENTRY  0x09
 124 #define NPE_VLAN_SETPORTVLANTABLERANGE  0x0A
 125 #define NPE_VLAN_SETRXQOSENTRY          0x0B
 126 #define NPE_VLAN_SETPORTIDEXTRACTIONMODE 0x0C
 127 #define NPE_STP_SETBLOCKINGSTATE        0x0D
 128 #define NPE_FW_SETFIREWALLMODE          0x0E
 129 #define NPE_PC_SETFRAMECONTROLDURATIONID 0x0F
 130 #define NPE_PC_SETAPMACTABLE            0x11
 131 #define NPE_SETLOOPBACK_MODE            0x12
 132 #define NPE_PC_SETBSSIDTABLE            0x13
 133 #define NPE_ADDRESS_FILTER_CONFIG       0x14
 134 #define NPE_APPENDFCSCONFIG             0x15
 135 #define NPE_NOTIFY_MAC_RECOVERY_DONE    0x16
 136 #define NPE_MAC_RECOVERY_START          0x17
 137
 138
 139 #ifdef __ARMEB__
 140 typedef struct sk_buff buffer_t;
 141 #define free_buffer dev_kfree_skb
 142 #define free_buffer_irq dev_kfree_skb_irq
 143 #else
 144 typedef void buffer_t;
 145 #define free_buffer kfree
 146 #define free_buffer_irq kfree
 147 #endif
 148
 149 struct eth_regs {
 150         u32 tx_control[2], __res1[2];           /* 000 */
 151         u32 rx_control[2], __res2[2];           /* 010 */
 152         u32 random_seed, __res3[3];             /* 020 */
 153         u32 partial_empty_threshold, __res4;    /* 030 */
 154         u32 partial_full_threshold, __res5;     /* 038 */
 155         u32 tx_start_bytes, __res6[3];          /* 040 */
 156         u32 tx_deferral, rx_deferral, __res7[2];/* 050 */
 157         u32 tx_2part_deferral[2], __res8[2];    /* 060 */
 158         u32 slot_time, __res9[3];               /* 070 */
 159         u32 mdio_command[4];                    /* 080 */
 160         u32 mdio_status[4];                     /* 090 */
 161         u32 mcast_mask[6], __res10[2];          /* 0A0 */
 162         u32 mcast_addr[6], __res11[2];          /* 0C0 */
 163         u32 int_clock_threshold, __res12[3];    /* 0E0 */
 164         u32 hw_addr[6], __res13[61];            /* 0F0 */
 165         u32 core_control;                       /* 1FC */
 166 };
 167
 168 struct port {
 169         struct resource *mem_res;
 170         struct eth_regs __iomem *regs;
 171         struct npe *npe;
 172         struct net_device *netdev;
 173         struct napi_struct napi;
 174         struct eth_plat_info *plat;
 175         buffer_t *rx_buff_tab[RX_DESCS], *tx_buff_tab[TX_DESCS];
 176         struct desc *desc_tab;  /* coherent */
 177         u32 desc_tab_phys;
 178         int id;                 /* logical port ID */
 179         int speed, duplex;
 180         u8 firmware[4];
 181         int hwts_tx_en;
 182         int hwts_rx_en;
 183 };
 184
 185 /* NPE message structure */
 186 struct msg {
 187 #ifdef __ARMEB__
 188         u8 cmd, eth_id, byte2, byte3;
 189         u8 byte4, byte5, byte6, byte7;
 190 #else
 191         u8 byte3, byte2, eth_id, cmd;
 192         u8 byte7, byte6, byte5, byte4;
 193 #endif
 194 };
 195
 196 /* Ethernet packet descriptor */
 197 struct desc {
 198         u32 next;               /* pointer to next buffer, unused */
 199
 200 #ifdef __ARMEB__
 201         u16 buf_len;            /* buffer length */
 202         u16 pkt_len;            /* packet length */
 203         u32 data;               /* pointer to data buffer in RAM */
 204         u8 dest_id;
 205         u8 src_id;
 206         u16 flags;
 207         u8 qos;
 208         u8 padlen;
 209         u16 vlan_tci;
 210 #else
 211         u16 pkt_len;            /* packet length */
 212         u16 buf_len;            /* buffer length */
 213         u32 data;               /* pointer to data buffer in RAM */
 214         u16 flags;
 215         u8 src_id;
 216         u8 dest_id;
 217         u16 vlan_tci;
 218         u8 padlen;
 219         u8 qos;
 220 #endif
 221
 222 #ifdef __ARMEB__
 223         u8 dst_mac_0, dst_mac_1, dst_mac_2, dst_mac_3;
 224         u8 dst_mac_4, dst_mac_5, src_mac_0, src_mac_1;
 225         u8 src_mac_2, src_mac_3, src_mac_4, src_mac_5;
 226 #else
 227         u8 dst_mac_3, dst_mac_2, dst_mac_1, dst_mac_0;
 228         u8 src_mac_1, src_mac_0, dst_mac_5, dst_mac_4;
 229         u8 src_mac_5, src_mac_4, src_mac_3, src_mac_2;
 230 #endif
 231 };
 232
 233
 234 #define rx_desc_phys(port, n)   ((port)->desc_tab_phys +                \
 235                                  (n) * sizeof(struct desc))
 236 #define rx_desc_ptr(port, n)    (&(port)->desc_tab[n])
 237
 238 #define tx_desc_phys(port, n)   ((port)->desc_tab_phys +                \
 239                                  ((n) + RX_DESCS) * sizeof(struct desc))
 240 #define tx_desc_ptr(port, n)    (&(port)->desc_tab[(n) + RX_DESCS])
 241
 242 #ifndef __ARMEB__
 243 static inline void memcpy_swab32(u32 *dest, u32 *src, int cnt)
 244 {
 245         int i;
 246         for (i = 0; i < cnt; i++)
 247                 dest[i] = swab32(src[i]);
 248 }
 249 #endif
 250
 251 static spinlock_t mdio_lock;
 252 static struct eth_regs __iomem *mdio_regs; /* mdio command and status only */
 253 static struct mii_bus *mdio_bus;
 254 static int ports_open;
 255 static struct port *npe_port_tab[MAX_NPES];
 256 static struct dma_pool *dma_pool;
 257
 258 static int ixp_ptp_match(struct sk_buff *skb, u16 uid_hi, u32 uid_lo, u16 seqid)
 259 {
 260         u8 *data = skb->data;
 261         unsigned int offset;
 262         u16 *hi, *id;
 263         u32 lo;
 264
 265         if (ptp_classify_raw(skb) != PTP_CLASS_V1_IPV4)
 266                 return 0;
 267
 268         offset = ETH_HLEN + IPV4_HLEN(data) + UDP_HLEN;
 269
 270         if (skb->len < offset + OFF_PTP_SEQUENCE_ID + sizeof(seqid))
 271                 return 0;
 272
 273         hi = (u16 *)(data + offset + OFF_PTP_SOURCE_UUID);
 274         id = (u16 *)(data + offset + OFF_PTP_SEQUENCE_ID);
 275
 276         memcpy(&lo, &hi[1], sizeof(lo));
 277
 278         return (uid_hi == ntohs(*hi) &&
 279                 uid_lo == ntohl(lo) &&
 280                 seqid  == ntohs(*id));
 281 }
 282
 283 static void ixp_rx_timestamp(struct port *port, struct sk_buff *skb)
 284 {
 285         struct skb_shared_hwtstamps *shhwtstamps;
 286         struct ixp46x_ts_regs *regs;
 287         u64 ns;
 288         u32 ch, hi, lo, val;
 289         u16 uid, seq;
 290
 291         if (!port->hwts_rx_en)
 292                 return;
 293
 294         ch = PORT2CHANNEL(port);
 295
 296         regs = (struct ixp46x_ts_regs __iomem *) IXP4XX_TIMESYNC_BASE_VIRT;
 297
 298         val = __raw_readl(&regs->channel[ch].ch_event);
 299
 300         if (!(val & RX_SNAPSHOT_LOCKED))
 301                 return;
 302
 303         lo = __raw_readl(&regs->channel[ch].src_uuid_lo);
 304         hi = __raw_readl(&regs->channel[ch].src_uuid_hi);
 305
 306         uid = hi & 0xffff;
 307         seq = (hi >> 16) & 0xffff;
 308
 309         if (!ixp_ptp_match(skb, htons(uid), htonl(lo), htons(seq)))
 310                 goto out;
 311
 312         lo = __raw_readl(&regs->channel[ch].rx_snap_lo);
 313         hi = __raw_readl(&regs->channel[ch].rx_snap_hi);
 314         ns = ((u64) hi) << 32;
 315         ns |= lo;
 316         ns <<= TICKS_NS_SHIFT;
 317
 318         shhwtstamps = skb_hwtstamps(skb);
 319         memset(shhwtstamps, 0, sizeof(*shhwtstamps));
 320         shhwtstamps->hwtstamp = ns_to_ktime(ns);
 321 out:
 322         __raw_writel(RX_SNAPSHOT_LOCKED, &regs->channel[ch].ch_event);
 323 }
 324
 325 static void ixp_tx_timestamp(struct port *port, struct sk_buff *skb)
 326 {
 327         struct skb_shared_hwtstamps shhwtstamps;
 328         struct ixp46x_ts_regs *regs;
 329         struct skb_shared_info *shtx;
 330         u64 ns;
 331         u32 ch, cnt, hi, lo, val;
 332
 333         shtx = skb_shinfo(skb);
 334         if (unlikely(shtx->tx_flags & SKBTX_HW_TSTAMP && port->hwts_tx_en))
 335                 shtx->tx_flags |= SKBTX_IN_PROGRESS;
 336         else
 337                 return;
 338
 339         ch = PORT2CHANNEL(port);
 340
 341         regs = (struct ixp46x_ts_regs __iomem *) IXP4XX_TIMESYNC_BASE_VIRT;
 342
 343         /*
 344          * This really stinks, but we have to poll for the Tx time stamp.
 345          * Usually, the time stamp is ready after 4 to 6 microseconds.
 346          */
 347         for (cnt = 0; cnt < 100; cnt++) {
 348                 val = __raw_readl(&regs->channel[ch].ch_event);
 349                 if (val & TX_SNAPSHOT_LOCKED)
 350                         break;
 351                 udelay(1);
 352         }
 353         if (!(val & TX_SNAPSHOT_LOCKED)) {
 354                 shtx->tx_flags &= ~SKBTX_IN_PROGRESS;
 355                 return;
 356         }
 357
 358         lo = __raw_readl(&regs->channel[ch].tx_snap_lo);
 359         hi = __raw_readl(&regs->channel[ch].tx_snap_hi);
 360         ns = ((u64) hi) << 32;
 361         ns |= lo;
 362         ns <<= TICKS_NS_SHIFT;
 363
 364         memset(&shhwtstamps, 0, sizeof(shhwtstamps));
 365         shhwtstamps.hwtstamp = ns_to_ktime(ns);
 366         skb_tstamp_tx(skb, &shhwtstamps);
 367
 368         __raw_writel(TX_SNAPSHOT_LOCKED, &regs->channel[ch].ch_event);
 369 }
 370
 371 static int hwtstamp_set(struct net_device *netdev, struct ifreq *ifr)
 372 {
 373         struct hwtstamp_config cfg;
 374         struct ixp46x_ts_regs *regs;
 375         struct port *port = netdev_priv(netdev);
 376         int ch;
 377
 378         if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg)))
 379                 return -EFAULT;
 380
 381         if (cfg.flags) /* reserved for future extensions */
 382                 return -EINVAL;
 383
 384         ch = PORT2CHANNEL(port);
 385         regs = (struct ixp46x_ts_regs __iomem *) IXP4XX_TIMESYNC_BASE_VIRT;
 386
 387         if (cfg.tx_type != HWTSTAMP_TX_OFF && cfg.tx_type != HWTSTAMP_TX_ON)
 388                 return -ERANGE;
 389
 390         switch (cfg.rx_filter) {
 391         case HWTSTAMP_FILTER_NONE:
 392                 port->hwts_rx_en = 0;
 393                 break;
 394         case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
 395                 port->hwts_rx_en = PTP_SLAVE_MODE;
 396                 __raw_writel(0, &regs->channel[ch].ch_control);
 397                 break;
 398         case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
 399                 port->hwts_rx_en = PTP_MASTER_MODE;
 400                 __raw_writel(MASTER_MODE, &regs->channel[ch].ch_control);
 401                 break;
 402         default:
 403                 return -ERANGE;
 404         }
 405
 406         port->hwts_tx_en = cfg.tx_type == HWTSTAMP_TX_ON;
 407
 408         /* Clear out any old time stamps. */
 409         __raw_writel(TX_SNAPSHOT_LOCKED | RX_SNAPSHOT_LOCKED,
 410                      &regs->channel[ch].ch_event);
 411
 412         return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
 413 }
 414
 415 static int hwtstamp_get(struct net_device *netdev, struct ifreq *ifr)
 416 {
 417         struct hwtstamp_config cfg;
 418         struct port *port = netdev_priv(netdev);
 419
 420         cfg.flags = 0;
 421         cfg.tx_type = port->hwts_tx_en ? HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF;
 422
 423         switch (port->hwts_rx_en) {
 424         case 0:
 425                 cfg.rx_filter = HWTSTAMP_FILTER_NONE;
 426                 break;
 427         case PTP_SLAVE_MODE:
 428                 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_SYNC;
 429                 break;
 430         case PTP_MASTER_MODE:
 431                 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ;
 432                 break;
 433         default:
 434                 WARN_ON_ONCE(1);
 435                 return -ERANGE;
 436         }
 437
 438         return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
 439 }
 440
 441 static int ixp4xx_mdio_cmd(struct mii_bus *bus, int phy_id, int location,
 442                            int write, u16 cmd)
 443 {
 444         int cycles = 0;
 445
 446         if (__raw_readl(&mdio_regs->mdio_command[3]) & 0x80) {
 447                 printk(KERN_ERR "%s: MII not ready to transmit\n", bus->name);
 448                 return -1;
 449         }
 450
 451         if (write) {
 452                 __raw_writel(cmd & 0xFF, &mdio_regs->mdio_command[0]);
 453                 __raw_writel(cmd >> 8, &mdio_regs->mdio_command[1]);
 454         }
 455         __raw_writel(((phy_id << 5) | location) & 0xFF,
 456                      &mdio_regs->mdio_command[2]);
 457         __raw_writel((phy_id >> 3) | (write << 2) | 0x80 /* GO */,
 458                      &mdio_regs->mdio_command[3]);
 459
 460         while ((cycles < MAX_MDIO_RETRIES) &&
 461                (__raw_readl(&mdio_regs->mdio_command[3]) & 0x80)) {
 462                 udelay(1);
 463                 cycles++;
 464         }
 465
 466         if (cycles == MAX_MDIO_RETRIES) {
 467                 printk(KERN_ERR "%s #%i: MII write failed\n", bus->name,
 468                        phy_id);
 469                 return -1;
 470         }
 471
 472 #if DEBUG_MDIO
 473         printk(KERN_DEBUG "%s #%i: mdio_%s() took %i cycles\n", bus->name,
 474                phy_id, write ? "write" : "read", cycles);
 475 #endif
 476
 477         if (write)
 478                 return 0;
 479
 480         if (__raw_readl(&mdio_regs->mdio_status[3]) & 0x80) {
 481 #if DEBUG_MDIO
 482                 printk(KERN_DEBUG "%s #%i: MII read failed\n", bus->name,
 483                        phy_id);
 484 #endif
 485                 return 0xFFFF; /* don't return error */
 486         }
 487
 488         return (__raw_readl(&mdio_regs->mdio_status[0]) & 0xFF) |
 489                 ((__raw_readl(&mdio_regs->mdio_status[1]) & 0xFF) << 8);
 490 }
 491
 492 static int ixp4xx_mdio_read(struct mii_bus *bus, int phy_id, int location)
 493 {
 494         unsigned long flags;
 495         int ret;
 496
 497         spin_lock_irqsave(&mdio_lock, flags);
 498         ret = ixp4xx_mdio_cmd(bus, phy_id, location, 0, 0);
 499         spin_unlock_irqrestore(&mdio_lock, flags);
 500 #if DEBUG_MDIO
 501         printk(KERN_DEBUG "%s #%i: MII read [%i] -> 0x%X\n", bus->name,
 502                phy_id, location, ret);
 503 #endif
 504         return ret;
 505 }
 506
 507 static int ixp4xx_mdio_write(struct mii_bus *bus, int phy_id, int location,
 508                              u16 val)
 509 {
 510         unsigned long flags;
 511         int ret;
 512
 513         spin_lock_irqsave(&mdio_lock, flags);
 514         ret = ixp4xx_mdio_cmd(bus, phy_id, location, 1, val);
 515         spin_unlock_irqrestore(&mdio_lock, flags);
 516 #if DEBUG_MDIO
 517         printk(KERN_DEBUG "%s #%i: MII write [%i] <- 0x%X, err = %i\n",
 518                bus->name, phy_id, location, val, ret);
 519 #endif
 520         return ret;
 521 }
 522
 523 static int ixp4xx_mdio_register(void)
 524 {
 525         int err;
 526
 527         if (!(mdio_bus = mdiobus_alloc()))
 528                 return -ENOMEM;
 529
 530         if (cpu_is_ixp43x()) {
 531                 /* IXP43x lacks NPE-B and uses NPE-C for MII PHY access */
 532                 if (!(ixp4xx_read_feature_bits() & IXP4XX_FEATURE_NPEC_ETH))
 533                         return -ENODEV;
 534                 mdio_regs = (struct eth_regs __iomem *)IXP4XX_EthC_BASE_VIRT;
 535         } else {
 536                 /* All MII PHY accesses use NPE-B Ethernet registers */
 537                 if (!(ixp4xx_read_feature_bits() & IXP4XX_FEATURE_NPEB_ETH0))
 538                         return -ENODEV;
 539                 mdio_regs = (struct eth_regs __iomem *)IXP4XX_EthB_BASE_VIRT;
 540         }
 541
 542         __raw_writel(DEFAULT_CORE_CNTRL, &mdio_regs->core_control);
 543         spin_lock_init(&mdio_lock);
 544         mdio_bus->name = "IXP4xx MII Bus";
 545         mdio_bus->read = &ixp4xx_mdio_read;
 546         mdio_bus->write = &ixp4xx_mdio_write;
 547         snprintf(mdio_bus->id, MII_BUS_ID_SIZE, "ixp4xx-eth-0");
 548
 549         if ((err = mdiobus_register(mdio_bus)))
 550                 mdiobus_free(mdio_bus);
 551         return err;
 552 }
 553
 554 static void ixp4xx_mdio_remove(void)
 555 {
 556         mdiobus_unregister(mdio_bus);
 557         mdiobus_free(mdio_bus);
 558 }
 559
 560
 561 static void ixp4xx_adjust_link(struct net_device *dev)
 562 {
 563         struct port *port = netdev_priv(dev);
 564         struct phy_device *phydev = dev->phydev;
 565
 566         if (!phydev->link) {
 567                 if (port->speed) {
 568                         port->speed = 0;
 569                         printk(KERN_INFO "%s: link down\n", dev->name);
 570                 }
 571                 return;
 572         }
 573
 574         if (port->speed == phydev->speed && port->duplex == phydev->duplex)
 575                 return;
 576
 577         port->speed = phydev->speed;
 578         port->duplex = phydev->duplex;
 579
 580         if (port->duplex)
 581                 __raw_writel(DEFAULT_TX_CNTRL0 & ~TX_CNTRL0_HALFDUPLEX,
 582                              &port->regs->tx_control[0]);
 583         else
 584                 __raw_writel(DEFAULT_TX_CNTRL0 | TX_CNTRL0_HALFDUPLEX,
 585                              &port->regs->tx_control[0]);
 586
 587         printk(KERN_INFO "%s: link up, speed %u Mb/s, %s duplex\n",
 588                dev->name, port->speed, port->duplex ? "full" : "half");
 589 }
 590
 591
 592 static inline void debug_pkt(struct net_device *dev, const char *func,
 593                              u8 *data, int len)
 594 {
 595 #if DEBUG_PKT_BYTES
 596         int i;
 597
 598         printk(KERN_DEBUG "%s: %s(%i) ", dev->name, func, len);
 599         for (i = 0; i < len; i++) {
 600                 if (i >= DEBUG_PKT_BYTES)
 601                         break;
 602                 printk("%s%02X",
 603                        ((i == 6) || (i == 12) || (i >= 14)) ? " " : "",
 604                        data[i]);
 605         }
 606         printk("\n");
 607 #endif
 608 }
 609
 610
 611 static inline void debug_desc(u32 phys, struct desc *desc)
 612 {
 613 #if DEBUG_DESC
 614         printk(KERN_DEBUG "%X: %X %3X %3X %08X %2X < %2X %4X %X"
 615                " %X %X %02X%02X%02X%02X%02X%02X < %02X%02X%02X%02X%02X%02X\n",
 616                phys, desc->next, desc->buf_len, desc->pkt_len,
 617                desc->data, desc->dest_id, desc->src_id, desc->flags,
 618                desc->qos, desc->padlen, desc->vlan_tci,
 619                desc->dst_mac_0, desc->dst_mac_1, desc->dst_mac_2,
 620                desc->dst_mac_3, desc->dst_mac_4, desc->dst_mac_5,
 621                desc->src_mac_0, desc->src_mac_1, desc->src_mac_2,
 622                desc->src_mac_3, desc->src_mac_4, desc->src_mac_5);
 623 #endif
 624 }
 625
 626 static inline int queue_get_desc(unsigned int queue, struct port *port,
 627                                  int is_tx)
 628 {
 629         u32 phys, tab_phys, n_desc;
 630         struct desc *tab;
 631
 632         if (!(phys = qmgr_get_entry(queue)))
 633                 return -1;
 634
 635         phys &= ~0x1F; /* mask out non-address bits */
 636         tab_phys = is_tx ? tx_desc_phys(port, 0) : rx_desc_phys(port, 0);
 637         tab = is_tx ? tx_desc_ptr(port, 0) : rx_desc_ptr(port, 0);
 638         n_desc = (phys - tab_phys) / sizeof(struct desc);
 639         BUG_ON(n_desc >= (is_tx ? TX_DESCS : RX_DESCS));
 640         debug_desc(phys, &tab[n_desc]);
 641         BUG_ON(tab[n_desc].next);
 642         return n_desc;
 643 }
 644
 645 static inline void queue_put_desc(unsigned int queue, u32 phys,
 646                                   struct desc *desc)
 647 {
 648         debug_desc(phys, desc);
 649         BUG_ON(phys & 0x1F);
 650         qmgr_put_entry(queue, phys);
 651         /* Don't check for queue overflow here, we've allocated sufficient
 652            length and queues >= 32 don't support this check anyway. */
 653 }
 654
 655
 656 static inline void dma_unmap_tx(struct port *port, struct desc *desc)
 657 {
 658 #ifdef __ARMEB__
 659         dma_unmap_single(&port->netdev->dev, desc->data,
 660                          desc->buf_len, DMA_TO_DEVICE);
 661 #else
 662         dma_unmap_single(&port->netdev->dev, desc->data & ~3,
 663                          ALIGN((desc->data & 3) + desc->buf_len, 4),
 664                          DMA_TO_DEVICE);
 665 #endif
 666 }
 667
 668
 669 static void eth_rx_irq(void *pdev)
 670 {
 671         struct net_device *dev = pdev;
 672         struct port *port = netdev_priv(dev);
 673
 674 #if DEBUG_RX
 675         printk(KERN_DEBUG "%s: eth_rx_irq\n", dev->name);
 676 #endif
 677         qmgr_disable_irq(port->plat->rxq);
 678         napi_schedule(&port->napi);
 679 }
 680
 681 static int eth_poll(struct napi_struct *napi, int budget)
 682 {
 683         struct port *port = container_of(napi, struct port, napi);
 684         struct net_device *dev = port->netdev;
 685         unsigned int rxq = port->plat->rxq, rxfreeq = RXFREE_QUEUE(port->id);
 686         int received = 0;
 687
 688 #if DEBUG_RX
 689         printk(KERN_DEBUG "%s: eth_poll\n", dev->name);
 690 #endif
 691
 692         while (received < budget) {
 693                 struct sk_buff *skb;
 694                 struct desc *desc;
 695                 int n;
 696 #ifdef __ARMEB__
 697                 struct sk_buff *temp;
 698                 u32 phys;
 699 #endif
 700
 701                 if ((n = queue_get_desc(rxq, port, 0)) < 0) {
 702 #if DEBUG_RX
 703                         printk(KERN_DEBUG "%s: eth_poll napi_complete\n",
 704                                dev->name);
 705 #endif
 706                         napi_complete(napi);
 707                         qmgr_enable_irq(rxq);
 708                         if (!qmgr_stat_below_low_watermark(rxq) &&
 709                             napi_reschedule(napi)) { /* not empty again */
 710 #if DEBUG_RX
 711                                 printk(KERN_DEBUG "%s: eth_poll"
 712                                        " napi_reschedule successed\n",
 713                                        dev->name);
 714 #endif
 715                                 qmgr_disable_irq(rxq);
 716                                 continue;
 717                         }
 718 #if DEBUG_RX
 719                         printk(KERN_DEBUG "%s: eth_poll all done\n",
 720                                dev->name);
 721 #endif
 722                         return received; /* all work done */
 723                 }
 724
 725                 desc = rx_desc_ptr(port, n);
 726
 727 #ifdef __ARMEB__
 728                 if ((skb = netdev_alloc_skb(dev, RX_BUFF_SIZE))) {
 729                         phys = dma_map_single(&dev->dev, skb->data,
 730                                               RX_BUFF_SIZE, DMA_FROM_DEVICE);
 731                         if (dma_mapping_error(&dev->dev, phys)) {
 732                                 dev_kfree_skb(skb);
 733                                 skb = NULL;
 734                         }
 735                 }
 736 #else
 737                 skb = netdev_alloc_skb(dev,
 738                                        ALIGN(NET_IP_ALIGN + desc->pkt_len, 4));
 739 #endif
 740
 741                 if (!skb) {
 742                         dev->stats.rx_dropped++;
 743                         /* put the desc back on RX-ready queue */
 744                         desc->buf_len = MAX_MRU;
 745                         desc->pkt_len = 0;
 746                         queue_put_desc(rxfreeq, rx_desc_phys(port, n), desc);
 747                         continue;
 748                 }
 749
 750                 /* process received frame */
 751 #ifdef __ARMEB__
 752                 temp = skb;
 753                 skb = port->rx_buff_tab[n];
 754                 dma_unmap_single(&dev->dev, desc->data - NET_IP_ALIGN,
 755                                  RX_BUFF_SIZE, DMA_FROM_DEVICE);
 756 #else
 757                 dma_sync_single_for_cpu(&dev->dev, desc->data - NET_IP_ALIGN,
 758                                         RX_BUFF_SIZE, DMA_FROM_DEVICE);
 759                 memcpy_swab32((u32 *)skb->data, (u32 *)port->rx_buff_tab[n],
 760                               ALIGN(NET_IP_ALIGN + desc->pkt_len, 4) / 4);
 761 #endif
 762                 skb_reserve(skb, NET_IP_ALIGN);
 763                 skb_put(skb, desc->pkt_len);
 764
 765                 debug_pkt(dev, "eth_poll", skb->data, skb->len);
 766
 767                 ixp_rx_timestamp(port, skb);
 768                 skb->protocol = eth_type_trans(skb, dev);
 769                 dev->stats.rx_packets++;
 770                 dev->stats.rx_bytes += skb->len;
 771                 netif_receive_skb(skb);
 772
 773                 /* put the new buffer on RX-free queue */
 774 #ifdef __ARMEB__
 775                 port->rx_buff_tab[n] = temp;
 776                 desc->data = phys + NET_IP_ALIGN;
 777 #endif
 778                 desc->buf_len = MAX_MRU;
 779                 desc->pkt_len = 0;
 780                 queue_put_desc(rxfreeq, rx_desc_phys(port, n), desc);
 781                 received++;
 782         }
 783
 784 #if DEBUG_RX
 785         printk(KERN_DEBUG "eth_poll(): end, not all work done\n");
 786 #endif
 787         return received;                /* not all work done */
 788 }
 789
 790
 791 static void eth_txdone_irq(void *unused)
 792 {
 793         u32 phys;
 794
 795 #if DEBUG_TX
 796         printk(KERN_DEBUG DRV_NAME ": eth_txdone_irq\n");
 797 #endif
 798         while ((phys = qmgr_get_entry(TXDONE_QUEUE)) != 0) {
 799                 u32 npe_id, n_desc;
 800                 struct port *port;
 801                 struct desc *desc;
 802                 int start;
 803
 804                 npe_id = phys & 3;
 805                 BUG_ON(npe_id >= MAX_NPES);
 806                 port = npe_port_tab[npe_id];
 807                 BUG_ON(!port);
 808                 phys &= ~0x1F; /* mask out non-address bits */
 809                 n_desc = (phys - tx_desc_phys(port, 0)) / sizeof(struct desc);
 810                 BUG_ON(n_desc >= TX_DESCS);
 811                 desc = tx_desc_ptr(port, n_desc);
 812                 debug_desc(phys, desc);
 813
 814                 if (port->tx_buff_tab[n_desc]) { /* not the draining packet */
 815                         port->netdev->stats.tx_packets++;
 816                         port->netdev->stats.tx_bytes += desc->pkt_len;
 817
 818                         dma_unmap_tx(port, desc);
 819 #if DEBUG_TX
 820                         printk(KERN_DEBUG "%s: eth_txdone_irq free %p\n",
 821                                port->netdev->name, port->tx_buff_tab[n_desc]);
 822 #endif
 823                         free_buffer_irq(port->tx_buff_tab[n_desc]);
 824                         port->tx_buff_tab[n_desc] = NULL;
 825                 }
 826
 827                 start = qmgr_stat_below_low_watermark(port->plat->txreadyq);
 828                 queue_put_desc(port->plat->txreadyq, phys, desc);
 829                 if (start) { /* TX-ready queue was empty */
 830 #if DEBUG_TX
 831                         printk(KERN_DEBUG "%s: eth_txdone_irq xmit ready\n",
 832                                port->netdev->name);
 833 #endif
 834                         netif_wake_queue(port->netdev);
 835                 }
 836         }
 837 }
 838
 839 static int eth_xmit(struct sk_buff *skb, struct net_device *dev)
 840 {
 841         struct port *port = netdev_priv(dev);
 842         unsigned int txreadyq = port->plat->txreadyq;
 843         int len, offset, bytes, n;
 844         void *mem;
 845         u32 phys;
 846         struct desc *desc;
 847
 848 #if DEBUG_TX
 849         printk(KERN_DEBUG "%s: eth_xmit\n", dev->name);
 850 #endif
 851
 852         if (unlikely(skb->len > MAX_MRU)) {
 853                 dev_kfree_skb(skb);
 854                 dev->stats.tx_errors++;
 855                 return NETDEV_TX_OK;
 856         }
 857
 858         debug_pkt(dev, "eth_xmit", skb->data, skb->len);
 859
 860         len = skb->len;
 861 #ifdef __ARMEB__
 862         offset = 0; /* no need to keep alignment */
 863         bytes = len;
 864         mem = skb->data;
 865 #else
 866         offset = (int)skb->data & 3; /* keep 32-bit alignment */
 867         bytes = ALIGN(offset + len, 4);
 868         if (!(mem = kmalloc(bytes, GFP_ATOMIC))) {
 869                 dev_kfree_skb(skb);
 870                 dev->stats.tx_dropped++;
 871                 return NETDEV_TX_OK;
 872         }
 873         memcpy_swab32(mem, (u32 *)((int)skb->data & ~3), bytes / 4);
 874 #endif
 875
 876         phys = dma_map_single(&dev->dev, mem, bytes, DMA_TO_DEVICE);
 877         if (dma_mapping_error(&dev->dev, phys)) {
 878                 dev_kfree_skb(skb);
 879 #ifndef __ARMEB__
 880                 kfree(mem);
 881 #endif
 882                 dev->stats.tx_dropped++;
 883                 return NETDEV_TX_OK;
 884         }
 885
 886         n = queue_get_desc(txreadyq, port, 1);
 887         BUG_ON(n < 0);
 888         desc = tx_desc_ptr(port, n);
 889
 890 #ifdef __ARMEB__
 891         port->tx_buff_tab[n] = skb;
 892 #else
 893         port->tx_buff_tab[n] = mem;
 894 #endif
 895         desc->data = phys + offset;
 896         desc->buf_len = desc->pkt_len = len;
 897
 898         /* NPE firmware pads short frames with zeros internally */
 899         wmb();
 900         queue_put_desc(TX_QUEUE(port->id), tx_desc_phys(port, n), desc);
 901
 902         if (qmgr_stat_below_low_watermark(txreadyq)) { /* empty */
 903 #if DEBUG_TX
 904                 printk(KERN_DEBUG "%s: eth_xmit queue full\n", dev->name);
 905 #endif
 906                 netif_stop_queue(dev);
 907                 /* we could miss TX ready interrupt */
 908                 /* really empty in fact */
 909                 if (!qmgr_stat_below_low_watermark(txreadyq)) {
 910 #if DEBUG_TX
 911                         printk(KERN_DEBUG "%s: eth_xmit ready again\n",
 912                                dev->name);
 913 #endif
 914                         netif_wake_queue(dev);
 915                 }
 916         }
 917
 918 #if DEBUG_TX
 919         printk(KERN_DEBUG "%s: eth_xmit end\n", dev->name);
 920 #endif
 921
 922         ixp_tx_timestamp(port, skb);
 923         skb_tx_timestamp(skb);
 924
 925 #ifndef __ARMEB__
 926         dev_kfree_skb(skb);
 927 #endif
 928         return NETDEV_TX_OK;
 929 }
 930
 931
 932 static void eth_set_mcast_list(struct net_device *dev)
 933 {
 934         struct port *port = netdev_priv(dev);
 935         struct netdev_hw_addr *ha;
 936         u8 diffs[ETH_ALEN], *addr;
 937         int i;
 938         static const u8 allmulti[] = { 0x01, 0x00, 0x00, 0x00, 0x00, 0x00 };
 939
 940         if ((dev->flags & IFF_ALLMULTI) && !(dev->flags & IFF_PROMISC)) {
 941                 for (i = 0; i < ETH_ALEN; i++) {
 942                         __raw_writel(allmulti[i], &port->regs->mcast_addr[i]);
 943                         __raw_writel(allmulti[i], &port->regs->mcast_mask[i]);
 944                 }
 945                 __raw_writel(DEFAULT_RX_CNTRL0 | RX_CNTRL0_ADDR_FLTR_EN,
 946                         &port->regs->rx_control[0]);
 947                 return;
 948         }
 949
 950         if ((dev->flags & IFF_PROMISC) || netdev_mc_empty(dev)) {
 951                 __raw_writel(DEFAULT_RX_CNTRL0 & ~RX_CNTRL0_ADDR_FLTR_EN,
 952                              &port->regs->rx_control[0]);
 953                 return;
 954         }
 955
 956         eth_zero_addr(diffs);
 957
 958         addr = NULL;
 959         netdev_for_each_mc_addr(ha, dev) {
 960                 if (!addr)
 961                         addr = ha->addr; /* first MAC address */
 962                 for (i = 0; i < ETH_ALEN; i++)
 963                         diffs[i] |= addr[i] ^ ha->addr[i];
 964         }
 965
 966         for (i = 0; i < ETH_ALEN; i++) {
 967                 __raw_writel(addr[i], &port->regs->mcast_addr[i]);
 968                 __raw_writel(~diffs[i], &port->regs->mcast_mask[i]);
 969         }
 970
 971         __raw_writel(DEFAULT_RX_CNTRL0 | RX_CNTRL0_ADDR_FLTR_EN,
 972                      &port->regs->rx_control[0]);
 973 }
 974
 975
 976 static int eth_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
 977 {
 978         if (!netif_running(dev))
 979                 return -EINVAL;
 980
 981         if (cpu_is_ixp46x()) {
 982                 if (cmd == SIOCSHWTSTAMP)
 983                         return hwtstamp_set(dev, req);
 984                 if (cmd == SIOCGHWTSTAMP)
 985                         return hwtstamp_get(dev, req);
 986         }
 987
 988         return phy_mii_ioctl(dev->phydev, req, cmd);
 989 }
 990
 991 /* ethtool support */
 992
 993 static void ixp4xx_get_drvinfo(struct net_device *dev,
 994                                struct ethtool_drvinfo *info)
 995 {
 996         struct port *port = netdev_priv(dev);
 997
 998         strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
 999         snprintf(info->fw_version, sizeof(info->fw_version), "%u:%u:%u:%u",
1000                  port->firmware[0], port->firmware[1],
1001                  port->firmware[2], port->firmware[3]);
1002         strlcpy(info->bus_info, "internal", sizeof(info->bus_info));
1003 }
1004
1005 static int ixp4xx_nway_reset(struct net_device *dev)
1006 {
1007         return phy_start_aneg(dev->phydev);
1008 }
1009
1010 int ixp46x_phc_index = -1;
1011 EXPORT_SYMBOL_GPL(ixp46x_phc_index);
1012
1013 static int ixp4xx_get_ts_info(struct net_device *dev,
1014                               struct ethtool_ts_info *info)
1015 {
1016         if (!cpu_is_ixp46x()) {
1017                 info->so_timestamping =
1018                         SOF_TIMESTAMPING_TX_SOFTWARE |
1019                         SOF_TIMESTAMPING_RX_SOFTWARE |
1020                         SOF_TIMESTAMPING_SOFTWARE;
1021                 info->phc_index = -1;
1022                 return 0;
1023         }
1024         info->so_timestamping =
1025                 SOF_TIMESTAMPING_TX_HARDWARE |
1026                 SOF_TIMESTAMPING_RX_HARDWARE |
1027                 SOF_TIMESTAMPING_RAW_HARDWARE;
1028         info->phc_index = ixp46x_phc_index;
1029         info->tx_types =
1030                 (1 << HWTSTAMP_TX_OFF) |
1031                 (1 << HWTSTAMP_TX_ON);
1032         info->rx_filters =
1033                 (1 << HWTSTAMP_FILTER_NONE) |
1034                 (1 << HWTSTAMP_FILTER_PTP_V1_L4_SYNC) |
1035                 (1 << HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ);
1036         return 0;
1037 }
1038
1039 static const struct ethtool_ops ixp4xx_ethtool_ops = {
1040         .get_drvinfo = ixp4xx_get_drvinfo,
1041         .nway_reset = ixp4xx_nway_reset,
1042         .get_link = ethtool_op_get_link,
1043         .get_ts_info = ixp4xx_get_ts_info,
1044         .get_link_ksettings = phy_ethtool_get_link_ksettings,
1045         .set_link_ksettings = phy_ethtool_set_link_ksettings,
1046 };
1047
1048
1049 static int request_queues(struct port *port)
1050 {
1051         int err;
1052
1053         err = qmgr_request_queue(RXFREE_QUEUE(port->id), RX_DESCS, 0, 0,
1054                                  "%s:RX-free", port->netdev->name);
1055         if (err)
1056                 return err;
1057
1058         err = qmgr_request_queue(port->plat->rxq, RX_DESCS, 0, 0,
1059                                  "%s:RX", port->netdev->name);
1060         if (err)
1061                 goto rel_rxfree;
1062
1063         err = qmgr_request_queue(TX_QUEUE(port->id), TX_DESCS, 0, 0,
1064                                  "%s:TX", port->netdev->name);
1065         if (err)
1066                 goto rel_rx;
1067
1068         err = qmgr_request_queue(port->plat->txreadyq, TX_DESCS, 0, 0,
1069                                  "%s:TX-ready", port->netdev->name);
1070         if (err)
1071                 goto rel_tx;
1072
1073         /* TX-done queue handles skbs sent out by the NPEs */
1074         if (!ports_open) {
1075                 err = qmgr_request_queue(TXDONE_QUEUE, TXDONE_QUEUE_LEN, 0, 0,
1076                                          "%s:TX-done", DRV_NAME);
1077                 if (err)
1078                         goto rel_txready;
1079         }
1080         return 0;
1081
1082 rel_txready:
1083         qmgr_release_queue(port->plat->txreadyq);
1084 rel_tx:
1085         qmgr_release_queue(TX_QUEUE(port->id));
1086 rel_rx:
1087         qmgr_release_queue(port->plat->rxq);
1088 rel_rxfree:
1089         qmgr_release_queue(RXFREE_QUEUE(port->id));
1090         printk(KERN_DEBUG "%s: unable to request hardware queues\n",
1091                port->netdev->name);
1092         return err;
1093 }
1094
1095 static void release_queues(struct port *port)
1096 {
1097         qmgr_release_queue(RXFREE_QUEUE(port->id));
1098         qmgr_release_queue(port->plat->rxq);
1099         qmgr_release_queue(TX_QUEUE(port->id));
1100         qmgr_release_queue(port->plat->txreadyq);
1101
1102         if (!ports_open)
1103                 qmgr_release_queue(TXDONE_QUEUE);
1104 }
1105
1106 static int init_queues(struct port *port)
1107 {
1108         int i;
1109
1110         if (!ports_open) {
1111                 dma_pool = dma_pool_create(DRV_NAME, &port->netdev->dev,
1112                                            POOL_ALLOC_SIZE, 32, 0);
1113                 if (!dma_pool)
1114                         return -ENOMEM;
1115         }
1116
1117         if (!(port->desc_tab = dma_pool_alloc(dma_pool, GFP_KERNEL,
1118                                               &port->desc_tab_phys)))
1119                 return -ENOMEM;
1120         memset(port->desc_tab, 0, POOL_ALLOC_SIZE);
1121         memset(port->rx_buff_tab, 0, sizeof(port->rx_buff_tab)); /* tables */
1122         memset(port->tx_buff_tab, 0, sizeof(port->tx_buff_tab));
1123
1124         /* Setup RX buffers */
1125         for (i = 0; i < RX_DESCS; i++) {
1126                 struct desc *desc = rx_desc_ptr(port, i);
1127                 buffer_t *buff; /* skb or kmalloc()ated memory */
1128                 void *data;
1129 #ifdef __ARMEB__
1130                 if (!(buff = netdev_alloc_skb(port->netdev, RX_BUFF_SIZE)))
1131                         return -ENOMEM;
1132                 data = buff->data;
1133 #else
1134                 if (!(buff = kmalloc(RX_BUFF_SIZE, GFP_KERNEL)))
1135                         return -ENOMEM;
1136                 data = buff;
1137 #endif
1138                 desc->buf_len = MAX_MRU;
1139                 desc->data = dma_map_single(&port->netdev->dev, data,
1140                                             RX_BUFF_SIZE, DMA_FROM_DEVICE);
1141                 if (dma_mapping_error(&port->netdev->dev, desc->data)) {
1142                         free_buffer(buff);
1143                         return -EIO;
1144                 }
1145                 desc->data += NET_IP_ALIGN;
1146                 port->rx_buff_tab[i] = buff;
1147         }
1148
1149         return 0;
1150 }
1151
1152 static void destroy_queues(struct port *port)
1153 {
1154         int i;
1155
1156         if (port->desc_tab) {
1157                 for (i = 0; i < RX_DESCS; i++) {
1158                         struct desc *desc = rx_desc_ptr(port, i);
1159                         buffer_t *buff = port->rx_buff_tab[i];
1160                         if (buff) {
1161                                 dma_unmap_single(&port->netdev->dev,
1162                                                  desc->data - NET_IP_ALIGN,
1163                                                  RX_BUFF_SIZE, DMA_FROM_DEVICE);
1164                                 free_buffer(buff);
1165                         }
1166                 }
1167                 for (i = 0; i < TX_DESCS; i++) {
1168                         struct desc *desc = tx_desc_ptr(port, i);
1169                         buffer_t *buff = port->tx_buff_tab[i];
1170                         if (buff) {
1171                                 dma_unmap_tx(port, desc);
1172                                 free_buffer(buff);
1173                         }
1174                 }
1175                 dma_pool_free(dma_pool, port->desc_tab, port->desc_tab_phys);
1176                 port->desc_tab = NULL;
1177         }
1178
1179         if (!ports_open && dma_pool) {
1180                 dma_pool_destroy(dma_pool);
1181                 dma_pool = NULL;
1182         }
1183 }
1184
1185 static int eth_open(struct net_device *dev)
1186 {
1187         struct port *port = netdev_priv(dev);
1188         struct npe *npe = port->npe;
1189         struct msg msg;
1190         int i, err;
1191
1192         if (!npe_running(npe)) {
1193                 err = npe_load_firmware(npe, npe_name(npe), &dev->dev);
1194                 if (err)
1195                         return err;
1196
1197                 if (npe_recv_message(npe, &msg, "ETH_GET_STATUS")) {
1198                         printk(KERN_ERR "%s: %s not responding\n", dev->name,
1199                                npe_name(npe));
1200                         return -EIO;
1201                 }
1202                 port->firmware[0] = msg.byte4;
1203                 port->firmware[1] = msg.byte5;
1204                 port->firmware[2] = msg.byte6;
1205                 port->firmware[3] = msg.byte7;
1206         }
1207
1208         memset(&msg, 0, sizeof(msg));
1209         msg.cmd = NPE_VLAN_SETRXQOSENTRY;
1210         msg.eth_id = port->id;
1211         msg.byte5 = port->plat->rxq | 0x80;
1212         msg.byte7 = port->plat->rxq << 4;
1213         for (i = 0; i < 8; i++) {
1214                 msg.byte3 = i;
1215                 if (npe_send_recv_message(port->npe, &msg, "ETH_SET_RXQ"))
1216                         return -EIO;
1217         }
1218
1219         msg.cmd = NPE_EDB_SETPORTADDRESS;
1220         msg.eth_id = PHYSICAL_ID(port->id);
1221         msg.byte2 = dev->dev_addr[0];
1222         msg.byte3 = dev->dev_addr[1];
1223         msg.byte4 = dev->dev_addr[2];
1224         msg.byte5 = dev->dev_addr[3];
1225         msg.byte6 = dev->dev_addr[4];
1226         msg.byte7 = dev->dev_addr[5];
1227         if (npe_send_recv_message(port->npe, &msg, "ETH_SET_MAC"))
1228                 return -EIO;
1229
1230         memset(&msg, 0, sizeof(msg));
1231         msg.cmd = NPE_FW_SETFIREWALLMODE;
1232         msg.eth_id = port->id;
1233         if (npe_send_recv_message(port->npe, &msg, "ETH_SET_FIREWALL_MODE"))
1234                 return -EIO;
1235
1236         if ((err = request_queues(port)) != 0)
1237                 return err;
1238
1239         if ((err = init_queues(port)) != 0) {
1240                 destroy_queues(port);
1241                 release_queues(port);
1242                 return err;
1243         }
1244
1245         port->speed = 0;        /* force "link up" message */
1246         phy_start(dev->phydev);
1247
1248         for (i = 0; i < ETH_ALEN; i++)
1249                 __raw_writel(dev->dev_addr[i], &port->regs->hw_addr[i]);
1250         __raw_writel(0x08, &port->regs->random_seed);
1251         __raw_writel(0x12, &port->regs->partial_empty_threshold);
1252         __raw_writel(0x30, &port->regs->partial_full_threshold);
1253         __raw_writel(0x08, &port->regs->tx_start_bytes);
1254         __raw_writel(0x15, &port->regs->tx_deferral);
1255         __raw_writel(0x08, &port->regs->tx_2part_deferral[0]);
1256         __raw_writel(0x07, &port->regs->tx_2part_deferral[1]);
1257         __raw_writel(0x80, &port->regs->slot_time);
1258         __raw_writel(0x01, &port->regs->int_clock_threshold);
1259
1260         /* Populate queues with buffers, no failure after this point */
1261         for (i = 0; i < TX_DESCS; i++)
1262                 queue_put_desc(port->plat->txreadyq,
1263                                tx_desc_phys(port, i), tx_desc_ptr(port, i));
1264
1265         for (i = 0; i < RX_DESCS; i++)
1266                 queue_put_desc(RXFREE_QUEUE(port->id),
1267                                rx_desc_phys(port, i), rx_desc_ptr(port, i));
1268
1269         __raw_writel(TX_CNTRL1_RETRIES, &port->regs->tx_control[1]);
1270         __raw_writel(DEFAULT_TX_CNTRL0, &port->regs->tx_control[0]);
1271         __raw_writel(0, &port->regs->rx_control[1]);
1272         __raw_writel(DEFAULT_RX_CNTRL0, &port->regs->rx_control[0]);
1273
1274         napi_enable(&port->napi);
1275         eth_set_mcast_list(dev);
1276         netif_start_queue(dev);
1277
1278         qmgr_set_irq(port->plat->rxq, QUEUE_IRQ_SRC_NOT_EMPTY,
1279                      eth_rx_irq, dev);
1280         if (!ports_open) {
1281                 qmgr_set_irq(TXDONE_QUEUE, QUEUE_IRQ_SRC_NOT_EMPTY,
1282                              eth_txdone_irq, NULL);
1283                 qmgr_enable_irq(TXDONE_QUEUE);
1284         }
1285         ports_open++;
1286         /* we may already have RX data, enables IRQ */
1287         napi_schedule(&port->napi);
1288         return 0;
1289 }
1290
1291 static int eth_close(struct net_device *dev)
1292 {
1293         struct port *port = netdev_priv(dev);
1294         struct msg msg;
1295         int buffs = RX_DESCS; /* allocated RX buffers */
1296         int i;
1297
1298         ports_open--;
1299         qmgr_disable_irq(port->plat->rxq);
1300         napi_disable(&port->napi);
1301         netif_stop_queue(dev);
1302
1303         while (queue_get_desc(RXFREE_QUEUE(port->id), port, 0) >= 0)
1304                 buffs--;
1305
1306         memset(&msg, 0, sizeof(msg));
1307         msg.cmd = NPE_SETLOOPBACK_MODE;
1308         msg.eth_id = port->id;
1309         msg.byte3 = 1;
1310         if (npe_send_recv_message(port->npe, &msg, "ETH_ENABLE_LOOPBACK"))
1311                 printk(KERN_CRIT "%s: unable to enable loopback\n", dev->name);
1312
1313         i = 0;
1314         do {                    /* drain RX buffers */
1315                 while (queue_get_desc(port->plat->rxq, port, 0) >= 0)
1316                         buffs--;
1317                 if (!buffs)
1318                         break;
1319                 if (qmgr_stat_empty(TX_QUEUE(port->id))) {
1320                         /* we have to inject some packet */
1321                         struct desc *desc;
1322                         u32 phys;
1323                         int n = queue_get_desc(port->plat->txreadyq, port, 1);
1324                         BUG_ON(n < 0);
1325                         desc = tx_desc_ptr(port, n);
1326                         phys = tx_desc_phys(port, n);
1327                         desc->buf_len = desc->pkt_len = 1;
1328                         wmb();
1329                         queue_put_desc(TX_QUEUE(port->id), phys, desc);
1330                 }
1331                 udelay(1);
1332         } while (++i < MAX_CLOSE_WAIT);
1333
1334         if (buffs)
1335                 printk(KERN_CRIT "%s: unable to drain RX queue, %i buffer(s)"
1336                        " left in NPE\n", dev->name, buffs);
1337 #if DEBUG_CLOSE
1338         if (!buffs)
1339                 printk(KERN_DEBUG "Draining RX queue took %i cycles\n", i);
1340 #endif
1341
1342         buffs = TX_DESCS;
1343         while (queue_get_desc(TX_QUEUE(port->id), port, 1) >= 0)
1344                 buffs--; /* cancel TX */
1345
1346         i = 0;
1347         do {
1348                 while (queue_get_desc(port->plat->txreadyq, port, 1) >= 0)
1349                         buffs--;
1350                 if (!buffs)
1351                         break;
1352         } while (++i < MAX_CLOSE_WAIT);
1353
1354         if (buffs)
1355                 printk(KERN_CRIT "%s: unable to drain TX queue, %i buffer(s) "
1356                        "left in NPE\n", dev->name, buffs);
1357 #if DEBUG_CLOSE
1358         if (!buffs)
1359                 printk(KERN_DEBUG "Draining TX queues took %i cycles\n", i);
1360 #endif
1361
1362         msg.byte3 = 0;
1363         if (npe_send_recv_message(port->npe, &msg, "ETH_DISABLE_LOOPBACK"))
1364                 printk(KERN_CRIT "%s: unable to disable loopback\n",
1365                        dev->name);
1366
1367         phy_stop(dev->phydev);
1368
1369         if (!ports_open)
1370                 qmgr_disable_irq(TXDONE_QUEUE);
1371         destroy_queues(port);
1372         release_queues(port);
1373         return 0;
1374 }
1375
1376 static const struct net_device_ops ixp4xx_netdev_ops = {
1377         .ndo_open = eth_open,
1378         .ndo_stop = eth_close,
1379         .ndo_start_xmit = eth_xmit,
1380         .ndo_set_rx_mode = eth_set_mcast_list,
1381         .ndo_do_ioctl = eth_ioctl,
1382         .ndo_change_mtu = eth_change_mtu,
1383         .ndo_set_mac_address = eth_mac_addr,
1384         .ndo_validate_addr = eth_validate_addr,
1385 };
1386
1387 static int eth_init_one(struct platform_device *pdev)
1388 {
1389         struct port *port;
1390         struct net_device *dev;
1391         struct eth_plat_info *plat = dev_get_platdata(&pdev->dev);
1392         struct phy_device *phydev = NULL;
1393         u32 regs_phys;
1394         char phy_id[MII_BUS_ID_SIZE + 3];
1395         int err;
1396
1397         if (!(dev = alloc_etherdev(sizeof(struct port))))
1398                 return -ENOMEM;
1399
1400         SET_NETDEV_DEV(dev, &pdev->dev);
1401         port = netdev_priv(dev);
1402         port->netdev = dev;
1403         port->id = pdev->id;
1404
1405         switch (port->id) {
1406         case IXP4XX_ETH_NPEA:
1407                 port->regs = (struct eth_regs __iomem *)IXP4XX_EthA_BASE_VIRT;
1408                 regs_phys  = IXP4XX_EthA_BASE_PHYS;
1409                 break;
1410         case IXP4XX_ETH_NPEB:
1411                 port->regs = (struct eth_regs __iomem *)IXP4XX_EthB_BASE_VIRT;
1412                 regs_phys  = IXP4XX_EthB_BASE_PHYS;
1413                 break;
1414         case IXP4XX_ETH_NPEC:
1415                 port->regs = (struct eth_regs __iomem *)IXP4XX_EthC_BASE_VIRT;
1416                 regs_phys  = IXP4XX_EthC_BASE_PHYS;
1417                 break;
1418         default:
1419                 err = -ENODEV;
1420                 goto err_free;
1421         }
1422
1423         dev->netdev_ops = &ixp4xx_netdev_ops;
1424         dev->ethtool_ops = &ixp4xx_ethtool_ops;
1425         dev->tx_queue_len = 100;
1426
1427         netif_napi_add(dev, &port->napi, eth_poll, NAPI_WEIGHT);
1428
1429         if (!(port->npe = npe_request(NPE_ID(port->id)))) {
1430                 err = -EIO;
1431                 goto err_free;
1432         }
1433
1434         port->mem_res = request_mem_region(regs_phys, REGS_SIZE, dev->name);
1435         if (!port->mem_res) {
1436                 err = -EBUSY;
1437                 goto err_npe_rel;
1438         }
1439
1440         port->plat = plat;
1441         npe_port_tab[NPE_ID(port->id)] = port;
1442         memcpy(dev->dev_addr, plat->hwaddr, ETH_ALEN);
1443
1444         platform_set_drvdata(pdev, dev);
1445
1446         __raw_writel(DEFAULT_CORE_CNTRL | CORE_RESET,
1447                      &port->regs->core_control);
1448         udelay(50);
1449         __raw_writel(DEFAULT_CORE_CNTRL, &port->regs->core_control);
1450         udelay(50);
1451
1452         snprintf(phy_id, MII_BUS_ID_SIZE + 3, PHY_ID_FMT,
1453                 mdio_bus->id, plat->phy);
1454         phydev = phy_connect(dev, phy_id, &ixp4xx_adjust_link,
1455                              PHY_INTERFACE_MODE_MII);
1456         if (IS_ERR(phydev)) {
1457                 err = PTR_ERR(phydev);
1458                 goto err_free_mem;
1459         }
1460
1461         phydev->irq = PHY_POLL;
1462
1463         if ((err = register_netdev(dev)))
1464                 goto err_phy_dis;
1465
1466         printk(KERN_INFO "%s: MII PHY %i on %s\n", dev->name, plat->phy,
1467                npe_name(port->npe));
1468
1469         return 0;
1470
1471 err_phy_dis:
1472         phy_disconnect(phydev);
1473 err_free_mem:
1474         npe_port_tab[NPE_ID(port->id)] = NULL;
1475         release_resource(port->mem_res);
1476 err_npe_rel:
1477         npe_release(port->npe);
1478 err_free:
1479         free_netdev(dev);
1480         return err;
1481 }
1482
1483 static int eth_remove_one(struct platform_device *pdev)
1484 {
1485         struct net_device *dev = platform_get_drvdata(pdev);
1486         struct phy_device *phydev = dev->phydev;
1487         struct port *port = netdev_priv(dev);
1488
1489         unregister_netdev(dev);
1490         phy_disconnect(phydev);
1491         npe_port_tab[NPE_ID(port->id)] = NULL;
1492         npe_release(port->npe);
1493         release_resource(port->mem_res);
1494         free_netdev(dev);
1495         return 0;
1496 }
1497
1498 static struct platform_driver ixp4xx_eth_driver = {
1499         .driver.name    = DRV_NAME,
1500         .probe          = eth_init_one,
1501         .remove         = eth_remove_one,
1502 };
1503
1504 static int __init eth_init_module(void)
1505 {
1506         int err;
1507         if ((err = ixp4xx_mdio_register()))
1508                 return err;
1509         return platform_driver_register(&ixp4xx_eth_driver);
1510 }
1511
1512 static void __exit eth_cleanup_module(void)
1513 {
1514         platform_driver_unregister(&ixp4xx_eth_driver);
1515         ixp4xx_mdio_remove();
1516 }
1517
1518 MODULE_AUTHOR("Krzysztof Halasa");
1519 MODULE_DESCRIPTION("Intel IXP4xx Ethernet driver");
1520 MODULE_LICENSE("GPL v2");
1521 MODULE_ALIAS("platform:ixp4xx_eth");
1522 module_init(eth_init_module);
1523 module_exit(eth_cleanup_module);