1 // SPDX-License-Identifier: GPL-2.0
3 * Driver for the Texas Instruments DP83867 PHY
5 * Copyright (C) 2015 Texas Instruments Inc.
8 #include <linux/ethtool.h>
9 #include <linux/kernel.h>
10 #include <linux/mii.h>
11 #include <linux/module.h>
13 #include <linux/phy.h>
14 #include <linux/delay.h>
15 #include <linux/netdevice.h>
16 #include <linux/etherdevice.h>
18 #include <dt-bindings/net/ti-dp83867.h>
20 #define DP83867_PHY_ID 0x2000a231
21 #define DP83867_DEVADDR 0x1f
23 #define MII_DP83867_PHYCTRL 0x10
24 #define MII_DP83867_MICR 0x12
25 #define MII_DP83867_ISR 0x13
26 #define DP83867_CFG2 0x14
27 #define DP83867_CFG3 0x1e
28 #define DP83867_CTRL 0x1f
30 /* Extended Registers */
31 #define DP83867_CFG4 0x0031
32 #define DP83867_CFG4_SGMII_ANEG_MASK (BIT(5) | BIT(6))
33 #define DP83867_CFG4_SGMII_ANEG_TIMER_11MS (3 << 5)
34 #define DP83867_CFG4_SGMII_ANEG_TIMER_800US (2 << 5)
35 #define DP83867_CFG4_SGMII_ANEG_TIMER_2US (1 << 5)
36 #define DP83867_CFG4_SGMII_ANEG_TIMER_16MS (0 << 5)
38 #define DP83867_RGMIICTL 0x0032
39 #define DP83867_STRAP_STS1 0x006E
40 #define DP83867_STRAP_STS2 0x006f
41 #define DP83867_RGMIIDCTL 0x0086
42 #define DP83867_RXFCFG 0x0134
43 #define DP83867_RXFPMD1 0x0136
44 #define DP83867_RXFPMD2 0x0137
45 #define DP83867_RXFPMD3 0x0138
46 #define DP83867_RXFSOP1 0x0139
47 #define DP83867_RXFSOP2 0x013A
48 #define DP83867_RXFSOP3 0x013B
49 #define DP83867_IO_MUX_CFG 0x0170
50 #define DP83867_SGMIICTL 0x00D3
51 #define DP83867_10M_SGMII_CFG 0x016F
52 #define DP83867_10M_SGMII_RATE_ADAPT_MASK BIT(7)
54 #define DP83867_SW_RESET BIT(15)
55 #define DP83867_SW_RESTART BIT(14)
57 /* MICR Interrupt bits */
58 #define MII_DP83867_MICR_AN_ERR_INT_EN BIT(15)
59 #define MII_DP83867_MICR_SPEED_CHNG_INT_EN BIT(14)
60 #define MII_DP83867_MICR_DUP_MODE_CHNG_INT_EN BIT(13)
61 #define MII_DP83867_MICR_PAGE_RXD_INT_EN BIT(12)
62 #define MII_DP83867_MICR_AUTONEG_COMP_INT_EN BIT(11)
63 #define MII_DP83867_MICR_LINK_STS_CHNG_INT_EN BIT(10)
64 #define MII_DP83867_MICR_FALSE_CARRIER_INT_EN BIT(8)
65 #define MII_DP83867_MICR_SLEEP_MODE_CHNG_INT_EN BIT(4)
66 #define MII_DP83867_MICR_WOL_INT_EN BIT(3)
67 #define MII_DP83867_MICR_XGMII_ERR_INT_EN BIT(2)
68 #define MII_DP83867_MICR_POL_CHNG_INT_EN BIT(1)
69 #define MII_DP83867_MICR_JABBER_INT_EN BIT(0)
72 #define DP83867_RGMII_TX_CLK_DELAY_EN BIT(1)
73 #define DP83867_RGMII_RX_CLK_DELAY_EN BIT(0)
76 #define DP83867_SGMII_TYPE BIT(14)
79 #define DP83867_WOL_MAGIC_EN BIT(0)
80 #define DP83867_WOL_BCAST_EN BIT(2)
81 #define DP83867_WOL_UCAST_EN BIT(4)
82 #define DP83867_WOL_SEC_EN BIT(5)
83 #define DP83867_WOL_ENH_MAC BIT(7)
86 #define DP83867_STRAP_STS1_RESERVED BIT(11)
89 #define DP83867_STRAP_STS2_CLK_SKEW_TX_MASK GENMASK(6, 4)
90 #define DP83867_STRAP_STS2_CLK_SKEW_TX_SHIFT 4
91 #define DP83867_STRAP_STS2_CLK_SKEW_RX_MASK GENMASK(2, 0)
92 #define DP83867_STRAP_STS2_CLK_SKEW_RX_SHIFT 0
93 #define DP83867_STRAP_STS2_CLK_SKEW_NONE BIT(2)
96 #define DP83867_PHYCR_FIFO_DEPTH_SHIFT 14
97 #define DP83867_PHYCR_FIFO_DEPTH_MAX 0x03
98 #define DP83867_PHYCR_FIFO_DEPTH_MASK GENMASK(15, 14)
99 #define DP83867_PHYCR_RESERVED_MASK BIT(11)
102 #define DP83867_RGMII_TX_CLK_DELAY_MAX 0xf
103 #define DP83867_RGMII_TX_CLK_DELAY_SHIFT 4
104 #define DP83867_RGMII_RX_CLK_DELAY_MAX 0xf
105 #define DP83867_RGMII_RX_CLK_DELAY_SHIFT 0
107 /* IO_MUX_CFG bits */
108 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MASK 0x1f
109 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX 0x0
110 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN 0x1f
111 #define DP83867_IO_MUX_CFG_CLK_O_DISABLE BIT(6)
112 #define DP83867_IO_MUX_CFG_CLK_O_SEL_MASK (0x1f << 8)
113 #define DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT 8
116 #define DP83867_CFG3_INT_OE BIT(7)
117 #define DP83867_CFG3_ROBUST_AUTO_MDIX BIT(9)
120 #define DP83867_CFG4_PORT_MIRROR_EN BIT(0)
123 DP83867_PORT_MIRROING_KEEP,
124 DP83867_PORT_MIRROING_EN,
125 DP83867_PORT_MIRROING_DIS,
128 struct dp83867_private {
134 bool rxctrl_strap_quirk;
137 bool sgmii_ref_clk_en;
140 static int dp83867_ack_interrupt(struct phy_device *phydev)
142 int err = phy_read(phydev, MII_DP83867_ISR);
150 static int dp83867_set_wol(struct phy_device *phydev,
151 struct ethtool_wolinfo *wol)
153 struct net_device *ndev = phydev->attached_dev;
154 u16 val_rxcfg, val_micr;
157 val_rxcfg = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_RXFCFG);
158 val_micr = phy_read(phydev, MII_DP83867_MICR);
160 if (wol->wolopts & (WAKE_MAGIC | WAKE_MAGICSECURE | WAKE_UCAST |
162 val_rxcfg |= DP83867_WOL_ENH_MAC;
163 val_micr |= MII_DP83867_MICR_WOL_INT_EN;
165 if (wol->wolopts & WAKE_MAGIC) {
166 mac = (u8 *)ndev->dev_addr;
168 if (!is_valid_ether_addr(mac))
171 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFPMD1,
172 (mac[1] << 8 | mac[0]));
173 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFPMD2,
174 (mac[3] << 8 | mac[2]));
175 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFPMD3,
176 (mac[5] << 8 | mac[4]));
178 val_rxcfg |= DP83867_WOL_MAGIC_EN;
180 val_rxcfg &= ~DP83867_WOL_MAGIC_EN;
183 if (wol->wolopts & WAKE_MAGICSECURE) {
184 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFSOP1,
185 (wol->sopass[1] << 8) | wol->sopass[0]);
186 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFSOP1,
187 (wol->sopass[3] << 8) | wol->sopass[2]);
188 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFSOP1,
189 (wol->sopass[5] << 8) | wol->sopass[4]);
191 val_rxcfg |= DP83867_WOL_SEC_EN;
193 val_rxcfg &= ~DP83867_WOL_SEC_EN;
196 if (wol->wolopts & WAKE_UCAST)
197 val_rxcfg |= DP83867_WOL_UCAST_EN;
199 val_rxcfg &= ~DP83867_WOL_UCAST_EN;
201 if (wol->wolopts & WAKE_BCAST)
202 val_rxcfg |= DP83867_WOL_BCAST_EN;
204 val_rxcfg &= ~DP83867_WOL_BCAST_EN;
206 val_rxcfg &= ~DP83867_WOL_ENH_MAC;
207 val_micr &= ~MII_DP83867_MICR_WOL_INT_EN;
210 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFCFG, val_rxcfg);
211 phy_write(phydev, MII_DP83867_MICR, val_micr);
216 static void dp83867_get_wol(struct phy_device *phydev,
217 struct ethtool_wolinfo *wol)
219 u16 value, sopass_val;
221 wol->supported = (WAKE_UCAST | WAKE_BCAST | WAKE_MAGIC |
225 value = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_RXFCFG);
227 if (value & DP83867_WOL_UCAST_EN)
228 wol->wolopts |= WAKE_UCAST;
230 if (value & DP83867_WOL_BCAST_EN)
231 wol->wolopts |= WAKE_BCAST;
233 if (value & DP83867_WOL_MAGIC_EN)
234 wol->wolopts |= WAKE_MAGIC;
236 if (value & DP83867_WOL_SEC_EN) {
237 sopass_val = phy_read_mmd(phydev, DP83867_DEVADDR,
239 wol->sopass[0] = (sopass_val & 0xff);
240 wol->sopass[1] = (sopass_val >> 8);
242 sopass_val = phy_read_mmd(phydev, DP83867_DEVADDR,
244 wol->sopass[2] = (sopass_val & 0xff);
245 wol->sopass[3] = (sopass_val >> 8);
247 sopass_val = phy_read_mmd(phydev, DP83867_DEVADDR,
249 wol->sopass[4] = (sopass_val & 0xff);
250 wol->sopass[5] = (sopass_val >> 8);
252 wol->wolopts |= WAKE_MAGICSECURE;
255 if (!(value & DP83867_WOL_ENH_MAC))
259 static int dp83867_config_intr(struct phy_device *phydev)
263 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
264 micr_status = phy_read(phydev, MII_DP83867_MICR);
269 (MII_DP83867_MICR_AN_ERR_INT_EN |
270 MII_DP83867_MICR_SPEED_CHNG_INT_EN |
271 MII_DP83867_MICR_AUTONEG_COMP_INT_EN |
272 MII_DP83867_MICR_LINK_STS_CHNG_INT_EN |
273 MII_DP83867_MICR_DUP_MODE_CHNG_INT_EN |
274 MII_DP83867_MICR_SLEEP_MODE_CHNG_INT_EN);
276 return phy_write(phydev, MII_DP83867_MICR, micr_status);
280 return phy_write(phydev, MII_DP83867_MICR, micr_status);
283 static int dp83867_config_port_mirroring(struct phy_device *phydev)
285 struct dp83867_private *dp83867 =
286 (struct dp83867_private *)phydev->priv;
288 if (dp83867->port_mirroring == DP83867_PORT_MIRROING_EN)
289 phy_set_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4,
290 DP83867_CFG4_PORT_MIRROR_EN);
292 phy_clear_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4,
293 DP83867_CFG4_PORT_MIRROR_EN);
297 #ifdef CONFIG_OF_MDIO
298 static int dp83867_of_init(struct phy_device *phydev)
300 struct dp83867_private *dp83867 = phydev->priv;
301 struct device *dev = &phydev->mdio.dev;
302 struct device_node *of_node = dev->of_node;
308 /* Optional configuration */
309 ret = of_property_read_u32(of_node, "ti,clk-output-sel",
310 &dp83867->clk_output_sel);
311 /* If not set, keep default */
313 dp83867->set_clk_output = true;
314 /* Valid values are 0 to DP83867_CLK_O_SEL_REF_CLK or
315 * DP83867_CLK_O_SEL_OFF.
317 if (dp83867->clk_output_sel > DP83867_CLK_O_SEL_REF_CLK &&
318 dp83867->clk_output_sel != DP83867_CLK_O_SEL_OFF) {
319 phydev_err(phydev, "ti,clk-output-sel value %u out of range\n",
320 dp83867->clk_output_sel);
325 if (of_property_read_bool(of_node, "ti,max-output-impedance"))
326 dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX;
327 else if (of_property_read_bool(of_node, "ti,min-output-impedance"))
328 dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN;
330 dp83867->io_impedance = -1; /* leave at default */
332 dp83867->rxctrl_strap_quirk = of_property_read_bool(of_node,
333 "ti,dp83867-rxctrl-strap-quirk");
335 dp83867->sgmii_ref_clk_en = of_property_read_bool(of_node,
336 "ti,sgmii-ref-clock-output-enable");
338 /* Existing behavior was to use default pin strapping delay in rgmii
339 * mode, but rgmii should have meant no delay. Warn existing users.
341 if (phydev->interface == PHY_INTERFACE_MODE_RGMII) {
342 const u16 val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_STRAP_STS2);
343 const u16 txskew = (val & DP83867_STRAP_STS2_CLK_SKEW_TX_MASK) >>
344 DP83867_STRAP_STS2_CLK_SKEW_TX_SHIFT;
345 const u16 rxskew = (val & DP83867_STRAP_STS2_CLK_SKEW_RX_MASK) >>
346 DP83867_STRAP_STS2_CLK_SKEW_RX_SHIFT;
348 if (txskew != DP83867_STRAP_STS2_CLK_SKEW_NONE ||
349 rxskew != DP83867_STRAP_STS2_CLK_SKEW_NONE)
351 "PHY has delays via pin strapping, but phy-mode = 'rgmii'\n"
352 "Should be 'rgmii-id' to use internal delays\n");
355 /* RX delay *must* be specified if internal delay of RX is used. */
356 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
357 phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) {
358 ret = of_property_read_u32(of_node, "ti,rx-internal-delay",
359 &dp83867->rx_id_delay);
361 phydev_err(phydev, "ti,rx-internal-delay must be specified\n");
364 if (dp83867->rx_id_delay > DP83867_RGMII_RX_CLK_DELAY_MAX) {
366 "ti,rx-internal-delay value of %u out of range\n",
367 dp83867->rx_id_delay);
372 /* TX delay *must* be specified if internal delay of RX is used. */
373 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
374 phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
375 ret = of_property_read_u32(of_node, "ti,tx-internal-delay",
376 &dp83867->tx_id_delay);
378 phydev_err(phydev, "ti,tx-internal-delay must be specified\n");
381 if (dp83867->tx_id_delay > DP83867_RGMII_TX_CLK_DELAY_MAX) {
383 "ti,tx-internal-delay value of %u out of range\n",
384 dp83867->tx_id_delay);
389 if (of_property_read_bool(of_node, "enet-phy-lane-swap"))
390 dp83867->port_mirroring = DP83867_PORT_MIRROING_EN;
392 if (of_property_read_bool(of_node, "enet-phy-lane-no-swap"))
393 dp83867->port_mirroring = DP83867_PORT_MIRROING_DIS;
395 ret = of_property_read_u32(of_node, "ti,fifo-depth",
396 &dp83867->fifo_depth);
399 "ti,fifo-depth property is required\n");
402 if (dp83867->fifo_depth > DP83867_PHYCR_FIFO_DEPTH_MAX) {
404 "ti,fifo-depth value %u out of range\n",
405 dp83867->fifo_depth);
411 static int dp83867_of_init(struct phy_device *phydev)
415 #endif /* CONFIG_OF_MDIO */
417 static int dp83867_probe(struct phy_device *phydev)
419 struct dp83867_private *dp83867;
421 dp83867 = devm_kzalloc(&phydev->mdio.dev, sizeof(*dp83867),
426 phydev->priv = dp83867;
428 return dp83867_of_init(phydev);
431 static int dp83867_config_init(struct phy_device *phydev)
433 struct dp83867_private *dp83867 = phydev->priv;
437 /* RX_DV/RX_CTRL strapped in mode 1 or mode 2 workaround */
438 if (dp83867->rxctrl_strap_quirk)
439 phy_clear_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4,
442 if (phy_interface_is_rgmii(phydev)) {
443 val = phy_read(phydev, MII_DP83867_PHYCTRL);
446 val &= ~DP83867_PHYCR_FIFO_DEPTH_MASK;
447 val |= (dp83867->fifo_depth << DP83867_PHYCR_FIFO_DEPTH_SHIFT);
449 /* The code below checks if "port mirroring" N/A MODE4 has been
450 * enabled during power on bootstrap.
452 * Such N/A mode enabled by mistake can put PHY IC in some
453 * internal testing mode and disable RGMII transmission.
455 * In this particular case one needs to check STRAP_STS1
456 * register's bit 11 (marked as RESERVED).
459 bs = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_STRAP_STS1);
460 if (bs & DP83867_STRAP_STS1_RESERVED)
461 val &= ~DP83867_PHYCR_RESERVED_MASK;
463 ret = phy_write(phydev, MII_DP83867_PHYCTRL, val);
467 /* If rgmii mode with no internal delay is selected, we do NOT use
468 * aligned mode as one might expect. Instead we use the PHY's default
469 * based on pin strapping. And the "mode 0" default is to *use*
470 * internal delay with a value of 7 (2.00 ns).
472 * Set up RGMII delays
474 val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIICTL);
476 val &= ~(DP83867_RGMII_TX_CLK_DELAY_EN | DP83867_RGMII_RX_CLK_DELAY_EN);
477 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
478 val |= (DP83867_RGMII_TX_CLK_DELAY_EN | DP83867_RGMII_RX_CLK_DELAY_EN);
480 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
481 val |= DP83867_RGMII_TX_CLK_DELAY_EN;
483 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
484 val |= DP83867_RGMII_RX_CLK_DELAY_EN;
486 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIICTL, val);
488 delay = (dp83867->rx_id_delay |
489 (dp83867->tx_id_delay << DP83867_RGMII_TX_CLK_DELAY_SHIFT));
491 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIIDCTL,
495 /* If specified, set io impedance */
496 if (dp83867->io_impedance >= 0)
497 phy_modify_mmd(phydev, DP83867_DEVADDR, DP83867_IO_MUX_CFG,
498 DP83867_IO_MUX_CFG_IO_IMPEDANCE_MASK,
499 dp83867->io_impedance);
501 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
502 /* For support SPEED_10 in SGMII mode
503 * DP83867_10M_SGMII_RATE_ADAPT bit
504 * has to be cleared by software. That
505 * does not affect SPEED_100 and
508 ret = phy_modify_mmd(phydev, DP83867_DEVADDR,
509 DP83867_10M_SGMII_CFG,
510 DP83867_10M_SGMII_RATE_ADAPT_MASK,
515 /* After reset SGMII Autoneg timer is set to 2us (bits 6 and 5
516 * are 01). That is not enough to finalize autoneg on some
517 * devices. Increase this timer duration to maximum 16ms.
519 ret = phy_modify_mmd(phydev, DP83867_DEVADDR,
521 DP83867_CFG4_SGMII_ANEG_MASK,
522 DP83867_CFG4_SGMII_ANEG_TIMER_16MS);
527 val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_SGMIICTL);
528 /* SGMII type is set to 4-wire mode by default.
529 * If we place appropriate property in dts (see above)
530 * switch on 6-wire mode.
532 if (dp83867->sgmii_ref_clk_en)
533 val |= DP83867_SGMII_TYPE;
535 val &= ~DP83867_SGMII_TYPE;
536 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_SGMIICTL, val);
539 val = phy_read(phydev, DP83867_CFG3);
540 /* Enable Interrupt output INT_OE in CFG3 register */
541 if (phy_interrupt_is_valid(phydev))
542 val |= DP83867_CFG3_INT_OE;
544 val |= DP83867_CFG3_ROBUST_AUTO_MDIX;
545 phy_write(phydev, DP83867_CFG3, val);
547 if (dp83867->port_mirroring != DP83867_PORT_MIRROING_KEEP)
548 dp83867_config_port_mirroring(phydev);
550 /* Clock output selection if muxing property is set */
551 if (dp83867->set_clk_output) {
552 u16 mask = DP83867_IO_MUX_CFG_CLK_O_DISABLE;
554 if (dp83867->clk_output_sel == DP83867_CLK_O_SEL_OFF) {
555 val = DP83867_IO_MUX_CFG_CLK_O_DISABLE;
557 mask |= DP83867_IO_MUX_CFG_CLK_O_SEL_MASK;
558 val = dp83867->clk_output_sel <<
559 DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT;
562 phy_modify_mmd(phydev, DP83867_DEVADDR, DP83867_IO_MUX_CFG,
569 static int dp83867_phy_reset(struct phy_device *phydev)
573 err = phy_write(phydev, DP83867_CTRL, DP83867_SW_RESET);
577 usleep_range(10, 20);
582 static struct phy_driver dp83867_driver[] = {
584 .phy_id = DP83867_PHY_ID,
585 .phy_id_mask = 0xfffffff0,
586 .name = "TI DP83867",
587 /* PHY_GBIT_FEATURES */
589 .probe = dp83867_probe,
590 .config_init = dp83867_config_init,
591 .soft_reset = dp83867_phy_reset,
593 .get_wol = dp83867_get_wol,
594 .set_wol = dp83867_set_wol,
597 .ack_interrupt = dp83867_ack_interrupt,
598 .config_intr = dp83867_config_intr,
600 .suspend = genphy_suspend,
601 .resume = genphy_resume,
604 module_phy_driver(dp83867_driver);
606 static struct mdio_device_id __maybe_unused dp83867_tbl[] = {
607 { DP83867_PHY_ID, 0xfffffff0 },
611 MODULE_DEVICE_TABLE(mdio, dp83867_tbl);
613 MODULE_DESCRIPTION("Texas Instruments DP83867 PHY driver");
614 MODULE_AUTHOR("Dan Murphy <dmurphy@ti.com");
615 MODULE_LICENSE("GPL v2");