2 * drivers/net/phy/marvell.c
4 * Driver for Marvell PHYs
8 * Copyright (c) 2004 Freescale Semiconductor, Inc.
10 * Copyright (c) 2013 Michael Stapelberg <michael@stapelberg.de>
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the
14 * Free Software Foundation; either version 2 of the License, or (at your
15 * option) any later version.
18 #include <linux/kernel.h>
19 #include <linux/string.h>
20 #include <linux/ctype.h>
21 #include <linux/errno.h>
22 #include <linux/unistd.h>
23 #include <linux/hwmon.h>
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/netdevice.h>
28 #include <linux/etherdevice.h>
29 #include <linux/skbuff.h>
30 #include <linux/spinlock.h>
32 #include <linux/module.h>
33 #include <linux/mii.h>
34 #include <linux/ethtool.h>
35 #include <linux/phy.h>
36 #include <linux/marvell_phy.h>
41 #include <linux/uaccess.h>
43 #define MII_MARVELL_PHY_PAGE 22
44 #define MII_MARVELL_COPPER_PAGE 0x00
45 #define MII_MARVELL_FIBER_PAGE 0x01
46 #define MII_MARVELL_MSCR_PAGE 0x02
47 #define MII_MARVELL_LED_PAGE 0x03
48 #define MII_MARVELL_MISC_TEST_PAGE 0x06
49 #define MII_MARVELL_WOL_PAGE 0x11
51 #define MII_M1011_IEVENT 0x13
52 #define MII_M1011_IEVENT_CLEAR 0x0000
54 #define MII_M1011_IMASK 0x12
55 #define MII_M1011_IMASK_INIT 0x6400
56 #define MII_M1011_IMASK_CLEAR 0x0000
58 #define MII_M1011_PHY_SCR 0x10
59 #define MII_M1011_PHY_SCR_MDI 0x0000
60 #define MII_M1011_PHY_SCR_MDI_X 0x0020
61 #define MII_M1011_PHY_SCR_AUTO_CROSS 0x0060
63 #define MII_M1111_PHY_LED_CONTROL 0x18
64 #define MII_M1111_PHY_LED_DIRECT 0x4100
65 #define MII_M1111_PHY_LED_COMBINE 0x411c
66 #define MII_M1111_PHY_EXT_CR 0x14
67 #define MII_M1111_RGMII_RX_DELAY BIT(7)
68 #define MII_M1111_RGMII_TX_DELAY BIT(1)
69 #define MII_M1111_PHY_EXT_SR 0x1b
71 #define MII_M1111_HWCFG_MODE_MASK 0xf
72 #define MII_M1111_HWCFG_MODE_FIBER_RGMII 0x3
73 #define MII_M1111_HWCFG_MODE_SGMII_NO_CLK 0x4
74 #define MII_M1111_HWCFG_MODE_RTBI 0x7
75 #define MII_M1111_HWCFG_MODE_COPPER_RTBI 0x9
76 #define MII_M1111_HWCFG_MODE_COPPER_RGMII 0xb
77 #define MII_M1111_HWCFG_FIBER_COPPER_RES BIT(13)
78 #define MII_M1111_HWCFG_FIBER_COPPER_AUTO BIT(15)
80 #define MII_88E1121_PHY_MSCR_REG 21
81 #define MII_88E1121_PHY_MSCR_RX_DELAY BIT(5)
82 #define MII_88E1121_PHY_MSCR_TX_DELAY BIT(4)
83 #define MII_88E1121_PHY_MSCR_DELAY_MASK (~(0x3 << 4))
85 #define MII_88E1121_MISC_TEST 0x1a
86 #define MII_88E1510_MISC_TEST_TEMP_THRESHOLD_MASK 0x1f00
87 #define MII_88E1510_MISC_TEST_TEMP_THRESHOLD_SHIFT 8
88 #define MII_88E1510_MISC_TEST_TEMP_IRQ_EN BIT(7)
89 #define MII_88E1510_MISC_TEST_TEMP_IRQ BIT(6)
90 #define MII_88E1121_MISC_TEST_TEMP_SENSOR_EN BIT(5)
91 #define MII_88E1121_MISC_TEST_TEMP_MASK 0x1f
93 #define MII_88E1510_TEMP_SENSOR 0x1b
94 #define MII_88E1510_TEMP_SENSOR_MASK 0xff
96 #define MII_88E1318S_PHY_MSCR1_REG 16
97 #define MII_88E1318S_PHY_MSCR1_PAD_ODD BIT(6)
99 /* Copper Specific Interrupt Enable Register */
100 #define MII_88E1318S_PHY_CSIER 0x12
101 /* WOL Event Interrupt Enable */
102 #define MII_88E1318S_PHY_CSIER_WOL_EIE BIT(7)
104 /* LED Timer Control Register */
105 #define MII_88E1318S_PHY_LED_TCR 0x12
106 #define MII_88E1318S_PHY_LED_TCR_FORCE_INT BIT(15)
107 #define MII_88E1318S_PHY_LED_TCR_INTn_ENABLE BIT(7)
108 #define MII_88E1318S_PHY_LED_TCR_INT_ACTIVE_LOW BIT(11)
110 /* Magic Packet MAC address registers */
111 #define MII_88E1318S_PHY_MAGIC_PACKET_WORD2 0x17
112 #define MII_88E1318S_PHY_MAGIC_PACKET_WORD1 0x18
113 #define MII_88E1318S_PHY_MAGIC_PACKET_WORD0 0x19
115 #define MII_88E1318S_PHY_WOL_CTRL 0x10
116 #define MII_88E1318S_PHY_WOL_CTRL_CLEAR_WOL_STATUS BIT(12)
117 #define MII_88E1318S_PHY_WOL_CTRL_MAGIC_PACKET_MATCH_ENABLE BIT(14)
119 #define MII_88E1121_PHY_LED_CTRL 16
120 #define MII_88E1121_PHY_LED_DEF 0x0030
122 #define MII_M1011_PHY_STATUS 0x11
123 #define MII_M1011_PHY_STATUS_1000 0x8000
124 #define MII_M1011_PHY_STATUS_100 0x4000
125 #define MII_M1011_PHY_STATUS_SPD_MASK 0xc000
126 #define MII_M1011_PHY_STATUS_FULLDUPLEX 0x2000
127 #define MII_M1011_PHY_STATUS_RESOLVED 0x0800
128 #define MII_M1011_PHY_STATUS_LINK 0x0400
130 #define MII_M1116R_CONTROL_REG_MAC 21
132 #define MII_88E3016_PHY_SPEC_CTRL 0x10
133 #define MII_88E3016_DISABLE_SCRAMBLER 0x0200
134 #define MII_88E3016_AUTO_MDIX_CROSSOVER 0x0030
136 #define MII_88E1510_GEN_CTRL_REG_1 0x14
137 #define MII_88E1510_GEN_CTRL_REG_1_MODE_MASK 0x7
138 #define MII_88E1510_GEN_CTRL_REG_1_MODE_SGMII 0x1 /* SGMII to copper */
139 #define MII_88E1510_GEN_CTRL_REG_1_RESET 0x8000 /* Soft reset */
141 #define LPA_FIBER_1000HALF 0x40
142 #define LPA_FIBER_1000FULL 0x20
144 #define LPA_PAUSE_FIBER 0x180
145 #define LPA_PAUSE_ASYM_FIBER 0x100
147 #define ADVERTISE_FIBER_1000HALF 0x40
148 #define ADVERTISE_FIBER_1000FULL 0x20
150 #define ADVERTISE_PAUSE_FIBER 0x180
151 #define ADVERTISE_PAUSE_ASYM_FIBER 0x100
153 #define REGISTER_LINK_STATUS 0x400
154 #define NB_FIBER_STATS 1
156 MODULE_DESCRIPTION("Marvell PHY driver");
157 MODULE_AUTHOR("Andy Fleming");
158 MODULE_LICENSE("GPL");
160 struct marvell_hw_stat {
167 static struct marvell_hw_stat marvell_hw_stats[] = {
168 { "phy_receive_errors_copper", 0, 21, 16},
169 { "phy_idle_errors", 0, 10, 8 },
170 { "phy_receive_errors_fiber", 1, 21, 16},
173 struct marvell_priv {
174 u64 stats[ARRAY_SIZE(marvell_hw_stats)];
176 struct device *hwmon_dev;
179 static int marvell_get_page(struct phy_device *phydev)
181 return phy_read(phydev, MII_MARVELL_PHY_PAGE);
184 static int marvell_set_page(struct phy_device *phydev, int page)
186 return phy_write(phydev, MII_MARVELL_PHY_PAGE, page);
189 static int marvell_get_set_page(struct phy_device *phydev, int page)
191 int oldpage = marvell_get_page(phydev);
197 return marvell_set_page(phydev, page);
202 static int marvell_ack_interrupt(struct phy_device *phydev)
206 /* Clear the interrupts by reading the reg */
207 err = phy_read(phydev, MII_M1011_IEVENT);
215 static int marvell_config_intr(struct phy_device *phydev)
219 if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
220 err = phy_write(phydev, MII_M1011_IMASK,
221 MII_M1011_IMASK_INIT);
223 err = phy_write(phydev, MII_M1011_IMASK,
224 MII_M1011_IMASK_CLEAR);
229 static int marvell_set_polarity(struct phy_device *phydev, int polarity)
235 /* get the current settings */
236 reg = phy_read(phydev, MII_M1011_PHY_SCR);
241 val &= ~MII_M1011_PHY_SCR_AUTO_CROSS;
244 val |= MII_M1011_PHY_SCR_MDI;
247 val |= MII_M1011_PHY_SCR_MDI_X;
249 case ETH_TP_MDI_AUTO:
250 case ETH_TP_MDI_INVALID:
252 val |= MII_M1011_PHY_SCR_AUTO_CROSS;
257 /* Set the new polarity value in the register */
258 err = phy_write(phydev, MII_M1011_PHY_SCR, val);
266 static int marvell_config_aneg(struct phy_device *phydev)
270 err = marvell_set_polarity(phydev, phydev->mdix_ctrl);
274 err = phy_write(phydev, MII_M1111_PHY_LED_CONTROL,
275 MII_M1111_PHY_LED_DIRECT);
279 err = genphy_config_aneg(phydev);
283 if (phydev->autoneg != AUTONEG_ENABLE) {
284 /* A write to speed/duplex bits (that is performed by
285 * genphy_config_aneg() call above) must be followed by
286 * a software reset. Otherwise, the write has no effect.
288 err = genphy_soft_reset(phydev);
296 static int m88e1101_config_aneg(struct phy_device *phydev)
300 /* This Marvell PHY has an errata which requires
301 * that certain registers get written in order
302 * to restart autonegotiation
304 err = genphy_soft_reset(phydev);
308 err = phy_write(phydev, 0x1d, 0x1f);
312 err = phy_write(phydev, 0x1e, 0x200c);
316 err = phy_write(phydev, 0x1d, 0x5);
320 err = phy_write(phydev, 0x1e, 0);
324 err = phy_write(phydev, 0x1e, 0x100);
328 return marvell_config_aneg(phydev);
331 static int m88e1111_config_aneg(struct phy_device *phydev)
335 /* The Marvell PHY has an errata which requires
336 * that certain registers get written in order
337 * to restart autonegotiation
339 err = genphy_soft_reset(phydev);
341 err = marvell_set_polarity(phydev, phydev->mdix_ctrl);
345 err = phy_write(phydev, MII_M1111_PHY_LED_CONTROL,
346 MII_M1111_PHY_LED_DIRECT);
350 err = genphy_config_aneg(phydev);
354 if (phydev->autoneg != AUTONEG_ENABLE) {
355 /* A write to speed/duplex bits (that is performed by
356 * genphy_config_aneg() call above) must be followed by
357 * a software reset. Otherwise, the write has no effect.
359 err = genphy_soft_reset(phydev);
367 #ifdef CONFIG_OF_MDIO
368 /* Set and/or override some configuration registers based on the
369 * marvell,reg-init property stored in the of_node for the phydev.
371 * marvell,reg-init = <reg-page reg mask value>,...;
373 * There may be one or more sets of <reg-page reg mask value>:
375 * reg-page: which register bank to use.
377 * mask: if non-zero, ANDed with existing register value.
378 * value: ORed with the masked value and written to the regiser.
381 static int marvell_of_reg_init(struct phy_device *phydev)
384 int len, i, saved_page, current_page, ret;
386 if (!phydev->mdio.dev.of_node)
389 paddr = of_get_property(phydev->mdio.dev.of_node,
390 "marvell,reg-init", &len);
391 if (!paddr || len < (4 * sizeof(*paddr)))
394 saved_page = marvell_get_page(phydev);
397 current_page = saved_page;
400 len /= sizeof(*paddr);
401 for (i = 0; i < len - 3; i += 4) {
402 u16 page = be32_to_cpup(paddr + i);
403 u16 reg = be32_to_cpup(paddr + i + 1);
404 u16 mask = be32_to_cpup(paddr + i + 2);
405 u16 val_bits = be32_to_cpup(paddr + i + 3);
408 if (page != current_page) {
410 ret = marvell_set_page(phydev, page);
417 val = phy_read(phydev, reg);
426 ret = phy_write(phydev, reg, val);
431 if (current_page != saved_page) {
432 i = marvell_set_page(phydev, saved_page);
439 static int marvell_of_reg_init(struct phy_device *phydev)
443 #endif /* CONFIG_OF_MDIO */
445 static int m88e1121_config_aneg(struct phy_device *phydev)
447 int err, oldpage, mscr;
449 oldpage = marvell_get_set_page(phydev, MII_MARVELL_MSCR_PAGE);
453 if (phy_interface_is_rgmii(phydev)) {
454 mscr = phy_read(phydev, MII_88E1121_PHY_MSCR_REG) &
455 MII_88E1121_PHY_MSCR_DELAY_MASK;
457 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
458 mscr |= (MII_88E1121_PHY_MSCR_RX_DELAY |
459 MII_88E1121_PHY_MSCR_TX_DELAY);
460 else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
461 mscr |= MII_88E1121_PHY_MSCR_RX_DELAY;
462 else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
463 mscr |= MII_88E1121_PHY_MSCR_TX_DELAY;
465 err = phy_write(phydev, MII_88E1121_PHY_MSCR_REG, mscr);
470 marvell_set_page(phydev, oldpage);
472 err = genphy_soft_reset(phydev);
476 err = phy_write(phydev, MII_M1011_PHY_SCR,
477 MII_M1011_PHY_SCR_AUTO_CROSS);
481 return genphy_config_aneg(phydev);
484 static int m88e1318_config_aneg(struct phy_device *phydev)
486 int err, oldpage, mscr;
488 oldpage = marvell_get_set_page(phydev, MII_MARVELL_MSCR_PAGE);
492 mscr = phy_read(phydev, MII_88E1318S_PHY_MSCR1_REG);
493 mscr |= MII_88E1318S_PHY_MSCR1_PAD_ODD;
495 err = phy_write(phydev, MII_88E1318S_PHY_MSCR1_REG, mscr);
499 err = marvell_set_page(phydev, oldpage);
503 return m88e1121_config_aneg(phydev);
507 * ethtool_adv_to_fiber_adv_t
508 * @ethadv: the ethtool advertisement settings
510 * A small helper function that translates ethtool advertisement
511 * settings to phy autonegotiation advertisements for the
512 * MII_ADV register for fiber link.
514 static inline u32 ethtool_adv_to_fiber_adv_t(u32 ethadv)
518 if (ethadv & ADVERTISED_1000baseT_Half)
519 result |= ADVERTISE_FIBER_1000HALF;
520 if (ethadv & ADVERTISED_1000baseT_Full)
521 result |= ADVERTISE_FIBER_1000FULL;
523 if ((ethadv & ADVERTISE_PAUSE_ASYM) && (ethadv & ADVERTISE_PAUSE_CAP))
524 result |= LPA_PAUSE_ASYM_FIBER;
525 else if (ethadv & ADVERTISE_PAUSE_CAP)
526 result |= (ADVERTISE_PAUSE_FIBER
527 & (~ADVERTISE_PAUSE_ASYM_FIBER));
533 * marvell_config_aneg_fiber - restart auto-negotiation or write BMCR
534 * @phydev: target phy_device struct
536 * Description: If auto-negotiation is enabled, we configure the
537 * advertising, and then restart auto-negotiation. If it is not
538 * enabled, then we write the BMCR. Adapted for fiber link in
539 * some Marvell's devices.
541 static int marvell_config_aneg_fiber(struct phy_device *phydev)
548 if (phydev->autoneg != AUTONEG_ENABLE)
549 return genphy_setup_forced(phydev);
551 /* Only allow advertising what this PHY supports */
552 phydev->advertising &= phydev->supported;
553 advertise = phydev->advertising;
555 /* Setup fiber advertisement */
556 adv = phy_read(phydev, MII_ADVERTISE);
561 adv &= ~(ADVERTISE_FIBER_1000HALF | ADVERTISE_FIBER_1000FULL
563 adv |= ethtool_adv_to_fiber_adv_t(advertise);
566 err = phy_write(phydev, MII_ADVERTISE, adv);
574 /* Advertisement hasn't changed, but maybe aneg was never on to
575 * begin with? Or maybe phy was isolated?
577 int ctl = phy_read(phydev, MII_BMCR);
582 if (!(ctl & BMCR_ANENABLE) || (ctl & BMCR_ISOLATE))
583 changed = 1; /* do restart aneg */
586 /* Only restart aneg if we are advertising something different
587 * than we were before.
590 changed = genphy_restart_aneg(phydev);
595 static int m88e1510_config_aneg(struct phy_device *phydev)
599 err = marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
603 /* Configure the copper link first */
604 err = m88e1318_config_aneg(phydev);
608 /* Then the fiber link */
609 err = marvell_set_page(phydev, MII_MARVELL_FIBER_PAGE);
613 err = marvell_config_aneg_fiber(phydev);
617 return marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
620 marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
624 static int marvell_config_init(struct phy_device *phydev)
626 /* Set registers from marvell,reg-init DT property */
627 return marvell_of_reg_init(phydev);
630 static int m88e1116r_config_init(struct phy_device *phydev)
635 err = genphy_soft_reset(phydev);
641 err = marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
645 temp = phy_read(phydev, MII_M1011_PHY_SCR);
646 temp |= (7 << 12); /* max number of gigabit attempts */
647 temp |= (1 << 11); /* enable downshift */
648 temp |= MII_M1011_PHY_SCR_AUTO_CROSS;
649 err = phy_write(phydev, MII_M1011_PHY_SCR, temp);
653 err = marvell_set_page(phydev, MII_MARVELL_MSCR_PAGE);
656 temp = phy_read(phydev, MII_M1116R_CONTROL_REG_MAC);
659 err = phy_write(phydev, MII_M1116R_CONTROL_REG_MAC, temp);
662 err = marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
666 err = genphy_soft_reset(phydev);
670 return marvell_config_init(phydev);
673 static int m88e3016_config_init(struct phy_device *phydev)
677 /* Enable Scrambler and Auto-Crossover */
678 reg = phy_read(phydev, MII_88E3016_PHY_SPEC_CTRL);
682 reg &= ~MII_88E3016_DISABLE_SCRAMBLER;
683 reg |= MII_88E3016_AUTO_MDIX_CROSSOVER;
685 reg = phy_write(phydev, MII_88E3016_PHY_SPEC_CTRL, reg);
689 return marvell_config_init(phydev);
692 static int m88e1111_config_init_hwcfg_mode(struct phy_device *phydev,
694 int fibre_copper_auto)
698 temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
702 temp &= ~(MII_M1111_HWCFG_MODE_MASK |
703 MII_M1111_HWCFG_FIBER_COPPER_AUTO |
704 MII_M1111_HWCFG_FIBER_COPPER_RES);
707 if (fibre_copper_auto)
708 temp |= MII_M1111_HWCFG_FIBER_COPPER_AUTO;
710 return phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
713 static int m88e1111_config_init_rgmii_delays(struct phy_device *phydev)
717 temp = phy_read(phydev, MII_M1111_PHY_EXT_CR);
721 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) {
722 temp |= (MII_M1111_RGMII_RX_DELAY | MII_M1111_RGMII_TX_DELAY);
723 } else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) {
724 temp &= ~MII_M1111_RGMII_TX_DELAY;
725 temp |= MII_M1111_RGMII_RX_DELAY;
726 } else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
727 temp &= ~MII_M1111_RGMII_RX_DELAY;
728 temp |= MII_M1111_RGMII_TX_DELAY;
731 return phy_write(phydev, MII_M1111_PHY_EXT_CR, temp);
734 static int m88e1111_config_init_rgmii(struct phy_device *phydev)
739 err = m88e1111_config_init_rgmii_delays(phydev);
743 temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
747 temp &= ~(MII_M1111_HWCFG_MODE_MASK);
749 if (temp & MII_M1111_HWCFG_FIBER_COPPER_RES)
750 temp |= MII_M1111_HWCFG_MODE_FIBER_RGMII;
752 temp |= MII_M1111_HWCFG_MODE_COPPER_RGMII;
754 return phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
757 static int m88e1111_config_init_sgmii(struct phy_device *phydev)
761 err = m88e1111_config_init_hwcfg_mode(
763 MII_M1111_HWCFG_MODE_SGMII_NO_CLK,
764 MII_M1111_HWCFG_FIBER_COPPER_AUTO);
768 /* make sure copper is selected */
769 return marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
772 static int m88e1111_config_init_rtbi(struct phy_device *phydev)
776 err = m88e1111_config_init_rgmii_delays(phydev);
780 err = m88e1111_config_init_hwcfg_mode(
782 MII_M1111_HWCFG_MODE_RTBI,
783 MII_M1111_HWCFG_FIBER_COPPER_AUTO);
788 err = genphy_soft_reset(phydev);
792 return m88e1111_config_init_hwcfg_mode(
794 MII_M1111_HWCFG_MODE_RTBI,
795 MII_M1111_HWCFG_FIBER_COPPER_AUTO);
798 static int m88e1111_config_init(struct phy_device *phydev)
802 if (phy_interface_is_rgmii(phydev)) {
803 err = m88e1111_config_init_rgmii(phydev);
808 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
809 err = m88e1111_config_init_sgmii(phydev);
814 if (phydev->interface == PHY_INTERFACE_MODE_RTBI) {
815 err = m88e1111_config_init_rtbi(phydev);
820 err = marvell_of_reg_init(phydev);
824 return genphy_soft_reset(phydev);
827 static int m88e1121_config_init(struct phy_device *phydev)
831 oldpage = marvell_get_set_page(phydev, MII_MARVELL_LED_PAGE);
835 /* Default PHY LED config: LED[0] .. Link, LED[1] .. Activity */
836 err = phy_write(phydev, MII_88E1121_PHY_LED_CTRL,
837 MII_88E1121_PHY_LED_DEF);
841 marvell_set_page(phydev, oldpage);
843 /* Set marvell,reg-init configuration from device tree */
844 return marvell_config_init(phydev);
847 static int m88e1510_config_init(struct phy_device *phydev)
852 /* SGMII-to-Copper mode initialization */
853 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
855 err = marvell_set_page(phydev, 18);
859 /* In reg 20, write MODE[2:0] = 0x1 (SGMII to Copper) */
860 temp = phy_read(phydev, MII_88E1510_GEN_CTRL_REG_1);
861 temp &= ~MII_88E1510_GEN_CTRL_REG_1_MODE_MASK;
862 temp |= MII_88E1510_GEN_CTRL_REG_1_MODE_SGMII;
863 err = phy_write(phydev, MII_88E1510_GEN_CTRL_REG_1, temp);
867 /* PHY reset is necessary after changing MODE[2:0] */
868 temp |= MII_88E1510_GEN_CTRL_REG_1_RESET;
869 err = phy_write(phydev, MII_88E1510_GEN_CTRL_REG_1, temp);
873 /* Reset page selection */
874 err = marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
879 return m88e1121_config_init(phydev);
882 static int m88e1118_config_aneg(struct phy_device *phydev)
886 err = genphy_soft_reset(phydev);
890 err = phy_write(phydev, MII_M1011_PHY_SCR,
891 MII_M1011_PHY_SCR_AUTO_CROSS);
895 err = genphy_config_aneg(phydev);
899 static int m88e1118_config_init(struct phy_device *phydev)
904 err = marvell_set_page(phydev, MII_MARVELL_MSCR_PAGE);
908 /* Enable 1000 Mbit */
909 err = phy_write(phydev, 0x15, 0x1070);
914 err = marvell_set_page(phydev, MII_MARVELL_LED_PAGE);
918 /* Adjust LED Control */
919 if (phydev->dev_flags & MARVELL_PHY_M1118_DNS323_LEDS)
920 err = phy_write(phydev, 0x10, 0x1100);
922 err = phy_write(phydev, 0x10, 0x021e);
926 err = marvell_of_reg_init(phydev);
931 err = marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
935 return genphy_soft_reset(phydev);
938 static int m88e1149_config_init(struct phy_device *phydev)
943 err = marvell_set_page(phydev, MII_MARVELL_MSCR_PAGE);
947 /* Enable 1000 Mbit */
948 err = phy_write(phydev, 0x15, 0x1048);
952 err = marvell_of_reg_init(phydev);
957 err = marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
961 return genphy_soft_reset(phydev);
964 static int m88e1145_config_init_rgmii(struct phy_device *phydev)
969 err = m88e1111_config_init_rgmii_delays(phydev);
973 if (phydev->dev_flags & MARVELL_PHY_M1145_FLAGS_RESISTANCE) {
974 err = phy_write(phydev, 0x1d, 0x0012);
978 temp = phy_read(phydev, 0x1e);
983 temp |= 2 << 9; /* 36 ohm */
984 temp |= 2 << 6; /* 39 ohm */
986 err = phy_write(phydev, 0x1e, temp);
990 err = phy_write(phydev, 0x1d, 0x3);
994 err = phy_write(phydev, 0x1e, 0x8000);
999 static int m88e1145_config_init_sgmii(struct phy_device *phydev)
1001 return m88e1111_config_init_hwcfg_mode(
1002 phydev, MII_M1111_HWCFG_MODE_SGMII_NO_CLK,
1003 MII_M1111_HWCFG_FIBER_COPPER_AUTO);
1006 static int m88e1145_config_init(struct phy_device *phydev)
1010 /* Take care of errata E0 & E1 */
1011 err = phy_write(phydev, 0x1d, 0x001b);
1015 err = phy_write(phydev, 0x1e, 0x418f);
1019 err = phy_write(phydev, 0x1d, 0x0016);
1023 err = phy_write(phydev, 0x1e, 0xa2da);
1027 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) {
1028 err = m88e1145_config_init_rgmii(phydev);
1033 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
1034 err = m88e1145_config_init_sgmii(phydev);
1039 err = marvell_of_reg_init(phydev);
1047 * fiber_lpa_to_ethtool_lpa_t
1048 * @lpa: value of the MII_LPA register for fiber link
1050 * A small helper function that translates MII_LPA
1051 * bits to ethtool LP advertisement settings.
1053 static u32 fiber_lpa_to_ethtool_lpa_t(u32 lpa)
1057 if (lpa & LPA_FIBER_1000HALF)
1058 result |= ADVERTISED_1000baseT_Half;
1059 if (lpa & LPA_FIBER_1000FULL)
1060 result |= ADVERTISED_1000baseT_Full;
1066 * marvell_update_link - update link status in real time in @phydev
1067 * @phydev: target phy_device struct
1069 * Description: Update the value in phydev->link to reflect the
1070 * current link value.
1072 static int marvell_update_link(struct phy_device *phydev, int fiber)
1076 /* Use the generic register for copper link, or specific
1077 * register for fiber case
1080 status = phy_read(phydev, MII_M1011_PHY_STATUS);
1084 if ((status & REGISTER_LINK_STATUS) == 0)
1089 return genphy_update_link(phydev);
1095 static int marvell_read_status_page_an(struct phy_device *phydev,
1102 status = phy_read(phydev, MII_M1011_PHY_STATUS);
1106 lpa = phy_read(phydev, MII_LPA);
1110 lpagb = phy_read(phydev, MII_STAT1000);
1114 if (status & MII_M1011_PHY_STATUS_FULLDUPLEX)
1115 phydev->duplex = DUPLEX_FULL;
1117 phydev->duplex = DUPLEX_HALF;
1119 status = status & MII_M1011_PHY_STATUS_SPD_MASK;
1121 phydev->asym_pause = 0;
1124 case MII_M1011_PHY_STATUS_1000:
1125 phydev->speed = SPEED_1000;
1128 case MII_M1011_PHY_STATUS_100:
1129 phydev->speed = SPEED_100;
1133 phydev->speed = SPEED_10;
1138 phydev->lp_advertising =
1139 mii_stat1000_to_ethtool_lpa_t(lpagb) |
1140 mii_lpa_to_ethtool_lpa_t(lpa);
1142 if (phydev->duplex == DUPLEX_FULL) {
1143 phydev->pause = lpa & LPA_PAUSE_CAP ? 1 : 0;
1144 phydev->asym_pause = lpa & LPA_PAUSE_ASYM ? 1 : 0;
1147 /* The fiber link is only 1000M capable */
1148 phydev->lp_advertising = fiber_lpa_to_ethtool_lpa_t(lpa);
1150 if (phydev->duplex == DUPLEX_FULL) {
1151 if (!(lpa & LPA_PAUSE_FIBER)) {
1153 phydev->asym_pause = 0;
1154 } else if ((lpa & LPA_PAUSE_ASYM_FIBER)) {
1156 phydev->asym_pause = 1;
1159 phydev->asym_pause = 0;
1166 static int marvell_read_status_page_fixed(struct phy_device *phydev)
1168 int bmcr = phy_read(phydev, MII_BMCR);
1173 if (bmcr & BMCR_FULLDPLX)
1174 phydev->duplex = DUPLEX_FULL;
1176 phydev->duplex = DUPLEX_HALF;
1178 if (bmcr & BMCR_SPEED1000)
1179 phydev->speed = SPEED_1000;
1180 else if (bmcr & BMCR_SPEED100)
1181 phydev->speed = SPEED_100;
1183 phydev->speed = SPEED_10;
1186 phydev->asym_pause = 0;
1187 phydev->lp_advertising = 0;
1192 /* marvell_read_status_page
1195 * Check the link, then figure out the current state
1196 * by comparing what we advertise with what the link partner
1197 * advertises. Start by checking the gigabit possibilities,
1198 * then move on to 10/100.
1200 static int marvell_read_status_page(struct phy_device *phydev, int page)
1205 /* Detect and update the link, but return if there
1208 if (page == MII_MARVELL_FIBER_PAGE)
1213 err = marvell_update_link(phydev, fiber);
1217 if (phydev->autoneg == AUTONEG_ENABLE)
1218 err = marvell_read_status_page_an(phydev, fiber);
1220 err = marvell_read_status_page_fixed(phydev);
1225 /* marvell_read_status
1227 * Some Marvell's phys have two modes: fiber and copper.
1228 * Both need status checked.
1230 * First, check the fiber link and status.
1231 * If the fiber link is down, check the copper link and status which
1232 * will be the default value if both link are down.
1234 static int marvell_read_status(struct phy_device *phydev)
1238 /* Check the fiber mode first */
1239 if (phydev->supported & SUPPORTED_FIBRE &&
1240 phydev->interface != PHY_INTERFACE_MODE_SGMII) {
1241 err = marvell_set_page(phydev, MII_MARVELL_FIBER_PAGE);
1245 err = marvell_read_status_page(phydev, MII_MARVELL_FIBER_PAGE);
1249 /* If the fiber link is up, it is the selected and
1250 * used link. In this case, we need to stay in the
1251 * fiber page. Please to be careful about that, avoid
1252 * to restore Copper page in other functions which
1253 * could break the behaviour for some fiber phy like
1259 /* If fiber link is down, check and save copper mode state */
1260 err = marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
1265 return marvell_read_status_page(phydev, MII_MARVELL_COPPER_PAGE);
1268 marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
1274 * Some Marvell's phys have two modes: fiber and copper.
1275 * Both need to be suspended
1277 static int marvell_suspend(struct phy_device *phydev)
1281 /* Suspend the fiber mode first */
1282 if (!(phydev->supported & SUPPORTED_FIBRE)) {
1283 err = marvell_set_page(phydev, MII_MARVELL_FIBER_PAGE);
1287 /* With the page set, use the generic suspend */
1288 err = genphy_suspend(phydev);
1292 /* Then, the copper link */
1293 err = marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
1298 /* With the page set, use the generic suspend */
1299 return genphy_suspend(phydev);
1302 marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
1308 * Some Marvell's phys have two modes: fiber and copper.
1309 * Both need to be resumed
1311 static int marvell_resume(struct phy_device *phydev)
1315 /* Resume the fiber mode first */
1316 if (!(phydev->supported & SUPPORTED_FIBRE)) {
1317 err = marvell_set_page(phydev, MII_MARVELL_FIBER_PAGE);
1321 /* With the page set, use the generic resume */
1322 err = genphy_resume(phydev);
1326 /* Then, the copper link */
1327 err = marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
1332 /* With the page set, use the generic resume */
1333 return genphy_resume(phydev);
1336 marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
1340 static int marvell_aneg_done(struct phy_device *phydev)
1342 int retval = phy_read(phydev, MII_M1011_PHY_STATUS);
1344 return (retval < 0) ? retval : (retval & MII_M1011_PHY_STATUS_RESOLVED);
1347 static int m88e1121_did_interrupt(struct phy_device *phydev)
1351 imask = phy_read(phydev, MII_M1011_IEVENT);
1353 if (imask & MII_M1011_IMASK_INIT)
1359 static void m88e1318_get_wol(struct phy_device *phydev,
1360 struct ethtool_wolinfo *wol)
1362 wol->supported = WAKE_MAGIC;
1365 if (marvell_set_page(phydev, MII_MARVELL_WOL_PAGE) < 0)
1368 if (phy_read(phydev, MII_88E1318S_PHY_WOL_CTRL) &
1369 MII_88E1318S_PHY_WOL_CTRL_MAGIC_PACKET_MATCH_ENABLE)
1370 wol->wolopts |= WAKE_MAGIC;
1372 if (marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE) < 0)
1376 static int m88e1318_set_wol(struct phy_device *phydev,
1377 struct ethtool_wolinfo *wol)
1379 int err, oldpage, temp;
1381 oldpage = marvell_get_page(phydev);
1383 if (wol->wolopts & WAKE_MAGIC) {
1384 /* Explicitly switch to page 0x00, just to be sure */
1385 err = marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
1389 /* Enable the WOL interrupt */
1390 temp = phy_read(phydev, MII_88E1318S_PHY_CSIER);
1391 temp |= MII_88E1318S_PHY_CSIER_WOL_EIE;
1392 err = phy_write(phydev, MII_88E1318S_PHY_CSIER, temp);
1396 err = marvell_set_page(phydev, MII_MARVELL_LED_PAGE);
1400 /* Setup LED[2] as interrupt pin (active low) */
1401 temp = phy_read(phydev, MII_88E1318S_PHY_LED_TCR);
1402 temp &= ~MII_88E1318S_PHY_LED_TCR_FORCE_INT;
1403 temp |= MII_88E1318S_PHY_LED_TCR_INTn_ENABLE;
1404 temp |= MII_88E1318S_PHY_LED_TCR_INT_ACTIVE_LOW;
1405 err = phy_write(phydev, MII_88E1318S_PHY_LED_TCR, temp);
1409 err = marvell_set_page(phydev, MII_MARVELL_WOL_PAGE);
1413 /* Store the device address for the magic packet */
1414 err = phy_write(phydev, MII_88E1318S_PHY_MAGIC_PACKET_WORD2,
1415 ((phydev->attached_dev->dev_addr[5] << 8) |
1416 phydev->attached_dev->dev_addr[4]));
1419 err = phy_write(phydev, MII_88E1318S_PHY_MAGIC_PACKET_WORD1,
1420 ((phydev->attached_dev->dev_addr[3] << 8) |
1421 phydev->attached_dev->dev_addr[2]));
1424 err = phy_write(phydev, MII_88E1318S_PHY_MAGIC_PACKET_WORD0,
1425 ((phydev->attached_dev->dev_addr[1] << 8) |
1426 phydev->attached_dev->dev_addr[0]));
1430 /* Clear WOL status and enable magic packet matching */
1431 temp = phy_read(phydev, MII_88E1318S_PHY_WOL_CTRL);
1432 temp |= MII_88E1318S_PHY_WOL_CTRL_CLEAR_WOL_STATUS;
1433 temp |= MII_88E1318S_PHY_WOL_CTRL_MAGIC_PACKET_MATCH_ENABLE;
1434 err = phy_write(phydev, MII_88E1318S_PHY_WOL_CTRL, temp);
1438 err = marvell_set_page(phydev, MII_MARVELL_WOL_PAGE);
1442 /* Clear WOL status and disable magic packet matching */
1443 temp = phy_read(phydev, MII_88E1318S_PHY_WOL_CTRL);
1444 temp |= MII_88E1318S_PHY_WOL_CTRL_CLEAR_WOL_STATUS;
1445 temp &= ~MII_88E1318S_PHY_WOL_CTRL_MAGIC_PACKET_MATCH_ENABLE;
1446 err = phy_write(phydev, MII_88E1318S_PHY_WOL_CTRL, temp);
1451 err = marvell_set_page(phydev, oldpage);
1458 static int marvell_get_sset_count(struct phy_device *phydev)
1460 if (phydev->supported & SUPPORTED_FIBRE)
1461 return ARRAY_SIZE(marvell_hw_stats);
1463 return ARRAY_SIZE(marvell_hw_stats) - NB_FIBER_STATS;
1466 static void marvell_get_strings(struct phy_device *phydev, u8 *data)
1470 for (i = 0; i < ARRAY_SIZE(marvell_hw_stats); i++) {
1471 memcpy(data + i * ETH_GSTRING_LEN,
1472 marvell_hw_stats[i].string, ETH_GSTRING_LEN);
1477 #define UINT64_MAX (u64)(~((u64)0))
1479 static u64 marvell_get_stat(struct phy_device *phydev, int i)
1481 struct marvell_hw_stat stat = marvell_hw_stats[i];
1482 struct marvell_priv *priv = phydev->priv;
1486 oldpage = marvell_get_set_page(phydev, stat.page);
1490 val = phy_read(phydev, stat.reg);
1494 val = val & ((1 << stat.bits) - 1);
1495 priv->stats[i] += val;
1496 ret = priv->stats[i];
1499 marvell_set_page(phydev, oldpage);
1504 static void marvell_get_stats(struct phy_device *phydev,
1505 struct ethtool_stats *stats, u64 *data)
1509 for (i = 0; i < ARRAY_SIZE(marvell_hw_stats); i++)
1510 data[i] = marvell_get_stat(phydev, i);
1514 static int m88e1121_get_temp(struct phy_device *phydev, long *temp)
1522 mutex_lock(&phydev->lock);
1524 oldpage = marvell_get_set_page(phydev, MII_MARVELL_MISC_TEST_PAGE);
1526 mutex_unlock(&phydev->lock);
1530 /* Enable temperature sensor */
1531 ret = phy_read(phydev, MII_88E1121_MISC_TEST);
1535 ret = phy_write(phydev, MII_88E1121_MISC_TEST,
1536 ret | MII_88E1121_MISC_TEST_TEMP_SENSOR_EN);
1540 /* Wait for temperature to stabilize */
1541 usleep_range(10000, 12000);
1543 val = phy_read(phydev, MII_88E1121_MISC_TEST);
1549 /* Disable temperature sensor */
1550 ret = phy_write(phydev, MII_88E1121_MISC_TEST,
1551 ret & ~MII_88E1121_MISC_TEST_TEMP_SENSOR_EN);
1555 *temp = ((val & MII_88E1121_MISC_TEST_TEMP_MASK) - 5) * 5000;
1558 marvell_set_page(phydev, oldpage);
1559 mutex_unlock(&phydev->lock);
1564 static int m88e1121_hwmon_read(struct device *dev,
1565 enum hwmon_sensor_types type,
1566 u32 attr, int channel, long *temp)
1568 struct phy_device *phydev = dev_get_drvdata(dev);
1572 case hwmon_temp_input:
1573 err = m88e1121_get_temp(phydev, temp);
1582 static umode_t m88e1121_hwmon_is_visible(const void *data,
1583 enum hwmon_sensor_types type,
1584 u32 attr, int channel)
1586 if (type != hwmon_temp)
1590 case hwmon_temp_input:
1597 static u32 m88e1121_hwmon_chip_config[] = {
1598 HWMON_C_REGISTER_TZ,
1602 static const struct hwmon_channel_info m88e1121_hwmon_chip = {
1604 .config = m88e1121_hwmon_chip_config,
1607 static u32 m88e1121_hwmon_temp_config[] = {
1612 static const struct hwmon_channel_info m88e1121_hwmon_temp = {
1614 .config = m88e1121_hwmon_temp_config,
1617 static const struct hwmon_channel_info *m88e1121_hwmon_info[] = {
1618 &m88e1121_hwmon_chip,
1619 &m88e1121_hwmon_temp,
1623 static const struct hwmon_ops m88e1121_hwmon_hwmon_ops = {
1624 .is_visible = m88e1121_hwmon_is_visible,
1625 .read = m88e1121_hwmon_read,
1628 static const struct hwmon_chip_info m88e1121_hwmon_chip_info = {
1629 .ops = &m88e1121_hwmon_hwmon_ops,
1630 .info = m88e1121_hwmon_info,
1633 static int m88e1510_get_temp(struct phy_device *phydev, long *temp)
1640 mutex_lock(&phydev->lock);
1642 oldpage = marvell_get_set_page(phydev, MII_MARVELL_MISC_TEST_PAGE);
1644 mutex_unlock(&phydev->lock);
1648 ret = phy_read(phydev, MII_88E1510_TEMP_SENSOR);
1652 *temp = ((ret & MII_88E1510_TEMP_SENSOR_MASK) - 25) * 1000;
1655 marvell_set_page(phydev, oldpage);
1656 mutex_unlock(&phydev->lock);
1661 static int m88e1510_get_temp_critical(struct phy_device *phydev, long *temp)
1668 mutex_lock(&phydev->lock);
1670 oldpage = marvell_get_set_page(phydev, MII_MARVELL_MISC_TEST_PAGE);
1672 mutex_unlock(&phydev->lock);
1676 ret = phy_read(phydev, MII_88E1121_MISC_TEST);
1680 *temp = (((ret & MII_88E1510_MISC_TEST_TEMP_THRESHOLD_MASK) >>
1681 MII_88E1510_MISC_TEST_TEMP_THRESHOLD_SHIFT) * 5) - 25;
1686 marvell_set_page(phydev, oldpage);
1687 mutex_unlock(&phydev->lock);
1692 static int m88e1510_set_temp_critical(struct phy_device *phydev, long temp)
1697 mutex_lock(&phydev->lock);
1699 oldpage = marvell_get_set_page(phydev, MII_MARVELL_MISC_TEST_PAGE);
1701 mutex_unlock(&phydev->lock);
1705 ret = phy_read(phydev, MII_88E1121_MISC_TEST);
1710 temp = clamp_val(DIV_ROUND_CLOSEST(temp, 5) + 5, 0, 0x1f);
1711 ret = phy_write(phydev, MII_88E1121_MISC_TEST,
1712 (ret & ~MII_88E1510_MISC_TEST_TEMP_THRESHOLD_MASK) |
1713 (temp << MII_88E1510_MISC_TEST_TEMP_THRESHOLD_SHIFT));
1716 marvell_set_page(phydev, oldpage);
1717 mutex_unlock(&phydev->lock);
1722 static int m88e1510_get_temp_alarm(struct phy_device *phydev, long *alarm)
1729 mutex_lock(&phydev->lock);
1731 oldpage = marvell_get_set_page(phydev, MII_MARVELL_MISC_TEST_PAGE);
1733 mutex_unlock(&phydev->lock);
1737 ret = phy_read(phydev, MII_88E1121_MISC_TEST);
1740 *alarm = !!(ret & MII_88E1510_MISC_TEST_TEMP_IRQ);
1743 marvell_set_page(phydev, oldpage);
1744 mutex_unlock(&phydev->lock);
1749 static int m88e1510_hwmon_read(struct device *dev,
1750 enum hwmon_sensor_types type,
1751 u32 attr, int channel, long *temp)
1753 struct phy_device *phydev = dev_get_drvdata(dev);
1757 case hwmon_temp_input:
1758 err = m88e1510_get_temp(phydev, temp);
1760 case hwmon_temp_crit:
1761 err = m88e1510_get_temp_critical(phydev, temp);
1763 case hwmon_temp_max_alarm:
1764 err = m88e1510_get_temp_alarm(phydev, temp);
1773 static int m88e1510_hwmon_write(struct device *dev,
1774 enum hwmon_sensor_types type,
1775 u32 attr, int channel, long temp)
1777 struct phy_device *phydev = dev_get_drvdata(dev);
1781 case hwmon_temp_crit:
1782 err = m88e1510_set_temp_critical(phydev, temp);
1790 static umode_t m88e1510_hwmon_is_visible(const void *data,
1791 enum hwmon_sensor_types type,
1792 u32 attr, int channel)
1794 if (type != hwmon_temp)
1798 case hwmon_temp_input:
1799 case hwmon_temp_max_alarm:
1801 case hwmon_temp_crit:
1808 static u32 m88e1510_hwmon_temp_config[] = {
1809 HWMON_T_INPUT | HWMON_T_CRIT | HWMON_T_MAX_ALARM,
1813 static const struct hwmon_channel_info m88e1510_hwmon_temp = {
1815 .config = m88e1510_hwmon_temp_config,
1818 static const struct hwmon_channel_info *m88e1510_hwmon_info[] = {
1819 &m88e1121_hwmon_chip,
1820 &m88e1510_hwmon_temp,
1824 static const struct hwmon_ops m88e1510_hwmon_hwmon_ops = {
1825 .is_visible = m88e1510_hwmon_is_visible,
1826 .read = m88e1510_hwmon_read,
1827 .write = m88e1510_hwmon_write,
1830 static const struct hwmon_chip_info m88e1510_hwmon_chip_info = {
1831 .ops = &m88e1510_hwmon_hwmon_ops,
1832 .info = m88e1510_hwmon_info,
1835 static int marvell_hwmon_name(struct phy_device *phydev)
1837 struct marvell_priv *priv = phydev->priv;
1838 struct device *dev = &phydev->mdio.dev;
1839 const char *devname = dev_name(dev);
1840 size_t len = strlen(devname);
1843 priv->hwmon_name = devm_kzalloc(dev, len, GFP_KERNEL);
1844 if (!priv->hwmon_name)
1847 for (i = j = 0; i < len && devname[i]; i++) {
1848 if (isalnum(devname[i]))
1849 priv->hwmon_name[j++] = devname[i];
1855 static int marvell_hwmon_probe(struct phy_device *phydev,
1856 const struct hwmon_chip_info *chip)
1858 struct marvell_priv *priv = phydev->priv;
1859 struct device *dev = &phydev->mdio.dev;
1862 err = marvell_hwmon_name(phydev);
1866 priv->hwmon_dev = devm_hwmon_device_register_with_info(
1867 dev, priv->hwmon_name, phydev, chip, NULL);
1869 return PTR_ERR_OR_ZERO(priv->hwmon_dev);
1872 static int m88e1121_hwmon_probe(struct phy_device *phydev)
1874 return marvell_hwmon_probe(phydev, &m88e1121_hwmon_chip_info);
1877 static int m88e1510_hwmon_probe(struct phy_device *phydev)
1879 return marvell_hwmon_probe(phydev, &m88e1510_hwmon_chip_info);
1882 static int m88e1121_hwmon_probe(struct phy_device *phydev)
1887 static int m88e1510_hwmon_probe(struct phy_device *phydev)
1893 static int marvell_probe(struct phy_device *phydev)
1895 struct marvell_priv *priv;
1897 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL);
1901 phydev->priv = priv;
1906 static int m88e1121_probe(struct phy_device *phydev)
1910 err = marvell_probe(phydev);
1914 return m88e1121_hwmon_probe(phydev);
1917 static int m88e1510_probe(struct phy_device *phydev)
1921 err = marvell_probe(phydev);
1925 return m88e1510_hwmon_probe(phydev);
1928 static struct phy_driver marvell_drivers[] = {
1930 .phy_id = MARVELL_PHY_ID_88E1101,
1931 .phy_id_mask = MARVELL_PHY_ID_MASK,
1932 .name = "Marvell 88E1101",
1933 .features = PHY_GBIT_FEATURES,
1934 .flags = PHY_HAS_INTERRUPT,
1935 .probe = marvell_probe,
1936 .config_init = &marvell_config_init,
1937 .config_aneg = &m88e1101_config_aneg,
1938 .read_status = &genphy_read_status,
1939 .ack_interrupt = &marvell_ack_interrupt,
1940 .config_intr = &marvell_config_intr,
1941 .resume = &genphy_resume,
1942 .suspend = &genphy_suspend,
1943 .get_sset_count = marvell_get_sset_count,
1944 .get_strings = marvell_get_strings,
1945 .get_stats = marvell_get_stats,
1948 .phy_id = MARVELL_PHY_ID_88E1112,
1949 .phy_id_mask = MARVELL_PHY_ID_MASK,
1950 .name = "Marvell 88E1112",
1951 .features = PHY_GBIT_FEATURES,
1952 .flags = PHY_HAS_INTERRUPT,
1953 .probe = marvell_probe,
1954 .config_init = &m88e1111_config_init,
1955 .config_aneg = &marvell_config_aneg,
1956 .read_status = &genphy_read_status,
1957 .ack_interrupt = &marvell_ack_interrupt,
1958 .config_intr = &marvell_config_intr,
1959 .resume = &genphy_resume,
1960 .suspend = &genphy_suspend,
1961 .get_sset_count = marvell_get_sset_count,
1962 .get_strings = marvell_get_strings,
1963 .get_stats = marvell_get_stats,
1966 .phy_id = MARVELL_PHY_ID_88E1111,
1967 .phy_id_mask = MARVELL_PHY_ID_MASK,
1968 .name = "Marvell 88E1111",
1969 .features = PHY_GBIT_FEATURES,
1970 .flags = PHY_HAS_INTERRUPT,
1971 .probe = marvell_probe,
1972 .config_init = &m88e1111_config_init,
1973 .config_aneg = &m88e1111_config_aneg,
1974 .read_status = &marvell_read_status,
1975 .ack_interrupt = &marvell_ack_interrupt,
1976 .config_intr = &marvell_config_intr,
1977 .resume = &genphy_resume,
1978 .suspend = &genphy_suspend,
1979 .get_sset_count = marvell_get_sset_count,
1980 .get_strings = marvell_get_strings,
1981 .get_stats = marvell_get_stats,
1984 .phy_id = MARVELL_PHY_ID_88E1118,
1985 .phy_id_mask = MARVELL_PHY_ID_MASK,
1986 .name = "Marvell 88E1118",
1987 .features = PHY_GBIT_FEATURES,
1988 .flags = PHY_HAS_INTERRUPT,
1989 .probe = marvell_probe,
1990 .config_init = &m88e1118_config_init,
1991 .config_aneg = &m88e1118_config_aneg,
1992 .read_status = &genphy_read_status,
1993 .ack_interrupt = &marvell_ack_interrupt,
1994 .config_intr = &marvell_config_intr,
1995 .resume = &genphy_resume,
1996 .suspend = &genphy_suspend,
1997 .get_sset_count = marvell_get_sset_count,
1998 .get_strings = marvell_get_strings,
1999 .get_stats = marvell_get_stats,
2002 .phy_id = MARVELL_PHY_ID_88E1121R,
2003 .phy_id_mask = MARVELL_PHY_ID_MASK,
2004 .name = "Marvell 88E1121R",
2005 .features = PHY_GBIT_FEATURES,
2006 .flags = PHY_HAS_INTERRUPT,
2007 .probe = &m88e1121_probe,
2008 .config_init = &m88e1121_config_init,
2009 .config_aneg = &m88e1121_config_aneg,
2010 .read_status = &marvell_read_status,
2011 .ack_interrupt = &marvell_ack_interrupt,
2012 .config_intr = &marvell_config_intr,
2013 .did_interrupt = &m88e1121_did_interrupt,
2014 .resume = &genphy_resume,
2015 .suspend = &genphy_suspend,
2016 .get_sset_count = marvell_get_sset_count,
2017 .get_strings = marvell_get_strings,
2018 .get_stats = marvell_get_stats,
2021 .phy_id = MARVELL_PHY_ID_88E1318S,
2022 .phy_id_mask = MARVELL_PHY_ID_MASK,
2023 .name = "Marvell 88E1318S",
2024 .features = PHY_GBIT_FEATURES,
2025 .flags = PHY_HAS_INTERRUPT,
2026 .probe = marvell_probe,
2027 .config_init = &m88e1121_config_init,
2028 .config_aneg = &m88e1318_config_aneg,
2029 .read_status = &marvell_read_status,
2030 .ack_interrupt = &marvell_ack_interrupt,
2031 .config_intr = &marvell_config_intr,
2032 .did_interrupt = &m88e1121_did_interrupt,
2033 .get_wol = &m88e1318_get_wol,
2034 .set_wol = &m88e1318_set_wol,
2035 .resume = &genphy_resume,
2036 .suspend = &genphy_suspend,
2037 .get_sset_count = marvell_get_sset_count,
2038 .get_strings = marvell_get_strings,
2039 .get_stats = marvell_get_stats,
2042 .phy_id = MARVELL_PHY_ID_88E1145,
2043 .phy_id_mask = MARVELL_PHY_ID_MASK,
2044 .name = "Marvell 88E1145",
2045 .features = PHY_GBIT_FEATURES,
2046 .flags = PHY_HAS_INTERRUPT,
2047 .probe = marvell_probe,
2048 .config_init = &m88e1145_config_init,
2049 .config_aneg = &marvell_config_aneg,
2050 .read_status = &genphy_read_status,
2051 .ack_interrupt = &marvell_ack_interrupt,
2052 .config_intr = &marvell_config_intr,
2053 .resume = &genphy_resume,
2054 .suspend = &genphy_suspend,
2055 .get_sset_count = marvell_get_sset_count,
2056 .get_strings = marvell_get_strings,
2057 .get_stats = marvell_get_stats,
2060 .phy_id = MARVELL_PHY_ID_88E1149R,
2061 .phy_id_mask = MARVELL_PHY_ID_MASK,
2062 .name = "Marvell 88E1149R",
2063 .features = PHY_GBIT_FEATURES,
2064 .flags = PHY_HAS_INTERRUPT,
2065 .probe = marvell_probe,
2066 .config_init = &m88e1149_config_init,
2067 .config_aneg = &m88e1118_config_aneg,
2068 .read_status = &genphy_read_status,
2069 .ack_interrupt = &marvell_ack_interrupt,
2070 .config_intr = &marvell_config_intr,
2071 .resume = &genphy_resume,
2072 .suspend = &genphy_suspend,
2073 .get_sset_count = marvell_get_sset_count,
2074 .get_strings = marvell_get_strings,
2075 .get_stats = marvell_get_stats,
2078 .phy_id = MARVELL_PHY_ID_88E1240,
2079 .phy_id_mask = MARVELL_PHY_ID_MASK,
2080 .name = "Marvell 88E1240",
2081 .features = PHY_GBIT_FEATURES,
2082 .flags = PHY_HAS_INTERRUPT,
2083 .probe = marvell_probe,
2084 .config_init = &m88e1111_config_init,
2085 .config_aneg = &marvell_config_aneg,
2086 .read_status = &genphy_read_status,
2087 .ack_interrupt = &marvell_ack_interrupt,
2088 .config_intr = &marvell_config_intr,
2089 .resume = &genphy_resume,
2090 .suspend = &genphy_suspend,
2091 .get_sset_count = marvell_get_sset_count,
2092 .get_strings = marvell_get_strings,
2093 .get_stats = marvell_get_stats,
2096 .phy_id = MARVELL_PHY_ID_88E1116R,
2097 .phy_id_mask = MARVELL_PHY_ID_MASK,
2098 .name = "Marvell 88E1116R",
2099 .features = PHY_GBIT_FEATURES,
2100 .flags = PHY_HAS_INTERRUPT,
2101 .probe = marvell_probe,
2102 .config_init = &m88e1116r_config_init,
2103 .config_aneg = &genphy_config_aneg,
2104 .read_status = &genphy_read_status,
2105 .ack_interrupt = &marvell_ack_interrupt,
2106 .config_intr = &marvell_config_intr,
2107 .resume = &genphy_resume,
2108 .suspend = &genphy_suspend,
2109 .get_sset_count = marvell_get_sset_count,
2110 .get_strings = marvell_get_strings,
2111 .get_stats = marvell_get_stats,
2114 .phy_id = MARVELL_PHY_ID_88E1510,
2115 .phy_id_mask = MARVELL_PHY_ID_MASK,
2116 .name = "Marvell 88E1510",
2117 .features = PHY_GBIT_FEATURES | SUPPORTED_FIBRE,
2118 .flags = PHY_HAS_INTERRUPT,
2119 .probe = &m88e1510_probe,
2120 .config_init = &m88e1510_config_init,
2121 .config_aneg = &m88e1510_config_aneg,
2122 .read_status = &marvell_read_status,
2123 .ack_interrupt = &marvell_ack_interrupt,
2124 .config_intr = &marvell_config_intr,
2125 .did_interrupt = &m88e1121_did_interrupt,
2126 .get_wol = &m88e1318_get_wol,
2127 .set_wol = &m88e1318_set_wol,
2128 .resume = &marvell_resume,
2129 .suspend = &marvell_suspend,
2130 .get_sset_count = marvell_get_sset_count,
2131 .get_strings = marvell_get_strings,
2132 .get_stats = marvell_get_stats,
2133 .set_loopback = genphy_loopback,
2136 .phy_id = MARVELL_PHY_ID_88E1540,
2137 .phy_id_mask = MARVELL_PHY_ID_MASK,
2138 .name = "Marvell 88E1540",
2139 .features = PHY_GBIT_FEATURES,
2140 .flags = PHY_HAS_INTERRUPT,
2141 .probe = m88e1510_probe,
2142 .config_init = &marvell_config_init,
2143 .config_aneg = &m88e1510_config_aneg,
2144 .read_status = &marvell_read_status,
2145 .ack_interrupt = &marvell_ack_interrupt,
2146 .config_intr = &marvell_config_intr,
2147 .did_interrupt = &m88e1121_did_interrupt,
2148 .resume = &genphy_resume,
2149 .suspend = &genphy_suspend,
2150 .get_sset_count = marvell_get_sset_count,
2151 .get_strings = marvell_get_strings,
2152 .get_stats = marvell_get_stats,
2155 .phy_id = MARVELL_PHY_ID_88E1545,
2156 .phy_id_mask = MARVELL_PHY_ID_MASK,
2157 .name = "Marvell 88E1545",
2158 .probe = m88e1510_probe,
2159 .features = PHY_GBIT_FEATURES,
2160 .flags = PHY_HAS_INTERRUPT,
2161 .config_init = &marvell_config_init,
2162 .config_aneg = &m88e1510_config_aneg,
2163 .read_status = &marvell_read_status,
2164 .ack_interrupt = &marvell_ack_interrupt,
2165 .config_intr = &marvell_config_intr,
2166 .did_interrupt = &m88e1121_did_interrupt,
2167 .resume = &genphy_resume,
2168 .suspend = &genphy_suspend,
2169 .get_sset_count = marvell_get_sset_count,
2170 .get_strings = marvell_get_strings,
2171 .get_stats = marvell_get_stats,
2174 .phy_id = MARVELL_PHY_ID_88E3016,
2175 .phy_id_mask = MARVELL_PHY_ID_MASK,
2176 .name = "Marvell 88E3016",
2177 .features = PHY_BASIC_FEATURES,
2178 .flags = PHY_HAS_INTERRUPT,
2179 .probe = marvell_probe,
2180 .config_aneg = &genphy_config_aneg,
2181 .config_init = &m88e3016_config_init,
2182 .aneg_done = &marvell_aneg_done,
2183 .read_status = &marvell_read_status,
2184 .ack_interrupt = &marvell_ack_interrupt,
2185 .config_intr = &marvell_config_intr,
2186 .did_interrupt = &m88e1121_did_interrupt,
2187 .resume = &genphy_resume,
2188 .suspend = &genphy_suspend,
2189 .get_sset_count = marvell_get_sset_count,
2190 .get_strings = marvell_get_strings,
2191 .get_stats = marvell_get_stats,
2194 .phy_id = MARVELL_PHY_ID_88E6390,
2195 .phy_id_mask = MARVELL_PHY_ID_MASK,
2196 .name = "Marvell 88E6390",
2197 .features = PHY_GBIT_FEATURES,
2198 .flags = PHY_HAS_INTERRUPT,
2199 .probe = m88e1510_probe,
2200 .config_init = &marvell_config_init,
2201 .config_aneg = &m88e1510_config_aneg,
2202 .read_status = &marvell_read_status,
2203 .ack_interrupt = &marvell_ack_interrupt,
2204 .config_intr = &marvell_config_intr,
2205 .did_interrupt = &m88e1121_did_interrupt,
2206 .resume = &genphy_resume,
2207 .suspend = &genphy_suspend,
2208 .get_sset_count = marvell_get_sset_count,
2209 .get_strings = marvell_get_strings,
2210 .get_stats = marvell_get_stats,
2214 module_phy_driver(marvell_drivers);
2216 static struct mdio_device_id __maybe_unused marvell_tbl[] = {
2217 { MARVELL_PHY_ID_88E1101, MARVELL_PHY_ID_MASK },
2218 { MARVELL_PHY_ID_88E1112, MARVELL_PHY_ID_MASK },
2219 { MARVELL_PHY_ID_88E1111, MARVELL_PHY_ID_MASK },
2220 { MARVELL_PHY_ID_88E1118, MARVELL_PHY_ID_MASK },
2221 { MARVELL_PHY_ID_88E1121R, MARVELL_PHY_ID_MASK },
2222 { MARVELL_PHY_ID_88E1145, MARVELL_PHY_ID_MASK },
2223 { MARVELL_PHY_ID_88E1149R, MARVELL_PHY_ID_MASK },
2224 { MARVELL_PHY_ID_88E1240, MARVELL_PHY_ID_MASK },
2225 { MARVELL_PHY_ID_88E1318S, MARVELL_PHY_ID_MASK },
2226 { MARVELL_PHY_ID_88E1116R, MARVELL_PHY_ID_MASK },
2227 { MARVELL_PHY_ID_88E1510, MARVELL_PHY_ID_MASK },
2228 { MARVELL_PHY_ID_88E1540, MARVELL_PHY_ID_MASK },
2229 { MARVELL_PHY_ID_88E1545, MARVELL_PHY_ID_MASK },
2230 { MARVELL_PHY_ID_88E3016, MARVELL_PHY_ID_MASK },
2231 { MARVELL_PHY_ID_88E6390, MARVELL_PHY_ID_MASK },
2235 MODULE_DEVICE_TABLE(mdio, marvell_tbl);