2 * drivers/net/phy/marvell.c
4 * Driver for Marvell PHYs
8 * Copyright (c) 2004 Freescale Semiconductor, Inc.
10 * Copyright (c) 2013 Michael Stapelberg <michael@stapelberg.de>
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the
14 * Free Software Foundation; either version 2 of the License, or (at your
15 * option) any later version.
18 #include <linux/kernel.h>
19 #include <linux/string.h>
20 #include <linux/errno.h>
21 #include <linux/unistd.h>
22 #include <linux/interrupt.h>
23 #include <linux/init.h>
24 #include <linux/delay.h>
25 #include <linux/netdevice.h>
26 #include <linux/etherdevice.h>
27 #include <linux/skbuff.h>
28 #include <linux/spinlock.h>
30 #include <linux/module.h>
31 #include <linux/mii.h>
32 #include <linux/ethtool.h>
33 #include <linux/phy.h>
34 #include <linux/marvell_phy.h>
39 #include <linux/uaccess.h>
41 #define MII_MARVELL_PHY_PAGE 22
43 #define MII_M1011_IEVENT 0x13
44 #define MII_M1011_IEVENT_CLEAR 0x0000
46 #define MII_M1011_IMASK 0x12
47 #define MII_M1011_IMASK_INIT 0x6400
48 #define MII_M1011_IMASK_CLEAR 0x0000
50 #define MII_M1011_PHY_SCR 0x10
51 #define MII_M1011_PHY_SCR_MDI 0x0000
52 #define MII_M1011_PHY_SCR_MDI_X 0x0020
53 #define MII_M1011_PHY_SCR_AUTO_CROSS 0x0060
55 #define MII_M1145_PHY_EXT_ADDR_PAGE 0x16
56 #define MII_M1145_PHY_EXT_SR 0x1b
57 #define MII_M1145_PHY_EXT_CR 0x14
58 #define MII_M1145_RGMII_RX_DELAY 0x0080
59 #define MII_M1145_RGMII_TX_DELAY 0x0002
60 #define MII_M1145_HWCFG_MODE_SGMII_NO_CLK 0x4
61 #define MII_M1145_HWCFG_MODE_MASK 0xf
62 #define MII_M1145_HWCFG_FIBER_COPPER_AUTO 0x8000
64 #define MII_M1145_HWCFG_MODE_SGMII_NO_CLK 0x4
65 #define MII_M1145_HWCFG_MODE_MASK 0xf
66 #define MII_M1145_HWCFG_FIBER_COPPER_AUTO 0x8000
68 #define MII_M1111_PHY_LED_CONTROL 0x18
69 #define MII_M1111_PHY_LED_DIRECT 0x4100
70 #define MII_M1111_PHY_LED_COMBINE 0x411c
71 #define MII_M1111_PHY_EXT_CR 0x14
72 #define MII_M1111_RX_DELAY 0x80
73 #define MII_M1111_TX_DELAY 0x2
74 #define MII_M1111_PHY_EXT_SR 0x1b
76 #define MII_M1111_HWCFG_MODE_MASK 0xf
77 #define MII_M1111_HWCFG_MODE_COPPER_RGMII 0xb
78 #define MII_M1111_HWCFG_MODE_FIBER_RGMII 0x3
79 #define MII_M1111_HWCFG_MODE_SGMII_NO_CLK 0x4
80 #define MII_M1111_HWCFG_MODE_COPPER_RTBI 0x9
81 #define MII_M1111_HWCFG_FIBER_COPPER_AUTO 0x8000
82 #define MII_M1111_HWCFG_FIBER_COPPER_RES 0x2000
84 #define MII_M1111_COPPER 0
85 #define MII_M1111_FIBER 1
87 #define MII_88E1121_PHY_MSCR_PAGE 2
88 #define MII_88E1121_PHY_MSCR_REG 21
89 #define MII_88E1121_PHY_MSCR_RX_DELAY BIT(5)
90 #define MII_88E1121_PHY_MSCR_TX_DELAY BIT(4)
91 #define MII_88E1121_PHY_MSCR_DELAY_MASK (~(0x3 << 4))
93 #define MII_88E1318S_PHY_MSCR1_REG 16
94 #define MII_88E1318S_PHY_MSCR1_PAD_ODD BIT(6)
96 /* Copper Specific Interrupt Enable Register */
97 #define MII_88E1318S_PHY_CSIER 0x12
98 /* WOL Event Interrupt Enable */
99 #define MII_88E1318S_PHY_CSIER_WOL_EIE BIT(7)
101 /* LED Timer Control Register */
102 #define MII_88E1318S_PHY_LED_PAGE 0x03
103 #define MII_88E1318S_PHY_LED_TCR 0x12
104 #define MII_88E1318S_PHY_LED_TCR_FORCE_INT BIT(15)
105 #define MII_88E1318S_PHY_LED_TCR_INTn_ENABLE BIT(7)
106 #define MII_88E1318S_PHY_LED_TCR_INT_ACTIVE_LOW BIT(11)
108 /* Magic Packet MAC address registers */
109 #define MII_88E1318S_PHY_MAGIC_PACKET_WORD2 0x17
110 #define MII_88E1318S_PHY_MAGIC_PACKET_WORD1 0x18
111 #define MII_88E1318S_PHY_MAGIC_PACKET_WORD0 0x19
113 #define MII_88E1318S_PHY_WOL_PAGE 0x11
114 #define MII_88E1318S_PHY_WOL_CTRL 0x10
115 #define MII_88E1318S_PHY_WOL_CTRL_CLEAR_WOL_STATUS BIT(12)
116 #define MII_88E1318S_PHY_WOL_CTRL_MAGIC_PACKET_MATCH_ENABLE BIT(14)
118 #define MII_88E1121_PHY_LED_CTRL 16
119 #define MII_88E1121_PHY_LED_PAGE 3
120 #define MII_88E1121_PHY_LED_DEF 0x0030
122 #define MII_M1011_PHY_STATUS 0x11
123 #define MII_M1011_PHY_STATUS_1000 0x8000
124 #define MII_M1011_PHY_STATUS_100 0x4000
125 #define MII_M1011_PHY_STATUS_SPD_MASK 0xc000
126 #define MII_M1011_PHY_STATUS_FULLDUPLEX 0x2000
127 #define MII_M1011_PHY_STATUS_RESOLVED 0x0800
128 #define MII_M1011_PHY_STATUS_LINK 0x0400
130 #define MII_M1116R_CONTROL_REG_MAC 21
132 #define MII_88E3016_PHY_SPEC_CTRL 0x10
133 #define MII_88E3016_DISABLE_SCRAMBLER 0x0200
134 #define MII_88E3016_AUTO_MDIX_CROSSOVER 0x0030
136 #define MII_88E1510_GEN_CTRL_REG_1 0x14
137 #define MII_88E1510_GEN_CTRL_REG_1_MODE_MASK 0x7
138 #define MII_88E1510_GEN_CTRL_REG_1_MODE_SGMII 0x1 /* SGMII to copper */
139 #define MII_88E1510_GEN_CTRL_REG_1_RESET 0x8000 /* Soft reset */
141 #define LPA_FIBER_1000HALF 0x40
142 #define LPA_FIBER_1000FULL 0x20
144 #define LPA_PAUSE_FIBER 0x180
145 #define LPA_PAUSE_ASYM_FIBER 0x100
147 #define ADVERTISE_FIBER_1000HALF 0x40
148 #define ADVERTISE_FIBER_1000FULL 0x20
150 #define ADVERTISE_PAUSE_FIBER 0x180
151 #define ADVERTISE_PAUSE_ASYM_FIBER 0x100
153 #define REGISTER_LINK_STATUS 0x400
154 #define NB_FIBER_STATS 1
156 MODULE_DESCRIPTION("Marvell PHY driver");
157 MODULE_AUTHOR("Andy Fleming");
158 MODULE_LICENSE("GPL");
160 struct marvell_hw_stat {
167 static struct marvell_hw_stat marvell_hw_stats[] = {
168 { "phy_receive_errors_copper", 0, 21, 16},
169 { "phy_idle_errors", 0, 10, 8 },
170 { "phy_receive_errors_fiber", 1, 21, 16},
173 struct marvell_priv {
174 u64 stats[ARRAY_SIZE(marvell_hw_stats)];
177 static int marvell_ack_interrupt(struct phy_device *phydev)
181 /* Clear the interrupts by reading the reg */
182 err = phy_read(phydev, MII_M1011_IEVENT);
190 static int marvell_config_intr(struct phy_device *phydev)
194 if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
195 err = phy_write(phydev, MII_M1011_IMASK, MII_M1011_IMASK_INIT);
197 err = phy_write(phydev, MII_M1011_IMASK, MII_M1011_IMASK_CLEAR);
202 static int marvell_set_polarity(struct phy_device *phydev, int polarity)
208 /* get the current settings */
209 reg = phy_read(phydev, MII_M1011_PHY_SCR);
214 val &= ~MII_M1011_PHY_SCR_AUTO_CROSS;
217 val |= MII_M1011_PHY_SCR_MDI;
220 val |= MII_M1011_PHY_SCR_MDI_X;
222 case ETH_TP_MDI_AUTO:
223 case ETH_TP_MDI_INVALID:
225 val |= MII_M1011_PHY_SCR_AUTO_CROSS;
230 /* Set the new polarity value in the register */
231 err = phy_write(phydev, MII_M1011_PHY_SCR, val);
239 static int marvell_config_aneg(struct phy_device *phydev)
243 /* The Marvell PHY has an errata which requires
244 * that certain registers get written in order
245 * to restart autonegotiation */
246 err = phy_write(phydev, MII_BMCR, BMCR_RESET);
251 err = phy_write(phydev, 0x1d, 0x1f);
255 err = phy_write(phydev, 0x1e, 0x200c);
259 err = phy_write(phydev, 0x1d, 0x5);
263 err = phy_write(phydev, 0x1e, 0);
267 err = phy_write(phydev, 0x1e, 0x100);
271 err = marvell_set_polarity(phydev, phydev->mdix_ctrl);
275 err = phy_write(phydev, MII_M1111_PHY_LED_CONTROL,
276 MII_M1111_PHY_LED_DIRECT);
280 err = genphy_config_aneg(phydev);
284 if (phydev->autoneg != AUTONEG_ENABLE) {
288 * A write to speed/duplex bits (that is performed by
289 * genphy_config_aneg() call above) must be followed by
290 * a software reset. Otherwise, the write has no effect.
292 bmcr = phy_read(phydev, MII_BMCR);
296 err = phy_write(phydev, MII_BMCR, bmcr | BMCR_RESET);
304 static int m88e1111_config_aneg(struct phy_device *phydev)
308 /* The Marvell PHY has an errata which requires
309 * that certain registers get written in order
310 * to restart autonegotiation
312 err = phy_write(phydev, MII_BMCR, BMCR_RESET);
314 err = marvell_set_polarity(phydev, phydev->mdix_ctrl);
318 err = phy_write(phydev, MII_M1111_PHY_LED_CONTROL,
319 MII_M1111_PHY_LED_DIRECT);
323 err = genphy_config_aneg(phydev);
327 if (phydev->autoneg != AUTONEG_ENABLE) {
330 /* A write to speed/duplex bits (that is performed by
331 * genphy_config_aneg() call above) must be followed by
332 * a software reset. Otherwise, the write has no effect.
334 bmcr = phy_read(phydev, MII_BMCR);
338 err = phy_write(phydev, MII_BMCR, bmcr | BMCR_RESET);
346 #ifdef CONFIG_OF_MDIO
348 * Set and/or override some configuration registers based on the
349 * marvell,reg-init property stored in the of_node for the phydev.
351 * marvell,reg-init = <reg-page reg mask value>,...;
353 * There may be one or more sets of <reg-page reg mask value>:
355 * reg-page: which register bank to use.
357 * mask: if non-zero, ANDed with existing register value.
358 * value: ORed with the masked value and written to the regiser.
361 static int marvell_of_reg_init(struct phy_device *phydev)
364 int len, i, saved_page, current_page, ret;
366 if (!phydev->mdio.dev.of_node)
369 paddr = of_get_property(phydev->mdio.dev.of_node,
370 "marvell,reg-init", &len);
371 if (!paddr || len < (4 * sizeof(*paddr)))
374 saved_page = phy_read(phydev, MII_MARVELL_PHY_PAGE);
377 current_page = saved_page;
380 len /= sizeof(*paddr);
381 for (i = 0; i < len - 3; i += 4) {
382 u16 reg_page = be32_to_cpup(paddr + i);
383 u16 reg = be32_to_cpup(paddr + i + 1);
384 u16 mask = be32_to_cpup(paddr + i + 2);
385 u16 val_bits = be32_to_cpup(paddr + i + 3);
388 if (reg_page != current_page) {
389 current_page = reg_page;
390 ret = phy_write(phydev, MII_MARVELL_PHY_PAGE, reg_page);
397 val = phy_read(phydev, reg);
406 ret = phy_write(phydev, reg, val);
412 if (current_page != saved_page) {
413 i = phy_write(phydev, MII_MARVELL_PHY_PAGE, saved_page);
420 static int marvell_of_reg_init(struct phy_device *phydev)
424 #endif /* CONFIG_OF_MDIO */
426 static int m88e1121_config_aneg(struct phy_device *phydev)
428 int err, oldpage, mscr;
430 oldpage = phy_read(phydev, MII_MARVELL_PHY_PAGE);
432 err = phy_write(phydev, MII_MARVELL_PHY_PAGE,
433 MII_88E1121_PHY_MSCR_PAGE);
437 if (phy_interface_is_rgmii(phydev)) {
439 mscr = phy_read(phydev, MII_88E1121_PHY_MSCR_REG) &
440 MII_88E1121_PHY_MSCR_DELAY_MASK;
442 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
443 mscr |= (MII_88E1121_PHY_MSCR_RX_DELAY |
444 MII_88E1121_PHY_MSCR_TX_DELAY);
445 else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
446 mscr |= MII_88E1121_PHY_MSCR_RX_DELAY;
447 else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
448 mscr |= MII_88E1121_PHY_MSCR_TX_DELAY;
450 err = phy_write(phydev, MII_88E1121_PHY_MSCR_REG, mscr);
455 phy_write(phydev, MII_MARVELL_PHY_PAGE, oldpage);
457 err = phy_write(phydev, MII_BMCR, BMCR_RESET);
461 err = phy_write(phydev, MII_M1011_PHY_SCR,
462 MII_M1011_PHY_SCR_AUTO_CROSS);
466 return genphy_config_aneg(phydev);
469 static int m88e1318_config_aneg(struct phy_device *phydev)
471 int err, oldpage, mscr;
473 oldpage = phy_read(phydev, MII_MARVELL_PHY_PAGE);
475 err = phy_write(phydev, MII_MARVELL_PHY_PAGE,
476 MII_88E1121_PHY_MSCR_PAGE);
480 mscr = phy_read(phydev, MII_88E1318S_PHY_MSCR1_REG);
481 mscr |= MII_88E1318S_PHY_MSCR1_PAD_ODD;
483 err = phy_write(phydev, MII_88E1318S_PHY_MSCR1_REG, mscr);
487 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, oldpage);
491 return m88e1121_config_aneg(phydev);
495 * ethtool_adv_to_fiber_adv_t
496 * @ethadv: the ethtool advertisement settings
498 * A small helper function that translates ethtool advertisement
499 * settings to phy autonegotiation advertisements for the
500 * MII_ADV register for fiber link.
502 static inline u32 ethtool_adv_to_fiber_adv_t(u32 ethadv)
506 if (ethadv & ADVERTISED_1000baseT_Half)
507 result |= ADVERTISE_FIBER_1000HALF;
508 if (ethadv & ADVERTISED_1000baseT_Full)
509 result |= ADVERTISE_FIBER_1000FULL;
511 if ((ethadv & ADVERTISE_PAUSE_ASYM) && (ethadv & ADVERTISE_PAUSE_CAP))
512 result |= LPA_PAUSE_ASYM_FIBER;
513 else if (ethadv & ADVERTISE_PAUSE_CAP)
514 result |= (ADVERTISE_PAUSE_FIBER
515 & (~ADVERTISE_PAUSE_ASYM_FIBER));
521 * marvell_config_aneg_fiber - restart auto-negotiation or write BMCR
522 * @phydev: target phy_device struct
524 * Description: If auto-negotiation is enabled, we configure the
525 * advertising, and then restart auto-negotiation. If it is not
526 * enabled, then we write the BMCR. Adapted for fiber link in
527 * some Marvell's devices.
529 static int marvell_config_aneg_fiber(struct phy_device *phydev)
536 if (phydev->autoneg != AUTONEG_ENABLE)
537 return genphy_setup_forced(phydev);
539 /* Only allow advertising what this PHY supports */
540 phydev->advertising &= phydev->supported;
541 advertise = phydev->advertising;
543 /* Setup fiber advertisement */
544 adv = phy_read(phydev, MII_ADVERTISE);
549 adv &= ~(ADVERTISE_FIBER_1000HALF | ADVERTISE_FIBER_1000FULL
551 adv |= ethtool_adv_to_fiber_adv_t(advertise);
554 err = phy_write(phydev, MII_ADVERTISE, adv);
562 /* Advertisement hasn't changed, but maybe aneg was never on to
563 * begin with? Or maybe phy was isolated?
565 int ctl = phy_read(phydev, MII_BMCR);
570 if (!(ctl & BMCR_ANENABLE) || (ctl & BMCR_ISOLATE))
571 changed = 1; /* do restart aneg */
574 /* Only restart aneg if we are advertising something different
575 * than we were before.
578 changed = genphy_restart_aneg(phydev);
583 static int m88e1510_config_aneg(struct phy_device *phydev)
587 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, MII_M1111_COPPER);
591 /* Configure the copper link first */
592 err = m88e1318_config_aneg(phydev);
596 /* Then the fiber link */
597 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, MII_M1111_FIBER);
601 err = marvell_config_aneg_fiber(phydev);
605 return phy_write(phydev, MII_MARVELL_PHY_PAGE, MII_M1111_COPPER);
608 phy_write(phydev, MII_MARVELL_PHY_PAGE, MII_M1111_COPPER);
612 static int marvell_config_init(struct phy_device *phydev)
614 /* Set registers from marvell,reg-init DT property */
615 return marvell_of_reg_init(phydev);
618 static int m88e1116r_config_init(struct phy_device *phydev)
623 temp = phy_read(phydev, MII_BMCR);
625 err = phy_write(phydev, MII_BMCR, temp);
631 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0);
635 temp = phy_read(phydev, MII_M1011_PHY_SCR);
636 temp |= (7 << 12); /* max number of gigabit attempts */
637 temp |= (1 << 11); /* enable downshift */
638 temp |= MII_M1011_PHY_SCR_AUTO_CROSS;
639 err = phy_write(phydev, MII_M1011_PHY_SCR, temp);
643 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 2);
646 temp = phy_read(phydev, MII_M1116R_CONTROL_REG_MAC);
649 err = phy_write(phydev, MII_M1116R_CONTROL_REG_MAC, temp);
652 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0);
656 temp = phy_read(phydev, MII_BMCR);
658 err = phy_write(phydev, MII_BMCR, temp);
664 return marvell_config_init(phydev);
667 static int m88e3016_config_init(struct phy_device *phydev)
671 /* Enable Scrambler and Auto-Crossover */
672 reg = phy_read(phydev, MII_88E3016_PHY_SPEC_CTRL);
676 reg &= ~MII_88E3016_DISABLE_SCRAMBLER;
677 reg |= MII_88E3016_AUTO_MDIX_CROSSOVER;
679 reg = phy_write(phydev, MII_88E3016_PHY_SPEC_CTRL, reg);
683 return marvell_config_init(phydev);
686 static int m88e1111_config_init(struct phy_device *phydev)
691 if (phy_interface_is_rgmii(phydev)) {
693 temp = phy_read(phydev, MII_M1111_PHY_EXT_CR);
697 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) {
698 temp |= (MII_M1111_RX_DELAY | MII_M1111_TX_DELAY);
699 } else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) {
700 temp &= ~MII_M1111_TX_DELAY;
701 temp |= MII_M1111_RX_DELAY;
702 } else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
703 temp &= ~MII_M1111_RX_DELAY;
704 temp |= MII_M1111_TX_DELAY;
707 err = phy_write(phydev, MII_M1111_PHY_EXT_CR, temp);
711 temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
715 temp &= ~(MII_M1111_HWCFG_MODE_MASK);
717 if (temp & MII_M1111_HWCFG_FIBER_COPPER_RES)
718 temp |= MII_M1111_HWCFG_MODE_FIBER_RGMII;
720 temp |= MII_M1111_HWCFG_MODE_COPPER_RGMII;
722 err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
727 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
728 temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
732 temp &= ~(MII_M1111_HWCFG_MODE_MASK);
733 temp |= MII_M1111_HWCFG_MODE_SGMII_NO_CLK;
734 temp |= MII_M1111_HWCFG_FIBER_COPPER_AUTO;
736 err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
740 /* make sure copper is selected */
741 err = phy_read(phydev, MII_M1145_PHY_EXT_ADDR_PAGE);
745 err = phy_write(phydev, MII_M1145_PHY_EXT_ADDR_PAGE,
751 if (phydev->interface == PHY_INTERFACE_MODE_RTBI) {
752 temp = phy_read(phydev, MII_M1111_PHY_EXT_CR);
755 temp |= (MII_M1111_RX_DELAY | MII_M1111_TX_DELAY);
756 err = phy_write(phydev, MII_M1111_PHY_EXT_CR, temp);
760 temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
763 temp &= ~(MII_M1111_HWCFG_MODE_MASK | MII_M1111_HWCFG_FIBER_COPPER_RES);
764 temp |= 0x7 | MII_M1111_HWCFG_FIBER_COPPER_AUTO;
765 err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
770 err = phy_write(phydev, MII_BMCR, BMCR_RESET);
774 temp = phy_read(phydev, MII_BMCR);
775 while (temp & BMCR_RESET);
777 temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
780 temp &= ~(MII_M1111_HWCFG_MODE_MASK | MII_M1111_HWCFG_FIBER_COPPER_RES);
781 temp |= MII_M1111_HWCFG_MODE_COPPER_RTBI | MII_M1111_HWCFG_FIBER_COPPER_AUTO;
782 err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
787 err = marvell_of_reg_init(phydev);
791 return phy_write(phydev, MII_BMCR, BMCR_RESET);
794 static int m88e1121_config_init(struct phy_device *phydev)
798 oldpage = phy_read(phydev, MII_MARVELL_PHY_PAGE);
800 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, MII_88E1121_PHY_LED_PAGE);
804 /* Default PHY LED config: LED[0] .. Link, LED[1] .. Activity */
805 err = phy_write(phydev, MII_88E1121_PHY_LED_CTRL,
806 MII_88E1121_PHY_LED_DEF);
810 phy_write(phydev, MII_MARVELL_PHY_PAGE, oldpage);
812 /* Set marvell,reg-init configuration from device tree */
813 return marvell_config_init(phydev);
816 static int m88e1510_config_init(struct phy_device *phydev)
821 /* SGMII-to-Copper mode initialization */
822 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
824 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 18);
828 /* In reg 20, write MODE[2:0] = 0x1 (SGMII to Copper) */
829 temp = phy_read(phydev, MII_88E1510_GEN_CTRL_REG_1);
830 temp &= ~MII_88E1510_GEN_CTRL_REG_1_MODE_MASK;
831 temp |= MII_88E1510_GEN_CTRL_REG_1_MODE_SGMII;
832 err = phy_write(phydev, MII_88E1510_GEN_CTRL_REG_1, temp);
836 /* PHY reset is necessary after changing MODE[2:0] */
837 temp |= MII_88E1510_GEN_CTRL_REG_1_RESET;
838 err = phy_write(phydev, MII_88E1510_GEN_CTRL_REG_1, temp);
842 /* Reset page selection */
843 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0);
848 return m88e1121_config_init(phydev);
851 static int m88e1118_config_aneg(struct phy_device *phydev)
855 err = phy_write(phydev, MII_BMCR, BMCR_RESET);
859 err = phy_write(phydev, MII_M1011_PHY_SCR,
860 MII_M1011_PHY_SCR_AUTO_CROSS);
864 err = genphy_config_aneg(phydev);
868 static int m88e1118_config_init(struct phy_device *phydev)
873 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x0002);
877 /* Enable 1000 Mbit */
878 err = phy_write(phydev, 0x15, 0x1070);
883 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x0003);
887 /* Adjust LED Control */
888 if (phydev->dev_flags & MARVELL_PHY_M1118_DNS323_LEDS)
889 err = phy_write(phydev, 0x10, 0x1100);
891 err = phy_write(phydev, 0x10, 0x021e);
895 err = marvell_of_reg_init(phydev);
900 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x0);
904 return phy_write(phydev, MII_BMCR, BMCR_RESET);
907 static int m88e1149_config_init(struct phy_device *phydev)
912 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x0002);
916 /* Enable 1000 Mbit */
917 err = phy_write(phydev, 0x15, 0x1048);
921 err = marvell_of_reg_init(phydev);
926 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x0);
930 return phy_write(phydev, MII_BMCR, BMCR_RESET);
933 static int m88e1145_config_init(struct phy_device *phydev)
938 /* Take care of errata E0 & E1 */
939 err = phy_write(phydev, 0x1d, 0x001b);
943 err = phy_write(phydev, 0x1e, 0x418f);
947 err = phy_write(phydev, 0x1d, 0x0016);
951 err = phy_write(phydev, 0x1e, 0xa2da);
955 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) {
956 int temp = phy_read(phydev, MII_M1145_PHY_EXT_CR);
960 temp |= (MII_M1145_RGMII_RX_DELAY | MII_M1145_RGMII_TX_DELAY);
962 err = phy_write(phydev, MII_M1145_PHY_EXT_CR, temp);
966 if (phydev->dev_flags & MARVELL_PHY_M1145_FLAGS_RESISTANCE) {
967 err = phy_write(phydev, 0x1d, 0x0012);
971 temp = phy_read(phydev, 0x1e);
976 temp |= 2 << 9; /* 36 ohm */
977 temp |= 2 << 6; /* 39 ohm */
979 err = phy_write(phydev, 0x1e, temp);
983 err = phy_write(phydev, 0x1d, 0x3);
987 err = phy_write(phydev, 0x1e, 0x8000);
993 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
994 temp = phy_read(phydev, MII_M1145_PHY_EXT_SR);
998 temp &= ~MII_M1145_HWCFG_MODE_MASK;
999 temp |= MII_M1145_HWCFG_MODE_SGMII_NO_CLK;
1000 temp |= MII_M1145_HWCFG_FIBER_COPPER_AUTO;
1002 err = phy_write(phydev, MII_M1145_PHY_EXT_SR, temp);
1007 err = marvell_of_reg_init(phydev);
1015 * fiber_lpa_to_ethtool_lpa_t
1016 * @lpa: value of the MII_LPA register for fiber link
1018 * A small helper function that translates MII_LPA
1019 * bits to ethtool LP advertisement settings.
1021 static u32 fiber_lpa_to_ethtool_lpa_t(u32 lpa)
1025 if (lpa & LPA_FIBER_1000HALF)
1026 result |= ADVERTISED_1000baseT_Half;
1027 if (lpa & LPA_FIBER_1000FULL)
1028 result |= ADVERTISED_1000baseT_Full;
1034 * marvell_update_link - update link status in real time in @phydev
1035 * @phydev: target phy_device struct
1037 * Description: Update the value in phydev->link to reflect the
1038 * current link value.
1040 static int marvell_update_link(struct phy_device *phydev, int fiber)
1044 /* Use the generic register for copper link, or specific
1045 * register for fiber case */
1047 status = phy_read(phydev, MII_M1011_PHY_STATUS);
1051 if ((status & REGISTER_LINK_STATUS) == 0)
1056 return genphy_update_link(phydev);
1062 /* marvell_read_status_page
1065 * Check the link, then figure out the current state
1066 * by comparing what we advertise with what the link partner
1067 * advertises. Start by checking the gigabit possibilities,
1068 * then move on to 10/100.
1070 static int marvell_read_status_page(struct phy_device *phydev, int page)
1079 /* Detect and update the link, but return if there
1081 if (page == MII_M1111_FIBER)
1086 err = marvell_update_link(phydev, fiber);
1090 if (AUTONEG_ENABLE == phydev->autoneg) {
1091 status = phy_read(phydev, MII_M1011_PHY_STATUS);
1095 lpa = phy_read(phydev, MII_LPA);
1099 lpagb = phy_read(phydev, MII_STAT1000);
1103 adv = phy_read(phydev, MII_ADVERTISE);
1109 if (status & MII_M1011_PHY_STATUS_FULLDUPLEX)
1110 phydev->duplex = DUPLEX_FULL;
1112 phydev->duplex = DUPLEX_HALF;
1114 status = status & MII_M1011_PHY_STATUS_SPD_MASK;
1115 phydev->pause = phydev->asym_pause = 0;
1118 case MII_M1011_PHY_STATUS_1000:
1119 phydev->speed = SPEED_1000;
1122 case MII_M1011_PHY_STATUS_100:
1123 phydev->speed = SPEED_100;
1127 phydev->speed = SPEED_10;
1132 phydev->lp_advertising = mii_stat1000_to_ethtool_lpa_t(lpagb) |
1133 mii_lpa_to_ethtool_lpa_t(lpa);
1135 if (phydev->duplex == DUPLEX_FULL) {
1136 phydev->pause = lpa & LPA_PAUSE_CAP ? 1 : 0;
1137 phydev->asym_pause = lpa & LPA_PAUSE_ASYM ? 1 : 0;
1140 /* The fiber link is only 1000M capable */
1141 phydev->lp_advertising = fiber_lpa_to_ethtool_lpa_t(lpa);
1143 if (phydev->duplex == DUPLEX_FULL) {
1144 if (!(lpa & LPA_PAUSE_FIBER)) {
1146 phydev->asym_pause = 0;
1147 } else if ((lpa & LPA_PAUSE_ASYM_FIBER)) {
1149 phydev->asym_pause = 1;
1152 phydev->asym_pause = 0;
1157 int bmcr = phy_read(phydev, MII_BMCR);
1162 if (bmcr & BMCR_FULLDPLX)
1163 phydev->duplex = DUPLEX_FULL;
1165 phydev->duplex = DUPLEX_HALF;
1167 if (bmcr & BMCR_SPEED1000)
1168 phydev->speed = SPEED_1000;
1169 else if (bmcr & BMCR_SPEED100)
1170 phydev->speed = SPEED_100;
1172 phydev->speed = SPEED_10;
1174 phydev->pause = phydev->asym_pause = 0;
1175 phydev->lp_advertising = 0;
1181 /* marvell_read_status
1183 * Some Marvell's phys have two modes: fiber and copper.
1184 * Both need status checked.
1186 * First, check the fiber link and status.
1187 * If the fiber link is down, check the copper link and status which
1188 * will be the default value if both link are down.
1190 static int marvell_read_status(struct phy_device *phydev)
1194 /* Check the fiber mode first */
1195 if (phydev->supported & SUPPORTED_FIBRE &&
1196 phydev->interface != PHY_INTERFACE_MODE_SGMII) {
1197 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, MII_M1111_FIBER);
1201 err = marvell_read_status_page(phydev, MII_M1111_FIBER);
1205 /* If the fiber link is up, it is the selected and used link.
1206 * In this case, we need to stay in the fiber page.
1207 * Please to be careful about that, avoid to restore Copper page
1208 * in other functions which could break the behaviour
1209 * for some fiber phy like 88E1512.
1214 /* If fiber link is down, check and save copper mode state */
1215 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, MII_M1111_COPPER);
1220 return marvell_read_status_page(phydev, MII_M1111_COPPER);
1223 phy_write(phydev, MII_MARVELL_PHY_PAGE, MII_M1111_COPPER);
1229 * Some Marvell's phys have two modes: fiber and copper.
1230 * Both need to be suspended
1232 static int marvell_suspend(struct phy_device *phydev)
1236 /* Suspend the fiber mode first */
1237 if (!(phydev->supported & SUPPORTED_FIBRE)) {
1238 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, MII_M1111_FIBER);
1242 /* With the page set, use the generic suspend */
1243 err = genphy_suspend(phydev);
1247 /* Then, the copper link */
1248 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, MII_M1111_COPPER);
1253 /* With the page set, use the generic suspend */
1254 return genphy_suspend(phydev);
1257 phy_write(phydev, MII_MARVELL_PHY_PAGE, MII_M1111_COPPER);
1263 * Some Marvell's phys have two modes: fiber and copper.
1264 * Both need to be resumed
1266 static int marvell_resume(struct phy_device *phydev)
1270 /* Resume the fiber mode first */
1271 if (!(phydev->supported & SUPPORTED_FIBRE)) {
1272 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, MII_M1111_FIBER);
1276 /* With the page set, use the generic resume */
1277 err = genphy_resume(phydev);
1281 /* Then, the copper link */
1282 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, MII_M1111_COPPER);
1287 /* With the page set, use the generic resume */
1288 return genphy_resume(phydev);
1291 phy_write(phydev, MII_MARVELL_PHY_PAGE, MII_M1111_COPPER);
1295 static int marvell_aneg_done(struct phy_device *phydev)
1297 int retval = phy_read(phydev, MII_M1011_PHY_STATUS);
1298 return (retval < 0) ? retval : (retval & MII_M1011_PHY_STATUS_RESOLVED);
1301 static int m88e1121_did_interrupt(struct phy_device *phydev)
1305 imask = phy_read(phydev, MII_M1011_IEVENT);
1307 if (imask & MII_M1011_IMASK_INIT)
1313 static void m88e1318_get_wol(struct phy_device *phydev, struct ethtool_wolinfo *wol)
1315 wol->supported = WAKE_MAGIC;
1318 if (phy_write(phydev, MII_MARVELL_PHY_PAGE,
1319 MII_88E1318S_PHY_WOL_PAGE) < 0)
1322 if (phy_read(phydev, MII_88E1318S_PHY_WOL_CTRL) &
1323 MII_88E1318S_PHY_WOL_CTRL_MAGIC_PACKET_MATCH_ENABLE)
1324 wol->wolopts |= WAKE_MAGIC;
1326 if (phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x00) < 0)
1330 static int m88e1318_set_wol(struct phy_device *phydev, struct ethtool_wolinfo *wol)
1332 int err, oldpage, temp;
1334 oldpage = phy_read(phydev, MII_MARVELL_PHY_PAGE);
1336 if (wol->wolopts & WAKE_MAGIC) {
1337 /* Explicitly switch to page 0x00, just to be sure */
1338 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x00);
1342 /* Enable the WOL interrupt */
1343 temp = phy_read(phydev, MII_88E1318S_PHY_CSIER);
1344 temp |= MII_88E1318S_PHY_CSIER_WOL_EIE;
1345 err = phy_write(phydev, MII_88E1318S_PHY_CSIER, temp);
1349 err = phy_write(phydev, MII_MARVELL_PHY_PAGE,
1350 MII_88E1318S_PHY_LED_PAGE);
1354 /* Setup LED[2] as interrupt pin (active low) */
1355 temp = phy_read(phydev, MII_88E1318S_PHY_LED_TCR);
1356 temp &= ~MII_88E1318S_PHY_LED_TCR_FORCE_INT;
1357 temp |= MII_88E1318S_PHY_LED_TCR_INTn_ENABLE;
1358 temp |= MII_88E1318S_PHY_LED_TCR_INT_ACTIVE_LOW;
1359 err = phy_write(phydev, MII_88E1318S_PHY_LED_TCR, temp);
1363 err = phy_write(phydev, MII_MARVELL_PHY_PAGE,
1364 MII_88E1318S_PHY_WOL_PAGE);
1368 /* Store the device address for the magic packet */
1369 err = phy_write(phydev, MII_88E1318S_PHY_MAGIC_PACKET_WORD2,
1370 ((phydev->attached_dev->dev_addr[5] << 8) |
1371 phydev->attached_dev->dev_addr[4]));
1374 err = phy_write(phydev, MII_88E1318S_PHY_MAGIC_PACKET_WORD1,
1375 ((phydev->attached_dev->dev_addr[3] << 8) |
1376 phydev->attached_dev->dev_addr[2]));
1379 err = phy_write(phydev, MII_88E1318S_PHY_MAGIC_PACKET_WORD0,
1380 ((phydev->attached_dev->dev_addr[1] << 8) |
1381 phydev->attached_dev->dev_addr[0]));
1385 /* Clear WOL status and enable magic packet matching */
1386 temp = phy_read(phydev, MII_88E1318S_PHY_WOL_CTRL);
1387 temp |= MII_88E1318S_PHY_WOL_CTRL_CLEAR_WOL_STATUS;
1388 temp |= MII_88E1318S_PHY_WOL_CTRL_MAGIC_PACKET_MATCH_ENABLE;
1389 err = phy_write(phydev, MII_88E1318S_PHY_WOL_CTRL, temp);
1393 err = phy_write(phydev, MII_MARVELL_PHY_PAGE,
1394 MII_88E1318S_PHY_WOL_PAGE);
1398 /* Clear WOL status and disable magic packet matching */
1399 temp = phy_read(phydev, MII_88E1318S_PHY_WOL_CTRL);
1400 temp |= MII_88E1318S_PHY_WOL_CTRL_CLEAR_WOL_STATUS;
1401 temp &= ~MII_88E1318S_PHY_WOL_CTRL_MAGIC_PACKET_MATCH_ENABLE;
1402 err = phy_write(phydev, MII_88E1318S_PHY_WOL_CTRL, temp);
1407 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, oldpage);
1414 static int marvell_get_sset_count(struct phy_device *phydev)
1416 if (phydev->supported & SUPPORTED_FIBRE)
1417 return ARRAY_SIZE(marvell_hw_stats);
1419 return ARRAY_SIZE(marvell_hw_stats) - NB_FIBER_STATS;
1422 static void marvell_get_strings(struct phy_device *phydev, u8 *data)
1426 for (i = 0; i < ARRAY_SIZE(marvell_hw_stats); i++) {
1427 memcpy(data + i * ETH_GSTRING_LEN,
1428 marvell_hw_stats[i].string, ETH_GSTRING_LEN);
1433 #define UINT64_MAX (u64)(~((u64)0))
1435 static u64 marvell_get_stat(struct phy_device *phydev, int i)
1437 struct marvell_hw_stat stat = marvell_hw_stats[i];
1438 struct marvell_priv *priv = phydev->priv;
1439 int err, oldpage, val;
1442 oldpage = phy_read(phydev, MII_MARVELL_PHY_PAGE);
1443 err = phy_write(phydev, MII_MARVELL_PHY_PAGE,
1448 val = phy_read(phydev, stat.reg);
1452 val = val & ((1 << stat.bits) - 1);
1453 priv->stats[i] += val;
1454 ret = priv->stats[i];
1457 phy_write(phydev, MII_MARVELL_PHY_PAGE, oldpage);
1462 static void marvell_get_stats(struct phy_device *phydev,
1463 struct ethtool_stats *stats, u64 *data)
1467 for (i = 0; i < ARRAY_SIZE(marvell_hw_stats); i++)
1468 data[i] = marvell_get_stat(phydev, i);
1471 static int marvell_probe(struct phy_device *phydev)
1473 struct marvell_priv *priv;
1475 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL);
1479 phydev->priv = priv;
1484 static struct phy_driver marvell_drivers[] = {
1486 .phy_id = MARVELL_PHY_ID_88E1101,
1487 .phy_id_mask = MARVELL_PHY_ID_MASK,
1488 .name = "Marvell 88E1101",
1489 .features = PHY_GBIT_FEATURES,
1490 .probe = marvell_probe,
1491 .flags = PHY_HAS_INTERRUPT,
1492 .config_init = &marvell_config_init,
1493 .config_aneg = &marvell_config_aneg,
1494 .read_status = &genphy_read_status,
1495 .ack_interrupt = &marvell_ack_interrupt,
1496 .config_intr = &marvell_config_intr,
1497 .resume = &genphy_resume,
1498 .suspend = &genphy_suspend,
1499 .get_sset_count = marvell_get_sset_count,
1500 .get_strings = marvell_get_strings,
1501 .get_stats = marvell_get_stats,
1504 .phy_id = MARVELL_PHY_ID_88E1112,
1505 .phy_id_mask = MARVELL_PHY_ID_MASK,
1506 .name = "Marvell 88E1112",
1507 .features = PHY_GBIT_FEATURES,
1508 .flags = PHY_HAS_INTERRUPT,
1509 .probe = marvell_probe,
1510 .config_init = &m88e1111_config_init,
1511 .config_aneg = &marvell_config_aneg,
1512 .read_status = &genphy_read_status,
1513 .ack_interrupt = &marvell_ack_interrupt,
1514 .config_intr = &marvell_config_intr,
1515 .resume = &genphy_resume,
1516 .suspend = &genphy_suspend,
1517 .get_sset_count = marvell_get_sset_count,
1518 .get_strings = marvell_get_strings,
1519 .get_stats = marvell_get_stats,
1522 .phy_id = MARVELL_PHY_ID_88E1111,
1523 .phy_id_mask = MARVELL_PHY_ID_MASK,
1524 .name = "Marvell 88E1111",
1525 .features = PHY_GBIT_FEATURES,
1526 .flags = PHY_HAS_INTERRUPT,
1527 .probe = marvell_probe,
1528 .config_init = &m88e1111_config_init,
1529 .config_aneg = &m88e1111_config_aneg,
1530 .read_status = &marvell_read_status,
1531 .ack_interrupt = &marvell_ack_interrupt,
1532 .config_intr = &marvell_config_intr,
1533 .resume = &genphy_resume,
1534 .suspend = &genphy_suspend,
1535 .get_sset_count = marvell_get_sset_count,
1536 .get_strings = marvell_get_strings,
1537 .get_stats = marvell_get_stats,
1540 .phy_id = MARVELL_PHY_ID_88E1118,
1541 .phy_id_mask = MARVELL_PHY_ID_MASK,
1542 .name = "Marvell 88E1118",
1543 .features = PHY_GBIT_FEATURES,
1544 .flags = PHY_HAS_INTERRUPT,
1545 .probe = marvell_probe,
1546 .config_init = &m88e1118_config_init,
1547 .config_aneg = &m88e1118_config_aneg,
1548 .read_status = &genphy_read_status,
1549 .ack_interrupt = &marvell_ack_interrupt,
1550 .config_intr = &marvell_config_intr,
1551 .resume = &genphy_resume,
1552 .suspend = &genphy_suspend,
1553 .get_sset_count = marvell_get_sset_count,
1554 .get_strings = marvell_get_strings,
1555 .get_stats = marvell_get_stats,
1558 .phy_id = MARVELL_PHY_ID_88E1121R,
1559 .phy_id_mask = MARVELL_PHY_ID_MASK,
1560 .name = "Marvell 88E1121R",
1561 .features = PHY_GBIT_FEATURES,
1562 .flags = PHY_HAS_INTERRUPT,
1563 .probe = marvell_probe,
1564 .config_init = &m88e1121_config_init,
1565 .config_aneg = &m88e1121_config_aneg,
1566 .read_status = &marvell_read_status,
1567 .ack_interrupt = &marvell_ack_interrupt,
1568 .config_intr = &marvell_config_intr,
1569 .did_interrupt = &m88e1121_did_interrupt,
1570 .resume = &genphy_resume,
1571 .suspend = &genphy_suspend,
1572 .get_sset_count = marvell_get_sset_count,
1573 .get_strings = marvell_get_strings,
1574 .get_stats = marvell_get_stats,
1577 .phy_id = MARVELL_PHY_ID_88E1318S,
1578 .phy_id_mask = MARVELL_PHY_ID_MASK,
1579 .name = "Marvell 88E1318S",
1580 .features = PHY_GBIT_FEATURES,
1581 .flags = PHY_HAS_INTERRUPT,
1582 .probe = marvell_probe,
1583 .config_init = &m88e1121_config_init,
1584 .config_aneg = &m88e1318_config_aneg,
1585 .read_status = &marvell_read_status,
1586 .ack_interrupt = &marvell_ack_interrupt,
1587 .config_intr = &marvell_config_intr,
1588 .did_interrupt = &m88e1121_did_interrupt,
1589 .get_wol = &m88e1318_get_wol,
1590 .set_wol = &m88e1318_set_wol,
1591 .resume = &genphy_resume,
1592 .suspend = &genphy_suspend,
1593 .get_sset_count = marvell_get_sset_count,
1594 .get_strings = marvell_get_strings,
1595 .get_stats = marvell_get_stats,
1598 .phy_id = MARVELL_PHY_ID_88E1145,
1599 .phy_id_mask = MARVELL_PHY_ID_MASK,
1600 .name = "Marvell 88E1145",
1601 .features = PHY_GBIT_FEATURES,
1602 .flags = PHY_HAS_INTERRUPT,
1603 .probe = marvell_probe,
1604 .config_init = &m88e1145_config_init,
1605 .config_aneg = &marvell_config_aneg,
1606 .read_status = &genphy_read_status,
1607 .ack_interrupt = &marvell_ack_interrupt,
1608 .config_intr = &marvell_config_intr,
1609 .resume = &genphy_resume,
1610 .suspend = &genphy_suspend,
1611 .get_sset_count = marvell_get_sset_count,
1612 .get_strings = marvell_get_strings,
1613 .get_stats = marvell_get_stats,
1616 .phy_id = MARVELL_PHY_ID_88E1149R,
1617 .phy_id_mask = MARVELL_PHY_ID_MASK,
1618 .name = "Marvell 88E1149R",
1619 .features = PHY_GBIT_FEATURES,
1620 .flags = PHY_HAS_INTERRUPT,
1621 .probe = marvell_probe,
1622 .config_init = &m88e1149_config_init,
1623 .config_aneg = &m88e1118_config_aneg,
1624 .read_status = &genphy_read_status,
1625 .ack_interrupt = &marvell_ack_interrupt,
1626 .config_intr = &marvell_config_intr,
1627 .resume = &genphy_resume,
1628 .suspend = &genphy_suspend,
1629 .get_sset_count = marvell_get_sset_count,
1630 .get_strings = marvell_get_strings,
1631 .get_stats = marvell_get_stats,
1634 .phy_id = MARVELL_PHY_ID_88E1240,
1635 .phy_id_mask = MARVELL_PHY_ID_MASK,
1636 .name = "Marvell 88E1240",
1637 .features = PHY_GBIT_FEATURES,
1638 .flags = PHY_HAS_INTERRUPT,
1639 .probe = marvell_probe,
1640 .config_init = &m88e1111_config_init,
1641 .config_aneg = &marvell_config_aneg,
1642 .read_status = &genphy_read_status,
1643 .ack_interrupt = &marvell_ack_interrupt,
1644 .config_intr = &marvell_config_intr,
1645 .resume = &genphy_resume,
1646 .suspend = &genphy_suspend,
1647 .get_sset_count = marvell_get_sset_count,
1648 .get_strings = marvell_get_strings,
1649 .get_stats = marvell_get_stats,
1652 .phy_id = MARVELL_PHY_ID_88E1116R,
1653 .phy_id_mask = MARVELL_PHY_ID_MASK,
1654 .name = "Marvell 88E1116R",
1655 .features = PHY_GBIT_FEATURES,
1656 .flags = PHY_HAS_INTERRUPT,
1657 .probe = marvell_probe,
1658 .config_init = &m88e1116r_config_init,
1659 .config_aneg = &genphy_config_aneg,
1660 .read_status = &genphy_read_status,
1661 .ack_interrupt = &marvell_ack_interrupt,
1662 .config_intr = &marvell_config_intr,
1663 .resume = &genphy_resume,
1664 .suspend = &genphy_suspend,
1665 .get_sset_count = marvell_get_sset_count,
1666 .get_strings = marvell_get_strings,
1667 .get_stats = marvell_get_stats,
1670 .phy_id = MARVELL_PHY_ID_88E1510,
1671 .phy_id_mask = MARVELL_PHY_ID_MASK,
1672 .name = "Marvell 88E1510",
1673 .features = PHY_GBIT_FEATURES | SUPPORTED_FIBRE,
1674 .flags = PHY_HAS_INTERRUPT,
1675 .probe = marvell_probe,
1676 .config_init = &m88e1510_config_init,
1677 .config_aneg = &m88e1510_config_aneg,
1678 .read_status = &marvell_read_status,
1679 .ack_interrupt = &marvell_ack_interrupt,
1680 .config_intr = &marvell_config_intr,
1681 .did_interrupt = &m88e1121_did_interrupt,
1682 .get_wol = &m88e1318_get_wol,
1683 .set_wol = &m88e1318_set_wol,
1684 .resume = &marvell_resume,
1685 .suspend = &marvell_suspend,
1686 .get_sset_count = marvell_get_sset_count,
1687 .get_strings = marvell_get_strings,
1688 .get_stats = marvell_get_stats,
1691 .phy_id = MARVELL_PHY_ID_88E1540,
1692 .phy_id_mask = MARVELL_PHY_ID_MASK,
1693 .name = "Marvell 88E1540",
1694 .features = PHY_GBIT_FEATURES,
1695 .flags = PHY_HAS_INTERRUPT,
1696 .probe = marvell_probe,
1697 .config_init = &marvell_config_init,
1698 .config_aneg = &m88e1510_config_aneg,
1699 .read_status = &marvell_read_status,
1700 .ack_interrupt = &marvell_ack_interrupt,
1701 .config_intr = &marvell_config_intr,
1702 .did_interrupt = &m88e1121_did_interrupt,
1703 .resume = &genphy_resume,
1704 .suspend = &genphy_suspend,
1705 .get_sset_count = marvell_get_sset_count,
1706 .get_strings = marvell_get_strings,
1707 .get_stats = marvell_get_stats,
1710 .phy_id = MARVELL_PHY_ID_88E3016,
1711 .phy_id_mask = MARVELL_PHY_ID_MASK,
1712 .name = "Marvell 88E3016",
1713 .features = PHY_BASIC_FEATURES,
1714 .flags = PHY_HAS_INTERRUPT,
1715 .probe = marvell_probe,
1716 .config_aneg = &genphy_config_aneg,
1717 .config_init = &m88e3016_config_init,
1718 .aneg_done = &marvell_aneg_done,
1719 .read_status = &marvell_read_status,
1720 .ack_interrupt = &marvell_ack_interrupt,
1721 .config_intr = &marvell_config_intr,
1722 .did_interrupt = &m88e1121_did_interrupt,
1723 .resume = &genphy_resume,
1724 .suspend = &genphy_suspend,
1725 .get_sset_count = marvell_get_sset_count,
1726 .get_strings = marvell_get_strings,
1727 .get_stats = marvell_get_stats,
1731 module_phy_driver(marvell_drivers);
1733 static struct mdio_device_id __maybe_unused marvell_tbl[] = {
1734 { MARVELL_PHY_ID_88E1101, MARVELL_PHY_ID_MASK },
1735 { MARVELL_PHY_ID_88E1112, MARVELL_PHY_ID_MASK },
1736 { MARVELL_PHY_ID_88E1111, MARVELL_PHY_ID_MASK },
1737 { MARVELL_PHY_ID_88E1118, MARVELL_PHY_ID_MASK },
1738 { MARVELL_PHY_ID_88E1121R, MARVELL_PHY_ID_MASK },
1739 { MARVELL_PHY_ID_88E1145, MARVELL_PHY_ID_MASK },
1740 { MARVELL_PHY_ID_88E1149R, MARVELL_PHY_ID_MASK },
1741 { MARVELL_PHY_ID_88E1240, MARVELL_PHY_ID_MASK },
1742 { MARVELL_PHY_ID_88E1318S, MARVELL_PHY_ID_MASK },
1743 { MARVELL_PHY_ID_88E1116R, MARVELL_PHY_ID_MASK },
1744 { MARVELL_PHY_ID_88E1510, MARVELL_PHY_ID_MASK },
1745 { MARVELL_PHY_ID_88E1540, MARVELL_PHY_ID_MASK },
1746 { MARVELL_PHY_ID_88E3016, MARVELL_PHY_ID_MASK },
1750 MODULE_DEVICE_TABLE(mdio, marvell_tbl);