1 // SPDX-License-Identifier: GPL-2.0+
3 * Marvell 10G 88x3310 PHY driver
5 * Based upon the ID registers, this PHY appears to be a mixture of IPs
6 * from two different companies.
8 * There appears to be several different data paths through the PHY which
9 * are automatically managed by the PHY. The following has been determined
10 * via observation and experimentation for a setup using single-lane Serdes:
12 * SGMII PHYXS -- BASE-T PCS -- 10G PMA -- AN -- Copper (for <= 1G)
13 * 10GBASE-KR PHYXS -- BASE-T PCS -- 10G PMA -- AN -- Copper (for 10G)
14 * 10GBASE-KR PHYXS -- BASE-R PCS -- Fiber
16 * With XAUI, observation shows:
18 * XAUI PHYXS -- <appropriate PCS as above>
20 * and no switching of the host interface mode occurs.
22 * If both the fiber and copper ports are connected, the first to gain
23 * link takes priority and the other port is completely locked out.
25 #include <linux/ctype.h>
26 #include <linux/hwmon.h>
27 #include <linux/marvell_phy.h>
28 #include <linux/phy.h>
30 #define MV_PHY_ALASKA_NBT_QUIRK_MASK 0xfffffffe
31 #define MV_PHY_ALASKA_NBT_QUIRK_REV (MARVELL_PHY_ID_88X3310 | 0xa)
34 MV_PCS_BASE_T = 0x0000,
35 MV_PCS_BASE_R = 0x1000,
36 MV_PCS_1000BASEX = 0x2000,
38 MV_PCS_PAIRSWAP = 0x8182,
39 MV_PCS_PAIRSWAP_MASK = 0x0003,
40 MV_PCS_PAIRSWAP_AB = 0x0002,
41 MV_PCS_PAIRSWAP_NONE = 0x0003,
43 /* These registers appear at 0x800X and 0xa00X - the 0xa00X control
44 * registers appear to set themselves to the 0x800X when AN is
45 * restarted, but status registers appear readable from either.
47 MV_AN_CTRL1000 = 0x8000, /* 1000base-T control register */
48 MV_AN_STAT1000 = 0x8001, /* 1000base-T status register */
50 /* Vendor2 MMD registers */
51 MV_V2_PORT_CTRL = 0xf001,
52 MV_V2_PORT_CTRL_PWRDOWN = 0x0800,
53 MV_V2_TEMP_CTRL = 0xf08a,
54 MV_V2_TEMP_CTRL_MASK = 0xc000,
55 MV_V2_TEMP_CTRL_SAMPLE = 0x0000,
56 MV_V2_TEMP_CTRL_DISABLE = 0xc000,
58 MV_V2_TEMP_UNKNOWN = 0x9600, /* unknown function */
62 struct device *hwmon_dev;
67 static umode_t mv3310_hwmon_is_visible(const void *data,
68 enum hwmon_sensor_types type,
69 u32 attr, int channel)
71 if (type == hwmon_chip && attr == hwmon_chip_update_interval)
73 if (type == hwmon_temp && attr == hwmon_temp_input)
78 static int mv3310_hwmon_read(struct device *dev, enum hwmon_sensor_types type,
79 u32 attr, int channel, long *value)
81 struct phy_device *phydev = dev_get_drvdata(dev);
84 if (type == hwmon_chip && attr == hwmon_chip_update_interval) {
85 *value = MSEC_PER_SEC;
89 if (type == hwmon_temp && attr == hwmon_temp_input) {
90 temp = phy_read_mmd(phydev, MDIO_MMD_VEND2, MV_V2_TEMP);
94 *value = ((temp & 0xff) - 75) * 1000;
102 static const struct hwmon_ops mv3310_hwmon_ops = {
103 .is_visible = mv3310_hwmon_is_visible,
104 .read = mv3310_hwmon_read,
107 static u32 mv3310_hwmon_chip_config[] = {
108 HWMON_C_REGISTER_TZ | HWMON_C_UPDATE_INTERVAL,
112 static const struct hwmon_channel_info mv3310_hwmon_chip = {
114 .config = mv3310_hwmon_chip_config,
117 static u32 mv3310_hwmon_temp_config[] = {
122 static const struct hwmon_channel_info mv3310_hwmon_temp = {
124 .config = mv3310_hwmon_temp_config,
127 static const struct hwmon_channel_info *mv3310_hwmon_info[] = {
133 static const struct hwmon_chip_info mv3310_hwmon_chip_info = {
134 .ops = &mv3310_hwmon_ops,
135 .info = mv3310_hwmon_info,
138 static int mv3310_hwmon_config(struct phy_device *phydev, bool enable)
143 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, MV_V2_TEMP,
148 val = enable ? MV_V2_TEMP_CTRL_SAMPLE : MV_V2_TEMP_CTRL_DISABLE;
150 return phy_modify_mmd(phydev, MDIO_MMD_VEND2, MV_V2_TEMP_CTRL,
151 MV_V2_TEMP_CTRL_MASK, val);
154 static void mv3310_hwmon_disable(void *data)
156 struct phy_device *phydev = data;
158 mv3310_hwmon_config(phydev, false);
161 static int mv3310_hwmon_probe(struct phy_device *phydev)
163 struct device *dev = &phydev->mdio.dev;
164 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev);
167 priv->hwmon_name = devm_kstrdup(dev, dev_name(dev), GFP_KERNEL);
168 if (!priv->hwmon_name)
171 for (i = j = 0; priv->hwmon_name[i]; i++) {
172 if (isalnum(priv->hwmon_name[i])) {
174 priv->hwmon_name[j] = priv->hwmon_name[i];
178 priv->hwmon_name[j] = '\0';
180 ret = mv3310_hwmon_config(phydev, true);
184 ret = devm_add_action_or_reset(dev, mv3310_hwmon_disable, phydev);
188 priv->hwmon_dev = devm_hwmon_device_register_with_info(dev,
189 priv->hwmon_name, phydev,
190 &mv3310_hwmon_chip_info, NULL);
192 return PTR_ERR_OR_ZERO(priv->hwmon_dev);
195 static inline int mv3310_hwmon_config(struct phy_device *phydev, bool enable)
200 static int mv3310_hwmon_probe(struct phy_device *phydev)
206 static int mv3310_probe(struct phy_device *phydev)
208 struct mv3310_priv *priv;
209 u32 mmd_mask = MDIO_DEVS_PMAPMD | MDIO_DEVS_AN;
212 if (!phydev->is_c45 ||
213 (phydev->c45_ids.devices_in_package & mmd_mask) != mmd_mask)
216 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL);
220 dev_set_drvdata(&phydev->mdio.dev, priv);
222 ret = mv3310_hwmon_probe(phydev);
229 static int mv3310_suspend(struct phy_device *phydev)
231 return phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL,
232 MV_V2_PORT_CTRL_PWRDOWN);
235 static int mv3310_resume(struct phy_device *phydev)
239 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL,
240 MV_V2_PORT_CTRL_PWRDOWN);
244 return mv3310_hwmon_config(phydev, true);
247 /* Some PHYs in the Alaska family such as the 88X3310 and the 88E2010
248 * don't set bit 14 in PMA Extended Abilities (1.11), although they do
249 * support 2.5GBASET and 5GBASET. For these models, we can still read their
250 * 2.5G/5G extended abilities register (1.21). We detect these models based on
251 * the PMA device identifier, with a mask matching models known to have this
254 static bool mv3310_has_pma_ngbaset_quirk(struct phy_device *phydev)
256 if (!(phydev->c45_ids.devices_in_package & MDIO_DEVS_PMAPMD))
259 /* Only some revisions of the 88X3310 family PMA seem to be impacted */
260 return (phydev->c45_ids.device_ids[MDIO_MMD_PMAPMD] &
261 MV_PHY_ALASKA_NBT_QUIRK_MASK) == MV_PHY_ALASKA_NBT_QUIRK_REV;
264 static int mv3310_config_init(struct phy_device *phydev)
266 /* Check that the PHY interface type is compatible */
267 if (phydev->interface != PHY_INTERFACE_MODE_SGMII &&
268 phydev->interface != PHY_INTERFACE_MODE_2500BASEX &&
269 phydev->interface != PHY_INTERFACE_MODE_XAUI &&
270 phydev->interface != PHY_INTERFACE_MODE_RXAUI &&
271 phydev->interface != PHY_INTERFACE_MODE_10GKR)
277 static int mv3310_get_features(struct phy_device *phydev)
281 ret = genphy_c45_pma_read_abilities(phydev);
285 if (mv3310_has_pma_ngbaset_quirk(phydev)) {
286 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD,
287 MDIO_PMA_NG_EXTABLE);
291 linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
293 val & MDIO_PMA_NG_EXTABLE_2_5GBT);
295 linkmode_mod_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT,
297 val & MDIO_PMA_NG_EXTABLE_5GBT);
303 static int mv3310_config_aneg(struct phy_device *phydev)
305 bool changed = false;
309 /* We don't support manual MDI control */
310 phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
312 if (phydev->autoneg == AUTONEG_DISABLE)
313 return genphy_c45_pma_setup_forced(phydev);
315 ret = genphy_c45_an_config_aneg(phydev);
321 /* Clause 45 has no standardized support for 1000BaseT, therefore
322 * use vendor registers for this mode.
324 reg = linkmode_adv_to_mii_ctrl1000_t(phydev->advertising);
325 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MV_AN_CTRL1000,
326 ADVERTISE_1000FULL | ADVERTISE_1000HALF, reg);
332 return genphy_c45_check_and_restart_aneg(phydev, changed);
335 static int mv3310_aneg_done(struct phy_device *phydev)
339 val = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_BASE_R + MDIO_STAT1);
343 if (val & MDIO_STAT1_LSTATUS)
346 return genphy_c45_aneg_done(phydev);
349 static void mv3310_update_interface(struct phy_device *phydev)
351 if ((phydev->interface == PHY_INTERFACE_MODE_SGMII ||
352 phydev->interface == PHY_INTERFACE_MODE_2500BASEX ||
353 phydev->interface == PHY_INTERFACE_MODE_10GKR) && phydev->link) {
354 /* The PHY automatically switches its serdes interface (and
355 * active PHYXS instance) between Cisco SGMII, 10GBase-KR and
356 * 2500BaseX modes according to the speed. Florian suggests
357 * setting phydev->interface to communicate this to the MAC.
358 * Only do this if we are already in one of the above modes.
360 switch (phydev->speed) {
362 phydev->interface = PHY_INTERFACE_MODE_10GKR;
365 phydev->interface = PHY_INTERFACE_MODE_2500BASEX;
370 phydev->interface = PHY_INTERFACE_MODE_SGMII;
378 /* 10GBASE-ER,LR,LRM,SR do not support autonegotiation. */
379 static int mv3310_read_10gbr_status(struct phy_device *phydev)
382 phydev->speed = SPEED_10000;
383 phydev->duplex = DUPLEX_FULL;
385 mv3310_update_interface(phydev);
390 static int mv3310_read_status(struct phy_device *phydev)
394 phydev->speed = SPEED_UNKNOWN;
395 phydev->duplex = DUPLEX_UNKNOWN;
396 linkmode_zero(phydev->lp_advertising);
399 phydev->asym_pause = 0;
402 val = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_BASE_R + MDIO_STAT1);
406 if (val & MDIO_STAT1_LSTATUS)
407 return mv3310_read_10gbr_status(phydev);
409 val = genphy_c45_read_link(phydev);
413 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1);
417 if (val & MDIO_AN_STAT1_COMPLETE) {
418 val = genphy_c45_read_lpa(phydev);
422 /* Read the link partner's 1G advertisement */
423 val = phy_read_mmd(phydev, MDIO_MMD_AN, MV_AN_STAT1000);
427 mii_stat1000_mod_linkmode_lpa_t(phydev->lp_advertising, val);
429 if (phydev->autoneg == AUTONEG_ENABLE)
430 phy_resolve_aneg_linkmode(phydev);
433 if (phydev->autoneg != AUTONEG_ENABLE) {
434 val = genphy_c45_read_pma(phydev);
439 if (phydev->speed == SPEED_10000) {
440 val = genphy_c45_read_mdix(phydev);
444 val = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_PAIRSWAP);
448 switch (val & MV_PCS_PAIRSWAP_MASK) {
449 case MV_PCS_PAIRSWAP_AB:
450 phydev->mdix = ETH_TP_MDI_X;
452 case MV_PCS_PAIRSWAP_NONE:
453 phydev->mdix = ETH_TP_MDI;
456 phydev->mdix = ETH_TP_MDI_INVALID;
461 mv3310_update_interface(phydev);
466 static struct phy_driver mv3310_drivers[] = {
468 .phy_id = MARVELL_PHY_ID_88X3310,
469 .phy_id_mask = MARVELL_PHY_ID_MASK,
471 .get_features = mv3310_get_features,
472 .soft_reset = genphy_no_soft_reset,
473 .config_init = mv3310_config_init,
474 .probe = mv3310_probe,
475 .suspend = mv3310_suspend,
476 .resume = mv3310_resume,
477 .config_aneg = mv3310_config_aneg,
478 .aneg_done = mv3310_aneg_done,
479 .read_status = mv3310_read_status,
482 .phy_id = MARVELL_PHY_ID_88E2110,
483 .phy_id_mask = MARVELL_PHY_ID_MASK,
485 .get_features = genphy_c45_pma_read_abilities,
486 .probe = mv3310_probe,
487 .suspend = mv3310_suspend,
488 .resume = mv3310_resume,
489 .soft_reset = genphy_no_soft_reset,
490 .config_init = mv3310_config_init,
491 .config_aneg = mv3310_config_aneg,
492 .aneg_done = mv3310_aneg_done,
493 .read_status = mv3310_read_status,
497 module_phy_driver(mv3310_drivers);
499 static struct mdio_device_id __maybe_unused mv3310_tbl[] = {
500 { MARVELL_PHY_ID_88X3310, MARVELL_PHY_ID_MASK },
501 { MARVELL_PHY_ID_88E2110, MARVELL_PHY_ID_MASK },
504 MODULE_DEVICE_TABLE(mdio, mv3310_tbl);
505 MODULE_DESCRIPTION("Marvell Alaska X 10Gigabit Ethernet PHY driver (MV88X3310)");
506 MODULE_LICENSE("GPL");