drivers/net/phy/mscc.c

   1 /*
   2  * Driver for Microsemi VSC85xx PHYs
   3  *
   4  * Author: Nagaraju Lakkaraju
   5  * License: Dual MIT/GPL
   6  * Copyright (c) 2016 Microsemi Corporation
   7  */
   8
   9 #include <linux/kernel.h>
  10 #include <linux/module.h>
  11 #include <linux/mdio.h>
  12 #include <linux/mii.h>
  13 #include <linux/phy.h>
  14 #include <linux/of.h>
  15 #include <linux/netdevice.h>
  16 #include <dt-bindings/net/mscc-phy-vsc8531.h>
  17
  18 enum rgmii_rx_clock_delay {
  19         RGMII_RX_CLK_DELAY_0_2_NS = 0,
  20         RGMII_RX_CLK_DELAY_0_8_NS = 1,
  21         RGMII_RX_CLK_DELAY_1_1_NS = 2,
  22         RGMII_RX_CLK_DELAY_1_7_NS = 3,
  23         RGMII_RX_CLK_DELAY_2_0_NS = 4,
  24         RGMII_RX_CLK_DELAY_2_3_NS = 5,
  25         RGMII_RX_CLK_DELAY_2_6_NS = 6,
  26         RGMII_RX_CLK_DELAY_3_4_NS = 7
  27 };
  28
  29 /* Microsemi VSC85xx PHY registers */
  30 /* IEEE 802. Std Registers */
  31 #define MSCC_PHY_BYPASS_CONTROL           18
  32 #define DISABLE_HP_AUTO_MDIX_MASK         0x0080
  33 #define DISABLE_PAIR_SWAP_CORR_MASK       0x0020
  34 #define DISABLE_POLARITY_CORR_MASK        0x0010
  35
  36 #define MSCC_PHY_EXT_PHY_CNTL_1           23
  37 #define MAC_IF_SELECTION_MASK             0x1800
  38 #define MAC_IF_SELECTION_GMII             0
  39 #define MAC_IF_SELECTION_RMII             1
  40 #define MAC_IF_SELECTION_RGMII            2
  41 #define MAC_IF_SELECTION_POS              11
  42 #define FAR_END_LOOPBACK_MODE_MASK        0x0008
  43
  44 #define MII_VSC85XX_INT_MASK              25
  45 #define MII_VSC85XX_INT_MASK_MASK         0xa000
  46 #define MII_VSC85XX_INT_MASK_WOL          0x0040
  47 #define MII_VSC85XX_INT_STATUS            26
  48
  49 #define MSCC_PHY_WOL_MAC_CONTROL          27
  50 #define EDGE_RATE_CNTL_POS                5
  51 #define EDGE_RATE_CNTL_MASK               0x00E0
  52
  53 #define MSCC_PHY_DEV_AUX_CNTL             28
  54 #define HP_AUTO_MDIX_X_OVER_IND_MASK      0x2000
  55
  56 #define MSCC_PHY_LED_MODE_SEL             29
  57 #define LED_MODE_SEL_POS(x)               ((x) * 4)
  58 #define LED_MODE_SEL_MASK(x)              (GENMASK(3, 0) << LED_MODE_SEL_POS(x))
  59 #define LED_MODE_SEL(x, mode)             (((mode) << LED_MODE_SEL_POS(x)) & LED_MODE_SEL_MASK(x))
  60
  61 #define MSCC_EXT_PAGE_ACCESS              31
  62 #define MSCC_PHY_PAGE_STANDARD            0x0000 /* Standard registers */
  63 #define MSCC_PHY_PAGE_EXTENDED            0x0001 /* Extended registers */
  64 #define MSCC_PHY_PAGE_EXTENDED_2          0x0002 /* Extended reg - page 2 */
  65
  66 /* Extended Page 1 Registers */
  67 #define MSCC_PHY_EXT_MODE_CNTL            19
  68 #define FORCE_MDI_CROSSOVER_MASK          0x000C
  69 #define FORCE_MDI_CROSSOVER_MDIX          0x000C
  70 #define FORCE_MDI_CROSSOVER_MDI           0x0008
  71
  72 #define MSCC_PHY_ACTIPHY_CNTL             20
  73 #define DOWNSHIFT_CNTL_MASK               0x001C
  74 #define DOWNSHIFT_EN                      0x0010
  75 #define DOWNSHIFT_CNTL_POS                2
  76
  77 /* Extended Page 2 Registers */
  78 #define MSCC_PHY_RGMII_CNTL               20
  79 #define RGMII_RX_CLK_DELAY_MASK           0x0070
  80 #define RGMII_RX_CLK_DELAY_POS            4
  81
  82 #define MSCC_PHY_WOL_LOWER_MAC_ADDR       21
  83 #define MSCC_PHY_WOL_MID_MAC_ADDR         22
  84 #define MSCC_PHY_WOL_UPPER_MAC_ADDR       23
  85 #define MSCC_PHY_WOL_LOWER_PASSWD         24
  86 #define MSCC_PHY_WOL_MID_PASSWD           25
  87 #define MSCC_PHY_WOL_UPPER_PASSWD         26
  88
  89 #define MSCC_PHY_WOL_MAC_CONTROL          27
  90 #define SECURE_ON_ENABLE                  0x8000
  91 #define SECURE_ON_PASSWD_LEN_4            0x4000
  92
  93 /* Microsemi PHY ID's */
  94 #define PHY_ID_VSC8530                    0x00070560
  95 #define PHY_ID_VSC8531                    0x00070570
  96 #define PHY_ID_VSC8540                    0x00070760
  97 #define PHY_ID_VSC8541                    0x00070770
  98
  99 #define MSCC_VDDMAC_1500                  1500
 100 #define MSCC_VDDMAC_1800                  1800
 101 #define MSCC_VDDMAC_2500                  2500
 102 #define MSCC_VDDMAC_3300                  3300
 103
 104 #define DOWNSHIFT_COUNT_MAX               5
 105
 106 #define MAX_LEDS                          4
 107 #define VSC85XX_SUPP_LED_MODES (BIT(VSC8531_LINK_ACTIVITY) | \
 108                                 BIT(VSC8531_LINK_1000_ACTIVITY) | \
 109                                 BIT(VSC8531_LINK_100_ACTIVITY) | \
 110                                 BIT(VSC8531_LINK_10_ACTIVITY) | \
 111                                 BIT(VSC8531_LINK_100_1000_ACTIVITY) | \
 112                                 BIT(VSC8531_LINK_10_1000_ACTIVITY) | \
 113                                 BIT(VSC8531_LINK_10_100_ACTIVITY) | \
 114                                 BIT(VSC8531_DUPLEX_COLLISION) | \
 115                                 BIT(VSC8531_COLLISION) | \
 116                                 BIT(VSC8531_ACTIVITY) | \
 117                                 BIT(VSC8531_AUTONEG_FAULT) | \
 118                                 BIT(VSC8531_SERIAL_MODE) | \
 119                                 BIT(VSC8531_FORCE_LED_OFF) | \
 120                                 BIT(VSC8531_FORCE_LED_ON))
 121
 122 struct vsc8531_private {
 123         int rate_magic;
 124         u16 supp_led_modes;
 125         u32 leds_mode[MAX_LEDS];
 126         u8 nleds;
 127 };
 128
 129 #ifdef CONFIG_OF_MDIO
 130 struct vsc8531_edge_rate_table {
 131         u32 vddmac;
 132         u32 slowdown[8];
 133 };
 134
 135 static const struct vsc8531_edge_rate_table edge_table[] = {
 136         {MSCC_VDDMAC_3300, { 0, 2,  4,  7, 10, 17, 29, 53} },
 137         {MSCC_VDDMAC_2500, { 0, 3,  6, 10, 14, 23, 37, 63} },
 138         {MSCC_VDDMAC_1800, { 0, 5,  9, 16, 23, 35, 52, 76} },
 139         {MSCC_VDDMAC_1500, { 0, 6, 14, 21, 29, 42, 58, 77} },
 140 };
 141 #endif /* CONFIG_OF_MDIO */
 142
 143 static int vsc85xx_phy_page_set(struct phy_device *phydev, u16 page)
 144 {
 145         int rc;
 146
 147         rc = phy_write(phydev, MSCC_EXT_PAGE_ACCESS, page);
 148         return rc;
 149 }
 150
 151 static int vsc85xx_led_cntl_set(struct phy_device *phydev,
 152                                 u8 led_num,
 153                                 u8 mode)
 154 {
 155         int rc;
 156         u16 reg_val;
 157
 158         mutex_lock(&phydev->lock);
 159         reg_val = phy_read(phydev, MSCC_PHY_LED_MODE_SEL);
 160         reg_val &= ~LED_MODE_SEL_MASK(led_num);
 161         reg_val |= LED_MODE_SEL(led_num, (u16)mode);
 162         rc = phy_write(phydev, MSCC_PHY_LED_MODE_SEL, reg_val);
 163         mutex_unlock(&phydev->lock);
 164
 165         return rc;
 166 }
 167
 168 static int vsc85xx_mdix_get(struct phy_device *phydev, u8 *mdix)
 169 {
 170         u16 reg_val;
 171
 172         reg_val = phy_read(phydev, MSCC_PHY_DEV_AUX_CNTL);
 173         if (reg_val & HP_AUTO_MDIX_X_OVER_IND_MASK)
 174                 *mdix = ETH_TP_MDI_X;
 175         else
 176                 *mdix = ETH_TP_MDI;
 177
 178         return 0;
 179 }
 180
 181 static int vsc85xx_mdix_set(struct phy_device *phydev, u8 mdix)
 182 {
 183         int rc;
 184         u16 reg_val;
 185
 186         reg_val = phy_read(phydev, MSCC_PHY_BYPASS_CONTROL);
 187         if ((mdix == ETH_TP_MDI) || (mdix == ETH_TP_MDI_X)) {
 188                 reg_val |= (DISABLE_PAIR_SWAP_CORR_MASK |
 189                             DISABLE_POLARITY_CORR_MASK  |
 190                             DISABLE_HP_AUTO_MDIX_MASK);
 191         } else {
 192                 reg_val &= ~(DISABLE_PAIR_SWAP_CORR_MASK |
 193                              DISABLE_POLARITY_CORR_MASK  |
 194                              DISABLE_HP_AUTO_MDIX_MASK);
 195         }
 196         rc = phy_write(phydev, MSCC_PHY_BYPASS_CONTROL, reg_val);
 197         if (rc != 0)
 198                 return rc;
 199
 200         rc = vsc85xx_phy_page_set(phydev, MSCC_PHY_PAGE_EXTENDED);
 201         if (rc != 0)
 202                 return rc;
 203
 204         reg_val = phy_read(phydev, MSCC_PHY_EXT_MODE_CNTL);
 205         reg_val &= ~(FORCE_MDI_CROSSOVER_MASK);
 206         if (mdix == ETH_TP_MDI)
 207                 reg_val |= FORCE_MDI_CROSSOVER_MDI;
 208         else if (mdix == ETH_TP_MDI_X)
 209                 reg_val |= FORCE_MDI_CROSSOVER_MDIX;
 210         rc = phy_write(phydev, MSCC_PHY_EXT_MODE_CNTL, reg_val);
 211         if (rc != 0)
 212                 return rc;
 213
 214         rc = vsc85xx_phy_page_set(phydev, MSCC_PHY_PAGE_STANDARD);
 215         if (rc != 0)
 216                 return rc;
 217
 218         return genphy_restart_aneg(phydev);
 219 }
 220
 221 static int vsc85xx_downshift_get(struct phy_device *phydev, u8 *count)
 222 {
 223         int rc;
 224         u16 reg_val;
 225
 226         rc = vsc85xx_phy_page_set(phydev, MSCC_PHY_PAGE_EXTENDED);
 227         if (rc != 0)
 228                 goto out;
 229
 230         reg_val = phy_read(phydev, MSCC_PHY_ACTIPHY_CNTL);
 231         reg_val &= DOWNSHIFT_CNTL_MASK;
 232         if (!(reg_val & DOWNSHIFT_EN))
 233                 *count = DOWNSHIFT_DEV_DISABLE;
 234         else
 235                 *count = ((reg_val & ~DOWNSHIFT_EN) >> DOWNSHIFT_CNTL_POS) + 2;
 236         rc = vsc85xx_phy_page_set(phydev, MSCC_PHY_PAGE_STANDARD);
 237
 238 out:
 239         return rc;
 240 }
 241
 242 static int vsc85xx_downshift_set(struct phy_device *phydev, u8 count)
 243 {
 244         int rc;
 245         u16 reg_val;
 246
 247         if (count == DOWNSHIFT_DEV_DEFAULT_COUNT) {
 248                 /* Default downshift count 3 (i.e. Bit3:2 = 0b01) */
 249                 count = ((1 << DOWNSHIFT_CNTL_POS) | DOWNSHIFT_EN);
 250         } else if (count > DOWNSHIFT_COUNT_MAX || count == 1) {
 251                 phydev_err(phydev, "Downshift count should be 2,3,4 or 5\n");
 252                 return -ERANGE;
 253         } else if (count) {
 254                 /* Downshift count is either 2,3,4 or 5 */
 255                 count = (((count - 2) << DOWNSHIFT_CNTL_POS) | DOWNSHIFT_EN);
 256         }
 257
 258         rc = vsc85xx_phy_page_set(phydev, MSCC_PHY_PAGE_EXTENDED);
 259         if (rc != 0)
 260                 goto out;
 261
 262         reg_val = phy_read(phydev, MSCC_PHY_ACTIPHY_CNTL);
 263         reg_val &= ~(DOWNSHIFT_CNTL_MASK);
 264         reg_val |= count;
 265         rc = phy_write(phydev, MSCC_PHY_ACTIPHY_CNTL, reg_val);
 266         if (rc != 0)
 267                 goto out;
 268
 269         rc = vsc85xx_phy_page_set(phydev, MSCC_PHY_PAGE_STANDARD);
 270
 271 out:
 272         return rc;
 273 }
 274
 275 static int vsc85xx_wol_set(struct phy_device *phydev,
 276                            struct ethtool_wolinfo *wol)
 277 {
 278         int rc;
 279         u16 reg_val;
 280         u8  i;
 281         u16 pwd[3] = {0, 0, 0};
 282         struct ethtool_wolinfo *wol_conf = wol;
 283         u8 *mac_addr = phydev->attached_dev->dev_addr;
 284
 285         mutex_lock(&phydev->lock);
 286         rc = vsc85xx_phy_page_set(phydev, MSCC_PHY_PAGE_EXTENDED_2);
 287         if (rc != 0)
 288                 goto out_unlock;
 289
 290         if (wol->wolopts & WAKE_MAGIC) {
 291                 /* Store the device address for the magic packet */
 292                 for (i = 0; i < ARRAY_SIZE(pwd); i++)
 293                         pwd[i] = mac_addr[5 - (i * 2 + 1)] << 8 |
 294                                  mac_addr[5 - i * 2];
 295                 phy_write(phydev, MSCC_PHY_WOL_LOWER_MAC_ADDR, pwd[0]);
 296                 phy_write(phydev, MSCC_PHY_WOL_MID_MAC_ADDR, pwd[1]);
 297                 phy_write(phydev, MSCC_PHY_WOL_UPPER_MAC_ADDR, pwd[2]);
 298         } else {
 299                 phy_write(phydev, MSCC_PHY_WOL_LOWER_MAC_ADDR, 0);
 300                 phy_write(phydev, MSCC_PHY_WOL_MID_MAC_ADDR, 0);
 301                 phy_write(phydev, MSCC_PHY_WOL_UPPER_MAC_ADDR, 0);
 302         }
 303
 304         if (wol_conf->wolopts & WAKE_MAGICSECURE) {
 305                 for (i = 0; i < ARRAY_SIZE(pwd); i++)
 306                         pwd[i] = wol_conf->sopass[5 - (i * 2 + 1)] << 8 |
 307                                  wol_conf->sopass[5 - i * 2];
 308                 phy_write(phydev, MSCC_PHY_WOL_LOWER_PASSWD, pwd[0]);
 309                 phy_write(phydev, MSCC_PHY_WOL_MID_PASSWD, pwd[1]);
 310                 phy_write(phydev, MSCC_PHY_WOL_UPPER_PASSWD, pwd[2]);
 311         } else {
 312                 phy_write(phydev, MSCC_PHY_WOL_LOWER_PASSWD, 0);
 313                 phy_write(phydev, MSCC_PHY_WOL_MID_PASSWD, 0);
 314                 phy_write(phydev, MSCC_PHY_WOL_UPPER_PASSWD, 0);
 315         }
 316
 317         reg_val = phy_read(phydev, MSCC_PHY_WOL_MAC_CONTROL);
 318         if (wol_conf->wolopts & WAKE_MAGICSECURE)
 319                 reg_val |= SECURE_ON_ENABLE;
 320         else
 321                 reg_val &= ~SECURE_ON_ENABLE;
 322         phy_write(phydev, MSCC_PHY_WOL_MAC_CONTROL, reg_val);
 323
 324         rc = vsc85xx_phy_page_set(phydev, MSCC_PHY_PAGE_STANDARD);
 325         if (rc != 0)
 326                 goto out_unlock;
 327
 328         if (wol->wolopts & WAKE_MAGIC) {
 329                 /* Enable the WOL interrupt */
 330                 reg_val = phy_read(phydev, MII_VSC85XX_INT_MASK);
 331                 reg_val |= MII_VSC85XX_INT_MASK_WOL;
 332                 rc = phy_write(phydev, MII_VSC85XX_INT_MASK, reg_val);
 333                 if (rc != 0)
 334                         goto out_unlock;
 335         } else {
 336                 /* Disable the WOL interrupt */
 337                 reg_val = phy_read(phydev, MII_VSC85XX_INT_MASK);
 338                 reg_val &= (~MII_VSC85XX_INT_MASK_WOL);
 339                 rc = phy_write(phydev, MII_VSC85XX_INT_MASK, reg_val);
 340                 if (rc != 0)
 341                         goto out_unlock;
 342         }
 343         /* Clear WOL iterrupt status */
 344         reg_val = phy_read(phydev, MII_VSC85XX_INT_STATUS);
 345
 346 out_unlock:
 347         mutex_unlock(&phydev->lock);
 348
 349         return rc;
 350 }
 351
 352 static void vsc85xx_wol_get(struct phy_device *phydev,
 353                             struct ethtool_wolinfo *wol)
 354 {
 355         int rc;
 356         u16 reg_val;
 357         u8  i;
 358         u16 pwd[3] = {0, 0, 0};
 359         struct ethtool_wolinfo *wol_conf = wol;
 360
 361         mutex_lock(&phydev->lock);
 362         rc = vsc85xx_phy_page_set(phydev, MSCC_PHY_PAGE_EXTENDED_2);
 363         if (rc != 0)
 364                 goto out_unlock;
 365
 366         reg_val = phy_read(phydev, MSCC_PHY_WOL_MAC_CONTROL);
 367         if (reg_val & SECURE_ON_ENABLE)
 368                 wol_conf->wolopts |= WAKE_MAGICSECURE;
 369         if (wol_conf->wolopts & WAKE_MAGICSECURE) {
 370                 pwd[0] = phy_read(phydev, MSCC_PHY_WOL_LOWER_PASSWD);
 371                 pwd[1] = phy_read(phydev, MSCC_PHY_WOL_MID_PASSWD);
 372                 pwd[2] = phy_read(phydev, MSCC_PHY_WOL_UPPER_PASSWD);
 373                 for (i = 0; i < ARRAY_SIZE(pwd); i++) {
 374                         wol_conf->sopass[5 - i * 2] = pwd[i] & 0x00ff;
 375                         wol_conf->sopass[5 - (i * 2 + 1)] = (pwd[i] & 0xff00)
 376                                                             >> 8;
 377                 }
 378         }
 379
 380         rc = vsc85xx_phy_page_set(phydev, MSCC_PHY_PAGE_STANDARD);
 381
 382 out_unlock:
 383         mutex_unlock(&phydev->lock);
 384 }
 385
 386 #ifdef CONFIG_OF_MDIO
 387 static int vsc85xx_edge_rate_magic_get(struct phy_device *phydev)
 388 {
 389         u32 vdd, sd;
 390         int rc, i, j;
 391         struct device *dev = &phydev->mdio.dev;
 392         struct device_node *of_node = dev->of_node;
 393         u8 sd_array_size = ARRAY_SIZE(edge_table[0].slowdown);
 394
 395         if (!of_node)
 396                 return -ENODEV;
 397
 398         rc = of_property_read_u32(of_node, "vsc8531,vddmac", &vdd);
 399         if (rc != 0)
 400                 vdd = MSCC_VDDMAC_3300;
 401
 402         rc = of_property_read_u32(of_node, "vsc8531,edge-slowdown", &sd);
 403         if (rc != 0)
 404                 sd = 0;
 405
 406         for (i = 0; i < ARRAY_SIZE(edge_table); i++)
 407                 if (edge_table[i].vddmac == vdd)
 408                         for (j = 0; j < sd_array_size; j++)
 409                                 if (edge_table[i].slowdown[j] == sd)
 410                                         return (sd_array_size - j - 1);
 411
 412         return -EINVAL;
 413 }
 414
 415 static int vsc85xx_dt_led_mode_get(struct phy_device *phydev,
 416                                    char *led,
 417                                    u32 default_mode)
 418 {
 419         struct vsc8531_private *priv = phydev->priv;
 420         struct device *dev = &phydev->mdio.dev;
 421         struct device_node *of_node = dev->of_node;
 422         u32 led_mode;
 423         int err;
 424
 425         if (!of_node)
 426                 return -ENODEV;
 427
 428         led_mode = default_mode;
 429         err = of_property_read_u32(of_node, led, &led_mode);
 430         if (!err && !(BIT(led_mode) & priv->supp_led_modes)) {
 431                 phydev_err(phydev, "DT %s invalid\n", led);
 432                 return -EINVAL;
 433         }
 434
 435         return led_mode;
 436 }
 437
 438 #else
 439 static int vsc85xx_edge_rate_magic_get(struct phy_device *phydev)
 440 {
 441         return 0;
 442 }
 443
 444 static int vsc85xx_dt_led_mode_get(struct phy_device *phydev,
 445                                    char *led,
 446                                    u8 default_mode)
 447 {
 448         return default_mode;
 449 }
 450 #endif /* CONFIG_OF_MDIO */
 451
 452 static int vsc85xx_dt_led_modes_get(struct phy_device *phydev,
 453                                     u32 *default_mode)
 454 {
 455         struct vsc8531_private *priv = phydev->priv;
 456         char led_dt_prop[28];
 457         int i, ret;
 458
 459         for (i = 0; i < priv->nleds; i++) {
 460                 ret = sprintf(led_dt_prop, "vsc8531,led-%d-mode", i);
 461                 if (ret < 0)
 462                         return ret;
 463
 464                 ret = vsc85xx_dt_led_mode_get(phydev, led_dt_prop,
 465                                               default_mode[i]);
 466                 if (ret < 0)
 467                         return ret;
 468                 priv->leds_mode[i] = ret;
 469         }
 470
 471         return 0;
 472 }
 473
 474 static int vsc85xx_edge_rate_cntl_set(struct phy_device *phydev, u8 edge_rate)
 475 {
 476         int rc;
 477         u16 reg_val;
 478
 479         mutex_lock(&phydev->lock);
 480         rc = vsc85xx_phy_page_set(phydev, MSCC_PHY_PAGE_EXTENDED_2);
 481         if (rc != 0)
 482                 goto out_unlock;
 483         reg_val = phy_read(phydev, MSCC_PHY_WOL_MAC_CONTROL);
 484         reg_val &= ~(EDGE_RATE_CNTL_MASK);
 485         reg_val |= (edge_rate << EDGE_RATE_CNTL_POS);
 486         rc = phy_write(phydev, MSCC_PHY_WOL_MAC_CONTROL, reg_val);
 487         if (rc != 0)
 488                 goto out_unlock;
 489         rc = vsc85xx_phy_page_set(phydev, MSCC_PHY_PAGE_STANDARD);
 490
 491 out_unlock:
 492         mutex_unlock(&phydev->lock);
 493
 494         return rc;
 495 }
 496
 497 static int vsc85xx_mac_if_set(struct phy_device *phydev,
 498                               phy_interface_t interface)
 499 {
 500         int rc;
 501         u16 reg_val;
 502
 503         mutex_lock(&phydev->lock);
 504         reg_val = phy_read(phydev, MSCC_PHY_EXT_PHY_CNTL_1);
 505         reg_val &= ~(MAC_IF_SELECTION_MASK);
 506         switch (interface) {
 507         case PHY_INTERFACE_MODE_RGMII:
 508                 reg_val |= (MAC_IF_SELECTION_RGMII << MAC_IF_SELECTION_POS);
 509                 break;
 510         case PHY_INTERFACE_MODE_RMII:
 511                 reg_val |= (MAC_IF_SELECTION_RMII << MAC_IF_SELECTION_POS);
 512                 break;
 513         case PHY_INTERFACE_MODE_MII:
 514         case PHY_INTERFACE_MODE_GMII:
 515                 reg_val |= (MAC_IF_SELECTION_GMII << MAC_IF_SELECTION_POS);
 516                 break;
 517         default:
 518                 rc = -EINVAL;
 519                 goto out_unlock;
 520         }
 521         rc = phy_write(phydev, MSCC_PHY_EXT_PHY_CNTL_1, reg_val);
 522         if (rc != 0)
 523                 goto out_unlock;
 524
 525         rc = genphy_soft_reset(phydev);
 526
 527 out_unlock:
 528         mutex_unlock(&phydev->lock);
 529
 530         return rc;
 531 }
 532
 533 static int vsc85xx_default_config(struct phy_device *phydev)
 534 {
 535         int rc;
 536         u16 reg_val;
 537
 538         phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
 539         mutex_lock(&phydev->lock);
 540         rc = vsc85xx_phy_page_set(phydev, MSCC_PHY_PAGE_EXTENDED_2);
 541         if (rc != 0)
 542                 goto out_unlock;
 543
 544         reg_val = phy_read(phydev, MSCC_PHY_RGMII_CNTL);
 545         reg_val &= ~(RGMII_RX_CLK_DELAY_MASK);
 546         reg_val |= (RGMII_RX_CLK_DELAY_1_1_NS << RGMII_RX_CLK_DELAY_POS);
 547         phy_write(phydev, MSCC_PHY_RGMII_CNTL, reg_val);
 548         rc = vsc85xx_phy_page_set(phydev, MSCC_PHY_PAGE_STANDARD);
 549
 550 out_unlock:
 551         mutex_unlock(&phydev->lock);
 552
 553         return rc;
 554 }
 555
 556 static int vsc85xx_get_tunable(struct phy_device *phydev,
 557                                struct ethtool_tunable *tuna, void *data)
 558 {
 559         switch (tuna->id) {
 560         case ETHTOOL_PHY_DOWNSHIFT:
 561                 return vsc85xx_downshift_get(phydev, (u8 *)data);
 562         default:
 563                 return -EINVAL;
 564         }
 565 }
 566
 567 static int vsc85xx_set_tunable(struct phy_device *phydev,
 568                                struct ethtool_tunable *tuna,
 569                                const void *data)
 570 {
 571         switch (tuna->id) {
 572         case ETHTOOL_PHY_DOWNSHIFT:
 573                 return vsc85xx_downshift_set(phydev, *(u8 *)data);
 574         default:
 575                 return -EINVAL;
 576         }
 577 }
 578
 579 static int vsc85xx_config_init(struct phy_device *phydev)
 580 {
 581         int rc, i;
 582         struct vsc8531_private *vsc8531 = phydev->priv;
 583
 584         rc = vsc85xx_default_config(phydev);
 585         if (rc)
 586                 return rc;
 587
 588         rc = vsc85xx_mac_if_set(phydev, phydev->interface);
 589         if (rc)
 590                 return rc;
 591
 592         rc = vsc85xx_edge_rate_cntl_set(phydev, vsc8531->rate_magic);
 593         if (rc)
 594                 return rc;
 595
 596         for (i = 0; i < vsc8531->nleds; i++) {
 597                 rc = vsc85xx_led_cntl_set(phydev, i, vsc8531->leds_mode[i]);
 598                 if (rc)
 599                         return rc;
 600         }
 601
 602         rc = genphy_config_init(phydev);
 603
 604         return rc;
 605 }
 606
 607 static int vsc85xx_ack_interrupt(struct phy_device *phydev)
 608 {
 609         int rc = 0;
 610
 611         if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
 612                 rc = phy_read(phydev, MII_VSC85XX_INT_STATUS);
 613
 614         return (rc < 0) ? rc : 0;
 615 }
 616
 617 static int vsc85xx_config_intr(struct phy_device *phydev)
 618 {
 619         int rc;
 620
 621         if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
 622                 rc = phy_write(phydev, MII_VSC85XX_INT_MASK,
 623                                MII_VSC85XX_INT_MASK_MASK);
 624         } else {
 625                 rc = phy_write(phydev, MII_VSC85XX_INT_MASK, 0);
 626                 if (rc < 0)
 627                         return rc;
 628                 rc = phy_read(phydev, MII_VSC85XX_INT_STATUS);
 629         }
 630
 631         return rc;
 632 }
 633
 634 static int vsc85xx_config_aneg(struct phy_device *phydev)
 635 {
 636         int rc;
 637
 638         rc = vsc85xx_mdix_set(phydev, phydev->mdix_ctrl);
 639         if (rc < 0)
 640                 return rc;
 641
 642         return genphy_config_aneg(phydev);
 643 }
 644
 645 static int vsc85xx_read_status(struct phy_device *phydev)
 646 {
 647         int rc;
 648
 649         rc = vsc85xx_mdix_get(phydev, &phydev->mdix);
 650         if (rc < 0)
 651                 return rc;
 652
 653         return genphy_read_status(phydev);
 654 }
 655
 656 static int vsc85xx_probe(struct phy_device *phydev)
 657 {
 658         struct vsc8531_private *vsc8531;
 659         int rate_magic;
 660         u32 default_mode[2] = {VSC8531_LINK_1000_ACTIVITY,
 661            VSC8531_LINK_100_ACTIVITY};
 662
 663         rate_magic = vsc85xx_edge_rate_magic_get(phydev);
 664         if (rate_magic < 0)
 665                 return rate_magic;
 666
 667         vsc8531 = devm_kzalloc(&phydev->mdio.dev, sizeof(*vsc8531), GFP_KERNEL);
 668         if (!vsc8531)
 669                 return -ENOMEM;
 670
 671         phydev->priv = vsc8531;
 672
 673         vsc8531->rate_magic = rate_magic;
 674         vsc8531->nleds = 2;
 675         vsc8531->supp_led_modes = VSC85XX_SUPP_LED_MODES;
 676
 677         return vsc85xx_dt_led_modes_get(phydev, default_mode);
 678 }
 679
 680 /* Microsemi VSC85xx PHYs */
 681 static struct phy_driver vsc85xx_driver[] = {
 682 {
 683         .phy_id         = PHY_ID_VSC8530,
 684         .name           = "Microsemi FE VSC8530",
 685         .phy_id_mask    = 0xfffffff0,
 686         .features       = PHY_BASIC_FEATURES,
 687         .flags          = PHY_HAS_INTERRUPT,
 688         .soft_reset     = &genphy_soft_reset,
 689         .config_init    = &vsc85xx_config_init,
 690         .config_aneg    = &vsc85xx_config_aneg,
 691         .aneg_done      = &genphy_aneg_done,
 692         .read_status    = &vsc85xx_read_status,
 693         .ack_interrupt  = &vsc85xx_ack_interrupt,
 694         .config_intr    = &vsc85xx_config_intr,
 695         .suspend        = &genphy_suspend,
 696         .resume         = &genphy_resume,
 697         .probe          = &vsc85xx_probe,
 698         .set_wol        = &vsc85xx_wol_set,
 699         .get_wol        = &vsc85xx_wol_get,
 700         .get_tunable    = &vsc85xx_get_tunable,
 701         .set_tunable    = &vsc85xx_set_tunable,
 702 },
 703 {
 704         .phy_id         = PHY_ID_VSC8531,
 705         .name           = "Microsemi VSC8531",
 706         .phy_id_mask    = 0xfffffff0,
 707         .features       = PHY_GBIT_FEATURES,
 708         .flags          = PHY_HAS_INTERRUPT,
 709         .soft_reset     = &genphy_soft_reset,
 710         .config_init    = &vsc85xx_config_init,
 711         .config_aneg    = &vsc85xx_config_aneg,
 712         .aneg_done      = &genphy_aneg_done,
 713         .read_status    = &vsc85xx_read_status,
 714         .ack_interrupt  = &vsc85xx_ack_interrupt,
 715         .config_intr    = &vsc85xx_config_intr,
 716         .suspend        = &genphy_suspend,
 717         .resume         = &genphy_resume,
 718         .probe          = &vsc85xx_probe,
 719         .set_wol        = &vsc85xx_wol_set,
 720         .get_wol        = &vsc85xx_wol_get,
 721         .get_tunable    = &vsc85xx_get_tunable,
 722         .set_tunable    = &vsc85xx_set_tunable,
 723 },
 724 {
 725         .phy_id         = PHY_ID_VSC8540,
 726         .name           = "Microsemi FE VSC8540 SyncE",
 727         .phy_id_mask    = 0xfffffff0,
 728         .features       = PHY_BASIC_FEATURES,
 729         .flags          = PHY_HAS_INTERRUPT,
 730         .soft_reset     = &genphy_soft_reset,
 731         .config_init    = &vsc85xx_config_init,
 732         .config_aneg    = &vsc85xx_config_aneg,
 733         .aneg_done      = &genphy_aneg_done,
 734         .read_status    = &vsc85xx_read_status,
 735         .ack_interrupt  = &vsc85xx_ack_interrupt,
 736         .config_intr    = &vsc85xx_config_intr,
 737         .suspend        = &genphy_suspend,
 738         .resume         = &genphy_resume,
 739         .probe          = &vsc85xx_probe,
 740         .set_wol        = &vsc85xx_wol_set,
 741         .get_wol        = &vsc85xx_wol_get,
 742         .get_tunable    = &vsc85xx_get_tunable,
 743         .set_tunable    = &vsc85xx_set_tunable,
 744 },
 745 {
 746         .phy_id         = PHY_ID_VSC8541,
 747         .name           = "Microsemi VSC8541 SyncE",
 748         .phy_id_mask    = 0xfffffff0,
 749         .features       = PHY_GBIT_FEATURES,
 750         .flags          = PHY_HAS_INTERRUPT,
 751         .soft_reset     = &genphy_soft_reset,
 752         .config_init    = &vsc85xx_config_init,
 753         .config_aneg    = &vsc85xx_config_aneg,
 754         .aneg_done      = &genphy_aneg_done,
 755         .read_status    = &vsc85xx_read_status,
 756         .ack_interrupt  = &vsc85xx_ack_interrupt,
 757         .config_intr    = &vsc85xx_config_intr,
 758         .suspend        = &genphy_suspend,
 759         .resume         = &genphy_resume,
 760         .probe          = &vsc85xx_probe,
 761         .set_wol        = &vsc85xx_wol_set,
 762         .get_wol        = &vsc85xx_wol_get,
 763         .get_tunable    = &vsc85xx_get_tunable,
 764         .set_tunable    = &vsc85xx_set_tunable,
 765 }
 766
 767 };
 768
 769 module_phy_driver(vsc85xx_driver);
 770
 771 static struct mdio_device_id __maybe_unused vsc85xx_tbl[] = {
 772         { PHY_ID_VSC8530, 0xfffffff0, },
 773         { PHY_ID_VSC8531, 0xfffffff0, },
 774         { PHY_ID_VSC8540, 0xfffffff0, },
 775         { PHY_ID_VSC8541, 0xfffffff0, },
 776         { }
 777 };
 778
 779 MODULE_DEVICE_TABLE(mdio, vsc85xx_tbl);
 780
 781 MODULE_DESCRIPTION("Microsemi VSC85xx PHY driver");
 782 MODULE_AUTHOR("Nagaraju Lakkaraju");
 783 MODULE_LICENSE("Dual MIT/GPL");