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1 /*
2  *  Copyright (c) 2014 Realtek Semiconductor Corp. All rights reserved.
3  *
4  * This program is free software; you can redistribute it and/or
5  * modify it under the terms of the GNU General Public License
6  * version 2 as published by the Free Software Foundation.
7  *
8  */
9
10 #include <linux/signal.h>
11 #include <linux/slab.h>
12 #include <linux/module.h>
13 #include <linux/netdevice.h>
14 #include <linux/etherdevice.h>
15 #include <linux/mii.h>
16 #include <linux/ethtool.h>
17 #include <linux/usb.h>
18 #include <linux/crc32.h>
19 #include <linux/if_vlan.h>
20 #include <linux/uaccess.h>
21 #include <linux/list.h>
22 #include <linux/ip.h>
23 #include <linux/ipv6.h>
24 #include <net/ip6_checksum.h>
25 #include <uapi/linux/mdio.h>
26 #include <linux/mdio.h>
27 #include <linux/usb/cdc.h>
28 #include <linux/suspend.h>
29 #include <linux/acpi.h>
30
31 /* Information for net-next */
32 #define NETNEXT_VERSION         "09"
33
34 /* Information for net */
35 #define NET_VERSION             "9"
36
37 #define DRIVER_VERSION          "v1." NETNEXT_VERSION "." NET_VERSION
38 #define DRIVER_AUTHOR "Realtek linux nic maintainers <nic_swsd@realtek.com>"
39 #define DRIVER_DESC "Realtek RTL8152/RTL8153 Based USB Ethernet Adapters"
40 #define MODULENAME "r8152"
41
42 #define R8152_PHY_ID            32
43
44 #define PLA_IDR                 0xc000
45 #define PLA_RCR                 0xc010
46 #define PLA_RMS                 0xc016
47 #define PLA_RXFIFO_CTRL0        0xc0a0
48 #define PLA_RXFIFO_CTRL1        0xc0a4
49 #define PLA_RXFIFO_CTRL2        0xc0a8
50 #define PLA_DMY_REG0            0xc0b0
51 #define PLA_FMC                 0xc0b4
52 #define PLA_CFG_WOL             0xc0b6
53 #define PLA_TEREDO_CFG          0xc0bc
54 #define PLA_TEREDO_WAKE_BASE    0xc0c4
55 #define PLA_MAR                 0xcd00
56 #define PLA_BACKUP              0xd000
57 #define PAL_BDC_CR              0xd1a0
58 #define PLA_TEREDO_TIMER        0xd2cc
59 #define PLA_REALWOW_TIMER       0xd2e8
60 #define PLA_EFUSE_DATA          0xdd00
61 #define PLA_EFUSE_CMD           0xdd02
62 #define PLA_LEDSEL              0xdd90
63 #define PLA_LED_FEATURE         0xdd92
64 #define PLA_PHYAR               0xde00
65 #define PLA_BOOT_CTRL           0xe004
66 #define PLA_GPHY_INTR_IMR       0xe022
67 #define PLA_EEE_CR              0xe040
68 #define PLA_EEEP_CR             0xe080
69 #define PLA_MAC_PWR_CTRL        0xe0c0
70 #define PLA_MAC_PWR_CTRL2       0xe0ca
71 #define PLA_MAC_PWR_CTRL3       0xe0cc
72 #define PLA_MAC_PWR_CTRL4       0xe0ce
73 #define PLA_WDT6_CTRL           0xe428
74 #define PLA_TCR0                0xe610
75 #define PLA_TCR1                0xe612
76 #define PLA_MTPS                0xe615
77 #define PLA_TXFIFO_CTRL         0xe618
78 #define PLA_RSTTALLY            0xe800
79 #define PLA_CR                  0xe813
80 #define PLA_CRWECR              0xe81c
81 #define PLA_CONFIG12            0xe81e  /* CONFIG1, CONFIG2 */
82 #define PLA_CONFIG34            0xe820  /* CONFIG3, CONFIG4 */
83 #define PLA_CONFIG5             0xe822
84 #define PLA_PHY_PWR             0xe84c
85 #define PLA_OOB_CTRL            0xe84f
86 #define PLA_CPCR                0xe854
87 #define PLA_MISC_0              0xe858
88 #define PLA_MISC_1              0xe85a
89 #define PLA_OCP_GPHY_BASE       0xe86c
90 #define PLA_TALLYCNT            0xe890
91 #define PLA_SFF_STS_7           0xe8de
92 #define PLA_PHYSTATUS           0xe908
93 #define PLA_BP_BA               0xfc26
94 #define PLA_BP_0                0xfc28
95 #define PLA_BP_1                0xfc2a
96 #define PLA_BP_2                0xfc2c
97 #define PLA_BP_3                0xfc2e
98 #define PLA_BP_4                0xfc30
99 #define PLA_BP_5                0xfc32
100 #define PLA_BP_6                0xfc34
101 #define PLA_BP_7                0xfc36
102 #define PLA_BP_EN               0xfc38
103
104 #define USB_USB2PHY             0xb41e
105 #define USB_SSPHYLINK2          0xb428
106 #define USB_U2P3_CTRL           0xb460
107 #define USB_CSR_DUMMY1          0xb464
108 #define USB_CSR_DUMMY2          0xb466
109 #define USB_DEV_STAT            0xb808
110 #define USB_CONNECT_TIMER       0xcbf8
111 #define USB_MSC_TIMER           0xcbfc
112 #define USB_BURST_SIZE          0xcfc0
113 #define USB_LPM_CONFIG          0xcfd8
114 #define USB_USB_CTRL            0xd406
115 #define USB_PHY_CTRL            0xd408
116 #define USB_TX_AGG              0xd40a
117 #define USB_RX_BUF_TH           0xd40c
118 #define USB_USB_TIMER           0xd428
119 #define USB_RX_EARLY_TIMEOUT    0xd42c
120 #define USB_RX_EARLY_SIZE       0xd42e
121 #define USB_PM_CTRL_STATUS      0xd432  /* RTL8153A */
122 #define USB_RX_EXTRA_AGGR_TMR   0xd432  /* RTL8153B */
123 #define USB_TX_DMA              0xd434
124 #define USB_UPT_RXDMA_OWN       0xd437
125 #define USB_TOLERANCE           0xd490
126 #define USB_LPM_CTRL            0xd41a
127 #define USB_BMU_RESET           0xd4b0
128 #define USB_U1U2_TIMER          0xd4da
129 #define USB_UPS_CTRL            0xd800
130 #define USB_POWER_CUT           0xd80a
131 #define USB_MISC_0              0xd81a
132 #define USB_MISC_1              0xd81f
133 #define USB_AFE_CTRL2           0xd824
134 #define USB_UPS_CFG             0xd842
135 #define USB_UPS_FLAGS           0xd848
136 #define USB_WDT11_CTRL          0xe43c
137 #define USB_BP_BA               0xfc26
138 #define USB_BP_0                0xfc28
139 #define USB_BP_1                0xfc2a
140 #define USB_BP_2                0xfc2c
141 #define USB_BP_3                0xfc2e
142 #define USB_BP_4                0xfc30
143 #define USB_BP_5                0xfc32
144 #define USB_BP_6                0xfc34
145 #define USB_BP_7                0xfc36
146 #define USB_BP_EN               0xfc38
147 #define USB_BP_8                0xfc38
148 #define USB_BP_9                0xfc3a
149 #define USB_BP_10               0xfc3c
150 #define USB_BP_11               0xfc3e
151 #define USB_BP_12               0xfc40
152 #define USB_BP_13               0xfc42
153 #define USB_BP_14               0xfc44
154 #define USB_BP_15               0xfc46
155 #define USB_BP2_EN              0xfc48
156
157 /* OCP Registers */
158 #define OCP_ALDPS_CONFIG        0x2010
159 #define OCP_EEE_CONFIG1         0x2080
160 #define OCP_EEE_CONFIG2         0x2092
161 #define OCP_EEE_CONFIG3         0x2094
162 #define OCP_BASE_MII            0xa400
163 #define OCP_EEE_AR              0xa41a
164 #define OCP_EEE_DATA            0xa41c
165 #define OCP_PHY_STATUS          0xa420
166 #define OCP_NCTL_CFG            0xa42c
167 #define OCP_POWER_CFG           0xa430
168 #define OCP_EEE_CFG             0xa432
169 #define OCP_SRAM_ADDR           0xa436
170 #define OCP_SRAM_DATA           0xa438
171 #define OCP_DOWN_SPEED          0xa442
172 #define OCP_EEE_ABLE            0xa5c4
173 #define OCP_EEE_ADV             0xa5d0
174 #define OCP_EEE_LPABLE          0xa5d2
175 #define OCP_PHY_STATE           0xa708          /* nway state for 8153 */
176 #define OCP_PHY_PATCH_STAT      0xb800
177 #define OCP_PHY_PATCH_CMD       0xb820
178 #define OCP_ADC_IOFFSET         0xbcfc
179 #define OCP_ADC_CFG             0xbc06
180 #define OCP_SYSCLK_CFG          0xc416
181
182 /* SRAM Register */
183 #define SRAM_GREEN_CFG          0x8011
184 #define SRAM_LPF_CFG            0x8012
185 #define SRAM_10M_AMP1           0x8080
186 #define SRAM_10M_AMP2           0x8082
187 #define SRAM_IMPEDANCE          0x8084
188
189 /* PLA_RCR */
190 #define RCR_AAP                 0x00000001
191 #define RCR_APM                 0x00000002
192 #define RCR_AM                  0x00000004
193 #define RCR_AB                  0x00000008
194 #define RCR_ACPT_ALL            (RCR_AAP | RCR_APM | RCR_AM | RCR_AB)
195
196 /* PLA_RXFIFO_CTRL0 */
197 #define RXFIFO_THR1_NORMAL      0x00080002
198 #define RXFIFO_THR1_OOB         0x01800003
199
200 /* PLA_RXFIFO_CTRL1 */
201 #define RXFIFO_THR2_FULL        0x00000060
202 #define RXFIFO_THR2_HIGH        0x00000038
203 #define RXFIFO_THR2_OOB         0x0000004a
204 #define RXFIFO_THR2_NORMAL      0x00a0
205
206 /* PLA_RXFIFO_CTRL2 */
207 #define RXFIFO_THR3_FULL        0x00000078
208 #define RXFIFO_THR3_HIGH        0x00000048
209 #define RXFIFO_THR3_OOB         0x0000005a
210 #define RXFIFO_THR3_NORMAL      0x0110
211
212 /* PLA_TXFIFO_CTRL */
213 #define TXFIFO_THR_NORMAL       0x00400008
214 #define TXFIFO_THR_NORMAL2      0x01000008
215
216 /* PLA_DMY_REG0 */
217 #define ECM_ALDPS               0x0002
218
219 /* PLA_FMC */
220 #define FMC_FCR_MCU_EN          0x0001
221
222 /* PLA_EEEP_CR */
223 #define EEEP_CR_EEEP_TX         0x0002
224
225 /* PLA_WDT6_CTRL */
226 #define WDT6_SET_MODE           0x0010
227
228 /* PLA_TCR0 */
229 #define TCR0_TX_EMPTY           0x0800
230 #define TCR0_AUTO_FIFO          0x0080
231
232 /* PLA_TCR1 */
233 #define VERSION_MASK            0x7cf0
234
235 /* PLA_MTPS */
236 #define MTPS_JUMBO              (12 * 1024 / 64)
237 #define MTPS_DEFAULT            (6 * 1024 / 64)
238
239 /* PLA_RSTTALLY */
240 #define TALLY_RESET             0x0001
241
242 /* PLA_CR */
243 #define CR_RST                  0x10
244 #define CR_RE                   0x08
245 #define CR_TE                   0x04
246
247 /* PLA_CRWECR */
248 #define CRWECR_NORAML           0x00
249 #define CRWECR_CONFIG           0xc0
250
251 /* PLA_OOB_CTRL */
252 #define NOW_IS_OOB              0x80
253 #define TXFIFO_EMPTY            0x20
254 #define RXFIFO_EMPTY            0x10
255 #define LINK_LIST_READY         0x02
256 #define DIS_MCU_CLROOB          0x01
257 #define FIFO_EMPTY              (TXFIFO_EMPTY | RXFIFO_EMPTY)
258
259 /* PLA_MISC_1 */
260 #define RXDY_GATED_EN           0x0008
261
262 /* PLA_SFF_STS_7 */
263 #define RE_INIT_LL              0x8000
264 #define MCU_BORW_EN             0x4000
265
266 /* PLA_CPCR */
267 #define CPCR_RX_VLAN            0x0040
268
269 /* PLA_CFG_WOL */
270 #define MAGIC_EN                0x0001
271
272 /* PLA_TEREDO_CFG */
273 #define TEREDO_SEL              0x8000
274 #define TEREDO_WAKE_MASK        0x7f00
275 #define TEREDO_RS_EVENT_MASK    0x00fe
276 #define OOB_TEREDO_EN           0x0001
277
278 /* PAL_BDC_CR */
279 #define ALDPS_PROXY_MODE        0x0001
280
281 /* PLA_EFUSE_CMD */
282 #define EFUSE_READ_CMD          BIT(15)
283 #define EFUSE_DATA_BIT16        BIT(7)
284
285 /* PLA_CONFIG34 */
286 #define LINK_ON_WAKE_EN         0x0010
287 #define LINK_OFF_WAKE_EN        0x0008
288
289 /* PLA_CONFIG5 */
290 #define BWF_EN                  0x0040
291 #define MWF_EN                  0x0020
292 #define UWF_EN                  0x0010
293 #define LAN_WAKE_EN             0x0002
294
295 /* PLA_LED_FEATURE */
296 #define LED_MODE_MASK           0x0700
297
298 /* PLA_PHY_PWR */
299 #define TX_10M_IDLE_EN          0x0080
300 #define PFM_PWM_SWITCH          0x0040
301
302 /* PLA_MAC_PWR_CTRL */
303 #define D3_CLK_GATED_EN         0x00004000
304 #define MCU_CLK_RATIO           0x07010f07
305 #define MCU_CLK_RATIO_MASK      0x0f0f0f0f
306 #define ALDPS_SPDWN_RATIO       0x0f87
307
308 /* PLA_MAC_PWR_CTRL2 */
309 #define EEE_SPDWN_RATIO         0x8007
310 #define MAC_CLK_SPDWN_EN        BIT(15)
311
312 /* PLA_MAC_PWR_CTRL3 */
313 #define PKT_AVAIL_SPDWN_EN      0x0100
314 #define SUSPEND_SPDWN_EN        0x0004
315 #define U1U2_SPDWN_EN           0x0002
316 #define L1_SPDWN_EN             0x0001
317
318 /* PLA_MAC_PWR_CTRL4 */
319 #define PWRSAVE_SPDWN_EN        0x1000
320 #define RXDV_SPDWN_EN           0x0800
321 #define TX10MIDLE_EN            0x0100
322 #define TP100_SPDWN_EN          0x0020
323 #define TP500_SPDWN_EN          0x0010
324 #define TP1000_SPDWN_EN         0x0008
325 #define EEE_SPDWN_EN            0x0001
326
327 /* PLA_GPHY_INTR_IMR */
328 #define GPHY_STS_MSK            0x0001
329 #define SPEED_DOWN_MSK          0x0002
330 #define SPDWN_RXDV_MSK          0x0004
331 #define SPDWN_LINKCHG_MSK       0x0008
332
333 /* PLA_PHYAR */
334 #define PHYAR_FLAG              0x80000000
335
336 /* PLA_EEE_CR */
337 #define EEE_RX_EN               0x0001
338 #define EEE_TX_EN               0x0002
339
340 /* PLA_BOOT_CTRL */
341 #define AUTOLOAD_DONE           0x0002
342
343 /* USB_USB2PHY */
344 #define USB2PHY_SUSPEND         0x0001
345 #define USB2PHY_L1              0x0002
346
347 /* USB_SSPHYLINK2 */
348 #define pwd_dn_scale_mask       0x3ffe
349 #define pwd_dn_scale(x)         ((x) << 1)
350
351 /* USB_CSR_DUMMY1 */
352 #define DYNAMIC_BURST           0x0001
353
354 /* USB_CSR_DUMMY2 */
355 #define EP4_FULL_FC             0x0001
356
357 /* USB_DEV_STAT */
358 #define STAT_SPEED_MASK         0x0006
359 #define STAT_SPEED_HIGH         0x0000
360 #define STAT_SPEED_FULL         0x0002
361
362 /* USB_LPM_CONFIG */
363 #define LPM_U1U2_EN             BIT(0)
364
365 /* USB_TX_AGG */
366 #define TX_AGG_MAX_THRESHOLD    0x03
367
368 /* USB_RX_BUF_TH */
369 #define RX_THR_SUPPER           0x0c350180
370 #define RX_THR_HIGH             0x7a120180
371 #define RX_THR_SLOW             0xffff0180
372 #define RX_THR_B                0x00010001
373
374 /* USB_TX_DMA */
375 #define TEST_MODE_DISABLE       0x00000001
376 #define TX_SIZE_ADJUST1         0x00000100
377
378 /* USB_BMU_RESET */
379 #define BMU_RESET_EP_IN         0x01
380 #define BMU_RESET_EP_OUT        0x02
381
382 /* USB_UPT_RXDMA_OWN */
383 #define OWN_UPDATE              BIT(0)
384 #define OWN_CLEAR               BIT(1)
385
386 /* USB_UPS_CTRL */
387 #define POWER_CUT               0x0100
388
389 /* USB_PM_CTRL_STATUS */
390 #define RESUME_INDICATE         0x0001
391
392 /* USB_USB_CTRL */
393 #define RX_AGG_DISABLE          0x0010
394 #define RX_ZERO_EN              0x0080
395
396 /* USB_U2P3_CTRL */
397 #define U2P3_ENABLE             0x0001
398
399 /* USB_POWER_CUT */
400 #define PWR_EN                  0x0001
401 #define PHASE2_EN               0x0008
402 #define UPS_EN                  BIT(4)
403 #define USP_PREWAKE             BIT(5)
404
405 /* USB_MISC_0 */
406 #define PCUT_STATUS             0x0001
407
408 /* USB_RX_EARLY_TIMEOUT */
409 #define COALESCE_SUPER           85000U
410 #define COALESCE_HIGH           250000U
411 #define COALESCE_SLOW           524280U
412
413 /* USB_WDT11_CTRL */
414 #define TIMER11_EN              0x0001
415
416 /* USB_LPM_CTRL */
417 /* bit 4 ~ 5: fifo empty boundary */
418 #define FIFO_EMPTY_1FB          0x30    /* 0x1fb * 64 = 32448 bytes */
419 /* bit 2 ~ 3: LMP timer */
420 #define LPM_TIMER_MASK          0x0c
421 #define LPM_TIMER_500MS         0x04    /* 500 ms */
422 #define LPM_TIMER_500US         0x0c    /* 500 us */
423 #define ROK_EXIT_LPM            0x02
424
425 /* USB_AFE_CTRL2 */
426 #define SEN_VAL_MASK            0xf800
427 #define SEN_VAL_NORMAL          0xa000
428 #define SEL_RXIDLE              0x0100
429
430 /* USB_UPS_CFG */
431 #define SAW_CNT_1MS_MASK        0x0fff
432
433 /* USB_UPS_FLAGS */
434 #define UPS_FLAGS_R_TUNE                BIT(0)
435 #define UPS_FLAGS_EN_10M_CKDIV          BIT(1)
436 #define UPS_FLAGS_250M_CKDIV            BIT(2)
437 #define UPS_FLAGS_EN_ALDPS              BIT(3)
438 #define UPS_FLAGS_CTAP_SHORT_DIS        BIT(4)
439 #define UPS_FLAGS_SPEED_MASK            (0xf << 16)
440 #define ups_flags_speed(x)              ((x) << 16)
441 #define UPS_FLAGS_EN_EEE                BIT(20)
442 #define UPS_FLAGS_EN_500M_EEE           BIT(21)
443 #define UPS_FLAGS_EN_EEE_CKDIV          BIT(22)
444 #define UPS_FLAGS_EEE_PLLOFF_GIGA       BIT(24)
445 #define UPS_FLAGS_EEE_CMOD_LV_EN        BIT(25)
446 #define UPS_FLAGS_EN_GREEN              BIT(26)
447 #define UPS_FLAGS_EN_FLOW_CTR           BIT(27)
448
449 enum spd_duplex {
450         NWAY_10M_HALF = 1,
451         NWAY_10M_FULL,
452         NWAY_100M_HALF,
453         NWAY_100M_FULL,
454         NWAY_1000M_FULL,
455         FORCE_10M_HALF,
456         FORCE_10M_FULL,
457         FORCE_100M_HALF,
458         FORCE_100M_FULL,
459 };
460
461 /* OCP_ALDPS_CONFIG */
462 #define ENPWRSAVE               0x8000
463 #define ENPDNPS                 0x0200
464 #define LINKENA                 0x0100
465 #define DIS_SDSAVE              0x0010
466
467 /* OCP_PHY_STATUS */
468 #define PHY_STAT_MASK           0x0007
469 #define PHY_STAT_EXT_INIT       2
470 #define PHY_STAT_LAN_ON         3
471 #define PHY_STAT_PWRDN          5
472
473 /* OCP_NCTL_CFG */
474 #define PGA_RETURN_EN           BIT(1)
475
476 /* OCP_POWER_CFG */
477 #define EEE_CLKDIV_EN           0x8000
478 #define EN_ALDPS                0x0004
479 #define EN_10M_PLLOFF           0x0001
480
481 /* OCP_EEE_CONFIG1 */
482 #define RG_TXLPI_MSK_HFDUP      0x8000
483 #define RG_MATCLR_EN            0x4000
484 #define EEE_10_CAP              0x2000
485 #define EEE_NWAY_EN             0x1000
486 #define TX_QUIET_EN             0x0200
487 #define RX_QUIET_EN             0x0100
488 #define sd_rise_time_mask       0x0070
489 #define sd_rise_time(x)         (min(x, 7) << 4)        /* bit 4 ~ 6 */
490 #define RG_RXLPI_MSK_HFDUP      0x0008
491 #define SDFALLTIME              0x0007  /* bit 0 ~ 2 */
492
493 /* OCP_EEE_CONFIG2 */
494 #define RG_LPIHYS_NUM           0x7000  /* bit 12 ~ 15 */
495 #define RG_DACQUIET_EN          0x0400
496 #define RG_LDVQUIET_EN          0x0200
497 #define RG_CKRSEL               0x0020
498 #define RG_EEEPRG_EN            0x0010
499
500 /* OCP_EEE_CONFIG3 */
501 #define fast_snr_mask           0xff80
502 #define fast_snr(x)             (min(x, 0x1ff) << 7)    /* bit 7 ~ 15 */
503 #define RG_LFS_SEL              0x0060  /* bit 6 ~ 5 */
504 #define MSK_PH                  0x0006  /* bit 0 ~ 3 */
505
506 /* OCP_EEE_AR */
507 /* bit[15:14] function */
508 #define FUN_ADDR                0x0000
509 #define FUN_DATA                0x4000
510 /* bit[4:0] device addr */
511
512 /* OCP_EEE_CFG */
513 #define CTAP_SHORT_EN           0x0040
514 #define EEE10_EN                0x0010
515
516 /* OCP_DOWN_SPEED */
517 #define EN_EEE_CMODE            BIT(14)
518 #define EN_EEE_1000             BIT(13)
519 #define EN_EEE_100              BIT(12)
520 #define EN_10M_CLKDIV           BIT(11)
521 #define EN_10M_BGOFF            0x0080
522
523 /* OCP_PHY_STATE */
524 #define TXDIS_STATE             0x01
525 #define ABD_STATE               0x02
526
527 /* OCP_PHY_PATCH_STAT */
528 #define PATCH_READY             BIT(6)
529
530 /* OCP_PHY_PATCH_CMD */
531 #define PATCH_REQUEST           BIT(4)
532
533 /* OCP_ADC_CFG */
534 #define CKADSEL_L               0x0100
535 #define ADC_EN                  0x0080
536 #define EN_EMI_L                0x0040
537
538 /* OCP_SYSCLK_CFG */
539 #define clk_div_expo(x)         (min(x, 5) << 8)
540
541 /* SRAM_GREEN_CFG */
542 #define GREEN_ETH_EN            BIT(15)
543 #define R_TUNE_EN               BIT(11)
544
545 /* SRAM_LPF_CFG */
546 #define LPF_AUTO_TUNE           0x8000
547
548 /* SRAM_10M_AMP1 */
549 #define GDAC_IB_UPALL           0x0008
550
551 /* SRAM_10M_AMP2 */
552 #define AMP_DN                  0x0200
553
554 /* SRAM_IMPEDANCE */
555 #define RX_DRIVING_MASK         0x6000
556
557 /* MAC PASSTHRU */
558 #define AD_MASK                 0xfee0
559 #define BND_MASK                0x0004
560 #define BD_MASK                 0x0001
561 #define EFUSE                   0xcfdb
562 #define PASS_THRU_MASK          0x1
563
564 enum rtl_register_content {
565         _1000bps        = 0x10,
566         _100bps         = 0x08,
567         _10bps          = 0x04,
568         LINK_STATUS     = 0x02,
569         FULL_DUP        = 0x01,
570 };
571
572 #define RTL8152_MAX_TX          4
573 #define RTL8152_MAX_RX          10
574 #define INTBUFSIZE              2
575 #define TX_ALIGN                4
576 #define RX_ALIGN                8
577
578 #define INTR_LINK               0x0004
579
580 #define RTL8152_REQT_READ       0xc0
581 #define RTL8152_REQT_WRITE      0x40
582 #define RTL8152_REQ_GET_REGS    0x05
583 #define RTL8152_REQ_SET_REGS    0x05
584
585 #define BYTE_EN_DWORD           0xff
586 #define BYTE_EN_WORD            0x33
587 #define BYTE_EN_BYTE            0x11
588 #define BYTE_EN_SIX_BYTES       0x3f
589 #define BYTE_EN_START_MASK      0x0f
590 #define BYTE_EN_END_MASK        0xf0
591
592 #define RTL8153_MAX_PACKET      9216 /* 9K */
593 #define RTL8153_MAX_MTU         (RTL8153_MAX_PACKET - VLAN_ETH_HLEN - \
594                                  ETH_FCS_LEN)
595 #define RTL8152_RMS             (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN)
596 #define RTL8153_RMS             RTL8153_MAX_PACKET
597 #define RTL8152_TX_TIMEOUT      (5 * HZ)
598 #define RTL8152_NAPI_WEIGHT     64
599 #define rx_reserved_size(x)     ((x) + VLAN_ETH_HLEN + ETH_FCS_LEN + \
600                                  sizeof(struct rx_desc) + RX_ALIGN)
601
602 /* rtl8152 flags */
603 enum rtl8152_flags {
604         RTL8152_UNPLUG = 0,
605         RTL8152_SET_RX_MODE,
606         WORK_ENABLE,
607         RTL8152_LINK_CHG,
608         SELECTIVE_SUSPEND,
609         PHY_RESET,
610         SCHEDULE_NAPI,
611         GREEN_ETHERNET,
612         DELL_TB_RX_AGG_BUG,
613 };
614
615 /* Define these values to match your device */
616 #define VENDOR_ID_REALTEK               0x0bda
617 #define VENDOR_ID_MICROSOFT             0x045e
618 #define VENDOR_ID_SAMSUNG               0x04e8
619 #define VENDOR_ID_LENOVO                0x17ef
620 #define VENDOR_ID_LINKSYS               0x13b1
621 #define VENDOR_ID_NVIDIA                0x0955
622 #define VENDOR_ID_TPLINK                0x2357
623
624 #define MCU_TYPE_PLA                    0x0100
625 #define MCU_TYPE_USB                    0x0000
626
627 struct tally_counter {
628         __le64  tx_packets;
629         __le64  rx_packets;
630         __le64  tx_errors;
631         __le32  rx_errors;
632         __le16  rx_missed;
633         __le16  align_errors;
634         __le32  tx_one_collision;
635         __le32  tx_multi_collision;
636         __le64  rx_unicast;
637         __le64  rx_broadcast;
638         __le32  rx_multicast;
639         __le16  tx_aborted;
640         __le16  tx_underrun;
641 };
642
643 struct rx_desc {
644         __le32 opts1;
645 #define RX_LEN_MASK                     0x7fff
646
647         __le32 opts2;
648 #define RD_UDP_CS                       BIT(23)
649 #define RD_TCP_CS                       BIT(22)
650 #define RD_IPV6_CS                      BIT(20)
651 #define RD_IPV4_CS                      BIT(19)
652
653         __le32 opts3;
654 #define IPF                             BIT(23) /* IP checksum fail */
655 #define UDPF                            BIT(22) /* UDP checksum fail */
656 #define TCPF                            BIT(21) /* TCP checksum fail */
657 #define RX_VLAN_TAG                     BIT(16)
658
659         __le32 opts4;
660         __le32 opts5;
661         __le32 opts6;
662 };
663
664 struct tx_desc {
665         __le32 opts1;
666 #define TX_FS                   BIT(31) /* First segment of a packet */
667 #define TX_LS                   BIT(30) /* Final segment of a packet */
668 #define GTSENDV4                BIT(28)
669 #define GTSENDV6                BIT(27)
670 #define GTTCPHO_SHIFT           18
671 #define GTTCPHO_MAX             0x7fU
672 #define TX_LEN_MAX              0x3ffffU
673
674         __le32 opts2;
675 #define UDP_CS                  BIT(31) /* Calculate UDP/IP checksum */
676 #define TCP_CS                  BIT(30) /* Calculate TCP/IP checksum */
677 #define IPV4_CS                 BIT(29) /* Calculate IPv4 checksum */
678 #define IPV6_CS                 BIT(28) /* Calculate IPv6 checksum */
679 #define MSS_SHIFT               17
680 #define MSS_MAX                 0x7ffU
681 #define TCPHO_SHIFT             17
682 #define TCPHO_MAX               0x7ffU
683 #define TX_VLAN_TAG             BIT(16)
684 };
685
686 struct r8152;
687
688 struct rx_agg {
689         struct list_head list;
690         struct urb *urb;
691         struct r8152 *context;
692         void *buffer;
693         void *head;
694 };
695
696 struct tx_agg {
697         struct list_head list;
698         struct urb *urb;
699         struct r8152 *context;
700         void *buffer;
701         void *head;
702         u32 skb_num;
703         u32 skb_len;
704 };
705
706 struct r8152 {
707         unsigned long flags;
708         struct usb_device *udev;
709         struct napi_struct napi;
710         struct usb_interface *intf;
711         struct net_device *netdev;
712         struct urb *intr_urb;
713         struct tx_agg tx_info[RTL8152_MAX_TX];
714         struct rx_agg rx_info[RTL8152_MAX_RX];
715         struct list_head rx_done, tx_free;
716         struct sk_buff_head tx_queue, rx_queue;
717         spinlock_t rx_lock, tx_lock;
718         struct delayed_work schedule, hw_phy_work;
719         struct mii_if_info mii;
720         struct mutex control;   /* use for hw setting */
721 #ifdef CONFIG_PM_SLEEP
722         struct notifier_block pm_notifier;
723 #endif
724
725         struct rtl_ops {
726                 void (*init)(struct r8152 *);
727                 int (*enable)(struct r8152 *);
728                 void (*disable)(struct r8152 *);
729                 void (*up)(struct r8152 *);
730                 void (*down)(struct r8152 *);
731                 void (*unload)(struct r8152 *);
732                 int (*eee_get)(struct r8152 *, struct ethtool_eee *);
733                 int (*eee_set)(struct r8152 *, struct ethtool_eee *);
734                 bool (*in_nway)(struct r8152 *);
735                 void (*hw_phy_cfg)(struct r8152 *);
736                 void (*autosuspend_en)(struct r8152 *tp, bool enable);
737         } rtl_ops;
738
739         int intr_interval;
740         u32 saved_wolopts;
741         u32 msg_enable;
742         u32 tx_qlen;
743         u32 coalesce;
744         u16 ocp_base;
745         u16 speed;
746         u8 *intr_buff;
747         u8 version;
748         u8 duplex;
749         u8 autoneg;
750 };
751
752 enum rtl_version {
753         RTL_VER_UNKNOWN = 0,
754         RTL_VER_01,
755         RTL_VER_02,
756         RTL_VER_03,
757         RTL_VER_04,
758         RTL_VER_05,
759         RTL_VER_06,
760         RTL_VER_07,
761         RTL_VER_08,
762         RTL_VER_09,
763         RTL_VER_MAX
764 };
765
766 enum tx_csum_stat {
767         TX_CSUM_SUCCESS = 0,
768         TX_CSUM_TSO,
769         TX_CSUM_NONE
770 };
771
772 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
773  * The RTL chips use a 64 element hash table based on the Ethernet CRC.
774  */
775 static const int multicast_filter_limit = 32;
776 static unsigned int agg_buf_sz = 16384;
777
778 #define RTL_LIMITED_TSO_SIZE    (agg_buf_sz - sizeof(struct tx_desc) - \
779                                  VLAN_ETH_HLEN - ETH_FCS_LEN)
780
781 static
782 int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
783 {
784         int ret;
785         void *tmp;
786
787         tmp = kmalloc(size, GFP_KERNEL);
788         if (!tmp)
789                 return -ENOMEM;
790
791         ret = usb_control_msg(tp->udev, usb_rcvctrlpipe(tp->udev, 0),
792                               RTL8152_REQ_GET_REGS, RTL8152_REQT_READ,
793                               value, index, tmp, size, 500);
794
795         memcpy(data, tmp, size);
796         kfree(tmp);
797
798         return ret;
799 }
800
801 static
802 int set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
803 {
804         int ret;
805         void *tmp;
806
807         tmp = kmemdup(data, size, GFP_KERNEL);
808         if (!tmp)
809                 return -ENOMEM;
810
811         ret = usb_control_msg(tp->udev, usb_sndctrlpipe(tp->udev, 0),
812                               RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE,
813                               value, index, tmp, size, 500);
814
815         kfree(tmp);
816
817         return ret;
818 }
819
820 static int generic_ocp_read(struct r8152 *tp, u16 index, u16 size,
821                             void *data, u16 type)
822 {
823         u16 limit = 64;
824         int ret = 0;
825
826         if (test_bit(RTL8152_UNPLUG, &tp->flags))
827                 return -ENODEV;
828
829         /* both size and indix must be 4 bytes align */
830         if ((size & 3) || !size || (index & 3) || !data)
831                 return -EPERM;
832
833         if ((u32)index + (u32)size > 0xffff)
834                 return -EPERM;
835
836         while (size) {
837                 if (size > limit) {
838                         ret = get_registers(tp, index, type, limit, data);
839                         if (ret < 0)
840                                 break;
841
842                         index += limit;
843                         data += limit;
844                         size -= limit;
845                 } else {
846                         ret = get_registers(tp, index, type, size, data);
847                         if (ret < 0)
848                                 break;
849
850                         index += size;
851                         data += size;
852                         size = 0;
853                         break;
854                 }
855         }
856
857         if (ret == -ENODEV)
858                 set_bit(RTL8152_UNPLUG, &tp->flags);
859
860         return ret;
861 }
862
863 static int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen,
864                              u16 size, void *data, u16 type)
865 {
866         int ret;
867         u16 byteen_start, byteen_end, byen;
868         u16 limit = 512;
869
870         if (test_bit(RTL8152_UNPLUG, &tp->flags))
871                 return -ENODEV;
872
873         /* both size and indix must be 4 bytes align */
874         if ((size & 3) || !size || (index & 3) || !data)
875                 return -EPERM;
876
877         if ((u32)index + (u32)size > 0xffff)
878                 return -EPERM;
879
880         byteen_start = byteen & BYTE_EN_START_MASK;
881         byteen_end = byteen & BYTE_EN_END_MASK;
882
883         byen = byteen_start | (byteen_start << 4);
884         ret = set_registers(tp, index, type | byen, 4, data);
885         if (ret < 0)
886                 goto error1;
887
888         index += 4;
889         data += 4;
890         size -= 4;
891
892         if (size) {
893                 size -= 4;
894
895                 while (size) {
896                         if (size > limit) {
897                                 ret = set_registers(tp, index,
898                                                     type | BYTE_EN_DWORD,
899                                                     limit, data);
900                                 if (ret < 0)
901                                         goto error1;
902
903                                 index += limit;
904                                 data += limit;
905                                 size -= limit;
906                         } else {
907                                 ret = set_registers(tp, index,
908                                                     type | BYTE_EN_DWORD,
909                                                     size, data);
910                                 if (ret < 0)
911                                         goto error1;
912
913                                 index += size;
914                                 data += size;
915                                 size = 0;
916                                 break;
917                         }
918                 }
919
920                 byen = byteen_end | (byteen_end >> 4);
921                 ret = set_registers(tp, index, type | byen, 4, data);
922                 if (ret < 0)
923                         goto error1;
924         }
925
926 error1:
927         if (ret == -ENODEV)
928                 set_bit(RTL8152_UNPLUG, &tp->flags);
929
930         return ret;
931 }
932
933 static inline
934 int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
935 {
936         return generic_ocp_read(tp, index, size, data, MCU_TYPE_PLA);
937 }
938
939 static inline
940 int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
941 {
942         return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_PLA);
943 }
944
945 static inline
946 int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
947 {
948         return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_USB);
949 }
950
951 static u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index)
952 {
953         __le32 data;
954
955         generic_ocp_read(tp, index, sizeof(data), &data, type);
956
957         return __le32_to_cpu(data);
958 }
959
960 static void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data)
961 {
962         __le32 tmp = __cpu_to_le32(data);
963
964         generic_ocp_write(tp, index, BYTE_EN_DWORD, sizeof(tmp), &tmp, type);
965 }
966
967 static u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index)
968 {
969         u32 data;
970         __le32 tmp;
971         u16 byen = BYTE_EN_WORD;
972         u8 shift = index & 2;
973
974         index &= ~3;
975         byen <<= shift;
976
977         generic_ocp_read(tp, index, sizeof(tmp), &tmp, type | byen);
978
979         data = __le32_to_cpu(tmp);
980         data >>= (shift * 8);
981         data &= 0xffff;
982
983         return (u16)data;
984 }
985
986 static void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data)
987 {
988         u32 mask = 0xffff;
989         __le32 tmp;
990         u16 byen = BYTE_EN_WORD;
991         u8 shift = index & 2;
992
993         data &= mask;
994
995         if (index & 2) {
996                 byen <<= shift;
997                 mask <<= (shift * 8);
998                 data <<= (shift * 8);
999                 index &= ~3;
1000         }
1001
1002         tmp = __cpu_to_le32(data);
1003
1004         generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
1005 }
1006
1007 static u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index)
1008 {
1009         u32 data;
1010         __le32 tmp;
1011         u8 shift = index & 3;
1012
1013         index &= ~3;
1014
1015         generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
1016
1017         data = __le32_to_cpu(tmp);
1018         data >>= (shift * 8);
1019         data &= 0xff;
1020
1021         return (u8)data;
1022 }
1023
1024 static void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data)
1025 {
1026         u32 mask = 0xff;
1027         __le32 tmp;
1028         u16 byen = BYTE_EN_BYTE;
1029         u8 shift = index & 3;
1030
1031         data &= mask;
1032
1033         if (index & 3) {
1034                 byen <<= shift;
1035                 mask <<= (shift * 8);
1036                 data <<= (shift * 8);
1037                 index &= ~3;
1038         }
1039
1040         tmp = __cpu_to_le32(data);
1041
1042         generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
1043 }
1044
1045 static u16 ocp_reg_read(struct r8152 *tp, u16 addr)
1046 {
1047         u16 ocp_base, ocp_index;
1048
1049         ocp_base = addr & 0xf000;
1050         if (ocp_base != tp->ocp_base) {
1051                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
1052                 tp->ocp_base = ocp_base;
1053         }
1054
1055         ocp_index = (addr & 0x0fff) | 0xb000;
1056         return ocp_read_word(tp, MCU_TYPE_PLA, ocp_index);
1057 }
1058
1059 static void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data)
1060 {
1061         u16 ocp_base, ocp_index;
1062
1063         ocp_base = addr & 0xf000;
1064         if (ocp_base != tp->ocp_base) {
1065                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
1066                 tp->ocp_base = ocp_base;
1067         }
1068
1069         ocp_index = (addr & 0x0fff) | 0xb000;
1070         ocp_write_word(tp, MCU_TYPE_PLA, ocp_index, data);
1071 }
1072
1073 static inline void r8152_mdio_write(struct r8152 *tp, u32 reg_addr, u32 value)
1074 {
1075         ocp_reg_write(tp, OCP_BASE_MII + reg_addr * 2, value);
1076 }
1077
1078 static inline int r8152_mdio_read(struct r8152 *tp, u32 reg_addr)
1079 {
1080         return ocp_reg_read(tp, OCP_BASE_MII + reg_addr * 2);
1081 }
1082
1083 static void sram_write(struct r8152 *tp, u16 addr, u16 data)
1084 {
1085         ocp_reg_write(tp, OCP_SRAM_ADDR, addr);
1086         ocp_reg_write(tp, OCP_SRAM_DATA, data);
1087 }
1088
1089 static u16 sram_read(struct r8152 *tp, u16 addr)
1090 {
1091         ocp_reg_write(tp, OCP_SRAM_ADDR, addr);
1092         return ocp_reg_read(tp, OCP_SRAM_DATA);
1093 }
1094
1095 static int read_mii_word(struct net_device *netdev, int phy_id, int reg)
1096 {
1097         struct r8152 *tp = netdev_priv(netdev);
1098         int ret;
1099
1100         if (test_bit(RTL8152_UNPLUG, &tp->flags))
1101                 return -ENODEV;
1102
1103         if (phy_id != R8152_PHY_ID)
1104                 return -EINVAL;
1105
1106         ret = r8152_mdio_read(tp, reg);
1107
1108         return ret;
1109 }
1110
1111 static
1112 void write_mii_word(struct net_device *netdev, int phy_id, int reg, int val)
1113 {
1114         struct r8152 *tp = netdev_priv(netdev);
1115
1116         if (test_bit(RTL8152_UNPLUG, &tp->flags))
1117                 return;
1118
1119         if (phy_id != R8152_PHY_ID)
1120                 return;
1121
1122         r8152_mdio_write(tp, reg, val);
1123 }
1124
1125 static int
1126 r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags);
1127
1128 static int rtl8152_set_mac_address(struct net_device *netdev, void *p)
1129 {
1130         struct r8152 *tp = netdev_priv(netdev);
1131         struct sockaddr *addr = p;
1132         int ret = -EADDRNOTAVAIL;
1133
1134         if (!is_valid_ether_addr(addr->sa_data))
1135                 goto out1;
1136
1137         ret = usb_autopm_get_interface(tp->intf);
1138         if (ret < 0)
1139                 goto out1;
1140
1141         mutex_lock(&tp->control);
1142
1143         memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
1144
1145         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
1146         pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, addr->sa_data);
1147         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
1148
1149         mutex_unlock(&tp->control);
1150
1151         usb_autopm_put_interface(tp->intf);
1152 out1:
1153         return ret;
1154 }
1155
1156 /* Devices containing proper chips can support a persistent
1157  * host system provided MAC address.
1158  * Examples of this are Dell TB15 and Dell WD15 docks
1159  */
1160 static int vendor_mac_passthru_addr_read(struct r8152 *tp, struct sockaddr *sa)
1161 {
1162         acpi_status status;
1163         struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
1164         union acpi_object *obj;
1165         int ret = -EINVAL;
1166         u32 ocp_data;
1167         unsigned char buf[6];
1168
1169         /* test for -AD variant of RTL8153 */
1170         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
1171         if ((ocp_data & AD_MASK) == 0x1000) {
1172                 /* test for MAC address pass-through bit */
1173                 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, EFUSE);
1174                 if ((ocp_data & PASS_THRU_MASK) != 1) {
1175                         netif_dbg(tp, probe, tp->netdev,
1176                                   "No efuse for RTL8153-AD MAC pass through\n");
1177                         return -ENODEV;
1178                 }
1179         } else {
1180                 /* test for RTL8153-BND and RTL8153-BD */
1181                 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_1);
1182                 if ((ocp_data & BND_MASK) == 0 && (ocp_data & BD_MASK) == 0) {
1183                         netif_dbg(tp, probe, tp->netdev,
1184                                   "Invalid variant for MAC pass through\n");
1185                         return -ENODEV;
1186                 }
1187         }
1188
1189         /* returns _AUXMAC_#AABBCCDDEEFF# */
1190         status = acpi_evaluate_object(NULL, "\\_SB.AMAC", NULL, &buffer);
1191         obj = (union acpi_object *)buffer.pointer;
1192         if (!ACPI_SUCCESS(status))
1193                 return -ENODEV;
1194         if (obj->type != ACPI_TYPE_BUFFER || obj->string.length != 0x17) {
1195                 netif_warn(tp, probe, tp->netdev,
1196                            "Invalid buffer for pass-thru MAC addr: (%d, %d)\n",
1197                            obj->type, obj->string.length);
1198                 goto amacout;
1199         }
1200         if (strncmp(obj->string.pointer, "_AUXMAC_#", 9) != 0 ||
1201             strncmp(obj->string.pointer + 0x15, "#", 1) != 0) {
1202                 netif_warn(tp, probe, tp->netdev,
1203                            "Invalid header when reading pass-thru MAC addr\n");
1204                 goto amacout;
1205         }
1206         ret = hex2bin(buf, obj->string.pointer + 9, 6);
1207         if (!(ret == 0 && is_valid_ether_addr(buf))) {
1208                 netif_warn(tp, probe, tp->netdev,
1209                            "Invalid MAC for pass-thru MAC addr: %d, %pM\n",
1210                            ret, buf);
1211                 ret = -EINVAL;
1212                 goto amacout;
1213         }
1214         memcpy(sa->sa_data, buf, 6);
1215         netif_info(tp, probe, tp->netdev,
1216                    "Using pass-thru MAC addr %pM\n", sa->sa_data);
1217
1218 amacout:
1219         kfree(obj);
1220         return ret;
1221 }
1222
1223 static int determine_ethernet_addr(struct r8152 *tp, struct sockaddr *sa)
1224 {
1225         struct net_device *dev = tp->netdev;
1226         int ret;
1227
1228         if (tp->version == RTL_VER_01) {
1229                 ret = pla_ocp_read(tp, PLA_IDR, 8, sa->sa_data);
1230         } else {
1231                 /* if device doesn't support MAC pass through this will
1232                  * be expected to be non-zero
1233                  */
1234                 ret = vendor_mac_passthru_addr_read(tp, sa);
1235                 if (ret < 0)
1236                         ret = pla_ocp_read(tp, PLA_BACKUP, 8, sa->sa_data);
1237         }
1238
1239         if (ret < 0) {
1240                 netif_err(tp, probe, dev, "Get ether addr fail\n");
1241         } else if (!is_valid_ether_addr(sa->sa_data)) {
1242                 netif_err(tp, probe, dev, "Invalid ether addr %pM\n",
1243                           sa->sa_data);
1244                 eth_hw_addr_random(dev);
1245                 ether_addr_copy(sa->sa_data, dev->dev_addr);
1246                 netif_info(tp, probe, dev, "Random ether addr %pM\n",
1247                            sa->sa_data);
1248                 return 0;
1249         }
1250
1251         return ret;
1252 }
1253
1254 static int set_ethernet_addr(struct r8152 *tp)
1255 {
1256         struct net_device *dev = tp->netdev;
1257         struct sockaddr sa;
1258         int ret;
1259
1260         ret = determine_ethernet_addr(tp, &sa);
1261         if (ret < 0)
1262                 return ret;
1263
1264         if (tp->version == RTL_VER_01)
1265                 ether_addr_copy(dev->dev_addr, sa.sa_data);
1266         else
1267                 ret = rtl8152_set_mac_address(dev, &sa);
1268
1269         return ret;
1270 }
1271
1272 static void read_bulk_callback(struct urb *urb)
1273 {
1274         struct net_device *netdev;
1275         int status = urb->status;
1276         struct rx_agg *agg;
1277         struct r8152 *tp;
1278         unsigned long flags;
1279
1280         agg = urb->context;
1281         if (!agg)
1282                 return;
1283
1284         tp = agg->context;
1285         if (!tp)
1286                 return;
1287
1288         if (test_bit(RTL8152_UNPLUG, &tp->flags))
1289                 return;
1290
1291         if (!test_bit(WORK_ENABLE, &tp->flags))
1292                 return;
1293
1294         netdev = tp->netdev;
1295
1296         /* When link down, the driver would cancel all bulks. */
1297         /* This avoid the re-submitting bulk */
1298         if (!netif_carrier_ok(netdev))
1299                 return;
1300
1301         usb_mark_last_busy(tp->udev);
1302
1303         switch (status) {
1304         case 0:
1305                 if (urb->actual_length < ETH_ZLEN)
1306                         break;
1307
1308                 spin_lock_irqsave(&tp->rx_lock, flags);
1309                 list_add_tail(&agg->list, &tp->rx_done);
1310                 spin_unlock_irqrestore(&tp->rx_lock, flags);
1311                 napi_schedule(&tp->napi);
1312                 return;
1313         case -ESHUTDOWN:
1314                 set_bit(RTL8152_UNPLUG, &tp->flags);
1315                 netif_device_detach(tp->netdev);
1316                 return;
1317         case -ENOENT:
1318                 return; /* the urb is in unlink state */
1319         case -ETIME:
1320                 if (net_ratelimit())
1321                         netdev_warn(netdev, "maybe reset is needed?\n");
1322                 break;
1323         default:
1324                 if (net_ratelimit())
1325                         netdev_warn(netdev, "Rx status %d\n", status);
1326                 break;
1327         }
1328
1329         r8152_submit_rx(tp, agg, GFP_ATOMIC);
1330 }
1331
1332 static void write_bulk_callback(struct urb *urb)
1333 {
1334         struct net_device_stats *stats;
1335         struct net_device *netdev;
1336         struct tx_agg *agg;
1337         struct r8152 *tp;
1338         unsigned long flags;
1339         int status = urb->status;
1340
1341         agg = urb->context;
1342         if (!agg)
1343                 return;
1344
1345         tp = agg->context;
1346         if (!tp)
1347                 return;
1348
1349         netdev = tp->netdev;
1350         stats = &netdev->stats;
1351         if (status) {
1352                 if (net_ratelimit())
1353                         netdev_warn(netdev, "Tx status %d\n", status);
1354                 stats->tx_errors += agg->skb_num;
1355         } else {
1356                 stats->tx_packets += agg->skb_num;
1357                 stats->tx_bytes += agg->skb_len;
1358         }
1359
1360         spin_lock_irqsave(&tp->tx_lock, flags);
1361         list_add_tail(&agg->list, &tp->tx_free);
1362         spin_unlock_irqrestore(&tp->tx_lock, flags);
1363
1364         usb_autopm_put_interface_async(tp->intf);
1365
1366         if (!netif_carrier_ok(netdev))
1367                 return;
1368
1369         if (!test_bit(WORK_ENABLE, &tp->flags))
1370                 return;
1371
1372         if (test_bit(RTL8152_UNPLUG, &tp->flags))
1373                 return;
1374
1375         if (!skb_queue_empty(&tp->tx_queue))
1376                 napi_schedule(&tp->napi);
1377 }
1378
1379 static void intr_callback(struct urb *urb)
1380 {
1381         struct r8152 *tp;
1382         __le16 *d;
1383         int status = urb->status;
1384         int res;
1385
1386         tp = urb->context;
1387         if (!tp)
1388                 return;
1389
1390         if (!test_bit(WORK_ENABLE, &tp->flags))
1391                 return;
1392
1393         if (test_bit(RTL8152_UNPLUG, &tp->flags))
1394                 return;
1395
1396         switch (status) {
1397         case 0:                 /* success */
1398                 break;
1399         case -ECONNRESET:       /* unlink */
1400         case -ESHUTDOWN:
1401                 netif_device_detach(tp->netdev);
1402                 /* fall through */
1403         case -ENOENT:
1404         case -EPROTO:
1405                 netif_info(tp, intr, tp->netdev,
1406                            "Stop submitting intr, status %d\n", status);
1407                 return;
1408         case -EOVERFLOW:
1409                 netif_info(tp, intr, tp->netdev, "intr status -EOVERFLOW\n");
1410                 goto resubmit;
1411         /* -EPIPE:  should clear the halt */
1412         default:
1413                 netif_info(tp, intr, tp->netdev, "intr status %d\n", status);
1414                 goto resubmit;
1415         }
1416
1417         d = urb->transfer_buffer;
1418         if (INTR_LINK & __le16_to_cpu(d[0])) {
1419                 if (!netif_carrier_ok(tp->netdev)) {
1420                         set_bit(RTL8152_LINK_CHG, &tp->flags);
1421                         schedule_delayed_work(&tp->schedule, 0);
1422                 }
1423         } else {
1424                 if (netif_carrier_ok(tp->netdev)) {
1425                         netif_stop_queue(tp->netdev);
1426                         set_bit(RTL8152_LINK_CHG, &tp->flags);
1427                         schedule_delayed_work(&tp->schedule, 0);
1428                 }
1429         }
1430
1431 resubmit:
1432         res = usb_submit_urb(urb, GFP_ATOMIC);
1433         if (res == -ENODEV) {
1434                 set_bit(RTL8152_UNPLUG, &tp->flags);
1435                 netif_device_detach(tp->netdev);
1436         } else if (res) {
1437                 netif_err(tp, intr, tp->netdev,
1438                           "can't resubmit intr, status %d\n", res);
1439         }
1440 }
1441
1442 static inline void *rx_agg_align(void *data)
1443 {
1444         return (void *)ALIGN((uintptr_t)data, RX_ALIGN);
1445 }
1446
1447 static inline void *tx_agg_align(void *data)
1448 {
1449         return (void *)ALIGN((uintptr_t)data, TX_ALIGN);
1450 }
1451
1452 static void free_all_mem(struct r8152 *tp)
1453 {
1454         int i;
1455
1456         for (i = 0; i < RTL8152_MAX_RX; i++) {
1457                 usb_free_urb(tp->rx_info[i].urb);
1458                 tp->rx_info[i].urb = NULL;
1459
1460                 kfree(tp->rx_info[i].buffer);
1461                 tp->rx_info[i].buffer = NULL;
1462                 tp->rx_info[i].head = NULL;
1463         }
1464
1465         for (i = 0; i < RTL8152_MAX_TX; i++) {
1466                 usb_free_urb(tp->tx_info[i].urb);
1467                 tp->tx_info[i].urb = NULL;
1468
1469                 kfree(tp->tx_info[i].buffer);
1470                 tp->tx_info[i].buffer = NULL;
1471                 tp->tx_info[i].head = NULL;
1472         }
1473
1474         usb_free_urb(tp->intr_urb);
1475         tp->intr_urb = NULL;
1476
1477         kfree(tp->intr_buff);
1478         tp->intr_buff = NULL;
1479 }
1480
1481 static int alloc_all_mem(struct r8152 *tp)
1482 {
1483         struct net_device *netdev = tp->netdev;
1484         struct usb_interface *intf = tp->intf;
1485         struct usb_host_interface *alt = intf->cur_altsetting;
1486         struct usb_host_endpoint *ep_intr = alt->endpoint + 2;
1487         struct urb *urb;
1488         int node, i;
1489         u8 *buf;
1490
1491         node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1;
1492
1493         spin_lock_init(&tp->rx_lock);
1494         spin_lock_init(&tp->tx_lock);
1495         INIT_LIST_HEAD(&tp->tx_free);
1496         INIT_LIST_HEAD(&tp->rx_done);
1497         skb_queue_head_init(&tp->tx_queue);
1498         skb_queue_head_init(&tp->rx_queue);
1499
1500         for (i = 0; i < RTL8152_MAX_RX; i++) {
1501                 buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node);
1502                 if (!buf)
1503                         goto err1;
1504
1505                 if (buf != rx_agg_align(buf)) {
1506                         kfree(buf);
1507                         buf = kmalloc_node(agg_buf_sz + RX_ALIGN, GFP_KERNEL,
1508                                            node);
1509                         if (!buf)
1510                                 goto err1;
1511                 }
1512
1513                 urb = usb_alloc_urb(0, GFP_KERNEL);
1514                 if (!urb) {
1515                         kfree(buf);
1516                         goto err1;
1517                 }
1518
1519                 INIT_LIST_HEAD(&tp->rx_info[i].list);
1520                 tp->rx_info[i].context = tp;
1521                 tp->rx_info[i].urb = urb;
1522                 tp->rx_info[i].buffer = buf;
1523                 tp->rx_info[i].head = rx_agg_align(buf);
1524         }
1525
1526         for (i = 0; i < RTL8152_MAX_TX; i++) {
1527                 buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node);
1528                 if (!buf)
1529                         goto err1;
1530
1531                 if (buf != tx_agg_align(buf)) {
1532                         kfree(buf);
1533                         buf = kmalloc_node(agg_buf_sz + TX_ALIGN, GFP_KERNEL,
1534                                            node);
1535                         if (!buf)
1536                                 goto err1;
1537                 }
1538
1539                 urb = usb_alloc_urb(0, GFP_KERNEL);
1540                 if (!urb) {
1541                         kfree(buf);
1542                         goto err1;
1543                 }
1544
1545                 INIT_LIST_HEAD(&tp->tx_info[i].list);
1546                 tp->tx_info[i].context = tp;
1547                 tp->tx_info[i].urb = urb;
1548                 tp->tx_info[i].buffer = buf;
1549                 tp->tx_info[i].head = tx_agg_align(buf);
1550
1551                 list_add_tail(&tp->tx_info[i].list, &tp->tx_free);
1552         }
1553
1554         tp->intr_urb = usb_alloc_urb(0, GFP_KERNEL);
1555         if (!tp->intr_urb)
1556                 goto err1;
1557
1558         tp->intr_buff = kmalloc(INTBUFSIZE, GFP_KERNEL);
1559         if (!tp->intr_buff)
1560                 goto err1;
1561
1562         tp->intr_interval = (int)ep_intr->desc.bInterval;
1563         usb_fill_int_urb(tp->intr_urb, tp->udev, usb_rcvintpipe(tp->udev, 3),
1564                          tp->intr_buff, INTBUFSIZE, intr_callback,
1565                          tp, tp->intr_interval);
1566
1567         return 0;
1568
1569 err1:
1570         free_all_mem(tp);
1571         return -ENOMEM;
1572 }
1573
1574 static struct tx_agg *r8152_get_tx_agg(struct r8152 *tp)
1575 {
1576         struct tx_agg *agg = NULL;
1577         unsigned long flags;
1578
1579         if (list_empty(&tp->tx_free))
1580                 return NULL;
1581
1582         spin_lock_irqsave(&tp->tx_lock, flags);
1583         if (!list_empty(&tp->tx_free)) {
1584                 struct list_head *cursor;
1585
1586                 cursor = tp->tx_free.next;
1587                 list_del_init(cursor);
1588                 agg = list_entry(cursor, struct tx_agg, list);
1589         }
1590         spin_unlock_irqrestore(&tp->tx_lock, flags);
1591
1592         return agg;
1593 }
1594
1595 /* r8152_csum_workaround()
1596  * The hw limites the value the transport offset. When the offset is out of the
1597  * range, calculate the checksum by sw.
1598  */
1599 static void r8152_csum_workaround(struct r8152 *tp, struct sk_buff *skb,
1600                                   struct sk_buff_head *list)
1601 {
1602         if (skb_shinfo(skb)->gso_size) {
1603                 netdev_features_t features = tp->netdev->features;
1604                 struct sk_buff_head seg_list;
1605                 struct sk_buff *segs, *nskb;
1606
1607                 features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
1608                 segs = skb_gso_segment(skb, features);
1609                 if (IS_ERR(segs) || !segs)
1610                         goto drop;
1611
1612                 __skb_queue_head_init(&seg_list);
1613
1614                 do {
1615                         nskb = segs;
1616                         segs = segs->next;
1617                         nskb->next = NULL;
1618                         __skb_queue_tail(&seg_list, nskb);
1619                 } while (segs);
1620
1621                 skb_queue_splice(&seg_list, list);
1622                 dev_kfree_skb(skb);
1623         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
1624                 if (skb_checksum_help(skb) < 0)
1625                         goto drop;
1626
1627                 __skb_queue_head(list, skb);
1628         } else {
1629                 struct net_device_stats *stats;
1630
1631 drop:
1632                 stats = &tp->netdev->stats;
1633                 stats->tx_dropped++;
1634                 dev_kfree_skb(skb);
1635         }
1636 }
1637
1638 /* msdn_giant_send_check()
1639  * According to the document of microsoft, the TCP Pseudo Header excludes the
1640  * packet length for IPv6 TCP large packets.
1641  */
1642 static int msdn_giant_send_check(struct sk_buff *skb)
1643 {
1644         const struct ipv6hdr *ipv6h;
1645         struct tcphdr *th;
1646         int ret;
1647
1648         ret = skb_cow_head(skb, 0);
1649         if (ret)
1650                 return ret;
1651
1652         ipv6h = ipv6_hdr(skb);
1653         th = tcp_hdr(skb);
1654
1655         th->check = 0;
1656         th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0);
1657
1658         return ret;
1659 }
1660
1661 static inline void rtl_tx_vlan_tag(struct tx_desc *desc, struct sk_buff *skb)
1662 {
1663         if (skb_vlan_tag_present(skb)) {
1664                 u32 opts2;
1665
1666                 opts2 = TX_VLAN_TAG | swab16(skb_vlan_tag_get(skb));
1667                 desc->opts2 |= cpu_to_le32(opts2);
1668         }
1669 }
1670
1671 static inline void rtl_rx_vlan_tag(struct rx_desc *desc, struct sk_buff *skb)
1672 {
1673         u32 opts2 = le32_to_cpu(desc->opts2);
1674
1675         if (opts2 & RX_VLAN_TAG)
1676                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
1677                                        swab16(opts2 & 0xffff));
1678 }
1679
1680 static int r8152_tx_csum(struct r8152 *tp, struct tx_desc *desc,
1681                          struct sk_buff *skb, u32 len, u32 transport_offset)
1682 {
1683         u32 mss = skb_shinfo(skb)->gso_size;
1684         u32 opts1, opts2 = 0;
1685         int ret = TX_CSUM_SUCCESS;
1686
1687         WARN_ON_ONCE(len > TX_LEN_MAX);
1688
1689         opts1 = len | TX_FS | TX_LS;
1690
1691         if (mss) {
1692                 if (transport_offset > GTTCPHO_MAX) {
1693                         netif_warn(tp, tx_err, tp->netdev,
1694                                    "Invalid transport offset 0x%x for TSO\n",
1695                                    transport_offset);
1696                         ret = TX_CSUM_TSO;
1697                         goto unavailable;
1698                 }
1699
1700                 switch (vlan_get_protocol(skb)) {
1701                 case htons(ETH_P_IP):
1702                         opts1 |= GTSENDV4;
1703                         break;
1704
1705                 case htons(ETH_P_IPV6):
1706                         if (msdn_giant_send_check(skb)) {
1707                                 ret = TX_CSUM_TSO;
1708                                 goto unavailable;
1709                         }
1710                         opts1 |= GTSENDV6;
1711                         break;
1712
1713                 default:
1714                         WARN_ON_ONCE(1);
1715                         break;
1716                 }
1717
1718                 opts1 |= transport_offset << GTTCPHO_SHIFT;
1719                 opts2 |= min(mss, MSS_MAX) << MSS_SHIFT;
1720         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
1721                 u8 ip_protocol;
1722
1723                 if (transport_offset > TCPHO_MAX) {
1724                         netif_warn(tp, tx_err, tp->netdev,
1725                                    "Invalid transport offset 0x%x\n",
1726                                    transport_offset);
1727                         ret = TX_CSUM_NONE;
1728                         goto unavailable;
1729                 }
1730
1731                 switch (vlan_get_protocol(skb)) {
1732                 case htons(ETH_P_IP):
1733                         opts2 |= IPV4_CS;
1734                         ip_protocol = ip_hdr(skb)->protocol;
1735                         break;
1736
1737                 case htons(ETH_P_IPV6):
1738                         opts2 |= IPV6_CS;
1739                         ip_protocol = ipv6_hdr(skb)->nexthdr;
1740                         break;
1741
1742                 default:
1743                         ip_protocol = IPPROTO_RAW;
1744                         break;
1745                 }
1746
1747                 if (ip_protocol == IPPROTO_TCP)
1748                         opts2 |= TCP_CS;
1749                 else if (ip_protocol == IPPROTO_UDP)
1750                         opts2 |= UDP_CS;
1751                 else
1752                         WARN_ON_ONCE(1);
1753
1754                 opts2 |= transport_offset << TCPHO_SHIFT;
1755         }
1756
1757         desc->opts2 = cpu_to_le32(opts2);
1758         desc->opts1 = cpu_to_le32(opts1);
1759
1760 unavailable:
1761         return ret;
1762 }
1763
1764 static int r8152_tx_agg_fill(struct r8152 *tp, struct tx_agg *agg)
1765 {
1766         struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
1767         int remain, ret;
1768         u8 *tx_data;
1769
1770         __skb_queue_head_init(&skb_head);
1771         spin_lock(&tx_queue->lock);
1772         skb_queue_splice_init(tx_queue, &skb_head);
1773         spin_unlock(&tx_queue->lock);
1774
1775         tx_data = agg->head;
1776         agg->skb_num = 0;
1777         agg->skb_len = 0;
1778         remain = agg_buf_sz;
1779
1780         while (remain >= ETH_ZLEN + sizeof(struct tx_desc)) {
1781                 struct tx_desc *tx_desc;
1782                 struct sk_buff *skb;
1783                 unsigned int len;
1784                 u32 offset;
1785
1786                 skb = __skb_dequeue(&skb_head);
1787                 if (!skb)
1788                         break;
1789
1790                 len = skb->len + sizeof(*tx_desc);
1791
1792                 if (len > remain) {
1793                         __skb_queue_head(&skb_head, skb);
1794                         break;
1795                 }
1796
1797                 tx_data = tx_agg_align(tx_data);
1798                 tx_desc = (struct tx_desc *)tx_data;
1799
1800                 offset = (u32)skb_transport_offset(skb);
1801
1802                 if (r8152_tx_csum(tp, tx_desc, skb, skb->len, offset)) {
1803                         r8152_csum_workaround(tp, skb, &skb_head);
1804                         continue;
1805                 }
1806
1807                 rtl_tx_vlan_tag(tx_desc, skb);
1808
1809                 tx_data += sizeof(*tx_desc);
1810
1811                 len = skb->len;
1812                 if (skb_copy_bits(skb, 0, tx_data, len) < 0) {
1813                         struct net_device_stats *stats = &tp->netdev->stats;
1814
1815                         stats->tx_dropped++;
1816                         dev_kfree_skb_any(skb);
1817                         tx_data -= sizeof(*tx_desc);
1818                         continue;
1819                 }
1820
1821                 tx_data += len;
1822                 agg->skb_len += len;
1823                 agg->skb_num += skb_shinfo(skb)->gso_segs ?: 1;
1824
1825                 dev_kfree_skb_any(skb);
1826
1827                 remain = agg_buf_sz - (int)(tx_agg_align(tx_data) - agg->head);
1828
1829                 if (test_bit(DELL_TB_RX_AGG_BUG, &tp->flags))
1830                         break;
1831         }
1832
1833         if (!skb_queue_empty(&skb_head)) {
1834                 spin_lock(&tx_queue->lock);
1835                 skb_queue_splice(&skb_head, tx_queue);
1836                 spin_unlock(&tx_queue->lock);
1837         }
1838
1839         netif_tx_lock(tp->netdev);
1840
1841         if (netif_queue_stopped(tp->netdev) &&
1842             skb_queue_len(&tp->tx_queue) < tp->tx_qlen)
1843                 netif_wake_queue(tp->netdev);
1844
1845         netif_tx_unlock(tp->netdev);
1846
1847         ret = usb_autopm_get_interface_async(tp->intf);
1848         if (ret < 0)
1849                 goto out_tx_fill;
1850
1851         usb_fill_bulk_urb(agg->urb, tp->udev, usb_sndbulkpipe(tp->udev, 2),
1852                           agg->head, (int)(tx_data - (u8 *)agg->head),
1853                           (usb_complete_t)write_bulk_callback, agg);
1854
1855         ret = usb_submit_urb(agg->urb, GFP_ATOMIC);
1856         if (ret < 0)
1857                 usb_autopm_put_interface_async(tp->intf);
1858
1859 out_tx_fill:
1860         return ret;
1861 }
1862
1863 static u8 r8152_rx_csum(struct r8152 *tp, struct rx_desc *rx_desc)
1864 {
1865         u8 checksum = CHECKSUM_NONE;
1866         u32 opts2, opts3;
1867
1868         if (!(tp->netdev->features & NETIF_F_RXCSUM))
1869                 goto return_result;
1870
1871         opts2 = le32_to_cpu(rx_desc->opts2);
1872         opts3 = le32_to_cpu(rx_desc->opts3);
1873
1874         if (opts2 & RD_IPV4_CS) {
1875                 if (opts3 & IPF)
1876                         checksum = CHECKSUM_NONE;
1877                 else if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF))
1878                         checksum = CHECKSUM_UNNECESSARY;
1879                 else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF))
1880                         checksum = CHECKSUM_UNNECESSARY;
1881         } else if (opts2 & RD_IPV6_CS) {
1882                 if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF))
1883                         checksum = CHECKSUM_UNNECESSARY;
1884                 else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF))
1885                         checksum = CHECKSUM_UNNECESSARY;
1886         }
1887
1888 return_result:
1889         return checksum;
1890 }
1891
1892 static int rx_bottom(struct r8152 *tp, int budget)
1893 {
1894         unsigned long flags;
1895         struct list_head *cursor, *next, rx_queue;
1896         int ret = 0, work_done = 0;
1897         struct napi_struct *napi = &tp->napi;
1898
1899         if (!skb_queue_empty(&tp->rx_queue)) {
1900                 while (work_done < budget) {
1901                         struct sk_buff *skb = __skb_dequeue(&tp->rx_queue);
1902                         struct net_device *netdev = tp->netdev;
1903                         struct net_device_stats *stats = &netdev->stats;
1904                         unsigned int pkt_len;
1905
1906                         if (!skb)
1907                                 break;
1908
1909                         pkt_len = skb->len;
1910                         napi_gro_receive(napi, skb);
1911                         work_done++;
1912                         stats->rx_packets++;
1913                         stats->rx_bytes += pkt_len;
1914                 }
1915         }
1916
1917         if (list_empty(&tp->rx_done))
1918                 goto out1;
1919
1920         INIT_LIST_HEAD(&rx_queue);
1921         spin_lock_irqsave(&tp->rx_lock, flags);
1922         list_splice_init(&tp->rx_done, &rx_queue);
1923         spin_unlock_irqrestore(&tp->rx_lock, flags);
1924
1925         list_for_each_safe(cursor, next, &rx_queue) {
1926                 struct rx_desc *rx_desc;
1927                 struct rx_agg *agg;
1928                 int len_used = 0;
1929                 struct urb *urb;
1930                 u8 *rx_data;
1931
1932                 list_del_init(cursor);
1933
1934                 agg = list_entry(cursor, struct rx_agg, list);
1935                 urb = agg->urb;
1936                 if (urb->actual_length < ETH_ZLEN)
1937                         goto submit;
1938
1939                 rx_desc = agg->head;
1940                 rx_data = agg->head;
1941                 len_used += sizeof(struct rx_desc);
1942
1943                 while (urb->actual_length > len_used) {
1944                         struct net_device *netdev = tp->netdev;
1945                         struct net_device_stats *stats = &netdev->stats;
1946                         unsigned int pkt_len;
1947                         struct sk_buff *skb;
1948
1949                         /* limite the skb numbers for rx_queue */
1950                         if (unlikely(skb_queue_len(&tp->rx_queue) >= 1000))
1951                                 break;
1952
1953                         pkt_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK;
1954                         if (pkt_len < ETH_ZLEN)
1955                                 break;
1956
1957                         len_used += pkt_len;
1958                         if (urb->actual_length < len_used)
1959                                 break;
1960
1961                         pkt_len -= ETH_FCS_LEN;
1962                         rx_data += sizeof(struct rx_desc);
1963
1964                         skb = napi_alloc_skb(napi, pkt_len);
1965                         if (!skb) {
1966                                 stats->rx_dropped++;
1967                                 goto find_next_rx;
1968                         }
1969
1970                         skb->ip_summed = r8152_rx_csum(tp, rx_desc);
1971                         memcpy(skb->data, rx_data, pkt_len);
1972                         skb_put(skb, pkt_len);
1973                         skb->protocol = eth_type_trans(skb, netdev);
1974                         rtl_rx_vlan_tag(rx_desc, skb);
1975                         if (work_done < budget) {
1976                                 napi_gro_receive(napi, skb);
1977                                 work_done++;
1978                                 stats->rx_packets++;
1979                                 stats->rx_bytes += pkt_len;
1980                         } else {
1981                                 __skb_queue_tail(&tp->rx_queue, skb);
1982                         }
1983
1984 find_next_rx:
1985                         rx_data = rx_agg_align(rx_data + pkt_len + ETH_FCS_LEN);
1986                         rx_desc = (struct rx_desc *)rx_data;
1987                         len_used = (int)(rx_data - (u8 *)agg->head);
1988                         len_used += sizeof(struct rx_desc);
1989                 }
1990
1991 submit:
1992                 if (!ret) {
1993                         ret = r8152_submit_rx(tp, agg, GFP_ATOMIC);
1994                 } else {
1995                         urb->actual_length = 0;
1996                         list_add_tail(&agg->list, next);
1997                 }
1998         }
1999
2000         if (!list_empty(&rx_queue)) {
2001                 spin_lock_irqsave(&tp->rx_lock, flags);
2002                 list_splice_tail(&rx_queue, &tp->rx_done);
2003                 spin_unlock_irqrestore(&tp->rx_lock, flags);
2004         }
2005
2006 out1:
2007         return work_done;
2008 }
2009
2010 static void tx_bottom(struct r8152 *tp)
2011 {
2012         int res;
2013
2014         do {
2015                 struct tx_agg *agg;
2016
2017                 if (skb_queue_empty(&tp->tx_queue))
2018                         break;
2019
2020                 agg = r8152_get_tx_agg(tp);
2021                 if (!agg)
2022                         break;
2023
2024                 res = r8152_tx_agg_fill(tp, agg);
2025                 if (res) {
2026                         struct net_device *netdev = tp->netdev;
2027
2028                         if (res == -ENODEV) {
2029                                 set_bit(RTL8152_UNPLUG, &tp->flags);
2030                                 netif_device_detach(netdev);
2031                         } else {
2032                                 struct net_device_stats *stats = &netdev->stats;
2033                                 unsigned long flags;
2034
2035                                 netif_warn(tp, tx_err, netdev,
2036                                            "failed tx_urb %d\n", res);
2037                                 stats->tx_dropped += agg->skb_num;
2038
2039                                 spin_lock_irqsave(&tp->tx_lock, flags);
2040                                 list_add_tail(&agg->list, &tp->tx_free);
2041                                 spin_unlock_irqrestore(&tp->tx_lock, flags);
2042                         }
2043                 }
2044         } while (res == 0);
2045 }
2046
2047 static void bottom_half(struct r8152 *tp)
2048 {
2049         if (test_bit(RTL8152_UNPLUG, &tp->flags))
2050                 return;
2051
2052         if (!test_bit(WORK_ENABLE, &tp->flags))
2053                 return;
2054
2055         /* When link down, the driver would cancel all bulks. */
2056         /* This avoid the re-submitting bulk */
2057         if (!netif_carrier_ok(tp->netdev))
2058                 return;
2059
2060         clear_bit(SCHEDULE_NAPI, &tp->flags);
2061
2062         tx_bottom(tp);
2063 }
2064
2065 static int r8152_poll(struct napi_struct *napi, int budget)
2066 {
2067         struct r8152 *tp = container_of(napi, struct r8152, napi);
2068         int work_done;
2069
2070         work_done = rx_bottom(tp, budget);
2071         bottom_half(tp);
2072
2073         if (work_done < budget) {
2074                 if (!napi_complete_done(napi, work_done))
2075                         goto out;
2076                 if (!list_empty(&tp->rx_done))
2077                         napi_schedule(napi);
2078                 else if (!skb_queue_empty(&tp->tx_queue) &&
2079                          !list_empty(&tp->tx_free))
2080                         napi_schedule(napi);
2081         }
2082
2083 out:
2084         return work_done;
2085 }
2086
2087 static
2088 int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags)
2089 {
2090         int ret;
2091
2092         /* The rx would be stopped, so skip submitting */
2093         if (test_bit(RTL8152_UNPLUG, &tp->flags) ||
2094             !test_bit(WORK_ENABLE, &tp->flags) || !netif_carrier_ok(tp->netdev))
2095                 return 0;
2096
2097         usb_fill_bulk_urb(agg->urb, tp->udev, usb_rcvbulkpipe(tp->udev, 1),
2098                           agg->head, agg_buf_sz,
2099                           (usb_complete_t)read_bulk_callback, agg);
2100
2101         ret = usb_submit_urb(agg->urb, mem_flags);
2102         if (ret == -ENODEV) {
2103                 set_bit(RTL8152_UNPLUG, &tp->flags);
2104                 netif_device_detach(tp->netdev);
2105         } else if (ret) {
2106                 struct urb *urb = agg->urb;
2107                 unsigned long flags;
2108
2109                 urb->actual_length = 0;
2110                 spin_lock_irqsave(&tp->rx_lock, flags);
2111                 list_add_tail(&agg->list, &tp->rx_done);
2112                 spin_unlock_irqrestore(&tp->rx_lock, flags);
2113
2114                 netif_err(tp, rx_err, tp->netdev,
2115                           "Couldn't submit rx[%p], ret = %d\n", agg, ret);
2116
2117                 napi_schedule(&tp->napi);
2118         }
2119
2120         return ret;
2121 }
2122
2123 static void rtl_drop_queued_tx(struct r8152 *tp)
2124 {
2125         struct net_device_stats *stats = &tp->netdev->stats;
2126         struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
2127         struct sk_buff *skb;
2128
2129         if (skb_queue_empty(tx_queue))
2130                 return;
2131
2132         __skb_queue_head_init(&skb_head);
2133         spin_lock_bh(&tx_queue->lock);
2134         skb_queue_splice_init(tx_queue, &skb_head);
2135         spin_unlock_bh(&tx_queue->lock);
2136
2137         while ((skb = __skb_dequeue(&skb_head))) {
2138                 dev_kfree_skb(skb);
2139                 stats->tx_dropped++;
2140         }
2141 }
2142
2143 static void rtl8152_tx_timeout(struct net_device *netdev)
2144 {
2145         struct r8152 *tp = netdev_priv(netdev);
2146
2147         netif_warn(tp, tx_err, netdev, "Tx timeout\n");
2148
2149         usb_queue_reset_device(tp->intf);
2150 }
2151
2152 static void rtl8152_set_rx_mode(struct net_device *netdev)
2153 {
2154         struct r8152 *tp = netdev_priv(netdev);
2155
2156         if (netif_carrier_ok(netdev)) {
2157                 set_bit(RTL8152_SET_RX_MODE, &tp->flags);
2158                 schedule_delayed_work(&tp->schedule, 0);
2159         }
2160 }
2161
2162 static void _rtl8152_set_rx_mode(struct net_device *netdev)
2163 {
2164         struct r8152 *tp = netdev_priv(netdev);
2165         u32 mc_filter[2];       /* Multicast hash filter */
2166         __le32 tmp[2];
2167         u32 ocp_data;
2168
2169         netif_stop_queue(netdev);
2170         ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2171         ocp_data &= ~RCR_ACPT_ALL;
2172         ocp_data |= RCR_AB | RCR_APM;
2173
2174         if (netdev->flags & IFF_PROMISC) {
2175                 /* Unconditionally log net taps. */
2176                 netif_notice(tp, link, netdev, "Promiscuous mode enabled\n");
2177                 ocp_data |= RCR_AM | RCR_AAP;
2178                 mc_filter[1] = 0xffffffff;
2179                 mc_filter[0] = 0xffffffff;
2180         } else if ((netdev_mc_count(netdev) > multicast_filter_limit) ||
2181                    (netdev->flags & IFF_ALLMULTI)) {
2182                 /* Too many to filter perfectly -- accept all multicasts. */
2183                 ocp_data |= RCR_AM;
2184                 mc_filter[1] = 0xffffffff;
2185                 mc_filter[0] = 0xffffffff;
2186         } else {
2187                 struct netdev_hw_addr *ha;
2188
2189                 mc_filter[1] = 0;
2190                 mc_filter[0] = 0;
2191                 netdev_for_each_mc_addr(ha, netdev) {
2192                         int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
2193
2194                         mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
2195                         ocp_data |= RCR_AM;
2196                 }
2197         }
2198
2199         tmp[0] = __cpu_to_le32(swab32(mc_filter[1]));
2200         tmp[1] = __cpu_to_le32(swab32(mc_filter[0]));
2201
2202         pla_ocp_write(tp, PLA_MAR, BYTE_EN_DWORD, sizeof(tmp), tmp);
2203         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2204         netif_wake_queue(netdev);
2205 }
2206
2207 static netdev_features_t
2208 rtl8152_features_check(struct sk_buff *skb, struct net_device *dev,
2209                        netdev_features_t features)
2210 {
2211         u32 mss = skb_shinfo(skb)->gso_size;
2212         int max_offset = mss ? GTTCPHO_MAX : TCPHO_MAX;
2213         int offset = skb_transport_offset(skb);
2214
2215         if ((mss || skb->ip_summed == CHECKSUM_PARTIAL) && offset > max_offset)
2216                 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
2217         else if ((skb->len + sizeof(struct tx_desc)) > agg_buf_sz)
2218                 features &= ~NETIF_F_GSO_MASK;
2219
2220         return features;
2221 }
2222
2223 static netdev_tx_t rtl8152_start_xmit(struct sk_buff *skb,
2224                                       struct net_device *netdev)
2225 {
2226         struct r8152 *tp = netdev_priv(netdev);
2227
2228         skb_tx_timestamp(skb);
2229
2230         skb_queue_tail(&tp->tx_queue, skb);
2231
2232         if (!list_empty(&tp->tx_free)) {
2233                 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
2234                         set_bit(SCHEDULE_NAPI, &tp->flags);
2235                         schedule_delayed_work(&tp->schedule, 0);
2236                 } else {
2237                         usb_mark_last_busy(tp->udev);
2238                         napi_schedule(&tp->napi);
2239                 }
2240         } else if (skb_queue_len(&tp->tx_queue) > tp->tx_qlen) {
2241                 netif_stop_queue(netdev);
2242         }
2243
2244         return NETDEV_TX_OK;
2245 }
2246
2247 static void r8152b_reset_packet_filter(struct r8152 *tp)
2248 {
2249         u32     ocp_data;
2250
2251         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC);
2252         ocp_data &= ~FMC_FCR_MCU_EN;
2253         ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
2254         ocp_data |= FMC_FCR_MCU_EN;
2255         ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
2256 }
2257
2258 static void rtl8152_nic_reset(struct r8152 *tp)
2259 {
2260         int     i;
2261
2262         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, CR_RST);
2263
2264         for (i = 0; i < 1000; i++) {
2265                 if (!(ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR) & CR_RST))
2266                         break;
2267                 usleep_range(100, 400);
2268         }
2269 }
2270
2271 static void set_tx_qlen(struct r8152 *tp)
2272 {
2273         struct net_device *netdev = tp->netdev;
2274
2275         tp->tx_qlen = agg_buf_sz / (netdev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN +
2276                                     sizeof(struct tx_desc));
2277 }
2278
2279 static inline u8 rtl8152_get_speed(struct r8152 *tp)
2280 {
2281         return ocp_read_byte(tp, MCU_TYPE_PLA, PLA_PHYSTATUS);
2282 }
2283
2284 static void rtl_set_eee_plus(struct r8152 *tp)
2285 {
2286         u32 ocp_data;
2287         u8 speed;
2288
2289         speed = rtl8152_get_speed(tp);
2290         if (speed & _10bps) {
2291                 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
2292                 ocp_data |= EEEP_CR_EEEP_TX;
2293                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
2294         } else {
2295                 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
2296                 ocp_data &= ~EEEP_CR_EEEP_TX;
2297                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
2298         }
2299 }
2300
2301 static void rxdy_gated_en(struct r8152 *tp, bool enable)
2302 {
2303         u32 ocp_data;
2304
2305         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1);
2306         if (enable)
2307                 ocp_data |= RXDY_GATED_EN;
2308         else
2309                 ocp_data &= ~RXDY_GATED_EN;
2310         ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data);
2311 }
2312
2313 static int rtl_start_rx(struct r8152 *tp)
2314 {
2315         int i, ret = 0;
2316
2317         INIT_LIST_HEAD(&tp->rx_done);
2318         for (i = 0; i < RTL8152_MAX_RX; i++) {
2319                 INIT_LIST_HEAD(&tp->rx_info[i].list);
2320                 ret = r8152_submit_rx(tp, &tp->rx_info[i], GFP_KERNEL);
2321                 if (ret)
2322                         break;
2323         }
2324
2325         if (ret && ++i < RTL8152_MAX_RX) {
2326                 struct list_head rx_queue;
2327                 unsigned long flags;
2328
2329                 INIT_LIST_HEAD(&rx_queue);
2330
2331                 do {
2332                         struct rx_agg *agg = &tp->rx_info[i++];
2333                         struct urb *urb = agg->urb;
2334
2335                         urb->actual_length = 0;
2336                         list_add_tail(&agg->list, &rx_queue);
2337                 } while (i < RTL8152_MAX_RX);
2338
2339                 spin_lock_irqsave(&tp->rx_lock, flags);
2340                 list_splice_tail(&rx_queue, &tp->rx_done);
2341                 spin_unlock_irqrestore(&tp->rx_lock, flags);
2342         }
2343
2344         return ret;
2345 }
2346
2347 static int rtl_stop_rx(struct r8152 *tp)
2348 {
2349         int i;
2350
2351         for (i = 0; i < RTL8152_MAX_RX; i++)
2352                 usb_kill_urb(tp->rx_info[i].urb);
2353
2354         while (!skb_queue_empty(&tp->rx_queue))
2355                 dev_kfree_skb(__skb_dequeue(&tp->rx_queue));
2356
2357         return 0;
2358 }
2359
2360 static int rtl_enable(struct r8152 *tp)
2361 {
2362         u32 ocp_data;
2363
2364         r8152b_reset_packet_filter(tp);
2365
2366         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR);
2367         ocp_data |= CR_RE | CR_TE;
2368         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data);
2369
2370         rxdy_gated_en(tp, false);
2371
2372         return 0;
2373 }
2374
2375 static int rtl8152_enable(struct r8152 *tp)
2376 {
2377         if (test_bit(RTL8152_UNPLUG, &tp->flags))
2378                 return -ENODEV;
2379
2380         set_tx_qlen(tp);
2381         rtl_set_eee_plus(tp);
2382
2383         return rtl_enable(tp);
2384 }
2385
2386 static inline void r8153b_rx_agg_chg_indicate(struct r8152 *tp)
2387 {
2388         ocp_write_byte(tp, MCU_TYPE_USB, USB_UPT_RXDMA_OWN,
2389                        OWN_UPDATE | OWN_CLEAR);
2390 }
2391
2392 static void r8153_set_rx_early_timeout(struct r8152 *tp)
2393 {
2394         u32 ocp_data = tp->coalesce / 8;
2395
2396         switch (tp->version) {
2397         case RTL_VER_03:
2398         case RTL_VER_04:
2399         case RTL_VER_05:
2400         case RTL_VER_06:
2401                 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT,
2402                                ocp_data);
2403                 break;
2404
2405         case RTL_VER_08:
2406         case RTL_VER_09:
2407                 /* The RTL8153B uses USB_RX_EXTRA_AGGR_TMR for rx timeout
2408                  * primarily. For USB_RX_EARLY_TIMEOUT, we fix it to 128ns.
2409                  */
2410                 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT,
2411                                128 / 8);
2412                 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EXTRA_AGGR_TMR,
2413                                ocp_data);
2414                 r8153b_rx_agg_chg_indicate(tp);
2415                 break;
2416
2417         default:
2418                 break;
2419         }
2420 }
2421
2422 static void r8153_set_rx_early_size(struct r8152 *tp)
2423 {
2424         u32 ocp_data = agg_buf_sz - rx_reserved_size(tp->netdev->mtu);
2425
2426         switch (tp->version) {
2427         case RTL_VER_03:
2428         case RTL_VER_04:
2429         case RTL_VER_05:
2430         case RTL_VER_06:
2431                 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE,
2432                                ocp_data / 4);
2433                 break;
2434         case RTL_VER_08:
2435         case RTL_VER_09:
2436                 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE,
2437                                ocp_data / 8);
2438                 r8153b_rx_agg_chg_indicate(tp);
2439                 break;
2440         default:
2441                 WARN_ON_ONCE(1);
2442                 break;
2443         }
2444 }
2445
2446 static int rtl8153_enable(struct r8152 *tp)
2447 {
2448         if (test_bit(RTL8152_UNPLUG, &tp->flags))
2449                 return -ENODEV;
2450
2451         set_tx_qlen(tp);
2452         rtl_set_eee_plus(tp);
2453         r8153_set_rx_early_timeout(tp);
2454         r8153_set_rx_early_size(tp);
2455
2456         return rtl_enable(tp);
2457 }
2458
2459 static void rtl_disable(struct r8152 *tp)
2460 {
2461         u32 ocp_data;
2462         int i;
2463
2464         if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
2465                 rtl_drop_queued_tx(tp);
2466                 return;
2467         }
2468
2469         ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2470         ocp_data &= ~RCR_ACPT_ALL;
2471         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2472
2473         rtl_drop_queued_tx(tp);
2474
2475         for (i = 0; i < RTL8152_MAX_TX; i++)
2476                 usb_kill_urb(tp->tx_info[i].urb);
2477
2478         rxdy_gated_en(tp, true);
2479
2480         for (i = 0; i < 1000; i++) {
2481                 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2482                 if ((ocp_data & FIFO_EMPTY) == FIFO_EMPTY)
2483                         break;
2484                 usleep_range(1000, 2000);
2485         }
2486
2487         for (i = 0; i < 1000; i++) {
2488                 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0) & TCR0_TX_EMPTY)
2489                         break;
2490                 usleep_range(1000, 2000);
2491         }
2492
2493         rtl_stop_rx(tp);
2494
2495         rtl8152_nic_reset(tp);
2496 }
2497
2498 static void r8152_power_cut_en(struct r8152 *tp, bool enable)
2499 {
2500         u32 ocp_data;
2501
2502         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL);
2503         if (enable)
2504                 ocp_data |= POWER_CUT;
2505         else
2506                 ocp_data &= ~POWER_CUT;
2507         ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data);
2508
2509         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS);
2510         ocp_data &= ~RESUME_INDICATE;
2511         ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data);
2512 }
2513
2514 static void rtl_rx_vlan_en(struct r8152 *tp, bool enable)
2515 {
2516         u32 ocp_data;
2517
2518         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
2519         if (enable)
2520                 ocp_data |= CPCR_RX_VLAN;
2521         else
2522                 ocp_data &= ~CPCR_RX_VLAN;
2523         ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
2524 }
2525
2526 static int rtl8152_set_features(struct net_device *dev,
2527                                 netdev_features_t features)
2528 {
2529         netdev_features_t changed = features ^ dev->features;
2530         struct r8152 *tp = netdev_priv(dev);
2531         int ret;
2532
2533         ret = usb_autopm_get_interface(tp->intf);
2534         if (ret < 0)
2535                 goto out;
2536
2537         mutex_lock(&tp->control);
2538
2539         if (changed & NETIF_F_HW_VLAN_CTAG_RX) {
2540                 if (features & NETIF_F_HW_VLAN_CTAG_RX)
2541                         rtl_rx_vlan_en(tp, true);
2542                 else
2543                         rtl_rx_vlan_en(tp, false);
2544         }
2545
2546         mutex_unlock(&tp->control);
2547
2548         usb_autopm_put_interface(tp->intf);
2549
2550 out:
2551         return ret;
2552 }
2553
2554 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
2555
2556 static u32 __rtl_get_wol(struct r8152 *tp)
2557 {
2558         u32 ocp_data;
2559         u32 wolopts = 0;
2560
2561         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2562         if (ocp_data & LINK_ON_WAKE_EN)
2563                 wolopts |= WAKE_PHY;
2564
2565         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
2566         if (ocp_data & UWF_EN)
2567                 wolopts |= WAKE_UCAST;
2568         if (ocp_data & BWF_EN)
2569                 wolopts |= WAKE_BCAST;
2570         if (ocp_data & MWF_EN)
2571                 wolopts |= WAKE_MCAST;
2572
2573         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
2574         if (ocp_data & MAGIC_EN)
2575                 wolopts |= WAKE_MAGIC;
2576
2577         return wolopts;
2578 }
2579
2580 static void __rtl_set_wol(struct r8152 *tp, u32 wolopts)
2581 {
2582         u32 ocp_data;
2583
2584         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
2585
2586         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2587         ocp_data &= ~LINK_ON_WAKE_EN;
2588         if (wolopts & WAKE_PHY)
2589                 ocp_data |= LINK_ON_WAKE_EN;
2590         ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
2591
2592         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
2593         ocp_data &= ~(UWF_EN | BWF_EN | MWF_EN);
2594         if (wolopts & WAKE_UCAST)
2595                 ocp_data |= UWF_EN;
2596         if (wolopts & WAKE_BCAST)
2597                 ocp_data |= BWF_EN;
2598         if (wolopts & WAKE_MCAST)
2599                 ocp_data |= MWF_EN;
2600         ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG5, ocp_data);
2601
2602         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
2603
2604         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
2605         ocp_data &= ~MAGIC_EN;
2606         if (wolopts & WAKE_MAGIC)
2607                 ocp_data |= MAGIC_EN;
2608         ocp_write_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL, ocp_data);
2609
2610         if (wolopts & WAKE_ANY)
2611                 device_set_wakeup_enable(&tp->udev->dev, true);
2612         else
2613                 device_set_wakeup_enable(&tp->udev->dev, false);
2614 }
2615
2616 static void r8153_mac_clk_spd(struct r8152 *tp, bool enable)
2617 {
2618         /* MAC clock speed down */
2619         if (enable) {
2620                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL,
2621                                ALDPS_SPDWN_RATIO);
2622                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2,
2623                                EEE_SPDWN_RATIO);
2624                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3,
2625                                PKT_AVAIL_SPDWN_EN | SUSPEND_SPDWN_EN |
2626                                U1U2_SPDWN_EN | L1_SPDWN_EN);
2627                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4,
2628                                PWRSAVE_SPDWN_EN | RXDV_SPDWN_EN | TX10MIDLE_EN |
2629                                TP100_SPDWN_EN | TP500_SPDWN_EN | EEE_SPDWN_EN |
2630                                TP1000_SPDWN_EN);
2631         } else {
2632                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, 0);
2633                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, 0);
2634                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, 0);
2635                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, 0);
2636         }
2637 }
2638
2639 static void r8153_u1u2en(struct r8152 *tp, bool enable)
2640 {
2641         u8 u1u2[8];
2642
2643         if (enable)
2644                 memset(u1u2, 0xff, sizeof(u1u2));
2645         else
2646                 memset(u1u2, 0x00, sizeof(u1u2));
2647
2648         usb_ocp_write(tp, USB_TOLERANCE, BYTE_EN_SIX_BYTES, sizeof(u1u2), u1u2);
2649 }
2650
2651 static void r8153b_u1u2en(struct r8152 *tp, bool enable)
2652 {
2653         u32 ocp_data;
2654
2655         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_LPM_CONFIG);
2656         if (enable)
2657                 ocp_data |= LPM_U1U2_EN;
2658         else
2659                 ocp_data &= ~LPM_U1U2_EN;
2660
2661         ocp_write_word(tp, MCU_TYPE_USB, USB_LPM_CONFIG, ocp_data);
2662 }
2663
2664 static void r8153_u2p3en(struct r8152 *tp, bool enable)
2665 {
2666         u32 ocp_data;
2667
2668         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL);
2669         if (enable)
2670                 ocp_data |= U2P3_ENABLE;
2671         else
2672                 ocp_data &= ~U2P3_ENABLE;
2673         ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data);
2674 }
2675
2676 static void r8153b_ups_flags_w1w0(struct r8152 *tp, u32 set, u32 clear)
2677 {
2678         u32 ocp_data;
2679
2680         ocp_data = ocp_read_dword(tp, MCU_TYPE_USB, USB_UPS_FLAGS);
2681         ocp_data &= ~clear;
2682         ocp_data |= set;
2683         ocp_write_dword(tp, MCU_TYPE_USB, USB_UPS_FLAGS, ocp_data);
2684 }
2685
2686 static void r8153b_green_en(struct r8152 *tp, bool enable)
2687 {
2688         u16 data;
2689
2690         if (enable) {
2691                 sram_write(tp, 0x8045, 0);      /* 10M abiq&ldvbias */
2692                 sram_write(tp, 0x804d, 0x1222); /* 100M short abiq&ldvbias */
2693                 sram_write(tp, 0x805d, 0x0022); /* 1000M short abiq&ldvbias */
2694         } else {
2695                 sram_write(tp, 0x8045, 0x2444); /* 10M abiq&ldvbias */
2696                 sram_write(tp, 0x804d, 0x2444); /* 100M short abiq&ldvbias */
2697                 sram_write(tp, 0x805d, 0x2444); /* 1000M short abiq&ldvbias */
2698         }
2699
2700         data = sram_read(tp, SRAM_GREEN_CFG);
2701         data |= GREEN_ETH_EN;
2702         sram_write(tp, SRAM_GREEN_CFG, data);
2703
2704         r8153b_ups_flags_w1w0(tp, UPS_FLAGS_EN_GREEN, 0);
2705 }
2706
2707 static u16 r8153_phy_status(struct r8152 *tp, u16 desired)
2708 {
2709         u16 data;
2710         int i;
2711
2712         for (i = 0; i < 500; i++) {
2713                 data = ocp_reg_read(tp, OCP_PHY_STATUS);
2714                 data &= PHY_STAT_MASK;
2715                 if (desired) {
2716                         if (data == desired)
2717                                 break;
2718                 } else if (data == PHY_STAT_LAN_ON || data == PHY_STAT_PWRDN ||
2719                            data == PHY_STAT_EXT_INIT) {
2720                         break;
2721                 }
2722
2723                 msleep(20);
2724         }
2725
2726         return data;
2727 }
2728
2729 static void r8153b_ups_en(struct r8152 *tp, bool enable)
2730 {
2731         u32 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_POWER_CUT);
2732
2733         if (enable) {
2734                 ocp_data |= UPS_EN | USP_PREWAKE | PHASE2_EN;
2735                 ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
2736
2737                 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, 0xcfff);
2738                 ocp_data |= BIT(0);
2739                 ocp_write_byte(tp, MCU_TYPE_USB, 0xcfff, ocp_data);
2740         } else {
2741                 u16 data;
2742
2743                 ocp_data &= ~(UPS_EN | USP_PREWAKE);
2744                 ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
2745
2746                 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, 0xcfff);
2747                 ocp_data &= ~BIT(0);
2748                 ocp_write_byte(tp, MCU_TYPE_USB, 0xcfff, ocp_data);
2749
2750                 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
2751                 ocp_data &= ~PCUT_STATUS;
2752                 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
2753
2754                 data = r8153_phy_status(tp, 0);
2755
2756                 switch (data) {
2757                 case PHY_STAT_PWRDN:
2758                 case PHY_STAT_EXT_INIT:
2759                         r8153b_green_en(tp,
2760                                         test_bit(GREEN_ETHERNET, &tp->flags));
2761
2762                         data = r8152_mdio_read(tp, MII_BMCR);
2763                         data &= ~BMCR_PDOWN;
2764                         data |= BMCR_RESET;
2765                         r8152_mdio_write(tp, MII_BMCR, data);
2766
2767                         data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
2768                         /* fall through */
2769
2770                 default:
2771                         if (data != PHY_STAT_LAN_ON)
2772                                 netif_warn(tp, link, tp->netdev,
2773                                            "PHY not ready");
2774                         break;
2775                 }
2776         }
2777 }
2778
2779 static void r8153_power_cut_en(struct r8152 *tp, bool enable)
2780 {
2781         u32 ocp_data;
2782
2783         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT);
2784         if (enable)
2785                 ocp_data |= PWR_EN | PHASE2_EN;
2786         else
2787                 ocp_data &= ~(PWR_EN | PHASE2_EN);
2788         ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
2789
2790         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
2791         ocp_data &= ~PCUT_STATUS;
2792         ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
2793 }
2794
2795 static void r8153b_power_cut_en(struct r8152 *tp, bool enable)
2796 {
2797         u32 ocp_data;
2798
2799         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT);
2800         if (enable)
2801                 ocp_data |= PWR_EN | PHASE2_EN;
2802         else
2803                 ocp_data &= ~PWR_EN;
2804         ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
2805
2806         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
2807         ocp_data &= ~PCUT_STATUS;
2808         ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
2809 }
2810
2811 static void r8153b_queue_wake(struct r8152 *tp, bool enable)
2812 {
2813         u32 ocp_data;
2814
2815         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, 0xd38a);
2816         if (enable)
2817                 ocp_data |= BIT(0);
2818         else
2819                 ocp_data &= ~BIT(0);
2820         ocp_write_byte(tp, MCU_TYPE_PLA, 0xd38a, ocp_data);
2821
2822         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, 0xd38c);
2823         ocp_data &= ~BIT(0);
2824         ocp_write_byte(tp, MCU_TYPE_PLA, 0xd38c, ocp_data);
2825 }
2826
2827 static bool rtl_can_wakeup(struct r8152 *tp)
2828 {
2829         struct usb_device *udev = tp->udev;
2830
2831         return (udev->actconfig->desc.bmAttributes & USB_CONFIG_ATT_WAKEUP);
2832 }
2833
2834 static void rtl_runtime_suspend_enable(struct r8152 *tp, bool enable)
2835 {
2836         if (enable) {
2837                 u32 ocp_data;
2838
2839                 __rtl_set_wol(tp, WAKE_ANY);
2840
2841                 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
2842
2843                 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2844                 ocp_data |= LINK_OFF_WAKE_EN;
2845                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
2846
2847                 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
2848         } else {
2849                 u32 ocp_data;
2850
2851                 __rtl_set_wol(tp, tp->saved_wolopts);
2852
2853                 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
2854
2855                 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2856                 ocp_data &= ~LINK_OFF_WAKE_EN;
2857                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
2858
2859                 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
2860         }
2861 }
2862
2863 static void rtl8153_runtime_enable(struct r8152 *tp, bool enable)
2864 {
2865         if (enable) {
2866                 r8153_u1u2en(tp, false);
2867                 r8153_u2p3en(tp, false);
2868                 r8153_mac_clk_spd(tp, true);
2869                 rtl_runtime_suspend_enable(tp, true);
2870         } else {
2871                 rtl_runtime_suspend_enable(tp, false);
2872                 r8153_mac_clk_spd(tp, false);
2873
2874                 switch (tp->version) {
2875                 case RTL_VER_03:
2876                 case RTL_VER_04:
2877                         break;
2878                 case RTL_VER_05:
2879                 case RTL_VER_06:
2880                 default:
2881                         r8153_u2p3en(tp, true);
2882                         break;
2883                 }
2884
2885                 r8153_u1u2en(tp, true);
2886         }
2887 }
2888
2889 static void rtl8153b_runtime_enable(struct r8152 *tp, bool enable)
2890 {
2891         if (enable) {
2892                 r8153b_queue_wake(tp, true);
2893                 r8153b_u1u2en(tp, false);
2894                 r8153_u2p3en(tp, false);
2895                 rtl_runtime_suspend_enable(tp, true);
2896                 r8153b_ups_en(tp, true);
2897         } else {
2898                 r8153b_ups_en(tp, false);
2899                 r8153b_queue_wake(tp, false);
2900                 rtl_runtime_suspend_enable(tp, false);
2901                 r8153_u2p3en(tp, true);
2902                 r8153b_u1u2en(tp, true);
2903         }
2904 }
2905
2906 static void r8153_teredo_off(struct r8152 *tp)
2907 {
2908         u32 ocp_data;
2909
2910         switch (tp->version) {
2911         case RTL_VER_01:
2912         case RTL_VER_02:
2913         case RTL_VER_03:
2914         case RTL_VER_04:
2915         case RTL_VER_05:
2916         case RTL_VER_06:
2917         case RTL_VER_07:
2918                 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
2919                 ocp_data &= ~(TEREDO_SEL | TEREDO_RS_EVENT_MASK |
2920                               OOB_TEREDO_EN);
2921                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
2922                 break;
2923
2924         case RTL_VER_08:
2925         case RTL_VER_09:
2926                 /* The bit 0 ~ 7 are relative with teredo settings. They are
2927                  * W1C (write 1 to clear), so set all 1 to disable it.
2928                  */
2929                 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, 0xff);
2930                 break;
2931
2932         default:
2933                 break;
2934         }
2935
2936         ocp_write_word(tp, MCU_TYPE_PLA, PLA_WDT6_CTRL, WDT6_SET_MODE);
2937         ocp_write_word(tp, MCU_TYPE_PLA, PLA_REALWOW_TIMER, 0);
2938         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TEREDO_TIMER, 0);
2939 }
2940
2941 static void rtl_reset_bmu(struct r8152 *tp)
2942 {
2943         u32 ocp_data;
2944
2945         ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_BMU_RESET);
2946         ocp_data &= ~(BMU_RESET_EP_IN | BMU_RESET_EP_OUT);
2947         ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data);
2948         ocp_data |= BMU_RESET_EP_IN | BMU_RESET_EP_OUT;
2949         ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data);
2950 }
2951
2952 static void r8152_aldps_en(struct r8152 *tp, bool enable)
2953 {
2954         if (enable) {
2955                 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPWRSAVE | ENPDNPS |
2956                                                     LINKENA | DIS_SDSAVE);
2957         } else {
2958                 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPDNPS | LINKENA |
2959                                                     DIS_SDSAVE);
2960                 msleep(20);
2961         }
2962 }
2963
2964 static inline void r8152_mmd_indirect(struct r8152 *tp, u16 dev, u16 reg)
2965 {
2966         ocp_reg_write(tp, OCP_EEE_AR, FUN_ADDR | dev);
2967         ocp_reg_write(tp, OCP_EEE_DATA, reg);
2968         ocp_reg_write(tp, OCP_EEE_AR, FUN_DATA | dev);
2969 }
2970
2971 static u16 r8152_mmd_read(struct r8152 *tp, u16 dev, u16 reg)
2972 {
2973         u16 data;
2974
2975         r8152_mmd_indirect(tp, dev, reg);
2976         data = ocp_reg_read(tp, OCP_EEE_DATA);
2977         ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
2978
2979         return data;
2980 }
2981
2982 static void r8152_mmd_write(struct r8152 *tp, u16 dev, u16 reg, u16 data)
2983 {
2984         r8152_mmd_indirect(tp, dev, reg);
2985         ocp_reg_write(tp, OCP_EEE_DATA, data);
2986         ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
2987 }
2988
2989 static void r8152_eee_en(struct r8152 *tp, bool enable)
2990 {
2991         u16 config1, config2, config3;
2992         u32 ocp_data;
2993
2994         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
2995         config1 = ocp_reg_read(tp, OCP_EEE_CONFIG1) & ~sd_rise_time_mask;
2996         config2 = ocp_reg_read(tp, OCP_EEE_CONFIG2);
2997         config3 = ocp_reg_read(tp, OCP_EEE_CONFIG3) & ~fast_snr_mask;
2998
2999         if (enable) {
3000                 ocp_data |= EEE_RX_EN | EEE_TX_EN;
3001                 config1 |= EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN | RX_QUIET_EN;
3002                 config1 |= sd_rise_time(1);
3003                 config2 |= RG_DACQUIET_EN | RG_LDVQUIET_EN;
3004                 config3 |= fast_snr(42);
3005         } else {
3006                 ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
3007                 config1 &= ~(EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN |
3008                              RX_QUIET_EN);
3009                 config1 |= sd_rise_time(7);
3010                 config2 &= ~(RG_DACQUIET_EN | RG_LDVQUIET_EN);
3011                 config3 |= fast_snr(511);
3012         }
3013
3014         ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
3015         ocp_reg_write(tp, OCP_EEE_CONFIG1, config1);
3016         ocp_reg_write(tp, OCP_EEE_CONFIG2, config2);
3017         ocp_reg_write(tp, OCP_EEE_CONFIG3, config3);
3018 }
3019
3020 static void r8152b_enable_eee(struct r8152 *tp)
3021 {
3022         r8152_eee_en(tp, true);
3023         r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, MDIO_EEE_100TX);
3024 }
3025
3026 static void r8152b_enable_fc(struct r8152 *tp)
3027 {
3028         u16 anar;
3029
3030         anar = r8152_mdio_read(tp, MII_ADVERTISE);
3031         anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
3032         r8152_mdio_write(tp, MII_ADVERTISE, anar);
3033 }
3034
3035 static void rtl8152_disable(struct r8152 *tp)
3036 {
3037         r8152_aldps_en(tp, false);
3038         rtl_disable(tp);
3039         r8152_aldps_en(tp, true);
3040 }
3041
3042 static void r8152b_hw_phy_cfg(struct r8152 *tp)
3043 {
3044         r8152b_enable_eee(tp);
3045         r8152_aldps_en(tp, true);
3046         r8152b_enable_fc(tp);
3047
3048         set_bit(PHY_RESET, &tp->flags);
3049 }
3050
3051 static void r8152b_exit_oob(struct r8152 *tp)
3052 {
3053         u32 ocp_data;
3054         int i;
3055
3056         ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
3057         ocp_data &= ~RCR_ACPT_ALL;
3058         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
3059
3060         rxdy_gated_en(tp, true);
3061         r8153_teredo_off(tp);
3062         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
3063         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00);
3064
3065         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3066         ocp_data &= ~NOW_IS_OOB;
3067         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
3068
3069         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
3070         ocp_data &= ~MCU_BORW_EN;
3071         ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
3072
3073         for (i = 0; i < 1000; i++) {
3074                 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3075                 if (ocp_data & LINK_LIST_READY)
3076                         break;
3077                 usleep_range(1000, 2000);
3078         }
3079
3080         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
3081         ocp_data |= RE_INIT_LL;
3082         ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
3083
3084         for (i = 0; i < 1000; i++) {
3085                 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3086                 if (ocp_data & LINK_LIST_READY)
3087                         break;
3088                 usleep_range(1000, 2000);
3089         }
3090
3091         rtl8152_nic_reset(tp);
3092
3093         /* rx share fifo credit full threshold */
3094         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
3095
3096         if (tp->udev->speed == USB_SPEED_FULL ||
3097             tp->udev->speed == USB_SPEED_LOW) {
3098                 /* rx share fifo credit near full threshold */
3099                 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
3100                                 RXFIFO_THR2_FULL);
3101                 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
3102                                 RXFIFO_THR3_FULL);
3103         } else {
3104                 /* rx share fifo credit near full threshold */
3105                 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
3106                                 RXFIFO_THR2_HIGH);
3107                 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
3108                                 RXFIFO_THR3_HIGH);
3109         }
3110
3111         /* TX share fifo free credit full threshold */
3112         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL);
3113
3114         ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD);
3115         ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_HIGH);
3116         ocp_write_dword(tp, MCU_TYPE_USB, USB_TX_DMA,
3117                         TEST_MODE_DISABLE | TX_SIZE_ADJUST1);
3118
3119         rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
3120
3121         ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
3122
3123         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
3124         ocp_data |= TCR0_AUTO_FIFO;
3125         ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
3126 }
3127
3128 static void r8152b_enter_oob(struct r8152 *tp)
3129 {
3130         u32 ocp_data;
3131         int i;
3132
3133         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3134         ocp_data &= ~NOW_IS_OOB;
3135         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
3136
3137         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB);
3138         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB);
3139         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB);
3140
3141         rtl_disable(tp);
3142
3143         for (i = 0; i < 1000; i++) {
3144                 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3145                 if (ocp_data & LINK_LIST_READY)
3146                         break;
3147                 usleep_range(1000, 2000);
3148         }
3149
3150         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
3151         ocp_data |= RE_INIT_LL;
3152         ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
3153
3154         for (i = 0; i < 1000; i++) {
3155                 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3156                 if (ocp_data & LINK_LIST_READY)
3157                         break;
3158                 usleep_range(1000, 2000);
3159         }
3160
3161         ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
3162
3163         rtl_rx_vlan_en(tp, true);
3164
3165         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR);
3166         ocp_data |= ALDPS_PROXY_MODE;
3167         ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data);
3168
3169         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3170         ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
3171         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
3172
3173         rxdy_gated_en(tp, false);
3174
3175         ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
3176         ocp_data |= RCR_APM | RCR_AM | RCR_AB;
3177         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
3178 }
3179
3180 static int r8153_patch_request(struct r8152 *tp, bool request)
3181 {
3182         u16 data;
3183         int i;
3184
3185         data = ocp_reg_read(tp, OCP_PHY_PATCH_CMD);
3186         if (request)
3187                 data |= PATCH_REQUEST;
3188         else
3189                 data &= ~PATCH_REQUEST;
3190         ocp_reg_write(tp, OCP_PHY_PATCH_CMD, data);
3191
3192         for (i = 0; request && i < 5000; i++) {
3193                 usleep_range(1000, 2000);
3194                 if (ocp_reg_read(tp, OCP_PHY_PATCH_STAT) & PATCH_READY)
3195                         break;
3196         }
3197
3198         if (request && !(ocp_reg_read(tp, OCP_PHY_PATCH_STAT) & PATCH_READY)) {
3199                 netif_err(tp, drv, tp->netdev, "patch request fail\n");
3200                 r8153_patch_request(tp, false);
3201                 return -ETIME;
3202         } else {
3203                 return 0;
3204         }
3205 }
3206
3207 static void r8153_aldps_en(struct r8152 *tp, bool enable)
3208 {
3209         u16 data;
3210
3211         data = ocp_reg_read(tp, OCP_POWER_CFG);
3212         if (enable) {
3213                 data |= EN_ALDPS;
3214                 ocp_reg_write(tp, OCP_POWER_CFG, data);
3215         } else {
3216                 int i;
3217
3218                 data &= ~EN_ALDPS;
3219                 ocp_reg_write(tp, OCP_POWER_CFG, data);
3220                 for (i = 0; i < 20; i++) {
3221                         usleep_range(1000, 2000);
3222                         if (ocp_read_word(tp, MCU_TYPE_PLA, 0xe000) & 0x0100)
3223                                 break;
3224                 }
3225         }
3226 }
3227
3228 static void r8153b_aldps_en(struct r8152 *tp, bool enable)
3229 {
3230         r8153_aldps_en(tp, enable);
3231
3232         if (enable)
3233                 r8153b_ups_flags_w1w0(tp, UPS_FLAGS_EN_ALDPS, 0);
3234         else
3235                 r8153b_ups_flags_w1w0(tp, 0, UPS_FLAGS_EN_ALDPS);
3236 }
3237
3238 static void r8153_eee_en(struct r8152 *tp, bool enable)
3239 {
3240         u32 ocp_data;
3241         u16 config;
3242
3243         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
3244         config = ocp_reg_read(tp, OCP_EEE_CFG);
3245
3246         if (enable) {
3247                 ocp_data |= EEE_RX_EN | EEE_TX_EN;
3248                 config |= EEE10_EN;
3249         } else {
3250                 ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
3251                 config &= ~EEE10_EN;
3252         }
3253
3254         ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
3255         ocp_reg_write(tp, OCP_EEE_CFG, config);
3256 }
3257
3258 static void r8153b_eee_en(struct r8152 *tp, bool enable)
3259 {
3260         r8153_eee_en(tp, enable);
3261
3262         if (enable)
3263                 r8153b_ups_flags_w1w0(tp, UPS_FLAGS_EN_EEE, 0);
3264         else
3265                 r8153b_ups_flags_w1w0(tp, 0, UPS_FLAGS_EN_EEE);
3266 }
3267
3268 static void r8153b_enable_fc(struct r8152 *tp)
3269 {
3270         r8152b_enable_fc(tp);
3271         r8153b_ups_flags_w1w0(tp, UPS_FLAGS_EN_FLOW_CTR, 0);
3272 }
3273
3274 static void r8153_hw_phy_cfg(struct r8152 *tp)
3275 {
3276         u32 ocp_data;
3277         u16 data;
3278
3279         /* disable ALDPS before updating the PHY parameters */
3280         r8153_aldps_en(tp, false);
3281
3282         /* disable EEE before updating the PHY parameters */
3283         r8153_eee_en(tp, false);
3284         ocp_reg_write(tp, OCP_EEE_ADV, 0);
3285
3286         if (tp->version == RTL_VER_03) {
3287                 data = ocp_reg_read(tp, OCP_EEE_CFG);
3288                 data &= ~CTAP_SHORT_EN;
3289                 ocp_reg_write(tp, OCP_EEE_CFG, data);
3290         }
3291
3292         data = ocp_reg_read(tp, OCP_POWER_CFG);
3293         data |= EEE_CLKDIV_EN;
3294         ocp_reg_write(tp, OCP_POWER_CFG, data);
3295
3296         data = ocp_reg_read(tp, OCP_DOWN_SPEED);
3297         data |= EN_10M_BGOFF;
3298         ocp_reg_write(tp, OCP_DOWN_SPEED, data);
3299         data = ocp_reg_read(tp, OCP_POWER_CFG);
3300         data |= EN_10M_PLLOFF;
3301         ocp_reg_write(tp, OCP_POWER_CFG, data);
3302         sram_write(tp, SRAM_IMPEDANCE, 0x0b13);
3303
3304         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
3305         ocp_data |= PFM_PWM_SWITCH;
3306         ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
3307
3308         /* Enable LPF corner auto tune */
3309         sram_write(tp, SRAM_LPF_CFG, 0xf70f);
3310
3311         /* Adjust 10M Amplitude */
3312         sram_write(tp, SRAM_10M_AMP1, 0x00af);
3313         sram_write(tp, SRAM_10M_AMP2, 0x0208);
3314
3315         r8153_eee_en(tp, true);
3316         ocp_reg_write(tp, OCP_EEE_ADV, MDIO_EEE_1000T | MDIO_EEE_100TX);
3317
3318         r8153_aldps_en(tp, true);
3319         r8152b_enable_fc(tp);
3320
3321         switch (tp->version) {
3322         case RTL_VER_03:
3323         case RTL_VER_04:
3324                 break;
3325         case RTL_VER_05:
3326         case RTL_VER_06:
3327         default:
3328                 r8153_u2p3en(tp, true);
3329                 break;
3330         }
3331
3332         set_bit(PHY_RESET, &tp->flags);
3333 }
3334
3335 static u32 r8152_efuse_read(struct r8152 *tp, u8 addr)
3336 {
3337         u32 ocp_data;
3338
3339         ocp_write_word(tp, MCU_TYPE_PLA, PLA_EFUSE_CMD, EFUSE_READ_CMD | addr);
3340         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EFUSE_CMD);
3341         ocp_data = (ocp_data & EFUSE_DATA_BIT16) << 9;  /* data of bit16 */
3342         ocp_data |= ocp_read_word(tp, MCU_TYPE_PLA, PLA_EFUSE_DATA);
3343
3344         return ocp_data;
3345 }
3346
3347 static void r8153b_hw_phy_cfg(struct r8152 *tp)
3348 {
3349         u32 ocp_data, ups_flags = 0;
3350         u16 data;
3351
3352         /* disable ALDPS before updating the PHY parameters */
3353         r8153b_aldps_en(tp, false);
3354
3355         /* disable EEE before updating the PHY parameters */
3356         r8153b_eee_en(tp, false);
3357         ocp_reg_write(tp, OCP_EEE_ADV, 0);
3358
3359         r8153b_green_en(tp, test_bit(GREEN_ETHERNET, &tp->flags));
3360
3361         data = sram_read(tp, SRAM_GREEN_CFG);
3362         data |= R_TUNE_EN;
3363         sram_write(tp, SRAM_GREEN_CFG, data);
3364         data = ocp_reg_read(tp, OCP_NCTL_CFG);
3365         data |= PGA_RETURN_EN;
3366         ocp_reg_write(tp, OCP_NCTL_CFG, data);
3367
3368         /* ADC Bias Calibration:
3369          * read efuse offset 0x7d to get a 17-bit data. Remove the dummy/fake
3370          * bit (bit3) to rebuild the real 16-bit data. Write the data to the
3371          * ADC ioffset.
3372          */
3373         ocp_data = r8152_efuse_read(tp, 0x7d);
3374         data = (u16)(((ocp_data & 0x1fff0) >> 1) | (ocp_data & 0x7));
3375         if (data != 0xffff)
3376                 ocp_reg_write(tp, OCP_ADC_IOFFSET, data);
3377
3378         /* ups mode tx-link-pulse timing adjustment:
3379          * rg_saw_cnt = OCP reg 0xC426 Bit[13:0]
3380          * swr_cnt_1ms_ini = 16000000 / rg_saw_cnt
3381          */
3382         ocp_data = ocp_reg_read(tp, 0xc426);
3383         ocp_data &= 0x3fff;
3384         if (ocp_data) {
3385                 u32 swr_cnt_1ms_ini;
3386
3387                 swr_cnt_1ms_ini = (16000000 / ocp_data) & SAW_CNT_1MS_MASK;
3388                 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CFG);
3389                 ocp_data = (ocp_data & ~SAW_CNT_1MS_MASK) | swr_cnt_1ms_ini;
3390                 ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CFG, ocp_data);
3391         }
3392
3393         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
3394         ocp_data |= PFM_PWM_SWITCH;
3395         ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
3396
3397         /* Advnace EEE */
3398         if (!r8153_patch_request(tp, true)) {
3399                 data = ocp_reg_read(tp, OCP_POWER_CFG);
3400                 data |= EEE_CLKDIV_EN;
3401                 ocp_reg_write(tp, OCP_POWER_CFG, data);
3402
3403                 data = ocp_reg_read(tp, OCP_DOWN_SPEED);
3404                 data |= EN_EEE_CMODE | EN_EEE_1000 | EN_10M_CLKDIV;
3405                 ocp_reg_write(tp, OCP_DOWN_SPEED, data);
3406
3407                 ocp_reg_write(tp, OCP_SYSCLK_CFG, 0);
3408                 ocp_reg_write(tp, OCP_SYSCLK_CFG, clk_div_expo(5));
3409
3410                 ups_flags |= UPS_FLAGS_EN_10M_CKDIV | UPS_FLAGS_250M_CKDIV |
3411                              UPS_FLAGS_EN_EEE_CKDIV | UPS_FLAGS_EEE_CMOD_LV_EN |
3412                              UPS_FLAGS_EEE_PLLOFF_GIGA;
3413
3414                 r8153_patch_request(tp, false);
3415         }
3416
3417         r8153b_ups_flags_w1w0(tp, ups_flags, 0);
3418
3419         r8153b_eee_en(tp, true);
3420         ocp_reg_write(tp, OCP_EEE_ADV, MDIO_EEE_1000T | MDIO_EEE_100TX);
3421
3422         r8153b_aldps_en(tp, true);
3423         r8153b_enable_fc(tp);
3424         r8153_u2p3en(tp, true);
3425
3426         set_bit(PHY_RESET, &tp->flags);
3427 }
3428
3429 static void r8153_first_init(struct r8152 *tp)
3430 {
3431         u32 ocp_data;
3432         int i;
3433
3434         r8153_mac_clk_spd(tp, false);
3435         rxdy_gated_en(tp, true);
3436         r8153_teredo_off(tp);
3437
3438         ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
3439         ocp_data &= ~RCR_ACPT_ALL;
3440         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
3441
3442         rtl8152_nic_reset(tp);
3443         rtl_reset_bmu(tp);
3444
3445         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3446         ocp_data &= ~NOW_IS_OOB;
3447         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
3448
3449         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
3450         ocp_data &= ~MCU_BORW_EN;
3451         ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
3452
3453         for (i = 0; i < 1000; i++) {
3454                 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3455                 if (ocp_data & LINK_LIST_READY)
3456                         break;
3457                 usleep_range(1000, 2000);
3458         }
3459
3460         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
3461         ocp_data |= RE_INIT_LL;
3462         ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
3463
3464         for (i = 0; i < 1000; i++) {
3465                 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3466                 if (ocp_data & LINK_LIST_READY)
3467                         break;
3468                 usleep_range(1000, 2000);
3469         }
3470
3471         rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
3472
3473         ocp_data = tp->netdev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN;
3474         ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, ocp_data);
3475         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_JUMBO);
3476
3477         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
3478         ocp_data |= TCR0_AUTO_FIFO;
3479         ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
3480
3481         rtl8152_nic_reset(tp);
3482
3483         /* rx share fifo credit full threshold */
3484         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
3485         ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL);
3486         ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL);
3487         /* TX share fifo free credit full threshold */
3488         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2);
3489 }
3490
3491 static void r8153_enter_oob(struct r8152 *tp)
3492 {
3493         u32 ocp_data;
3494         int i;
3495
3496         r8153_mac_clk_spd(tp, true);
3497
3498         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3499         ocp_data &= ~NOW_IS_OOB;
3500         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
3501
3502         rtl_disable(tp);
3503         rtl_reset_bmu(tp);
3504
3505         for (i = 0; i < 1000; i++) {
3506                 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3507                 if (ocp_data & LINK_LIST_READY)
3508                         break;
3509                 usleep_range(1000, 2000);
3510         }
3511
3512         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
3513         ocp_data |= RE_INIT_LL;
3514         ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
3515
3516         for (i = 0; i < 1000; i++) {
3517                 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3518                 if (ocp_data & LINK_LIST_READY)
3519                         break;
3520                 usleep_range(1000, 2000);
3521         }
3522
3523         ocp_data = tp->netdev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN;
3524         ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, ocp_data);
3525
3526         switch (tp->version) {
3527         case RTL_VER_03:
3528         case RTL_VER_04:
3529         case RTL_VER_05:
3530         case RTL_VER_06:
3531                 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
3532                 ocp_data &= ~TEREDO_WAKE_MASK;
3533                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
3534                 break;
3535
3536         case RTL_VER_08:
3537         case RTL_VER_09:
3538                 /* Clear teredo wake event. bit[15:8] is the teredo wakeup
3539                  * type. Set it to zero. bits[7:0] are the W1C bits about
3540                  * the events. Set them to all 1 to clear them.
3541                  */
3542                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_WAKE_BASE, 0x00ff);
3543                 break;
3544
3545         default:
3546                 break;
3547         }
3548
3549         rtl_rx_vlan_en(tp, true);
3550
3551         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR);
3552         ocp_data |= ALDPS_PROXY_MODE;
3553         ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data);
3554
3555         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3556         ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
3557         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
3558
3559         rxdy_gated_en(tp, false);
3560
3561         ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
3562         ocp_data |= RCR_APM | RCR_AM | RCR_AB;
3563         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
3564 }
3565
3566 static void rtl8153_disable(struct r8152 *tp)
3567 {
3568         r8153_aldps_en(tp, false);
3569         rtl_disable(tp);
3570         rtl_reset_bmu(tp);
3571         r8153_aldps_en(tp, true);
3572 }
3573
3574 static void rtl8153b_disable(struct r8152 *tp)
3575 {
3576         r8153b_aldps_en(tp, false);
3577         rtl_disable(tp);
3578         rtl_reset_bmu(tp);
3579         r8153b_aldps_en(tp, true);
3580 }
3581
3582 static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u16 speed, u8 duplex)
3583 {
3584         u16 bmcr, anar, gbcr;
3585         enum spd_duplex speed_duplex;
3586         int ret = 0;
3587
3588         anar = r8152_mdio_read(tp, MII_ADVERTISE);
3589         anar &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
3590                   ADVERTISE_100HALF | ADVERTISE_100FULL);
3591         if (tp->mii.supports_gmii) {
3592                 gbcr = r8152_mdio_read(tp, MII_CTRL1000);
3593                 gbcr &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
3594         } else {
3595                 gbcr = 0;
3596         }
3597
3598         if (autoneg == AUTONEG_DISABLE) {
3599                 if (speed == SPEED_10) {
3600                         bmcr = 0;
3601                         anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
3602                         speed_duplex = FORCE_10M_HALF;
3603                 } else if (speed == SPEED_100) {
3604                         bmcr = BMCR_SPEED100;
3605                         anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
3606                         speed_duplex = FORCE_100M_HALF;
3607                 } else if (speed == SPEED_1000 && tp->mii.supports_gmii) {
3608                         bmcr = BMCR_SPEED1000;
3609                         gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
3610                         speed_duplex = NWAY_1000M_FULL;
3611                 } else {
3612                         ret = -EINVAL;
3613                         goto out;
3614                 }
3615
3616                 if (duplex == DUPLEX_FULL) {
3617                         bmcr |= BMCR_FULLDPLX;
3618                         if (speed != SPEED_1000)
3619                                 speed_duplex++;
3620                 }
3621         } else {
3622                 if (speed == SPEED_10) {
3623                         if (duplex == DUPLEX_FULL) {
3624                                 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
3625                                 speed_duplex = NWAY_10M_FULL;
3626                         } else {
3627                                 anar |= ADVERTISE_10HALF;
3628                                 speed_duplex = NWAY_10M_HALF;
3629                         }
3630                 } else if (speed == SPEED_100) {
3631                         if (duplex == DUPLEX_FULL) {
3632                                 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
3633                                 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
3634                                 speed_duplex = NWAY_100M_FULL;
3635                         } else {
3636                                 anar |= ADVERTISE_10HALF;
3637                                 anar |= ADVERTISE_100HALF;
3638                                 speed_duplex = NWAY_100M_HALF;
3639                         }
3640                 } else if (speed == SPEED_1000 && tp->mii.supports_gmii) {
3641                         if (duplex == DUPLEX_FULL) {
3642                                 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
3643                                 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
3644                                 gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
3645                         } else {
3646                                 anar |= ADVERTISE_10HALF;
3647                                 anar |= ADVERTISE_100HALF;
3648                                 gbcr |= ADVERTISE_1000HALF;
3649                         }
3650                         speed_duplex = NWAY_1000M_FULL;
3651                 } else {
3652                         ret = -EINVAL;
3653                         goto out;
3654                 }
3655
3656                 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
3657         }
3658
3659         if (test_and_clear_bit(PHY_RESET, &tp->flags))
3660                 bmcr |= BMCR_RESET;
3661
3662         if (tp->mii.supports_gmii)
3663                 r8152_mdio_write(tp, MII_CTRL1000, gbcr);
3664
3665         r8152_mdio_write(tp, MII_ADVERTISE, anar);
3666         r8152_mdio_write(tp, MII_BMCR, bmcr);
3667
3668         switch (tp->version) {
3669         case RTL_VER_08:
3670         case RTL_VER_09:
3671                 r8153b_ups_flags_w1w0(tp, ups_flags_speed(speed_duplex),
3672                                       UPS_FLAGS_SPEED_MASK);
3673                 break;
3674
3675         default:
3676                 break;
3677         }
3678
3679         if (bmcr & BMCR_RESET) {
3680                 int i;
3681
3682                 for (i = 0; i < 50; i++) {
3683                         msleep(20);
3684                         if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0)
3685                                 break;
3686                 }
3687         }
3688
3689 out:
3690         return ret;
3691 }
3692
3693 static void rtl8152_up(struct r8152 *tp)
3694 {
3695         if (test_bit(RTL8152_UNPLUG, &tp->flags))
3696                 return;
3697
3698         r8152_aldps_en(tp, false);
3699         r8152b_exit_oob(tp);
3700         r8152_aldps_en(tp, true);
3701 }
3702
3703 static void rtl8152_down(struct r8152 *tp)
3704 {
3705         if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
3706                 rtl_drop_queued_tx(tp);
3707                 return;
3708         }
3709
3710         r8152_power_cut_en(tp, false);
3711         r8152_aldps_en(tp, false);
3712         r8152b_enter_oob(tp);
3713         r8152_aldps_en(tp, true);
3714 }
3715
3716 static void rtl8153_up(struct r8152 *tp)
3717 {
3718         if (test_bit(RTL8152_UNPLUG, &tp->flags))
3719                 return;
3720
3721         r8153_u1u2en(tp, false);
3722         r8153_u2p3en(tp, false);
3723         r8153_aldps_en(tp, false);
3724         r8153_first_init(tp);
3725         r8153_aldps_en(tp, true);
3726
3727         switch (tp->version) {
3728         case RTL_VER_03:
3729         case RTL_VER_04:
3730                 break;
3731         case RTL_VER_05:
3732         case RTL_VER_06:
3733         default:
3734                 r8153_u2p3en(tp, true);
3735                 break;
3736         }
3737
3738         r8153_u1u2en(tp, true);
3739 }
3740
3741 static void rtl8153_down(struct r8152 *tp)
3742 {
3743         if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
3744                 rtl_drop_queued_tx(tp);
3745                 return;
3746         }
3747
3748         r8153_u1u2en(tp, false);
3749         r8153_u2p3en(tp, false);
3750         r8153_power_cut_en(tp, false);
3751         r8153_aldps_en(tp, false);
3752         r8153_enter_oob(tp);
3753         r8153_aldps_en(tp, true);
3754 }
3755
3756 static void rtl8153b_up(struct r8152 *tp)
3757 {
3758         if (test_bit(RTL8152_UNPLUG, &tp->flags))
3759                 return;
3760
3761         r8153b_u1u2en(tp, false);
3762         r8153_u2p3en(tp, false);
3763         r8153b_aldps_en(tp, false);
3764
3765         r8153_first_init(tp);
3766         ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_B);
3767
3768         r8153b_aldps_en(tp, true);
3769         r8153_u2p3en(tp, true);
3770         r8153b_u1u2en(tp, true);
3771 }
3772
3773 static void rtl8153b_down(struct r8152 *tp)
3774 {
3775         if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
3776                 rtl_drop_queued_tx(tp);
3777                 return;
3778         }
3779
3780         r8153b_u1u2en(tp, false);
3781         r8153_u2p3en(tp, false);
3782         r8153b_power_cut_en(tp, false);
3783         r8153b_aldps_en(tp, false);
3784         r8153_enter_oob(tp);
3785         r8153b_aldps_en(tp, true);
3786 }
3787
3788 static bool rtl8152_in_nway(struct r8152 *tp)
3789 {
3790         u16 nway_state;
3791
3792         ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, 0x2000);
3793         tp->ocp_base = 0x2000;
3794         ocp_write_byte(tp, MCU_TYPE_PLA, 0xb014, 0x4c);         /* phy state */
3795         nway_state = ocp_read_word(tp, MCU_TYPE_PLA, 0xb01a);
3796
3797         /* bit 15: TXDIS_STATE, bit 14: ABD_STATE */
3798         if (nway_state & 0xc000)
3799                 return false;
3800         else
3801                 return true;
3802 }
3803
3804 static bool rtl8153_in_nway(struct r8152 *tp)
3805 {
3806         u16 phy_state = ocp_reg_read(tp, OCP_PHY_STATE) & 0xff;
3807
3808         if (phy_state == TXDIS_STATE || phy_state == ABD_STATE)
3809                 return false;
3810         else
3811                 return true;
3812 }
3813
3814 static void set_carrier(struct r8152 *tp)
3815 {
3816         struct net_device *netdev = tp->netdev;
3817         struct napi_struct *napi = &tp->napi;
3818         u8 speed;
3819
3820         speed = rtl8152_get_speed(tp);
3821
3822         if (speed & LINK_STATUS) {
3823                 if (!netif_carrier_ok(netdev)) {
3824                         tp->rtl_ops.enable(tp);
3825                         netif_stop_queue(netdev);
3826                         napi_disable(napi);
3827                         netif_carrier_on(netdev);
3828                         rtl_start_rx(tp);
3829                         clear_bit(RTL8152_SET_RX_MODE, &tp->flags);
3830                         _rtl8152_set_rx_mode(netdev);
3831                         napi_enable(&tp->napi);
3832                         netif_wake_queue(netdev);
3833                         netif_info(tp, link, netdev, "carrier on\n");
3834                 } else if (netif_queue_stopped(netdev) &&
3835                            skb_queue_len(&tp->tx_queue) < tp->tx_qlen) {
3836                         netif_wake_queue(netdev);
3837                 }
3838         } else {
3839                 if (netif_carrier_ok(netdev)) {
3840                         netif_carrier_off(netdev);
3841                         napi_disable(napi);
3842                         tp->rtl_ops.disable(tp);
3843                         napi_enable(napi);
3844                         netif_info(tp, link, netdev, "carrier off\n");
3845                 }
3846         }
3847 }
3848
3849 static void rtl_work_func_t(struct work_struct *work)
3850 {
3851         struct r8152 *tp = container_of(work, struct r8152, schedule.work);
3852
3853         /* If the device is unplugged or !netif_running(), the workqueue
3854          * doesn't need to wake the device, and could return directly.
3855          */
3856         if (test_bit(RTL8152_UNPLUG, &tp->flags) || !netif_running(tp->netdev))
3857                 return;
3858
3859         if (usb_autopm_get_interface(tp->intf) < 0)
3860                 return;
3861
3862         if (!test_bit(WORK_ENABLE, &tp->flags))
3863                 goto out1;
3864
3865         if (!mutex_trylock(&tp->control)) {
3866                 schedule_delayed_work(&tp->schedule, 0);
3867                 goto out1;
3868         }
3869
3870         if (test_and_clear_bit(RTL8152_LINK_CHG, &tp->flags))
3871                 set_carrier(tp);
3872
3873         if (test_and_clear_bit(RTL8152_SET_RX_MODE, &tp->flags))
3874                 _rtl8152_set_rx_mode(tp->netdev);
3875
3876         /* don't schedule napi before linking */
3877         if (test_and_clear_bit(SCHEDULE_NAPI, &tp->flags) &&
3878             netif_carrier_ok(tp->netdev))
3879                 napi_schedule(&tp->napi);
3880
3881         mutex_unlock(&tp->control);
3882
3883 out1:
3884         usb_autopm_put_interface(tp->intf);
3885 }
3886
3887 static void rtl_hw_phy_work_func_t(struct work_struct *work)
3888 {
3889         struct r8152 *tp = container_of(work, struct r8152, hw_phy_work.work);
3890
3891         if (test_bit(RTL8152_UNPLUG, &tp->flags))
3892                 return;
3893
3894         if (usb_autopm_get_interface(tp->intf) < 0)
3895                 return;
3896
3897         mutex_lock(&tp->control);
3898
3899         tp->rtl_ops.hw_phy_cfg(tp);
3900
3901         rtl8152_set_speed(tp, tp->autoneg, tp->speed, tp->duplex);
3902
3903         mutex_unlock(&tp->control);
3904
3905         usb_autopm_put_interface(tp->intf);
3906 }
3907
3908 #ifdef CONFIG_PM_SLEEP
3909 static int rtl_notifier(struct notifier_block *nb, unsigned long action,
3910                         void *data)
3911 {
3912         struct r8152 *tp = container_of(nb, struct r8152, pm_notifier);
3913
3914         switch (action) {
3915         case PM_HIBERNATION_PREPARE:
3916         case PM_SUSPEND_PREPARE:
3917                 usb_autopm_get_interface(tp->intf);
3918                 break;
3919
3920         case PM_POST_HIBERNATION:
3921         case PM_POST_SUSPEND:
3922                 usb_autopm_put_interface(tp->intf);
3923                 break;
3924
3925         case PM_POST_RESTORE:
3926         case PM_RESTORE_PREPARE:
3927         default:
3928                 break;
3929         }
3930
3931         return NOTIFY_DONE;
3932 }
3933 #endif
3934
3935 static int rtl8152_open(struct net_device *netdev)
3936 {
3937         struct r8152 *tp = netdev_priv(netdev);
3938         int res = 0;
3939
3940         res = alloc_all_mem(tp);
3941         if (res)
3942                 goto out;
3943
3944         res = usb_autopm_get_interface(tp->intf);
3945         if (res < 0)
3946                 goto out_free;
3947
3948         mutex_lock(&tp->control);
3949
3950         tp->rtl_ops.up(tp);
3951
3952         netif_carrier_off(netdev);
3953         netif_start_queue(netdev);
3954         set_bit(WORK_ENABLE, &tp->flags);
3955
3956         res = usb_submit_urb(tp->intr_urb, GFP_KERNEL);
3957         if (res) {
3958                 if (res == -ENODEV)
3959                         netif_device_detach(tp->netdev);
3960                 netif_warn(tp, ifup, netdev, "intr_urb submit failed: %d\n",
3961                            res);
3962                 goto out_unlock;
3963         }
3964         napi_enable(&tp->napi);
3965
3966         mutex_unlock(&tp->control);
3967
3968         usb_autopm_put_interface(tp->intf);
3969 #ifdef CONFIG_PM_SLEEP
3970         tp->pm_notifier.notifier_call = rtl_notifier;
3971         register_pm_notifier(&tp->pm_notifier);
3972 #endif
3973         return 0;
3974
3975 out_unlock:
3976         mutex_unlock(&tp->control);
3977         usb_autopm_put_interface(tp->intf);
3978 out_free:
3979         free_all_mem(tp);
3980 out:
3981         return res;
3982 }
3983
3984 static int rtl8152_close(struct net_device *netdev)
3985 {
3986         struct r8152 *tp = netdev_priv(netdev);
3987         int res = 0;
3988
3989 #ifdef CONFIG_PM_SLEEP
3990         unregister_pm_notifier(&tp->pm_notifier);
3991 #endif
3992         if (!test_bit(RTL8152_UNPLUG, &tp->flags))
3993                 napi_disable(&tp->napi);
3994         clear_bit(WORK_ENABLE, &tp->flags);
3995         usb_kill_urb(tp->intr_urb);
3996         cancel_delayed_work_sync(&tp->schedule);
3997         netif_stop_queue(netdev);
3998
3999         res = usb_autopm_get_interface(tp->intf);
4000         if (res < 0 || test_bit(RTL8152_UNPLUG, &tp->flags)) {
4001                 rtl_drop_queued_tx(tp);
4002                 rtl_stop_rx(tp);
4003         } else {
4004                 mutex_lock(&tp->control);
4005
4006                 tp->rtl_ops.down(tp);
4007
4008                 mutex_unlock(&tp->control);
4009
4010                 usb_autopm_put_interface(tp->intf);
4011         }
4012
4013         free_all_mem(tp);
4014
4015         return res;
4016 }
4017
4018 static void rtl_tally_reset(struct r8152 *tp)
4019 {
4020         u32 ocp_data;
4021
4022         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY);
4023         ocp_data |= TALLY_RESET;
4024         ocp_write_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY, ocp_data);
4025 }
4026
4027 static void r8152b_init(struct r8152 *tp)
4028 {
4029         u32 ocp_data;
4030         u16 data;
4031
4032         if (test_bit(RTL8152_UNPLUG, &tp->flags))
4033                 return;
4034
4035         data = r8152_mdio_read(tp, MII_BMCR);
4036         if (data & BMCR_PDOWN) {
4037                 data &= ~BMCR_PDOWN;
4038                 r8152_mdio_write(tp, MII_BMCR, data);
4039         }
4040
4041         r8152_aldps_en(tp, false);
4042
4043         if (tp->version == RTL_VER_01) {
4044                 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
4045                 ocp_data &= ~LED_MODE_MASK;
4046                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
4047         }
4048
4049         r8152_power_cut_en(tp, false);
4050
4051         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
4052         ocp_data |= TX_10M_IDLE_EN | PFM_PWM_SWITCH;
4053         ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
4054         ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL);
4055         ocp_data &= ~MCU_CLK_RATIO_MASK;
4056         ocp_data |= MCU_CLK_RATIO | D3_CLK_GATED_EN;
4057         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ocp_data);
4058         ocp_data = GPHY_STS_MSK | SPEED_DOWN_MSK |
4059                    SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK;
4060         ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, ocp_data);
4061
4062         rtl_tally_reset(tp);
4063
4064         /* enable rx aggregation */
4065         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
4066         ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
4067         ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
4068 }
4069
4070 static void r8153_init(struct r8152 *tp)
4071 {
4072         u32 ocp_data;
4073         u16 data;
4074         int i;
4075
4076         if (test_bit(RTL8152_UNPLUG, &tp->flags))
4077                 return;
4078
4079         r8153_u1u2en(tp, false);
4080
4081         for (i = 0; i < 500; i++) {
4082                 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
4083                     AUTOLOAD_DONE)
4084                         break;
4085                 msleep(20);
4086         }
4087
4088         data = r8153_phy_status(tp, 0);
4089
4090         if (tp->version == RTL_VER_03 || tp->version == RTL_VER_04 ||
4091             tp->version == RTL_VER_05)
4092                 ocp_reg_write(tp, OCP_ADC_CFG, CKADSEL_L | ADC_EN | EN_EMI_L);
4093
4094         data = r8152_mdio_read(tp, MII_BMCR);
4095         if (data & BMCR_PDOWN) {
4096                 data &= ~BMCR_PDOWN;
4097                 r8152_mdio_write(tp, MII_BMCR, data);
4098         }
4099
4100         data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
4101
4102         r8153_u2p3en(tp, false);
4103
4104         if (tp->version == RTL_VER_04) {
4105                 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2);
4106                 ocp_data &= ~pwd_dn_scale_mask;
4107                 ocp_data |= pwd_dn_scale(96);
4108                 ocp_write_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2, ocp_data);
4109
4110                 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY);
4111                 ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND;
4112                 ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data);
4113         } else if (tp->version == RTL_VER_05) {
4114                 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0);
4115                 ocp_data &= ~ECM_ALDPS;
4116                 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0, ocp_data);
4117
4118                 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1);
4119                 if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0)
4120                         ocp_data &= ~DYNAMIC_BURST;
4121                 else
4122                         ocp_data |= DYNAMIC_BURST;
4123                 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data);
4124         } else if (tp->version == RTL_VER_06) {
4125                 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1);
4126                 if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0)
4127                         ocp_data &= ~DYNAMIC_BURST;
4128                 else
4129                         ocp_data |= DYNAMIC_BURST;
4130                 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data);
4131         }
4132
4133         ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2);
4134         ocp_data |= EP4_FULL_FC;
4135         ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2, ocp_data);
4136
4137         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL);
4138         ocp_data &= ~TIMER11_EN;
4139         ocp_write_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL, ocp_data);
4140
4141         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
4142         ocp_data &= ~LED_MODE_MASK;
4143         ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
4144
4145         ocp_data = FIFO_EMPTY_1FB | ROK_EXIT_LPM;
4146         if (tp->version == RTL_VER_04 && tp->udev->speed < USB_SPEED_SUPER)
4147                 ocp_data |= LPM_TIMER_500MS;
4148         else
4149                 ocp_data |= LPM_TIMER_500US;
4150         ocp_write_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL, ocp_data);
4151
4152         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2);
4153         ocp_data &= ~SEN_VAL_MASK;
4154         ocp_data |= SEN_VAL_NORMAL | SEL_RXIDLE;
4155         ocp_write_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2, ocp_data);
4156
4157         ocp_write_word(tp, MCU_TYPE_USB, USB_CONNECT_TIMER, 0x0001);
4158
4159         r8153_power_cut_en(tp, false);
4160         r8153_u1u2en(tp, true);
4161         r8153_mac_clk_spd(tp, false);
4162         usb_enable_lpm(tp->udev);
4163
4164         /* rx aggregation */
4165         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
4166         ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
4167         if (test_bit(DELL_TB_RX_AGG_BUG, &tp->flags))
4168                 ocp_data |= RX_AGG_DISABLE;
4169
4170         ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
4171
4172         rtl_tally_reset(tp);
4173
4174         switch (tp->udev->speed) {
4175         case USB_SPEED_SUPER:
4176         case USB_SPEED_SUPER_PLUS:
4177                 tp->coalesce = COALESCE_SUPER;
4178                 break;
4179         case USB_SPEED_HIGH:
4180                 tp->coalesce = COALESCE_HIGH;
4181                 break;
4182         default:
4183                 tp->coalesce = COALESCE_SLOW;
4184                 break;
4185         }
4186 }
4187
4188 static void r8153b_init(struct r8152 *tp)
4189 {
4190         u32 ocp_data;
4191         u16 data;
4192         int i;
4193
4194         if (test_bit(RTL8152_UNPLUG, &tp->flags))
4195                 return;
4196
4197         r8153b_u1u2en(tp, false);
4198
4199         for (i = 0; i < 500; i++) {
4200                 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
4201                     AUTOLOAD_DONE)
4202                         break;
4203                 msleep(20);
4204         }
4205
4206         data = r8153_phy_status(tp, 0);
4207
4208         data = r8152_mdio_read(tp, MII_BMCR);
4209         if (data & BMCR_PDOWN) {
4210                 data &= ~BMCR_PDOWN;
4211                 r8152_mdio_write(tp, MII_BMCR, data);
4212         }
4213
4214         data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
4215
4216         r8153_u2p3en(tp, false);
4217
4218         /* MSC timer = 0xfff * 8ms = 32760 ms */
4219         ocp_write_word(tp, MCU_TYPE_USB, USB_MSC_TIMER, 0x0fff);
4220
4221         /* U1/U2/L1 idle timer. 500 us */
4222         ocp_write_word(tp, MCU_TYPE_USB, USB_U1U2_TIMER, 500);
4223
4224         r8153b_power_cut_en(tp, false);
4225         r8153b_ups_en(tp, false);
4226         r8153b_queue_wake(tp, false);
4227         rtl_runtime_suspend_enable(tp, false);
4228         r8153b_u1u2en(tp, true);
4229         usb_enable_lpm(tp->udev);
4230
4231         /* MAC clock speed down */
4232         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2);
4233         ocp_data |= MAC_CLK_SPDWN_EN;
4234         ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, ocp_data);
4235
4236         set_bit(GREEN_ETHERNET, &tp->flags);
4237
4238         /* rx aggregation */
4239         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
4240         ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
4241         ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
4242
4243         rtl_tally_reset(tp);
4244
4245         tp->coalesce = 15000;   /* 15 us */
4246 }
4247
4248 static int rtl8152_pre_reset(struct usb_interface *intf)
4249 {
4250         struct r8152 *tp = usb_get_intfdata(intf);
4251         struct net_device *netdev;
4252
4253         if (!tp)
4254                 return 0;
4255
4256         netdev = tp->netdev;
4257         if (!netif_running(netdev))
4258                 return 0;
4259
4260         netif_stop_queue(netdev);
4261         napi_disable(&tp->napi);
4262         clear_bit(WORK_ENABLE, &tp->flags);
4263         usb_kill_urb(tp->intr_urb);
4264         cancel_delayed_work_sync(&tp->schedule);
4265         if (netif_carrier_ok(netdev)) {
4266                 mutex_lock(&tp->control);
4267                 tp->rtl_ops.disable(tp);
4268                 mutex_unlock(&tp->control);
4269         }
4270
4271         return 0;
4272 }
4273
4274 static int rtl8152_post_reset(struct usb_interface *intf)
4275 {
4276         struct r8152 *tp = usb_get_intfdata(intf);
4277         struct net_device *netdev;
4278         struct sockaddr sa;
4279
4280         if (!tp)
4281                 return 0;
4282
4283         /* reset the MAC adddress in case of policy change */
4284         if (determine_ethernet_addr(tp, &sa) >= 0) {
4285                 rtnl_lock();
4286                 dev_set_mac_address (tp->netdev, &sa, NULL);
4287                 rtnl_unlock();
4288         }
4289
4290         netdev = tp->netdev;
4291         if (!netif_running(netdev))
4292                 return 0;
4293
4294         set_bit(WORK_ENABLE, &tp->flags);
4295         if (netif_carrier_ok(netdev)) {
4296                 mutex_lock(&tp->control);
4297                 tp->rtl_ops.enable(tp);
4298                 rtl_start_rx(tp);
4299                 _rtl8152_set_rx_mode(netdev);
4300                 mutex_unlock(&tp->control);
4301         }
4302
4303         napi_enable(&tp->napi);
4304         netif_wake_queue(netdev);
4305         usb_submit_urb(tp->intr_urb, GFP_KERNEL);
4306
4307         if (!list_empty(&tp->rx_done))
4308                 napi_schedule(&tp->napi);
4309
4310         return 0;
4311 }
4312
4313 static bool delay_autosuspend(struct r8152 *tp)
4314 {
4315         bool sw_linking = !!netif_carrier_ok(tp->netdev);
4316         bool hw_linking = !!(rtl8152_get_speed(tp) & LINK_STATUS);
4317
4318         /* This means a linking change occurs and the driver doesn't detect it,
4319          * yet. If the driver has disabled tx/rx and hw is linking on, the
4320          * device wouldn't wake up by receiving any packet.
4321          */
4322         if (work_busy(&tp->schedule.work) || sw_linking != hw_linking)
4323                 return true;
4324
4325         /* If the linking down is occurred by nway, the device may miss the
4326          * linking change event. And it wouldn't wake when linking on.
4327          */
4328         if (!sw_linking && tp->rtl_ops.in_nway(tp))
4329                 return true;
4330         else if (!skb_queue_empty(&tp->tx_queue))
4331                 return true;
4332         else
4333                 return false;
4334 }
4335
4336 static int rtl8152_runtime_resume(struct r8152 *tp)
4337 {
4338         struct net_device *netdev = tp->netdev;
4339
4340         if (netif_running(netdev) && netdev->flags & IFF_UP) {
4341                 struct napi_struct *napi = &tp->napi;
4342
4343                 tp->rtl_ops.autosuspend_en(tp, false);
4344                 napi_disable(napi);
4345                 set_bit(WORK_ENABLE, &tp->flags);
4346
4347                 if (netif_carrier_ok(netdev)) {
4348                         if (rtl8152_get_speed(tp) & LINK_STATUS) {
4349                                 rtl_start_rx(tp);
4350                         } else {
4351                                 netif_carrier_off(netdev);
4352                                 tp->rtl_ops.disable(tp);
4353                                 netif_info(tp, link, netdev, "linking down\n");
4354                         }
4355                 }
4356
4357                 napi_enable(napi);
4358                 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
4359                 smp_mb__after_atomic();
4360
4361                 if (!list_empty(&tp->rx_done))
4362                         napi_schedule(&tp->napi);
4363
4364                 usb_submit_urb(tp->intr_urb, GFP_NOIO);
4365         } else {
4366                 if (netdev->flags & IFF_UP)
4367                         tp->rtl_ops.autosuspend_en(tp, false);
4368
4369                 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
4370         }
4371
4372         return 0;
4373 }
4374
4375 static int rtl8152_system_resume(struct r8152 *tp)
4376 {
4377         struct net_device *netdev = tp->netdev;
4378
4379         netif_device_attach(netdev);
4380
4381         if (netif_running(netdev) && netdev->flags & IFF_UP) {
4382                 tp->rtl_ops.up(tp);
4383                 netif_carrier_off(netdev);
4384                 set_bit(WORK_ENABLE, &tp->flags);
4385                 usb_submit_urb(tp->intr_urb, GFP_NOIO);
4386         }
4387
4388         return 0;
4389 }
4390
4391 static int rtl8152_runtime_suspend(struct r8152 *tp)
4392 {
4393         struct net_device *netdev = tp->netdev;
4394         int ret = 0;
4395
4396         set_bit(SELECTIVE_SUSPEND, &tp->flags);
4397         smp_mb__after_atomic();
4398
4399         if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) {
4400                 u32 rcr = 0;
4401
4402                 if (netif_carrier_ok(netdev)) {
4403                         u32 ocp_data;
4404
4405                         rcr = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
4406                         ocp_data = rcr & ~RCR_ACPT_ALL;
4407                         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
4408                         rxdy_gated_en(tp, true);
4409                         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA,
4410                                                  PLA_OOB_CTRL);
4411                         if (!(ocp_data & RXFIFO_EMPTY)) {
4412                                 rxdy_gated_en(tp, false);
4413                                 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, rcr);
4414                                 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
4415                                 smp_mb__after_atomic();
4416                                 ret = -EBUSY;
4417                                 goto out1;
4418                         }
4419                 }
4420
4421                 clear_bit(WORK_ENABLE, &tp->flags);
4422                 usb_kill_urb(tp->intr_urb);
4423
4424                 tp->rtl_ops.autosuspend_en(tp, true);
4425
4426                 if (netif_carrier_ok(netdev)) {
4427                         struct napi_struct *napi = &tp->napi;
4428
4429                         napi_disable(napi);
4430                         rtl_stop_rx(tp);
4431                         rxdy_gated_en(tp, false);
4432                         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, rcr);
4433                         napi_enable(napi);
4434                 }
4435
4436                 if (delay_autosuspend(tp)) {
4437                         rtl8152_runtime_resume(tp);
4438                         ret = -EBUSY;
4439                 }
4440         }
4441
4442 out1:
4443         return ret;
4444 }
4445
4446 static int rtl8152_system_suspend(struct r8152 *tp)
4447 {
4448         struct net_device *netdev = tp->netdev;
4449
4450         netif_device_detach(netdev);
4451
4452         if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) {
4453                 struct napi_struct *napi = &tp->napi;
4454
4455                 clear_bit(WORK_ENABLE, &tp->flags);
4456                 usb_kill_urb(tp->intr_urb);
4457                 napi_disable(napi);
4458                 cancel_delayed_work_sync(&tp->schedule);
4459                 tp->rtl_ops.down(tp);
4460                 napi_enable(napi);
4461         }
4462
4463         return 0;
4464 }
4465
4466 static int rtl8152_suspend(struct usb_interface *intf, pm_message_t message)
4467 {
4468         struct r8152 *tp = usb_get_intfdata(intf);
4469         int ret;
4470
4471         mutex_lock(&tp->control);
4472
4473         if (PMSG_IS_AUTO(message))
4474                 ret = rtl8152_runtime_suspend(tp);
4475         else
4476                 ret = rtl8152_system_suspend(tp);
4477
4478         mutex_unlock(&tp->control);
4479
4480         return ret;
4481 }
4482
4483 static int rtl8152_resume(struct usb_interface *intf)
4484 {
4485         struct r8152 *tp = usb_get_intfdata(intf);
4486         int ret;
4487
4488         mutex_lock(&tp->control);
4489
4490         if (test_bit(SELECTIVE_SUSPEND, &tp->flags))
4491                 ret = rtl8152_runtime_resume(tp);
4492         else
4493                 ret = rtl8152_system_resume(tp);
4494
4495         mutex_unlock(&tp->control);
4496
4497         return ret;
4498 }
4499
4500 static int rtl8152_reset_resume(struct usb_interface *intf)
4501 {
4502         struct r8152 *tp = usb_get_intfdata(intf);
4503
4504         clear_bit(SELECTIVE_SUSPEND, &tp->flags);
4505         mutex_lock(&tp->control);
4506         tp->rtl_ops.init(tp);
4507         queue_delayed_work(system_long_wq, &tp->hw_phy_work, 0);
4508         mutex_unlock(&tp->control);
4509         return rtl8152_resume(intf);
4510 }
4511
4512 static void rtl8152_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
4513 {
4514         struct r8152 *tp = netdev_priv(dev);
4515
4516         if (usb_autopm_get_interface(tp->intf) < 0)
4517                 return;
4518
4519         if (!rtl_can_wakeup(tp)) {
4520                 wol->supported = 0;
4521                 wol->wolopts = 0;
4522         } else {
4523                 mutex_lock(&tp->control);
4524                 wol->supported = WAKE_ANY;
4525                 wol->wolopts = __rtl_get_wol(tp);
4526                 mutex_unlock(&tp->control);
4527         }
4528
4529         usb_autopm_put_interface(tp->intf);
4530 }
4531
4532 static int rtl8152_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
4533 {
4534         struct r8152 *tp = netdev_priv(dev);
4535         int ret;
4536
4537         if (!rtl_can_wakeup(tp))
4538                 return -EOPNOTSUPP;
4539
4540         if (wol->wolopts & ~WAKE_ANY)
4541                 return -EINVAL;
4542
4543         ret = usb_autopm_get_interface(tp->intf);
4544         if (ret < 0)
4545                 goto out_set_wol;
4546
4547         mutex_lock(&tp->control);
4548
4549         __rtl_set_wol(tp, wol->wolopts);
4550         tp->saved_wolopts = wol->wolopts & WAKE_ANY;
4551
4552         mutex_unlock(&tp->control);
4553
4554         usb_autopm_put_interface(tp->intf);
4555
4556 out_set_wol:
4557         return ret;
4558 }
4559
4560 static u32 rtl8152_get_msglevel(struct net_device *dev)
4561 {
4562         struct r8152 *tp = netdev_priv(dev);
4563
4564         return tp->msg_enable;
4565 }
4566
4567 static void rtl8152_set_msglevel(struct net_device *dev, u32 value)
4568 {
4569         struct r8152 *tp = netdev_priv(dev);
4570
4571         tp->msg_enable = value;
4572 }
4573
4574 static void rtl8152_get_drvinfo(struct net_device *netdev,
4575                                 struct ethtool_drvinfo *info)
4576 {
4577         struct r8152 *tp = netdev_priv(netdev);
4578
4579         strlcpy(info->driver, MODULENAME, sizeof(info->driver));
4580         strlcpy(info->version, DRIVER_VERSION, sizeof(info->version));
4581         usb_make_path(tp->udev, info->bus_info, sizeof(info->bus_info));
4582 }
4583
4584 static
4585 int rtl8152_get_link_ksettings(struct net_device *netdev,
4586                                struct ethtool_link_ksettings *cmd)
4587 {
4588         struct r8152 *tp = netdev_priv(netdev);
4589         int ret;
4590
4591         if (!tp->mii.mdio_read)
4592                 return -EOPNOTSUPP;
4593
4594         ret = usb_autopm_get_interface(tp->intf);
4595         if (ret < 0)
4596                 goto out;
4597
4598         mutex_lock(&tp->control);
4599
4600         mii_ethtool_get_link_ksettings(&tp->mii, cmd);
4601
4602         mutex_unlock(&tp->control);
4603
4604         usb_autopm_put_interface(tp->intf);
4605
4606 out:
4607         return ret;
4608 }
4609
4610 static int rtl8152_set_link_ksettings(struct net_device *dev,
4611                                       const struct ethtool_link_ksettings *cmd)
4612 {
4613         struct r8152 *tp = netdev_priv(dev);
4614         int ret;
4615
4616         ret = usb_autopm_get_interface(tp->intf);
4617         if (ret < 0)
4618                 goto out;
4619
4620         mutex_lock(&tp->control);
4621
4622         ret = rtl8152_set_speed(tp, cmd->base.autoneg, cmd->base.speed,
4623                                 cmd->base.duplex);
4624         if (!ret) {
4625                 tp->autoneg = cmd->base.autoneg;
4626                 tp->speed = cmd->base.speed;
4627                 tp->duplex = cmd->base.duplex;
4628         }
4629
4630         mutex_unlock(&tp->control);
4631
4632         usb_autopm_put_interface(tp->intf);
4633
4634 out:
4635         return ret;
4636 }
4637
4638 static const char rtl8152_gstrings[][ETH_GSTRING_LEN] = {
4639         "tx_packets",
4640         "rx_packets",
4641         "tx_errors",
4642         "rx_errors",
4643         "rx_missed",
4644         "align_errors",
4645         "tx_single_collisions",
4646         "tx_multi_collisions",
4647         "rx_unicast",
4648         "rx_broadcast",
4649         "rx_multicast",
4650         "tx_aborted",
4651         "tx_underrun",
4652 };
4653
4654 static int rtl8152_get_sset_count(struct net_device *dev, int sset)
4655 {
4656         switch (sset) {
4657         case ETH_SS_STATS:
4658                 return ARRAY_SIZE(rtl8152_gstrings);
4659         default:
4660                 return -EOPNOTSUPP;
4661         }
4662 }
4663
4664 static void rtl8152_get_ethtool_stats(struct net_device *dev,
4665                                       struct ethtool_stats *stats, u64 *data)
4666 {
4667         struct r8152 *tp = netdev_priv(dev);
4668         struct tally_counter tally;
4669
4670         if (usb_autopm_get_interface(tp->intf) < 0)
4671                 return;
4672
4673         generic_ocp_read(tp, PLA_TALLYCNT, sizeof(tally), &tally, MCU_TYPE_PLA);
4674
4675         usb_autopm_put_interface(tp->intf);
4676
4677         data[0] = le64_to_cpu(tally.tx_packets);
4678         data[1] = le64_to_cpu(tally.rx_packets);
4679         data[2] = le64_to_cpu(tally.tx_errors);
4680         data[3] = le32_to_cpu(tally.rx_errors);
4681         data[4] = le16_to_cpu(tally.rx_missed);
4682         data[5] = le16_to_cpu(tally.align_errors);
4683         data[6] = le32_to_cpu(tally.tx_one_collision);
4684         data[7] = le32_to_cpu(tally.tx_multi_collision);
4685         data[8] = le64_to_cpu(tally.rx_unicast);
4686         data[9] = le64_to_cpu(tally.rx_broadcast);
4687         data[10] = le32_to_cpu(tally.rx_multicast);
4688         data[11] = le16_to_cpu(tally.tx_aborted);
4689         data[12] = le16_to_cpu(tally.tx_underrun);
4690 }
4691
4692 static void rtl8152_get_strings(struct net_device *dev, u32 stringset, u8 *data)
4693 {
4694         switch (stringset) {
4695         case ETH_SS_STATS:
4696                 memcpy(data, *rtl8152_gstrings, sizeof(rtl8152_gstrings));
4697                 break;
4698         }
4699 }
4700
4701 static int r8152_get_eee(struct r8152 *tp, struct ethtool_eee *eee)
4702 {
4703         u32 ocp_data, lp, adv, supported = 0;
4704         u16 val;
4705
4706         val = r8152_mmd_read(tp, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE);
4707         supported = mmd_eee_cap_to_ethtool_sup_t(val);
4708
4709         val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV);
4710         adv = mmd_eee_adv_to_ethtool_adv_t(val);
4711
4712         val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE);
4713         lp = mmd_eee_adv_to_ethtool_adv_t(val);
4714
4715         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
4716         ocp_data &= EEE_RX_EN | EEE_TX_EN;
4717
4718         eee->eee_enabled = !!ocp_data;
4719         eee->eee_active = !!(supported & adv & lp);
4720         eee->supported = supported;
4721         eee->advertised = adv;
4722         eee->lp_advertised = lp;
4723
4724         return 0;
4725 }
4726
4727 static int r8152_set_eee(struct r8152 *tp, struct ethtool_eee *eee)
4728 {
4729         u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised);
4730
4731         r8152_eee_en(tp, eee->eee_enabled);
4732
4733         if (!eee->eee_enabled)
4734                 val = 0;
4735
4736         r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);
4737
4738         return 0;
4739 }
4740
4741 static int r8153_get_eee(struct r8152 *tp, struct ethtool_eee *eee)
4742 {
4743         u32 ocp_data, lp, adv, supported = 0;
4744         u16 val;
4745
4746         val = ocp_reg_read(tp, OCP_EEE_ABLE);
4747         supported = mmd_eee_cap_to_ethtool_sup_t(val);
4748
4749         val = ocp_reg_read(tp, OCP_EEE_ADV);
4750         adv = mmd_eee_adv_to_ethtool_adv_t(val);
4751
4752         val = ocp_reg_read(tp, OCP_EEE_LPABLE);
4753         lp = mmd_eee_adv_to_ethtool_adv_t(val);
4754
4755         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
4756         ocp_data &= EEE_RX_EN | EEE_TX_EN;
4757
4758         eee->eee_enabled = !!ocp_data;
4759         eee->eee_active = !!(supported & adv & lp);
4760         eee->supported = supported;
4761         eee->advertised = adv;
4762         eee->lp_advertised = lp;
4763
4764         return 0;
4765 }
4766
4767 static int r8153_set_eee(struct r8152 *tp, struct ethtool_eee *eee)
4768 {
4769         u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised);
4770
4771         r8153_eee_en(tp, eee->eee_enabled);
4772
4773         if (!eee->eee_enabled)
4774                 val = 0;
4775
4776         ocp_reg_write(tp, OCP_EEE_ADV, val);
4777
4778         return 0;
4779 }
4780
4781 static int r8153b_set_eee(struct r8152 *tp, struct ethtool_eee *eee)
4782 {
4783         u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised);
4784
4785         r8153b_eee_en(tp, eee->eee_enabled);
4786
4787         if (!eee->eee_enabled)
4788                 val = 0;
4789
4790         ocp_reg_write(tp, OCP_EEE_ADV, val);
4791
4792         return 0;
4793 }
4794
4795 static int
4796 rtl_ethtool_get_eee(struct net_device *net, struct ethtool_eee *edata)
4797 {
4798         struct r8152 *tp = netdev_priv(net);
4799         int ret;
4800
4801         ret = usb_autopm_get_interface(tp->intf);
4802         if (ret < 0)
4803                 goto out;
4804
4805         mutex_lock(&tp->control);
4806
4807         ret = tp->rtl_ops.eee_get(tp, edata);
4808
4809         mutex_unlock(&tp->control);
4810
4811         usb_autopm_put_interface(tp->intf);
4812
4813 out:
4814         return ret;
4815 }
4816
4817 static int
4818 rtl_ethtool_set_eee(struct net_device *net, struct ethtool_eee *edata)
4819 {
4820         struct r8152 *tp = netdev_priv(net);
4821         int ret;
4822
4823         ret = usb_autopm_get_interface(tp->intf);
4824         if (ret < 0)
4825                 goto out;
4826
4827         mutex_lock(&tp->control);
4828
4829         ret = tp->rtl_ops.eee_set(tp, edata);
4830         if (!ret)
4831                 ret = mii_nway_restart(&tp->mii);
4832
4833         mutex_unlock(&tp->control);
4834
4835         usb_autopm_put_interface(tp->intf);
4836
4837 out:
4838         return ret;
4839 }
4840
4841 static int rtl8152_nway_reset(struct net_device *dev)
4842 {
4843         struct r8152 *tp = netdev_priv(dev);
4844         int ret;
4845
4846         ret = usb_autopm_get_interface(tp->intf);
4847         if (ret < 0)
4848                 goto out;
4849
4850         mutex_lock(&tp->control);
4851
4852         ret = mii_nway_restart(&tp->mii);
4853
4854         mutex_unlock(&tp->control);
4855
4856         usb_autopm_put_interface(tp->intf);
4857
4858 out:
4859         return ret;
4860 }
4861
4862 static int rtl8152_get_coalesce(struct net_device *netdev,
4863                                 struct ethtool_coalesce *coalesce)
4864 {
4865         struct r8152 *tp = netdev_priv(netdev);
4866
4867         switch (tp->version) {
4868         case RTL_VER_01:
4869         case RTL_VER_02:
4870         case RTL_VER_07:
4871                 return -EOPNOTSUPP;
4872         default:
4873                 break;
4874         }
4875
4876         coalesce->rx_coalesce_usecs = tp->coalesce;
4877
4878         return 0;
4879 }
4880
4881 static int rtl8152_set_coalesce(struct net_device *netdev,
4882                                 struct ethtool_coalesce *coalesce)
4883 {
4884         struct r8152 *tp = netdev_priv(netdev);
4885         int ret;
4886
4887         switch (tp->version) {
4888         case RTL_VER_01:
4889         case RTL_VER_02:
4890         case RTL_VER_07:
4891                 return -EOPNOTSUPP;
4892         default:
4893                 break;
4894         }
4895
4896         if (coalesce->rx_coalesce_usecs > COALESCE_SLOW)
4897                 return -EINVAL;
4898
4899         ret = usb_autopm_get_interface(tp->intf);
4900         if (ret < 0)
4901                 return ret;
4902
4903         mutex_lock(&tp->control);
4904
4905         if (tp->coalesce != coalesce->rx_coalesce_usecs) {
4906                 tp->coalesce = coalesce->rx_coalesce_usecs;
4907
4908                 if (netif_running(tp->netdev) && netif_carrier_ok(netdev))
4909                         r8153_set_rx_early_timeout(tp);
4910         }
4911
4912         mutex_unlock(&tp->control);
4913
4914         usb_autopm_put_interface(tp->intf);
4915
4916         return ret;
4917 }
4918
4919 static const struct ethtool_ops ops = {
4920         .get_drvinfo = rtl8152_get_drvinfo,
4921         .get_link = ethtool_op_get_link,
4922         .nway_reset = rtl8152_nway_reset,
4923         .get_msglevel = rtl8152_get_msglevel,
4924         .set_msglevel = rtl8152_set_msglevel,
4925         .get_wol = rtl8152_get_wol,
4926         .set_wol = rtl8152_set_wol,
4927         .get_strings = rtl8152_get_strings,
4928         .get_sset_count = rtl8152_get_sset_count,
4929         .get_ethtool_stats = rtl8152_get_ethtool_stats,
4930         .get_coalesce = rtl8152_get_coalesce,
4931         .set_coalesce = rtl8152_set_coalesce,
4932         .get_eee = rtl_ethtool_get_eee,
4933         .set_eee = rtl_ethtool_set_eee,
4934         .get_link_ksettings = rtl8152_get_link_ksettings,
4935         .set_link_ksettings = rtl8152_set_link_ksettings,
4936 };
4937
4938 static int rtl8152_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
4939 {
4940         struct r8152 *tp = netdev_priv(netdev);
4941         struct mii_ioctl_data *data = if_mii(rq);
4942         int res;
4943
4944         if (test_bit(RTL8152_UNPLUG, &tp->flags))
4945                 return -ENODEV;
4946
4947         res = usb_autopm_get_interface(tp->intf);
4948         if (res < 0)
4949                 goto out;
4950
4951         switch (cmd) {
4952         case SIOCGMIIPHY:
4953                 data->phy_id = R8152_PHY_ID; /* Internal PHY */
4954                 break;
4955
4956         case SIOCGMIIREG:
4957                 mutex_lock(&tp->control);
4958                 data->val_out = r8152_mdio_read(tp, data->reg_num);
4959                 mutex_unlock(&tp->control);
4960                 break;
4961
4962         case SIOCSMIIREG:
4963                 if (!capable(CAP_NET_ADMIN)) {
4964                         res = -EPERM;
4965                         break;
4966                 }
4967                 mutex_lock(&tp->control);
4968                 r8152_mdio_write(tp, data->reg_num, data->val_in);
4969                 mutex_unlock(&tp->control);
4970                 break;
4971
4972         default:
4973                 res = -EOPNOTSUPP;
4974         }
4975
4976         usb_autopm_put_interface(tp->intf);
4977
4978 out:
4979         return res;
4980 }
4981
4982 static int rtl8152_change_mtu(struct net_device *dev, int new_mtu)
4983 {
4984         struct r8152 *tp = netdev_priv(dev);
4985         int ret;
4986
4987         switch (tp->version) {
4988         case RTL_VER_01:
4989         case RTL_VER_02:
4990         case RTL_VER_07:
4991                 dev->mtu = new_mtu;
4992                 return 0;
4993         default:
4994                 break;
4995         }
4996
4997         ret = usb_autopm_get_interface(tp->intf);
4998         if (ret < 0)
4999                 return ret;
5000
5001         mutex_lock(&tp->control);
5002
5003         dev->mtu = new_mtu;
5004
5005         if (netif_running(dev)) {
5006                 u32 rms = new_mtu + VLAN_ETH_HLEN + ETH_FCS_LEN;
5007
5008                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, rms);
5009
5010                 if (netif_carrier_ok(dev))
5011                         r8153_set_rx_early_size(tp);
5012         }
5013
5014         mutex_unlock(&tp->control);
5015
5016         usb_autopm_put_interface(tp->intf);
5017
5018         return ret;
5019 }
5020
5021 static const struct net_device_ops rtl8152_netdev_ops = {
5022         .ndo_open               = rtl8152_open,
5023         .ndo_stop               = rtl8152_close,
5024         .ndo_do_ioctl           = rtl8152_ioctl,
5025         .ndo_start_xmit         = rtl8152_start_xmit,
5026         .ndo_tx_timeout         = rtl8152_tx_timeout,
5027         .ndo_set_features       = rtl8152_set_features,
5028         .ndo_set_rx_mode        = rtl8152_set_rx_mode,
5029         .ndo_set_mac_address    = rtl8152_set_mac_address,
5030         .ndo_change_mtu         = rtl8152_change_mtu,
5031         .ndo_validate_addr      = eth_validate_addr,
5032         .ndo_features_check     = rtl8152_features_check,
5033 };
5034
5035 static void rtl8152_unload(struct r8152 *tp)
5036 {
5037         if (test_bit(RTL8152_UNPLUG, &tp->flags))
5038                 return;
5039
5040         if (tp->version != RTL_VER_01)
5041                 r8152_power_cut_en(tp, true);
5042 }
5043
5044 static void rtl8153_unload(struct r8152 *tp)
5045 {
5046         if (test_bit(RTL8152_UNPLUG, &tp->flags))
5047                 return;
5048
5049         r8153_power_cut_en(tp, false);
5050 }
5051
5052 static void rtl8153b_unload(struct r8152 *tp)
5053 {
5054         if (test_bit(RTL8152_UNPLUG, &tp->flags))
5055                 return;
5056
5057         r8153b_power_cut_en(tp, false);
5058 }
5059
5060 static int rtl_ops_init(struct r8152 *tp)
5061 {
5062         struct rtl_ops *ops = &tp->rtl_ops;
5063         int ret = 0;
5064
5065         switch (tp->version) {
5066         case RTL_VER_01:
5067         case RTL_VER_02:
5068         case RTL_VER_07:
5069                 ops->init               = r8152b_init;
5070                 ops->enable             = rtl8152_enable;
5071                 ops->disable            = rtl8152_disable;
5072                 ops->up                 = rtl8152_up;
5073                 ops->down               = rtl8152_down;
5074                 ops->unload             = rtl8152_unload;
5075                 ops->eee_get            = r8152_get_eee;
5076                 ops->eee_set            = r8152_set_eee;
5077                 ops->in_nway            = rtl8152_in_nway;
5078                 ops->hw_phy_cfg         = r8152b_hw_phy_cfg;
5079                 ops->autosuspend_en     = rtl_runtime_suspend_enable;
5080                 break;
5081
5082         case RTL_VER_03:
5083         case RTL_VER_04:
5084         case RTL_VER_05:
5085         case RTL_VER_06:
5086                 ops->init               = r8153_init;
5087                 ops->enable             = rtl8153_enable;
5088                 ops->disable            = rtl8153_disable;
5089                 ops->up                 = rtl8153_up;
5090                 ops->down               = rtl8153_down;
5091                 ops->unload             = rtl8153_unload;
5092                 ops->eee_get            = r8153_get_eee;
5093                 ops->eee_set            = r8153_set_eee;
5094                 ops->in_nway            = rtl8153_in_nway;
5095                 ops->hw_phy_cfg         = r8153_hw_phy_cfg;
5096                 ops->autosuspend_en     = rtl8153_runtime_enable;
5097                 break;
5098
5099         case RTL_VER_08:
5100         case RTL_VER_09:
5101                 ops->init               = r8153b_init;
5102                 ops->enable             = rtl8153_enable;
5103                 ops->disable            = rtl8153b_disable;
5104                 ops->up                 = rtl8153b_up;
5105                 ops->down               = rtl8153b_down;
5106                 ops->unload             = rtl8153b_unload;
5107                 ops->eee_get            = r8153_get_eee;
5108                 ops->eee_set            = r8153b_set_eee;
5109                 ops->in_nway            = rtl8153_in_nway;
5110                 ops->hw_phy_cfg         = r8153b_hw_phy_cfg;
5111                 ops->autosuspend_en     = rtl8153b_runtime_enable;
5112                 break;
5113
5114         default:
5115                 ret = -ENODEV;
5116                 netif_err(tp, probe, tp->netdev, "Unknown Device\n");
5117                 break;
5118         }
5119
5120         return ret;
5121 }
5122
5123 static u8 rtl_get_version(struct usb_interface *intf)
5124 {
5125         struct usb_device *udev = interface_to_usbdev(intf);
5126         u32 ocp_data = 0;
5127         __le32 *tmp;
5128         u8 version;
5129         int ret;
5130
5131         tmp = kmalloc(sizeof(*tmp), GFP_KERNEL);
5132         if (!tmp)
5133                 return 0;
5134
5135         ret = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
5136                               RTL8152_REQ_GET_REGS, RTL8152_REQT_READ,
5137                               PLA_TCR0, MCU_TYPE_PLA, tmp, sizeof(*tmp), 500);
5138         if (ret > 0)
5139                 ocp_data = (__le32_to_cpu(*tmp) >> 16) & VERSION_MASK;
5140
5141         kfree(tmp);
5142
5143         switch (ocp_data) {
5144         case 0x4c00:
5145                 version = RTL_VER_01;
5146                 break;
5147         case 0x4c10:
5148                 version = RTL_VER_02;
5149                 break;
5150         case 0x5c00:
5151                 version = RTL_VER_03;
5152                 break;
5153         case 0x5c10:
5154                 version = RTL_VER_04;
5155                 break;
5156         case 0x5c20:
5157                 version = RTL_VER_05;
5158                 break;
5159         case 0x5c30:
5160                 version = RTL_VER_06;
5161                 break;
5162         case 0x4800:
5163                 version = RTL_VER_07;
5164                 break;
5165         case 0x6000:
5166                 version = RTL_VER_08;
5167                 break;
5168         case 0x6010:
5169                 version = RTL_VER_09;
5170                 break;
5171         default:
5172                 version = RTL_VER_UNKNOWN;
5173                 dev_info(&intf->dev, "Unknown version 0x%04x\n", ocp_data);
5174                 break;
5175         }
5176
5177         dev_dbg(&intf->dev, "Detected version 0x%04x\n", version);
5178
5179         return version;
5180 }
5181
5182 static int rtl8152_probe(struct usb_interface *intf,
5183                          const struct usb_device_id *id)
5184 {
5185         struct usb_device *udev = interface_to_usbdev(intf);
5186         u8 version = rtl_get_version(intf);
5187         struct r8152 *tp;
5188         struct net_device *netdev;
5189         int ret;
5190
5191         if (version == RTL_VER_UNKNOWN)
5192                 return -ENODEV;
5193
5194         if (udev->actconfig->desc.bConfigurationValue != 1) {
5195                 usb_driver_set_configuration(udev, 1);
5196                 return -ENODEV;
5197         }
5198
5199         usb_reset_device(udev);
5200         netdev = alloc_etherdev(sizeof(struct r8152));
5201         if (!netdev) {
5202                 dev_err(&intf->dev, "Out of memory\n");
5203                 return -ENOMEM;
5204         }
5205
5206         SET_NETDEV_DEV(netdev, &intf->dev);
5207         tp = netdev_priv(netdev);
5208         tp->msg_enable = 0x7FFF;
5209
5210         tp->udev = udev;
5211         tp->netdev = netdev;
5212         tp->intf = intf;
5213         tp->version = version;
5214
5215         switch (version) {
5216         case RTL_VER_01:
5217         case RTL_VER_02:
5218         case RTL_VER_07:
5219                 tp->mii.supports_gmii = 0;
5220                 break;
5221         default:
5222                 tp->mii.supports_gmii = 1;
5223                 break;
5224         }
5225
5226         ret = rtl_ops_init(tp);
5227         if (ret)
5228                 goto out;
5229
5230         mutex_init(&tp->control);
5231         INIT_DELAYED_WORK(&tp->schedule, rtl_work_func_t);
5232         INIT_DELAYED_WORK(&tp->hw_phy_work, rtl_hw_phy_work_func_t);
5233
5234         netdev->netdev_ops = &rtl8152_netdev_ops;
5235         netdev->watchdog_timeo = RTL8152_TX_TIMEOUT;
5236
5237         netdev->features |= NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
5238                             NETIF_F_TSO | NETIF_F_FRAGLIST | NETIF_F_IPV6_CSUM |
5239                             NETIF_F_TSO6 | NETIF_F_HW_VLAN_CTAG_RX |
5240                             NETIF_F_HW_VLAN_CTAG_TX;
5241         netdev->hw_features = NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
5242                               NETIF_F_TSO | NETIF_F_FRAGLIST |
5243                               NETIF_F_IPV6_CSUM | NETIF_F_TSO6 |
5244                               NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX;
5245         netdev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
5246                                 NETIF_F_HIGHDMA | NETIF_F_FRAGLIST |
5247                                 NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
5248
5249         if (tp->version == RTL_VER_01) {
5250                 netdev->features &= ~NETIF_F_RXCSUM;
5251                 netdev->hw_features &= ~NETIF_F_RXCSUM;
5252         }
5253
5254         if (le16_to_cpu(udev->descriptor.bcdDevice) == 0x3011 && udev->serial &&
5255             (!strcmp(udev->serial, "000001000000") || !strcmp(udev->serial, "000002000000"))) {
5256                 dev_info(&udev->dev, "Dell TB16 Dock, disable RX aggregation");
5257                 set_bit(DELL_TB_RX_AGG_BUG, &tp->flags);
5258         }
5259
5260         netdev->ethtool_ops = &ops;
5261         netif_set_gso_max_size(netdev, RTL_LIMITED_TSO_SIZE);
5262
5263         /* MTU range: 68 - 1500 or 9194 */
5264         netdev->min_mtu = ETH_MIN_MTU;
5265         switch (tp->version) {
5266         case RTL_VER_01:
5267         case RTL_VER_02:
5268                 netdev->max_mtu = ETH_DATA_LEN;
5269                 break;
5270         default:
5271                 netdev->max_mtu = RTL8153_MAX_MTU;
5272                 break;
5273         }
5274
5275         tp->mii.dev = netdev;
5276         tp->mii.mdio_read = read_mii_word;
5277         tp->mii.mdio_write = write_mii_word;
5278         tp->mii.phy_id_mask = 0x3f;
5279         tp->mii.reg_num_mask = 0x1f;
5280         tp->mii.phy_id = R8152_PHY_ID;
5281
5282         tp->autoneg = AUTONEG_ENABLE;
5283         tp->speed = tp->mii.supports_gmii ? SPEED_1000 : SPEED_100;
5284         tp->duplex = DUPLEX_FULL;
5285
5286         intf->needs_remote_wakeup = 1;
5287
5288         tp->rtl_ops.init(tp);
5289         queue_delayed_work(system_long_wq, &tp->hw_phy_work, 0);
5290         set_ethernet_addr(tp);
5291
5292         usb_set_intfdata(intf, tp);
5293         netif_napi_add(netdev, &tp->napi, r8152_poll, RTL8152_NAPI_WEIGHT);
5294
5295         ret = register_netdev(netdev);
5296         if (ret != 0) {
5297                 netif_err(tp, probe, netdev, "couldn't register the device\n");
5298                 goto out1;
5299         }
5300
5301         if (!rtl_can_wakeup(tp))
5302                 __rtl_set_wol(tp, 0);
5303
5304         tp->saved_wolopts = __rtl_get_wol(tp);
5305         if (tp->saved_wolopts)
5306                 device_set_wakeup_enable(&udev->dev, true);
5307         else
5308                 device_set_wakeup_enable(&udev->dev, false);
5309
5310         netif_info(tp, probe, netdev, "%s\n", DRIVER_VERSION);
5311
5312         return 0;
5313
5314 out1:
5315         netif_napi_del(&tp->napi);
5316         usb_set_intfdata(intf, NULL);
5317 out:
5318         free_netdev(netdev);
5319         return ret;
5320 }
5321
5322 static void rtl8152_disconnect(struct usb_interface *intf)
5323 {
5324         struct r8152 *tp = usb_get_intfdata(intf);
5325
5326         usb_set_intfdata(intf, NULL);
5327         if (tp) {
5328                 struct usb_device *udev = tp->udev;
5329
5330                 if (udev->state == USB_STATE_NOTATTACHED)
5331                         set_bit(RTL8152_UNPLUG, &tp->flags);
5332
5333                 netif_napi_del(&tp->napi);
5334                 unregister_netdev(tp->netdev);
5335                 cancel_delayed_work_sync(&tp->hw_phy_work);
5336                 tp->rtl_ops.unload(tp);
5337                 free_netdev(tp->netdev);
5338         }
5339 }
5340
5341 #define REALTEK_USB_DEVICE(vend, prod)  \
5342         .match_flags = USB_DEVICE_ID_MATCH_DEVICE | \
5343                        USB_DEVICE_ID_MATCH_INT_CLASS, \
5344         .idVendor = (vend), \
5345         .idProduct = (prod), \
5346         .bInterfaceClass = USB_CLASS_VENDOR_SPEC \
5347 }, \
5348 { \
5349         .match_flags = USB_DEVICE_ID_MATCH_INT_INFO | \
5350                        USB_DEVICE_ID_MATCH_DEVICE, \
5351         .idVendor = (vend), \
5352         .idProduct = (prod), \
5353         .bInterfaceClass = USB_CLASS_COMM, \
5354         .bInterfaceSubClass = USB_CDC_SUBCLASS_ETHERNET, \
5355         .bInterfaceProtocol = USB_CDC_PROTO_NONE
5356
5357 /* table of devices that work with this driver */
5358 static const struct usb_device_id rtl8152_table[] = {
5359         {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8050)},
5360         {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8152)},
5361         {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8153)},
5362         {REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT, 0x07ab)},
5363         {REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT, 0x07c6)},
5364         {REALTEK_USB_DEVICE(VENDOR_ID_SAMSUNG, 0xa101)},
5365         {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO,  0x304f)},
5366         {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO,  0x3062)},
5367         {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO,  0x3069)},
5368         {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO,  0x7205)},
5369         {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO,  0x720c)},
5370         {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO,  0x7214)},
5371         {REALTEK_USB_DEVICE(VENDOR_ID_LINKSYS, 0x0041)},
5372         {REALTEK_USB_DEVICE(VENDOR_ID_NVIDIA,  0x09ff)},
5373         {REALTEK_USB_DEVICE(VENDOR_ID_TPLINK,  0x0601)},
5374         {}
5375 };
5376
5377 MODULE_DEVICE_TABLE(usb, rtl8152_table);
5378
5379 static struct usb_driver rtl8152_driver = {
5380         .name =         MODULENAME,
5381         .id_table =     rtl8152_table,
5382         .probe =        rtl8152_probe,
5383         .disconnect =   rtl8152_disconnect,
5384         .suspend =      rtl8152_suspend,
5385         .resume =       rtl8152_resume,
5386         .reset_resume = rtl8152_reset_resume,
5387         .pre_reset =    rtl8152_pre_reset,
5388         .post_reset =   rtl8152_post_reset,
5389         .supports_autosuspend = 1,
5390         .disable_hub_initiated_lpm = 1,
5391 };
5392
5393 module_usb_driver(rtl8152_driver);
5394
5395 MODULE_AUTHOR(DRIVER_AUTHOR);
5396 MODULE_DESCRIPTION(DRIVER_DESC);
5397 MODULE_LICENSE("GPL");
5398 MODULE_VERSION(DRIVER_VERSION);