1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2014 Realtek Semiconductor Corp. All rights reserved.
6 #include <linux/signal.h>
7 #include <linux/slab.h>
8 #include <linux/module.h>
9 #include <linux/netdevice.h>
10 #include <linux/etherdevice.h>
11 #include <linux/mii.h>
12 #include <linux/ethtool.h>
13 #include <linux/usb.h>
14 #include <linux/crc32.h>
15 #include <linux/if_vlan.h>
16 #include <linux/uaccess.h>
17 #include <linux/list.h>
19 #include <linux/ipv6.h>
20 #include <net/ip6_checksum.h>
21 #include <uapi/linux/mdio.h>
22 #include <linux/mdio.h>
23 #include <linux/usb/cdc.h>
24 #include <linux/suspend.h>
25 #include <linux/acpi.h>
27 /* Information for net-next */
28 #define NETNEXT_VERSION "09"
30 /* Information for net */
31 #define NET_VERSION "10"
33 #define DRIVER_VERSION "v1." NETNEXT_VERSION "." NET_VERSION
34 #define DRIVER_AUTHOR "Realtek linux nic maintainers <nic_swsd@realtek.com>"
35 #define DRIVER_DESC "Realtek RTL8152/RTL8153 Based USB Ethernet Adapters"
36 #define MODULENAME "r8152"
38 #define R8152_PHY_ID 32
40 #define PLA_IDR 0xc000
41 #define PLA_RCR 0xc010
42 #define PLA_RMS 0xc016
43 #define PLA_RXFIFO_CTRL0 0xc0a0
44 #define PLA_RXFIFO_CTRL1 0xc0a4
45 #define PLA_RXFIFO_CTRL2 0xc0a8
46 #define PLA_DMY_REG0 0xc0b0
47 #define PLA_FMC 0xc0b4
48 #define PLA_CFG_WOL 0xc0b6
49 #define PLA_TEREDO_CFG 0xc0bc
50 #define PLA_TEREDO_WAKE_BASE 0xc0c4
51 #define PLA_MAR 0xcd00
52 #define PLA_BACKUP 0xd000
53 #define PLA_BDC_CR 0xd1a0
54 #define PLA_TEREDO_TIMER 0xd2cc
55 #define PLA_REALWOW_TIMER 0xd2e8
56 #define PLA_SUSPEND_FLAG 0xd38a
57 #define PLA_INDICATE_FALG 0xd38c
58 #define PLA_EXTRA_STATUS 0xd398
59 #define PLA_EFUSE_DATA 0xdd00
60 #define PLA_EFUSE_CMD 0xdd02
61 #define PLA_LEDSEL 0xdd90
62 #define PLA_LED_FEATURE 0xdd92
63 #define PLA_PHYAR 0xde00
64 #define PLA_BOOT_CTRL 0xe004
65 #define PLA_GPHY_INTR_IMR 0xe022
66 #define PLA_EEE_CR 0xe040
67 #define PLA_EEEP_CR 0xe080
68 #define PLA_MAC_PWR_CTRL 0xe0c0
69 #define PLA_MAC_PWR_CTRL2 0xe0ca
70 #define PLA_MAC_PWR_CTRL3 0xe0cc
71 #define PLA_MAC_PWR_CTRL4 0xe0ce
72 #define PLA_WDT6_CTRL 0xe428
73 #define PLA_TCR0 0xe610
74 #define PLA_TCR1 0xe612
75 #define PLA_MTPS 0xe615
76 #define PLA_TXFIFO_CTRL 0xe618
77 #define PLA_RSTTALLY 0xe800
79 #define PLA_CRWECR 0xe81c
80 #define PLA_CONFIG12 0xe81e /* CONFIG1, CONFIG2 */
81 #define PLA_CONFIG34 0xe820 /* CONFIG3, CONFIG4 */
82 #define PLA_CONFIG5 0xe822
83 #define PLA_PHY_PWR 0xe84c
84 #define PLA_OOB_CTRL 0xe84f
85 #define PLA_CPCR 0xe854
86 #define PLA_MISC_0 0xe858
87 #define PLA_MISC_1 0xe85a
88 #define PLA_OCP_GPHY_BASE 0xe86c
89 #define PLA_TALLYCNT 0xe890
90 #define PLA_SFF_STS_7 0xe8de
91 #define PLA_PHYSTATUS 0xe908
92 #define PLA_BP_BA 0xfc26
93 #define PLA_BP_0 0xfc28
94 #define PLA_BP_1 0xfc2a
95 #define PLA_BP_2 0xfc2c
96 #define PLA_BP_3 0xfc2e
97 #define PLA_BP_4 0xfc30
98 #define PLA_BP_5 0xfc32
99 #define PLA_BP_6 0xfc34
100 #define PLA_BP_7 0xfc36
101 #define PLA_BP_EN 0xfc38
103 #define USB_USB2PHY 0xb41e
104 #define USB_SSPHYLINK2 0xb428
105 #define USB_U2P3_CTRL 0xb460
106 #define USB_CSR_DUMMY1 0xb464
107 #define USB_CSR_DUMMY2 0xb466
108 #define USB_DEV_STAT 0xb808
109 #define USB_CONNECT_TIMER 0xcbf8
110 #define USB_MSC_TIMER 0xcbfc
111 #define USB_BURST_SIZE 0xcfc0
112 #define USB_LPM_CONFIG 0xcfd8
113 #define USB_USB_CTRL 0xd406
114 #define USB_PHY_CTRL 0xd408
115 #define USB_TX_AGG 0xd40a
116 #define USB_RX_BUF_TH 0xd40c
117 #define USB_USB_TIMER 0xd428
118 #define USB_RX_EARLY_TIMEOUT 0xd42c
119 #define USB_RX_EARLY_SIZE 0xd42e
120 #define USB_PM_CTRL_STATUS 0xd432 /* RTL8153A */
121 #define USB_RX_EXTRA_AGGR_TMR 0xd432 /* RTL8153B */
122 #define USB_TX_DMA 0xd434
123 #define USB_UPT_RXDMA_OWN 0xd437
124 #define USB_TOLERANCE 0xd490
125 #define USB_LPM_CTRL 0xd41a
126 #define USB_BMU_RESET 0xd4b0
127 #define USB_U1U2_TIMER 0xd4da
128 #define USB_UPS_CTRL 0xd800
129 #define USB_POWER_CUT 0xd80a
130 #define USB_MISC_0 0xd81a
131 #define USB_MISC_1 0xd81f
132 #define USB_AFE_CTRL2 0xd824
133 #define USB_UPS_CFG 0xd842
134 #define USB_UPS_FLAGS 0xd848
135 #define USB_WDT11_CTRL 0xe43c
136 #define USB_BP_BA 0xfc26
137 #define USB_BP_0 0xfc28
138 #define USB_BP_1 0xfc2a
139 #define USB_BP_2 0xfc2c
140 #define USB_BP_3 0xfc2e
141 #define USB_BP_4 0xfc30
142 #define USB_BP_5 0xfc32
143 #define USB_BP_6 0xfc34
144 #define USB_BP_7 0xfc36
145 #define USB_BP_EN 0xfc38
146 #define USB_BP_8 0xfc38
147 #define USB_BP_9 0xfc3a
148 #define USB_BP_10 0xfc3c
149 #define USB_BP_11 0xfc3e
150 #define USB_BP_12 0xfc40
151 #define USB_BP_13 0xfc42
152 #define USB_BP_14 0xfc44
153 #define USB_BP_15 0xfc46
154 #define USB_BP2_EN 0xfc48
157 #define OCP_ALDPS_CONFIG 0x2010
158 #define OCP_EEE_CONFIG1 0x2080
159 #define OCP_EEE_CONFIG2 0x2092
160 #define OCP_EEE_CONFIG3 0x2094
161 #define OCP_BASE_MII 0xa400
162 #define OCP_EEE_AR 0xa41a
163 #define OCP_EEE_DATA 0xa41c
164 #define OCP_PHY_STATUS 0xa420
165 #define OCP_NCTL_CFG 0xa42c
166 #define OCP_POWER_CFG 0xa430
167 #define OCP_EEE_CFG 0xa432
168 #define OCP_SRAM_ADDR 0xa436
169 #define OCP_SRAM_DATA 0xa438
170 #define OCP_DOWN_SPEED 0xa442
171 #define OCP_EEE_ABLE 0xa5c4
172 #define OCP_EEE_ADV 0xa5d0
173 #define OCP_EEE_LPABLE 0xa5d2
174 #define OCP_PHY_STATE 0xa708 /* nway state for 8153 */
175 #define OCP_PHY_PATCH_STAT 0xb800
176 #define OCP_PHY_PATCH_CMD 0xb820
177 #define OCP_ADC_IOFFSET 0xbcfc
178 #define OCP_ADC_CFG 0xbc06
179 #define OCP_SYSCLK_CFG 0xc416
182 #define SRAM_GREEN_CFG 0x8011
183 #define SRAM_LPF_CFG 0x8012
184 #define SRAM_10M_AMP1 0x8080
185 #define SRAM_10M_AMP2 0x8082
186 #define SRAM_IMPEDANCE 0x8084
189 #define RCR_AAP 0x00000001
190 #define RCR_APM 0x00000002
191 #define RCR_AM 0x00000004
192 #define RCR_AB 0x00000008
193 #define RCR_ACPT_ALL (RCR_AAP | RCR_APM | RCR_AM | RCR_AB)
195 /* PLA_RXFIFO_CTRL0 */
196 #define RXFIFO_THR1_NORMAL 0x00080002
197 #define RXFIFO_THR1_OOB 0x01800003
199 /* PLA_RXFIFO_CTRL1 */
200 #define RXFIFO_THR2_FULL 0x00000060
201 #define RXFIFO_THR2_HIGH 0x00000038
202 #define RXFIFO_THR2_OOB 0x0000004a
203 #define RXFIFO_THR2_NORMAL 0x00a0
205 /* PLA_RXFIFO_CTRL2 */
206 #define RXFIFO_THR3_FULL 0x00000078
207 #define RXFIFO_THR3_HIGH 0x00000048
208 #define RXFIFO_THR3_OOB 0x0000005a
209 #define RXFIFO_THR3_NORMAL 0x0110
211 /* PLA_TXFIFO_CTRL */
212 #define TXFIFO_THR_NORMAL 0x00400008
213 #define TXFIFO_THR_NORMAL2 0x01000008
216 #define ECM_ALDPS 0x0002
219 #define FMC_FCR_MCU_EN 0x0001
222 #define EEEP_CR_EEEP_TX 0x0002
225 #define WDT6_SET_MODE 0x0010
228 #define TCR0_TX_EMPTY 0x0800
229 #define TCR0_AUTO_FIFO 0x0080
232 #define VERSION_MASK 0x7cf0
235 #define MTPS_JUMBO (12 * 1024 / 64)
236 #define MTPS_DEFAULT (6 * 1024 / 64)
239 #define TALLY_RESET 0x0001
247 #define CRWECR_NORAML 0x00
248 #define CRWECR_CONFIG 0xc0
251 #define NOW_IS_OOB 0x80
252 #define TXFIFO_EMPTY 0x20
253 #define RXFIFO_EMPTY 0x10
254 #define LINK_LIST_READY 0x02
255 #define DIS_MCU_CLROOB 0x01
256 #define FIFO_EMPTY (TXFIFO_EMPTY | RXFIFO_EMPTY)
259 #define RXDY_GATED_EN 0x0008
262 #define RE_INIT_LL 0x8000
263 #define MCU_BORW_EN 0x4000
266 #define CPCR_RX_VLAN 0x0040
269 #define MAGIC_EN 0x0001
272 #define TEREDO_SEL 0x8000
273 #define TEREDO_WAKE_MASK 0x7f00
274 #define TEREDO_RS_EVENT_MASK 0x00fe
275 #define OOB_TEREDO_EN 0x0001
278 #define ALDPS_PROXY_MODE 0x0001
281 #define EFUSE_READ_CMD BIT(15)
282 #define EFUSE_DATA_BIT16 BIT(7)
285 #define LINK_ON_WAKE_EN 0x0010
286 #define LINK_OFF_WAKE_EN 0x0008
289 #define BWF_EN 0x0040
290 #define MWF_EN 0x0020
291 #define UWF_EN 0x0010
292 #define LAN_WAKE_EN 0x0002
294 /* PLA_LED_FEATURE */
295 #define LED_MODE_MASK 0x0700
298 #define TX_10M_IDLE_EN 0x0080
299 #define PFM_PWM_SWITCH 0x0040
301 /* PLA_MAC_PWR_CTRL */
302 #define D3_CLK_GATED_EN 0x00004000
303 #define MCU_CLK_RATIO 0x07010f07
304 #define MCU_CLK_RATIO_MASK 0x0f0f0f0f
305 #define ALDPS_SPDWN_RATIO 0x0f87
307 /* PLA_MAC_PWR_CTRL2 */
308 #define EEE_SPDWN_RATIO 0x8007
309 #define MAC_CLK_SPDWN_EN BIT(15)
311 /* PLA_MAC_PWR_CTRL3 */
312 #define PKT_AVAIL_SPDWN_EN 0x0100
313 #define SUSPEND_SPDWN_EN 0x0004
314 #define U1U2_SPDWN_EN 0x0002
315 #define L1_SPDWN_EN 0x0001
317 /* PLA_MAC_PWR_CTRL4 */
318 #define PWRSAVE_SPDWN_EN 0x1000
319 #define RXDV_SPDWN_EN 0x0800
320 #define TX10MIDLE_EN 0x0100
321 #define TP100_SPDWN_EN 0x0020
322 #define TP500_SPDWN_EN 0x0010
323 #define TP1000_SPDWN_EN 0x0008
324 #define EEE_SPDWN_EN 0x0001
326 /* PLA_GPHY_INTR_IMR */
327 #define GPHY_STS_MSK 0x0001
328 #define SPEED_DOWN_MSK 0x0002
329 #define SPDWN_RXDV_MSK 0x0004
330 #define SPDWN_LINKCHG_MSK 0x0008
333 #define PHYAR_FLAG 0x80000000
336 #define EEE_RX_EN 0x0001
337 #define EEE_TX_EN 0x0002
340 #define AUTOLOAD_DONE 0x0002
342 /* PLA_SUSPEND_FLAG */
343 #define LINK_CHG_EVENT BIT(0)
345 /* PLA_INDICATE_FALG */
346 #define UPCOMING_RUNTIME_D3 BIT(0)
348 /* PLA_EXTRA_STATUS */
349 #define LINK_CHANGE_FLAG BIT(8)
352 #define USB2PHY_SUSPEND 0x0001
353 #define USB2PHY_L1 0x0002
356 #define pwd_dn_scale_mask 0x3ffe
357 #define pwd_dn_scale(x) ((x) << 1)
360 #define DYNAMIC_BURST 0x0001
363 #define EP4_FULL_FC 0x0001
366 #define STAT_SPEED_MASK 0x0006
367 #define STAT_SPEED_HIGH 0x0000
368 #define STAT_SPEED_FULL 0x0002
371 #define LPM_U1U2_EN BIT(0)
374 #define TX_AGG_MAX_THRESHOLD 0x03
377 #define RX_THR_SUPPER 0x0c350180
378 #define RX_THR_HIGH 0x7a120180
379 #define RX_THR_SLOW 0xffff0180
380 #define RX_THR_B 0x00010001
383 #define TEST_MODE_DISABLE 0x00000001
384 #define TX_SIZE_ADJUST1 0x00000100
387 #define BMU_RESET_EP_IN 0x01
388 #define BMU_RESET_EP_OUT 0x02
390 /* USB_UPT_RXDMA_OWN */
391 #define OWN_UPDATE BIT(0)
392 #define OWN_CLEAR BIT(1)
395 #define POWER_CUT 0x0100
397 /* USB_PM_CTRL_STATUS */
398 #define RESUME_INDICATE 0x0001
401 #define RX_AGG_DISABLE 0x0010
402 #define RX_ZERO_EN 0x0080
405 #define U2P3_ENABLE 0x0001
408 #define PWR_EN 0x0001
409 #define PHASE2_EN 0x0008
410 #define UPS_EN BIT(4)
411 #define USP_PREWAKE BIT(5)
414 #define PCUT_STATUS 0x0001
416 /* USB_RX_EARLY_TIMEOUT */
417 #define COALESCE_SUPER 85000U
418 #define COALESCE_HIGH 250000U
419 #define COALESCE_SLOW 524280U
422 #define TIMER11_EN 0x0001
425 /* bit 4 ~ 5: fifo empty boundary */
426 #define FIFO_EMPTY_1FB 0x30 /* 0x1fb * 64 = 32448 bytes */
427 /* bit 2 ~ 3: LMP timer */
428 #define LPM_TIMER_MASK 0x0c
429 #define LPM_TIMER_500MS 0x04 /* 500 ms */
430 #define LPM_TIMER_500US 0x0c /* 500 us */
431 #define ROK_EXIT_LPM 0x02
434 #define SEN_VAL_MASK 0xf800
435 #define SEN_VAL_NORMAL 0xa000
436 #define SEL_RXIDLE 0x0100
439 #define SAW_CNT_1MS_MASK 0x0fff
442 #define UPS_FLAGS_R_TUNE BIT(0)
443 #define UPS_FLAGS_EN_10M_CKDIV BIT(1)
444 #define UPS_FLAGS_250M_CKDIV BIT(2)
445 #define UPS_FLAGS_EN_ALDPS BIT(3)
446 #define UPS_FLAGS_CTAP_SHORT_DIS BIT(4)
447 #define UPS_FLAGS_SPEED_MASK (0xf << 16)
448 #define ups_flags_speed(x) ((x) << 16)
449 #define UPS_FLAGS_EN_EEE BIT(20)
450 #define UPS_FLAGS_EN_500M_EEE BIT(21)
451 #define UPS_FLAGS_EN_EEE_CKDIV BIT(22)
452 #define UPS_FLAGS_EEE_PLLOFF_GIGA BIT(24)
453 #define UPS_FLAGS_EEE_CMOD_LV_EN BIT(25)
454 #define UPS_FLAGS_EN_GREEN BIT(26)
455 #define UPS_FLAGS_EN_FLOW_CTR BIT(27)
469 /* OCP_ALDPS_CONFIG */
470 #define ENPWRSAVE 0x8000
471 #define ENPDNPS 0x0200
472 #define LINKENA 0x0100
473 #define DIS_SDSAVE 0x0010
476 #define PHY_STAT_MASK 0x0007
477 #define PHY_STAT_EXT_INIT 2
478 #define PHY_STAT_LAN_ON 3
479 #define PHY_STAT_PWRDN 5
482 #define PGA_RETURN_EN BIT(1)
485 #define EEE_CLKDIV_EN 0x8000
486 #define EN_ALDPS 0x0004
487 #define EN_10M_PLLOFF 0x0001
489 /* OCP_EEE_CONFIG1 */
490 #define RG_TXLPI_MSK_HFDUP 0x8000
491 #define RG_MATCLR_EN 0x4000
492 #define EEE_10_CAP 0x2000
493 #define EEE_NWAY_EN 0x1000
494 #define TX_QUIET_EN 0x0200
495 #define RX_QUIET_EN 0x0100
496 #define sd_rise_time_mask 0x0070
497 #define sd_rise_time(x) (min(x, 7) << 4) /* bit 4 ~ 6 */
498 #define RG_RXLPI_MSK_HFDUP 0x0008
499 #define SDFALLTIME 0x0007 /* bit 0 ~ 2 */
501 /* OCP_EEE_CONFIG2 */
502 #define RG_LPIHYS_NUM 0x7000 /* bit 12 ~ 15 */
503 #define RG_DACQUIET_EN 0x0400
504 #define RG_LDVQUIET_EN 0x0200
505 #define RG_CKRSEL 0x0020
506 #define RG_EEEPRG_EN 0x0010
508 /* OCP_EEE_CONFIG3 */
509 #define fast_snr_mask 0xff80
510 #define fast_snr(x) (min(x, 0x1ff) << 7) /* bit 7 ~ 15 */
511 #define RG_LFS_SEL 0x0060 /* bit 6 ~ 5 */
512 #define MSK_PH 0x0006 /* bit 0 ~ 3 */
515 /* bit[15:14] function */
516 #define FUN_ADDR 0x0000
517 #define FUN_DATA 0x4000
518 /* bit[4:0] device addr */
521 #define CTAP_SHORT_EN 0x0040
522 #define EEE10_EN 0x0010
525 #define EN_EEE_CMODE BIT(14)
526 #define EN_EEE_1000 BIT(13)
527 #define EN_EEE_100 BIT(12)
528 #define EN_10M_CLKDIV BIT(11)
529 #define EN_10M_BGOFF 0x0080
532 #define TXDIS_STATE 0x01
533 #define ABD_STATE 0x02
535 /* OCP_PHY_PATCH_STAT */
536 #define PATCH_READY BIT(6)
538 /* OCP_PHY_PATCH_CMD */
539 #define PATCH_REQUEST BIT(4)
542 #define CKADSEL_L 0x0100
543 #define ADC_EN 0x0080
544 #define EN_EMI_L 0x0040
547 #define clk_div_expo(x) (min(x, 5) << 8)
550 #define GREEN_ETH_EN BIT(15)
551 #define R_TUNE_EN BIT(11)
554 #define LPF_AUTO_TUNE 0x8000
557 #define GDAC_IB_UPALL 0x0008
560 #define AMP_DN 0x0200
563 #define RX_DRIVING_MASK 0x6000
566 #define AD_MASK 0xfee0
567 #define BND_MASK 0x0004
568 #define BD_MASK 0x0001
570 #define PASS_THRU_MASK 0x1
572 enum rtl_register_content {
580 #define RTL8152_MAX_TX 4
581 #define RTL8152_MAX_RX 10
586 #define INTR_LINK 0x0004
588 #define RTL8152_REQT_READ 0xc0
589 #define RTL8152_REQT_WRITE 0x40
590 #define RTL8152_REQ_GET_REGS 0x05
591 #define RTL8152_REQ_SET_REGS 0x05
593 #define BYTE_EN_DWORD 0xff
594 #define BYTE_EN_WORD 0x33
595 #define BYTE_EN_BYTE 0x11
596 #define BYTE_EN_SIX_BYTES 0x3f
597 #define BYTE_EN_START_MASK 0x0f
598 #define BYTE_EN_END_MASK 0xf0
600 #define RTL8153_MAX_PACKET 9216 /* 9K */
601 #define RTL8153_MAX_MTU (RTL8153_MAX_PACKET - VLAN_ETH_HLEN - \
603 #define RTL8152_RMS (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN)
604 #define RTL8153_RMS RTL8153_MAX_PACKET
605 #define RTL8152_TX_TIMEOUT (5 * HZ)
606 #define RTL8152_NAPI_WEIGHT 64
607 #define rx_reserved_size(x) ((x) + VLAN_ETH_HLEN + ETH_FCS_LEN + \
608 sizeof(struct rx_desc) + RX_ALIGN)
623 /* Define these values to match your device */
624 #define VENDOR_ID_REALTEK 0x0bda
625 #define VENDOR_ID_MICROSOFT 0x045e
626 #define VENDOR_ID_SAMSUNG 0x04e8
627 #define VENDOR_ID_LENOVO 0x17ef
628 #define VENDOR_ID_LINKSYS 0x13b1
629 #define VENDOR_ID_NVIDIA 0x0955
630 #define VENDOR_ID_TPLINK 0x2357
632 #define MCU_TYPE_PLA 0x0100
633 #define MCU_TYPE_USB 0x0000
635 struct tally_counter {
642 __le32 tx_one_collision;
643 __le32 tx_multi_collision;
653 #define RX_LEN_MASK 0x7fff
656 #define RD_UDP_CS BIT(23)
657 #define RD_TCP_CS BIT(22)
658 #define RD_IPV6_CS BIT(20)
659 #define RD_IPV4_CS BIT(19)
662 #define IPF BIT(23) /* IP checksum fail */
663 #define UDPF BIT(22) /* UDP checksum fail */
664 #define TCPF BIT(21) /* TCP checksum fail */
665 #define RX_VLAN_TAG BIT(16)
674 #define TX_FS BIT(31) /* First segment of a packet */
675 #define TX_LS BIT(30) /* Final segment of a packet */
676 #define GTSENDV4 BIT(28)
677 #define GTSENDV6 BIT(27)
678 #define GTTCPHO_SHIFT 18
679 #define GTTCPHO_MAX 0x7fU
680 #define TX_LEN_MAX 0x3ffffU
683 #define UDP_CS BIT(31) /* Calculate UDP/IP checksum */
684 #define TCP_CS BIT(30) /* Calculate TCP/IP checksum */
685 #define IPV4_CS BIT(29) /* Calculate IPv4 checksum */
686 #define IPV6_CS BIT(28) /* Calculate IPv6 checksum */
688 #define MSS_MAX 0x7ffU
689 #define TCPHO_SHIFT 17
690 #define TCPHO_MAX 0x7ffU
691 #define TX_VLAN_TAG BIT(16)
697 struct list_head list;
699 struct r8152 *context;
705 struct list_head list;
707 struct r8152 *context;
716 struct usb_device *udev;
717 struct napi_struct napi;
718 struct usb_interface *intf;
719 struct net_device *netdev;
720 struct urb *intr_urb;
721 struct tx_agg tx_info[RTL8152_MAX_TX];
722 struct rx_agg rx_info[RTL8152_MAX_RX];
723 struct list_head rx_done, tx_free;
724 struct sk_buff_head tx_queue, rx_queue;
725 spinlock_t rx_lock, tx_lock;
726 struct delayed_work schedule, hw_phy_work;
727 struct mii_if_info mii;
728 struct mutex control; /* use for hw setting */
729 #ifdef CONFIG_PM_SLEEP
730 struct notifier_block pm_notifier;
734 void (*init)(struct r8152 *);
735 int (*enable)(struct r8152 *);
736 void (*disable)(struct r8152 *);
737 void (*up)(struct r8152 *);
738 void (*down)(struct r8152 *);
739 void (*unload)(struct r8152 *);
740 int (*eee_get)(struct r8152 *, struct ethtool_eee *);
741 int (*eee_set)(struct r8152 *, struct ethtool_eee *);
742 bool (*in_nway)(struct r8152 *);
743 void (*hw_phy_cfg)(struct r8152 *);
744 void (*autosuspend_en)(struct r8152 *tp, bool enable);
780 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
781 * The RTL chips use a 64 element hash table based on the Ethernet CRC.
783 static const int multicast_filter_limit = 32;
784 static unsigned int agg_buf_sz = 16384;
786 #define RTL_LIMITED_TSO_SIZE (agg_buf_sz - sizeof(struct tx_desc) - \
787 VLAN_ETH_HLEN - ETH_FCS_LEN)
790 int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
795 tmp = kmalloc(size, GFP_KERNEL);
799 ret = usb_control_msg(tp->udev, usb_rcvctrlpipe(tp->udev, 0),
800 RTL8152_REQ_GET_REGS, RTL8152_REQT_READ,
801 value, index, tmp, size, 500);
803 memcpy(data, tmp, size);
810 int set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
815 tmp = kmemdup(data, size, GFP_KERNEL);
819 ret = usb_control_msg(tp->udev, usb_sndctrlpipe(tp->udev, 0),
820 RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE,
821 value, index, tmp, size, 500);
828 static void rtl_set_unplug(struct r8152 *tp)
830 if (tp->udev->state == USB_STATE_NOTATTACHED) {
831 set_bit(RTL8152_UNPLUG, &tp->flags);
832 smp_mb__after_atomic();
836 static int generic_ocp_read(struct r8152 *tp, u16 index, u16 size,
837 void *data, u16 type)
842 if (test_bit(RTL8152_UNPLUG, &tp->flags))
845 /* both size and indix must be 4 bytes align */
846 if ((size & 3) || !size || (index & 3) || !data)
849 if ((u32)index + (u32)size > 0xffff)
854 ret = get_registers(tp, index, type, limit, data);
862 ret = get_registers(tp, index, type, size, data);
879 static int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen,
880 u16 size, void *data, u16 type)
883 u16 byteen_start, byteen_end, byen;
886 if (test_bit(RTL8152_UNPLUG, &tp->flags))
889 /* both size and indix must be 4 bytes align */
890 if ((size & 3) || !size || (index & 3) || !data)
893 if ((u32)index + (u32)size > 0xffff)
896 byteen_start = byteen & BYTE_EN_START_MASK;
897 byteen_end = byteen & BYTE_EN_END_MASK;
899 byen = byteen_start | (byteen_start << 4);
900 ret = set_registers(tp, index, type | byen, 4, data);
913 ret = set_registers(tp, index,
914 type | BYTE_EN_DWORD,
923 ret = set_registers(tp, index,
924 type | BYTE_EN_DWORD,
936 byen = byteen_end | (byteen_end >> 4);
937 ret = set_registers(tp, index, type | byen, 4, data);
950 int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
952 return generic_ocp_read(tp, index, size, data, MCU_TYPE_PLA);
956 int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
958 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_PLA);
962 int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
964 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_USB);
967 static u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index)
971 generic_ocp_read(tp, index, sizeof(data), &data, type);
973 return __le32_to_cpu(data);
976 static void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data)
978 __le32 tmp = __cpu_to_le32(data);
980 generic_ocp_write(tp, index, BYTE_EN_DWORD, sizeof(tmp), &tmp, type);
983 static u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index)
987 u16 byen = BYTE_EN_WORD;
988 u8 shift = index & 2;
993 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type | byen);
995 data = __le32_to_cpu(tmp);
996 data >>= (shift * 8);
1002 static void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data)
1006 u16 byen = BYTE_EN_WORD;
1007 u8 shift = index & 2;
1013 mask <<= (shift * 8);
1014 data <<= (shift * 8);
1018 tmp = __cpu_to_le32(data);
1020 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
1023 static u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index)
1027 u8 shift = index & 3;
1031 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
1033 data = __le32_to_cpu(tmp);
1034 data >>= (shift * 8);
1040 static void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data)
1044 u16 byen = BYTE_EN_BYTE;
1045 u8 shift = index & 3;
1051 mask <<= (shift * 8);
1052 data <<= (shift * 8);
1056 tmp = __cpu_to_le32(data);
1058 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
1061 static u16 ocp_reg_read(struct r8152 *tp, u16 addr)
1063 u16 ocp_base, ocp_index;
1065 ocp_base = addr & 0xf000;
1066 if (ocp_base != tp->ocp_base) {
1067 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
1068 tp->ocp_base = ocp_base;
1071 ocp_index = (addr & 0x0fff) | 0xb000;
1072 return ocp_read_word(tp, MCU_TYPE_PLA, ocp_index);
1075 static void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data)
1077 u16 ocp_base, ocp_index;
1079 ocp_base = addr & 0xf000;
1080 if (ocp_base != tp->ocp_base) {
1081 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
1082 tp->ocp_base = ocp_base;
1085 ocp_index = (addr & 0x0fff) | 0xb000;
1086 ocp_write_word(tp, MCU_TYPE_PLA, ocp_index, data);
1089 static inline void r8152_mdio_write(struct r8152 *tp, u32 reg_addr, u32 value)
1091 ocp_reg_write(tp, OCP_BASE_MII + reg_addr * 2, value);
1094 static inline int r8152_mdio_read(struct r8152 *tp, u32 reg_addr)
1096 return ocp_reg_read(tp, OCP_BASE_MII + reg_addr * 2);
1099 static void sram_write(struct r8152 *tp, u16 addr, u16 data)
1101 ocp_reg_write(tp, OCP_SRAM_ADDR, addr);
1102 ocp_reg_write(tp, OCP_SRAM_DATA, data);
1105 static u16 sram_read(struct r8152 *tp, u16 addr)
1107 ocp_reg_write(tp, OCP_SRAM_ADDR, addr);
1108 return ocp_reg_read(tp, OCP_SRAM_DATA);
1111 static int read_mii_word(struct net_device *netdev, int phy_id, int reg)
1113 struct r8152 *tp = netdev_priv(netdev);
1116 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1119 if (phy_id != R8152_PHY_ID)
1122 ret = r8152_mdio_read(tp, reg);
1128 void write_mii_word(struct net_device *netdev, int phy_id, int reg, int val)
1130 struct r8152 *tp = netdev_priv(netdev);
1132 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1135 if (phy_id != R8152_PHY_ID)
1138 r8152_mdio_write(tp, reg, val);
1142 r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags);
1144 static int rtl8152_set_mac_address(struct net_device *netdev, void *p)
1146 struct r8152 *tp = netdev_priv(netdev);
1147 struct sockaddr *addr = p;
1148 int ret = -EADDRNOTAVAIL;
1150 if (!is_valid_ether_addr(addr->sa_data))
1153 ret = usb_autopm_get_interface(tp->intf);
1157 mutex_lock(&tp->control);
1159 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
1161 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
1162 pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, addr->sa_data);
1163 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
1165 mutex_unlock(&tp->control);
1167 usb_autopm_put_interface(tp->intf);
1172 /* Devices containing proper chips can support a persistent
1173 * host system provided MAC address.
1174 * Examples of this are Dell TB15 and Dell WD15 docks
1176 static int vendor_mac_passthru_addr_read(struct r8152 *tp, struct sockaddr *sa)
1179 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
1180 union acpi_object *obj;
1183 unsigned char buf[6];
1185 /* test for -AD variant of RTL8153 */
1186 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
1187 if ((ocp_data & AD_MASK) == 0x1000) {
1188 /* test for MAC address pass-through bit */
1189 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, EFUSE);
1190 if ((ocp_data & PASS_THRU_MASK) != 1) {
1191 netif_dbg(tp, probe, tp->netdev,
1192 "No efuse for RTL8153-AD MAC pass through\n");
1196 /* test for RTL8153-BND and RTL8153-BD */
1197 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_1);
1198 if ((ocp_data & BND_MASK) == 0 && (ocp_data & BD_MASK) == 0) {
1199 netif_dbg(tp, probe, tp->netdev,
1200 "Invalid variant for MAC pass through\n");
1205 /* returns _AUXMAC_#AABBCCDDEEFF# */
1206 status = acpi_evaluate_object(NULL, "\\_SB.AMAC", NULL, &buffer);
1207 obj = (union acpi_object *)buffer.pointer;
1208 if (!ACPI_SUCCESS(status))
1210 if (obj->type != ACPI_TYPE_BUFFER || obj->string.length != 0x17) {
1211 netif_warn(tp, probe, tp->netdev,
1212 "Invalid buffer for pass-thru MAC addr: (%d, %d)\n",
1213 obj->type, obj->string.length);
1216 if (strncmp(obj->string.pointer, "_AUXMAC_#", 9) != 0 ||
1217 strncmp(obj->string.pointer + 0x15, "#", 1) != 0) {
1218 netif_warn(tp, probe, tp->netdev,
1219 "Invalid header when reading pass-thru MAC addr\n");
1222 ret = hex2bin(buf, obj->string.pointer + 9, 6);
1223 if (!(ret == 0 && is_valid_ether_addr(buf))) {
1224 netif_warn(tp, probe, tp->netdev,
1225 "Invalid MAC for pass-thru MAC addr: %d, %pM\n",
1230 memcpy(sa->sa_data, buf, 6);
1231 netif_info(tp, probe, tp->netdev,
1232 "Using pass-thru MAC addr %pM\n", sa->sa_data);
1239 static int determine_ethernet_addr(struct r8152 *tp, struct sockaddr *sa)
1241 struct net_device *dev = tp->netdev;
1244 sa->sa_family = dev->type;
1246 if (tp->version == RTL_VER_01) {
1247 ret = pla_ocp_read(tp, PLA_IDR, 8, sa->sa_data);
1249 /* if device doesn't support MAC pass through this will
1250 * be expected to be non-zero
1252 ret = vendor_mac_passthru_addr_read(tp, sa);
1254 ret = pla_ocp_read(tp, PLA_BACKUP, 8, sa->sa_data);
1258 netif_err(tp, probe, dev, "Get ether addr fail\n");
1259 } else if (!is_valid_ether_addr(sa->sa_data)) {
1260 netif_err(tp, probe, dev, "Invalid ether addr %pM\n",
1262 eth_hw_addr_random(dev);
1263 ether_addr_copy(sa->sa_data, dev->dev_addr);
1264 netif_info(tp, probe, dev, "Random ether addr %pM\n",
1272 static int set_ethernet_addr(struct r8152 *tp)
1274 struct net_device *dev = tp->netdev;
1278 ret = determine_ethernet_addr(tp, &sa);
1282 if (tp->version == RTL_VER_01)
1283 ether_addr_copy(dev->dev_addr, sa.sa_data);
1285 ret = rtl8152_set_mac_address(dev, &sa);
1290 static void read_bulk_callback(struct urb *urb)
1292 struct net_device *netdev;
1293 int status = urb->status;
1296 unsigned long flags;
1306 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1309 if (!test_bit(WORK_ENABLE, &tp->flags))
1312 netdev = tp->netdev;
1314 /* When link down, the driver would cancel all bulks. */
1315 /* This avoid the re-submitting bulk */
1316 if (!netif_carrier_ok(netdev))
1319 usb_mark_last_busy(tp->udev);
1323 if (urb->actual_length < ETH_ZLEN)
1326 spin_lock_irqsave(&tp->rx_lock, flags);
1327 list_add_tail(&agg->list, &tp->rx_done);
1328 spin_unlock_irqrestore(&tp->rx_lock, flags);
1329 napi_schedule(&tp->napi);
1333 netif_device_detach(tp->netdev);
1336 return; /* the urb is in unlink state */
1338 if (net_ratelimit())
1339 netdev_warn(netdev, "maybe reset is needed?\n");
1342 if (net_ratelimit())
1343 netdev_warn(netdev, "Rx status %d\n", status);
1347 r8152_submit_rx(tp, agg, GFP_ATOMIC);
1350 static void write_bulk_callback(struct urb *urb)
1352 struct net_device_stats *stats;
1353 struct net_device *netdev;
1356 unsigned long flags;
1357 int status = urb->status;
1367 netdev = tp->netdev;
1368 stats = &netdev->stats;
1370 if (net_ratelimit())
1371 netdev_warn(netdev, "Tx status %d\n", status);
1372 stats->tx_errors += agg->skb_num;
1374 stats->tx_packets += agg->skb_num;
1375 stats->tx_bytes += agg->skb_len;
1378 spin_lock_irqsave(&tp->tx_lock, flags);
1379 list_add_tail(&agg->list, &tp->tx_free);
1380 spin_unlock_irqrestore(&tp->tx_lock, flags);
1382 usb_autopm_put_interface_async(tp->intf);
1384 if (!netif_carrier_ok(netdev))
1387 if (!test_bit(WORK_ENABLE, &tp->flags))
1390 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1393 if (!skb_queue_empty(&tp->tx_queue))
1394 napi_schedule(&tp->napi);
1397 static void intr_callback(struct urb *urb)
1401 int status = urb->status;
1408 if (!test_bit(WORK_ENABLE, &tp->flags))
1411 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1415 case 0: /* success */
1417 case -ECONNRESET: /* unlink */
1419 netif_device_detach(tp->netdev);
1423 netif_info(tp, intr, tp->netdev,
1424 "Stop submitting intr, status %d\n", status);
1427 netif_info(tp, intr, tp->netdev, "intr status -EOVERFLOW\n");
1429 /* -EPIPE: should clear the halt */
1431 netif_info(tp, intr, tp->netdev, "intr status %d\n", status);
1435 d = urb->transfer_buffer;
1436 if (INTR_LINK & __le16_to_cpu(d[0])) {
1437 if (!netif_carrier_ok(tp->netdev)) {
1438 set_bit(RTL8152_LINK_CHG, &tp->flags);
1439 schedule_delayed_work(&tp->schedule, 0);
1442 if (netif_carrier_ok(tp->netdev)) {
1443 netif_stop_queue(tp->netdev);
1444 set_bit(RTL8152_LINK_CHG, &tp->flags);
1445 schedule_delayed_work(&tp->schedule, 0);
1450 res = usb_submit_urb(urb, GFP_ATOMIC);
1451 if (res == -ENODEV) {
1453 netif_device_detach(tp->netdev);
1455 netif_err(tp, intr, tp->netdev,
1456 "can't resubmit intr, status %d\n", res);
1460 static inline void *rx_agg_align(void *data)
1462 return (void *)ALIGN((uintptr_t)data, RX_ALIGN);
1465 static inline void *tx_agg_align(void *data)
1467 return (void *)ALIGN((uintptr_t)data, TX_ALIGN);
1470 static void free_all_mem(struct r8152 *tp)
1474 for (i = 0; i < RTL8152_MAX_RX; i++) {
1475 usb_free_urb(tp->rx_info[i].urb);
1476 tp->rx_info[i].urb = NULL;
1478 kfree(tp->rx_info[i].buffer);
1479 tp->rx_info[i].buffer = NULL;
1480 tp->rx_info[i].head = NULL;
1483 for (i = 0; i < RTL8152_MAX_TX; i++) {
1484 usb_free_urb(tp->tx_info[i].urb);
1485 tp->tx_info[i].urb = NULL;
1487 kfree(tp->tx_info[i].buffer);
1488 tp->tx_info[i].buffer = NULL;
1489 tp->tx_info[i].head = NULL;
1492 usb_free_urb(tp->intr_urb);
1493 tp->intr_urb = NULL;
1495 kfree(tp->intr_buff);
1496 tp->intr_buff = NULL;
1499 static int alloc_all_mem(struct r8152 *tp)
1501 struct net_device *netdev = tp->netdev;
1502 struct usb_interface *intf = tp->intf;
1503 struct usb_host_interface *alt = intf->cur_altsetting;
1504 struct usb_host_endpoint *ep_intr = alt->endpoint + 2;
1509 node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1;
1511 spin_lock_init(&tp->rx_lock);
1512 spin_lock_init(&tp->tx_lock);
1513 INIT_LIST_HEAD(&tp->tx_free);
1514 INIT_LIST_HEAD(&tp->rx_done);
1515 skb_queue_head_init(&tp->tx_queue);
1516 skb_queue_head_init(&tp->rx_queue);
1518 for (i = 0; i < RTL8152_MAX_RX; i++) {
1519 buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node);
1523 if (buf != rx_agg_align(buf)) {
1525 buf = kmalloc_node(agg_buf_sz + RX_ALIGN, GFP_KERNEL,
1531 urb = usb_alloc_urb(0, GFP_KERNEL);
1537 INIT_LIST_HEAD(&tp->rx_info[i].list);
1538 tp->rx_info[i].context = tp;
1539 tp->rx_info[i].urb = urb;
1540 tp->rx_info[i].buffer = buf;
1541 tp->rx_info[i].head = rx_agg_align(buf);
1544 for (i = 0; i < RTL8152_MAX_TX; i++) {
1545 buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node);
1549 if (buf != tx_agg_align(buf)) {
1551 buf = kmalloc_node(agg_buf_sz + TX_ALIGN, GFP_KERNEL,
1557 urb = usb_alloc_urb(0, GFP_KERNEL);
1563 INIT_LIST_HEAD(&tp->tx_info[i].list);
1564 tp->tx_info[i].context = tp;
1565 tp->tx_info[i].urb = urb;
1566 tp->tx_info[i].buffer = buf;
1567 tp->tx_info[i].head = tx_agg_align(buf);
1569 list_add_tail(&tp->tx_info[i].list, &tp->tx_free);
1572 tp->intr_urb = usb_alloc_urb(0, GFP_KERNEL);
1576 tp->intr_buff = kmalloc(INTBUFSIZE, GFP_KERNEL);
1580 tp->intr_interval = (int)ep_intr->desc.bInterval;
1581 usb_fill_int_urb(tp->intr_urb, tp->udev, usb_rcvintpipe(tp->udev, 3),
1582 tp->intr_buff, INTBUFSIZE, intr_callback,
1583 tp, tp->intr_interval);
1592 static struct tx_agg *r8152_get_tx_agg(struct r8152 *tp)
1594 struct tx_agg *agg = NULL;
1595 unsigned long flags;
1597 if (list_empty(&tp->tx_free))
1600 spin_lock_irqsave(&tp->tx_lock, flags);
1601 if (!list_empty(&tp->tx_free)) {
1602 struct list_head *cursor;
1604 cursor = tp->tx_free.next;
1605 list_del_init(cursor);
1606 agg = list_entry(cursor, struct tx_agg, list);
1608 spin_unlock_irqrestore(&tp->tx_lock, flags);
1613 /* r8152_csum_workaround()
1614 * The hw limites the value the transport offset. When the offset is out of the
1615 * range, calculate the checksum by sw.
1617 static void r8152_csum_workaround(struct r8152 *tp, struct sk_buff *skb,
1618 struct sk_buff_head *list)
1620 if (skb_shinfo(skb)->gso_size) {
1621 netdev_features_t features = tp->netdev->features;
1622 struct sk_buff_head seg_list;
1623 struct sk_buff *segs, *nskb;
1625 features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
1626 segs = skb_gso_segment(skb, features);
1627 if (IS_ERR(segs) || !segs)
1630 __skb_queue_head_init(&seg_list);
1636 __skb_queue_tail(&seg_list, nskb);
1639 skb_queue_splice(&seg_list, list);
1641 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
1642 if (skb_checksum_help(skb) < 0)
1645 __skb_queue_head(list, skb);
1647 struct net_device_stats *stats;
1650 stats = &tp->netdev->stats;
1651 stats->tx_dropped++;
1656 /* msdn_giant_send_check()
1657 * According to the document of microsoft, the TCP Pseudo Header excludes the
1658 * packet length for IPv6 TCP large packets.
1660 static int msdn_giant_send_check(struct sk_buff *skb)
1662 const struct ipv6hdr *ipv6h;
1666 ret = skb_cow_head(skb, 0);
1670 ipv6h = ipv6_hdr(skb);
1674 th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0);
1679 static inline void rtl_tx_vlan_tag(struct tx_desc *desc, struct sk_buff *skb)
1681 if (skb_vlan_tag_present(skb)) {
1684 opts2 = TX_VLAN_TAG | swab16(skb_vlan_tag_get(skb));
1685 desc->opts2 |= cpu_to_le32(opts2);
1689 static inline void rtl_rx_vlan_tag(struct rx_desc *desc, struct sk_buff *skb)
1691 u32 opts2 = le32_to_cpu(desc->opts2);
1693 if (opts2 & RX_VLAN_TAG)
1694 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
1695 swab16(opts2 & 0xffff));
1698 static int r8152_tx_csum(struct r8152 *tp, struct tx_desc *desc,
1699 struct sk_buff *skb, u32 len, u32 transport_offset)
1701 u32 mss = skb_shinfo(skb)->gso_size;
1702 u32 opts1, opts2 = 0;
1703 int ret = TX_CSUM_SUCCESS;
1705 WARN_ON_ONCE(len > TX_LEN_MAX);
1707 opts1 = len | TX_FS | TX_LS;
1710 if (transport_offset > GTTCPHO_MAX) {
1711 netif_warn(tp, tx_err, tp->netdev,
1712 "Invalid transport offset 0x%x for TSO\n",
1718 switch (vlan_get_protocol(skb)) {
1719 case htons(ETH_P_IP):
1723 case htons(ETH_P_IPV6):
1724 if (msdn_giant_send_check(skb)) {
1736 opts1 |= transport_offset << GTTCPHO_SHIFT;
1737 opts2 |= min(mss, MSS_MAX) << MSS_SHIFT;
1738 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
1741 if (transport_offset > TCPHO_MAX) {
1742 netif_warn(tp, tx_err, tp->netdev,
1743 "Invalid transport offset 0x%x\n",
1749 switch (vlan_get_protocol(skb)) {
1750 case htons(ETH_P_IP):
1752 ip_protocol = ip_hdr(skb)->protocol;
1755 case htons(ETH_P_IPV6):
1757 ip_protocol = ipv6_hdr(skb)->nexthdr;
1761 ip_protocol = IPPROTO_RAW;
1765 if (ip_protocol == IPPROTO_TCP)
1767 else if (ip_protocol == IPPROTO_UDP)
1772 opts2 |= transport_offset << TCPHO_SHIFT;
1775 desc->opts2 = cpu_to_le32(opts2);
1776 desc->opts1 = cpu_to_le32(opts1);
1782 static int r8152_tx_agg_fill(struct r8152 *tp, struct tx_agg *agg)
1784 struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
1788 __skb_queue_head_init(&skb_head);
1789 spin_lock(&tx_queue->lock);
1790 skb_queue_splice_init(tx_queue, &skb_head);
1791 spin_unlock(&tx_queue->lock);
1793 tx_data = agg->head;
1796 remain = agg_buf_sz;
1798 while (remain >= ETH_ZLEN + sizeof(struct tx_desc)) {
1799 struct tx_desc *tx_desc;
1800 struct sk_buff *skb;
1804 skb = __skb_dequeue(&skb_head);
1808 len = skb->len + sizeof(*tx_desc);
1811 __skb_queue_head(&skb_head, skb);
1815 tx_data = tx_agg_align(tx_data);
1816 tx_desc = (struct tx_desc *)tx_data;
1818 offset = (u32)skb_transport_offset(skb);
1820 if (r8152_tx_csum(tp, tx_desc, skb, skb->len, offset)) {
1821 r8152_csum_workaround(tp, skb, &skb_head);
1825 rtl_tx_vlan_tag(tx_desc, skb);
1827 tx_data += sizeof(*tx_desc);
1830 if (skb_copy_bits(skb, 0, tx_data, len) < 0) {
1831 struct net_device_stats *stats = &tp->netdev->stats;
1833 stats->tx_dropped++;
1834 dev_kfree_skb_any(skb);
1835 tx_data -= sizeof(*tx_desc);
1840 agg->skb_len += len;
1841 agg->skb_num += skb_shinfo(skb)->gso_segs ?: 1;
1843 dev_kfree_skb_any(skb);
1845 remain = agg_buf_sz - (int)(tx_agg_align(tx_data) - agg->head);
1847 if (test_bit(DELL_TB_RX_AGG_BUG, &tp->flags))
1851 if (!skb_queue_empty(&skb_head)) {
1852 spin_lock(&tx_queue->lock);
1853 skb_queue_splice(&skb_head, tx_queue);
1854 spin_unlock(&tx_queue->lock);
1857 netif_tx_lock(tp->netdev);
1859 if (netif_queue_stopped(tp->netdev) &&
1860 skb_queue_len(&tp->tx_queue) < tp->tx_qlen)
1861 netif_wake_queue(tp->netdev);
1863 netif_tx_unlock(tp->netdev);
1865 ret = usb_autopm_get_interface_async(tp->intf);
1869 usb_fill_bulk_urb(agg->urb, tp->udev, usb_sndbulkpipe(tp->udev, 2),
1870 agg->head, (int)(tx_data - (u8 *)agg->head),
1871 (usb_complete_t)write_bulk_callback, agg);
1873 ret = usb_submit_urb(agg->urb, GFP_ATOMIC);
1875 usb_autopm_put_interface_async(tp->intf);
1881 static u8 r8152_rx_csum(struct r8152 *tp, struct rx_desc *rx_desc)
1883 u8 checksum = CHECKSUM_NONE;
1886 if (!(tp->netdev->features & NETIF_F_RXCSUM))
1889 opts2 = le32_to_cpu(rx_desc->opts2);
1890 opts3 = le32_to_cpu(rx_desc->opts3);
1892 if (opts2 & RD_IPV4_CS) {
1894 checksum = CHECKSUM_NONE;
1895 else if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF))
1896 checksum = CHECKSUM_UNNECESSARY;
1897 else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF))
1898 checksum = CHECKSUM_UNNECESSARY;
1899 } else if (opts2 & RD_IPV6_CS) {
1900 if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF))
1901 checksum = CHECKSUM_UNNECESSARY;
1902 else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF))
1903 checksum = CHECKSUM_UNNECESSARY;
1910 static int rx_bottom(struct r8152 *tp, int budget)
1912 unsigned long flags;
1913 struct list_head *cursor, *next, rx_queue;
1914 int ret = 0, work_done = 0;
1915 struct napi_struct *napi = &tp->napi;
1917 if (!skb_queue_empty(&tp->rx_queue)) {
1918 while (work_done < budget) {
1919 struct sk_buff *skb = __skb_dequeue(&tp->rx_queue);
1920 struct net_device *netdev = tp->netdev;
1921 struct net_device_stats *stats = &netdev->stats;
1922 unsigned int pkt_len;
1928 napi_gro_receive(napi, skb);
1930 stats->rx_packets++;
1931 stats->rx_bytes += pkt_len;
1935 if (list_empty(&tp->rx_done))
1938 INIT_LIST_HEAD(&rx_queue);
1939 spin_lock_irqsave(&tp->rx_lock, flags);
1940 list_splice_init(&tp->rx_done, &rx_queue);
1941 spin_unlock_irqrestore(&tp->rx_lock, flags);
1943 list_for_each_safe(cursor, next, &rx_queue) {
1944 struct rx_desc *rx_desc;
1950 list_del_init(cursor);
1952 agg = list_entry(cursor, struct rx_agg, list);
1954 if (urb->actual_length < ETH_ZLEN)
1957 rx_desc = agg->head;
1958 rx_data = agg->head;
1959 len_used += sizeof(struct rx_desc);
1961 while (urb->actual_length > len_used) {
1962 struct net_device *netdev = tp->netdev;
1963 struct net_device_stats *stats = &netdev->stats;
1964 unsigned int pkt_len;
1965 struct sk_buff *skb;
1967 /* limite the skb numbers for rx_queue */
1968 if (unlikely(skb_queue_len(&tp->rx_queue) >= 1000))
1971 pkt_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK;
1972 if (pkt_len < ETH_ZLEN)
1975 len_used += pkt_len;
1976 if (urb->actual_length < len_used)
1979 pkt_len -= ETH_FCS_LEN;
1980 rx_data += sizeof(struct rx_desc);
1982 skb = napi_alloc_skb(napi, pkt_len);
1984 stats->rx_dropped++;
1988 skb->ip_summed = r8152_rx_csum(tp, rx_desc);
1989 memcpy(skb->data, rx_data, pkt_len);
1990 skb_put(skb, pkt_len);
1991 skb->protocol = eth_type_trans(skb, netdev);
1992 rtl_rx_vlan_tag(rx_desc, skb);
1993 if (work_done < budget) {
1994 napi_gro_receive(napi, skb);
1996 stats->rx_packets++;
1997 stats->rx_bytes += pkt_len;
1999 __skb_queue_tail(&tp->rx_queue, skb);
2003 rx_data = rx_agg_align(rx_data + pkt_len + ETH_FCS_LEN);
2004 rx_desc = (struct rx_desc *)rx_data;
2005 len_used = (int)(rx_data - (u8 *)agg->head);
2006 len_used += sizeof(struct rx_desc);
2011 ret = r8152_submit_rx(tp, agg, GFP_ATOMIC);
2013 urb->actual_length = 0;
2014 list_add_tail(&agg->list, next);
2018 if (!list_empty(&rx_queue)) {
2019 spin_lock_irqsave(&tp->rx_lock, flags);
2020 list_splice_tail(&rx_queue, &tp->rx_done);
2021 spin_unlock_irqrestore(&tp->rx_lock, flags);
2028 static void tx_bottom(struct r8152 *tp)
2035 if (skb_queue_empty(&tp->tx_queue))
2038 agg = r8152_get_tx_agg(tp);
2042 res = r8152_tx_agg_fill(tp, agg);
2044 struct net_device *netdev = tp->netdev;
2046 if (res == -ENODEV) {
2048 netif_device_detach(netdev);
2050 struct net_device_stats *stats = &netdev->stats;
2051 unsigned long flags;
2053 netif_warn(tp, tx_err, netdev,
2054 "failed tx_urb %d\n", res);
2055 stats->tx_dropped += agg->skb_num;
2057 spin_lock_irqsave(&tp->tx_lock, flags);
2058 list_add_tail(&agg->list, &tp->tx_free);
2059 spin_unlock_irqrestore(&tp->tx_lock, flags);
2065 static void bottom_half(struct r8152 *tp)
2067 if (test_bit(RTL8152_UNPLUG, &tp->flags))
2070 if (!test_bit(WORK_ENABLE, &tp->flags))
2073 /* When link down, the driver would cancel all bulks. */
2074 /* This avoid the re-submitting bulk */
2075 if (!netif_carrier_ok(tp->netdev))
2078 clear_bit(SCHEDULE_NAPI, &tp->flags);
2083 static int r8152_poll(struct napi_struct *napi, int budget)
2085 struct r8152 *tp = container_of(napi, struct r8152, napi);
2088 work_done = rx_bottom(tp, budget);
2091 if (work_done < budget) {
2092 if (!napi_complete_done(napi, work_done))
2094 if (!list_empty(&tp->rx_done))
2095 napi_schedule(napi);
2096 else if (!skb_queue_empty(&tp->tx_queue) &&
2097 !list_empty(&tp->tx_free))
2098 napi_schedule(napi);
2106 int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags)
2110 /* The rx would be stopped, so skip submitting */
2111 if (test_bit(RTL8152_UNPLUG, &tp->flags) ||
2112 !test_bit(WORK_ENABLE, &tp->flags) || !netif_carrier_ok(tp->netdev))
2115 usb_fill_bulk_urb(agg->urb, tp->udev, usb_rcvbulkpipe(tp->udev, 1),
2116 agg->head, agg_buf_sz,
2117 (usb_complete_t)read_bulk_callback, agg);
2119 ret = usb_submit_urb(agg->urb, mem_flags);
2120 if (ret == -ENODEV) {
2122 netif_device_detach(tp->netdev);
2124 struct urb *urb = agg->urb;
2125 unsigned long flags;
2127 urb->actual_length = 0;
2128 spin_lock_irqsave(&tp->rx_lock, flags);
2129 list_add_tail(&agg->list, &tp->rx_done);
2130 spin_unlock_irqrestore(&tp->rx_lock, flags);
2132 netif_err(tp, rx_err, tp->netdev,
2133 "Couldn't submit rx[%p], ret = %d\n", agg, ret);
2135 napi_schedule(&tp->napi);
2141 static void rtl_drop_queued_tx(struct r8152 *tp)
2143 struct net_device_stats *stats = &tp->netdev->stats;
2144 struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
2145 struct sk_buff *skb;
2147 if (skb_queue_empty(tx_queue))
2150 __skb_queue_head_init(&skb_head);
2151 spin_lock_bh(&tx_queue->lock);
2152 skb_queue_splice_init(tx_queue, &skb_head);
2153 spin_unlock_bh(&tx_queue->lock);
2155 while ((skb = __skb_dequeue(&skb_head))) {
2157 stats->tx_dropped++;
2161 static void rtl8152_tx_timeout(struct net_device *netdev)
2163 struct r8152 *tp = netdev_priv(netdev);
2165 netif_warn(tp, tx_err, netdev, "Tx timeout\n");
2167 usb_queue_reset_device(tp->intf);
2170 static void rtl8152_set_rx_mode(struct net_device *netdev)
2172 struct r8152 *tp = netdev_priv(netdev);
2174 if (netif_carrier_ok(netdev)) {
2175 set_bit(RTL8152_SET_RX_MODE, &tp->flags);
2176 schedule_delayed_work(&tp->schedule, 0);
2180 static void _rtl8152_set_rx_mode(struct net_device *netdev)
2182 struct r8152 *tp = netdev_priv(netdev);
2183 u32 mc_filter[2]; /* Multicast hash filter */
2187 netif_stop_queue(netdev);
2188 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2189 ocp_data &= ~RCR_ACPT_ALL;
2190 ocp_data |= RCR_AB | RCR_APM;
2192 if (netdev->flags & IFF_PROMISC) {
2193 /* Unconditionally log net taps. */
2194 netif_notice(tp, link, netdev, "Promiscuous mode enabled\n");
2195 ocp_data |= RCR_AM | RCR_AAP;
2196 mc_filter[1] = 0xffffffff;
2197 mc_filter[0] = 0xffffffff;
2198 } else if ((netdev_mc_count(netdev) > multicast_filter_limit) ||
2199 (netdev->flags & IFF_ALLMULTI)) {
2200 /* Too many to filter perfectly -- accept all multicasts. */
2202 mc_filter[1] = 0xffffffff;
2203 mc_filter[0] = 0xffffffff;
2205 struct netdev_hw_addr *ha;
2209 netdev_for_each_mc_addr(ha, netdev) {
2210 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
2212 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
2217 tmp[0] = __cpu_to_le32(swab32(mc_filter[1]));
2218 tmp[1] = __cpu_to_le32(swab32(mc_filter[0]));
2220 pla_ocp_write(tp, PLA_MAR, BYTE_EN_DWORD, sizeof(tmp), tmp);
2221 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2222 netif_wake_queue(netdev);
2225 static netdev_features_t
2226 rtl8152_features_check(struct sk_buff *skb, struct net_device *dev,
2227 netdev_features_t features)
2229 u32 mss = skb_shinfo(skb)->gso_size;
2230 int max_offset = mss ? GTTCPHO_MAX : TCPHO_MAX;
2231 int offset = skb_transport_offset(skb);
2233 if ((mss || skb->ip_summed == CHECKSUM_PARTIAL) && offset > max_offset)
2234 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
2235 else if ((skb->len + sizeof(struct tx_desc)) > agg_buf_sz)
2236 features &= ~NETIF_F_GSO_MASK;
2241 static netdev_tx_t rtl8152_start_xmit(struct sk_buff *skb,
2242 struct net_device *netdev)
2244 struct r8152 *tp = netdev_priv(netdev);
2246 skb_tx_timestamp(skb);
2248 skb_queue_tail(&tp->tx_queue, skb);
2250 if (!list_empty(&tp->tx_free)) {
2251 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
2252 set_bit(SCHEDULE_NAPI, &tp->flags);
2253 schedule_delayed_work(&tp->schedule, 0);
2255 usb_mark_last_busy(tp->udev);
2256 napi_schedule(&tp->napi);
2258 } else if (skb_queue_len(&tp->tx_queue) > tp->tx_qlen) {
2259 netif_stop_queue(netdev);
2262 return NETDEV_TX_OK;
2265 static void r8152b_reset_packet_filter(struct r8152 *tp)
2269 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC);
2270 ocp_data &= ~FMC_FCR_MCU_EN;
2271 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
2272 ocp_data |= FMC_FCR_MCU_EN;
2273 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
2276 static void rtl8152_nic_reset(struct r8152 *tp)
2280 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, CR_RST);
2282 for (i = 0; i < 1000; i++) {
2283 if (!(ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR) & CR_RST))
2285 usleep_range(100, 400);
2289 static void set_tx_qlen(struct r8152 *tp)
2291 struct net_device *netdev = tp->netdev;
2293 tp->tx_qlen = agg_buf_sz / (netdev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN +
2294 sizeof(struct tx_desc));
2297 static inline u8 rtl8152_get_speed(struct r8152 *tp)
2299 return ocp_read_byte(tp, MCU_TYPE_PLA, PLA_PHYSTATUS);
2302 static void rtl_set_eee_plus(struct r8152 *tp)
2307 speed = rtl8152_get_speed(tp);
2308 if (speed & _10bps) {
2309 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
2310 ocp_data |= EEEP_CR_EEEP_TX;
2311 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
2313 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
2314 ocp_data &= ~EEEP_CR_EEEP_TX;
2315 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
2319 static void rxdy_gated_en(struct r8152 *tp, bool enable)
2323 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1);
2325 ocp_data |= RXDY_GATED_EN;
2327 ocp_data &= ~RXDY_GATED_EN;
2328 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data);
2331 static int rtl_start_rx(struct r8152 *tp)
2335 INIT_LIST_HEAD(&tp->rx_done);
2336 for (i = 0; i < RTL8152_MAX_RX; i++) {
2337 INIT_LIST_HEAD(&tp->rx_info[i].list);
2338 ret = r8152_submit_rx(tp, &tp->rx_info[i], GFP_KERNEL);
2343 if (ret && ++i < RTL8152_MAX_RX) {
2344 struct list_head rx_queue;
2345 unsigned long flags;
2347 INIT_LIST_HEAD(&rx_queue);
2350 struct rx_agg *agg = &tp->rx_info[i++];
2351 struct urb *urb = agg->urb;
2353 urb->actual_length = 0;
2354 list_add_tail(&agg->list, &rx_queue);
2355 } while (i < RTL8152_MAX_RX);
2357 spin_lock_irqsave(&tp->rx_lock, flags);
2358 list_splice_tail(&rx_queue, &tp->rx_done);
2359 spin_unlock_irqrestore(&tp->rx_lock, flags);
2365 static int rtl_stop_rx(struct r8152 *tp)
2369 for (i = 0; i < RTL8152_MAX_RX; i++)
2370 usb_kill_urb(tp->rx_info[i].urb);
2372 while (!skb_queue_empty(&tp->rx_queue))
2373 dev_kfree_skb(__skb_dequeue(&tp->rx_queue));
2378 static inline void r8153b_rx_agg_chg_indicate(struct r8152 *tp)
2380 ocp_write_byte(tp, MCU_TYPE_USB, USB_UPT_RXDMA_OWN,
2381 OWN_UPDATE | OWN_CLEAR);
2384 static int rtl_enable(struct r8152 *tp)
2388 r8152b_reset_packet_filter(tp);
2390 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR);
2391 ocp_data |= CR_RE | CR_TE;
2392 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data);
2394 switch (tp->version) {
2397 r8153b_rx_agg_chg_indicate(tp);
2403 rxdy_gated_en(tp, false);
2408 static int rtl8152_enable(struct r8152 *tp)
2410 if (test_bit(RTL8152_UNPLUG, &tp->flags))
2414 rtl_set_eee_plus(tp);
2416 return rtl_enable(tp);
2419 static void r8153_set_rx_early_timeout(struct r8152 *tp)
2421 u32 ocp_data = tp->coalesce / 8;
2423 switch (tp->version) {
2428 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT,
2434 /* The RTL8153B uses USB_RX_EXTRA_AGGR_TMR for rx timeout
2435 * primarily. For USB_RX_EARLY_TIMEOUT, we fix it to 128ns.
2437 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT,
2439 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EXTRA_AGGR_TMR,
2448 static void r8153_set_rx_early_size(struct r8152 *tp)
2450 u32 ocp_data = agg_buf_sz - rx_reserved_size(tp->netdev->mtu);
2452 switch (tp->version) {
2457 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE,
2462 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE,
2471 static int rtl8153_enable(struct r8152 *tp)
2473 if (test_bit(RTL8152_UNPLUG, &tp->flags))
2477 rtl_set_eee_plus(tp);
2478 r8153_set_rx_early_timeout(tp);
2479 r8153_set_rx_early_size(tp);
2481 return rtl_enable(tp);
2484 static void rtl_disable(struct r8152 *tp)
2489 if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
2490 rtl_drop_queued_tx(tp);
2494 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2495 ocp_data &= ~RCR_ACPT_ALL;
2496 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2498 rtl_drop_queued_tx(tp);
2500 for (i = 0; i < RTL8152_MAX_TX; i++)
2501 usb_kill_urb(tp->tx_info[i].urb);
2503 rxdy_gated_en(tp, true);
2505 for (i = 0; i < 1000; i++) {
2506 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2507 if ((ocp_data & FIFO_EMPTY) == FIFO_EMPTY)
2509 usleep_range(1000, 2000);
2512 for (i = 0; i < 1000; i++) {
2513 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0) & TCR0_TX_EMPTY)
2515 usleep_range(1000, 2000);
2520 rtl8152_nic_reset(tp);
2523 static void r8152_power_cut_en(struct r8152 *tp, bool enable)
2527 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL);
2529 ocp_data |= POWER_CUT;
2531 ocp_data &= ~POWER_CUT;
2532 ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data);
2534 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS);
2535 ocp_data &= ~RESUME_INDICATE;
2536 ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data);
2539 static void rtl_rx_vlan_en(struct r8152 *tp, bool enable)
2543 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
2545 ocp_data |= CPCR_RX_VLAN;
2547 ocp_data &= ~CPCR_RX_VLAN;
2548 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
2551 static int rtl8152_set_features(struct net_device *dev,
2552 netdev_features_t features)
2554 netdev_features_t changed = features ^ dev->features;
2555 struct r8152 *tp = netdev_priv(dev);
2558 ret = usb_autopm_get_interface(tp->intf);
2562 mutex_lock(&tp->control);
2564 if (changed & NETIF_F_HW_VLAN_CTAG_RX) {
2565 if (features & NETIF_F_HW_VLAN_CTAG_RX)
2566 rtl_rx_vlan_en(tp, true);
2568 rtl_rx_vlan_en(tp, false);
2571 mutex_unlock(&tp->control);
2573 usb_autopm_put_interface(tp->intf);
2579 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
2581 static u32 __rtl_get_wol(struct r8152 *tp)
2586 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2587 if (ocp_data & LINK_ON_WAKE_EN)
2588 wolopts |= WAKE_PHY;
2590 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
2591 if (ocp_data & UWF_EN)
2592 wolopts |= WAKE_UCAST;
2593 if (ocp_data & BWF_EN)
2594 wolopts |= WAKE_BCAST;
2595 if (ocp_data & MWF_EN)
2596 wolopts |= WAKE_MCAST;
2598 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
2599 if (ocp_data & MAGIC_EN)
2600 wolopts |= WAKE_MAGIC;
2605 static void __rtl_set_wol(struct r8152 *tp, u32 wolopts)
2609 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
2611 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2612 ocp_data &= ~LINK_ON_WAKE_EN;
2613 if (wolopts & WAKE_PHY)
2614 ocp_data |= LINK_ON_WAKE_EN;
2615 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
2617 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
2618 ocp_data &= ~(UWF_EN | BWF_EN | MWF_EN);
2619 if (wolopts & WAKE_UCAST)
2621 if (wolopts & WAKE_BCAST)
2623 if (wolopts & WAKE_MCAST)
2625 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG5, ocp_data);
2627 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
2629 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
2630 ocp_data &= ~MAGIC_EN;
2631 if (wolopts & WAKE_MAGIC)
2632 ocp_data |= MAGIC_EN;
2633 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL, ocp_data);
2635 if (wolopts & WAKE_ANY)
2636 device_set_wakeup_enable(&tp->udev->dev, true);
2638 device_set_wakeup_enable(&tp->udev->dev, false);
2641 static void r8153_mac_clk_spd(struct r8152 *tp, bool enable)
2643 /* MAC clock speed down */
2645 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL,
2647 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2,
2649 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3,
2650 PKT_AVAIL_SPDWN_EN | SUSPEND_SPDWN_EN |
2651 U1U2_SPDWN_EN | L1_SPDWN_EN);
2652 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4,
2653 PWRSAVE_SPDWN_EN | RXDV_SPDWN_EN | TX10MIDLE_EN |
2654 TP100_SPDWN_EN | TP500_SPDWN_EN | EEE_SPDWN_EN |
2657 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, 0);
2658 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, 0);
2659 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, 0);
2660 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, 0);
2664 static void r8153_u1u2en(struct r8152 *tp, bool enable)
2669 memset(u1u2, 0xff, sizeof(u1u2));
2671 memset(u1u2, 0x00, sizeof(u1u2));
2673 usb_ocp_write(tp, USB_TOLERANCE, BYTE_EN_SIX_BYTES, sizeof(u1u2), u1u2);
2676 static void r8153b_u1u2en(struct r8152 *tp, bool enable)
2680 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_LPM_CONFIG);
2682 ocp_data |= LPM_U1U2_EN;
2684 ocp_data &= ~LPM_U1U2_EN;
2686 ocp_write_word(tp, MCU_TYPE_USB, USB_LPM_CONFIG, ocp_data);
2689 static void r8153_u2p3en(struct r8152 *tp, bool enable)
2693 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL);
2695 ocp_data |= U2P3_ENABLE;
2697 ocp_data &= ~U2P3_ENABLE;
2698 ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data);
2701 static void r8153b_ups_flags_w1w0(struct r8152 *tp, u32 set, u32 clear)
2705 ocp_data = ocp_read_dword(tp, MCU_TYPE_USB, USB_UPS_FLAGS);
2708 ocp_write_dword(tp, MCU_TYPE_USB, USB_UPS_FLAGS, ocp_data);
2711 static void r8153b_green_en(struct r8152 *tp, bool enable)
2716 sram_write(tp, 0x8045, 0); /* 10M abiq&ldvbias */
2717 sram_write(tp, 0x804d, 0x1222); /* 100M short abiq&ldvbias */
2718 sram_write(tp, 0x805d, 0x0022); /* 1000M short abiq&ldvbias */
2720 sram_write(tp, 0x8045, 0x2444); /* 10M abiq&ldvbias */
2721 sram_write(tp, 0x804d, 0x2444); /* 100M short abiq&ldvbias */
2722 sram_write(tp, 0x805d, 0x2444); /* 1000M short abiq&ldvbias */
2725 data = sram_read(tp, SRAM_GREEN_CFG);
2726 data |= GREEN_ETH_EN;
2727 sram_write(tp, SRAM_GREEN_CFG, data);
2729 r8153b_ups_flags_w1w0(tp, UPS_FLAGS_EN_GREEN, 0);
2732 static u16 r8153_phy_status(struct r8152 *tp, u16 desired)
2737 for (i = 0; i < 500; i++) {
2738 data = ocp_reg_read(tp, OCP_PHY_STATUS);
2739 data &= PHY_STAT_MASK;
2741 if (data == desired)
2743 } else if (data == PHY_STAT_LAN_ON || data == PHY_STAT_PWRDN ||
2744 data == PHY_STAT_EXT_INIT) {
2754 static void r8153b_ups_en(struct r8152 *tp, bool enable)
2756 u32 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_POWER_CUT);
2759 ocp_data |= UPS_EN | USP_PREWAKE | PHASE2_EN;
2760 ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
2762 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, 0xcfff);
2764 ocp_write_byte(tp, MCU_TYPE_USB, 0xcfff, ocp_data);
2768 ocp_data &= ~(UPS_EN | USP_PREWAKE);
2769 ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
2771 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, 0xcfff);
2772 ocp_data &= ~BIT(0);
2773 ocp_write_byte(tp, MCU_TYPE_USB, 0xcfff, ocp_data);
2775 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
2776 ocp_data &= ~PCUT_STATUS;
2777 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
2779 data = r8153_phy_status(tp, 0);
2782 case PHY_STAT_PWRDN:
2783 case PHY_STAT_EXT_INIT:
2785 test_bit(GREEN_ETHERNET, &tp->flags));
2787 data = r8152_mdio_read(tp, MII_BMCR);
2788 data &= ~BMCR_PDOWN;
2790 r8152_mdio_write(tp, MII_BMCR, data);
2792 data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
2796 if (data != PHY_STAT_LAN_ON)
2797 netif_warn(tp, link, tp->netdev,
2804 static void r8153_power_cut_en(struct r8152 *tp, bool enable)
2808 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT);
2810 ocp_data |= PWR_EN | PHASE2_EN;
2812 ocp_data &= ~(PWR_EN | PHASE2_EN);
2813 ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
2815 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
2816 ocp_data &= ~PCUT_STATUS;
2817 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
2820 static void r8153b_power_cut_en(struct r8152 *tp, bool enable)
2824 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT);
2826 ocp_data |= PWR_EN | PHASE2_EN;
2828 ocp_data &= ~PWR_EN;
2829 ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
2831 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
2832 ocp_data &= ~PCUT_STATUS;
2833 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
2836 static void r8153_queue_wake(struct r8152 *tp, bool enable)
2840 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_INDICATE_FALG);
2842 ocp_data |= UPCOMING_RUNTIME_D3;
2844 ocp_data &= ~UPCOMING_RUNTIME_D3;
2845 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_INDICATE_FALG, ocp_data);
2847 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_SUSPEND_FLAG);
2848 ocp_data &= ~LINK_CHG_EVENT;
2849 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_SUSPEND_FLAG, ocp_data);
2851 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS);
2852 ocp_data &= ~LINK_CHANGE_FLAG;
2853 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data);
2856 static bool rtl_can_wakeup(struct r8152 *tp)
2858 struct usb_device *udev = tp->udev;
2860 return (udev->actconfig->desc.bmAttributes & USB_CONFIG_ATT_WAKEUP);
2863 static void rtl_runtime_suspend_enable(struct r8152 *tp, bool enable)
2868 __rtl_set_wol(tp, WAKE_ANY);
2870 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
2872 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2873 ocp_data |= LINK_OFF_WAKE_EN;
2874 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
2876 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
2880 __rtl_set_wol(tp, tp->saved_wolopts);
2882 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
2884 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2885 ocp_data &= ~LINK_OFF_WAKE_EN;
2886 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
2888 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
2892 static void rtl8153_runtime_enable(struct r8152 *tp, bool enable)
2895 r8153_u1u2en(tp, false);
2896 r8153_u2p3en(tp, false);
2897 r8153_mac_clk_spd(tp, true);
2898 rtl_runtime_suspend_enable(tp, true);
2900 rtl_runtime_suspend_enable(tp, false);
2901 r8153_mac_clk_spd(tp, false);
2903 switch (tp->version) {
2910 r8153_u2p3en(tp, true);
2914 r8153_u1u2en(tp, true);
2918 static void rtl8153b_runtime_enable(struct r8152 *tp, bool enable)
2921 r8153_queue_wake(tp, true);
2922 r8153b_u1u2en(tp, false);
2923 r8153_u2p3en(tp, false);
2924 rtl_runtime_suspend_enable(tp, true);
2925 r8153b_ups_en(tp, true);
2927 r8153b_ups_en(tp, false);
2928 r8153_queue_wake(tp, false);
2929 rtl_runtime_suspend_enable(tp, false);
2930 r8153_u2p3en(tp, true);
2931 r8153b_u1u2en(tp, true);
2935 static void r8153_teredo_off(struct r8152 *tp)
2939 switch (tp->version) {
2947 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
2948 ocp_data &= ~(TEREDO_SEL | TEREDO_RS_EVENT_MASK |
2950 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
2955 /* The bit 0 ~ 7 are relative with teredo settings. They are
2956 * W1C (write 1 to clear), so set all 1 to disable it.
2958 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, 0xff);
2965 ocp_write_word(tp, MCU_TYPE_PLA, PLA_WDT6_CTRL, WDT6_SET_MODE);
2966 ocp_write_word(tp, MCU_TYPE_PLA, PLA_REALWOW_TIMER, 0);
2967 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TEREDO_TIMER, 0);
2970 static void rtl_reset_bmu(struct r8152 *tp)
2974 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_BMU_RESET);
2975 ocp_data &= ~(BMU_RESET_EP_IN | BMU_RESET_EP_OUT);
2976 ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data);
2977 ocp_data |= BMU_RESET_EP_IN | BMU_RESET_EP_OUT;
2978 ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data);
2981 static void r8152_aldps_en(struct r8152 *tp, bool enable)
2984 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPWRSAVE | ENPDNPS |
2985 LINKENA | DIS_SDSAVE);
2987 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPDNPS | LINKENA |
2993 static inline void r8152_mmd_indirect(struct r8152 *tp, u16 dev, u16 reg)
2995 ocp_reg_write(tp, OCP_EEE_AR, FUN_ADDR | dev);
2996 ocp_reg_write(tp, OCP_EEE_DATA, reg);
2997 ocp_reg_write(tp, OCP_EEE_AR, FUN_DATA | dev);
3000 static u16 r8152_mmd_read(struct r8152 *tp, u16 dev, u16 reg)
3004 r8152_mmd_indirect(tp, dev, reg);
3005 data = ocp_reg_read(tp, OCP_EEE_DATA);
3006 ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
3011 static void r8152_mmd_write(struct r8152 *tp, u16 dev, u16 reg, u16 data)
3013 r8152_mmd_indirect(tp, dev, reg);
3014 ocp_reg_write(tp, OCP_EEE_DATA, data);
3015 ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
3018 static void r8152_eee_en(struct r8152 *tp, bool enable)
3020 u16 config1, config2, config3;
3023 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
3024 config1 = ocp_reg_read(tp, OCP_EEE_CONFIG1) & ~sd_rise_time_mask;
3025 config2 = ocp_reg_read(tp, OCP_EEE_CONFIG2);
3026 config3 = ocp_reg_read(tp, OCP_EEE_CONFIG3) & ~fast_snr_mask;
3029 ocp_data |= EEE_RX_EN | EEE_TX_EN;
3030 config1 |= EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN | RX_QUIET_EN;
3031 config1 |= sd_rise_time(1);
3032 config2 |= RG_DACQUIET_EN | RG_LDVQUIET_EN;
3033 config3 |= fast_snr(42);
3035 ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
3036 config1 &= ~(EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN |
3038 config1 |= sd_rise_time(7);
3039 config2 &= ~(RG_DACQUIET_EN | RG_LDVQUIET_EN);
3040 config3 |= fast_snr(511);
3043 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
3044 ocp_reg_write(tp, OCP_EEE_CONFIG1, config1);
3045 ocp_reg_write(tp, OCP_EEE_CONFIG2, config2);
3046 ocp_reg_write(tp, OCP_EEE_CONFIG3, config3);
3049 static void r8152b_enable_eee(struct r8152 *tp)
3051 r8152_eee_en(tp, true);
3052 r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, MDIO_EEE_100TX);
3055 static void r8152b_enable_fc(struct r8152 *tp)
3059 anar = r8152_mdio_read(tp, MII_ADVERTISE);
3060 anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
3061 r8152_mdio_write(tp, MII_ADVERTISE, anar);
3064 static void rtl8152_disable(struct r8152 *tp)
3066 r8152_aldps_en(tp, false);
3068 r8152_aldps_en(tp, true);
3071 static void r8152b_hw_phy_cfg(struct r8152 *tp)
3073 r8152b_enable_eee(tp);
3074 r8152_aldps_en(tp, true);
3075 r8152b_enable_fc(tp);
3077 set_bit(PHY_RESET, &tp->flags);
3080 static void r8152b_exit_oob(struct r8152 *tp)
3085 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
3086 ocp_data &= ~RCR_ACPT_ALL;
3087 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
3089 rxdy_gated_en(tp, true);
3090 r8153_teredo_off(tp);
3091 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
3092 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00);
3094 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3095 ocp_data &= ~NOW_IS_OOB;
3096 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
3098 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
3099 ocp_data &= ~MCU_BORW_EN;
3100 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
3102 for (i = 0; i < 1000; i++) {
3103 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3104 if (ocp_data & LINK_LIST_READY)
3106 usleep_range(1000, 2000);
3109 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
3110 ocp_data |= RE_INIT_LL;
3111 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
3113 for (i = 0; i < 1000; i++) {
3114 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3115 if (ocp_data & LINK_LIST_READY)
3117 usleep_range(1000, 2000);
3120 rtl8152_nic_reset(tp);
3122 /* rx share fifo credit full threshold */
3123 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
3125 if (tp->udev->speed == USB_SPEED_FULL ||
3126 tp->udev->speed == USB_SPEED_LOW) {
3127 /* rx share fifo credit near full threshold */
3128 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
3130 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
3133 /* rx share fifo credit near full threshold */
3134 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
3136 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
3140 /* TX share fifo free credit full threshold */
3141 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL);
3143 ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD);
3144 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_HIGH);
3145 ocp_write_dword(tp, MCU_TYPE_USB, USB_TX_DMA,
3146 TEST_MODE_DISABLE | TX_SIZE_ADJUST1);
3148 rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
3150 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
3152 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
3153 ocp_data |= TCR0_AUTO_FIFO;
3154 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
3157 static void r8152b_enter_oob(struct r8152 *tp)
3162 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3163 ocp_data &= ~NOW_IS_OOB;
3164 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
3166 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB);
3167 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB);
3168 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB);
3172 for (i = 0; i < 1000; i++) {
3173 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3174 if (ocp_data & LINK_LIST_READY)
3176 usleep_range(1000, 2000);
3179 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
3180 ocp_data |= RE_INIT_LL;
3181 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
3183 for (i = 0; i < 1000; i++) {
3184 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3185 if (ocp_data & LINK_LIST_READY)
3187 usleep_range(1000, 2000);
3190 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
3192 rtl_rx_vlan_en(tp, true);
3194 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BDC_CR);
3195 ocp_data |= ALDPS_PROXY_MODE;
3196 ocp_write_word(tp, MCU_TYPE_PLA, PLA_BDC_CR, ocp_data);
3198 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3199 ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
3200 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
3202 rxdy_gated_en(tp, false);
3204 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
3205 ocp_data |= RCR_APM | RCR_AM | RCR_AB;
3206 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
3209 static int r8153_patch_request(struct r8152 *tp, bool request)
3214 data = ocp_reg_read(tp, OCP_PHY_PATCH_CMD);
3216 data |= PATCH_REQUEST;
3218 data &= ~PATCH_REQUEST;
3219 ocp_reg_write(tp, OCP_PHY_PATCH_CMD, data);
3221 for (i = 0; request && i < 5000; i++) {
3222 usleep_range(1000, 2000);
3223 if (ocp_reg_read(tp, OCP_PHY_PATCH_STAT) & PATCH_READY)
3227 if (request && !(ocp_reg_read(tp, OCP_PHY_PATCH_STAT) & PATCH_READY)) {
3228 netif_err(tp, drv, tp->netdev, "patch request fail\n");
3229 r8153_patch_request(tp, false);
3236 static void r8153_aldps_en(struct r8152 *tp, bool enable)
3240 data = ocp_reg_read(tp, OCP_POWER_CFG);
3243 ocp_reg_write(tp, OCP_POWER_CFG, data);
3248 ocp_reg_write(tp, OCP_POWER_CFG, data);
3249 for (i = 0; i < 20; i++) {
3250 usleep_range(1000, 2000);
3251 if (ocp_read_word(tp, MCU_TYPE_PLA, 0xe000) & 0x0100)
3257 static void r8153b_aldps_en(struct r8152 *tp, bool enable)
3259 r8153_aldps_en(tp, enable);
3262 r8153b_ups_flags_w1w0(tp, UPS_FLAGS_EN_ALDPS, 0);
3264 r8153b_ups_flags_w1w0(tp, 0, UPS_FLAGS_EN_ALDPS);
3267 static void r8153_eee_en(struct r8152 *tp, bool enable)
3272 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
3273 config = ocp_reg_read(tp, OCP_EEE_CFG);
3276 ocp_data |= EEE_RX_EN | EEE_TX_EN;
3279 ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
3280 config &= ~EEE10_EN;
3283 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
3284 ocp_reg_write(tp, OCP_EEE_CFG, config);
3287 static void r8153b_eee_en(struct r8152 *tp, bool enable)
3289 r8153_eee_en(tp, enable);
3292 r8153b_ups_flags_w1w0(tp, UPS_FLAGS_EN_EEE, 0);
3294 r8153b_ups_flags_w1w0(tp, 0, UPS_FLAGS_EN_EEE);
3297 static void r8153b_enable_fc(struct r8152 *tp)
3299 r8152b_enable_fc(tp);
3300 r8153b_ups_flags_w1w0(tp, UPS_FLAGS_EN_FLOW_CTR, 0);
3303 static void r8153_hw_phy_cfg(struct r8152 *tp)
3308 /* disable ALDPS before updating the PHY parameters */
3309 r8153_aldps_en(tp, false);
3311 /* disable EEE before updating the PHY parameters */
3312 r8153_eee_en(tp, false);
3313 ocp_reg_write(tp, OCP_EEE_ADV, 0);
3315 if (tp->version == RTL_VER_03) {
3316 data = ocp_reg_read(tp, OCP_EEE_CFG);
3317 data &= ~CTAP_SHORT_EN;
3318 ocp_reg_write(tp, OCP_EEE_CFG, data);
3321 data = ocp_reg_read(tp, OCP_POWER_CFG);
3322 data |= EEE_CLKDIV_EN;
3323 ocp_reg_write(tp, OCP_POWER_CFG, data);
3325 data = ocp_reg_read(tp, OCP_DOWN_SPEED);
3326 data |= EN_10M_BGOFF;
3327 ocp_reg_write(tp, OCP_DOWN_SPEED, data);
3328 data = ocp_reg_read(tp, OCP_POWER_CFG);
3329 data |= EN_10M_PLLOFF;
3330 ocp_reg_write(tp, OCP_POWER_CFG, data);
3331 sram_write(tp, SRAM_IMPEDANCE, 0x0b13);
3333 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
3334 ocp_data |= PFM_PWM_SWITCH;
3335 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
3337 /* Enable LPF corner auto tune */
3338 sram_write(tp, SRAM_LPF_CFG, 0xf70f);
3340 /* Adjust 10M Amplitude */
3341 sram_write(tp, SRAM_10M_AMP1, 0x00af);
3342 sram_write(tp, SRAM_10M_AMP2, 0x0208);
3344 r8153_eee_en(tp, true);
3345 ocp_reg_write(tp, OCP_EEE_ADV, MDIO_EEE_1000T | MDIO_EEE_100TX);
3347 r8153_aldps_en(tp, true);
3348 r8152b_enable_fc(tp);
3350 switch (tp->version) {
3357 r8153_u2p3en(tp, true);
3361 set_bit(PHY_RESET, &tp->flags);
3364 static u32 r8152_efuse_read(struct r8152 *tp, u8 addr)
3368 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EFUSE_CMD, EFUSE_READ_CMD | addr);
3369 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EFUSE_CMD);
3370 ocp_data = (ocp_data & EFUSE_DATA_BIT16) << 9; /* data of bit16 */
3371 ocp_data |= ocp_read_word(tp, MCU_TYPE_PLA, PLA_EFUSE_DATA);
3376 static void r8153b_hw_phy_cfg(struct r8152 *tp)
3378 u32 ocp_data, ups_flags = 0;
3381 /* disable ALDPS before updating the PHY parameters */
3382 r8153b_aldps_en(tp, false);
3384 /* disable EEE before updating the PHY parameters */
3385 r8153b_eee_en(tp, false);
3386 ocp_reg_write(tp, OCP_EEE_ADV, 0);
3388 r8153b_green_en(tp, test_bit(GREEN_ETHERNET, &tp->flags));
3390 data = sram_read(tp, SRAM_GREEN_CFG);
3392 sram_write(tp, SRAM_GREEN_CFG, data);
3393 data = ocp_reg_read(tp, OCP_NCTL_CFG);
3394 data |= PGA_RETURN_EN;
3395 ocp_reg_write(tp, OCP_NCTL_CFG, data);
3397 /* ADC Bias Calibration:
3398 * read efuse offset 0x7d to get a 17-bit data. Remove the dummy/fake
3399 * bit (bit3) to rebuild the real 16-bit data. Write the data to the
3402 ocp_data = r8152_efuse_read(tp, 0x7d);
3403 data = (u16)(((ocp_data & 0x1fff0) >> 1) | (ocp_data & 0x7));
3405 ocp_reg_write(tp, OCP_ADC_IOFFSET, data);
3407 /* ups mode tx-link-pulse timing adjustment:
3408 * rg_saw_cnt = OCP reg 0xC426 Bit[13:0]
3409 * swr_cnt_1ms_ini = 16000000 / rg_saw_cnt
3411 ocp_data = ocp_reg_read(tp, 0xc426);
3414 u32 swr_cnt_1ms_ini;
3416 swr_cnt_1ms_ini = (16000000 / ocp_data) & SAW_CNT_1MS_MASK;
3417 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CFG);
3418 ocp_data = (ocp_data & ~SAW_CNT_1MS_MASK) | swr_cnt_1ms_ini;
3419 ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CFG, ocp_data);
3422 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
3423 ocp_data |= PFM_PWM_SWITCH;
3424 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
3427 if (!r8153_patch_request(tp, true)) {
3428 data = ocp_reg_read(tp, OCP_POWER_CFG);
3429 data |= EEE_CLKDIV_EN;
3430 ocp_reg_write(tp, OCP_POWER_CFG, data);
3432 data = ocp_reg_read(tp, OCP_DOWN_SPEED);
3433 data |= EN_EEE_CMODE | EN_EEE_1000 | EN_10M_CLKDIV;
3434 ocp_reg_write(tp, OCP_DOWN_SPEED, data);
3436 ocp_reg_write(tp, OCP_SYSCLK_CFG, 0);
3437 ocp_reg_write(tp, OCP_SYSCLK_CFG, clk_div_expo(5));
3439 ups_flags |= UPS_FLAGS_EN_10M_CKDIV | UPS_FLAGS_250M_CKDIV |
3440 UPS_FLAGS_EN_EEE_CKDIV | UPS_FLAGS_EEE_CMOD_LV_EN |
3441 UPS_FLAGS_EEE_PLLOFF_GIGA;
3443 r8153_patch_request(tp, false);
3446 r8153b_ups_flags_w1w0(tp, ups_flags, 0);
3448 r8153b_eee_en(tp, true);
3449 ocp_reg_write(tp, OCP_EEE_ADV, MDIO_EEE_1000T | MDIO_EEE_100TX);
3451 r8153b_aldps_en(tp, true);
3452 r8153b_enable_fc(tp);
3453 r8153_u2p3en(tp, true);
3455 set_bit(PHY_RESET, &tp->flags);
3458 static void r8153_first_init(struct r8152 *tp)
3463 r8153_mac_clk_spd(tp, false);
3464 rxdy_gated_en(tp, true);
3465 r8153_teredo_off(tp);
3467 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
3468 ocp_data &= ~RCR_ACPT_ALL;
3469 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
3471 rtl8152_nic_reset(tp);
3474 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3475 ocp_data &= ~NOW_IS_OOB;
3476 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
3478 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
3479 ocp_data &= ~MCU_BORW_EN;
3480 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
3482 for (i = 0; i < 1000; i++) {
3483 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3484 if (ocp_data & LINK_LIST_READY)
3486 usleep_range(1000, 2000);
3489 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
3490 ocp_data |= RE_INIT_LL;
3491 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
3493 for (i = 0; i < 1000; i++) {
3494 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3495 if (ocp_data & LINK_LIST_READY)
3497 usleep_range(1000, 2000);
3500 rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
3502 ocp_data = tp->netdev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN;
3503 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, ocp_data);
3504 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_JUMBO);
3506 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
3507 ocp_data |= TCR0_AUTO_FIFO;
3508 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
3510 rtl8152_nic_reset(tp);
3512 /* rx share fifo credit full threshold */
3513 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
3514 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL);
3515 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL);
3516 /* TX share fifo free credit full threshold */
3517 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2);
3520 static void r8153_enter_oob(struct r8152 *tp)
3525 r8153_mac_clk_spd(tp, true);
3527 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3528 ocp_data &= ~NOW_IS_OOB;
3529 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
3534 for (i = 0; i < 1000; i++) {
3535 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3536 if (ocp_data & LINK_LIST_READY)
3538 usleep_range(1000, 2000);
3541 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
3542 ocp_data |= RE_INIT_LL;
3543 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
3545 for (i = 0; i < 1000; i++) {
3546 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3547 if (ocp_data & LINK_LIST_READY)
3549 usleep_range(1000, 2000);
3552 ocp_data = tp->netdev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN;
3553 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, ocp_data);
3555 switch (tp->version) {
3560 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
3561 ocp_data &= ~TEREDO_WAKE_MASK;
3562 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
3567 /* Clear teredo wake event. bit[15:8] is the teredo wakeup
3568 * type. Set it to zero. bits[7:0] are the W1C bits about
3569 * the events. Set them to all 1 to clear them.
3571 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_WAKE_BASE, 0x00ff);
3578 rtl_rx_vlan_en(tp, true);
3580 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BDC_CR);
3581 ocp_data |= ALDPS_PROXY_MODE;
3582 ocp_write_word(tp, MCU_TYPE_PLA, PLA_BDC_CR, ocp_data);
3584 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3585 ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
3586 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
3588 rxdy_gated_en(tp, false);
3590 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
3591 ocp_data |= RCR_APM | RCR_AM | RCR_AB;
3592 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
3595 static void rtl8153_disable(struct r8152 *tp)
3597 r8153_aldps_en(tp, false);
3600 r8153_aldps_en(tp, true);
3603 static void rtl8153b_disable(struct r8152 *tp)
3605 r8153b_aldps_en(tp, false);
3608 r8153b_aldps_en(tp, true);
3611 static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u16 speed, u8 duplex)
3613 u16 bmcr, anar, gbcr;
3614 enum spd_duplex speed_duplex;
3617 anar = r8152_mdio_read(tp, MII_ADVERTISE);
3618 anar &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
3619 ADVERTISE_100HALF | ADVERTISE_100FULL);
3620 if (tp->mii.supports_gmii) {
3621 gbcr = r8152_mdio_read(tp, MII_CTRL1000);
3622 gbcr &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
3627 if (autoneg == AUTONEG_DISABLE) {
3628 if (speed == SPEED_10) {
3630 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
3631 speed_duplex = FORCE_10M_HALF;
3632 } else if (speed == SPEED_100) {
3633 bmcr = BMCR_SPEED100;
3634 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
3635 speed_duplex = FORCE_100M_HALF;
3636 } else if (speed == SPEED_1000 && tp->mii.supports_gmii) {
3637 bmcr = BMCR_SPEED1000;
3638 gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
3639 speed_duplex = NWAY_1000M_FULL;
3645 if (duplex == DUPLEX_FULL) {
3646 bmcr |= BMCR_FULLDPLX;
3647 if (speed != SPEED_1000)
3651 if (speed == SPEED_10) {
3652 if (duplex == DUPLEX_FULL) {
3653 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
3654 speed_duplex = NWAY_10M_FULL;
3656 anar |= ADVERTISE_10HALF;
3657 speed_duplex = NWAY_10M_HALF;
3659 } else if (speed == SPEED_100) {
3660 if (duplex == DUPLEX_FULL) {
3661 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
3662 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
3663 speed_duplex = NWAY_100M_FULL;
3665 anar |= ADVERTISE_10HALF;
3666 anar |= ADVERTISE_100HALF;
3667 speed_duplex = NWAY_100M_HALF;
3669 } else if (speed == SPEED_1000 && tp->mii.supports_gmii) {
3670 if (duplex == DUPLEX_FULL) {
3671 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
3672 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
3673 gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
3675 anar |= ADVERTISE_10HALF;
3676 anar |= ADVERTISE_100HALF;
3677 gbcr |= ADVERTISE_1000HALF;
3679 speed_duplex = NWAY_1000M_FULL;
3685 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
3688 if (test_and_clear_bit(PHY_RESET, &tp->flags))
3691 if (tp->mii.supports_gmii)
3692 r8152_mdio_write(tp, MII_CTRL1000, gbcr);
3694 r8152_mdio_write(tp, MII_ADVERTISE, anar);
3695 r8152_mdio_write(tp, MII_BMCR, bmcr);
3697 switch (tp->version) {
3700 r8153b_ups_flags_w1w0(tp, ups_flags_speed(speed_duplex),
3701 UPS_FLAGS_SPEED_MASK);
3708 if (bmcr & BMCR_RESET) {
3711 for (i = 0; i < 50; i++) {
3713 if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0)
3722 static void rtl8152_up(struct r8152 *tp)
3724 if (test_bit(RTL8152_UNPLUG, &tp->flags))
3727 r8152_aldps_en(tp, false);
3728 r8152b_exit_oob(tp);
3729 r8152_aldps_en(tp, true);
3732 static void rtl8152_down(struct r8152 *tp)
3734 if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
3735 rtl_drop_queued_tx(tp);
3739 r8152_power_cut_en(tp, false);
3740 r8152_aldps_en(tp, false);
3741 r8152b_enter_oob(tp);
3742 r8152_aldps_en(tp, true);
3745 static void rtl8153_up(struct r8152 *tp)
3747 if (test_bit(RTL8152_UNPLUG, &tp->flags))
3750 r8153_u1u2en(tp, false);
3751 r8153_u2p3en(tp, false);
3752 r8153_aldps_en(tp, false);
3753 r8153_first_init(tp);
3754 r8153_aldps_en(tp, true);
3756 switch (tp->version) {
3763 r8153_u2p3en(tp, true);
3767 r8153_u1u2en(tp, true);
3770 static void rtl8153_down(struct r8152 *tp)
3772 if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
3773 rtl_drop_queued_tx(tp);
3777 r8153_u1u2en(tp, false);
3778 r8153_u2p3en(tp, false);
3779 r8153_power_cut_en(tp, false);
3780 r8153_aldps_en(tp, false);
3781 r8153_enter_oob(tp);
3782 r8153_aldps_en(tp, true);
3785 static void rtl8153b_up(struct r8152 *tp)
3787 if (test_bit(RTL8152_UNPLUG, &tp->flags))
3790 r8153b_u1u2en(tp, false);
3791 r8153_u2p3en(tp, false);
3792 r8153b_aldps_en(tp, false);
3794 r8153_first_init(tp);
3795 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_B);
3797 r8153b_aldps_en(tp, true);
3798 r8153_u2p3en(tp, true);
3799 r8153b_u1u2en(tp, true);
3802 static void rtl8153b_down(struct r8152 *tp)
3804 if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
3805 rtl_drop_queued_tx(tp);
3809 r8153b_u1u2en(tp, false);
3810 r8153_u2p3en(tp, false);
3811 r8153b_power_cut_en(tp, false);
3812 r8153b_aldps_en(tp, false);
3813 r8153_enter_oob(tp);
3814 r8153b_aldps_en(tp, true);
3817 static bool rtl8152_in_nway(struct r8152 *tp)
3821 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, 0x2000);
3822 tp->ocp_base = 0x2000;
3823 ocp_write_byte(tp, MCU_TYPE_PLA, 0xb014, 0x4c); /* phy state */
3824 nway_state = ocp_read_word(tp, MCU_TYPE_PLA, 0xb01a);
3826 /* bit 15: TXDIS_STATE, bit 14: ABD_STATE */
3827 if (nway_state & 0xc000)
3833 static bool rtl8153_in_nway(struct r8152 *tp)
3835 u16 phy_state = ocp_reg_read(tp, OCP_PHY_STATE) & 0xff;
3837 if (phy_state == TXDIS_STATE || phy_state == ABD_STATE)
3843 static void set_carrier(struct r8152 *tp)
3845 struct net_device *netdev = tp->netdev;
3846 struct napi_struct *napi = &tp->napi;
3849 speed = rtl8152_get_speed(tp);
3851 if (speed & LINK_STATUS) {
3852 if (!netif_carrier_ok(netdev)) {
3853 tp->rtl_ops.enable(tp);
3854 netif_stop_queue(netdev);
3856 netif_carrier_on(netdev);
3858 clear_bit(RTL8152_SET_RX_MODE, &tp->flags);
3859 _rtl8152_set_rx_mode(netdev);
3860 napi_enable(&tp->napi);
3861 netif_wake_queue(netdev);
3862 netif_info(tp, link, netdev, "carrier on\n");
3863 } else if (netif_queue_stopped(netdev) &&
3864 skb_queue_len(&tp->tx_queue) < tp->tx_qlen) {
3865 netif_wake_queue(netdev);
3868 if (netif_carrier_ok(netdev)) {
3869 netif_carrier_off(netdev);
3871 tp->rtl_ops.disable(tp);
3873 netif_info(tp, link, netdev, "carrier off\n");
3878 static void rtl_work_func_t(struct work_struct *work)
3880 struct r8152 *tp = container_of(work, struct r8152, schedule.work);
3882 /* If the device is unplugged or !netif_running(), the workqueue
3883 * doesn't need to wake the device, and could return directly.
3885 if (test_bit(RTL8152_UNPLUG, &tp->flags) || !netif_running(tp->netdev))
3888 if (usb_autopm_get_interface(tp->intf) < 0)
3891 if (!test_bit(WORK_ENABLE, &tp->flags))
3894 if (!mutex_trylock(&tp->control)) {
3895 schedule_delayed_work(&tp->schedule, 0);
3899 if (test_and_clear_bit(RTL8152_LINK_CHG, &tp->flags))
3902 if (test_and_clear_bit(RTL8152_SET_RX_MODE, &tp->flags))
3903 _rtl8152_set_rx_mode(tp->netdev);
3905 /* don't schedule napi before linking */
3906 if (test_and_clear_bit(SCHEDULE_NAPI, &tp->flags) &&
3907 netif_carrier_ok(tp->netdev))
3908 napi_schedule(&tp->napi);
3910 mutex_unlock(&tp->control);
3913 usb_autopm_put_interface(tp->intf);
3916 static void rtl_hw_phy_work_func_t(struct work_struct *work)
3918 struct r8152 *tp = container_of(work, struct r8152, hw_phy_work.work);
3920 if (test_bit(RTL8152_UNPLUG, &tp->flags))
3923 if (usb_autopm_get_interface(tp->intf) < 0)
3926 mutex_lock(&tp->control);
3928 tp->rtl_ops.hw_phy_cfg(tp);
3930 rtl8152_set_speed(tp, tp->autoneg, tp->speed, tp->duplex);
3932 mutex_unlock(&tp->control);
3934 usb_autopm_put_interface(tp->intf);
3937 #ifdef CONFIG_PM_SLEEP
3938 static int rtl_notifier(struct notifier_block *nb, unsigned long action,
3941 struct r8152 *tp = container_of(nb, struct r8152, pm_notifier);
3944 case PM_HIBERNATION_PREPARE:
3945 case PM_SUSPEND_PREPARE:
3946 usb_autopm_get_interface(tp->intf);
3949 case PM_POST_HIBERNATION:
3950 case PM_POST_SUSPEND:
3951 usb_autopm_put_interface(tp->intf);
3954 case PM_POST_RESTORE:
3955 case PM_RESTORE_PREPARE:
3964 static int rtl8152_open(struct net_device *netdev)
3966 struct r8152 *tp = netdev_priv(netdev);
3969 res = alloc_all_mem(tp);
3973 res = usb_autopm_get_interface(tp->intf);
3977 mutex_lock(&tp->control);
3981 netif_carrier_off(netdev);
3982 netif_start_queue(netdev);
3983 set_bit(WORK_ENABLE, &tp->flags);
3985 res = usb_submit_urb(tp->intr_urb, GFP_KERNEL);
3988 netif_device_detach(tp->netdev);
3989 netif_warn(tp, ifup, netdev, "intr_urb submit failed: %d\n",
3993 napi_enable(&tp->napi);
3995 mutex_unlock(&tp->control);
3997 usb_autopm_put_interface(tp->intf);
3998 #ifdef CONFIG_PM_SLEEP
3999 tp->pm_notifier.notifier_call = rtl_notifier;
4000 register_pm_notifier(&tp->pm_notifier);
4005 mutex_unlock(&tp->control);
4006 usb_autopm_put_interface(tp->intf);
4013 static int rtl8152_close(struct net_device *netdev)
4015 struct r8152 *tp = netdev_priv(netdev);
4018 #ifdef CONFIG_PM_SLEEP
4019 unregister_pm_notifier(&tp->pm_notifier);
4021 if (!test_bit(RTL8152_UNPLUG, &tp->flags))
4022 napi_disable(&tp->napi);
4023 clear_bit(WORK_ENABLE, &tp->flags);
4024 usb_kill_urb(tp->intr_urb);
4025 cancel_delayed_work_sync(&tp->schedule);
4026 netif_stop_queue(netdev);
4028 res = usb_autopm_get_interface(tp->intf);
4029 if (res < 0 || test_bit(RTL8152_UNPLUG, &tp->flags)) {
4030 rtl_drop_queued_tx(tp);
4033 mutex_lock(&tp->control);
4035 tp->rtl_ops.down(tp);
4037 mutex_unlock(&tp->control);
4039 usb_autopm_put_interface(tp->intf);
4047 static void rtl_tally_reset(struct r8152 *tp)
4051 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY);
4052 ocp_data |= TALLY_RESET;
4053 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY, ocp_data);
4056 static void r8152b_init(struct r8152 *tp)
4061 if (test_bit(RTL8152_UNPLUG, &tp->flags))
4064 data = r8152_mdio_read(tp, MII_BMCR);
4065 if (data & BMCR_PDOWN) {
4066 data &= ~BMCR_PDOWN;
4067 r8152_mdio_write(tp, MII_BMCR, data);
4070 r8152_aldps_en(tp, false);
4072 if (tp->version == RTL_VER_01) {
4073 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
4074 ocp_data &= ~LED_MODE_MASK;
4075 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
4078 r8152_power_cut_en(tp, false);
4080 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
4081 ocp_data |= TX_10M_IDLE_EN | PFM_PWM_SWITCH;
4082 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
4083 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL);
4084 ocp_data &= ~MCU_CLK_RATIO_MASK;
4085 ocp_data |= MCU_CLK_RATIO | D3_CLK_GATED_EN;
4086 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ocp_data);
4087 ocp_data = GPHY_STS_MSK | SPEED_DOWN_MSK |
4088 SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK;
4089 ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, ocp_data);
4091 rtl_tally_reset(tp);
4093 /* enable rx aggregation */
4094 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
4095 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
4096 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
4099 static void r8153_init(struct r8152 *tp)
4105 if (test_bit(RTL8152_UNPLUG, &tp->flags))
4108 r8153_u1u2en(tp, false);
4110 for (i = 0; i < 500; i++) {
4111 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
4117 data = r8153_phy_status(tp, 0);
4119 if (tp->version == RTL_VER_03 || tp->version == RTL_VER_04 ||
4120 tp->version == RTL_VER_05)
4121 ocp_reg_write(tp, OCP_ADC_CFG, CKADSEL_L | ADC_EN | EN_EMI_L);
4123 data = r8152_mdio_read(tp, MII_BMCR);
4124 if (data & BMCR_PDOWN) {
4125 data &= ~BMCR_PDOWN;
4126 r8152_mdio_write(tp, MII_BMCR, data);
4129 data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
4131 r8153_u2p3en(tp, false);
4133 if (tp->version == RTL_VER_04) {
4134 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2);
4135 ocp_data &= ~pwd_dn_scale_mask;
4136 ocp_data |= pwd_dn_scale(96);
4137 ocp_write_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2, ocp_data);
4139 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY);
4140 ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND;
4141 ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data);
4142 } else if (tp->version == RTL_VER_05) {
4143 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0);
4144 ocp_data &= ~ECM_ALDPS;
4145 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0, ocp_data);
4147 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1);
4148 if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0)
4149 ocp_data &= ~DYNAMIC_BURST;
4151 ocp_data |= DYNAMIC_BURST;
4152 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data);
4153 } else if (tp->version == RTL_VER_06) {
4154 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1);
4155 if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0)
4156 ocp_data &= ~DYNAMIC_BURST;
4158 ocp_data |= DYNAMIC_BURST;
4159 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data);
4162 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2);
4163 ocp_data |= EP4_FULL_FC;
4164 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2, ocp_data);
4166 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL);
4167 ocp_data &= ~TIMER11_EN;
4168 ocp_write_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL, ocp_data);
4170 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
4171 ocp_data &= ~LED_MODE_MASK;
4172 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
4174 ocp_data = FIFO_EMPTY_1FB | ROK_EXIT_LPM;
4175 if (tp->version == RTL_VER_04 && tp->udev->speed < USB_SPEED_SUPER)
4176 ocp_data |= LPM_TIMER_500MS;
4178 ocp_data |= LPM_TIMER_500US;
4179 ocp_write_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL, ocp_data);
4181 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2);
4182 ocp_data &= ~SEN_VAL_MASK;
4183 ocp_data |= SEN_VAL_NORMAL | SEL_RXIDLE;
4184 ocp_write_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2, ocp_data);
4186 ocp_write_word(tp, MCU_TYPE_USB, USB_CONNECT_TIMER, 0x0001);
4188 r8153_power_cut_en(tp, false);
4189 r8153_u1u2en(tp, true);
4190 r8153_mac_clk_spd(tp, false);
4191 usb_enable_lpm(tp->udev);
4193 /* rx aggregation */
4194 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
4195 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
4196 if (test_bit(DELL_TB_RX_AGG_BUG, &tp->flags))
4197 ocp_data |= RX_AGG_DISABLE;
4199 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
4201 rtl_tally_reset(tp);
4203 switch (tp->udev->speed) {
4204 case USB_SPEED_SUPER:
4205 case USB_SPEED_SUPER_PLUS:
4206 tp->coalesce = COALESCE_SUPER;
4208 case USB_SPEED_HIGH:
4209 tp->coalesce = COALESCE_HIGH;
4212 tp->coalesce = COALESCE_SLOW;
4217 static void r8153b_init(struct r8152 *tp)
4223 if (test_bit(RTL8152_UNPLUG, &tp->flags))
4226 r8153b_u1u2en(tp, false);
4228 for (i = 0; i < 500; i++) {
4229 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
4235 data = r8153_phy_status(tp, 0);
4237 data = r8152_mdio_read(tp, MII_BMCR);
4238 if (data & BMCR_PDOWN) {
4239 data &= ~BMCR_PDOWN;
4240 r8152_mdio_write(tp, MII_BMCR, data);
4243 data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
4245 r8153_u2p3en(tp, false);
4247 /* MSC timer = 0xfff * 8ms = 32760 ms */
4248 ocp_write_word(tp, MCU_TYPE_USB, USB_MSC_TIMER, 0x0fff);
4250 /* U1/U2/L1 idle timer. 500 us */
4251 ocp_write_word(tp, MCU_TYPE_USB, USB_U1U2_TIMER, 500);
4253 r8153b_power_cut_en(tp, false);
4254 r8153b_ups_en(tp, false);
4255 r8153_queue_wake(tp, false);
4256 rtl_runtime_suspend_enable(tp, false);
4257 r8153b_u1u2en(tp, true);
4258 usb_enable_lpm(tp->udev);
4260 /* MAC clock speed down */
4261 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2);
4262 ocp_data |= MAC_CLK_SPDWN_EN;
4263 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, ocp_data);
4265 set_bit(GREEN_ETHERNET, &tp->flags);
4267 /* rx aggregation */
4268 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
4269 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
4270 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
4272 rtl_tally_reset(tp);
4274 tp->coalesce = 15000; /* 15 us */
4277 static int rtl8152_pre_reset(struct usb_interface *intf)
4279 struct r8152 *tp = usb_get_intfdata(intf);
4280 struct net_device *netdev;
4285 netdev = tp->netdev;
4286 if (!netif_running(netdev))
4289 netif_stop_queue(netdev);
4290 napi_disable(&tp->napi);
4291 clear_bit(WORK_ENABLE, &tp->flags);
4292 usb_kill_urb(tp->intr_urb);
4293 cancel_delayed_work_sync(&tp->schedule);
4294 if (netif_carrier_ok(netdev)) {
4295 mutex_lock(&tp->control);
4296 tp->rtl_ops.disable(tp);
4297 mutex_unlock(&tp->control);
4303 static int rtl8152_post_reset(struct usb_interface *intf)
4305 struct r8152 *tp = usb_get_intfdata(intf);
4306 struct net_device *netdev;
4312 /* reset the MAC adddress in case of policy change */
4313 if (determine_ethernet_addr(tp, &sa) >= 0) {
4315 dev_set_mac_address (tp->netdev, &sa, NULL);
4319 netdev = tp->netdev;
4320 if (!netif_running(netdev))
4323 set_bit(WORK_ENABLE, &tp->flags);
4324 if (netif_carrier_ok(netdev)) {
4325 mutex_lock(&tp->control);
4326 tp->rtl_ops.enable(tp);
4328 _rtl8152_set_rx_mode(netdev);
4329 mutex_unlock(&tp->control);
4332 napi_enable(&tp->napi);
4333 netif_wake_queue(netdev);
4334 usb_submit_urb(tp->intr_urb, GFP_KERNEL);
4336 if (!list_empty(&tp->rx_done))
4337 napi_schedule(&tp->napi);
4342 static bool delay_autosuspend(struct r8152 *tp)
4344 bool sw_linking = !!netif_carrier_ok(tp->netdev);
4345 bool hw_linking = !!(rtl8152_get_speed(tp) & LINK_STATUS);
4347 /* This means a linking change occurs and the driver doesn't detect it,
4348 * yet. If the driver has disabled tx/rx and hw is linking on, the
4349 * device wouldn't wake up by receiving any packet.
4351 if (work_busy(&tp->schedule.work) || sw_linking != hw_linking)
4354 /* If the linking down is occurred by nway, the device may miss the
4355 * linking change event. And it wouldn't wake when linking on.
4357 if (!sw_linking && tp->rtl_ops.in_nway(tp))
4359 else if (!skb_queue_empty(&tp->tx_queue))
4365 static int rtl8152_runtime_resume(struct r8152 *tp)
4367 struct net_device *netdev = tp->netdev;
4369 if (netif_running(netdev) && netdev->flags & IFF_UP) {
4370 struct napi_struct *napi = &tp->napi;
4372 tp->rtl_ops.autosuspend_en(tp, false);
4374 set_bit(WORK_ENABLE, &tp->flags);
4376 if (netif_carrier_ok(netdev)) {
4377 if (rtl8152_get_speed(tp) & LINK_STATUS) {
4380 netif_carrier_off(netdev);
4381 tp->rtl_ops.disable(tp);
4382 netif_info(tp, link, netdev, "linking down\n");
4387 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
4388 smp_mb__after_atomic();
4390 if (!list_empty(&tp->rx_done))
4391 napi_schedule(&tp->napi);
4393 usb_submit_urb(tp->intr_urb, GFP_NOIO);
4395 if (netdev->flags & IFF_UP)
4396 tp->rtl_ops.autosuspend_en(tp, false);
4398 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
4404 static int rtl8152_system_resume(struct r8152 *tp)
4406 struct net_device *netdev = tp->netdev;
4408 netif_device_attach(netdev);
4410 if (netif_running(netdev) && netdev->flags & IFF_UP) {
4412 netif_carrier_off(netdev);
4413 set_bit(WORK_ENABLE, &tp->flags);
4414 usb_submit_urb(tp->intr_urb, GFP_NOIO);
4420 static int rtl8152_runtime_suspend(struct r8152 *tp)
4422 struct net_device *netdev = tp->netdev;
4425 set_bit(SELECTIVE_SUSPEND, &tp->flags);
4426 smp_mb__after_atomic();
4428 if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) {
4431 if (netif_carrier_ok(netdev)) {
4434 rcr = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
4435 ocp_data = rcr & ~RCR_ACPT_ALL;
4436 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
4437 rxdy_gated_en(tp, true);
4438 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA,
4440 if (!(ocp_data & RXFIFO_EMPTY)) {
4441 rxdy_gated_en(tp, false);
4442 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, rcr);
4443 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
4444 smp_mb__after_atomic();
4450 clear_bit(WORK_ENABLE, &tp->flags);
4451 usb_kill_urb(tp->intr_urb);
4453 tp->rtl_ops.autosuspend_en(tp, true);
4455 if (netif_carrier_ok(netdev)) {
4456 struct napi_struct *napi = &tp->napi;
4460 rxdy_gated_en(tp, false);
4461 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, rcr);
4465 if (delay_autosuspend(tp)) {
4466 rtl8152_runtime_resume(tp);
4475 static int rtl8152_system_suspend(struct r8152 *tp)
4477 struct net_device *netdev = tp->netdev;
4479 netif_device_detach(netdev);
4481 if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) {
4482 struct napi_struct *napi = &tp->napi;
4484 clear_bit(WORK_ENABLE, &tp->flags);
4485 usb_kill_urb(tp->intr_urb);
4487 cancel_delayed_work_sync(&tp->schedule);
4488 tp->rtl_ops.down(tp);
4495 static int rtl8152_suspend(struct usb_interface *intf, pm_message_t message)
4497 struct r8152 *tp = usb_get_intfdata(intf);
4500 mutex_lock(&tp->control);
4502 if (PMSG_IS_AUTO(message))
4503 ret = rtl8152_runtime_suspend(tp);
4505 ret = rtl8152_system_suspend(tp);
4507 mutex_unlock(&tp->control);
4512 static int rtl8152_resume(struct usb_interface *intf)
4514 struct r8152 *tp = usb_get_intfdata(intf);
4517 mutex_lock(&tp->control);
4519 if (test_bit(SELECTIVE_SUSPEND, &tp->flags))
4520 ret = rtl8152_runtime_resume(tp);
4522 ret = rtl8152_system_resume(tp);
4524 mutex_unlock(&tp->control);
4529 static int rtl8152_reset_resume(struct usb_interface *intf)
4531 struct r8152 *tp = usb_get_intfdata(intf);
4533 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
4534 mutex_lock(&tp->control);
4535 tp->rtl_ops.init(tp);
4536 queue_delayed_work(system_long_wq, &tp->hw_phy_work, 0);
4537 mutex_unlock(&tp->control);
4538 return rtl8152_resume(intf);
4541 static void rtl8152_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
4543 struct r8152 *tp = netdev_priv(dev);
4545 if (usb_autopm_get_interface(tp->intf) < 0)
4548 if (!rtl_can_wakeup(tp)) {
4552 mutex_lock(&tp->control);
4553 wol->supported = WAKE_ANY;
4554 wol->wolopts = __rtl_get_wol(tp);
4555 mutex_unlock(&tp->control);
4558 usb_autopm_put_interface(tp->intf);
4561 static int rtl8152_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
4563 struct r8152 *tp = netdev_priv(dev);
4566 if (!rtl_can_wakeup(tp))
4569 if (wol->wolopts & ~WAKE_ANY)
4572 ret = usb_autopm_get_interface(tp->intf);
4576 mutex_lock(&tp->control);
4578 __rtl_set_wol(tp, wol->wolopts);
4579 tp->saved_wolopts = wol->wolopts & WAKE_ANY;
4581 mutex_unlock(&tp->control);
4583 usb_autopm_put_interface(tp->intf);
4589 static u32 rtl8152_get_msglevel(struct net_device *dev)
4591 struct r8152 *tp = netdev_priv(dev);
4593 return tp->msg_enable;
4596 static void rtl8152_set_msglevel(struct net_device *dev, u32 value)
4598 struct r8152 *tp = netdev_priv(dev);
4600 tp->msg_enable = value;
4603 static void rtl8152_get_drvinfo(struct net_device *netdev,
4604 struct ethtool_drvinfo *info)
4606 struct r8152 *tp = netdev_priv(netdev);
4608 strlcpy(info->driver, MODULENAME, sizeof(info->driver));
4609 strlcpy(info->version, DRIVER_VERSION, sizeof(info->version));
4610 usb_make_path(tp->udev, info->bus_info, sizeof(info->bus_info));
4614 int rtl8152_get_link_ksettings(struct net_device *netdev,
4615 struct ethtool_link_ksettings *cmd)
4617 struct r8152 *tp = netdev_priv(netdev);
4620 if (!tp->mii.mdio_read)
4623 ret = usb_autopm_get_interface(tp->intf);
4627 mutex_lock(&tp->control);
4629 mii_ethtool_get_link_ksettings(&tp->mii, cmd);
4631 mutex_unlock(&tp->control);
4633 usb_autopm_put_interface(tp->intf);
4639 static int rtl8152_set_link_ksettings(struct net_device *dev,
4640 const struct ethtool_link_ksettings *cmd)
4642 struct r8152 *tp = netdev_priv(dev);
4645 ret = usb_autopm_get_interface(tp->intf);
4649 mutex_lock(&tp->control);
4651 ret = rtl8152_set_speed(tp, cmd->base.autoneg, cmd->base.speed,
4654 tp->autoneg = cmd->base.autoneg;
4655 tp->speed = cmd->base.speed;
4656 tp->duplex = cmd->base.duplex;
4659 mutex_unlock(&tp->control);
4661 usb_autopm_put_interface(tp->intf);
4667 static const char rtl8152_gstrings[][ETH_GSTRING_LEN] = {
4674 "tx_single_collisions",
4675 "tx_multi_collisions",
4683 static int rtl8152_get_sset_count(struct net_device *dev, int sset)
4687 return ARRAY_SIZE(rtl8152_gstrings);
4693 static void rtl8152_get_ethtool_stats(struct net_device *dev,
4694 struct ethtool_stats *stats, u64 *data)
4696 struct r8152 *tp = netdev_priv(dev);
4697 struct tally_counter tally;
4699 if (usb_autopm_get_interface(tp->intf) < 0)
4702 generic_ocp_read(tp, PLA_TALLYCNT, sizeof(tally), &tally, MCU_TYPE_PLA);
4704 usb_autopm_put_interface(tp->intf);
4706 data[0] = le64_to_cpu(tally.tx_packets);
4707 data[1] = le64_to_cpu(tally.rx_packets);
4708 data[2] = le64_to_cpu(tally.tx_errors);
4709 data[3] = le32_to_cpu(tally.rx_errors);
4710 data[4] = le16_to_cpu(tally.rx_missed);
4711 data[5] = le16_to_cpu(tally.align_errors);
4712 data[6] = le32_to_cpu(tally.tx_one_collision);
4713 data[7] = le32_to_cpu(tally.tx_multi_collision);
4714 data[8] = le64_to_cpu(tally.rx_unicast);
4715 data[9] = le64_to_cpu(tally.rx_broadcast);
4716 data[10] = le32_to_cpu(tally.rx_multicast);
4717 data[11] = le16_to_cpu(tally.tx_aborted);
4718 data[12] = le16_to_cpu(tally.tx_underrun);
4721 static void rtl8152_get_strings(struct net_device *dev, u32 stringset, u8 *data)
4723 switch (stringset) {
4725 memcpy(data, *rtl8152_gstrings, sizeof(rtl8152_gstrings));
4730 static int r8152_get_eee(struct r8152 *tp, struct ethtool_eee *eee)
4732 u32 ocp_data, lp, adv, supported = 0;
4735 val = r8152_mmd_read(tp, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE);
4736 supported = mmd_eee_cap_to_ethtool_sup_t(val);
4738 val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV);
4739 adv = mmd_eee_adv_to_ethtool_adv_t(val);
4741 val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE);
4742 lp = mmd_eee_adv_to_ethtool_adv_t(val);
4744 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
4745 ocp_data &= EEE_RX_EN | EEE_TX_EN;
4747 eee->eee_enabled = !!ocp_data;
4748 eee->eee_active = !!(supported & adv & lp);
4749 eee->supported = supported;
4750 eee->advertised = adv;
4751 eee->lp_advertised = lp;
4756 static int r8152_set_eee(struct r8152 *tp, struct ethtool_eee *eee)
4758 u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised);
4760 r8152_eee_en(tp, eee->eee_enabled);
4762 if (!eee->eee_enabled)
4765 r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);
4770 static int r8153_get_eee(struct r8152 *tp, struct ethtool_eee *eee)
4772 u32 ocp_data, lp, adv, supported = 0;
4775 val = ocp_reg_read(tp, OCP_EEE_ABLE);
4776 supported = mmd_eee_cap_to_ethtool_sup_t(val);
4778 val = ocp_reg_read(tp, OCP_EEE_ADV);
4779 adv = mmd_eee_adv_to_ethtool_adv_t(val);
4781 val = ocp_reg_read(tp, OCP_EEE_LPABLE);
4782 lp = mmd_eee_adv_to_ethtool_adv_t(val);
4784 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
4785 ocp_data &= EEE_RX_EN | EEE_TX_EN;
4787 eee->eee_enabled = !!ocp_data;
4788 eee->eee_active = !!(supported & adv & lp);
4789 eee->supported = supported;
4790 eee->advertised = adv;
4791 eee->lp_advertised = lp;
4796 static int r8153_set_eee(struct r8152 *tp, struct ethtool_eee *eee)
4798 u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised);
4800 r8153_eee_en(tp, eee->eee_enabled);
4802 if (!eee->eee_enabled)
4805 ocp_reg_write(tp, OCP_EEE_ADV, val);
4810 static int r8153b_set_eee(struct r8152 *tp, struct ethtool_eee *eee)
4812 u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised);
4814 r8153b_eee_en(tp, eee->eee_enabled);
4816 if (!eee->eee_enabled)
4819 ocp_reg_write(tp, OCP_EEE_ADV, val);
4825 rtl_ethtool_get_eee(struct net_device *net, struct ethtool_eee *edata)
4827 struct r8152 *tp = netdev_priv(net);
4830 ret = usb_autopm_get_interface(tp->intf);
4834 mutex_lock(&tp->control);
4836 ret = tp->rtl_ops.eee_get(tp, edata);
4838 mutex_unlock(&tp->control);
4840 usb_autopm_put_interface(tp->intf);
4847 rtl_ethtool_set_eee(struct net_device *net, struct ethtool_eee *edata)
4849 struct r8152 *tp = netdev_priv(net);
4852 ret = usb_autopm_get_interface(tp->intf);
4856 mutex_lock(&tp->control);
4858 ret = tp->rtl_ops.eee_set(tp, edata);
4860 ret = mii_nway_restart(&tp->mii);
4862 mutex_unlock(&tp->control);
4864 usb_autopm_put_interface(tp->intf);
4870 static int rtl8152_nway_reset(struct net_device *dev)
4872 struct r8152 *tp = netdev_priv(dev);
4875 ret = usb_autopm_get_interface(tp->intf);
4879 mutex_lock(&tp->control);
4881 ret = mii_nway_restart(&tp->mii);
4883 mutex_unlock(&tp->control);
4885 usb_autopm_put_interface(tp->intf);
4891 static int rtl8152_get_coalesce(struct net_device *netdev,
4892 struct ethtool_coalesce *coalesce)
4894 struct r8152 *tp = netdev_priv(netdev);
4896 switch (tp->version) {
4905 coalesce->rx_coalesce_usecs = tp->coalesce;
4910 static int rtl8152_set_coalesce(struct net_device *netdev,
4911 struct ethtool_coalesce *coalesce)
4913 struct r8152 *tp = netdev_priv(netdev);
4916 switch (tp->version) {
4925 if (coalesce->rx_coalesce_usecs > COALESCE_SLOW)
4928 ret = usb_autopm_get_interface(tp->intf);
4932 mutex_lock(&tp->control);
4934 if (tp->coalesce != coalesce->rx_coalesce_usecs) {
4935 tp->coalesce = coalesce->rx_coalesce_usecs;
4937 if (netif_running(netdev) && netif_carrier_ok(netdev)) {
4938 netif_stop_queue(netdev);
4939 napi_disable(&tp->napi);
4940 tp->rtl_ops.disable(tp);
4941 tp->rtl_ops.enable(tp);
4943 clear_bit(RTL8152_SET_RX_MODE, &tp->flags);
4944 _rtl8152_set_rx_mode(netdev);
4945 napi_enable(&tp->napi);
4946 netif_wake_queue(netdev);
4950 mutex_unlock(&tp->control);
4952 usb_autopm_put_interface(tp->intf);
4957 static const struct ethtool_ops ops = {
4958 .get_drvinfo = rtl8152_get_drvinfo,
4959 .get_link = ethtool_op_get_link,
4960 .nway_reset = rtl8152_nway_reset,
4961 .get_msglevel = rtl8152_get_msglevel,
4962 .set_msglevel = rtl8152_set_msglevel,
4963 .get_wol = rtl8152_get_wol,
4964 .set_wol = rtl8152_set_wol,
4965 .get_strings = rtl8152_get_strings,
4966 .get_sset_count = rtl8152_get_sset_count,
4967 .get_ethtool_stats = rtl8152_get_ethtool_stats,
4968 .get_coalesce = rtl8152_get_coalesce,
4969 .set_coalesce = rtl8152_set_coalesce,
4970 .get_eee = rtl_ethtool_get_eee,
4971 .set_eee = rtl_ethtool_set_eee,
4972 .get_link_ksettings = rtl8152_get_link_ksettings,
4973 .set_link_ksettings = rtl8152_set_link_ksettings,
4976 static int rtl8152_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
4978 struct r8152 *tp = netdev_priv(netdev);
4979 struct mii_ioctl_data *data = if_mii(rq);
4982 if (test_bit(RTL8152_UNPLUG, &tp->flags))
4985 res = usb_autopm_get_interface(tp->intf);
4991 data->phy_id = R8152_PHY_ID; /* Internal PHY */
4995 mutex_lock(&tp->control);
4996 data->val_out = r8152_mdio_read(tp, data->reg_num);
4997 mutex_unlock(&tp->control);
5001 if (!capable(CAP_NET_ADMIN)) {
5005 mutex_lock(&tp->control);
5006 r8152_mdio_write(tp, data->reg_num, data->val_in);
5007 mutex_unlock(&tp->control);
5014 usb_autopm_put_interface(tp->intf);
5020 static int rtl8152_change_mtu(struct net_device *dev, int new_mtu)
5022 struct r8152 *tp = netdev_priv(dev);
5025 switch (tp->version) {
5035 ret = usb_autopm_get_interface(tp->intf);
5039 mutex_lock(&tp->control);
5043 if (netif_running(dev)) {
5044 u32 rms = new_mtu + VLAN_ETH_HLEN + ETH_FCS_LEN;
5046 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, rms);
5048 if (netif_carrier_ok(dev))
5049 r8153_set_rx_early_size(tp);
5052 mutex_unlock(&tp->control);
5054 usb_autopm_put_interface(tp->intf);
5059 static const struct net_device_ops rtl8152_netdev_ops = {
5060 .ndo_open = rtl8152_open,
5061 .ndo_stop = rtl8152_close,
5062 .ndo_do_ioctl = rtl8152_ioctl,
5063 .ndo_start_xmit = rtl8152_start_xmit,
5064 .ndo_tx_timeout = rtl8152_tx_timeout,
5065 .ndo_set_features = rtl8152_set_features,
5066 .ndo_set_rx_mode = rtl8152_set_rx_mode,
5067 .ndo_set_mac_address = rtl8152_set_mac_address,
5068 .ndo_change_mtu = rtl8152_change_mtu,
5069 .ndo_validate_addr = eth_validate_addr,
5070 .ndo_features_check = rtl8152_features_check,
5073 static void rtl8152_unload(struct r8152 *tp)
5075 if (test_bit(RTL8152_UNPLUG, &tp->flags))
5078 if (tp->version != RTL_VER_01)
5079 r8152_power_cut_en(tp, true);
5082 static void rtl8153_unload(struct r8152 *tp)
5084 if (test_bit(RTL8152_UNPLUG, &tp->flags))
5087 r8153_power_cut_en(tp, false);
5090 static void rtl8153b_unload(struct r8152 *tp)
5092 if (test_bit(RTL8152_UNPLUG, &tp->flags))
5095 r8153b_power_cut_en(tp, false);
5098 static int rtl_ops_init(struct r8152 *tp)
5100 struct rtl_ops *ops = &tp->rtl_ops;
5103 switch (tp->version) {
5107 ops->init = r8152b_init;
5108 ops->enable = rtl8152_enable;
5109 ops->disable = rtl8152_disable;
5110 ops->up = rtl8152_up;
5111 ops->down = rtl8152_down;
5112 ops->unload = rtl8152_unload;
5113 ops->eee_get = r8152_get_eee;
5114 ops->eee_set = r8152_set_eee;
5115 ops->in_nway = rtl8152_in_nway;
5116 ops->hw_phy_cfg = r8152b_hw_phy_cfg;
5117 ops->autosuspend_en = rtl_runtime_suspend_enable;
5124 ops->init = r8153_init;
5125 ops->enable = rtl8153_enable;
5126 ops->disable = rtl8153_disable;
5127 ops->up = rtl8153_up;
5128 ops->down = rtl8153_down;
5129 ops->unload = rtl8153_unload;
5130 ops->eee_get = r8153_get_eee;
5131 ops->eee_set = r8153_set_eee;
5132 ops->in_nway = rtl8153_in_nway;
5133 ops->hw_phy_cfg = r8153_hw_phy_cfg;
5134 ops->autosuspend_en = rtl8153_runtime_enable;
5139 ops->init = r8153b_init;
5140 ops->enable = rtl8153_enable;
5141 ops->disable = rtl8153b_disable;
5142 ops->up = rtl8153b_up;
5143 ops->down = rtl8153b_down;
5144 ops->unload = rtl8153b_unload;
5145 ops->eee_get = r8153_get_eee;
5146 ops->eee_set = r8153b_set_eee;
5147 ops->in_nway = rtl8153_in_nway;
5148 ops->hw_phy_cfg = r8153b_hw_phy_cfg;
5149 ops->autosuspend_en = rtl8153b_runtime_enable;
5154 netif_err(tp, probe, tp->netdev, "Unknown Device\n");
5161 static u8 rtl_get_version(struct usb_interface *intf)
5163 struct usb_device *udev = interface_to_usbdev(intf);
5169 tmp = kmalloc(sizeof(*tmp), GFP_KERNEL);
5173 ret = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
5174 RTL8152_REQ_GET_REGS, RTL8152_REQT_READ,
5175 PLA_TCR0, MCU_TYPE_PLA, tmp, sizeof(*tmp), 500);
5177 ocp_data = (__le32_to_cpu(*tmp) >> 16) & VERSION_MASK;
5183 version = RTL_VER_01;
5186 version = RTL_VER_02;
5189 version = RTL_VER_03;
5192 version = RTL_VER_04;
5195 version = RTL_VER_05;
5198 version = RTL_VER_06;
5201 version = RTL_VER_07;
5204 version = RTL_VER_08;
5207 version = RTL_VER_09;
5210 version = RTL_VER_UNKNOWN;
5211 dev_info(&intf->dev, "Unknown version 0x%04x\n", ocp_data);
5215 dev_dbg(&intf->dev, "Detected version 0x%04x\n", version);
5220 static int rtl8152_probe(struct usb_interface *intf,
5221 const struct usb_device_id *id)
5223 struct usb_device *udev = interface_to_usbdev(intf);
5224 u8 version = rtl_get_version(intf);
5226 struct net_device *netdev;
5229 if (version == RTL_VER_UNKNOWN)
5232 if (udev->actconfig->desc.bConfigurationValue != 1) {
5233 usb_driver_set_configuration(udev, 1);
5237 usb_reset_device(udev);
5238 netdev = alloc_etherdev(sizeof(struct r8152));
5240 dev_err(&intf->dev, "Out of memory\n");
5244 SET_NETDEV_DEV(netdev, &intf->dev);
5245 tp = netdev_priv(netdev);
5246 tp->msg_enable = 0x7FFF;
5249 tp->netdev = netdev;
5251 tp->version = version;
5257 tp->mii.supports_gmii = 0;
5260 tp->mii.supports_gmii = 1;
5264 ret = rtl_ops_init(tp);
5268 mutex_init(&tp->control);
5269 INIT_DELAYED_WORK(&tp->schedule, rtl_work_func_t);
5270 INIT_DELAYED_WORK(&tp->hw_phy_work, rtl_hw_phy_work_func_t);
5272 netdev->netdev_ops = &rtl8152_netdev_ops;
5273 netdev->watchdog_timeo = RTL8152_TX_TIMEOUT;
5275 netdev->features |= NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
5276 NETIF_F_TSO | NETIF_F_FRAGLIST | NETIF_F_IPV6_CSUM |
5277 NETIF_F_TSO6 | NETIF_F_HW_VLAN_CTAG_RX |
5278 NETIF_F_HW_VLAN_CTAG_TX;
5279 netdev->hw_features = NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
5280 NETIF_F_TSO | NETIF_F_FRAGLIST |
5281 NETIF_F_IPV6_CSUM | NETIF_F_TSO6 |
5282 NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX;
5283 netdev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
5284 NETIF_F_HIGHDMA | NETIF_F_FRAGLIST |
5285 NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
5287 if (tp->version == RTL_VER_01) {
5288 netdev->features &= ~NETIF_F_RXCSUM;
5289 netdev->hw_features &= ~NETIF_F_RXCSUM;
5292 if (le16_to_cpu(udev->descriptor.bcdDevice) == 0x3011 && udev->serial &&
5293 (!strcmp(udev->serial, "000001000000") || !strcmp(udev->serial, "000002000000"))) {
5294 dev_info(&udev->dev, "Dell TB16 Dock, disable RX aggregation");
5295 set_bit(DELL_TB_RX_AGG_BUG, &tp->flags);
5298 netdev->ethtool_ops = &ops;
5299 netif_set_gso_max_size(netdev, RTL_LIMITED_TSO_SIZE);
5301 /* MTU range: 68 - 1500 or 9194 */
5302 netdev->min_mtu = ETH_MIN_MTU;
5303 switch (tp->version) {
5306 netdev->max_mtu = ETH_DATA_LEN;
5309 netdev->max_mtu = RTL8153_MAX_MTU;
5313 tp->mii.dev = netdev;
5314 tp->mii.mdio_read = read_mii_word;
5315 tp->mii.mdio_write = write_mii_word;
5316 tp->mii.phy_id_mask = 0x3f;
5317 tp->mii.reg_num_mask = 0x1f;
5318 tp->mii.phy_id = R8152_PHY_ID;
5320 tp->autoneg = AUTONEG_ENABLE;
5321 tp->speed = tp->mii.supports_gmii ? SPEED_1000 : SPEED_100;
5322 tp->duplex = DUPLEX_FULL;
5324 intf->needs_remote_wakeup = 1;
5326 tp->rtl_ops.init(tp);
5327 queue_delayed_work(system_long_wq, &tp->hw_phy_work, 0);
5328 set_ethernet_addr(tp);
5330 usb_set_intfdata(intf, tp);
5331 netif_napi_add(netdev, &tp->napi, r8152_poll, RTL8152_NAPI_WEIGHT);
5333 ret = register_netdev(netdev);
5335 netif_err(tp, probe, netdev, "couldn't register the device\n");
5339 if (!rtl_can_wakeup(tp))
5340 __rtl_set_wol(tp, 0);
5342 tp->saved_wolopts = __rtl_get_wol(tp);
5343 if (tp->saved_wolopts)
5344 device_set_wakeup_enable(&udev->dev, true);
5346 device_set_wakeup_enable(&udev->dev, false);
5348 netif_info(tp, probe, netdev, "%s\n", DRIVER_VERSION);
5353 netif_napi_del(&tp->napi);
5354 usb_set_intfdata(intf, NULL);
5356 free_netdev(netdev);
5360 static void rtl8152_disconnect(struct usb_interface *intf)
5362 struct r8152 *tp = usb_get_intfdata(intf);
5364 usb_set_intfdata(intf, NULL);
5368 netif_napi_del(&tp->napi);
5369 unregister_netdev(tp->netdev);
5370 cancel_delayed_work_sync(&tp->hw_phy_work);
5371 tp->rtl_ops.unload(tp);
5372 free_netdev(tp->netdev);
5376 #define REALTEK_USB_DEVICE(vend, prod) \
5377 .match_flags = USB_DEVICE_ID_MATCH_DEVICE | \
5378 USB_DEVICE_ID_MATCH_INT_CLASS, \
5379 .idVendor = (vend), \
5380 .idProduct = (prod), \
5381 .bInterfaceClass = USB_CLASS_VENDOR_SPEC \
5384 .match_flags = USB_DEVICE_ID_MATCH_INT_INFO | \
5385 USB_DEVICE_ID_MATCH_DEVICE, \
5386 .idVendor = (vend), \
5387 .idProduct = (prod), \
5388 .bInterfaceClass = USB_CLASS_COMM, \
5389 .bInterfaceSubClass = USB_CDC_SUBCLASS_ETHERNET, \
5390 .bInterfaceProtocol = USB_CDC_PROTO_NONE
5392 /* table of devices that work with this driver */
5393 static const struct usb_device_id rtl8152_table[] = {
5394 {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8050)},
5395 {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8152)},
5396 {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8153)},
5397 {REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT, 0x07ab)},
5398 {REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT, 0x07c6)},
5399 {REALTEK_USB_DEVICE(VENDOR_ID_SAMSUNG, 0xa101)},
5400 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x304f)},
5401 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x3062)},
5402 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x3069)},
5403 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x7205)},
5404 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x720c)},
5405 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x7214)},
5406 {REALTEK_USB_DEVICE(VENDOR_ID_LINKSYS, 0x0041)},
5407 {REALTEK_USB_DEVICE(VENDOR_ID_NVIDIA, 0x09ff)},
5408 {REALTEK_USB_DEVICE(VENDOR_ID_TPLINK, 0x0601)},
5412 MODULE_DEVICE_TABLE(usb, rtl8152_table);
5414 static struct usb_driver rtl8152_driver = {
5416 .id_table = rtl8152_table,
5417 .probe = rtl8152_probe,
5418 .disconnect = rtl8152_disconnect,
5419 .suspend = rtl8152_suspend,
5420 .resume = rtl8152_resume,
5421 .reset_resume = rtl8152_reset_resume,
5422 .pre_reset = rtl8152_pre_reset,
5423 .post_reset = rtl8152_post_reset,
5424 .supports_autosuspend = 1,
5425 .disable_hub_initiated_lpm = 1,
5428 module_usb_driver(rtl8152_driver);
5430 MODULE_AUTHOR(DRIVER_AUTHOR);
5431 MODULE_DESCRIPTION(DRIVER_DESC);
5432 MODULE_LICENSE("GPL");
5433 MODULE_VERSION(DRIVER_VERSION);