drivers/net/wan/fsl_ucc_hdlc.c

   1 /* Freescale QUICC Engine HDLC Device Driver
   2  *
   3  * Copyright 2016 Freescale Semiconductor Inc.
   4  *
   5  * This program is free software; you can redistribute  it and/or modify it
   6  * under  the terms of  the GNU General  Public License as published by the
   7  * Free Software Foundation;  either version 2 of the  License, or (at your
   8  * option) any later version.
   9  */
  10
  11 #include <linux/delay.h>
  12 #include <linux/dma-mapping.h>
  13 #include <linux/hdlc.h>
  14 #include <linux/init.h>
  15 #include <linux/interrupt.h>
  16 #include <linux/io.h>
  17 #include <linux/irq.h>
  18 #include <linux/kernel.h>
  19 #include <linux/module.h>
  20 #include <linux/netdevice.h>
  21 #include <linux/of_address.h>
  22 #include <linux/of_irq.h>
  23 #include <linux/of_platform.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/sched.h>
  26 #include <linux/skbuff.h>
  27 #include <linux/slab.h>
  28 #include <linux/spinlock.h>
  29 #include <linux/stddef.h>
  30 #include <soc/fsl/qe/qe_tdm.h>
  31 #include <uapi/linux/if_arp.h>
  32
  33 #include "fsl_ucc_hdlc.h"
  34
  35 #define DRV_DESC "Freescale QE UCC HDLC Driver"
  36 #define DRV_NAME "ucc_hdlc"
  37
  38 #define TDM_PPPOHT_SLIC_MAXIN
  39
  40 static struct ucc_tdm_info utdm_primary_info = {
  41         .uf_info = {
  42                 .tsa = 0,
  43                 .cdp = 0,
  44                 .cds = 1,
  45                 .ctsp = 1,
  46                 .ctss = 1,
  47                 .revd = 0,
  48                 .urfs = 256,
  49                 .utfs = 256,
  50                 .urfet = 128,
  51                 .urfset = 192,
  52                 .utfet = 128,
  53                 .utftt = 0x40,
  54                 .ufpt = 256,
  55                 .mode = UCC_FAST_PROTOCOL_MODE_HDLC,
  56                 .ttx_trx = UCC_FAST_GUMR_TRANSPARENT_TTX_TRX_NORMAL,
  57                 .tenc = UCC_FAST_TX_ENCODING_NRZ,
  58                 .renc = UCC_FAST_RX_ENCODING_NRZ,
  59                 .tcrc = UCC_FAST_16_BIT_CRC,
  60                 .synl = UCC_FAST_SYNC_LEN_NOT_USED,
  61         },
  62
  63         .si_info = {
  64 #ifdef TDM_PPPOHT_SLIC_MAXIN
  65                 .simr_rfsd = 1,
  66                 .simr_tfsd = 2,
  67 #else
  68                 .simr_rfsd = 0,
  69                 .simr_tfsd = 0,
  70 #endif
  71                 .simr_crt = 0,
  72                 .simr_sl = 0,
  73                 .simr_ce = 1,
  74                 .simr_fe = 1,
  75                 .simr_gm = 0,
  76         },
  77 };
  78
  79 static struct ucc_tdm_info utdm_info[MAX_HDLC_NUM];
  80
  81 static int uhdlc_init(struct ucc_hdlc_private *priv)
  82 {
  83         struct ucc_tdm_info *ut_info;
  84         struct ucc_fast_info *uf_info;
  85         u32 cecr_subblock;
  86         u16 bd_status;
  87         int ret, i;
  88         void *bd_buffer;
  89         dma_addr_t bd_dma_addr;
  90         u32 riptr;
  91         u32 tiptr;
  92         u32 gumr;
  93
  94         ut_info = priv->ut_info;
  95         uf_info = &ut_info->uf_info;
  96
  97         if (priv->tsa) {
  98                 uf_info->tsa = 1;
  99                 uf_info->ctsp = 1;
 100         }
 101
 102         /* This sets HPM register in CMXUCR register which configures a
 103          * open drain connected HDLC bus
 104          */
 105         if (priv->hdlc_bus)
 106                 uf_info->brkpt_support = 1;
 107
 108         uf_info->uccm_mask = ((UCC_HDLC_UCCE_RXB | UCC_HDLC_UCCE_RXF |
 109                                 UCC_HDLC_UCCE_TXB) << 16);
 110
 111         ret = ucc_fast_init(uf_info, &priv->uccf);
 112         if (ret) {
 113                 dev_err(priv->dev, "Failed to init uccf.");
 114                 return ret;
 115         }
 116
 117         priv->uf_regs = priv->uccf->uf_regs;
 118         ucc_fast_disable(priv->uccf, COMM_DIR_RX | COMM_DIR_TX);
 119
 120         /* Loopback mode */
 121         if (priv->loopback) {
 122                 dev_info(priv->dev, "Loopback Mode\n");
 123                 /* use the same clock when work in loopback */
 124                 qe_setbrg(ut_info->uf_info.rx_clock, 20000000, 1);
 125
 126                 gumr = ioread32be(&priv->uf_regs->gumr);
 127                 gumr |= (UCC_FAST_GUMR_LOOPBACK | UCC_FAST_GUMR_CDS |
 128                          UCC_FAST_GUMR_TCI);
 129                 gumr &= ~(UCC_FAST_GUMR_CTSP | UCC_FAST_GUMR_RSYN);
 130                 iowrite32be(gumr, &priv->uf_regs->gumr);
 131         }
 132
 133         /* Initialize SI */
 134         if (priv->tsa)
 135                 ucc_tdm_init(priv->utdm, priv->ut_info);
 136
 137         /* Write to QE CECR, UCCx channel to Stop Transmission */
 138         cecr_subblock = ucc_fast_get_qe_cr_subblock(uf_info->ucc_num);
 139         ret = qe_issue_cmd(QE_STOP_TX, cecr_subblock,
 140                            QE_CR_PROTOCOL_UNSPECIFIED, 0);
 141
 142         /* Set UPSMR normal mode (need fixed)*/
 143         iowrite32be(0, &priv->uf_regs->upsmr);
 144
 145         /* hdlc_bus mode */
 146         if (priv->hdlc_bus) {
 147                 u32 upsmr;
 148
 149                 dev_info(priv->dev, "HDLC bus Mode\n");
 150                 upsmr = ioread32be(&priv->uf_regs->upsmr);
 151
 152                 /* bus mode and retransmit enable, with collision window
 153                  * set to 8 bytes
 154                  */
 155                 upsmr |= UCC_HDLC_UPSMR_RTE | UCC_HDLC_UPSMR_BUS |
 156                                 UCC_HDLC_UPSMR_CW8;
 157                 iowrite32be(upsmr, &priv->uf_regs->upsmr);
 158
 159                 /* explicitly disable CDS & CTSP */
 160                 gumr = ioread32be(&priv->uf_regs->gumr);
 161                 gumr &= ~(UCC_FAST_GUMR_CDS | UCC_FAST_GUMR_CTSP);
 162                 /* set automatic sync to explicitly ignore CD signal */
 163                 gumr |= UCC_FAST_GUMR_SYNL_AUTO;
 164                 iowrite32be(gumr, &priv->uf_regs->gumr);
 165         }
 166
 167         priv->rx_ring_size = RX_BD_RING_LEN;
 168         priv->tx_ring_size = TX_BD_RING_LEN;
 169         /* Alloc Rx BD */
 170         priv->rx_bd_base = dma_alloc_coherent(priv->dev,
 171                         RX_BD_RING_LEN * sizeof(struct qe_bd),
 172                         &priv->dma_rx_bd, GFP_KERNEL);
 173
 174         if (!priv->rx_bd_base) {
 175                 dev_err(priv->dev, "Cannot allocate MURAM memory for RxBDs\n");
 176                 ret = -ENOMEM;
 177                 goto free_uccf;
 178         }
 179
 180         /* Alloc Tx BD */
 181         priv->tx_bd_base = dma_alloc_coherent(priv->dev,
 182                         TX_BD_RING_LEN * sizeof(struct qe_bd),
 183                         &priv->dma_tx_bd, GFP_KERNEL);
 184
 185         if (!priv->tx_bd_base) {
 186                 dev_err(priv->dev, "Cannot allocate MURAM memory for TxBDs\n");
 187                 ret = -ENOMEM;
 188                 goto free_rx_bd;
 189         }
 190
 191         /* Alloc parameter ram for ucc hdlc */
 192         priv->ucc_pram_offset = qe_muram_alloc(sizeof(struct ucc_hdlc_param),
 193                                 ALIGNMENT_OF_UCC_HDLC_PRAM);
 194
 195         if (IS_ERR_VALUE(priv->ucc_pram_offset)) {
 196                 dev_err(priv->dev, "Can not allocate MURAM for hdlc parameter.\n");
 197                 ret = -ENOMEM;
 198                 goto free_tx_bd;
 199         }
 200
 201         priv->rx_skbuff = kcalloc(priv->rx_ring_size,
 202                                   sizeof(*priv->rx_skbuff),
 203                                   GFP_KERNEL);
 204         if (!priv->rx_skbuff)
 205                 goto free_ucc_pram;
 206
 207         priv->tx_skbuff = kcalloc(priv->tx_ring_size,
 208                                   sizeof(*priv->tx_skbuff),
 209                                   GFP_KERNEL);
 210         if (!priv->tx_skbuff)
 211                 goto free_rx_skbuff;
 212
 213         priv->skb_curtx = 0;
 214         priv->skb_dirtytx = 0;
 215         priv->curtx_bd = priv->tx_bd_base;
 216         priv->dirty_tx = priv->tx_bd_base;
 217         priv->currx_bd = priv->rx_bd_base;
 218         priv->currx_bdnum = 0;
 219
 220         /* init parameter base */
 221         cecr_subblock = ucc_fast_get_qe_cr_subblock(uf_info->ucc_num);
 222         ret = qe_issue_cmd(QE_ASSIGN_PAGE_TO_DEVICE, cecr_subblock,
 223                            QE_CR_PROTOCOL_UNSPECIFIED, priv->ucc_pram_offset);
 224
 225         priv->ucc_pram = (struct ucc_hdlc_param __iomem *)
 226                                         qe_muram_addr(priv->ucc_pram_offset);
 227
 228         /* Zero out parameter ram */
 229         memset_io(priv->ucc_pram, 0, sizeof(struct ucc_hdlc_param));
 230
 231         /* Alloc riptr, tiptr */
 232         riptr = qe_muram_alloc(32, 32);
 233         if (IS_ERR_VALUE(riptr)) {
 234                 dev_err(priv->dev, "Cannot allocate MURAM mem for Receive internal temp data pointer\n");
 235                 ret = -ENOMEM;
 236                 goto free_tx_skbuff;
 237         }
 238
 239         tiptr = qe_muram_alloc(32, 32);
 240         if (IS_ERR_VALUE(tiptr)) {
 241                 dev_err(priv->dev, "Cannot allocate MURAM mem for Transmit internal temp data pointer\n");
 242                 ret = -ENOMEM;
 243                 goto free_riptr;
 244         }
 245
 246         /* Set RIPTR, TIPTR */
 247         iowrite16be(riptr, &priv->ucc_pram->riptr);
 248         iowrite16be(tiptr, &priv->ucc_pram->tiptr);
 249
 250         /* Set MRBLR */
 251         iowrite16be(MAX_RX_BUF_LENGTH, &priv->ucc_pram->mrblr);
 252
 253         /* Set RBASE, TBASE */
 254         iowrite32be(priv->dma_rx_bd, &priv->ucc_pram->rbase);
 255         iowrite32be(priv->dma_tx_bd, &priv->ucc_pram->tbase);
 256
 257         /* Set RSTATE, TSTATE */
 258         iowrite32be(BMR_GBL | BMR_BIG_ENDIAN, &priv->ucc_pram->rstate);
 259         iowrite32be(BMR_GBL | BMR_BIG_ENDIAN, &priv->ucc_pram->tstate);
 260
 261         /* Set C_MASK, C_PRES for 16bit CRC */
 262         iowrite32be(CRC_16BIT_MASK, &priv->ucc_pram->c_mask);
 263         iowrite32be(CRC_16BIT_PRES, &priv->ucc_pram->c_pres);
 264
 265         iowrite16be(MAX_FRAME_LENGTH, &priv->ucc_pram->mflr);
 266         iowrite16be(DEFAULT_RFTHR, &priv->ucc_pram->rfthr);
 267         iowrite16be(DEFAULT_RFTHR, &priv->ucc_pram->rfcnt);
 268         iowrite16be(priv->hmask, &priv->ucc_pram->hmask);
 269         iowrite16be(DEFAULT_HDLC_ADDR, &priv->ucc_pram->haddr1);
 270         iowrite16be(DEFAULT_HDLC_ADDR, &priv->ucc_pram->haddr2);
 271         iowrite16be(DEFAULT_HDLC_ADDR, &priv->ucc_pram->haddr3);
 272         iowrite16be(DEFAULT_HDLC_ADDR, &priv->ucc_pram->haddr4);
 273
 274         /* Get BD buffer */
 275         bd_buffer = dma_zalloc_coherent(priv->dev,
 276                                         (RX_BD_RING_LEN + TX_BD_RING_LEN) *
 277                                         MAX_RX_BUF_LENGTH,
 278                                         &bd_dma_addr, GFP_KERNEL);
 279
 280         if (!bd_buffer) {
 281                 dev_err(priv->dev, "Could not allocate buffer descriptors\n");
 282                 ret = -ENOMEM;
 283                 goto free_tiptr;
 284         }
 285
 286         priv->rx_buffer = bd_buffer;
 287         priv->tx_buffer = bd_buffer + RX_BD_RING_LEN * MAX_RX_BUF_LENGTH;
 288
 289         priv->dma_rx_addr = bd_dma_addr;
 290         priv->dma_tx_addr = bd_dma_addr + RX_BD_RING_LEN * MAX_RX_BUF_LENGTH;
 291
 292         for (i = 0; i < RX_BD_RING_LEN; i++) {
 293                 if (i < (RX_BD_RING_LEN - 1))
 294                         bd_status = R_E_S | R_I_S;
 295                 else
 296                         bd_status = R_E_S | R_I_S | R_W_S;
 297
 298                 iowrite16be(bd_status, &priv->rx_bd_base[i].status);
 299                 iowrite32be(priv->dma_rx_addr + i * MAX_RX_BUF_LENGTH,
 300                             &priv->rx_bd_base[i].buf);
 301         }
 302
 303         for (i = 0; i < TX_BD_RING_LEN; i++) {
 304                 if (i < (TX_BD_RING_LEN - 1))
 305                         bd_status =  T_I_S | T_TC_S;
 306                 else
 307                         bd_status =  T_I_S | T_TC_S | T_W_S;
 308
 309                 iowrite16be(bd_status, &priv->tx_bd_base[i].status);
 310                 iowrite32be(priv->dma_tx_addr + i * MAX_RX_BUF_LENGTH,
 311                             &priv->tx_bd_base[i].buf);
 312         }
 313
 314         return 0;
 315
 316 free_tiptr:
 317         qe_muram_free(tiptr);
 318 free_riptr:
 319         qe_muram_free(riptr);
 320 free_tx_skbuff:
 321         kfree(priv->tx_skbuff);
 322 free_rx_skbuff:
 323         kfree(priv->rx_skbuff);
 324 free_ucc_pram:
 325         qe_muram_free(priv->ucc_pram_offset);
 326 free_tx_bd:
 327         dma_free_coherent(priv->dev,
 328                           TX_BD_RING_LEN * sizeof(struct qe_bd),
 329                           priv->tx_bd_base, priv->dma_tx_bd);
 330 free_rx_bd:
 331         dma_free_coherent(priv->dev,
 332                           RX_BD_RING_LEN * sizeof(struct qe_bd),
 333                           priv->rx_bd_base, priv->dma_rx_bd);
 334 free_uccf:
 335         ucc_fast_free(priv->uccf);
 336
 337         return ret;
 338 }
 339
 340 static netdev_tx_t ucc_hdlc_tx(struct sk_buff *skb, struct net_device *dev)
 341 {
 342         hdlc_device *hdlc = dev_to_hdlc(dev);
 343         struct ucc_hdlc_private *priv = (struct ucc_hdlc_private *)hdlc->priv;
 344         struct qe_bd __iomem *bd;
 345         u16 bd_status;
 346         unsigned long flags;
 347         u16 *proto_head;
 348
 349         switch (dev->type) {
 350         case ARPHRD_RAWHDLC:
 351                 if (skb_headroom(skb) < HDLC_HEAD_LEN) {
 352                         dev->stats.tx_dropped++;
 353                         dev_kfree_skb(skb);
 354                         netdev_err(dev, "No enough space for hdlc head\n");
 355                         return -ENOMEM;
 356                 }
 357
 358                 skb_push(skb, HDLC_HEAD_LEN);
 359
 360                 proto_head = (u16 *)skb->data;
 361                 *proto_head = htons(DEFAULT_HDLC_HEAD);
 362
 363                 dev->stats.tx_bytes += skb->len;
 364                 break;
 365
 366         case ARPHRD_PPP:
 367                 proto_head = (u16 *)skb->data;
 368                 if (*proto_head != htons(DEFAULT_PPP_HEAD)) {
 369                         dev->stats.tx_dropped++;
 370                         dev_kfree_skb(skb);
 371                         netdev_err(dev, "Wrong ppp header\n");
 372                         return -ENOMEM;
 373                 }
 374
 375                 dev->stats.tx_bytes += skb->len;
 376                 break;
 377
 378         case ARPHRD_ETHER:
 379                 dev->stats.tx_bytes += skb->len;
 380                 break;
 381
 382         default:
 383                 dev->stats.tx_dropped++;
 384                 dev_kfree_skb(skb);
 385                 return -ENOMEM;
 386         }
 387         spin_lock_irqsave(&priv->lock, flags);
 388
 389         /* Start from the next BD that should be filled */
 390         bd = priv->curtx_bd;
 391         bd_status = ioread16be(&bd->status);
 392         /* Save the skb pointer so we can free it later */
 393         priv->tx_skbuff[priv->skb_curtx] = skb;
 394
 395         /* Update the current skb pointer (wrapping if this was the last) */
 396         priv->skb_curtx =
 397             (priv->skb_curtx + 1) & TX_RING_MOD_MASK(TX_BD_RING_LEN);
 398
 399         /* copy skb data to tx buffer for sdma processing */
 400         memcpy(priv->tx_buffer + (be32_to_cpu(bd->buf) - priv->dma_tx_addr),
 401                skb->data, skb->len);
 402
 403         /* set bd status and length */
 404         bd_status = (bd_status & T_W_S) | T_R_S | T_I_S | T_L_S | T_TC_S;
 405
 406         iowrite16be(skb->len, &bd->length);
 407         iowrite16be(bd_status, &bd->status);
 408
 409         /* Move to next BD in the ring */
 410         if (!(bd_status & T_W_S))
 411                 bd += 1;
 412         else
 413                 bd = priv->tx_bd_base;
 414
 415         if (bd == priv->dirty_tx) {
 416                 if (!netif_queue_stopped(dev))
 417                         netif_stop_queue(dev);
 418         }
 419
 420         priv->curtx_bd = bd;
 421
 422         spin_unlock_irqrestore(&priv->lock, flags);
 423
 424         return NETDEV_TX_OK;
 425 }
 426
 427 static int hdlc_tx_done(struct ucc_hdlc_private *priv)
 428 {
 429         /* Start from the next BD that should be filled */
 430         struct net_device *dev = priv->ndev;
 431         struct qe_bd *bd;               /* BD pointer */
 432         u16 bd_status;
 433
 434         bd = priv->dirty_tx;
 435         bd_status = ioread16be(&bd->status);
 436
 437         /* Normal processing. */
 438         while ((bd_status & T_R_S) == 0) {
 439                 struct sk_buff *skb;
 440
 441                 /* BD contains already transmitted buffer.   */
 442                 /* Handle the transmitted buffer and release */
 443                 /* the BD to be used with the current frame  */
 444
 445                 skb = priv->tx_skbuff[priv->skb_dirtytx];
 446                 if (!skb)
 447                         break;
 448                 dev->stats.tx_packets++;
 449                 memset(priv->tx_buffer +
 450                        (be32_to_cpu(bd->buf) - priv->dma_tx_addr),
 451                        0, skb->len);
 452                 dev_kfree_skb_irq(skb);
 453
 454                 priv->tx_skbuff[priv->skb_dirtytx] = NULL;
 455                 priv->skb_dirtytx =
 456                     (priv->skb_dirtytx +
 457                      1) & TX_RING_MOD_MASK(TX_BD_RING_LEN);
 458
 459                 /* We freed a buffer, so now we can restart transmission */
 460                 if (netif_queue_stopped(dev))
 461                         netif_wake_queue(dev);
 462
 463                 /* Advance the confirmation BD pointer */
 464                 if (!(bd_status & T_W_S))
 465                         bd += 1;
 466                 else
 467                         bd = priv->tx_bd_base;
 468                 bd_status = ioread16be(&bd->status);
 469         }
 470         priv->dirty_tx = bd;
 471
 472         return 0;
 473 }
 474
 475 static int hdlc_rx_done(struct ucc_hdlc_private *priv, int rx_work_limit)
 476 {
 477         struct net_device *dev = priv->ndev;
 478         struct sk_buff *skb = NULL;
 479         hdlc_device *hdlc = dev_to_hdlc(dev);
 480         struct qe_bd *bd;
 481         u16 bd_status;
 482         u16 length, howmany = 0;
 483         u8 *bdbuffer;
 484
 485         bd = priv->currx_bd;
 486         bd_status = ioread16be(&bd->status);
 487
 488         /* while there are received buffers and BD is full (~R_E) */
 489         while (!((bd_status & (R_E_S)) || (--rx_work_limit < 0))) {
 490                 if (bd_status & R_OV_S)
 491                         dev->stats.rx_over_errors++;
 492                 if (bd_status & R_CR_S) {
 493                         dev->stats.rx_crc_errors++;
 494                         dev->stats.rx_dropped++;
 495                         goto recycle;
 496                 }
 497                 bdbuffer = priv->rx_buffer +
 498                         (priv->currx_bdnum * MAX_RX_BUF_LENGTH);
 499                 length = ioread16be(&bd->length);
 500
 501                 switch (dev->type) {
 502                 case ARPHRD_RAWHDLC:
 503                         bdbuffer += HDLC_HEAD_LEN;
 504                         length -= (HDLC_HEAD_LEN + HDLC_CRC_SIZE);
 505
 506                         skb = dev_alloc_skb(length);
 507                         if (!skb) {
 508                                 dev->stats.rx_dropped++;
 509                                 return -ENOMEM;
 510                         }
 511
 512                         skb_put(skb, length);
 513                         skb->len = length;
 514                         skb->dev = dev;
 515                         memcpy(skb->data, bdbuffer, length);
 516                         break;
 517
 518                 case ARPHRD_PPP:
 519                 case ARPHRD_ETHER:
 520                         length -= HDLC_CRC_SIZE;
 521
 522                         skb = dev_alloc_skb(length);
 523                         if (!skb) {
 524                                 dev->stats.rx_dropped++;
 525                                 return -ENOMEM;
 526                         }
 527
 528                         skb_put(skb, length);
 529                         skb->len = length;
 530                         skb->dev = dev;
 531                         memcpy(skb->data, bdbuffer, length);
 532                         break;
 533                 }
 534
 535                 dev->stats.rx_packets++;
 536                 dev->stats.rx_bytes += skb->len;
 537                 howmany++;
 538                 if (hdlc->proto)
 539                         skb->protocol = hdlc_type_trans(skb, dev);
 540                 netif_receive_skb(skb);
 541
 542 recycle:
 543                 iowrite16be(bd_status | R_E_S | R_I_S, &bd->status);
 544
 545                 /* update to point at the next bd */
 546                 if (bd_status & R_W_S) {
 547                         priv->currx_bdnum = 0;
 548                         bd = priv->rx_bd_base;
 549                 } else {
 550                         if (priv->currx_bdnum < (RX_BD_RING_LEN - 1))
 551                                 priv->currx_bdnum += 1;
 552                         else
 553                                 priv->currx_bdnum = RX_BD_RING_LEN - 1;
 554
 555                         bd += 1;
 556                 }
 557
 558                 bd_status = ioread16be(&bd->status);
 559         }
 560
 561         priv->currx_bd = bd;
 562         return howmany;
 563 }
 564
 565 static int ucc_hdlc_poll(struct napi_struct *napi, int budget)
 566 {
 567         struct ucc_hdlc_private *priv = container_of(napi,
 568                                                      struct ucc_hdlc_private,
 569                                                      napi);
 570         int howmany;
 571
 572         /* Tx event processing */
 573         spin_lock(&priv->lock);
 574         hdlc_tx_done(priv);
 575         spin_unlock(&priv->lock);
 576
 577         howmany = 0;
 578         howmany += hdlc_rx_done(priv, budget - howmany);
 579
 580         if (howmany < budget) {
 581                 napi_complete_done(napi, howmany);
 582                 qe_setbits32(priv->uccf->p_uccm,
 583                              (UCCE_HDLC_RX_EVENTS | UCCE_HDLC_TX_EVENTS) << 16);
 584         }
 585
 586         return howmany;
 587 }
 588
 589 static irqreturn_t ucc_hdlc_irq_handler(int irq, void *dev_id)
 590 {
 591         struct ucc_hdlc_private *priv = (struct ucc_hdlc_private *)dev_id;
 592         struct net_device *dev = priv->ndev;
 593         struct ucc_fast_private *uccf;
 594         struct ucc_tdm_info *ut_info;
 595         u32 ucce;
 596         u32 uccm;
 597
 598         ut_info = priv->ut_info;
 599         uccf = priv->uccf;
 600
 601         ucce = ioread32be(uccf->p_ucce);
 602         uccm = ioread32be(uccf->p_uccm);
 603         ucce &= uccm;
 604         iowrite32be(ucce, uccf->p_ucce);
 605         if (!ucce)
 606                 return IRQ_NONE;
 607
 608         if ((ucce >> 16) & (UCCE_HDLC_RX_EVENTS | UCCE_HDLC_TX_EVENTS)) {
 609                 if (napi_schedule_prep(&priv->napi)) {
 610                         uccm &= ~((UCCE_HDLC_RX_EVENTS | UCCE_HDLC_TX_EVENTS)
 611                                   << 16);
 612                         iowrite32be(uccm, uccf->p_uccm);
 613                         __napi_schedule(&priv->napi);
 614                 }
 615         }
 616
 617         /* Errors and other events */
 618         if (ucce >> 16 & UCC_HDLC_UCCE_BSY)
 619                 dev->stats.rx_errors++;
 620         if (ucce >> 16 & UCC_HDLC_UCCE_TXE)
 621                 dev->stats.tx_errors++;
 622
 623         return IRQ_HANDLED;
 624 }
 625
 626 static int uhdlc_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
 627 {
 628         const size_t size = sizeof(te1_settings);
 629         te1_settings line;
 630         struct ucc_hdlc_private *priv = netdev_priv(dev);
 631
 632         if (cmd != SIOCWANDEV)
 633                 return hdlc_ioctl(dev, ifr, cmd);
 634
 635         switch (ifr->ifr_settings.type) {
 636         case IF_GET_IFACE:
 637                 ifr->ifr_settings.type = IF_IFACE_E1;
 638                 if (ifr->ifr_settings.size < size) {
 639                         ifr->ifr_settings.size = size; /* data size wanted */
 640                         return -ENOBUFS;
 641                 }
 642                 memset(&line, 0, sizeof(line));
 643                 line.clock_type = priv->clocking;
 644
 645                 if (copy_to_user(ifr->ifr_settings.ifs_ifsu.sync, &line, size))
 646                         return -EFAULT;
 647                 return 0;
 648
 649         default:
 650                 return hdlc_ioctl(dev, ifr, cmd);
 651         }
 652 }
 653
 654 static int uhdlc_open(struct net_device *dev)
 655 {
 656         u32 cecr_subblock;
 657         hdlc_device *hdlc = dev_to_hdlc(dev);
 658         struct ucc_hdlc_private *priv = hdlc->priv;
 659         struct ucc_tdm *utdm = priv->utdm;
 660
 661         if (priv->hdlc_busy != 1) {
 662                 if (request_irq(priv->ut_info->uf_info.irq,
 663                                 ucc_hdlc_irq_handler, 0, "hdlc", priv))
 664                         return -ENODEV;
 665
 666                 cecr_subblock = ucc_fast_get_qe_cr_subblock(
 667                                         priv->ut_info->uf_info.ucc_num);
 668
 669                 qe_issue_cmd(QE_INIT_TX_RX, cecr_subblock,
 670                              QE_CR_PROTOCOL_UNSPECIFIED, 0);
 671
 672                 ucc_fast_enable(priv->uccf, COMM_DIR_RX | COMM_DIR_TX);
 673
 674                 /* Enable the TDM port */
 675                 if (priv->tsa)
 676                         utdm->si_regs->siglmr1_h |= (0x1 << utdm->tdm_port);
 677
 678                 priv->hdlc_busy = 1;
 679                 netif_device_attach(priv->ndev);
 680                 napi_enable(&priv->napi);
 681                 netif_start_queue(dev);
 682                 hdlc_open(dev);
 683         }
 684
 685         return 0;
 686 }
 687
 688 static void uhdlc_memclean(struct ucc_hdlc_private *priv)
 689 {
 690         qe_muram_free(priv->ucc_pram->riptr);
 691         qe_muram_free(priv->ucc_pram->tiptr);
 692
 693         if (priv->rx_bd_base) {
 694                 dma_free_coherent(priv->dev,
 695                                   RX_BD_RING_LEN * sizeof(struct qe_bd),
 696                                   priv->rx_bd_base, priv->dma_rx_bd);
 697
 698                 priv->rx_bd_base = NULL;
 699                 priv->dma_rx_bd = 0;
 700         }
 701
 702         if (priv->tx_bd_base) {
 703                 dma_free_coherent(priv->dev,
 704                                   TX_BD_RING_LEN * sizeof(struct qe_bd),
 705                                   priv->tx_bd_base, priv->dma_tx_bd);
 706
 707                 priv->tx_bd_base = NULL;
 708                 priv->dma_tx_bd = 0;
 709         }
 710
 711         if (priv->ucc_pram) {
 712                 qe_muram_free(priv->ucc_pram_offset);
 713                 priv->ucc_pram = NULL;
 714                 priv->ucc_pram_offset = 0;
 715          }
 716
 717         kfree(priv->rx_skbuff);
 718         priv->rx_skbuff = NULL;
 719
 720         kfree(priv->tx_skbuff);
 721         priv->tx_skbuff = NULL;
 722
 723         if (priv->uf_regs) {
 724                 iounmap(priv->uf_regs);
 725                 priv->uf_regs = NULL;
 726         }
 727
 728         if (priv->uccf) {
 729                 ucc_fast_free(priv->uccf);
 730                 priv->uccf = NULL;
 731         }
 732
 733         if (priv->rx_buffer) {
 734                 dma_free_coherent(priv->dev,
 735                                   RX_BD_RING_LEN * MAX_RX_BUF_LENGTH,
 736                                   priv->rx_buffer, priv->dma_rx_addr);
 737                 priv->rx_buffer = NULL;
 738                 priv->dma_rx_addr = 0;
 739         }
 740
 741         if (priv->tx_buffer) {
 742                 dma_free_coherent(priv->dev,
 743                                   TX_BD_RING_LEN * MAX_RX_BUF_LENGTH,
 744                                   priv->tx_buffer, priv->dma_tx_addr);
 745                 priv->tx_buffer = NULL;
 746                 priv->dma_tx_addr = 0;
 747         }
 748 }
 749
 750 static int uhdlc_close(struct net_device *dev)
 751 {
 752         struct ucc_hdlc_private *priv = dev_to_hdlc(dev)->priv;
 753         struct ucc_tdm *utdm = priv->utdm;
 754         u32 cecr_subblock;
 755
 756         napi_disable(&priv->napi);
 757         cecr_subblock = ucc_fast_get_qe_cr_subblock(
 758                                 priv->ut_info->uf_info.ucc_num);
 759
 760         qe_issue_cmd(QE_GRACEFUL_STOP_TX, cecr_subblock,
 761                      (u8)QE_CR_PROTOCOL_UNSPECIFIED, 0);
 762         qe_issue_cmd(QE_CLOSE_RX_BD, cecr_subblock,
 763                      (u8)QE_CR_PROTOCOL_UNSPECIFIED, 0);
 764
 765         if (priv->tsa)
 766                 utdm->si_regs->siglmr1_h &= ~(0x1 << utdm->tdm_port);
 767
 768         ucc_fast_disable(priv->uccf, COMM_DIR_RX | COMM_DIR_TX);
 769
 770         free_irq(priv->ut_info->uf_info.irq, priv);
 771         netif_stop_queue(dev);
 772         priv->hdlc_busy = 0;
 773
 774         return 0;
 775 }
 776
 777 static int ucc_hdlc_attach(struct net_device *dev, unsigned short encoding,
 778                            unsigned short parity)
 779 {
 780         struct ucc_hdlc_private *priv = dev_to_hdlc(dev)->priv;
 781
 782         if (encoding != ENCODING_NRZ &&
 783             encoding != ENCODING_NRZI)
 784                 return -EINVAL;
 785
 786         if (parity != PARITY_NONE &&
 787             parity != PARITY_CRC32_PR1_CCITT &&
 788             parity != PARITY_CRC16_PR0_CCITT &&
 789             parity != PARITY_CRC16_PR1_CCITT)
 790                 return -EINVAL;
 791
 792         priv->encoding = encoding;
 793         priv->parity = parity;
 794
 795         return 0;
 796 }
 797
 798 #ifdef CONFIG_PM
 799 static void store_clk_config(struct ucc_hdlc_private *priv)
 800 {
 801         struct qe_mux *qe_mux_reg = &qe_immr->qmx;
 802
 803         /* store si clk */
 804         priv->cmxsi1cr_h = ioread32be(&qe_mux_reg->cmxsi1cr_h);
 805         priv->cmxsi1cr_l = ioread32be(&qe_mux_reg->cmxsi1cr_l);
 806
 807         /* store si sync */
 808         priv->cmxsi1syr = ioread32be(&qe_mux_reg->cmxsi1syr);
 809
 810         /* store ucc clk */
 811         memcpy_fromio(priv->cmxucr, qe_mux_reg->cmxucr, 4 * sizeof(u32));
 812 }
 813
 814 static void resume_clk_config(struct ucc_hdlc_private *priv)
 815 {
 816         struct qe_mux *qe_mux_reg = &qe_immr->qmx;
 817
 818         memcpy_toio(qe_mux_reg->cmxucr, priv->cmxucr, 4 * sizeof(u32));
 819
 820         iowrite32be(priv->cmxsi1cr_h, &qe_mux_reg->cmxsi1cr_h);
 821         iowrite32be(priv->cmxsi1cr_l, &qe_mux_reg->cmxsi1cr_l);
 822
 823         iowrite32be(priv->cmxsi1syr, &qe_mux_reg->cmxsi1syr);
 824 }
 825
 826 static int uhdlc_suspend(struct device *dev)
 827 {
 828         struct ucc_hdlc_private *priv = dev_get_drvdata(dev);
 829         struct ucc_tdm_info *ut_info;
 830         struct ucc_fast __iomem *uf_regs;
 831
 832         if (!priv)
 833                 return -EINVAL;
 834
 835         if (!netif_running(priv->ndev))
 836                 return 0;
 837
 838         netif_device_detach(priv->ndev);
 839         napi_disable(&priv->napi);
 840
 841         ut_info = priv->ut_info;
 842         uf_regs = priv->uf_regs;
 843
 844         /* backup gumr guemr*/
 845         priv->gumr = ioread32be(&uf_regs->gumr);
 846         priv->guemr = ioread8(&uf_regs->guemr);
 847
 848         priv->ucc_pram_bak = kmalloc(sizeof(*priv->ucc_pram_bak),
 849                                         GFP_KERNEL);
 850         if (!priv->ucc_pram_bak)
 851                 return -ENOMEM;
 852
 853         /* backup HDLC parameter */
 854         memcpy_fromio(priv->ucc_pram_bak, priv->ucc_pram,
 855                       sizeof(struct ucc_hdlc_param));
 856
 857         /* store the clk configuration */
 858         store_clk_config(priv);
 859
 860         /* save power */
 861         ucc_fast_disable(priv->uccf, COMM_DIR_RX | COMM_DIR_TX);
 862
 863         return 0;
 864 }
 865
 866 static int uhdlc_resume(struct device *dev)
 867 {
 868         struct ucc_hdlc_private *priv = dev_get_drvdata(dev);
 869         struct ucc_tdm *utdm;
 870         struct ucc_tdm_info *ut_info;
 871         struct ucc_fast __iomem *uf_regs;
 872         struct ucc_fast_private *uccf;
 873         struct ucc_fast_info *uf_info;
 874         int ret, i;
 875         u32 cecr_subblock;
 876         u16 bd_status;
 877
 878         if (!priv)
 879                 return -EINVAL;
 880
 881         if (!netif_running(priv->ndev))
 882                 return 0;
 883
 884         utdm = priv->utdm;
 885         ut_info = priv->ut_info;
 886         uf_info = &ut_info->uf_info;
 887         uf_regs = priv->uf_regs;
 888         uccf = priv->uccf;
 889
 890         /* restore gumr guemr */
 891         iowrite8(priv->guemr, &uf_regs->guemr);
 892         iowrite32be(priv->gumr, &uf_regs->gumr);
 893
 894         /* Set Virtual Fifo registers */
 895         iowrite16be(uf_info->urfs, &uf_regs->urfs);
 896         iowrite16be(uf_info->urfet, &uf_regs->urfet);
 897         iowrite16be(uf_info->urfset, &uf_regs->urfset);
 898         iowrite16be(uf_info->utfs, &uf_regs->utfs);
 899         iowrite16be(uf_info->utfet, &uf_regs->utfet);
 900         iowrite16be(uf_info->utftt, &uf_regs->utftt);
 901         /* utfb, urfb are offsets from MURAM base */
 902         iowrite32be(uccf->ucc_fast_tx_virtual_fifo_base_offset, &uf_regs->utfb);
 903         iowrite32be(uccf->ucc_fast_rx_virtual_fifo_base_offset, &uf_regs->urfb);
 904
 905         /* Rx Tx and sync clock routing */
 906         resume_clk_config(priv);
 907
 908         iowrite32be(uf_info->uccm_mask, &uf_regs->uccm);
 909         iowrite32be(0xffffffff, &uf_regs->ucce);
 910
 911         ucc_fast_disable(priv->uccf, COMM_DIR_RX | COMM_DIR_TX);
 912
 913         /* rebuild SIRAM */
 914         if (priv->tsa)
 915                 ucc_tdm_init(priv->utdm, priv->ut_info);
 916
 917         /* Write to QE CECR, UCCx channel to Stop Transmission */
 918         cecr_subblock = ucc_fast_get_qe_cr_subblock(uf_info->ucc_num);
 919         ret = qe_issue_cmd(QE_STOP_TX, cecr_subblock,
 920                            (u8)QE_CR_PROTOCOL_UNSPECIFIED, 0);
 921
 922         /* Set UPSMR normal mode */
 923         iowrite32be(0, &uf_regs->upsmr);
 924
 925         /* init parameter base */
 926         cecr_subblock = ucc_fast_get_qe_cr_subblock(uf_info->ucc_num);
 927         ret = qe_issue_cmd(QE_ASSIGN_PAGE_TO_DEVICE, cecr_subblock,
 928                            QE_CR_PROTOCOL_UNSPECIFIED, priv->ucc_pram_offset);
 929
 930         priv->ucc_pram = (struct ucc_hdlc_param __iomem *)
 931                                 qe_muram_addr(priv->ucc_pram_offset);
 932
 933         /* restore ucc parameter */
 934         memcpy_toio(priv->ucc_pram, priv->ucc_pram_bak,
 935                     sizeof(struct ucc_hdlc_param));
 936         kfree(priv->ucc_pram_bak);
 937
 938         /* rebuild BD entry */
 939         for (i = 0; i < RX_BD_RING_LEN; i++) {
 940                 if (i < (RX_BD_RING_LEN - 1))
 941                         bd_status = R_E_S | R_I_S;
 942                 else
 943                         bd_status = R_E_S | R_I_S | R_W_S;
 944
 945                 iowrite16be(bd_status, &priv->rx_bd_base[i].status);
 946                 iowrite32be(priv->dma_rx_addr + i * MAX_RX_BUF_LENGTH,
 947                             &priv->rx_bd_base[i].buf);
 948         }
 949
 950         for (i = 0; i < TX_BD_RING_LEN; i++) {
 951                 if (i < (TX_BD_RING_LEN - 1))
 952                         bd_status =  T_I_S | T_TC_S;
 953                 else
 954                         bd_status =  T_I_S | T_TC_S | T_W_S;
 955
 956                 iowrite16be(bd_status, &priv->tx_bd_base[i].status);
 957                 iowrite32be(priv->dma_tx_addr + i * MAX_RX_BUF_LENGTH,
 958                             &priv->tx_bd_base[i].buf);
 959         }
 960
 961         /* if hdlc is busy enable TX and RX */
 962         if (priv->hdlc_busy == 1) {
 963                 cecr_subblock = ucc_fast_get_qe_cr_subblock(
 964                                         priv->ut_info->uf_info.ucc_num);
 965
 966                 qe_issue_cmd(QE_INIT_TX_RX, cecr_subblock,
 967                              (u8)QE_CR_PROTOCOL_UNSPECIFIED, 0);
 968
 969                 ucc_fast_enable(priv->uccf, COMM_DIR_RX | COMM_DIR_TX);
 970
 971                 /* Enable the TDM port */
 972                 if (priv->tsa)
 973                         utdm->si_regs->siglmr1_h |= (0x1 << utdm->tdm_port);
 974         }
 975
 976         napi_enable(&priv->napi);
 977         netif_device_attach(priv->ndev);
 978
 979         return 0;
 980 }
 981
 982 static const struct dev_pm_ops uhdlc_pm_ops = {
 983         .suspend = uhdlc_suspend,
 984         .resume = uhdlc_resume,
 985         .freeze = uhdlc_suspend,
 986         .thaw = uhdlc_resume,
 987 };
 988
 989 #define HDLC_PM_OPS (&uhdlc_pm_ops)
 990
 991 #else
 992
 993 #define HDLC_PM_OPS NULL
 994
 995 #endif
 996 static const struct net_device_ops uhdlc_ops = {
 997         .ndo_open       = uhdlc_open,
 998         .ndo_stop       = uhdlc_close,
 999         .ndo_start_xmit = hdlc_start_xmit,
1000         .ndo_do_ioctl   = uhdlc_ioctl,
1001 };
1002
1003 static int ucc_hdlc_probe(struct platform_device *pdev)
1004 {
1005         struct device_node *np = pdev->dev.of_node;
1006         struct ucc_hdlc_private *uhdlc_priv = NULL;
1007         struct ucc_tdm_info *ut_info;
1008         struct ucc_tdm *utdm = NULL;
1009         struct resource res;
1010         struct net_device *dev;
1011         hdlc_device *hdlc;
1012         int ucc_num;
1013         const char *sprop;
1014         int ret;
1015         u32 val;
1016
1017         ret = of_property_read_u32_index(np, "cell-index", 0, &val);
1018         if (ret) {
1019                 dev_err(&pdev->dev, "Invalid ucc property\n");
1020                 return -ENODEV;
1021         }
1022
1023         ucc_num = val - 1;
1024         if (ucc_num > (UCC_MAX_NUM - 1) || ucc_num < 0) {
1025                 dev_err(&pdev->dev, ": Invalid UCC num\n");
1026                 return -EINVAL;
1027         }
1028
1029         memcpy(&utdm_info[ucc_num], &utdm_primary_info,
1030                sizeof(utdm_primary_info));
1031
1032         ut_info = &utdm_info[ucc_num];
1033         ut_info->uf_info.ucc_num = ucc_num;
1034
1035         sprop = of_get_property(np, "rx-clock-name", NULL);
1036         if (sprop) {
1037                 ut_info->uf_info.rx_clock = qe_clock_source(sprop);
1038                 if ((ut_info->uf_info.rx_clock < QE_CLK_NONE) ||
1039                     (ut_info->uf_info.rx_clock > QE_CLK24)) {
1040                         dev_err(&pdev->dev, "Invalid rx-clock-name property\n");
1041                         return -EINVAL;
1042                 }
1043         } else {
1044                 dev_err(&pdev->dev, "Invalid rx-clock-name property\n");
1045                 return -EINVAL;
1046         }
1047
1048         sprop = of_get_property(np, "tx-clock-name", NULL);
1049         if (sprop) {
1050                 ut_info->uf_info.tx_clock = qe_clock_source(sprop);
1051                 if ((ut_info->uf_info.tx_clock < QE_CLK_NONE) ||
1052                     (ut_info->uf_info.tx_clock > QE_CLK24)) {
1053                         dev_err(&pdev->dev, "Invalid tx-clock-name property\n");
1054                         return -EINVAL;
1055                 }
1056         } else {
1057                 dev_err(&pdev->dev, "Invalid tx-clock-name property\n");
1058                 return -EINVAL;
1059         }
1060
1061         ret = of_address_to_resource(np, 0, &res);
1062         if (ret)
1063                 return -EINVAL;
1064
1065         ut_info->uf_info.regs = res.start;
1066         ut_info->uf_info.irq = irq_of_parse_and_map(np, 0);
1067
1068         uhdlc_priv = kzalloc(sizeof(*uhdlc_priv), GFP_KERNEL);
1069         if (!uhdlc_priv) {
1070                 return -ENOMEM;
1071         }
1072
1073         dev_set_drvdata(&pdev->dev, uhdlc_priv);
1074         uhdlc_priv->dev = &pdev->dev;
1075         uhdlc_priv->ut_info = ut_info;
1076
1077         if (of_get_property(np, "fsl,tdm-interface", NULL))
1078                 uhdlc_priv->tsa = 1;
1079
1080         if (of_get_property(np, "fsl,ucc-internal-loopback", NULL))
1081                 uhdlc_priv->loopback = 1;
1082
1083         if (of_get_property(np, "fsl,hdlc-bus", NULL))
1084                 uhdlc_priv->hdlc_bus = 1;
1085
1086         if (uhdlc_priv->tsa == 1) {
1087                 utdm = kzalloc(sizeof(*utdm), GFP_KERNEL);
1088                 if (!utdm) {
1089                         ret = -ENOMEM;
1090                         dev_err(&pdev->dev, "No mem to alloc ucc tdm data\n");
1091                         goto free_uhdlc_priv;
1092                 }
1093                 uhdlc_priv->utdm = utdm;
1094                 ret = ucc_of_parse_tdm(np, utdm, ut_info);
1095                 if (ret)
1096                         goto free_utdm;
1097         }
1098
1099         if (of_property_read_u16(np, "fsl,hmask", &uhdlc_priv->hmask))
1100                 uhdlc_priv->hmask = DEFAULT_ADDR_MASK;
1101
1102         ret = uhdlc_init(uhdlc_priv);
1103         if (ret) {
1104                 dev_err(&pdev->dev, "Failed to init uhdlc\n");
1105                 goto free_utdm;
1106         }
1107
1108         dev = alloc_hdlcdev(uhdlc_priv);
1109         if (!dev) {
1110                 ret = -ENOMEM;
1111                 pr_err("ucc_hdlc: unable to allocate memory\n");
1112                 goto undo_uhdlc_init;
1113         }
1114
1115         uhdlc_priv->ndev = dev;
1116         hdlc = dev_to_hdlc(dev);
1117         dev->tx_queue_len = 16;
1118         dev->netdev_ops = &uhdlc_ops;
1119         hdlc->attach = ucc_hdlc_attach;
1120         hdlc->xmit = ucc_hdlc_tx;
1121         netif_napi_add(dev, &uhdlc_priv->napi, ucc_hdlc_poll, 32);
1122         if (register_hdlc_device(dev)) {
1123                 ret = -ENOBUFS;
1124                 pr_err("ucc_hdlc: unable to register hdlc device\n");
1125                 free_netdev(dev);
1126                 goto free_dev;
1127         }
1128
1129         return 0;
1130
1131 free_dev:
1132         free_netdev(dev);
1133 undo_uhdlc_init:
1134 free_utdm:
1135         if (uhdlc_priv->tsa)
1136                 kfree(utdm);
1137 free_uhdlc_priv:
1138         kfree(uhdlc_priv);
1139         return ret;
1140 }
1141
1142 static int ucc_hdlc_remove(struct platform_device *pdev)
1143 {
1144         struct ucc_hdlc_private *priv = dev_get_drvdata(&pdev->dev);
1145
1146         uhdlc_memclean(priv);
1147
1148         if (priv->utdm->si_regs) {
1149                 iounmap(priv->utdm->si_regs);
1150                 priv->utdm->si_regs = NULL;
1151         }
1152
1153         if (priv->utdm->siram) {
1154                 iounmap(priv->utdm->siram);
1155                 priv->utdm->siram = NULL;
1156         }
1157         kfree(priv);
1158
1159         dev_info(&pdev->dev, "UCC based hdlc module removed\n");
1160
1161         return 0;
1162 }
1163
1164 static const struct of_device_id fsl_ucc_hdlc_of_match[] = {
1165         {
1166         .compatible = "fsl,ucc-hdlc",
1167         },
1168         {},
1169 };
1170
1171 MODULE_DEVICE_TABLE(of, fsl_ucc_hdlc_of_match);
1172
1173 static struct platform_driver ucc_hdlc_driver = {
1174         .probe  = ucc_hdlc_probe,
1175         .remove = ucc_hdlc_remove,
1176         .driver = {
1177                 .name           = DRV_NAME,
1178                 .pm             = HDLC_PM_OPS,
1179                 .of_match_table = fsl_ucc_hdlc_of_match,
1180         },
1181 };
1182
1183 module_platform_driver(ucc_hdlc_driver);
1184 MODULE_LICENSE("GPL");