2 * Copyright (c) 2005-2011 Atheros Communications Inc.
3 * Copyright (c) 2011-2017 Qualcomm Atheros, Inc.
4 * Copyright (c) 2018 The Linux Foundation. All rights reserved.
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
24 #define CE_HTT_H2T_MSG_SRC_NENTRIES 8192
26 /* Descriptor rings must be aligned to this boundary */
27 #define CE_DESC_RING_ALIGN 8
28 #define CE_SEND_FLAG_GATHER 0x00010000
31 * Copy Engine support: low-level Target-side Copy Engine API.
32 * This is a hardware access layer used by code that understands
33 * how to use copy engines.
36 struct ath10k_ce_pipe;
38 #define CE_DESC_FLAGS_GATHER (1 << 0)
39 #define CE_DESC_FLAGS_BYTE_SWAP (1 << 1)
40 #define CE_WCN3990_DESC_FLAGS_GATHER BIT(31)
42 #define CE_DESC_FLAGS_GET_MASK GENMASK(4, 0)
43 #define CE_DESC_37BIT_ADDR_MASK GENMASK_ULL(37, 0)
45 /* Following desc flags are used in QCA99X0 */
46 #define CE_DESC_FLAGS_HOST_INT_DIS (1 << 2)
47 #define CE_DESC_FLAGS_TGT_INT_DIS (1 << 3)
49 #define CE_DESC_FLAGS_META_DATA_MASK ar->hw_values->ce_desc_meta_data_mask
50 #define CE_DESC_FLAGS_META_DATA_LSB ar->hw_values->ce_desc_meta_data_lsb
55 __le16 flags; /* %CE_DESC_FLAGS_ */
60 __le16 nbytes; /* length in register map */
61 __le16 flags; /* fw_metadata_high */
62 __le32 toeplitz_hash_result;
65 #define CE_DESC_SIZE sizeof(struct ce_desc)
66 #define CE_DESC_SIZE_64 sizeof(struct ce_desc_64)
68 struct ath10k_ce_ring {
69 /* Number of entries in this ring; must be power of 2 */
70 unsigned int nentries;
71 unsigned int nentries_mask;
74 * For dest ring, this is the next index to be processed
75 * by software after it was/is received into.
77 * For src ring, this is the last descriptor that was sent
78 * and completion processed by software.
80 * Regardless of src or dest ring, this is an invariant
82 * write index >= read index >= sw_index
84 unsigned int sw_index;
86 unsigned int write_index;
88 * For src ring, this is the next index not yet processed by HW.
89 * This is a cached copy of the real HW index (read index), used
90 * for avoiding reading the HW index register more often than
92 * This extends the invariant:
93 * write index >= read index >= hw_index >= sw_index
95 * For dest ring, this is currently unused.
98 unsigned int hw_index;
100 /* Start of DMA-coherent area reserved for descriptors */
101 /* Host address space */
102 void *base_addr_owner_space_unaligned;
103 /* CE address space */
104 u32 base_addr_ce_space_unaligned;
107 * Actual start of descriptors.
108 * Aligned to descriptor-size boundary.
109 * Points into reserved DMA-coherent area, above.
111 /* Host address space */
112 void *base_addr_owner_space;
114 /* CE address space */
115 u32 base_addr_ce_space;
117 char *shadow_base_unaligned;
118 struct ce_desc *shadow_base;
121 void *per_transfer_context[0];
124 struct ath10k_ce_pipe {
128 unsigned int attr_flags;
132 void (*send_cb)(struct ath10k_ce_pipe *);
133 void (*recv_cb)(struct ath10k_ce_pipe *);
135 unsigned int src_sz_max;
136 struct ath10k_ce_ring *src_ring;
137 struct ath10k_ce_ring *dest_ring;
138 const struct ath10k_ce_ops *ops;
141 /* Copy Engine settable attributes */
144 struct ath10k_bus_ops {
145 u32 (*read32)(struct ath10k *ar, u32 offset);
146 void (*write32)(struct ath10k *ar, u32 offset, u32 value);
147 int (*get_num_banks)(struct ath10k *ar);
150 static inline struct ath10k_ce *ath10k_ce_priv(struct ath10k *ar)
152 return (struct ath10k_ce *)ar->ce_priv;
156 /* protects CE info */
158 const struct ath10k_bus_ops *bus_ops;
159 struct ath10k_ce_pipe ce_states[CE_COUNT_MAX];
162 /*==================Send====================*/
164 /* ath10k_ce_send flags */
165 #define CE_SEND_FLAG_BYTE_SWAP 1
168 * Queue a source buffer to be sent to an anonymous destination buffer.
169 * ce - which copy engine to use
170 * buffer - address of buffer
171 * nbytes - number of bytes to send
172 * transfer_id - arbitrary ID; reflected to destination
173 * flags - CE_SEND_FLAG_* values
174 * Returns 0 on success; otherwise an error status.
176 * Note: If no flags are specified, use CE's default data swap mode.
178 * Implementation note: pushes 1 buffer to Source ring
180 int ath10k_ce_send(struct ath10k_ce_pipe *ce_state,
181 void *per_transfer_send_context,
185 unsigned int transfer_id,
188 int ath10k_ce_send_nolock(struct ath10k_ce_pipe *ce_state,
189 void *per_transfer_context,
192 unsigned int transfer_id,
195 void __ath10k_ce_send_revert(struct ath10k_ce_pipe *pipe);
197 int ath10k_ce_num_free_src_entries(struct ath10k_ce_pipe *pipe);
199 /*==================Recv=======================*/
201 int __ath10k_ce_rx_num_free_bufs(struct ath10k_ce_pipe *pipe);
202 int ath10k_ce_rx_post_buf(struct ath10k_ce_pipe *pipe, void *ctx,
204 void ath10k_ce_rx_update_write_idx(struct ath10k_ce_pipe *pipe, u32 nentries);
207 /* Data is byte-swapped */
208 #define CE_RECV_FLAG_SWAPPED 1
211 * Supply data for the next completed unprocessed receive descriptor.
212 * Pops buffer from Dest ring.
214 int ath10k_ce_completed_recv_next(struct ath10k_ce_pipe *ce_state,
215 void **per_transfer_contextp,
216 unsigned int *nbytesp);
218 * Supply data for the next completed unprocessed send descriptor.
219 * Pops 1 completed send buffer from Source ring.
221 int ath10k_ce_completed_send_next(struct ath10k_ce_pipe *ce_state,
222 void **per_transfer_contextp);
224 int ath10k_ce_completed_send_next_nolock(struct ath10k_ce_pipe *ce_state,
225 void **per_transfer_contextp);
227 /*==================CE Engine Initialization=======================*/
229 int ath10k_ce_init_pipe(struct ath10k *ar, unsigned int ce_id,
230 const struct ce_attr *attr);
231 void ath10k_ce_deinit_pipe(struct ath10k *ar, unsigned int ce_id);
232 int ath10k_ce_alloc_pipe(struct ath10k *ar, int ce_id,
233 const struct ce_attr *attr);
234 void ath10k_ce_free_pipe(struct ath10k *ar, int ce_id);
236 /*==================CE Engine Shutdown=======================*/
238 * Support clean shutdown by allowing the caller to revoke
239 * receive buffers. Target DMA must be stopped before using
242 int ath10k_ce_revoke_recv_next(struct ath10k_ce_pipe *ce_state,
243 void **per_transfer_contextp,
244 dma_addr_t *bufferp);
246 int ath10k_ce_completed_recv_next_nolock(struct ath10k_ce_pipe *ce_state,
247 void **per_transfer_contextp,
248 unsigned int *nbytesp);
251 * Support clean shutdown by allowing the caller to cancel
252 * pending sends. Target DMA must be stopped before using
255 int ath10k_ce_cancel_send_next(struct ath10k_ce_pipe *ce_state,
256 void **per_transfer_contextp,
258 unsigned int *nbytesp,
259 unsigned int *transfer_idp);
261 /*==================CE Interrupt Handlers====================*/
262 void ath10k_ce_per_engine_service_any(struct ath10k *ar);
263 void ath10k_ce_per_engine_service(struct ath10k *ar, unsigned int ce_id);
264 int ath10k_ce_disable_interrupts(struct ath10k *ar);
265 void ath10k_ce_enable_interrupts(struct ath10k *ar);
266 void ath10k_ce_dump_registers(struct ath10k *ar,
267 struct ath10k_fw_crash_data *crash_data);
269 /* ce_attr.flags values */
270 /* Use NonSnooping PCIe accesses? */
271 #define CE_ATTR_NO_SNOOP 1
273 /* Byte swap data words */
274 #define CE_ATTR_BYTE_SWAP_DATA 2
276 /* Swizzle descriptors? */
277 #define CE_ATTR_SWIZZLE_DESCRIPTORS 4
279 /* no interrupt on copy completion */
280 #define CE_ATTR_DIS_INTR 8
282 /* Attributes of an instance of a Copy Engine */
284 /* CE_ATTR_* values */
287 /* #entries in source ring - Must be a power of 2 */
288 unsigned int src_nentries;
291 * Max source send size for this CE.
292 * This is also the minimum size of a destination buffer.
294 unsigned int src_sz_max;
296 /* #entries in destination ring - Must be a power of 2 */
297 unsigned int dest_nentries;
299 void (*send_cb)(struct ath10k_ce_pipe *);
300 void (*recv_cb)(struct ath10k_ce_pipe *);
303 struct ath10k_ce_ops {
304 struct ath10k_ce_ring *(*ce_alloc_src_ring)(struct ath10k *ar,
306 const struct ce_attr *attr);
307 struct ath10k_ce_ring *(*ce_alloc_dst_ring)(struct ath10k *ar,
309 const struct ce_attr *attr);
310 int (*ce_rx_post_buf)(struct ath10k_ce_pipe *pipe, void *ctx,
312 int (*ce_completed_recv_next_nolock)(struct ath10k_ce_pipe *ce_state,
313 void **per_transfer_contextp,
315 int (*ce_revoke_recv_next)(struct ath10k_ce_pipe *ce_state,
316 void **per_transfer_contextp,
317 dma_addr_t *nbytesp);
318 void (*ce_extract_desc_data)(struct ath10k *ar,
319 struct ath10k_ce_ring *src_ring,
320 u32 sw_index, dma_addr_t *bufferp,
321 u32 *nbytesp, u32 *transfer_idp);
322 void (*ce_free_pipe)(struct ath10k *ar, int ce_id);
323 int (*ce_send_nolock)(struct ath10k_ce_pipe *pipe,
324 void *per_transfer_context,
325 dma_addr_t buffer, u32 nbytes,
326 u32 transfer_id, u32 flags);
329 static inline u32 ath10k_ce_base_address(struct ath10k *ar, unsigned int ce_id)
331 return CE0_BASE_ADDRESS + (CE1_BASE_ADDRESS - CE0_BASE_ADDRESS) * ce_id;
334 #define CE_SRC_RING_TO_DESC(baddr, idx) \
335 (&(((struct ce_desc *)baddr)[idx]))
337 #define CE_DEST_RING_TO_DESC(baddr, idx) \
338 (&(((struct ce_desc *)baddr)[idx]))
340 #define CE_SRC_RING_TO_DESC_64(baddr, idx) \
341 (&(((struct ce_desc_64 *)baddr)[idx]))
343 #define CE_DEST_RING_TO_DESC_64(baddr, idx) \
344 (&(((struct ce_desc_64 *)baddr)[idx]))
346 /* Ring arithmetic (modulus number of entries in ring, which is a pwr of 2). */
347 #define CE_RING_DELTA(nentries_mask, fromidx, toidx) \
348 (((int)(toidx) - (int)(fromidx)) & (nentries_mask))
350 #define CE_RING_IDX_INCR(nentries_mask, idx) (((idx) + 1) & (nentries_mask))
351 #define CE_RING_IDX_ADD(nentries_mask, idx, num) \
352 (((idx) + (num)) & (nentries_mask))
354 #define CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB \
355 ar->regs->ce_wrap_intr_sum_host_msi_lsb
356 #define CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK \
357 ar->regs->ce_wrap_intr_sum_host_msi_mask
358 #define CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_GET(x) \
359 (((x) & CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK) >> \
360 CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB)
361 #define CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS 0x0000
362 #define CE_INTERRUPT_SUMMARY (GENMASK(CE_COUNT_MAX - 1, 0))
364 static inline u32 ath10k_ce_interrupt_summary(struct ath10k *ar)
366 struct ath10k_ce *ce = ath10k_ce_priv(ar);
368 if (!ar->hw_params.per_ce_irq)
369 return CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_GET(
370 ce->bus_ops->read32((ar), CE_WRAPPER_BASE_ADDRESS +
371 CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS));
373 return CE_INTERRUPT_SUMMARY;