2 * Copyright (c) 2005-2011 Atheros Communications Inc.
3 * Copyright (c) 2011-2017 Qualcomm Atheros, Inc.
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
21 #include "targaddrs.h"
23 #define ATH10K_FW_DIR "ath10k"
25 #define QCA988X_2_0_DEVICE_ID_UBNT (0x11ac)
26 #define QCA988X_2_0_DEVICE_ID (0x003c)
27 #define QCA6164_2_1_DEVICE_ID (0x0041)
28 #define QCA6174_2_1_DEVICE_ID (0x003e)
29 #define QCA99X0_2_0_DEVICE_ID (0x0040)
30 #define QCA9888_2_0_DEVICE_ID (0x0056)
31 #define QCA9984_1_0_DEVICE_ID (0x0046)
32 #define QCA9377_1_0_DEVICE_ID (0x0042)
33 #define QCA9887_1_0_DEVICE_ID (0x0050)
35 /* QCA988X 1.0 definitions (unsupported) */
36 #define QCA988X_HW_1_0_CHIP_ID_REV 0x0
38 /* QCA988X 2.0 definitions */
39 #define QCA988X_HW_2_0_VERSION 0x4100016c
40 #define QCA988X_HW_2_0_CHIP_ID_REV 0x2
41 #define QCA988X_HW_2_0_FW_DIR ATH10K_FW_DIR "/QCA988X/hw2.0"
42 #define QCA988X_HW_2_0_BOARD_DATA_FILE "board.bin"
43 #define QCA988X_HW_2_0_PATCH_LOAD_ADDR 0x1234
45 /* QCA9887 1.0 definitions */
46 #define QCA9887_HW_1_0_VERSION 0x4100016d
47 #define QCA9887_HW_1_0_CHIP_ID_REV 0
48 #define QCA9887_HW_1_0_FW_DIR ATH10K_FW_DIR "/QCA9887/hw1.0"
49 #define QCA9887_HW_1_0_BOARD_DATA_FILE "board.bin"
50 #define QCA9887_HW_1_0_PATCH_LOAD_ADDR 0x1234
52 /* QCA6174 target BMI version signatures */
53 #define QCA6174_HW_1_0_VERSION 0x05000000
54 #define QCA6174_HW_1_1_VERSION 0x05000001
55 #define QCA6174_HW_1_3_VERSION 0x05000003
56 #define QCA6174_HW_2_1_VERSION 0x05010000
57 #define QCA6174_HW_3_0_VERSION 0x05020000
58 #define QCA6174_HW_3_2_VERSION 0x05030000
60 /* QCA9377 target BMI version signatures */
61 #define QCA9377_HW_1_0_DEV_VERSION 0x05020000
62 #define QCA9377_HW_1_1_DEV_VERSION 0x05020001
64 enum qca6174_pci_rev {
65 QCA6174_PCI_REV_1_1 = 0x11,
66 QCA6174_PCI_REV_1_3 = 0x13,
67 QCA6174_PCI_REV_2_0 = 0x20,
68 QCA6174_PCI_REV_3_0 = 0x30,
71 enum qca6174_chip_id_rev {
72 QCA6174_HW_1_0_CHIP_ID_REV = 0,
73 QCA6174_HW_1_1_CHIP_ID_REV = 1,
74 QCA6174_HW_1_3_CHIP_ID_REV = 2,
75 QCA6174_HW_2_1_CHIP_ID_REV = 4,
76 QCA6174_HW_2_2_CHIP_ID_REV = 5,
77 QCA6174_HW_3_0_CHIP_ID_REV = 8,
78 QCA6174_HW_3_1_CHIP_ID_REV = 9,
79 QCA6174_HW_3_2_CHIP_ID_REV = 10,
82 enum qca9377_chip_id_rev {
83 QCA9377_HW_1_0_CHIP_ID_REV = 0x0,
84 QCA9377_HW_1_1_CHIP_ID_REV = 0x1,
87 #define QCA6174_HW_2_1_FW_DIR "ath10k/QCA6174/hw2.1"
88 #define QCA6174_HW_2_1_BOARD_DATA_FILE "board.bin"
89 #define QCA6174_HW_2_1_PATCH_LOAD_ADDR 0x1234
91 #define QCA6174_HW_3_0_FW_DIR "ath10k/QCA6174/hw3.0"
92 #define QCA6174_HW_3_0_BOARD_DATA_FILE "board.bin"
93 #define QCA6174_HW_3_0_PATCH_LOAD_ADDR 0x1234
95 /* QCA99X0 1.0 definitions (unsupported) */
96 #define QCA99X0_HW_1_0_CHIP_ID_REV 0x0
98 /* QCA99X0 2.0 definitions */
99 #define QCA99X0_HW_2_0_DEV_VERSION 0x01000000
100 #define QCA99X0_HW_2_0_CHIP_ID_REV 0x1
101 #define QCA99X0_HW_2_0_FW_DIR ATH10K_FW_DIR "/QCA99X0/hw2.0"
102 #define QCA99X0_HW_2_0_BOARD_DATA_FILE "board.bin"
103 #define QCA99X0_HW_2_0_PATCH_LOAD_ADDR 0x1234
105 /* QCA9984 1.0 defines */
106 #define QCA9984_HW_1_0_DEV_VERSION 0x1000000
107 #define QCA9984_HW_DEV_TYPE 0xa
108 #define QCA9984_HW_1_0_CHIP_ID_REV 0x0
109 #define QCA9984_HW_1_0_FW_DIR ATH10K_FW_DIR "/QCA9984/hw1.0"
110 #define QCA9984_HW_1_0_BOARD_DATA_FILE "board.bin"
111 #define QCA9984_HW_1_0_PATCH_LOAD_ADDR 0x1234
113 /* QCA9888 2.0 defines */
114 #define QCA9888_HW_2_0_DEV_VERSION 0x1000000
115 #define QCA9888_HW_DEV_TYPE 0xc
116 #define QCA9888_HW_2_0_CHIP_ID_REV 0x0
117 #define QCA9888_HW_2_0_FW_DIR ATH10K_FW_DIR "/QCA9888/hw2.0"
118 #define QCA9888_HW_2_0_BOARD_DATA_FILE "board.bin"
119 #define QCA9888_HW_2_0_PATCH_LOAD_ADDR 0x1234
121 /* QCA9377 1.0 definitions */
122 #define QCA9377_HW_1_0_FW_DIR ATH10K_FW_DIR "/QCA9377/hw1.0"
123 #define QCA9377_HW_1_0_BOARD_DATA_FILE "board.bin"
124 #define QCA9377_HW_1_0_PATCH_LOAD_ADDR 0x1234
126 /* QCA4019 1.0 definitions */
127 #define QCA4019_HW_1_0_DEV_VERSION 0x01000000
128 #define QCA4019_HW_1_0_FW_DIR ATH10K_FW_DIR "/QCA4019/hw1.0"
129 #define QCA4019_HW_1_0_BOARD_DATA_FILE "board.bin"
130 #define QCA4019_HW_1_0_PATCH_LOAD_ADDR 0x1234
132 /* WCN3990 1.0 definitions */
133 #define WCN3990_HW_1_0_DEV_VERSION ATH10K_HW_WCN3990
134 #define WCN3990_HW_1_0_FW_DIR ATH10K_FW_DIR "/WCN3990/hw1.0"
136 #define ATH10K_FW_FILE_BASE "firmware"
137 #define ATH10K_FW_API_MAX 6
138 #define ATH10K_FW_API_MIN 2
140 #define ATH10K_FW_API2_FILE "firmware-2.bin"
141 #define ATH10K_FW_API3_FILE "firmware-3.bin"
143 /* added support for ATH10K_FW_IE_WMI_OP_VERSION */
144 #define ATH10K_FW_API4_FILE "firmware-4.bin"
146 /* HTT id conflict fix for management frames over HTT */
147 #define ATH10K_FW_API5_FILE "firmware-5.bin"
149 /* the firmware-6.bin blob */
150 #define ATH10K_FW_API6_FILE "firmware-6.bin"
152 #define ATH10K_FW_UTF_FILE "utf.bin"
153 #define ATH10K_FW_UTF_API2_FILE "utf-2.bin"
155 /* includes also the null byte */
156 #define ATH10K_FIRMWARE_MAGIC "QCA-ATH10K"
157 #define ATH10K_BOARD_MAGIC "QCA-ATH10K-BOARD"
159 #define ATH10K_BOARD_API2_FILE "board-2.bin"
161 #define REG_DUMP_COUNT_QCA988X 60
163 struct ath10k_fw_ie {
169 enum ath10k_fw_ie_type {
170 ATH10K_FW_IE_FW_VERSION = 0,
171 ATH10K_FW_IE_TIMESTAMP = 1,
172 ATH10K_FW_IE_FEATURES = 2,
173 ATH10K_FW_IE_FW_IMAGE = 3,
174 ATH10K_FW_IE_OTP_IMAGE = 4,
176 /* WMI "operations" interface version, 32 bit value. Supported from
177 * FW API 4 and above.
179 ATH10K_FW_IE_WMI_OP_VERSION = 5,
181 /* HTT "operations" interface version, 32 bit value. Supported from
182 * FW API 5 and above.
184 ATH10K_FW_IE_HTT_OP_VERSION = 6,
186 /* Code swap image for firmware binary */
187 ATH10K_FW_IE_FW_CODE_SWAP_IMAGE = 7,
190 enum ath10k_fw_wmi_op_version {
191 ATH10K_FW_WMI_OP_VERSION_UNSET = 0,
193 ATH10K_FW_WMI_OP_VERSION_MAIN = 1,
194 ATH10K_FW_WMI_OP_VERSION_10_1 = 2,
195 ATH10K_FW_WMI_OP_VERSION_10_2 = 3,
196 ATH10K_FW_WMI_OP_VERSION_TLV = 4,
197 ATH10K_FW_WMI_OP_VERSION_10_2_4 = 5,
198 ATH10K_FW_WMI_OP_VERSION_10_4 = 6,
201 ATH10K_FW_WMI_OP_VERSION_MAX,
204 enum ath10k_fw_htt_op_version {
205 ATH10K_FW_HTT_OP_VERSION_UNSET = 0,
207 ATH10K_FW_HTT_OP_VERSION_MAIN = 1,
209 /* also used in 10.2 and 10.2.4 branches */
210 ATH10K_FW_HTT_OP_VERSION_10_1 = 2,
212 ATH10K_FW_HTT_OP_VERSION_TLV = 3,
214 ATH10K_FW_HTT_OP_VERSION_10_4 = 4,
217 ATH10K_FW_HTT_OP_VERSION_MAX,
220 enum ath10k_bd_ie_type {
221 /* contains sub IEs of enum ath10k_bd_ie_board_type */
222 ATH10K_BD_IE_BOARD = 0,
225 enum ath10k_bd_ie_board_type {
226 ATH10K_BD_IE_BOARD_NAME = 0,
227 ATH10K_BD_IE_BOARD_DATA = 1,
242 struct ath10k_hw_regs {
243 u32 rtc_soc_base_address;
244 u32 rtc_wmac_base_address;
245 u32 soc_core_base_address;
246 u32 wlan_mac_base_address;
247 u32 ce_wrapper_base_address;
248 u32 ce0_base_address;
249 u32 ce1_base_address;
250 u32 ce2_base_address;
251 u32 ce3_base_address;
252 u32 ce4_base_address;
253 u32 ce5_base_address;
254 u32 ce6_base_address;
255 u32 ce7_base_address;
256 u32 ce8_base_address;
257 u32 ce9_base_address;
258 u32 ce10_base_address;
259 u32 ce11_base_address;
260 u32 soc_reset_control_si0_rst_mask;
261 u32 soc_reset_control_ce_rst_mask;
262 u32 soc_chip_id_address;
263 u32 scratch_3_address;
264 u32 fw_indicator_address;
265 u32 pcie_local_base_address;
266 u32 ce_wrap_intr_sum_host_msi_lsb;
267 u32 ce_wrap_intr_sum_host_msi_mask;
268 u32 pcie_intr_fw_mask;
269 u32 pcie_intr_ce_mask_all;
270 u32 pcie_intr_clr_address;
271 u32 cpu_pll_init_address;
272 u32 cpu_speed_address;
273 u32 core_clk_div_address;
276 extern const struct ath10k_hw_regs qca988x_regs;
277 extern const struct ath10k_hw_regs qca6174_regs;
278 extern const struct ath10k_hw_regs qca99x0_regs;
279 extern const struct ath10k_hw_regs qca4019_regs;
280 extern const struct ath10k_hw_regs wcn3990_regs;
282 struct ath10k_hw_ce_regs_addr_map {
288 struct ath10k_hw_ce_ctrl1 {
296 struct ath10k_hw_ce_regs_addr_map *src_ring;
297 struct ath10k_hw_ce_regs_addr_map *dst_ring;
298 struct ath10k_hw_ce_regs_addr_map *dmax; };
300 struct ath10k_hw_ce_cmd_halt {
304 struct ath10k_hw_ce_regs_addr_map *status; };
306 struct ath10k_hw_ce_host_ie {
307 u32 copy_complete_reset;
308 struct ath10k_hw_ce_regs_addr_map *copy_complete; };
310 struct ath10k_hw_ce_host_wm_regs {
320 struct ath10k_hw_ce_misc_regs {
331 struct ath10k_hw_ce_dst_src_wm_regs {
335 struct ath10k_hw_ce_regs_addr_map *wm_low;
336 struct ath10k_hw_ce_regs_addr_map *wm_high; };
338 struct ath10k_hw_ce_regs {
345 u32 sr_wr_index_addr;
346 u32 dst_wr_index_addr;
347 u32 current_srri_addr;
348 u32 current_drri_addr;
349 u32 ddr_addr_for_rri_low;
350 u32 ddr_addr_for_rri_high;
354 struct ath10k_hw_ce_host_wm_regs *wm_regs;
355 struct ath10k_hw_ce_misc_regs *misc_regs;
356 struct ath10k_hw_ce_ctrl1 *ctrl1_regs;
357 struct ath10k_hw_ce_cmd_halt *cmd_halt;
358 struct ath10k_hw_ce_host_ie *host_ie;
359 struct ath10k_hw_ce_dst_src_wm_regs *wm_srcr;
360 struct ath10k_hw_ce_dst_src_wm_regs *wm_dstr; };
362 struct ath10k_hw_values {
363 u32 rtc_state_val_on;
365 u8 msi_assign_ce_max;
366 u8 num_target_ce_config_wlan;
367 u16 ce_desc_meta_data_mask;
368 u8 ce_desc_meta_data_lsb;
371 extern const struct ath10k_hw_values qca988x_values;
372 extern const struct ath10k_hw_values qca6174_values;
373 extern const struct ath10k_hw_values qca99x0_values;
374 extern const struct ath10k_hw_values qca9888_values;
375 extern const struct ath10k_hw_values qca4019_values;
376 extern const struct ath10k_hw_values wcn3990_values;
377 extern const struct ath10k_hw_ce_regs wcn3990_ce_regs;
378 extern const struct ath10k_hw_ce_regs qcax_ce_regs;
380 void ath10k_hw_fill_survey_time(struct ath10k *ar, struct survey_info *survey,
381 u32 cc, u32 rcc, u32 cc_prev, u32 rcc_prev);
383 #define QCA_REV_988X(ar) ((ar)->hw_rev == ATH10K_HW_QCA988X)
384 #define QCA_REV_9887(ar) ((ar)->hw_rev == ATH10K_HW_QCA9887)
385 #define QCA_REV_6174(ar) ((ar)->hw_rev == ATH10K_HW_QCA6174)
386 #define QCA_REV_99X0(ar) ((ar)->hw_rev == ATH10K_HW_QCA99X0)
387 #define QCA_REV_9888(ar) ((ar)->hw_rev == ATH10K_HW_QCA9888)
388 #define QCA_REV_9984(ar) ((ar)->hw_rev == ATH10K_HW_QCA9984)
389 #define QCA_REV_9377(ar) ((ar)->hw_rev == ATH10K_HW_QCA9377)
390 #define QCA_REV_40XX(ar) ((ar)->hw_rev == ATH10K_HW_QCA4019)
391 #define QCA_REV_WCN3990(ar) ((ar)->hw_rev == ATH10K_HW_WCN3990)
393 /* Known peculiarities:
394 * - raw appears in nwifi decap, raw and nwifi appear in ethernet decap
395 * - raw have FCS, nwifi doesn't
396 * - ethernet frames have 802.11 header decapped and parts (base hdr, cipher
397 * param, llc/snap) are aligned to 4byte boundaries each
399 enum ath10k_hw_txrx_mode {
400 ATH10K_HW_TXRX_RAW = 0,
402 /* Native Wifi decap mode is used to align IP frames to 4-byte
403 * boundaries and avoid a very expensive re-alignment in mac80211.
405 ATH10K_HW_TXRX_NATIVE_WIFI = 1,
406 ATH10K_HW_TXRX_ETHERNET = 2,
408 /* Valid for HTT >= 3.0. Used for management frames in TX_FRM. */
409 ATH10K_HW_TXRX_MGMT = 3,
412 enum ath10k_mcast2ucast_mode {
413 ATH10K_MCAST2UCAST_DISABLED = 0,
414 ATH10K_MCAST2UCAST_ENABLED = 1,
417 enum ath10k_hw_rate_ofdm {
418 ATH10K_HW_RATE_OFDM_48M = 0,
419 ATH10K_HW_RATE_OFDM_24M,
420 ATH10K_HW_RATE_OFDM_12M,
421 ATH10K_HW_RATE_OFDM_6M,
422 ATH10K_HW_RATE_OFDM_54M,
423 ATH10K_HW_RATE_OFDM_36M,
424 ATH10K_HW_RATE_OFDM_18M,
425 ATH10K_HW_RATE_OFDM_9M,
428 enum ath10k_hw_rate_cck {
429 ATH10K_HW_RATE_CCK_LP_11M = 0,
430 ATH10K_HW_RATE_CCK_LP_5_5M,
431 ATH10K_HW_RATE_CCK_LP_2M,
432 ATH10K_HW_RATE_CCK_LP_1M,
433 ATH10K_HW_RATE_CCK_SP_11M,
434 ATH10K_HW_RATE_CCK_SP_5_5M,
435 ATH10K_HW_RATE_CCK_SP_2M,
438 enum ath10k_hw_rate_rev2_cck {
439 ATH10K_HW_RATE_REV2_CCK_LP_1M = 1,
440 ATH10K_HW_RATE_REV2_CCK_LP_2M,
441 ATH10K_HW_RATE_REV2_CCK_LP_5_5M,
442 ATH10K_HW_RATE_REV2_CCK_LP_11M,
443 ATH10K_HW_RATE_REV2_CCK_SP_2M,
444 ATH10K_HW_RATE_REV2_CCK_SP_5_5M,
445 ATH10K_HW_RATE_REV2_CCK_SP_11M,
448 enum ath10k_hw_cc_wraparound_type {
449 ATH10K_HW_CC_WRAP_DISABLED = 0,
451 /* This type is when the HW chip has a quirky Cycle Counter
452 * wraparound which resets to 0x7fffffff instead of 0. All
453 * other CC related counters (e.g. Rx Clear Count) are divided
454 * by 2 so they never wraparound themselves.
456 ATH10K_HW_CC_WRAP_SHIFTED_ALL = 1,
458 /* Each hw counter wrapsaround independently. When the
459 * counter overflows the repestive counter is right shifted
460 * by 1, i.e reset to 0x7fffffff, and other counters will be
461 * running unaffected. In this type of wraparound, it should
462 * be possible to report accurate Rx busy time unlike the
465 ATH10K_HW_CC_WRAP_SHIFTED_EACH = 2,
468 enum ath10k_hw_refclk_speed {
469 ATH10K_HW_REFCLK_UNKNOWN = -1,
470 ATH10K_HW_REFCLK_48_MHZ = 0,
471 ATH10K_HW_REFCLK_19_2_MHZ = 1,
472 ATH10K_HW_REFCLK_24_MHZ = 2,
473 ATH10K_HW_REFCLK_26_MHZ = 3,
474 ATH10K_HW_REFCLK_37_4_MHZ = 4,
475 ATH10K_HW_REFCLK_38_4_MHZ = 5,
476 ATH10K_HW_REFCLK_40_MHZ = 6,
477 ATH10K_HW_REFCLK_52_MHZ = 7,
479 /* must be the last one */
480 ATH10K_HW_REFCLK_COUNT,
483 struct ath10k_hw_clk_params {
492 struct ath10k_hw_params {
500 /* Type of hw cycle counter wraparound logic, for more info
501 * refer enum ath10k_hw_cc_wraparound_type.
503 enum ath10k_hw_cc_wraparound_type cc_wraparound_type;
505 /* Some of chip expects fragment descriptor to be continuous
506 * memory for any TX operation. Set continuous_frag_desc flag
507 * for the hardware which have such requirement.
509 bool continuous_frag_desc;
511 /* CCK hardware rate table mapping for the newer chipsets
512 * like QCA99X0, QCA4019 got revised. The CCK h/w rate values
513 * are in a proper order with respect to the rate/preamble
515 bool cck_rate_map_rev2;
517 u32 channel_counters_freq_hz;
519 /* Mgmt tx descriptors threshold for limiting probe response
522 u32 max_probe_resp_desc_thres;
526 u32 max_spatial_stream;
529 struct ath10k_hw_params_fw {
533 size_t board_ext_size;
536 /* qca99x0 family chips deliver broadcast/multicast management
537 * frames encrypted and expect software do decryption.
539 bool sw_decrypt_mcast_mgmt;
541 const struct ath10k_hw_ops *hw_ops;
543 /* Number of bytes used for alignment in rx_hdr_status of rx desc. */
544 int decap_align_bytes;
546 /* hw specific clock control parameters */
547 const struct ath10k_hw_clk_params *hw_clk;
550 /* Number of bytes to be discarded for each FFT sample */
551 int spectral_bin_discard;
553 /* The board may have a restricted NSS for 160 or 80+80 vs what it
556 int vht160_mcs_rx_highest;
557 int vht160_mcs_tx_highest;
559 /* Number of ciphers supported (i.e First N) in cipher_suites array */
566 /* Targets supporting physical addressing capability above 32-bits */
569 /* Target rx ring fill level */
570 u32 rx_ring_fill_level;
572 /* target supporting per ce IRQ */
578 /* Defines needed for Rx descriptor abstraction */
579 struct ath10k_hw_ops {
580 int (*rx_desc_get_l3_pad_bytes)(struct htt_rx_desc *rxd);
581 void (*set_coverage_class)(struct ath10k *ar, s16 value);
582 int (*enable_pll_clk)(struct ath10k *ar);
585 extern const struct ath10k_hw_ops qca988x_ops;
586 extern const struct ath10k_hw_ops qca99x0_ops;
587 extern const struct ath10k_hw_ops qca6174_ops;
588 extern const struct ath10k_hw_ops wcn3990_ops;
590 extern const struct ath10k_hw_clk_params qca6174_clk[];
593 ath10k_rx_desc_get_l3_pad_bytes(struct ath10k_hw_params *hw,
594 struct htt_rx_desc *rxd)
596 if (hw->hw_ops->rx_desc_get_l3_pad_bytes)
597 return hw->hw_ops->rx_desc_get_l3_pad_bytes(rxd);
601 /* Target specific defines for MAIN firmware */
602 #define TARGET_NUM_VDEVS 8
603 #define TARGET_NUM_PEER_AST 2
604 #define TARGET_NUM_WDS_ENTRIES 32
605 #define TARGET_DMA_BURST_SIZE 0
606 #define TARGET_MAC_AGGR_DELIM 0
607 #define TARGET_AST_SKID_LIMIT 16
608 #define TARGET_NUM_STATIONS 16
609 #define TARGET_NUM_PEERS ((TARGET_NUM_STATIONS) + \
611 #define TARGET_NUM_OFFLOAD_PEERS 0
612 #define TARGET_NUM_OFFLOAD_REORDER_BUFS 0
613 #define TARGET_NUM_PEER_KEYS 2
614 #define TARGET_NUM_TIDS ((TARGET_NUM_PEERS) * 2)
615 #define TARGET_TX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2))
616 #define TARGET_RX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2))
617 #define TARGET_RX_TIMEOUT_LO_PRI 100
618 #define TARGET_RX_TIMEOUT_HI_PRI 40
620 #define TARGET_SCAN_MAX_PENDING_REQS 4
621 #define TARGET_BMISS_OFFLOAD_MAX_VDEV 3
622 #define TARGET_ROAM_OFFLOAD_MAX_VDEV 3
623 #define TARGET_ROAM_OFFLOAD_MAX_AP_PROFILES 8
624 #define TARGET_GTK_OFFLOAD_MAX_VDEV 3
625 #define TARGET_NUM_MCAST_GROUPS 0
626 #define TARGET_NUM_MCAST_TABLE_ELEMS 0
627 #define TARGET_MCAST2UCAST_MODE ATH10K_MCAST2UCAST_DISABLED
628 #define TARGET_TX_DBG_LOG_SIZE 1024
629 #define TARGET_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK 0
630 #define TARGET_VOW_CONFIG 0
631 #define TARGET_NUM_MSDU_DESC (1024 + 400)
632 #define TARGET_MAX_FRAG_ENTRIES 0
634 /* Target specific defines for 10.X firmware */
635 #define TARGET_10X_NUM_VDEVS 16
636 #define TARGET_10X_NUM_PEER_AST 2
637 #define TARGET_10X_NUM_WDS_ENTRIES 32
638 #define TARGET_10X_DMA_BURST_SIZE 0
639 #define TARGET_10X_MAC_AGGR_DELIM 0
640 #define TARGET_10X_AST_SKID_LIMIT 128
641 #define TARGET_10X_NUM_STATIONS 128
642 #define TARGET_10X_TX_STATS_NUM_STATIONS 118
643 #define TARGET_10X_NUM_PEERS ((TARGET_10X_NUM_STATIONS) + \
644 (TARGET_10X_NUM_VDEVS))
645 #define TARGET_10X_TX_STATS_NUM_PEERS ((TARGET_10X_TX_STATS_NUM_STATIONS) + \
646 (TARGET_10X_NUM_VDEVS))
647 #define TARGET_10X_NUM_OFFLOAD_PEERS 0
648 #define TARGET_10X_NUM_OFFLOAD_REORDER_BUFS 0
649 #define TARGET_10X_NUM_PEER_KEYS 2
650 #define TARGET_10X_NUM_TIDS_MAX 256
651 #define TARGET_10X_NUM_TIDS min((TARGET_10X_NUM_TIDS_MAX), \
652 (TARGET_10X_NUM_PEERS) * 2)
653 #define TARGET_10X_TX_STATS_NUM_TIDS min((TARGET_10X_NUM_TIDS_MAX), \
654 (TARGET_10X_TX_STATS_NUM_PEERS) * 2)
655 #define TARGET_10X_TX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2))
656 #define TARGET_10X_RX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2))
657 #define TARGET_10X_RX_TIMEOUT_LO_PRI 100
658 #define TARGET_10X_RX_TIMEOUT_HI_PRI 40
659 #define TARGET_10X_SCAN_MAX_PENDING_REQS 4
660 #define TARGET_10X_BMISS_OFFLOAD_MAX_VDEV 2
661 #define TARGET_10X_ROAM_OFFLOAD_MAX_VDEV 2
662 #define TARGET_10X_ROAM_OFFLOAD_MAX_AP_PROFILES 8
663 #define TARGET_10X_GTK_OFFLOAD_MAX_VDEV 3
664 #define TARGET_10X_NUM_MCAST_GROUPS 0
665 #define TARGET_10X_NUM_MCAST_TABLE_ELEMS 0
666 #define TARGET_10X_MCAST2UCAST_MODE ATH10K_MCAST2UCAST_DISABLED
667 #define TARGET_10X_TX_DBG_LOG_SIZE 1024
668 #define TARGET_10X_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK 1
669 #define TARGET_10X_VOW_CONFIG 0
670 #define TARGET_10X_NUM_MSDU_DESC (1024 + 400)
671 #define TARGET_10X_MAX_FRAG_ENTRIES 0
673 /* 10.2 parameters */
674 #define TARGET_10_2_DMA_BURST_SIZE 0
676 /* Target specific defines for WMI-TLV firmware */
677 #define TARGET_TLV_NUM_VDEVS 4
678 #define TARGET_TLV_NUM_STATIONS 32
679 #define TARGET_TLV_NUM_PEERS 33
680 #define TARGET_TLV_NUM_TDLS_VDEVS 1
681 #define TARGET_TLV_NUM_TIDS ((TARGET_TLV_NUM_PEERS) * 2)
682 #define TARGET_TLV_NUM_MSDU_DESC (1024 + 32)
683 #define TARGET_TLV_NUM_WOW_PATTERNS 22
685 /* Target specific defines for WMI-HL-1.0 firmware */
686 #define TARGET_HL_10_TLV_NUM_PEERS 14
687 #define TARGET_HL_10_TLV_AST_SKID_LIMIT 6
688 #define TARGET_HL_10_TLV_NUM_WDS_ENTRIES 2
690 /* Diagnostic Window */
691 #define CE_DIAG_PIPE 7
693 #define NUM_TARGET_CE_CONFIG_WLAN ar->hw_values->num_target_ce_config_wlan
695 /* Target specific defines for 10.4 firmware */
696 #define TARGET_10_4_NUM_VDEVS 16
697 #define TARGET_10_4_NUM_STATIONS 32
698 #define TARGET_10_4_NUM_PEERS ((TARGET_10_4_NUM_STATIONS) + \
699 (TARGET_10_4_NUM_VDEVS))
700 #define TARGET_10_4_ACTIVE_PEERS 0
702 #define TARGET_10_4_NUM_QCACHE_PEERS_MAX 512
703 #define TARGET_10_4_QCACHE_ACTIVE_PEERS 50
704 #define TARGET_10_4_QCACHE_ACTIVE_PEERS_PFC 35
705 #define TARGET_10_4_NUM_OFFLOAD_PEERS 0
706 #define TARGET_10_4_NUM_OFFLOAD_REORDER_BUFFS 0
707 #define TARGET_10_4_NUM_PEER_KEYS 2
708 #define TARGET_10_4_TGT_NUM_TIDS ((TARGET_10_4_NUM_PEERS) * 2)
709 #define TARGET_10_4_NUM_MSDU_DESC (1024 + 400)
710 #define TARGET_10_4_NUM_MSDU_DESC_PFC 2500
711 #define TARGET_10_4_AST_SKID_LIMIT 32
713 /* 100 ms for video, best-effort, and background */
714 #define TARGET_10_4_RX_TIMEOUT_LO_PRI 100
716 /* 40 ms for voice */
717 #define TARGET_10_4_RX_TIMEOUT_HI_PRI 40
719 #define TARGET_10_4_RX_DECAP_MODE ATH10K_HW_TXRX_NATIVE_WIFI
720 #define TARGET_10_4_SCAN_MAX_REQS 4
721 #define TARGET_10_4_BMISS_OFFLOAD_MAX_VDEV 3
722 #define TARGET_10_4_ROAM_OFFLOAD_MAX_VDEV 3
723 #define TARGET_10_4_ROAM_OFFLOAD_MAX_PROFILES 8
725 /* Note: mcast to ucast is disabled by default */
726 #define TARGET_10_4_NUM_MCAST_GROUPS 0
727 #define TARGET_10_4_NUM_MCAST_TABLE_ELEMS 0
728 #define TARGET_10_4_MCAST2UCAST_MODE 0
730 #define TARGET_10_4_TX_DBG_LOG_SIZE 1024
731 #define TARGET_10_4_NUM_WDS_ENTRIES 32
732 #define TARGET_10_4_DMA_BURST_SIZE 0
733 #define TARGET_10_4_MAC_AGGR_DELIM 0
734 #define TARGET_10_4_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK 1
735 #define TARGET_10_4_VOW_CONFIG 0
736 #define TARGET_10_4_GTK_OFFLOAD_MAX_VDEV 3
737 #define TARGET_10_4_11AC_TX_MAX_FRAGS 2
738 #define TARGET_10_4_MAX_PEER_EXT_STATS 16
739 #define TARGET_10_4_SMART_ANT_CAP 0
740 #define TARGET_10_4_BK_MIN_FREE 0
741 #define TARGET_10_4_BE_MIN_FREE 0
742 #define TARGET_10_4_VI_MIN_FREE 0
743 #define TARGET_10_4_VO_MIN_FREE 0
744 #define TARGET_10_4_RX_BATCH_MODE 1
745 #define TARGET_10_4_THERMAL_THROTTLING_CONFIG 0
746 #define TARGET_10_4_ATF_CONFIG 0
747 #define TARGET_10_4_IPHDR_PAD_CONFIG 1
748 #define TARGET_10_4_QWRAP_CONFIG 0
751 #define TARGET_10_4_NUM_TDLS_VDEVS 1
752 #define TARGET_10_4_NUM_TDLS_BUFFER_STA 1
753 #define TARGET_10_4_NUM_TDLS_SLEEP_STA 1
755 /* Maximum number of Copy Engine's supported */
756 #define CE_COUNT_MAX 12
758 /* Number of Copy Engines supported */
759 #define CE_COUNT ar->hw_values->ce_count
762 * Granted MSIs are assigned as follows:
763 * Firmware uses the first
764 * Remaining MSIs, if any, are used by Copy Engines
765 * This mapping is known to both Target firmware and Host software.
766 * It may be changed as long as Host and Target are kept in sync.
768 /* MSI for firmware (errors, etc.) */
769 #define MSI_ASSIGN_FW 0
771 /* MSIs for Copy Engines */
772 #define MSI_ASSIGN_CE_INITIAL 1
773 #define MSI_ASSIGN_CE_MAX ar->hw_values->msi_assign_ce_max
776 #define RTC_STATE_V_ON ar->hw_values->rtc_state_val_on
778 #define RTC_STATE_V_LSB 0
779 #define RTC_STATE_V_MASK 0x00000007
780 #define RTC_STATE_ADDRESS 0x0000
781 #define PCIE_SOC_WAKE_V_MASK 0x00000001
782 #define PCIE_SOC_WAKE_ADDRESS 0x0004
783 #define PCIE_SOC_WAKE_RESET 0x00000000
784 #define SOC_GLOBAL_RESET_ADDRESS 0x0008
786 #define RTC_SOC_BASE_ADDRESS ar->regs->rtc_soc_base_address
787 #define RTC_WMAC_BASE_ADDRESS ar->regs->rtc_wmac_base_address
788 #define MAC_COEX_BASE_ADDRESS 0x00006000
789 #define BT_COEX_BASE_ADDRESS 0x00007000
790 #define SOC_PCIE_BASE_ADDRESS 0x00008000
791 #define SOC_CORE_BASE_ADDRESS ar->regs->soc_core_base_address
792 #define WLAN_UART_BASE_ADDRESS 0x0000c000
793 #define WLAN_SI_BASE_ADDRESS 0x00010000
794 #define WLAN_GPIO_BASE_ADDRESS 0x00014000
795 #define WLAN_ANALOG_INTF_BASE_ADDRESS 0x0001c000
796 #define WLAN_MAC_BASE_ADDRESS ar->regs->wlan_mac_base_address
797 #define EFUSE_BASE_ADDRESS 0x00030000
798 #define FPGA_REG_BASE_ADDRESS 0x00039000
799 #define WLAN_UART2_BASE_ADDRESS 0x00054c00
800 #define CE_WRAPPER_BASE_ADDRESS ar->regs->ce_wrapper_base_address
801 #define CE0_BASE_ADDRESS ar->regs->ce0_base_address
802 #define CE1_BASE_ADDRESS ar->regs->ce1_base_address
803 #define CE2_BASE_ADDRESS ar->regs->ce2_base_address
804 #define CE3_BASE_ADDRESS ar->regs->ce3_base_address
805 #define CE4_BASE_ADDRESS ar->regs->ce4_base_address
806 #define CE5_BASE_ADDRESS ar->regs->ce5_base_address
807 #define CE6_BASE_ADDRESS ar->regs->ce6_base_address
808 #define CE7_BASE_ADDRESS ar->regs->ce7_base_address
809 #define DBI_BASE_ADDRESS 0x00060000
810 #define WLAN_ANALOG_INTF_PCIE_BASE_ADDRESS 0x0006c000
811 #define PCIE_LOCAL_BASE_ADDRESS ar->regs->pcie_local_base_address
813 #define SOC_RESET_CONTROL_ADDRESS 0x00000000
814 #define SOC_RESET_CONTROL_OFFSET 0x00000000
815 #define SOC_RESET_CONTROL_SI0_RST_MASK ar->regs->soc_reset_control_si0_rst_mask
816 #define SOC_RESET_CONTROL_CE_RST_MASK ar->regs->soc_reset_control_ce_rst_mask
817 #define SOC_RESET_CONTROL_CPU_WARM_RST_MASK 0x00000040
818 #define SOC_CPU_CLOCK_OFFSET 0x00000020
819 #define SOC_CPU_CLOCK_STANDARD_LSB 0
820 #define SOC_CPU_CLOCK_STANDARD_MASK 0x00000003
821 #define SOC_CLOCK_CONTROL_OFFSET 0x00000028
822 #define SOC_CLOCK_CONTROL_SI0_CLK_MASK 0x00000001
823 #define SOC_SYSTEM_SLEEP_OFFSET 0x000000c4
824 #define SOC_LPO_CAL_OFFSET 0x000000e0
825 #define SOC_LPO_CAL_ENABLE_LSB 20
826 #define SOC_LPO_CAL_ENABLE_MASK 0x00100000
827 #define SOC_LF_TIMER_CONTROL0_ADDRESS 0x00000050
828 #define SOC_LF_TIMER_CONTROL0_ENABLE_MASK 0x00000004
830 #define SOC_CHIP_ID_ADDRESS ar->regs->soc_chip_id_address
831 #define SOC_CHIP_ID_REV_LSB 8
832 #define SOC_CHIP_ID_REV_MASK 0x00000f00
834 #define WLAN_RESET_CONTROL_COLD_RST_MASK 0x00000008
835 #define WLAN_RESET_CONTROL_WARM_RST_MASK 0x00000004
836 #define WLAN_SYSTEM_SLEEP_DISABLE_LSB 0
837 #define WLAN_SYSTEM_SLEEP_DISABLE_MASK 0x00000001
839 #define WLAN_GPIO_PIN0_ADDRESS 0x00000028
840 #define WLAN_GPIO_PIN0_CONFIG_LSB 11
841 #define WLAN_GPIO_PIN0_CONFIG_MASK 0x00007800
842 #define WLAN_GPIO_PIN0_PAD_PULL_LSB 5
843 #define WLAN_GPIO_PIN0_PAD_PULL_MASK 0x00000060
844 #define WLAN_GPIO_PIN1_ADDRESS 0x0000002c
845 #define WLAN_GPIO_PIN1_CONFIG_MASK 0x00007800
846 #define WLAN_GPIO_PIN10_ADDRESS 0x00000050
847 #define WLAN_GPIO_PIN11_ADDRESS 0x00000054
848 #define WLAN_GPIO_PIN12_ADDRESS 0x00000058
849 #define WLAN_GPIO_PIN13_ADDRESS 0x0000005c
851 #define CLOCK_GPIO_OFFSET 0xffffffff
852 #define CLOCK_GPIO_BT_CLK_OUT_EN_LSB 0
853 #define CLOCK_GPIO_BT_CLK_OUT_EN_MASK 0
855 #define SI_CONFIG_OFFSET 0x00000000
856 #define SI_CONFIG_ERR_INT_LSB 19
857 #define SI_CONFIG_ERR_INT_MASK 0x00080000
858 #define SI_CONFIG_BIDIR_OD_DATA_LSB 18
859 #define SI_CONFIG_BIDIR_OD_DATA_MASK 0x00040000
860 #define SI_CONFIG_I2C_LSB 16
861 #define SI_CONFIG_I2C_MASK 0x00010000
862 #define SI_CONFIG_POS_SAMPLE_LSB 7
863 #define SI_CONFIG_POS_SAMPLE_MASK 0x00000080
864 #define SI_CONFIG_INACTIVE_DATA_LSB 5
865 #define SI_CONFIG_INACTIVE_DATA_MASK 0x00000020
866 #define SI_CONFIG_INACTIVE_CLK_LSB 4
867 #define SI_CONFIG_INACTIVE_CLK_MASK 0x00000010
868 #define SI_CONFIG_DIVIDER_LSB 0
869 #define SI_CONFIG_DIVIDER_MASK 0x0000000f
870 #define SI_CS_OFFSET 0x00000004
871 #define SI_CS_DONE_ERR_LSB 10
872 #define SI_CS_DONE_ERR_MASK 0x00000400
873 #define SI_CS_DONE_INT_LSB 9
874 #define SI_CS_DONE_INT_MASK 0x00000200
875 #define SI_CS_START_LSB 8
876 #define SI_CS_START_MASK 0x00000100
877 #define SI_CS_RX_CNT_LSB 4
878 #define SI_CS_RX_CNT_MASK 0x000000f0
879 #define SI_CS_TX_CNT_LSB 0
880 #define SI_CS_TX_CNT_MASK 0x0000000f
882 #define SI_TX_DATA0_OFFSET 0x00000008
883 #define SI_TX_DATA1_OFFSET 0x0000000c
884 #define SI_RX_DATA0_OFFSET 0x00000010
885 #define SI_RX_DATA1_OFFSET 0x00000014
887 #define CORE_CTRL_CPU_INTR_MASK 0x00002000
888 #define CORE_CTRL_PCIE_REG_31_MASK 0x00000800
889 #define CORE_CTRL_ADDRESS 0x0000
890 #define PCIE_INTR_ENABLE_ADDRESS 0x0008
891 #define PCIE_INTR_CAUSE_ADDRESS 0x000c
892 #define PCIE_INTR_CLR_ADDRESS ar->regs->pcie_intr_clr_address
893 #define SCRATCH_3_ADDRESS ar->regs->scratch_3_address
894 #define CPU_INTR_ADDRESS 0x0010
895 #define FW_RAM_CONFIG_ADDRESS 0x0018
897 #define CCNT_TO_MSEC(ar, x) ((x) / ar->hw_params.channel_counters_freq_hz)
899 /* Firmware indications to the Host via SCRATCH_3 register. */
900 #define FW_INDICATOR_ADDRESS ar->regs->fw_indicator_address
901 #define FW_IND_EVENT_PENDING 1
902 #define FW_IND_INITIALIZED 2
903 #define FW_IND_HOST_READY 0x80000000
905 /* HOST_REG interrupt from firmware */
906 #define PCIE_INTR_FIRMWARE_MASK ar->regs->pcie_intr_fw_mask
907 #define PCIE_INTR_CE_MASK_ALL ar->regs->pcie_intr_ce_mask_all
909 #define DRAM_BASE_ADDRESS 0x00400000
911 #define PCIE_BAR_REG_ADDRESS 0x40030
915 #define SYSTEM_SLEEP_OFFSET SOC_SYSTEM_SLEEP_OFFSET
916 #define WLAN_SYSTEM_SLEEP_OFFSET SOC_SYSTEM_SLEEP_OFFSET
917 #define WLAN_RESET_CONTROL_OFFSET SOC_RESET_CONTROL_OFFSET
918 #define CLOCK_CONTROL_OFFSET SOC_CLOCK_CONTROL_OFFSET
919 #define CLOCK_CONTROL_SI0_CLK_MASK SOC_CLOCK_CONTROL_SI0_CLK_MASK
920 #define RESET_CONTROL_MBOX_RST_MASK MISSING
921 #define RESET_CONTROL_SI0_RST_MASK SOC_RESET_CONTROL_SI0_RST_MASK
922 #define GPIO_BASE_ADDRESS WLAN_GPIO_BASE_ADDRESS
923 #define GPIO_PIN0_OFFSET WLAN_GPIO_PIN0_ADDRESS
924 #define GPIO_PIN1_OFFSET WLAN_GPIO_PIN1_ADDRESS
925 #define GPIO_PIN0_CONFIG_LSB WLAN_GPIO_PIN0_CONFIG_LSB
926 #define GPIO_PIN0_CONFIG_MASK WLAN_GPIO_PIN0_CONFIG_MASK
927 #define GPIO_PIN0_PAD_PULL_LSB WLAN_GPIO_PIN0_PAD_PULL_LSB
928 #define GPIO_PIN0_PAD_PULL_MASK WLAN_GPIO_PIN0_PAD_PULL_MASK
929 #define GPIO_PIN1_CONFIG_MASK WLAN_GPIO_PIN1_CONFIG_MASK
930 #define SI_BASE_ADDRESS WLAN_SI_BASE_ADDRESS
931 #define SCRATCH_BASE_ADDRESS SOC_CORE_BASE_ADDRESS
932 #define LOCAL_SCRATCH_OFFSET 0x18
933 #define CPU_CLOCK_OFFSET SOC_CPU_CLOCK_OFFSET
934 #define LPO_CAL_OFFSET SOC_LPO_CAL_OFFSET
935 #define GPIO_PIN10_OFFSET WLAN_GPIO_PIN10_ADDRESS
936 #define GPIO_PIN11_OFFSET WLAN_GPIO_PIN11_ADDRESS
937 #define GPIO_PIN12_OFFSET WLAN_GPIO_PIN12_ADDRESS
938 #define GPIO_PIN13_OFFSET WLAN_GPIO_PIN13_ADDRESS
939 #define CPU_CLOCK_STANDARD_LSB SOC_CPU_CLOCK_STANDARD_LSB
940 #define CPU_CLOCK_STANDARD_MASK SOC_CPU_CLOCK_STANDARD_MASK
941 #define LPO_CAL_ENABLE_LSB SOC_LPO_CAL_ENABLE_LSB
942 #define LPO_CAL_ENABLE_MASK SOC_LPO_CAL_ENABLE_MASK
943 #define ANALOG_INTF_BASE_ADDRESS WLAN_ANALOG_INTF_BASE_ADDRESS
944 #define MBOX_BASE_ADDRESS MISSING
945 #define INT_STATUS_ENABLE_ERROR_LSB MISSING
946 #define INT_STATUS_ENABLE_ERROR_MASK MISSING
947 #define INT_STATUS_ENABLE_CPU_LSB MISSING
948 #define INT_STATUS_ENABLE_CPU_MASK MISSING
949 #define INT_STATUS_ENABLE_COUNTER_LSB MISSING
950 #define INT_STATUS_ENABLE_COUNTER_MASK MISSING
951 #define INT_STATUS_ENABLE_MBOX_DATA_LSB MISSING
952 #define INT_STATUS_ENABLE_MBOX_DATA_MASK MISSING
953 #define ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB MISSING
954 #define ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK MISSING
955 #define ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB MISSING
956 #define ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK MISSING
957 #define COUNTER_INT_STATUS_ENABLE_BIT_LSB MISSING
958 #define COUNTER_INT_STATUS_ENABLE_BIT_MASK MISSING
959 #define INT_STATUS_ENABLE_ADDRESS MISSING
960 #define CPU_INT_STATUS_ENABLE_BIT_LSB MISSING
961 #define CPU_INT_STATUS_ENABLE_BIT_MASK MISSING
962 #define HOST_INT_STATUS_ADDRESS MISSING
963 #define CPU_INT_STATUS_ADDRESS MISSING
964 #define ERROR_INT_STATUS_ADDRESS MISSING
965 #define ERROR_INT_STATUS_WAKEUP_MASK MISSING
966 #define ERROR_INT_STATUS_WAKEUP_LSB MISSING
967 #define ERROR_INT_STATUS_RX_UNDERFLOW_MASK MISSING
968 #define ERROR_INT_STATUS_RX_UNDERFLOW_LSB MISSING
969 #define ERROR_INT_STATUS_TX_OVERFLOW_MASK MISSING
970 #define ERROR_INT_STATUS_TX_OVERFLOW_LSB MISSING
971 #define COUNT_DEC_ADDRESS MISSING
972 #define HOST_INT_STATUS_CPU_MASK MISSING
973 #define HOST_INT_STATUS_CPU_LSB MISSING
974 #define HOST_INT_STATUS_ERROR_MASK MISSING
975 #define HOST_INT_STATUS_ERROR_LSB MISSING
976 #define HOST_INT_STATUS_COUNTER_MASK MISSING
977 #define HOST_INT_STATUS_COUNTER_LSB MISSING
978 #define RX_LOOKAHEAD_VALID_ADDRESS MISSING
979 #define WINDOW_DATA_ADDRESS MISSING
980 #define WINDOW_READ_ADDR_ADDRESS MISSING
981 #define WINDOW_WRITE_ADDR_ADDRESS MISSING
983 #define QCA9887_1_0_I2C_SDA_GPIO_PIN 5
984 #define QCA9887_1_0_I2C_SDA_PIN_CONFIG 3
985 #define QCA9887_1_0_SI_CLK_GPIO_PIN 17
986 #define QCA9887_1_0_SI_CLK_PIN_CONFIG 3
987 #define QCA9887_1_0_GPIO_ENABLE_W1TS_LOW_ADDRESS 0x00000010
989 #define QCA9887_EEPROM_SELECT_READ 0xa10000a0
990 #define QCA9887_EEPROM_ADDR_HI_MASK 0x0000ff00
991 #define QCA9887_EEPROM_ADDR_HI_LSB 8
992 #define QCA9887_EEPROM_ADDR_LO_MASK 0x00ff0000
993 #define QCA9887_EEPROM_ADDR_LO_LSB 16
995 #define MBOX_RESET_CONTROL_ADDRESS 0x00000000
996 #define MBOX_HOST_INT_STATUS_ADDRESS 0x00000800
997 #define MBOX_HOST_INT_STATUS_ERROR_LSB 7
998 #define MBOX_HOST_INT_STATUS_ERROR_MASK 0x00000080
999 #define MBOX_HOST_INT_STATUS_CPU_LSB 6
1000 #define MBOX_HOST_INT_STATUS_CPU_MASK 0x00000040
1001 #define MBOX_HOST_INT_STATUS_COUNTER_LSB 4
1002 #define MBOX_HOST_INT_STATUS_COUNTER_MASK 0x00000010
1003 #define MBOX_CPU_INT_STATUS_ADDRESS 0x00000801
1004 #define MBOX_ERROR_INT_STATUS_ADDRESS 0x00000802
1005 #define MBOX_ERROR_INT_STATUS_WAKEUP_LSB 2
1006 #define MBOX_ERROR_INT_STATUS_WAKEUP_MASK 0x00000004
1007 #define MBOX_ERROR_INT_STATUS_RX_UNDERFLOW_LSB 1
1008 #define MBOX_ERROR_INT_STATUS_RX_UNDERFLOW_MASK 0x00000002
1009 #define MBOX_ERROR_INT_STATUS_TX_OVERFLOW_LSB 0
1010 #define MBOX_ERROR_INT_STATUS_TX_OVERFLOW_MASK 0x00000001
1011 #define MBOX_COUNTER_INT_STATUS_ADDRESS 0x00000803
1012 #define MBOX_COUNTER_INT_STATUS_COUNTER_LSB 0
1013 #define MBOX_COUNTER_INT_STATUS_COUNTER_MASK 0x000000ff
1014 #define MBOX_RX_LOOKAHEAD_VALID_ADDRESS 0x00000805
1015 #define MBOX_INT_STATUS_ENABLE_ADDRESS 0x00000828
1016 #define MBOX_INT_STATUS_ENABLE_ERROR_LSB 7
1017 #define MBOX_INT_STATUS_ENABLE_ERROR_MASK 0x00000080
1018 #define MBOX_INT_STATUS_ENABLE_CPU_LSB 6
1019 #define MBOX_INT_STATUS_ENABLE_CPU_MASK 0x00000040
1020 #define MBOX_INT_STATUS_ENABLE_INT_LSB 5
1021 #define MBOX_INT_STATUS_ENABLE_INT_MASK 0x00000020
1022 #define MBOX_INT_STATUS_ENABLE_COUNTER_LSB 4
1023 #define MBOX_INT_STATUS_ENABLE_COUNTER_MASK 0x00000010
1024 #define MBOX_INT_STATUS_ENABLE_MBOX_DATA_LSB 0
1025 #define MBOX_INT_STATUS_ENABLE_MBOX_DATA_MASK 0x0000000f
1026 #define MBOX_CPU_INT_STATUS_ENABLE_ADDRESS 0x00000819
1027 #define MBOX_CPU_INT_STATUS_ENABLE_BIT_LSB 0
1028 #define MBOX_CPU_INT_STATUS_ENABLE_BIT_MASK 0x000000ff
1029 #define MBOX_ERROR_STATUS_ENABLE_ADDRESS 0x0000081a
1030 #define MBOX_ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB 1
1031 #define MBOX_ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK 0x00000002
1032 #define MBOX_ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB 0
1033 #define MBOX_ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK 0x00000001
1034 #define MBOX_COUNTER_INT_STATUS_ENABLE_ADDRESS 0x0000081b
1035 #define MBOX_COUNTER_INT_STATUS_ENABLE_BIT_LSB 0
1036 #define MBOX_COUNTER_INT_STATUS_ENABLE_BIT_MASK 0x000000ff
1037 #define MBOX_COUNT_ADDRESS 0x00000820
1038 #define MBOX_COUNT_DEC_ADDRESS 0x00000840
1039 #define MBOX_WINDOW_DATA_ADDRESS 0x00000874
1040 #define MBOX_WINDOW_WRITE_ADDR_ADDRESS 0x00000878
1041 #define MBOX_WINDOW_READ_ADDR_ADDRESS 0x0000087c
1042 #define MBOX_CPU_DBG_SEL_ADDRESS 0x00000883
1043 #define MBOX_CPU_DBG_ADDRESS 0x00000884
1044 #define MBOX_RTC_BASE_ADDRESS 0x00000000
1045 #define MBOX_GPIO_BASE_ADDRESS 0x00005000
1046 #define MBOX_MBOX_BASE_ADDRESS 0x00008000
1048 #define RTC_STATE_V_GET(x) (((x) & RTC_STATE_V_MASK) >> RTC_STATE_V_LSB)
1050 /* Register definitions for first generation ath10k cards. These cards include
1051 * a mac thich has a register allocation similar to ath9k and at least some
1052 * registers including the ones relevant for modifying the coverage class are
1053 * identical to the ath9k definitions.
1054 * These registers are usually managed by the ath10k firmware. However by
1055 * overriding them it is possible to support coverage class modifications.
1057 #define WAVE1_PCU_ACK_CTS_TIMEOUT 0x8014
1058 #define WAVE1_PCU_ACK_CTS_TIMEOUT_MAX 0x00003FFF
1059 #define WAVE1_PCU_ACK_CTS_TIMEOUT_ACK_MASK 0x00003FFF
1060 #define WAVE1_PCU_ACK_CTS_TIMEOUT_ACK_LSB 0
1061 #define WAVE1_PCU_ACK_CTS_TIMEOUT_CTS_MASK 0x3FFF0000
1062 #define WAVE1_PCU_ACK_CTS_TIMEOUT_CTS_LSB 16
1064 #define WAVE1_PCU_GBL_IFS_SLOT 0x1070
1065 #define WAVE1_PCU_GBL_IFS_SLOT_MASK 0x0000FFFF
1066 #define WAVE1_PCU_GBL_IFS_SLOT_MAX 0x0000FFFF
1067 #define WAVE1_PCU_GBL_IFS_SLOT_LSB 0
1068 #define WAVE1_PCU_GBL_IFS_SLOT_RESV0 0xFFFF0000
1070 #define WAVE1_PHYCLK 0x801C
1071 #define WAVE1_PHYCLK_USEC_MASK 0x0000007F
1072 #define WAVE1_PHYCLK_USEC_LSB 0
1074 /* qca6174 PLL offset/mask */
1075 #define SOC_CORE_CLK_CTRL_OFFSET 0x00000114
1076 #define SOC_CORE_CLK_CTRL_DIV_LSB 0
1077 #define SOC_CORE_CLK_CTRL_DIV_MASK 0x00000007
1079 #define EFUSE_OFFSET 0x0000032c
1080 #define EFUSE_XTAL_SEL_LSB 8
1081 #define EFUSE_XTAL_SEL_MASK 0x00000700
1083 #define BB_PLL_CONFIG_OFFSET 0x000002f4
1084 #define BB_PLL_CONFIG_FRAC_LSB 0
1085 #define BB_PLL_CONFIG_FRAC_MASK 0x0003ffff
1086 #define BB_PLL_CONFIG_OUTDIV_LSB 18
1087 #define BB_PLL_CONFIG_OUTDIV_MASK 0x001c0000
1089 #define WLAN_PLL_SETTLE_OFFSET 0x0018
1090 #define WLAN_PLL_SETTLE_TIME_LSB 0
1091 #define WLAN_PLL_SETTLE_TIME_MASK 0x000007ff
1093 #define WLAN_PLL_CONTROL_OFFSET 0x0014
1094 #define WLAN_PLL_CONTROL_DIV_LSB 0
1095 #define WLAN_PLL_CONTROL_DIV_MASK 0x000003ff
1096 #define WLAN_PLL_CONTROL_REFDIV_LSB 10
1097 #define WLAN_PLL_CONTROL_REFDIV_MASK 0x00003c00
1098 #define WLAN_PLL_CONTROL_BYPASS_LSB 16
1099 #define WLAN_PLL_CONTROL_BYPASS_MASK 0x00010000
1100 #define WLAN_PLL_CONTROL_NOPWD_LSB 18
1101 #define WLAN_PLL_CONTROL_NOPWD_MASK 0x00040000
1103 #define RTC_SYNC_STATUS_OFFSET 0x0244
1104 #define RTC_SYNC_STATUS_PLL_CHANGING_LSB 5
1105 #define RTC_SYNC_STATUS_PLL_CHANGING_MASK 0x00000020
1106 /* qca6174 PLL offset/mask end */