1 // SPDX-License-Identifier: ISC
3 * Copyright (c) 2018 The Linux Foundation. All rights reserved.
7 #include <linux/kernel.h>
8 #include <linux/module.h>
10 #include <linux/of_device.h>
11 #include <linux/platform_device.h>
12 #include <linux/regulator/consumer.h>
20 #define ATH10K_SNOC_RX_POST_RETRY_MS 50
21 #define CE_POLL_PIPE 4
22 #define ATH10K_SNOC_WAKE_IRQ 2
24 static char *const ce_name[] = {
39 static struct ath10k_vreg_info vreg_cfg[] = {
40 {NULL, "vdd-0.8-cx-mx", 800000, 850000, 0, 0, false},
41 {NULL, "vdd-1.8-xo", 1800000, 1850000, 0, 0, false},
42 {NULL, "vdd-1.3-rfa", 1300000, 1350000, 0, 0, false},
43 {NULL, "vdd-3.3-ch0", 3300000, 3350000, 0, 0, false},
46 static struct ath10k_clk_info clk_cfg[] = {
47 {NULL, "cxo_ref_clk_pin", 0, false},
50 static void ath10k_snoc_htc_tx_cb(struct ath10k_ce_pipe *ce_state);
51 static void ath10k_snoc_htt_tx_cb(struct ath10k_ce_pipe *ce_state);
52 static void ath10k_snoc_htc_rx_cb(struct ath10k_ce_pipe *ce_state);
53 static void ath10k_snoc_htt_rx_cb(struct ath10k_ce_pipe *ce_state);
54 static void ath10k_snoc_htt_htc_rx_cb(struct ath10k_ce_pipe *ce_state);
55 static void ath10k_snoc_pktlog_rx_cb(struct ath10k_ce_pipe *ce_state);
57 static const struct ath10k_snoc_drv_priv drv_priv = {
58 .hw_rev = ATH10K_HW_WCN3990,
59 .dma_mask = DMA_BIT_MASK(35),
63 #define WCN3990_SRC_WR_IDX_OFFSET 0x3C
64 #define WCN3990_DST_WR_IDX_OFFSET 0x40
66 static struct ath10k_shadow_reg_cfg target_shadow_reg_cfg_map[] = {
68 .ce_id = __cpu_to_le16(0),
69 .reg_offset = __cpu_to_le16(WCN3990_SRC_WR_IDX_OFFSET),
73 .ce_id = __cpu_to_le16(3),
74 .reg_offset = __cpu_to_le16(WCN3990_SRC_WR_IDX_OFFSET),
78 .ce_id = __cpu_to_le16(4),
79 .reg_offset = __cpu_to_le16(WCN3990_SRC_WR_IDX_OFFSET),
83 .ce_id = __cpu_to_le16(5),
84 .reg_offset = __cpu_to_le16(WCN3990_SRC_WR_IDX_OFFSET),
88 .ce_id = __cpu_to_le16(7),
89 .reg_offset = __cpu_to_le16(WCN3990_SRC_WR_IDX_OFFSET),
93 .ce_id = __cpu_to_le16(1),
94 .reg_offset = __cpu_to_le16(WCN3990_DST_WR_IDX_OFFSET),
98 .ce_id = __cpu_to_le16(2),
99 .reg_offset = __cpu_to_le16(WCN3990_DST_WR_IDX_OFFSET),
103 .ce_id = __cpu_to_le16(7),
104 .reg_offset = __cpu_to_le16(WCN3990_DST_WR_IDX_OFFSET),
108 .ce_id = __cpu_to_le16(8),
109 .reg_offset = __cpu_to_le16(WCN3990_DST_WR_IDX_OFFSET),
113 .ce_id = __cpu_to_le16(9),
114 .reg_offset = __cpu_to_le16(WCN3990_DST_WR_IDX_OFFSET),
118 .ce_id = __cpu_to_le16(10),
119 .reg_offset = __cpu_to_le16(WCN3990_DST_WR_IDX_OFFSET),
123 .ce_id = __cpu_to_le16(11),
124 .reg_offset = __cpu_to_le16(WCN3990_DST_WR_IDX_OFFSET),
128 static struct ce_attr host_ce_config_wlan[] = {
129 /* CE0: host->target HTC control streams */
131 .flags = CE_ATTR_FLAGS,
135 .send_cb = ath10k_snoc_htc_tx_cb,
138 /* CE1: target->host HTT + HTC control */
140 .flags = CE_ATTR_FLAGS,
143 .dest_nentries = 512,
144 .recv_cb = ath10k_snoc_htt_htc_rx_cb,
147 /* CE2: target->host WMI */
149 .flags = CE_ATTR_FLAGS,
153 .recv_cb = ath10k_snoc_htc_rx_cb,
156 /* CE3: host->target WMI */
158 .flags = CE_ATTR_FLAGS,
162 .send_cb = ath10k_snoc_htc_tx_cb,
165 /* CE4: host->target HTT */
167 .flags = CE_ATTR_FLAGS | CE_ATTR_DIS_INTR,
168 .src_nentries = 2048,
171 .send_cb = ath10k_snoc_htt_tx_cb,
174 /* CE5: target->host HTT (ipa_uc->target ) */
176 .flags = CE_ATTR_FLAGS,
179 .dest_nentries = 512,
180 .recv_cb = ath10k_snoc_htt_rx_cb,
183 /* CE6: target autonomous hif_memcpy */
185 .flags = CE_ATTR_FLAGS,
191 /* CE7: ce_diag, the Diagnostic Window */
193 .flags = CE_ATTR_FLAGS,
199 /* CE8: Target to uMC */
201 .flags = CE_ATTR_FLAGS,
204 .dest_nentries = 128,
207 /* CE9 target->host HTT */
209 .flags = CE_ATTR_FLAGS,
212 .dest_nentries = 512,
213 .recv_cb = ath10k_snoc_htt_htc_rx_cb,
216 /* CE10: target->host HTT */
218 .flags = CE_ATTR_FLAGS,
221 .dest_nentries = 512,
222 .recv_cb = ath10k_snoc_htt_htc_rx_cb,
225 /* CE11: target -> host PKTLOG */
227 .flags = CE_ATTR_FLAGS,
230 .dest_nentries = 512,
231 .recv_cb = ath10k_snoc_pktlog_rx_cb,
235 static struct ce_pipe_config target_ce_config_wlan[] = {
236 /* CE0: host->target HTC control and raw streams */
238 .pipenum = __cpu_to_le32(0),
239 .pipedir = __cpu_to_le32(PIPEDIR_OUT),
240 .nentries = __cpu_to_le32(32),
241 .nbytes_max = __cpu_to_le32(2048),
242 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
243 .reserved = __cpu_to_le32(0),
246 /* CE1: target->host HTT + HTC control */
248 .pipenum = __cpu_to_le32(1),
249 .pipedir = __cpu_to_le32(PIPEDIR_IN),
250 .nentries = __cpu_to_le32(32),
251 .nbytes_max = __cpu_to_le32(2048),
252 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
253 .reserved = __cpu_to_le32(0),
256 /* CE2: target->host WMI */
258 .pipenum = __cpu_to_le32(2),
259 .pipedir = __cpu_to_le32(PIPEDIR_IN),
260 .nentries = __cpu_to_le32(64),
261 .nbytes_max = __cpu_to_le32(2048),
262 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
263 .reserved = __cpu_to_le32(0),
266 /* CE3: host->target WMI */
268 .pipenum = __cpu_to_le32(3),
269 .pipedir = __cpu_to_le32(PIPEDIR_OUT),
270 .nentries = __cpu_to_le32(32),
271 .nbytes_max = __cpu_to_le32(2048),
272 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
273 .reserved = __cpu_to_le32(0),
276 /* CE4: host->target HTT */
278 .pipenum = __cpu_to_le32(4),
279 .pipedir = __cpu_to_le32(PIPEDIR_OUT),
280 .nentries = __cpu_to_le32(256),
281 .nbytes_max = __cpu_to_le32(256),
282 .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR),
283 .reserved = __cpu_to_le32(0),
286 /* CE5: target->host HTT (HIF->HTT) */
288 .pipenum = __cpu_to_le32(5),
289 .pipedir = __cpu_to_le32(PIPEDIR_OUT),
290 .nentries = __cpu_to_le32(1024),
291 .nbytes_max = __cpu_to_le32(64),
292 .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR),
293 .reserved = __cpu_to_le32(0),
296 /* CE6: Reserved for target autonomous hif_memcpy */
298 .pipenum = __cpu_to_le32(6),
299 .pipedir = __cpu_to_le32(PIPEDIR_INOUT),
300 .nentries = __cpu_to_le32(32),
301 .nbytes_max = __cpu_to_le32(16384),
302 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
303 .reserved = __cpu_to_le32(0),
306 /* CE7 used only by Host */
308 .pipenum = __cpu_to_le32(7),
309 .pipedir = __cpu_to_le32(4),
310 .nentries = __cpu_to_le32(0),
311 .nbytes_max = __cpu_to_le32(0),
312 .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR),
313 .reserved = __cpu_to_le32(0),
316 /* CE8 Target to uMC */
318 .pipenum = __cpu_to_le32(8),
319 .pipedir = __cpu_to_le32(PIPEDIR_IN),
320 .nentries = __cpu_to_le32(32),
321 .nbytes_max = __cpu_to_le32(2048),
322 .flags = __cpu_to_le32(0),
323 .reserved = __cpu_to_le32(0),
326 /* CE9 target->host HTT */
328 .pipenum = __cpu_to_le32(9),
329 .pipedir = __cpu_to_le32(PIPEDIR_IN),
330 .nentries = __cpu_to_le32(32),
331 .nbytes_max = __cpu_to_le32(2048),
332 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
333 .reserved = __cpu_to_le32(0),
336 /* CE10 target->host HTT */
338 .pipenum = __cpu_to_le32(10),
339 .pipedir = __cpu_to_le32(PIPEDIR_IN),
340 .nentries = __cpu_to_le32(32),
341 .nbytes_max = __cpu_to_le32(2048),
342 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
343 .reserved = __cpu_to_le32(0),
346 /* CE11 target autonomous qcache memcpy */
348 .pipenum = __cpu_to_le32(11),
349 .pipedir = __cpu_to_le32(PIPEDIR_IN),
350 .nentries = __cpu_to_le32(32),
351 .nbytes_max = __cpu_to_le32(2048),
352 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
353 .reserved = __cpu_to_le32(0),
357 static struct service_to_pipe target_service_to_ce_map_wlan[] = {
359 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VO),
360 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
364 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VO),
365 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
369 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BK),
370 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
374 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BK),
375 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
379 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BE),
380 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
384 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BE),
385 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
389 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VI),
390 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
394 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VI),
395 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
399 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_CONTROL),
400 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
404 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_CONTROL),
405 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
409 __cpu_to_le32(ATH10K_HTC_SVC_ID_RSVD_CTRL),
410 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
414 __cpu_to_le32(ATH10K_HTC_SVC_ID_RSVD_CTRL),
415 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
419 __cpu_to_le32(ATH10K_HTC_SVC_ID_TEST_RAW_STREAMS),
420 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
424 __cpu_to_le32(ATH10K_HTC_SVC_ID_TEST_RAW_STREAMS),
425 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
429 __cpu_to_le32(ATH10K_HTC_SVC_ID_HTT_DATA_MSG),
430 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
434 __cpu_to_le32(ATH10K_HTC_SVC_ID_HTT_DATA_MSG),
435 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
439 __cpu_to_le32(ATH10K_HTC_SVC_ID_TEST_RAW_STREAMS),
440 __cpu_to_le32(PIPEDIR_OUT),
443 { /* in = DL = target -> host */
444 __cpu_to_le32(ATH10K_HTC_SVC_ID_HTT_DATA2_MSG),
445 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
448 { /* in = DL = target -> host */
449 __cpu_to_le32(ATH10K_HTC_SVC_ID_HTT_DATA3_MSG),
450 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
453 { /* in = DL = target -> host pktlog */
454 __cpu_to_le32(ATH10K_HTC_SVC_ID_HTT_LOG_MSG),
455 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
458 /* (Additions here) */
467 static void ath10k_snoc_write32(struct ath10k *ar, u32 offset, u32 value)
469 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
471 iowrite32(value, ar_snoc->mem + offset);
474 static u32 ath10k_snoc_read32(struct ath10k *ar, u32 offset)
476 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
479 val = ioread32(ar_snoc->mem + offset);
484 static int __ath10k_snoc_rx_post_buf(struct ath10k_snoc_pipe *pipe)
486 struct ath10k_ce_pipe *ce_pipe = pipe->ce_hdl;
487 struct ath10k *ar = pipe->hif_ce_state;
488 struct ath10k_ce *ce = ath10k_ce_priv(ar);
493 skb = dev_alloc_skb(pipe->buf_sz);
497 WARN_ONCE((unsigned long)skb->data & 3, "unaligned skb");
499 paddr = dma_map_single(ar->dev, skb->data,
500 skb->len + skb_tailroom(skb),
502 if (unlikely(dma_mapping_error(ar->dev, paddr))) {
503 ath10k_warn(ar, "failed to dma map snoc rx buf\n");
504 dev_kfree_skb_any(skb);
508 ATH10K_SKB_RXCB(skb)->paddr = paddr;
510 spin_lock_bh(&ce->ce_lock);
511 ret = ce_pipe->ops->ce_rx_post_buf(ce_pipe, skb, paddr);
512 spin_unlock_bh(&ce->ce_lock);
514 dma_unmap_single(ar->dev, paddr, skb->len + skb_tailroom(skb),
516 dev_kfree_skb_any(skb);
523 static void ath10k_snoc_rx_post_pipe(struct ath10k_snoc_pipe *pipe)
525 struct ath10k *ar = pipe->hif_ce_state;
526 struct ath10k_ce *ce = ath10k_ce_priv(ar);
527 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
528 struct ath10k_ce_pipe *ce_pipe = pipe->ce_hdl;
531 if (pipe->buf_sz == 0)
534 if (!ce_pipe->dest_ring)
537 spin_lock_bh(&ce->ce_lock);
538 num = __ath10k_ce_rx_num_free_bufs(ce_pipe);
539 spin_unlock_bh(&ce->ce_lock);
541 ret = __ath10k_snoc_rx_post_buf(pipe);
545 ath10k_warn(ar, "failed to post rx buf: %d\n", ret);
546 mod_timer(&ar_snoc->rx_post_retry, jiffies +
547 ATH10K_SNOC_RX_POST_RETRY_MS);
553 static void ath10k_snoc_rx_post(struct ath10k *ar)
555 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
558 for (i = 0; i < CE_COUNT; i++)
559 ath10k_snoc_rx_post_pipe(&ar_snoc->pipe_info[i]);
562 static void ath10k_snoc_process_rx_cb(struct ath10k_ce_pipe *ce_state,
563 void (*callback)(struct ath10k *ar,
564 struct sk_buff *skb))
566 struct ath10k *ar = ce_state->ar;
567 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
568 struct ath10k_snoc_pipe *pipe_info = &ar_snoc->pipe_info[ce_state->id];
570 struct sk_buff_head list;
571 void *transfer_context;
572 unsigned int nbytes, max_nbytes;
574 __skb_queue_head_init(&list);
575 while (ath10k_ce_completed_recv_next(ce_state, &transfer_context,
577 skb = transfer_context;
578 max_nbytes = skb->len + skb_tailroom(skb);
579 dma_unmap_single(ar->dev, ATH10K_SKB_RXCB(skb)->paddr,
580 max_nbytes, DMA_FROM_DEVICE);
582 if (unlikely(max_nbytes < nbytes)) {
583 ath10k_warn(ar, "rxed more than expected (nbytes %d, max %d)",
585 dev_kfree_skb_any(skb);
589 skb_put(skb, nbytes);
590 __skb_queue_tail(&list, skb);
593 while ((skb = __skb_dequeue(&list))) {
594 ath10k_dbg(ar, ATH10K_DBG_SNOC, "snoc rx ce pipe %d len %d\n",
595 ce_state->id, skb->len);
600 ath10k_snoc_rx_post_pipe(pipe_info);
603 static void ath10k_snoc_htc_rx_cb(struct ath10k_ce_pipe *ce_state)
605 ath10k_snoc_process_rx_cb(ce_state, ath10k_htc_rx_completion_handler);
608 static void ath10k_snoc_htt_htc_rx_cb(struct ath10k_ce_pipe *ce_state)
610 /* CE4 polling needs to be done whenever CE pipe which transports
611 * HTT Rx (target->host) is processed.
613 ath10k_ce_per_engine_service(ce_state->ar, CE_POLL_PIPE);
615 ath10k_snoc_process_rx_cb(ce_state, ath10k_htc_rx_completion_handler);
618 /* Called by lower (CE) layer when data is received from the Target.
619 * WCN3990 firmware uses separate CE(CE11) to transfer pktlog data.
621 static void ath10k_snoc_pktlog_rx_cb(struct ath10k_ce_pipe *ce_state)
623 ath10k_snoc_process_rx_cb(ce_state, ath10k_htc_rx_completion_handler);
626 static void ath10k_snoc_htt_rx_deliver(struct ath10k *ar, struct sk_buff *skb)
628 skb_pull(skb, sizeof(struct ath10k_htc_hdr));
629 ath10k_htt_t2h_msg_handler(ar, skb);
632 static void ath10k_snoc_htt_rx_cb(struct ath10k_ce_pipe *ce_state)
634 ath10k_ce_per_engine_service(ce_state->ar, CE_POLL_PIPE);
635 ath10k_snoc_process_rx_cb(ce_state, ath10k_snoc_htt_rx_deliver);
638 static void ath10k_snoc_rx_replenish_retry(struct timer_list *t)
640 struct ath10k_snoc *ar_snoc = from_timer(ar_snoc, t, rx_post_retry);
641 struct ath10k *ar = ar_snoc->ar;
643 ath10k_snoc_rx_post(ar);
646 static void ath10k_snoc_htc_tx_cb(struct ath10k_ce_pipe *ce_state)
648 struct ath10k *ar = ce_state->ar;
649 struct sk_buff_head list;
652 __skb_queue_head_init(&list);
653 while (ath10k_ce_completed_send_next(ce_state, (void **)&skb) == 0) {
657 __skb_queue_tail(&list, skb);
660 while ((skb = __skb_dequeue(&list)))
661 ath10k_htc_tx_completion_handler(ar, skb);
664 static void ath10k_snoc_htt_tx_cb(struct ath10k_ce_pipe *ce_state)
666 struct ath10k *ar = ce_state->ar;
669 while (ath10k_ce_completed_send_next(ce_state, (void **)&skb) == 0) {
673 dma_unmap_single(ar->dev, ATH10K_SKB_CB(skb)->paddr,
674 skb->len, DMA_TO_DEVICE);
675 ath10k_htt_hif_tx_complete(ar, skb);
679 static int ath10k_snoc_hif_tx_sg(struct ath10k *ar, u8 pipe_id,
680 struct ath10k_hif_sg_item *items, int n_items)
682 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
683 struct ath10k_ce *ce = ath10k_ce_priv(ar);
684 struct ath10k_snoc_pipe *snoc_pipe;
685 struct ath10k_ce_pipe *ce_pipe;
688 snoc_pipe = &ar_snoc->pipe_info[pipe_id];
689 ce_pipe = snoc_pipe->ce_hdl;
690 spin_lock_bh(&ce->ce_lock);
692 for (i = 0; i < n_items - 1; i++) {
693 ath10k_dbg(ar, ATH10K_DBG_SNOC,
694 "snoc tx item %d paddr %pad len %d n_items %d\n",
695 i, &items[i].paddr, items[i].len, n_items);
697 err = ath10k_ce_send_nolock(ce_pipe,
698 items[i].transfer_context,
701 items[i].transfer_id,
702 CE_SEND_FLAG_GATHER);
707 ath10k_dbg(ar, ATH10K_DBG_SNOC,
708 "snoc tx item %d paddr %pad len %d n_items %d\n",
709 i, &items[i].paddr, items[i].len, n_items);
711 err = ath10k_ce_send_nolock(ce_pipe,
712 items[i].transfer_context,
715 items[i].transfer_id,
720 spin_unlock_bh(&ce->ce_lock);
726 __ath10k_ce_send_revert(ce_pipe);
728 spin_unlock_bh(&ce->ce_lock);
732 static int ath10k_snoc_hif_get_target_info(struct ath10k *ar,
733 struct bmi_target_info *target_info)
735 target_info->version = ATH10K_HW_WCN3990;
736 target_info->type = ATH10K_HW_WCN3990;
741 static u16 ath10k_snoc_hif_get_free_queue_number(struct ath10k *ar, u8 pipe)
743 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
745 ath10k_dbg(ar, ATH10K_DBG_SNOC, "hif get free queue number\n");
747 return ath10k_ce_num_free_src_entries(ar_snoc->pipe_info[pipe].ce_hdl);
750 static void ath10k_snoc_hif_send_complete_check(struct ath10k *ar, u8 pipe,
755 ath10k_dbg(ar, ATH10K_DBG_SNOC, "snoc hif send complete check\n");
758 resources = ath10k_snoc_hif_get_free_queue_number(ar, pipe);
760 if (resources > (host_ce_config_wlan[pipe].src_nentries >> 1))
763 ath10k_ce_per_engine_service(ar, pipe);
766 static int ath10k_snoc_hif_map_service_to_pipe(struct ath10k *ar,
768 u8 *ul_pipe, u8 *dl_pipe)
770 const struct service_to_pipe *entry;
771 bool ul_set = false, dl_set = false;
774 ath10k_dbg(ar, ATH10K_DBG_SNOC, "snoc hif map service\n");
776 for (i = 0; i < ARRAY_SIZE(target_service_to_ce_map_wlan); i++) {
777 entry = &target_service_to_ce_map_wlan[i];
779 if (__le32_to_cpu(entry->service_id) != service_id)
782 switch (__le32_to_cpu(entry->pipedir)) {
787 *dl_pipe = __le32_to_cpu(entry->pipenum);
792 *ul_pipe = __le32_to_cpu(entry->pipenum);
798 *dl_pipe = __le32_to_cpu(entry->pipenum);
799 *ul_pipe = __le32_to_cpu(entry->pipenum);
806 if (!ul_set || !dl_set)
812 static void ath10k_snoc_hif_get_default_pipe(struct ath10k *ar,
813 u8 *ul_pipe, u8 *dl_pipe)
815 ath10k_dbg(ar, ATH10K_DBG_SNOC, "snoc hif get default pipe\n");
817 (void)ath10k_snoc_hif_map_service_to_pipe(ar,
818 ATH10K_HTC_SVC_ID_RSVD_CTRL,
822 static inline void ath10k_snoc_irq_disable(struct ath10k *ar)
824 ath10k_ce_disable_interrupts(ar);
827 static inline void ath10k_snoc_irq_enable(struct ath10k *ar)
829 ath10k_ce_enable_interrupts(ar);
832 static void ath10k_snoc_rx_pipe_cleanup(struct ath10k_snoc_pipe *snoc_pipe)
834 struct ath10k_ce_pipe *ce_pipe;
835 struct ath10k_ce_ring *ce_ring;
840 ar = snoc_pipe->hif_ce_state;
841 ce_pipe = snoc_pipe->ce_hdl;
842 ce_ring = ce_pipe->dest_ring;
847 if (!snoc_pipe->buf_sz)
850 for (i = 0; i < ce_ring->nentries; i++) {
851 skb = ce_ring->per_transfer_context[i];
855 ce_ring->per_transfer_context[i] = NULL;
857 dma_unmap_single(ar->dev, ATH10K_SKB_RXCB(skb)->paddr,
858 skb->len + skb_tailroom(skb),
860 dev_kfree_skb_any(skb);
864 static void ath10k_snoc_tx_pipe_cleanup(struct ath10k_snoc_pipe *snoc_pipe)
866 struct ath10k_ce_pipe *ce_pipe;
867 struct ath10k_ce_ring *ce_ring;
872 ar = snoc_pipe->hif_ce_state;
873 ce_pipe = snoc_pipe->ce_hdl;
874 ce_ring = ce_pipe->src_ring;
879 if (!snoc_pipe->buf_sz)
882 for (i = 0; i < ce_ring->nentries; i++) {
883 skb = ce_ring->per_transfer_context[i];
887 ce_ring->per_transfer_context[i] = NULL;
889 ath10k_htc_tx_completion_handler(ar, skb);
893 static void ath10k_snoc_buffer_cleanup(struct ath10k *ar)
895 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
896 struct ath10k_snoc_pipe *pipe_info;
899 del_timer_sync(&ar_snoc->rx_post_retry);
900 for (pipe_num = 0; pipe_num < CE_COUNT; pipe_num++) {
901 pipe_info = &ar_snoc->pipe_info[pipe_num];
902 ath10k_snoc_rx_pipe_cleanup(pipe_info);
903 ath10k_snoc_tx_pipe_cleanup(pipe_info);
907 static void ath10k_snoc_hif_stop(struct ath10k *ar)
909 if (!test_bit(ATH10K_FLAG_CRASH_FLUSH, &ar->dev_flags))
910 ath10k_snoc_irq_disable(ar);
912 napi_synchronize(&ar->napi);
913 napi_disable(&ar->napi);
914 ath10k_snoc_buffer_cleanup(ar);
915 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot hif stop\n");
918 static int ath10k_snoc_hif_start(struct ath10k *ar)
920 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
922 napi_enable(&ar->napi);
923 ath10k_snoc_irq_enable(ar);
924 ath10k_snoc_rx_post(ar);
926 clear_bit(ATH10K_SNOC_FLAG_RECOVERY, &ar_snoc->flags);
928 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot hif start\n");
933 static int ath10k_snoc_init_pipes(struct ath10k *ar)
937 for (i = 0; i < CE_COUNT; i++) {
938 ret = ath10k_ce_init_pipe(ar, i, &host_ce_config_wlan[i]);
940 ath10k_err(ar, "failed to initialize copy engine pipe %d: %d\n",
949 static int ath10k_snoc_wlan_enable(struct ath10k *ar,
950 enum ath10k_firmware_mode fw_mode)
952 struct ath10k_tgt_pipe_cfg tgt_cfg[CE_COUNT_MAX];
953 struct ath10k_qmi_wlan_enable_cfg cfg;
954 enum wlfw_driver_mode_enum_v01 mode;
957 for (pipe_num = 0; pipe_num < CE_COUNT_MAX; pipe_num++) {
958 tgt_cfg[pipe_num].pipe_num =
959 target_ce_config_wlan[pipe_num].pipenum;
960 tgt_cfg[pipe_num].pipe_dir =
961 target_ce_config_wlan[pipe_num].pipedir;
962 tgt_cfg[pipe_num].nentries =
963 target_ce_config_wlan[pipe_num].nentries;
964 tgt_cfg[pipe_num].nbytes_max =
965 target_ce_config_wlan[pipe_num].nbytes_max;
966 tgt_cfg[pipe_num].flags =
967 target_ce_config_wlan[pipe_num].flags;
968 tgt_cfg[pipe_num].reserved = 0;
971 cfg.num_ce_tgt_cfg = sizeof(target_ce_config_wlan) /
972 sizeof(struct ath10k_tgt_pipe_cfg);
973 cfg.ce_tgt_cfg = (struct ath10k_tgt_pipe_cfg *)
975 cfg.num_ce_svc_pipe_cfg = sizeof(target_service_to_ce_map_wlan) /
976 sizeof(struct ath10k_svc_pipe_cfg);
977 cfg.ce_svc_cfg = (struct ath10k_svc_pipe_cfg *)
978 &target_service_to_ce_map_wlan;
979 cfg.num_shadow_reg_cfg = sizeof(target_shadow_reg_cfg_map) /
980 sizeof(struct ath10k_shadow_reg_cfg);
981 cfg.shadow_reg_cfg = (struct ath10k_shadow_reg_cfg *)
982 &target_shadow_reg_cfg_map;
985 case ATH10K_FIRMWARE_MODE_NORMAL:
986 mode = QMI_WLFW_MISSION_V01;
988 case ATH10K_FIRMWARE_MODE_UTF:
989 mode = QMI_WLFW_FTM_V01;
992 ath10k_err(ar, "invalid firmware mode %d\n", fw_mode);
996 return ath10k_qmi_wlan_enable(ar, &cfg, mode,
1000 static void ath10k_snoc_wlan_disable(struct ath10k *ar)
1002 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
1004 /* If both ATH10K_FLAG_CRASH_FLUSH and ATH10K_SNOC_FLAG_RECOVERY
1005 * flags are not set, it means that the driver has restarted
1006 * due to a crash inject via debugfs. In this case, the driver
1007 * needs to restart the firmware and hence send qmi wlan disable,
1008 * during the driver restart sequence.
1010 if (!test_bit(ATH10K_FLAG_CRASH_FLUSH, &ar->dev_flags) ||
1011 !test_bit(ATH10K_SNOC_FLAG_RECOVERY, &ar_snoc->flags))
1012 ath10k_qmi_wlan_disable(ar);
1015 static void ath10k_snoc_hif_power_down(struct ath10k *ar)
1017 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot hif power down\n");
1019 ath10k_snoc_wlan_disable(ar);
1020 ath10k_ce_free_rri(ar);
1023 static int ath10k_snoc_hif_power_up(struct ath10k *ar,
1024 enum ath10k_firmware_mode fw_mode)
1028 ath10k_dbg(ar, ATH10K_DBG_SNOC, "%s:WCN3990 driver state = %d\n",
1029 __func__, ar->state);
1031 ret = ath10k_snoc_wlan_enable(ar, fw_mode);
1033 ath10k_err(ar, "failed to enable wcn3990: %d\n", ret);
1037 ath10k_ce_alloc_rri(ar);
1039 ret = ath10k_snoc_init_pipes(ar);
1041 ath10k_err(ar, "failed to initialize CE: %d\n", ret);
1042 goto err_wlan_enable;
1048 ath10k_snoc_wlan_disable(ar);
1053 static int ath10k_snoc_hif_set_target_log_mode(struct ath10k *ar,
1059 fw_dbg_mode = ATH10K_ENABLE_FW_LOG_CE;
1061 fw_dbg_mode = ATH10K_ENABLE_FW_LOG_DIAG;
1063 return ath10k_qmi_set_fw_log_mode(ar, fw_dbg_mode);
1067 static int ath10k_snoc_hif_suspend(struct ath10k *ar)
1069 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
1072 if (!device_may_wakeup(ar->dev))
1075 ret = enable_irq_wake(ar_snoc->ce_irqs[ATH10K_SNOC_WAKE_IRQ].irq_line);
1077 ath10k_err(ar, "failed to enable wakeup irq :%d\n", ret);
1081 ath10k_dbg(ar, ATH10K_DBG_SNOC, "snoc device suspended\n");
1086 static int ath10k_snoc_hif_resume(struct ath10k *ar)
1088 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
1091 if (!device_may_wakeup(ar->dev))
1094 ret = disable_irq_wake(ar_snoc->ce_irqs[ATH10K_SNOC_WAKE_IRQ].irq_line);
1096 ath10k_err(ar, "failed to disable wakeup irq: %d\n", ret);
1100 ath10k_dbg(ar, ATH10K_DBG_SNOC, "snoc device resumed\n");
1106 static const struct ath10k_hif_ops ath10k_snoc_hif_ops = {
1107 .read32 = ath10k_snoc_read32,
1108 .write32 = ath10k_snoc_write32,
1109 .start = ath10k_snoc_hif_start,
1110 .stop = ath10k_snoc_hif_stop,
1111 .map_service_to_pipe = ath10k_snoc_hif_map_service_to_pipe,
1112 .get_default_pipe = ath10k_snoc_hif_get_default_pipe,
1113 .power_up = ath10k_snoc_hif_power_up,
1114 .power_down = ath10k_snoc_hif_power_down,
1115 .tx_sg = ath10k_snoc_hif_tx_sg,
1116 .send_complete_check = ath10k_snoc_hif_send_complete_check,
1117 .get_free_queue_number = ath10k_snoc_hif_get_free_queue_number,
1118 .get_target_info = ath10k_snoc_hif_get_target_info,
1119 .set_target_log_mode = ath10k_snoc_hif_set_target_log_mode,
1122 .suspend = ath10k_snoc_hif_suspend,
1123 .resume = ath10k_snoc_hif_resume,
1127 static const struct ath10k_bus_ops ath10k_snoc_bus_ops = {
1128 .read32 = ath10k_snoc_read32,
1129 .write32 = ath10k_snoc_write32,
1132 static int ath10k_snoc_get_ce_id_from_irq(struct ath10k *ar, int irq)
1134 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
1137 for (i = 0; i < CE_COUNT_MAX; i++) {
1138 if (ar_snoc->ce_irqs[i].irq_line == irq)
1141 ath10k_err(ar, "No matching CE id for irq %d\n", irq);
1146 static irqreturn_t ath10k_snoc_per_engine_handler(int irq, void *arg)
1148 struct ath10k *ar = arg;
1149 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
1150 int ce_id = ath10k_snoc_get_ce_id_from_irq(ar, irq);
1152 if (ce_id < 0 || ce_id >= ARRAY_SIZE(ar_snoc->pipe_info)) {
1153 ath10k_warn(ar, "unexpected/invalid irq %d ce_id %d\n", irq,
1158 ath10k_snoc_irq_disable(ar);
1159 napi_schedule(&ar->napi);
1164 static int ath10k_snoc_napi_poll(struct napi_struct *ctx, int budget)
1166 struct ath10k *ar = container_of(ctx, struct ath10k, napi);
1169 if (test_bit(ATH10K_FLAG_CRASH_FLUSH, &ar->dev_flags)) {
1174 ath10k_ce_per_engine_service_any(ar);
1175 done = ath10k_htt_txrx_compl_task(ar, budget);
1177 if (done < budget) {
1179 ath10k_snoc_irq_enable(ar);
1185 static void ath10k_snoc_init_napi(struct ath10k *ar)
1187 netif_napi_add(&ar->napi_dev, &ar->napi, ath10k_snoc_napi_poll,
1188 ATH10K_NAPI_BUDGET);
1191 static int ath10k_snoc_request_irq(struct ath10k *ar)
1193 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
1194 int irqflags = IRQF_TRIGGER_RISING;
1197 for (id = 0; id < CE_COUNT_MAX; id++) {
1198 ret = request_irq(ar_snoc->ce_irqs[id].irq_line,
1199 ath10k_snoc_per_engine_handler,
1200 irqflags, ce_name[id], ar);
1203 "failed to register IRQ handler for CE %d: %d",
1212 for (id -= 1; id >= 0; id--)
1213 free_irq(ar_snoc->ce_irqs[id].irq_line, ar);
1218 static void ath10k_snoc_free_irq(struct ath10k *ar)
1220 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
1223 for (id = 0; id < CE_COUNT_MAX; id++)
1224 free_irq(ar_snoc->ce_irqs[id].irq_line, ar);
1227 static int ath10k_snoc_resource_init(struct ath10k *ar)
1229 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
1230 struct platform_device *pdev;
1231 struct resource *res;
1234 pdev = ar_snoc->dev;
1235 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "membase");
1237 ath10k_err(ar, "Memory base not found in DT\n");
1241 ar_snoc->mem_pa = res->start;
1242 ar_snoc->mem = devm_ioremap(&pdev->dev, ar_snoc->mem_pa,
1243 resource_size(res));
1244 if (!ar_snoc->mem) {
1245 ath10k_err(ar, "Memory base ioremap failed with physical address %pa\n",
1250 for (i = 0; i < CE_COUNT; i++) {
1251 res = platform_get_resource(ar_snoc->dev, IORESOURCE_IRQ, i);
1253 ath10k_err(ar, "failed to get IRQ%d\n", i);
1257 ar_snoc->ce_irqs[i].irq_line = res->start;
1264 int ath10k_snoc_fw_indication(struct ath10k *ar, u64 type)
1266 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
1267 struct ath10k_bus_params bus_params = {};
1270 if (test_bit(ATH10K_SNOC_FLAG_UNREGISTERING, &ar_snoc->flags))
1274 case ATH10K_QMI_EVENT_FW_READY_IND:
1275 if (test_bit(ATH10K_SNOC_FLAG_REGISTERED, &ar_snoc->flags)) {
1276 queue_work(ar->workqueue, &ar->restart_work);
1280 bus_params.dev_type = ATH10K_DEV_TYPE_LL;
1281 bus_params.chip_id = ar_snoc->target_info.soc_version;
1282 ret = ath10k_core_register(ar, &bus_params);
1284 ath10k_err(ar, "Failed to register driver core: %d\n",
1288 set_bit(ATH10K_SNOC_FLAG_REGISTERED, &ar_snoc->flags);
1290 case ATH10K_QMI_EVENT_FW_DOWN_IND:
1291 set_bit(ATH10K_SNOC_FLAG_RECOVERY, &ar_snoc->flags);
1292 set_bit(ATH10K_FLAG_CRASH_FLUSH, &ar->dev_flags);
1295 ath10k_err(ar, "invalid fw indication: %llx\n", type);
1302 static int ath10k_snoc_setup_resource(struct ath10k *ar)
1304 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
1305 struct ath10k_ce *ce = ath10k_ce_priv(ar);
1306 struct ath10k_snoc_pipe *pipe;
1309 timer_setup(&ar_snoc->rx_post_retry, ath10k_snoc_rx_replenish_retry, 0);
1310 spin_lock_init(&ce->ce_lock);
1311 for (i = 0; i < CE_COUNT; i++) {
1312 pipe = &ar_snoc->pipe_info[i];
1313 pipe->ce_hdl = &ce->ce_states[i];
1315 pipe->hif_ce_state = ar;
1317 ret = ath10k_ce_alloc_pipe(ar, i, &host_ce_config_wlan[i]);
1319 ath10k_err(ar, "failed to allocate copy engine pipe %d: %d\n",
1324 pipe->buf_sz = host_ce_config_wlan[i].src_sz_max;
1326 ath10k_snoc_init_napi(ar);
1331 static void ath10k_snoc_release_resource(struct ath10k *ar)
1335 netif_napi_del(&ar->napi);
1336 for (i = 0; i < CE_COUNT; i++)
1337 ath10k_ce_free_pipe(ar, i);
1340 static int ath10k_get_vreg_info(struct ath10k *ar, struct device *dev,
1341 struct ath10k_vreg_info *vreg_info)
1343 struct regulator *reg;
1346 reg = devm_regulator_get_optional(dev, vreg_info->name);
1351 if (ret == -EPROBE_DEFER) {
1352 ath10k_err(ar, "EPROBE_DEFER for regulator: %s\n",
1356 if (vreg_info->required) {
1357 ath10k_err(ar, "Regulator %s doesn't exist: %d\n",
1358 vreg_info->name, ret);
1361 ath10k_dbg(ar, ATH10K_DBG_SNOC,
1362 "Optional regulator %s doesn't exist: %d\n",
1363 vreg_info->name, ret);
1367 vreg_info->reg = reg;
1370 ath10k_dbg(ar, ATH10K_DBG_SNOC,
1371 "snog vreg %s min_v %u max_v %u load_ua %u settle_delay %lu\n",
1372 vreg_info->name, vreg_info->min_v, vreg_info->max_v,
1373 vreg_info->load_ua, vreg_info->settle_delay);
1378 static int ath10k_get_clk_info(struct ath10k *ar, struct device *dev,
1379 struct ath10k_clk_info *clk_info)
1384 handle = devm_clk_get(dev, clk_info->name);
1385 if (IS_ERR(handle)) {
1386 ret = PTR_ERR(handle);
1387 if (clk_info->required) {
1388 ath10k_err(ar, "snoc clock %s isn't available: %d\n",
1389 clk_info->name, ret);
1392 ath10k_dbg(ar, ATH10K_DBG_SNOC, "snoc ignoring clock %s: %d\n",
1398 ath10k_dbg(ar, ATH10K_DBG_SNOC, "snoc clock %s freq %u\n",
1399 clk_info->name, clk_info->freq);
1401 clk_info->handle = handle;
1406 static int __ath10k_snoc_vreg_on(struct ath10k *ar,
1407 struct ath10k_vreg_info *vreg_info)
1411 ath10k_dbg(ar, ATH10K_DBG_SNOC, "snoc regulator %s being enabled\n",
1414 ret = regulator_set_voltage(vreg_info->reg, vreg_info->min_v,
1418 "failed to set regulator %s voltage-min: %d voltage-max: %d\n",
1419 vreg_info->name, vreg_info->min_v, vreg_info->max_v);
1423 if (vreg_info->load_ua) {
1424 ret = regulator_set_load(vreg_info->reg, vreg_info->load_ua);
1426 ath10k_err(ar, "failed to set regulator %s load: %d\n",
1427 vreg_info->name, vreg_info->load_ua);
1432 ret = regulator_enable(vreg_info->reg);
1434 ath10k_err(ar, "failed to enable regulator %s\n",
1439 if (vreg_info->settle_delay)
1440 udelay(vreg_info->settle_delay);
1445 regulator_set_load(vreg_info->reg, 0);
1447 regulator_set_voltage(vreg_info->reg, 0, vreg_info->max_v);
1452 static int __ath10k_snoc_vreg_off(struct ath10k *ar,
1453 struct ath10k_vreg_info *vreg_info)
1457 ath10k_dbg(ar, ATH10K_DBG_SNOC, "snoc regulator %s being disabled\n",
1460 ret = regulator_disable(vreg_info->reg);
1462 ath10k_err(ar, "failed to disable regulator %s\n",
1465 ret = regulator_set_load(vreg_info->reg, 0);
1467 ath10k_err(ar, "failed to set load %s\n", vreg_info->name);
1469 ret = regulator_set_voltage(vreg_info->reg, 0, vreg_info->max_v);
1471 ath10k_err(ar, "failed to set voltage %s\n", vreg_info->name);
1476 static int ath10k_snoc_vreg_on(struct ath10k *ar)
1478 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
1479 struct ath10k_vreg_info *vreg_info;
1483 for (i = 0; i < ARRAY_SIZE(vreg_cfg); i++) {
1484 vreg_info = &ar_snoc->vreg[i];
1486 if (!vreg_info->reg)
1489 ret = __ath10k_snoc_vreg_on(ar, vreg_info);
1491 goto err_reg_config;
1497 for (i = i - 1; i >= 0; i--) {
1498 vreg_info = &ar_snoc->vreg[i];
1500 if (!vreg_info->reg)
1503 __ath10k_snoc_vreg_off(ar, vreg_info);
1509 static int ath10k_snoc_vreg_off(struct ath10k *ar)
1511 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
1512 struct ath10k_vreg_info *vreg_info;
1516 for (i = ARRAY_SIZE(vreg_cfg) - 1; i >= 0; i--) {
1517 vreg_info = &ar_snoc->vreg[i];
1519 if (!vreg_info->reg)
1522 ret = __ath10k_snoc_vreg_off(ar, vreg_info);
1528 static int ath10k_snoc_clk_init(struct ath10k *ar)
1530 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
1531 struct ath10k_clk_info *clk_info;
1535 for (i = 0; i < ARRAY_SIZE(clk_cfg); i++) {
1536 clk_info = &ar_snoc->clk[i];
1538 if (!clk_info->handle)
1541 ath10k_dbg(ar, ATH10K_DBG_SNOC, "snoc clock %s being enabled\n",
1544 if (clk_info->freq) {
1545 ret = clk_set_rate(clk_info->handle, clk_info->freq);
1548 ath10k_err(ar, "failed to set clock %s freq %u\n",
1549 clk_info->name, clk_info->freq);
1550 goto err_clock_config;
1554 ret = clk_prepare_enable(clk_info->handle);
1556 ath10k_err(ar, "failed to enable clock %s\n",
1558 goto err_clock_config;
1565 for (i = i - 1; i >= 0; i--) {
1566 clk_info = &ar_snoc->clk[i];
1568 if (!clk_info->handle)
1571 clk_disable_unprepare(clk_info->handle);
1577 static int ath10k_snoc_clk_deinit(struct ath10k *ar)
1579 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
1580 struct ath10k_clk_info *clk_info;
1583 for (i = 0; i < ARRAY_SIZE(clk_cfg); i++) {
1584 clk_info = &ar_snoc->clk[i];
1586 if (!clk_info->handle)
1589 ath10k_dbg(ar, ATH10K_DBG_SNOC, "snoc clock %s being disabled\n",
1592 clk_disable_unprepare(clk_info->handle);
1598 static int ath10k_hw_power_on(struct ath10k *ar)
1602 ath10k_dbg(ar, ATH10K_DBG_SNOC, "soc power on\n");
1604 ret = ath10k_snoc_vreg_on(ar);
1608 ret = ath10k_snoc_clk_init(ar);
1615 ath10k_snoc_vreg_off(ar);
1619 static int ath10k_hw_power_off(struct ath10k *ar)
1623 ath10k_dbg(ar, ATH10K_DBG_SNOC, "soc power off\n");
1625 ath10k_snoc_clk_deinit(ar);
1627 ret = ath10k_snoc_vreg_off(ar);
1632 static const struct of_device_id ath10k_snoc_dt_match[] = {
1633 { .compatible = "qcom,wcn3990-wifi",
1638 MODULE_DEVICE_TABLE(of, ath10k_snoc_dt_match);
1640 static int ath10k_snoc_probe(struct platform_device *pdev)
1642 const struct ath10k_snoc_drv_priv *drv_data;
1643 const struct of_device_id *of_id;
1644 struct ath10k_snoc *ar_snoc;
1651 of_id = of_match_device(ath10k_snoc_dt_match, &pdev->dev);
1653 dev_err(&pdev->dev, "failed to find matching device tree id\n");
1657 drv_data = of_id->data;
1660 ret = dma_set_mask_and_coherent(dev, drv_data->dma_mask);
1662 dev_err(dev, "failed to set dma mask: %d", ret);
1666 ar = ath10k_core_create(sizeof(*ar_snoc), dev, ATH10K_BUS_SNOC,
1667 drv_data->hw_rev, &ath10k_snoc_hif_ops);
1669 dev_err(dev, "failed to allocate core\n");
1673 ar_snoc = ath10k_snoc_priv(ar);
1674 ar_snoc->dev = pdev;
1675 platform_set_drvdata(pdev, ar);
1677 ar_snoc->ce.bus_ops = &ath10k_snoc_bus_ops;
1678 ar->ce_priv = &ar_snoc->ce;
1679 msa_size = drv_data->msa_size;
1681 ret = ath10k_snoc_resource_init(ar);
1683 ath10k_warn(ar, "failed to initialize resource: %d\n", ret);
1684 goto err_core_destroy;
1687 ret = ath10k_snoc_setup_resource(ar);
1689 ath10k_warn(ar, "failed to setup resource: %d\n", ret);
1690 goto err_core_destroy;
1692 ret = ath10k_snoc_request_irq(ar);
1694 ath10k_warn(ar, "failed to request irqs: %d\n", ret);
1695 goto err_release_resource;
1698 ar_snoc->vreg = vreg_cfg;
1699 for (i = 0; i < ARRAY_SIZE(vreg_cfg); i++) {
1700 ret = ath10k_get_vreg_info(ar, dev, &ar_snoc->vreg[i]);
1705 ar_snoc->clk = clk_cfg;
1706 for (i = 0; i < ARRAY_SIZE(clk_cfg); i++) {
1707 ret = ath10k_get_clk_info(ar, dev, &ar_snoc->clk[i]);
1712 ret = ath10k_hw_power_on(ar);
1714 ath10k_err(ar, "failed to power on device: %d\n", ret);
1718 ret = ath10k_qmi_init(ar, msa_size);
1720 ath10k_warn(ar, "failed to register wlfw qmi client: %d\n", ret);
1721 goto err_core_destroy;
1724 ath10k_dbg(ar, ATH10K_DBG_SNOC, "snoc probe\n");
1729 ath10k_snoc_free_irq(ar);
1731 err_release_resource:
1732 ath10k_snoc_release_resource(ar);
1735 ath10k_core_destroy(ar);
1740 static int ath10k_snoc_remove(struct platform_device *pdev)
1742 struct ath10k *ar = platform_get_drvdata(pdev);
1743 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
1745 ath10k_dbg(ar, ATH10K_DBG_SNOC, "snoc remove\n");
1747 reinit_completion(&ar->driver_recovery);
1749 if (test_bit(ATH10K_SNOC_FLAG_RECOVERY, &ar_snoc->flags))
1750 wait_for_completion_timeout(&ar->driver_recovery, 3 * HZ);
1752 set_bit(ATH10K_SNOC_FLAG_UNREGISTERING, &ar_snoc->flags);
1754 ath10k_core_unregister(ar);
1755 ath10k_hw_power_off(ar);
1756 ath10k_snoc_free_irq(ar);
1757 ath10k_snoc_release_resource(ar);
1758 ath10k_qmi_deinit(ar);
1759 ath10k_core_destroy(ar);
1764 static struct platform_driver ath10k_snoc_driver = {
1765 .probe = ath10k_snoc_probe,
1766 .remove = ath10k_snoc_remove,
1768 .name = "ath10k_snoc",
1769 .of_match_table = ath10k_snoc_dt_match,
1772 module_platform_driver(ath10k_snoc_driver);
1774 MODULE_AUTHOR("Qualcomm");
1775 MODULE_LICENSE("Dual BSD/GPL");
1776 MODULE_DESCRIPTION("Driver support for Atheros WCN3990 SNOC devices");