1 /******************************************************************************
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
8 * Copyright(c) 2007 - 2014 Intel Corporation. All rights reserved.
9 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
10 * Copyright(c) 2016 - 2017 Intel Deutschland GmbH
11 * Copyright (C) 2018 Intel Corporation
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of version 2 of the GNU General Public License as
15 * published by the Free Software Foundation.
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19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
22 * The full GNU General Public License is included in this distribution
23 * in the file called COPYING.
25 * Contact Information:
26 * Intel Linux Wireless <linuxwifi@intel.com>
27 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
31 * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved.
32 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
33 * Copyright(c) 2016 - 2017 Intel Deutschland GmbH
34 * Copyright (C) 2018 Intel Corporation
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38 * modification, are permitted provided that the following conditions
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63 *****************************************************************************/
64 #ifndef __iwl_fw_api_debug_h__
65 #define __iwl_fw_api_debug_h__
68 * enum iwl_debug_cmds - debug commands
73 * LMAC memory read/write, using &struct iwl_dbg_mem_access_cmd and
74 * &struct iwl_dbg_mem_access_rsp
79 * UMAC memory read/write, using &struct iwl_dbg_mem_access_cmd and
80 * &struct iwl_dbg_mem_access_rsp
84 * @MFU_ASSERT_DUMP_NTF:
85 * &struct iwl_mfu_assert_dump_notif
87 MFU_ASSERT_DUMP_NTF = 0xFE,
90 /* Error response/notification */
92 FW_ERR_UNKNOWN_CMD = 0x0,
93 FW_ERR_INVALID_CMD_PARAM = 0x1,
95 FW_ERR_ARC_MEMORY = 0x3,
96 FW_ERR_ARC_CODE = 0x4,
97 FW_ERR_WATCH_DOG = 0x5,
98 FW_ERR_WEP_GRP_KEY_INDX = 0x10,
99 FW_ERR_WEP_KEY_SIZE = 0x11,
100 FW_ERR_OBSOLETE_FUNC = 0x12,
101 FW_ERR_UNEXPECTED = 0xFE,
106 * struct iwl_error_resp - FW error indication
107 * ( REPLY_ERROR = 0x2 )
108 * @error_type: one of FW_ERR_*
109 * @cmd_id: the command ID for which the error occurred
110 * @reserved1: reserved
111 * @bad_cmd_seq_num: sequence number of the erroneous command
112 * @error_service: which service created the error, applicable only if
113 * error_type = 2, otherwise 0
114 * @timestamp: TSF in usecs.
116 struct iwl_error_resp {
120 __le16 bad_cmd_seq_num;
121 __le32 error_service;
125 #define TX_FIFO_MAX_NUM_9000 8
126 #define TX_FIFO_MAX_NUM 15
127 #define RX_FIFO_MAX_NUM 2
128 #define TX_FIFO_INTERNAL_MAX_NUM 6
131 * struct iwl_shared_mem_cfg_v2 - Shared memory configuration information
133 * @shared_mem_addr: shared memory addr (pre 8000 HW set to 0x0 as MARBH is not
135 * @shared_mem_size: shared memory size
136 * @sample_buff_addr: internal sample (mon/adc) buff addr (pre 8000 HW set to
137 * 0x0 as accessible only via DBGM RDAT)
138 * @sample_buff_size: internal sample buff size
139 * @txfifo_addr: start addr of TXF0 (excluding the context table 0.5KB), (pre
140 * 8000 HW set to 0x0 as not accessible)
141 * @txfifo_size: size of TXF0 ... TXF7
142 * @rxfifo_size: RXF1, RXF2 sizes. If there is no RXF2, it'll have a value of 0
143 * @page_buff_addr: used by UMAC and performance debug (page miss analysis),
144 * when paging is not supported this should be 0
145 * @page_buff_size: size of %page_buff_addr
146 * @rxfifo_addr: Start address of rxFifo
147 * @internal_txfifo_addr: start address of internalFifo
148 * @internal_txfifo_size: internal fifos' size
150 * NOTE: on firmware that don't have IWL_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG
151 * set, the last 3 members don't exist.
153 struct iwl_shared_mem_cfg_v2 {
154 __le32 shared_mem_addr;
155 __le32 shared_mem_size;
156 __le32 sample_buff_addr;
157 __le32 sample_buff_size;
159 __le32 txfifo_size[TX_FIFO_MAX_NUM_9000];
160 __le32 rxfifo_size[RX_FIFO_MAX_NUM];
161 __le32 page_buff_addr;
162 __le32 page_buff_size;
164 __le32 internal_txfifo_addr;
165 __le32 internal_txfifo_size[TX_FIFO_INTERNAL_MAX_NUM];
166 } __packed; /* SHARED_MEM_ALLOC_API_S_VER_2 */
169 * struct iwl_shared_mem_lmac_cfg - LMAC shared memory configuration
171 * @txfifo_addr: start addr of TXF0 (excluding the context table 0.5KB)
172 * @txfifo_size: size of TX FIFOs
173 * @rxfifo1_addr: RXF1 addr
174 * @rxfifo1_size: RXF1 size
176 struct iwl_shared_mem_lmac_cfg {
178 __le32 txfifo_size[TX_FIFO_MAX_NUM];
182 } __packed; /* SHARED_MEM_ALLOC_LMAC_API_S_VER_1 */
185 * struct iwl_shared_mem_cfg - Shared memory configuration information
187 * @shared_mem_addr: shared memory address
188 * @shared_mem_size: shared memory size
189 * @sample_buff_addr: internal sample (mon/adc) buff addr
190 * @sample_buff_size: internal sample buff size
191 * @rxfifo2_addr: start addr of RXF2
192 * @rxfifo2_size: size of RXF2
193 * @page_buff_addr: used by UMAC and performance debug (page miss analysis),
194 * when paging is not supported this should be 0
195 * @page_buff_size: size of %page_buff_addr
196 * @lmac_num: number of LMACs (1 or 2)
197 * @lmac_smem: per - LMAC smem data
199 struct iwl_shared_mem_cfg {
200 __le32 shared_mem_addr;
201 __le32 shared_mem_size;
202 __le32 sample_buff_addr;
203 __le32 sample_buff_size;
206 __le32 page_buff_addr;
207 __le32 page_buff_size;
209 struct iwl_shared_mem_lmac_cfg lmac_smem[2];
210 } __packed; /* SHARED_MEM_ALLOC_API_S_VER_3 */
213 * struct iwl_mfuart_load_notif - mfuart image version & status
214 * ( MFUART_LOAD_NOTIFICATION = 0xb1 )
215 * @installed_ver: installed image version
216 * @external_ver: external image version
217 * @status: MFUART loading status
218 * @duration: MFUART loading time
219 * @image_size: MFUART image size in bytes
221 struct iwl_mfuart_load_notif {
222 __le32 installed_ver;
226 /* image size valid only in v2 of the command */
228 } __packed; /* MFU_LOADER_NTFY_API_S_VER_2 */
231 * struct iwl_mfu_assert_dump_notif - mfuart dump logs
232 * ( MFU_ASSERT_DUMP_NTF = 0xfe )
233 * @assert_id: mfuart assert id that cause the notif
234 * @curr_reset_num: number of asserts since uptime
235 * @index_num: current chunk id
236 * @parts_num: total number of chunks
237 * @data_size: number of data bytes sent
240 struct iwl_mfu_assert_dump_notif {
242 __le32 curr_reset_num;
247 } __packed; /* MFU_DUMP_ASSERT_API_S_VER_1 */
250 * enum iwl_mvm_marker_id - marker ids
252 * The ids for different type of markers to insert into the usniffer logs
254 * @MARKER_ID_TX_FRAME_LATENCY: TX latency marker
255 * @MARKER_ID_SYNC_CLOCK: sync FW time and systime
257 enum iwl_mvm_marker_id {
258 MARKER_ID_TX_FRAME_LATENCY = 1,
259 MARKER_ID_SYNC_CLOCK = 2,
260 }; /* MARKER_ID_API_E_VER_2 */
263 * struct iwl_mvm_marker - mark info into the usniffer logs
265 * (MARKER_CMD = 0xcb)
267 * Mark the UTC time stamp into the usniffer logs together with additional
268 * metadata, so the usniffer output can be parsed.
269 * In the command response the ucode will return the GP2 time.
271 * @dw_len: The amount of dwords following this byte including this byte.
272 * @marker_id: A unique marker id (iwl_mvm_marker_id).
273 * @reserved: reserved.
274 * @timestamp: in milliseconds since 1970-01-01 00:00:00 UTC
275 * @metadata: additional meta data that will be written to the unsiffer log
277 struct iwl_mvm_marker {
283 } __packed; /* MARKER_API_S_VER_1 */
286 * struct iwl_mvm_marker_rsp - Response to marker cmd
288 * @gp2: The gp2 clock value in the FW
290 struct iwl_mvm_marker_rsp {
294 /* Operation types for the debug mem access */
296 DEBUG_MEM_OP_READ = 0,
297 DEBUG_MEM_OP_WRITE = 1,
298 DEBUG_MEM_OP_WRITE_BYTES = 2,
301 #define DEBUG_MEM_MAX_SIZE_DWORDS 32
304 * struct iwl_dbg_mem_access_cmd - Request the device to read/write memory
305 * @op: DEBUG_MEM_OP_*
306 * @addr: address to read/write from/to
307 * @len: in dwords, to read/write
308 * @data: for write opeations, contains the source buffer
310 struct iwl_dbg_mem_access_cmd {
315 } __packed; /* DEBUG_(U|L)MAC_RD_WR_CMD_API_S_VER_1 */
317 /* Status responses for the debug mem access */
319 DEBUG_MEM_STATUS_SUCCESS = 0x0,
320 DEBUG_MEM_STATUS_FAILED = 0x1,
321 DEBUG_MEM_STATUS_LOCKED = 0x2,
322 DEBUG_MEM_STATUS_HIDDEN = 0x3,
323 DEBUG_MEM_STATUS_LENGTH = 0x4,
327 * struct iwl_dbg_mem_access_rsp - Response to debug mem commands
328 * @status: DEBUG_MEM_STATUS_*
329 * @len: read dwords (0 for write operations)
330 * @data: contains the read DWs
332 struct iwl_dbg_mem_access_rsp {
336 } __packed; /* DEBUG_(U|L)MAC_RD_WR_RSP_API_S_VER_1 */
338 #define CONT_REC_COMMAND_SIZE 80
339 #define ENABLE_CONT_RECORDING 0x15
340 #define DISABLE_CONT_RECORDING 0x16
341 #define BUFFER_ALLOCATION 0x27
342 #define START_DEBUG_RECORDING 0x29
343 #define STOP_DEBUG_RECORDING 0x2A
346 * struct iwl_continuous_record_mode - recording mode
348 struct iwl_continuous_record_mode {
349 __le16 enable_recording;
353 * struct iwl_continuous_record_cmd - enable/disable continuous recording
355 struct iwl_continuous_record_cmd {
356 struct iwl_continuous_record_mode record_mode;
357 u8 pad[CONT_REC_COMMAND_SIZE -
358 sizeof(struct iwl_continuous_record_mode)];
361 /* maximum fragments to be allocated per target of allocationId */
362 #define IWL_BUFFER_LOCATION_MAX_FRAGS 2
365 * struct iwl_fragment_data single fragment structure
366 * @address: 64bit start address
367 * @size: size in bytes
369 struct iwl_fragment_data {
372 } __packed; /* FRAGMENT_STRUCTURE_API_S_VER_1 */
375 * struct iwl_buffer_allocation_cmd - buffer allocation command structure
376 * @allocation_id: id of the allocation
377 * @buffer_location: location of the buffer
378 * @num_frags: number of fragments
379 * @fragments: memory fragments
381 struct iwl_buffer_allocation_cmd {
382 __le32 allocation_id;
383 __le32 buffer_location;
385 struct iwl_fragment_data fragments[IWL_BUFFER_LOCATION_MAX_FRAGS];
386 } __packed; /* BUFFER_ALLOCATION_CMD_API_S_VER_1 */
388 #endif /* __iwl_fw_api_debug_h__ */