1 /******************************************************************************
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
8 * Copyright(c) 2008 - 2014 Intel Corporation. All rights reserved.
9 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
10 * Copyright(c) 2015 - 2017 Intel Deutschland GmbH
11 * Copyright(c) 2018 Intel Corporation
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of version 2 of the GNU General Public License as
15 * published by the Free Software Foundation.
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
22 * The full GNU General Public License is included in this distribution
23 * in the file called COPYING.
25 * Contact Information:
26 * Intel Linux Wireless <linuxwifi@intel.com>
27 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
31 * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved.
32 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
33 * Copyright(c) 2015 - 2017 Intel Deutschland GmbH
34 * Copyright(c) 2018 Intel Corporation
35 * All rights reserved.
37 * Redistribution and use in source and binary forms, with or without
38 * modification, are permitted provided that the following conditions
41 * * Redistributions of source code must retain the above copyright
42 * notice, this list of conditions and the following disclaimer.
43 * * Redistributions in binary form must reproduce the above copyright
44 * notice, this list of conditions and the following disclaimer in
45 * the documentation and/or other materials provided with the
47 * * Neither the name Intel Corporation nor the names of its
48 * contributors may be used to endorse or promote products derived
49 * from this software without specific prior written permission.
51 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
52 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
53 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
54 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
55 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
56 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
57 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
58 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
59 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
60 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
61 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
63 *****************************************************************************/
64 #include <linux/devcoredump.h>
74 * struct iwl_fw_dump_ptrs - set of pointers needed for the fw-error-dump
76 * @fwrt_ptr: pointer to the buffer coming from fwrt
77 * @trans_ptr: pointer to struct %iwl_trans_dump_data which contains the
79 * @trans_len: length of the valid data in trans_ptr
80 * @fwrt_len: length of the valid data in fwrt_ptr
82 struct iwl_fw_dump_ptrs {
83 struct iwl_trans_dump_data *trans_ptr;
88 #define RADIO_REG_MAX_READ 0x2ad
89 static void iwl_read_radio_regs(struct iwl_fw_runtime *fwrt,
90 struct iwl_fw_error_dump_data **dump_data)
92 u8 *pos = (void *)(*dump_data)->data;
96 IWL_DEBUG_INFO(fwrt, "WRT radio registers dump\n");
98 if (!iwl_trans_grab_nic_access(fwrt->trans, &flags))
101 (*dump_data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RADIO_REG);
102 (*dump_data)->len = cpu_to_le32(RADIO_REG_MAX_READ);
104 for (i = 0; i < RADIO_REG_MAX_READ; i++) {
105 u32 rd_cmd = RADIO_RSP_RD_CMD;
107 rd_cmd |= i << RADIO_RSP_ADDR_POS;
108 iwl_write_prph_no_grab(fwrt->trans, RSP_RADIO_CMD, rd_cmd);
109 *pos = (u8)iwl_read_prph_no_grab(fwrt->trans, RSP_RADIO_RDDAT);
114 *dump_data = iwl_fw_error_next_data(*dump_data);
116 iwl_trans_release_nic_access(fwrt->trans, &flags);
119 static void iwl_fwrt_dump_rxf(struct iwl_fw_runtime *fwrt,
120 struct iwl_fw_error_dump_data **dump_data,
121 int size, u32 offset, int fifo_num)
123 struct iwl_fw_error_dump_fifo *fifo_hdr;
128 fifo_hdr = (void *)(*dump_data)->data;
129 fifo_data = (void *)fifo_hdr->data;
132 /* No need to try to read the data if the length is 0 */
136 /* Add a TLV for the RXF */
137 (*dump_data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RXF);
138 (*dump_data)->len = cpu_to_le32(fifo_len + sizeof(*fifo_hdr));
140 fifo_hdr->fifo_num = cpu_to_le32(fifo_num);
141 fifo_hdr->available_bytes =
142 cpu_to_le32(iwl_trans_read_prph(fwrt->trans,
143 RXF_RD_D_SPACE + offset));
145 cpu_to_le32(iwl_trans_read_prph(fwrt->trans,
146 RXF_RD_WR_PTR + offset));
148 cpu_to_le32(iwl_trans_read_prph(fwrt->trans,
149 RXF_RD_RD_PTR + offset));
150 fifo_hdr->fence_ptr =
151 cpu_to_le32(iwl_trans_read_prph(fwrt->trans,
152 RXF_RD_FENCE_PTR + offset));
153 fifo_hdr->fence_mode =
154 cpu_to_le32(iwl_trans_read_prph(fwrt->trans,
155 RXF_SET_FENCE_MODE + offset));
158 iwl_trans_write_prph(fwrt->trans, RXF_SET_FENCE_MODE + offset, 0x1);
159 /* Set fence pointer to the same place like WR pointer */
160 iwl_trans_write_prph(fwrt->trans, RXF_LD_WR2FENCE + offset, 0x1);
161 /* Set fence offset */
162 iwl_trans_write_prph(fwrt->trans,
163 RXF_LD_FENCE_OFFSET_ADDR + offset, 0x0);
166 fifo_len /= sizeof(u32); /* Size in DWORDS */
167 for (i = 0; i < fifo_len; i++)
168 fifo_data[i] = iwl_trans_read_prph(fwrt->trans,
169 RXF_FIFO_RD_FENCE_INC +
171 *dump_data = iwl_fw_error_next_data(*dump_data);
174 static void iwl_fwrt_dump_txf(struct iwl_fw_runtime *fwrt,
175 struct iwl_fw_error_dump_data **dump_data,
176 int size, u32 offset, int fifo_num)
178 struct iwl_fw_error_dump_fifo *fifo_hdr;
183 fifo_hdr = (void *)(*dump_data)->data;
184 fifo_data = (void *)fifo_hdr->data;
187 /* No need to try to read the data if the length is 0 */
191 /* Add a TLV for the FIFO */
192 (*dump_data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_TXF);
193 (*dump_data)->len = cpu_to_le32(fifo_len + sizeof(*fifo_hdr));
195 fifo_hdr->fifo_num = cpu_to_le32(fifo_num);
196 fifo_hdr->available_bytes =
197 cpu_to_le32(iwl_trans_read_prph(fwrt->trans,
198 TXF_FIFO_ITEM_CNT + offset));
200 cpu_to_le32(iwl_trans_read_prph(fwrt->trans,
201 TXF_WR_PTR + offset));
203 cpu_to_le32(iwl_trans_read_prph(fwrt->trans,
204 TXF_RD_PTR + offset));
205 fifo_hdr->fence_ptr =
206 cpu_to_le32(iwl_trans_read_prph(fwrt->trans,
207 TXF_FENCE_PTR + offset));
208 fifo_hdr->fence_mode =
209 cpu_to_le32(iwl_trans_read_prph(fwrt->trans,
210 TXF_LOCK_FENCE + offset));
212 /* Set the TXF_READ_MODIFY_ADDR to TXF_WR_PTR */
213 iwl_trans_write_prph(fwrt->trans, TXF_READ_MODIFY_ADDR + offset,
214 TXF_WR_PTR + offset);
216 /* Dummy-read to advance the read pointer to the head */
217 iwl_trans_read_prph(fwrt->trans, TXF_READ_MODIFY_DATA + offset);
220 fifo_len /= sizeof(u32); /* Size in DWORDS */
221 for (i = 0; i < fifo_len; i++)
222 fifo_data[i] = iwl_trans_read_prph(fwrt->trans,
223 TXF_READ_MODIFY_DATA +
225 *dump_data = iwl_fw_error_next_data(*dump_data);
228 static void iwl_fw_dump_fifos(struct iwl_fw_runtime *fwrt,
229 struct iwl_fw_error_dump_data **dump_data)
231 struct iwl_fw_error_dump_fifo *fifo_hdr;
232 struct iwl_fwrt_shared_mem_cfg *cfg = &fwrt->smem_cfg;
238 IWL_DEBUG_INFO(fwrt, "WRT FIFO dump\n");
240 if (!iwl_trans_grab_nic_access(fwrt->trans, &flags))
243 if (fwrt->fw->dbg.dump_mask & BIT(IWL_FW_ERROR_DUMP_RXF)) {
245 iwl_fwrt_dump_rxf(fwrt, dump_data,
246 cfg->lmac[0].rxfifo1_size, 0, 0);
248 iwl_fwrt_dump_rxf(fwrt, dump_data, cfg->rxfifo2_size,
249 RXF_DIFF_FROM_PREV, 1);
250 /* Pull LMAC2 RXF1 */
251 if (fwrt->smem_cfg.num_lmacs > 1)
252 iwl_fwrt_dump_rxf(fwrt, dump_data,
253 cfg->lmac[1].rxfifo1_size,
254 LMAC2_PRPH_OFFSET, 2);
257 if (fwrt->fw->dbg.dump_mask & BIT(IWL_FW_ERROR_DUMP_TXF)) {
258 /* Pull TXF data from LMAC1 */
259 for (i = 0; i < fwrt->smem_cfg.num_txfifo_entries; i++) {
260 /* Mark the number of TXF we're pulling now */
261 iwl_trans_write_prph(fwrt->trans, TXF_LARC_NUM, i);
262 iwl_fwrt_dump_txf(fwrt, dump_data,
263 cfg->lmac[0].txfifo_size[i], 0, i);
266 /* Pull TXF data from LMAC2 */
267 if (fwrt->smem_cfg.num_lmacs > 1) {
268 for (i = 0; i < fwrt->smem_cfg.num_txfifo_entries;
270 /* Mark the number of TXF we're pulling now */
271 iwl_trans_write_prph(fwrt->trans,
273 LMAC2_PRPH_OFFSET, i);
274 iwl_fwrt_dump_txf(fwrt, dump_data,
275 cfg->lmac[1].txfifo_size[i],
277 i + cfg->num_txfifo_entries);
282 if (fwrt->fw->dbg.dump_mask & BIT(IWL_FW_ERROR_DUMP_INTERNAL_TXF) &&
283 fw_has_capa(&fwrt->fw->ucode_capa,
284 IWL_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG)) {
285 /* Pull UMAC internal TXF data from all TXFs */
287 i < ARRAY_SIZE(fwrt->smem_cfg.internal_txfifo_size);
289 fifo_hdr = (void *)(*dump_data)->data;
290 fifo_data = (void *)fifo_hdr->data;
291 fifo_len = fwrt->smem_cfg.internal_txfifo_size[i];
293 /* No need to try to read the data if the length is 0 */
297 /* Add a TLV for the internal FIFOs */
299 cpu_to_le32(IWL_FW_ERROR_DUMP_INTERNAL_TXF);
301 cpu_to_le32(fifo_len + sizeof(*fifo_hdr));
303 fifo_hdr->fifo_num = cpu_to_le32(i);
305 /* Mark the number of TXF we're pulling now */
306 iwl_trans_write_prph(fwrt->trans, TXF_CPU2_NUM, i +
307 fwrt->smem_cfg.num_txfifo_entries);
309 fifo_hdr->available_bytes =
310 cpu_to_le32(iwl_trans_read_prph(fwrt->trans,
311 TXF_CPU2_FIFO_ITEM_CNT));
313 cpu_to_le32(iwl_trans_read_prph(fwrt->trans,
316 cpu_to_le32(iwl_trans_read_prph(fwrt->trans,
318 fifo_hdr->fence_ptr =
319 cpu_to_le32(iwl_trans_read_prph(fwrt->trans,
320 TXF_CPU2_FENCE_PTR));
321 fifo_hdr->fence_mode =
322 cpu_to_le32(iwl_trans_read_prph(fwrt->trans,
323 TXF_CPU2_LOCK_FENCE));
325 /* Set TXF_CPU2_READ_MODIFY_ADDR to TXF_CPU2_WR_PTR */
326 iwl_trans_write_prph(fwrt->trans,
327 TXF_CPU2_READ_MODIFY_ADDR,
330 /* Dummy-read to advance the read pointer to head */
331 iwl_trans_read_prph(fwrt->trans,
332 TXF_CPU2_READ_MODIFY_DATA);
335 fifo_len /= sizeof(u32); /* Size in DWORDS */
336 for (j = 0; j < fifo_len; j++)
338 iwl_trans_read_prph(fwrt->trans,
339 TXF_CPU2_READ_MODIFY_DATA);
340 *dump_data = iwl_fw_error_next_data(*dump_data);
344 iwl_trans_release_nic_access(fwrt->trans, &flags);
347 #define IWL8260_ICCM_OFFSET 0x44000 /* Only for B-step */
348 #define IWL8260_ICCM_LEN 0xC000 /* Only for B-step */
350 struct iwl_prph_range {
354 static const struct iwl_prph_range iwl_prph_dump_addr_comm[] = {
355 { .start = 0x00a00000, .end = 0x00a00000 },
356 { .start = 0x00a0000c, .end = 0x00a00024 },
357 { .start = 0x00a0002c, .end = 0x00a0003c },
358 { .start = 0x00a00410, .end = 0x00a00418 },
359 { .start = 0x00a00420, .end = 0x00a00420 },
360 { .start = 0x00a00428, .end = 0x00a00428 },
361 { .start = 0x00a00430, .end = 0x00a0043c },
362 { .start = 0x00a00444, .end = 0x00a00444 },
363 { .start = 0x00a004c0, .end = 0x00a004cc },
364 { .start = 0x00a004d8, .end = 0x00a004d8 },
365 { .start = 0x00a004e0, .end = 0x00a004f0 },
366 { .start = 0x00a00840, .end = 0x00a00840 },
367 { .start = 0x00a00850, .end = 0x00a00858 },
368 { .start = 0x00a01004, .end = 0x00a01008 },
369 { .start = 0x00a01010, .end = 0x00a01010 },
370 { .start = 0x00a01018, .end = 0x00a01018 },
371 { .start = 0x00a01024, .end = 0x00a01024 },
372 { .start = 0x00a0102c, .end = 0x00a01034 },
373 { .start = 0x00a0103c, .end = 0x00a01040 },
374 { .start = 0x00a01048, .end = 0x00a01094 },
375 { .start = 0x00a01c00, .end = 0x00a01c20 },
376 { .start = 0x00a01c58, .end = 0x00a01c58 },
377 { .start = 0x00a01c7c, .end = 0x00a01c7c },
378 { .start = 0x00a01c28, .end = 0x00a01c54 },
379 { .start = 0x00a01c5c, .end = 0x00a01c5c },
380 { .start = 0x00a01c60, .end = 0x00a01cdc },
381 { .start = 0x00a01ce0, .end = 0x00a01d0c },
382 { .start = 0x00a01d18, .end = 0x00a01d20 },
383 { .start = 0x00a01d2c, .end = 0x00a01d30 },
384 { .start = 0x00a01d40, .end = 0x00a01d5c },
385 { .start = 0x00a01d80, .end = 0x00a01d80 },
386 { .start = 0x00a01d98, .end = 0x00a01d9c },
387 { .start = 0x00a01da8, .end = 0x00a01da8 },
388 { .start = 0x00a01db8, .end = 0x00a01df4 },
389 { .start = 0x00a01dc0, .end = 0x00a01dfc },
390 { .start = 0x00a01e00, .end = 0x00a01e2c },
391 { .start = 0x00a01e40, .end = 0x00a01e60 },
392 { .start = 0x00a01e68, .end = 0x00a01e6c },
393 { .start = 0x00a01e74, .end = 0x00a01e74 },
394 { .start = 0x00a01e84, .end = 0x00a01e90 },
395 { .start = 0x00a01e9c, .end = 0x00a01ec4 },
396 { .start = 0x00a01ed0, .end = 0x00a01ee0 },
397 { .start = 0x00a01f00, .end = 0x00a01f1c },
398 { .start = 0x00a01f44, .end = 0x00a01ffc },
399 { .start = 0x00a02000, .end = 0x00a02048 },
400 { .start = 0x00a02068, .end = 0x00a020f0 },
401 { .start = 0x00a02100, .end = 0x00a02118 },
402 { .start = 0x00a02140, .end = 0x00a0214c },
403 { .start = 0x00a02168, .end = 0x00a0218c },
404 { .start = 0x00a021c0, .end = 0x00a021c0 },
405 { .start = 0x00a02400, .end = 0x00a02410 },
406 { .start = 0x00a02418, .end = 0x00a02420 },
407 { .start = 0x00a02428, .end = 0x00a0242c },
408 { .start = 0x00a02434, .end = 0x00a02434 },
409 { .start = 0x00a02440, .end = 0x00a02460 },
410 { .start = 0x00a02468, .end = 0x00a024b0 },
411 { .start = 0x00a024c8, .end = 0x00a024cc },
412 { .start = 0x00a02500, .end = 0x00a02504 },
413 { .start = 0x00a0250c, .end = 0x00a02510 },
414 { .start = 0x00a02540, .end = 0x00a02554 },
415 { .start = 0x00a02580, .end = 0x00a025f4 },
416 { .start = 0x00a02600, .end = 0x00a0260c },
417 { .start = 0x00a02648, .end = 0x00a02650 },
418 { .start = 0x00a02680, .end = 0x00a02680 },
419 { .start = 0x00a026c0, .end = 0x00a026d0 },
420 { .start = 0x00a02700, .end = 0x00a0270c },
421 { .start = 0x00a02804, .end = 0x00a02804 },
422 { .start = 0x00a02818, .end = 0x00a0281c },
423 { .start = 0x00a02c00, .end = 0x00a02db4 },
424 { .start = 0x00a02df4, .end = 0x00a02fb0 },
425 { .start = 0x00a03000, .end = 0x00a03014 },
426 { .start = 0x00a0301c, .end = 0x00a0302c },
427 { .start = 0x00a03034, .end = 0x00a03038 },
428 { .start = 0x00a03040, .end = 0x00a03048 },
429 { .start = 0x00a03060, .end = 0x00a03068 },
430 { .start = 0x00a03070, .end = 0x00a03074 },
431 { .start = 0x00a0307c, .end = 0x00a0307c },
432 { .start = 0x00a03080, .end = 0x00a03084 },
433 { .start = 0x00a0308c, .end = 0x00a03090 },
434 { .start = 0x00a03098, .end = 0x00a03098 },
435 { .start = 0x00a030a0, .end = 0x00a030a0 },
436 { .start = 0x00a030a8, .end = 0x00a030b4 },
437 { .start = 0x00a030bc, .end = 0x00a030bc },
438 { .start = 0x00a030c0, .end = 0x00a0312c },
439 { .start = 0x00a03c00, .end = 0x00a03c5c },
440 { .start = 0x00a04400, .end = 0x00a04454 },
441 { .start = 0x00a04460, .end = 0x00a04474 },
442 { .start = 0x00a044c0, .end = 0x00a044ec },
443 { .start = 0x00a04500, .end = 0x00a04504 },
444 { .start = 0x00a04510, .end = 0x00a04538 },
445 { .start = 0x00a04540, .end = 0x00a04548 },
446 { .start = 0x00a04560, .end = 0x00a0457c },
447 { .start = 0x00a04590, .end = 0x00a04598 },
448 { .start = 0x00a045c0, .end = 0x00a045f4 },
451 static const struct iwl_prph_range iwl_prph_dump_addr_9000[] = {
452 { .start = 0x00a05c00, .end = 0x00a05c18 },
453 { .start = 0x00a05400, .end = 0x00a056e8 },
454 { .start = 0x00a08000, .end = 0x00a098bc },
455 { .start = 0x00a02400, .end = 0x00a02758 },
458 static void iwl_read_prph_block(struct iwl_trans *trans, u32 start,
459 u32 len_bytes, __le32 *data)
463 for (i = 0; i < len_bytes; i += 4)
464 *data++ = cpu_to_le32(iwl_read_prph_no_grab(trans, start + i));
467 static void iwl_dump_prph(struct iwl_trans *trans,
468 struct iwl_fw_error_dump_data **data,
469 const struct iwl_prph_range *iwl_prph_dump_addr,
472 struct iwl_fw_error_dump_prph *prph;
476 IWL_DEBUG_INFO(trans, "WRT PRPH dump\n");
478 if (!iwl_trans_grab_nic_access(trans, &flags))
481 for (i = 0; i < range_len; i++) {
482 /* The range includes both boundaries */
483 int num_bytes_in_chunk = iwl_prph_dump_addr[i].end -
484 iwl_prph_dump_addr[i].start + 4;
486 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PRPH);
487 (*data)->len = cpu_to_le32(sizeof(*prph) +
489 prph = (void *)(*data)->data;
490 prph->prph_start = cpu_to_le32(iwl_prph_dump_addr[i].start);
492 iwl_read_prph_block(trans, iwl_prph_dump_addr[i].start,
493 /* our range is inclusive, hence + 4 */
494 iwl_prph_dump_addr[i].end -
495 iwl_prph_dump_addr[i].start + 4,
498 *data = iwl_fw_error_next_data(*data);
501 iwl_trans_release_nic_access(trans, &flags);
505 * alloc_sgtable - allocates scallerlist table in the given size,
506 * fills it with pages and returns it
507 * @size: the size (in bytes) of the table
509 static struct scatterlist *alloc_sgtable(int size)
511 int alloc_size, nents, i;
512 struct page *new_page;
513 struct scatterlist *iter;
514 struct scatterlist *table;
516 nents = DIV_ROUND_UP(size, PAGE_SIZE);
517 table = kcalloc(nents, sizeof(*table), GFP_KERNEL);
520 sg_init_table(table, nents);
522 for_each_sg(table, iter, sg_nents(table), i) {
523 new_page = alloc_page(GFP_KERNEL);
525 /* release all previous allocated pages in the table */
527 for_each_sg(table, iter, sg_nents(table), i) {
528 new_page = sg_page(iter);
530 __free_page(new_page);
534 alloc_size = min_t(int, size, PAGE_SIZE);
536 sg_set_page(iter, new_page, alloc_size, 0);
541 static int iwl_fw_get_prph_len(struct iwl_fw_runtime *fwrt)
546 for (i = 0; i < ARRAY_SIZE(iwl_prph_dump_addr_comm);
548 /* The range includes both boundaries */
549 int num_bytes_in_chunk =
550 iwl_prph_dump_addr_comm[i].end -
551 iwl_prph_dump_addr_comm[i].start + 4;
553 prph_len += sizeof(struct iwl_fw_error_dump_data) +
554 sizeof(struct iwl_fw_error_dump_prph) +
558 if (fwrt->trans->cfg->mq_rx_supported) {
560 ARRAY_SIZE(iwl_prph_dump_addr_9000); i++) {
561 /* The range includes both boundaries */
562 int num_bytes_in_chunk =
563 iwl_prph_dump_addr_9000[i].end -
564 iwl_prph_dump_addr_9000[i].start + 4;
566 prph_len += sizeof(struct iwl_fw_error_dump_data) +
567 sizeof(struct iwl_fw_error_dump_prph) +
574 static void iwl_fw_dump_mem(struct iwl_fw_runtime *fwrt,
575 struct iwl_fw_error_dump_data **dump_data,
576 u32 len, u32 ofs, u32 type)
578 struct iwl_fw_error_dump_mem *dump_mem;
583 (*dump_data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_MEM);
584 (*dump_data)->len = cpu_to_le32(len + sizeof(*dump_mem));
585 dump_mem = (void *)(*dump_data)->data;
586 dump_mem->type = cpu_to_le32(type);
587 dump_mem->offset = cpu_to_le32(ofs);
588 iwl_trans_read_mem_bytes(fwrt->trans, ofs, dump_mem->data, len);
589 *dump_data = iwl_fw_error_next_data(*dump_data);
591 IWL_DEBUG_INFO(fwrt, "WRT memory dump. Type=%u\n", dump_mem->type);
594 #define ADD_LEN(len, item_len, const_len) \
595 do {size_t item = item_len; len += (!!item) * const_len + item; } \
598 static int iwl_fw_fifo_len(struct iwl_fw_runtime *fwrt,
599 struct iwl_fwrt_shared_mem_cfg *mem_cfg)
601 size_t hdr_len = sizeof(struct iwl_fw_error_dump_data) +
602 sizeof(struct iwl_fw_error_dump_fifo);
606 if (!(fwrt->fw->dbg.dump_mask & BIT(IWL_FW_ERROR_DUMP_RXF)))
609 /* Count RXF2 size */
610 ADD_LEN(fifo_len, mem_cfg->rxfifo2_size, hdr_len);
612 /* Count RXF1 sizes */
613 for (i = 0; i < mem_cfg->num_lmacs; i++)
614 ADD_LEN(fifo_len, mem_cfg->lmac[i].rxfifo1_size, hdr_len);
617 if (!(fwrt->fw->dbg.dump_mask & BIT(IWL_FW_ERROR_DUMP_TXF)))
618 goto dump_internal_txf;
620 /* Count TXF sizes */
621 for (i = 0; i < mem_cfg->num_lmacs; i++) {
624 for (j = 0; j < mem_cfg->num_txfifo_entries; j++)
625 ADD_LEN(fifo_len, mem_cfg->lmac[i].txfifo_size[j],
630 if (!((fwrt->fw->dbg.dump_mask & BIT(IWL_FW_ERROR_DUMP_INTERNAL_TXF)) &&
631 fw_has_capa(&fwrt->fw->ucode_capa,
632 IWL_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG)))
635 for (i = 0; i < ARRAY_SIZE(mem_cfg->internal_txfifo_size); i++)
636 ADD_LEN(fifo_len, mem_cfg->internal_txfifo_size[i], hdr_len);
642 static struct iwl_fw_error_dump_file *
643 _iwl_fw_error_dump(struct iwl_fw_runtime *fwrt,
644 struct iwl_fw_dump_ptrs *fw_error_dump)
646 struct iwl_fw_error_dump_file *dump_file;
647 struct iwl_fw_error_dump_data *dump_data;
648 struct iwl_fw_error_dump_info *dump_info;
649 struct iwl_fw_error_dump_smem_cfg *dump_smem_cfg;
650 struct iwl_fw_error_dump_trigger_desc *dump_trig;
651 u32 sram_len, sram_ofs;
652 const struct iwl_fw_dbg_mem_seg_tlv *fw_mem = fwrt->fw->dbg.mem_tlv;
653 struct iwl_fwrt_shared_mem_cfg *mem_cfg = &fwrt->smem_cfg;
654 u32 file_len, fifo_len = 0, prph_len = 0, radio_len = 0;
655 u32 smem_len = fwrt->fw->dbg.n_mem_tlv ? 0 : fwrt->trans->cfg->smem_len;
656 u32 sram2_len = fwrt->fw->dbg.n_mem_tlv ?
657 0 : fwrt->trans->cfg->dccm2_len;
660 /* SRAM - include stack CCM if driver knows the values for it */
661 if (!fwrt->trans->cfg->dccm_offset || !fwrt->trans->cfg->dccm_len) {
662 const struct fw_img *img;
664 img = &fwrt->fw->img[fwrt->cur_fw_img];
665 sram_ofs = img->sec[IWL_UCODE_SECTION_DATA].offset;
666 sram_len = img->sec[IWL_UCODE_SECTION_DATA].len;
668 sram_ofs = fwrt->trans->cfg->dccm_offset;
669 sram_len = fwrt->trans->cfg->dccm_len;
672 /* reading RXF/TXF sizes */
673 if (test_bit(STATUS_FW_ERROR, &fwrt->trans->status)) {
674 fifo_len = iwl_fw_fifo_len(fwrt, mem_cfg);
676 /* Make room for PRPH registers */
677 if (!fwrt->trans->cfg->gen2 &&
678 fwrt->fw->dbg.dump_mask & BIT(IWL_FW_ERROR_DUMP_PRPH))
679 prph_len += iwl_fw_get_prph_len(fwrt);
681 if (fwrt->trans->cfg->device_family == IWL_DEVICE_FAMILY_7000 &&
682 fwrt->fw->dbg.dump_mask & BIT(IWL_FW_ERROR_DUMP_RADIO_REG))
683 radio_len = sizeof(*dump_data) + RADIO_REG_MAX_READ;
686 file_len = sizeof(*dump_file) + fifo_len + prph_len + radio_len;
688 if (fwrt->fw->dbg.dump_mask & BIT(IWL_FW_ERROR_DUMP_DEV_FW_INFO))
689 file_len += sizeof(*dump_data) + sizeof(*dump_info);
690 if (fwrt->fw->dbg.dump_mask & BIT(IWL_FW_ERROR_DUMP_MEM_CFG))
691 file_len += sizeof(*dump_data) + sizeof(*dump_smem_cfg);
693 if (fwrt->fw->dbg.dump_mask & BIT(IWL_FW_ERROR_DUMP_MEM)) {
694 size_t hdr_len = sizeof(*dump_data) +
695 sizeof(struct iwl_fw_error_dump_mem);
697 /* Dump SRAM only if no mem_tlvs */
698 if (!fwrt->fw->dbg.n_mem_tlv)
699 ADD_LEN(file_len, sram_len, hdr_len);
701 /* Make room for all mem types that exist */
702 ADD_LEN(file_len, smem_len, hdr_len);
703 ADD_LEN(file_len, sram2_len, hdr_len);
705 for (i = 0; i < fwrt->fw->dbg.n_mem_tlv; i++)
706 ADD_LEN(file_len, le32_to_cpu(fw_mem[i].len), hdr_len);
709 /* Make room for fw's virtual image pages, if it exists */
710 if (fwrt->fw->dbg.dump_mask & BIT(IWL_FW_ERROR_DUMP_PAGING) &&
711 !fwrt->trans->cfg->gen2 &&
712 fwrt->fw->img[fwrt->cur_fw_img].paging_mem_size &&
713 fwrt->fw_paging_db[0].fw_paging_block)
714 file_len += fwrt->num_of_paging_blk *
715 (sizeof(*dump_data) +
716 sizeof(struct iwl_fw_error_dump_paging) +
719 if (iwl_fw_dbg_is_d3_debug_enabled(fwrt) && fwrt->dump.d3_debug_data) {
720 file_len += sizeof(*dump_data) +
721 fwrt->trans->cfg->d3_debug_data_length * 2;
724 /* If we only want a monitor dump, reset the file length */
725 if (fwrt->dump.monitor_only) {
726 file_len = sizeof(*dump_file) + sizeof(*dump_data) * 2 +
727 sizeof(*dump_info) + sizeof(*dump_smem_cfg);
730 if (fwrt->fw->dbg.dump_mask & BIT(IWL_FW_ERROR_DUMP_ERROR_INFO) &&
732 file_len += sizeof(*dump_data) + sizeof(*dump_trig) +
733 fwrt->dump.desc->len;
735 dump_file = vzalloc(file_len);
739 fw_error_dump->fwrt_ptr = dump_file;
741 dump_file->barker = cpu_to_le32(IWL_FW_ERROR_DUMP_BARKER);
742 dump_data = (void *)dump_file->data;
744 if (fwrt->fw->dbg.dump_mask & BIT(IWL_FW_ERROR_DUMP_DEV_FW_INFO)) {
745 dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_DEV_FW_INFO);
746 dump_data->len = cpu_to_le32(sizeof(*dump_info));
747 dump_info = (void *)dump_data->data;
748 dump_info->device_family =
749 fwrt->trans->cfg->device_family ==
750 IWL_DEVICE_FAMILY_7000 ?
751 cpu_to_le32(IWL_FW_ERROR_DUMP_FAMILY_7) :
752 cpu_to_le32(IWL_FW_ERROR_DUMP_FAMILY_8);
754 cpu_to_le32(CSR_HW_REV_STEP(fwrt->trans->hw_rev));
755 memcpy(dump_info->fw_human_readable, fwrt->fw->human_readable,
756 sizeof(dump_info->fw_human_readable));
757 strncpy(dump_info->dev_human_readable, fwrt->trans->cfg->name,
758 sizeof(dump_info->dev_human_readable) - 1);
759 strncpy(dump_info->bus_human_readable, fwrt->dev->bus->name,
760 sizeof(dump_info->bus_human_readable) - 1);
762 dump_data = iwl_fw_error_next_data(dump_data);
765 if (fwrt->fw->dbg.dump_mask & BIT(IWL_FW_ERROR_DUMP_MEM_CFG)) {
766 /* Dump shared memory configuration */
767 dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_MEM_CFG);
768 dump_data->len = cpu_to_le32(sizeof(*dump_smem_cfg));
769 dump_smem_cfg = (void *)dump_data->data;
770 dump_smem_cfg->num_lmacs = cpu_to_le32(mem_cfg->num_lmacs);
771 dump_smem_cfg->num_txfifo_entries =
772 cpu_to_le32(mem_cfg->num_txfifo_entries);
773 for (i = 0; i < MAX_NUM_LMAC; i++) {
775 u32 *txf_size = mem_cfg->lmac[i].txfifo_size;
777 for (j = 0; j < TX_FIFO_MAX_NUM; j++)
778 dump_smem_cfg->lmac[i].txfifo_size[j] =
779 cpu_to_le32(txf_size[j]);
780 dump_smem_cfg->lmac[i].rxfifo1_size =
781 cpu_to_le32(mem_cfg->lmac[i].rxfifo1_size);
783 dump_smem_cfg->rxfifo2_size =
784 cpu_to_le32(mem_cfg->rxfifo2_size);
785 dump_smem_cfg->internal_txfifo_addr =
786 cpu_to_le32(mem_cfg->internal_txfifo_addr);
787 for (i = 0; i < TX_FIFO_INTERNAL_MAX_NUM; i++) {
788 dump_smem_cfg->internal_txfifo_size[i] =
789 cpu_to_le32(mem_cfg->internal_txfifo_size[i]);
792 dump_data = iwl_fw_error_next_data(dump_data);
795 /* We only dump the FIFOs if the FW is in error state */
797 iwl_fw_dump_fifos(fwrt, &dump_data);
799 iwl_read_radio_regs(fwrt, &dump_data);
802 if (fwrt->fw->dbg.dump_mask & BIT(IWL_FW_ERROR_DUMP_ERROR_INFO) &&
804 dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_ERROR_INFO);
805 dump_data->len = cpu_to_le32(sizeof(*dump_trig) +
806 fwrt->dump.desc->len);
807 dump_trig = (void *)dump_data->data;
808 memcpy(dump_trig, &fwrt->dump.desc->trig_desc,
809 sizeof(*dump_trig) + fwrt->dump.desc->len);
811 dump_data = iwl_fw_error_next_data(dump_data);
814 /* In case we only want monitor dump, skip to dump trasport data */
815 if (fwrt->dump.monitor_only)
818 if (fwrt->fw->dbg.dump_mask & BIT(IWL_FW_ERROR_DUMP_MEM)) {
819 const struct iwl_fw_dbg_mem_seg_tlv *fw_dbg_mem =
820 fwrt->fw->dbg.mem_tlv;
822 if (!fwrt->fw->dbg.n_mem_tlv)
823 iwl_fw_dump_mem(fwrt, &dump_data, sram_len, sram_ofs,
824 IWL_FW_ERROR_DUMP_MEM_SRAM);
826 for (i = 0; i < fwrt->fw->dbg.n_mem_tlv; i++) {
827 u32 len = le32_to_cpu(fw_dbg_mem[i].len);
828 u32 ofs = le32_to_cpu(fw_dbg_mem[i].ofs);
830 iwl_fw_dump_mem(fwrt, &dump_data, len, ofs,
831 le32_to_cpu(fw_dbg_mem[i].data_type));
834 iwl_fw_dump_mem(fwrt, &dump_data, smem_len,
835 fwrt->trans->cfg->smem_offset,
836 IWL_FW_ERROR_DUMP_MEM_SMEM);
838 iwl_fw_dump_mem(fwrt, &dump_data, sram2_len,
839 fwrt->trans->cfg->dccm2_offset,
840 IWL_FW_ERROR_DUMP_MEM_SRAM);
843 if (iwl_fw_dbg_is_d3_debug_enabled(fwrt) && fwrt->dump.d3_debug_data) {
844 u32 addr = fwrt->trans->cfg->d3_debug_data_base_addr;
845 size_t data_size = fwrt->trans->cfg->d3_debug_data_length;
847 dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_D3_DEBUG_DATA);
848 dump_data->len = cpu_to_le32(data_size * 2);
850 memcpy(dump_data->data, fwrt->dump.d3_debug_data, data_size);
852 kfree(fwrt->dump.d3_debug_data);
853 fwrt->dump.d3_debug_data = NULL;
855 iwl_trans_read_mem_bytes(fwrt->trans, addr,
856 dump_data->data + data_size,
859 dump_data = iwl_fw_error_next_data(dump_data);
862 /* Dump fw's virtual image */
863 if (fwrt->fw->dbg.dump_mask & BIT(IWL_FW_ERROR_DUMP_PAGING) &&
864 !fwrt->trans->cfg->gen2 &&
865 fwrt->fw->img[fwrt->cur_fw_img].paging_mem_size &&
866 fwrt->fw_paging_db[0].fw_paging_block) {
867 IWL_DEBUG_INFO(fwrt, "WRT paging dump\n");
868 for (i = 1; i < fwrt->num_of_paging_blk + 1; i++) {
869 struct iwl_fw_error_dump_paging *paging;
871 fwrt->fw_paging_db[i].fw_paging_block;
872 dma_addr_t addr = fwrt->fw_paging_db[i].fw_paging_phys;
874 dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PAGING);
875 dump_data->len = cpu_to_le32(sizeof(*paging) +
877 paging = (void *)dump_data->data;
878 paging->index = cpu_to_le32(i);
879 dma_sync_single_for_cpu(fwrt->trans->dev, addr,
882 memcpy(paging->data, page_address(pages),
884 dump_data = iwl_fw_error_next_data(dump_data);
889 iwl_dump_prph(fwrt->trans, &dump_data,
890 iwl_prph_dump_addr_comm,
891 ARRAY_SIZE(iwl_prph_dump_addr_comm));
893 if (fwrt->trans->cfg->mq_rx_supported)
894 iwl_dump_prph(fwrt->trans, &dump_data,
895 iwl_prph_dump_addr_9000,
896 ARRAY_SIZE(iwl_prph_dump_addr_9000));
900 dump_file->file_len = cpu_to_le32(file_len);
904 void iwl_fw_error_dump(struct iwl_fw_runtime *fwrt)
906 struct iwl_fw_dump_ptrs *fw_error_dump;
907 struct iwl_fw_error_dump_file *dump_file;
908 struct scatterlist *sg_dump_data;
911 IWL_DEBUG_INFO(fwrt, "WRT dump start\n");
913 /* there's no point in fw dump if the bus is dead */
914 if (test_bit(STATUS_TRANS_DEAD, &fwrt->trans->status)) {
915 IWL_ERR(fwrt, "Skip fw error dump since bus is dead\n");
919 fw_error_dump = kzalloc(sizeof(*fw_error_dump), GFP_KERNEL);
923 dump_file = _iwl_fw_error_dump(fwrt, fw_error_dump);
925 kfree(fw_error_dump);
929 fw_error_dump->trans_ptr = iwl_trans_dump_data(fwrt->trans,
930 fwrt->dump.monitor_only);
931 file_len = le32_to_cpu(dump_file->file_len);
932 fw_error_dump->fwrt_len = file_len;
933 if (fw_error_dump->trans_ptr) {
934 file_len += fw_error_dump->trans_ptr->len;
935 dump_file->file_len = cpu_to_le32(file_len);
938 sg_dump_data = alloc_sgtable(file_len);
940 sg_pcopy_from_buffer(sg_dump_data,
941 sg_nents(sg_dump_data),
942 fw_error_dump->fwrt_ptr,
943 fw_error_dump->fwrt_len, 0);
944 if (fw_error_dump->trans_ptr)
945 sg_pcopy_from_buffer(sg_dump_data,
946 sg_nents(sg_dump_data),
947 fw_error_dump->trans_ptr->data,
948 fw_error_dump->trans_ptr->len,
949 fw_error_dump->fwrt_len);
950 dev_coredumpsg(fwrt->trans->dev, sg_dump_data, file_len,
953 vfree(fw_error_dump->fwrt_ptr);
954 vfree(fw_error_dump->trans_ptr);
955 kfree(fw_error_dump);
958 iwl_fw_free_dump_desc(fwrt);
959 clear_bit(IWL_FWRT_STATUS_DUMPING, &fwrt->status);
960 IWL_DEBUG_INFO(fwrt, "WRT dump done\n");
962 IWL_EXPORT_SYMBOL(iwl_fw_error_dump);
964 const struct iwl_fw_dump_desc iwl_dump_desc_assert = {
966 .type = cpu_to_le32(FW_DBG_TRIGGER_FW_ASSERT),
969 IWL_EXPORT_SYMBOL(iwl_dump_desc_assert);
971 void iwl_fw_alive_error_dump(struct iwl_fw_runtime *fwrt)
973 struct iwl_fw_dump_desc *iwl_dump_desc_no_alive =
974 kmalloc(sizeof(*iwl_dump_desc_no_alive), GFP_KERNEL);
976 if (!iwl_dump_desc_no_alive)
979 iwl_dump_desc_no_alive->trig_desc.type =
980 cpu_to_le32(FW_DBG_TRIGGER_NO_ALIVE);
981 iwl_dump_desc_no_alive->len = 0;
983 if (WARN_ON(fwrt->dump.desc))
984 iwl_fw_free_dump_desc(fwrt);
986 IWL_WARN(fwrt, "Collecting data: trigger %d fired.\n",
987 FW_DBG_TRIGGER_NO_ALIVE);
989 fwrt->dump.desc = iwl_dump_desc_no_alive;
990 iwl_fw_error_dump(fwrt);
991 clear_bit(IWL_FWRT_STATUS_WAIT_ALIVE, &fwrt->status);
993 IWL_EXPORT_SYMBOL(iwl_fw_alive_error_dump);
995 int iwl_fw_dbg_collect_desc(struct iwl_fw_runtime *fwrt,
996 const struct iwl_fw_dump_desc *desc,
1001 * If the loading of the FW completed successfully, the next step is to
1002 * get the SMEM config data. Thus, if fwrt->smem_cfg.num_lmacs is non
1003 * zero, the FW was already loaded successully. If the state is "NO_FW"
1004 * in such a case - exit, since FW may be dead. Otherwise, we
1005 * can try to collect the data, since FW might just not be fully
1006 * loaded (no "ALIVE" yet), and the debug data is accessible.
1008 * Corner case: got the FW alive but crashed before getting the SMEM
1009 * config. In such a case, due to HW access problems, we might
1012 if (fwrt->trans->state == IWL_TRANS_NO_FW &&
1013 fwrt->smem_cfg.num_lmacs)
1016 if (test_and_set_bit(IWL_FWRT_STATUS_DUMPING, &fwrt->status) ||
1017 test_bit(IWL_FWRT_STATUS_WAIT_ALIVE, &fwrt->status))
1020 if (WARN_ON(fwrt->dump.desc))
1021 iwl_fw_free_dump_desc(fwrt);
1023 IWL_WARN(fwrt, "Collecting data: trigger %d fired.\n",
1024 le32_to_cpu(desc->trig_desc.type));
1026 fwrt->dump.desc = desc;
1027 fwrt->dump.monitor_only = monitor_only;
1029 schedule_delayed_work(&fwrt->dump.wk, delay);
1033 IWL_EXPORT_SYMBOL(iwl_fw_dbg_collect_desc);
1035 int iwl_fw_dbg_collect(struct iwl_fw_runtime *fwrt,
1036 enum iwl_fw_dbg_trigger trig,
1037 const char *str, size_t len,
1038 struct iwl_fw_dbg_trigger_tlv *trigger)
1040 struct iwl_fw_dump_desc *desc;
1041 unsigned int delay = 0;
1042 bool monitor_only = false;
1045 u16 occurrences = le16_to_cpu(trigger->occurrences) - 1;
1047 if (!le16_to_cpu(trigger->occurrences))
1050 if (trigger->flags & IWL_FW_DBG_FORCE_RESTART) {
1051 IWL_WARN(fwrt, "Force restart: trigger %d fired.\n",
1053 iwl_force_nmi(fwrt->trans);
1057 trigger->occurrences = cpu_to_le16(occurrences);
1058 delay = le16_to_cpu(trigger->trig_dis_ms);
1059 monitor_only = trigger->mode & IWL_FW_DBG_TRIGGER_MONITOR_ONLY;
1062 desc = kzalloc(sizeof(*desc) + len, GFP_ATOMIC);
1068 desc->trig_desc.type = cpu_to_le32(trig);
1069 memcpy(desc->trig_desc.data, str, len);
1071 return iwl_fw_dbg_collect_desc(fwrt, desc, monitor_only, delay);
1073 IWL_EXPORT_SYMBOL(iwl_fw_dbg_collect);
1075 int iwl_fw_dbg_collect_trig(struct iwl_fw_runtime *fwrt,
1076 struct iwl_fw_dbg_trigger_tlv *trigger,
1077 const char *fmt, ...)
1085 buf[sizeof(buf) - 1] = '\0';
1088 vsnprintf(buf, sizeof(buf), fmt, ap);
1091 /* check for truncation */
1092 if (WARN_ON_ONCE(buf[sizeof(buf) - 1]))
1093 buf[sizeof(buf) - 1] = '\0';
1095 len = strlen(buf) + 1;
1098 ret = iwl_fw_dbg_collect(fwrt, le32_to_cpu(trigger->id), buf, len,
1106 IWL_EXPORT_SYMBOL(iwl_fw_dbg_collect_trig);
1108 int iwl_fw_start_dbg_conf(struct iwl_fw_runtime *fwrt, u8 conf_id)
1114 if (WARN_ONCE(conf_id >= ARRAY_SIZE(fwrt->fw->dbg.conf_tlv),
1115 "Invalid configuration %d\n", conf_id))
1118 /* EARLY START - firmware's configuration is hard coded */
1119 if ((!fwrt->fw->dbg.conf_tlv[conf_id] ||
1120 !fwrt->fw->dbg.conf_tlv[conf_id]->num_of_hcmds) &&
1121 conf_id == FW_DBG_START_FROM_ALIVE)
1124 if (!fwrt->fw->dbg.conf_tlv[conf_id])
1127 if (fwrt->dump.conf != FW_DBG_INVALID)
1128 IWL_WARN(fwrt, "FW already configured (%d) - re-configuring\n",
1131 /* Send all HCMDs for configuring the FW debug */
1132 ptr = (void *)&fwrt->fw->dbg.conf_tlv[conf_id]->hcmd;
1133 for (i = 0; i < fwrt->fw->dbg.conf_tlv[conf_id]->num_of_hcmds; i++) {
1134 struct iwl_fw_dbg_conf_hcmd *cmd = (void *)ptr;
1135 struct iwl_host_cmd hcmd = {
1137 .len = { le16_to_cpu(cmd->len), },
1138 .data = { cmd->data, },
1141 ret = iwl_trans_send_cmd(fwrt->trans, &hcmd);
1145 ptr += sizeof(*cmd);
1146 ptr += le16_to_cpu(cmd->len);
1149 fwrt->dump.conf = conf_id;
1153 IWL_EXPORT_SYMBOL(iwl_fw_start_dbg_conf);
1155 /* this function assumes dump_start was called beforehand and dump_end will be
1158 void iwl_fw_dbg_collect_sync(struct iwl_fw_runtime *fwrt)
1160 struct iwl_fw_dbg_params params = {0};
1162 if (!test_bit(IWL_FWRT_STATUS_DUMPING, &fwrt->status))
1165 if (fwrt->ops && fwrt->ops->fw_running &&
1166 !fwrt->ops->fw_running(fwrt->ops_ctx)) {
1167 IWL_ERR(fwrt, "Firmware not running - cannot dump error\n");
1168 iwl_fw_free_dump_desc(fwrt);
1169 clear_bit(IWL_FWRT_STATUS_DUMPING, &fwrt->status);
1173 iwl_fw_dbg_stop_recording(fwrt, ¶ms);
1175 iwl_fw_error_dump(fwrt);
1177 /* start recording again if the firmware is not crashed */
1178 if (!test_bit(STATUS_FW_ERROR, &fwrt->trans->status) &&
1179 fwrt->fw->dbg.dest_tlv) {
1180 /* wait before we collect the data till the DBGC stop */
1182 iwl_fw_dbg_restart_recording(fwrt, ¶ms);
1185 IWL_EXPORT_SYMBOL(iwl_fw_dbg_collect_sync);
1187 void iwl_fw_error_dump_wk(struct work_struct *work)
1189 struct iwl_fw_runtime *fwrt =
1190 container_of(work, struct iwl_fw_runtime, dump.wk.work);
1192 if (fwrt->ops && fwrt->ops->dump_start &&
1193 fwrt->ops->dump_start(fwrt->ops_ctx))
1196 iwl_fw_dbg_collect_sync(fwrt);
1198 if (fwrt->ops && fwrt->ops->dump_end)
1199 fwrt->ops->dump_end(fwrt->ops_ctx);
1202 void iwl_fw_dbg_read_d3_debug_data(struct iwl_fw_runtime *fwrt)
1204 const struct iwl_cfg *cfg = fwrt->trans->cfg;
1206 if (!iwl_fw_dbg_is_d3_debug_enabled(fwrt))
1209 if (!fwrt->dump.d3_debug_data) {
1210 fwrt->dump.d3_debug_data = kmalloc(cfg->d3_debug_data_length,
1212 if (!fwrt->dump.d3_debug_data) {
1214 "failed to allocate memory for D3 debug data\n");
1219 /* if the buffer holds previous debug data it is overwritten */
1220 iwl_trans_read_mem_bytes(fwrt->trans, cfg->d3_debug_data_base_addr,
1221 fwrt->dump.d3_debug_data,
1222 cfg->d3_debug_data_length);
1224 IWL_EXPORT_SYMBOL(iwl_fw_dbg_read_d3_debug_data);