1 /******************************************************************************
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
8 * Copyright(c) 2008 - 2014 Intel Corporation. All rights reserved.
9 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
10 * Copyright(c) 2015 - 2017 Intel Deutschland GmbH
11 * Copyright(c) 2018 - 2019 Intel Corporation
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of version 2 of the GNU General Public License as
15 * published by the Free Software Foundation.
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
22 * The full GNU General Public License is included in this distribution
23 * in the file called COPYING.
25 * Contact Information:
26 * Intel Linux Wireless <linuxwifi@intel.com>
27 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
31 * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved.
32 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
33 * Copyright(c) 2015 - 2017 Intel Deutschland GmbH
34 * Copyright(c) 2018 - 2019 Intel Corporation
35 * All rights reserved.
37 * Redistribution and use in source and binary forms, with or without
38 * modification, are permitted provided that the following conditions
41 * * Redistributions of source code must retain the above copyright
42 * notice, this list of conditions and the following disclaimer.
43 * * Redistributions in binary form must reproduce the above copyright
44 * notice, this list of conditions and the following disclaimer in
45 * the documentation and/or other materials provided with the
47 * * Neither the name Intel Corporation nor the names of its
48 * contributors may be used to endorse or promote products derived
49 * from this software without specific prior written permission.
51 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
52 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
53 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
54 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
55 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
56 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
57 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
58 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
59 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
60 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
61 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
63 *****************************************************************************/
64 #include <linux/devcoredump.h>
74 * struct iwl_fw_dump_ptrs - set of pointers needed for the fw-error-dump
76 * @fwrt_ptr: pointer to the buffer coming from fwrt
77 * @trans_ptr: pointer to struct %iwl_trans_dump_data which contains the
79 * @trans_len: length of the valid data in trans_ptr
80 * @fwrt_len: length of the valid data in fwrt_ptr
82 struct iwl_fw_dump_ptrs {
83 struct iwl_trans_dump_data *trans_ptr;
88 #define RADIO_REG_MAX_READ 0x2ad
89 static void iwl_read_radio_regs(struct iwl_fw_runtime *fwrt,
90 struct iwl_fw_error_dump_data **dump_data)
92 u8 *pos = (void *)(*dump_data)->data;
96 IWL_DEBUG_INFO(fwrt, "WRT radio registers dump\n");
98 if (!iwl_trans_grab_nic_access(fwrt->trans, &flags))
101 (*dump_data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RADIO_REG);
102 (*dump_data)->len = cpu_to_le32(RADIO_REG_MAX_READ);
104 for (i = 0; i < RADIO_REG_MAX_READ; i++) {
105 u32 rd_cmd = RADIO_RSP_RD_CMD;
107 rd_cmd |= i << RADIO_RSP_ADDR_POS;
108 iwl_write_prph_no_grab(fwrt->trans, RSP_RADIO_CMD, rd_cmd);
109 *pos = (u8)iwl_read_prph_no_grab(fwrt->trans, RSP_RADIO_RDDAT);
114 *dump_data = iwl_fw_error_next_data(*dump_data);
116 iwl_trans_release_nic_access(fwrt->trans, &flags);
119 static void iwl_fwrt_dump_rxf(struct iwl_fw_runtime *fwrt,
120 struct iwl_fw_error_dump_data **dump_data,
121 int size, u32 offset, int fifo_num)
123 struct iwl_fw_error_dump_fifo *fifo_hdr;
128 fifo_hdr = (void *)(*dump_data)->data;
129 fifo_data = (void *)fifo_hdr->data;
132 /* No need to try to read the data if the length is 0 */
136 /* Add a TLV for the RXF */
137 (*dump_data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RXF);
138 (*dump_data)->len = cpu_to_le32(fifo_len + sizeof(*fifo_hdr));
140 fifo_hdr->fifo_num = cpu_to_le32(fifo_num);
141 fifo_hdr->available_bytes =
142 cpu_to_le32(iwl_trans_read_prph(fwrt->trans,
143 RXF_RD_D_SPACE + offset));
145 cpu_to_le32(iwl_trans_read_prph(fwrt->trans,
146 RXF_RD_WR_PTR + offset));
148 cpu_to_le32(iwl_trans_read_prph(fwrt->trans,
149 RXF_RD_RD_PTR + offset));
150 fifo_hdr->fence_ptr =
151 cpu_to_le32(iwl_trans_read_prph(fwrt->trans,
152 RXF_RD_FENCE_PTR + offset));
153 fifo_hdr->fence_mode =
154 cpu_to_le32(iwl_trans_read_prph(fwrt->trans,
155 RXF_SET_FENCE_MODE + offset));
158 iwl_trans_write_prph(fwrt->trans, RXF_SET_FENCE_MODE + offset, 0x1);
159 /* Set fence pointer to the same place like WR pointer */
160 iwl_trans_write_prph(fwrt->trans, RXF_LD_WR2FENCE + offset, 0x1);
161 /* Set fence offset */
162 iwl_trans_write_prph(fwrt->trans,
163 RXF_LD_FENCE_OFFSET_ADDR + offset, 0x0);
166 fifo_len /= sizeof(u32); /* Size in DWORDS */
167 for (i = 0; i < fifo_len; i++)
168 fifo_data[i] = iwl_trans_read_prph(fwrt->trans,
169 RXF_FIFO_RD_FENCE_INC +
171 *dump_data = iwl_fw_error_next_data(*dump_data);
174 static void iwl_fwrt_dump_txf(struct iwl_fw_runtime *fwrt,
175 struct iwl_fw_error_dump_data **dump_data,
176 int size, u32 offset, int fifo_num)
178 struct iwl_fw_error_dump_fifo *fifo_hdr;
183 fifo_hdr = (void *)(*dump_data)->data;
184 fifo_data = (void *)fifo_hdr->data;
187 /* No need to try to read the data if the length is 0 */
191 /* Add a TLV for the FIFO */
192 (*dump_data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_TXF);
193 (*dump_data)->len = cpu_to_le32(fifo_len + sizeof(*fifo_hdr));
195 fifo_hdr->fifo_num = cpu_to_le32(fifo_num);
196 fifo_hdr->available_bytes =
197 cpu_to_le32(iwl_trans_read_prph(fwrt->trans,
198 TXF_FIFO_ITEM_CNT + offset));
200 cpu_to_le32(iwl_trans_read_prph(fwrt->trans,
201 TXF_WR_PTR + offset));
203 cpu_to_le32(iwl_trans_read_prph(fwrt->trans,
204 TXF_RD_PTR + offset));
205 fifo_hdr->fence_ptr =
206 cpu_to_le32(iwl_trans_read_prph(fwrt->trans,
207 TXF_FENCE_PTR + offset));
208 fifo_hdr->fence_mode =
209 cpu_to_le32(iwl_trans_read_prph(fwrt->trans,
210 TXF_LOCK_FENCE + offset));
212 /* Set the TXF_READ_MODIFY_ADDR to TXF_WR_PTR */
213 iwl_trans_write_prph(fwrt->trans, TXF_READ_MODIFY_ADDR + offset,
214 TXF_WR_PTR + offset);
216 /* Dummy-read to advance the read pointer to the head */
217 iwl_trans_read_prph(fwrt->trans, TXF_READ_MODIFY_DATA + offset);
220 fifo_len /= sizeof(u32); /* Size in DWORDS */
221 for (i = 0; i < fifo_len; i++)
222 fifo_data[i] = iwl_trans_read_prph(fwrt->trans,
223 TXF_READ_MODIFY_DATA +
225 *dump_data = iwl_fw_error_next_data(*dump_data);
228 static void iwl_fw_dump_rxf(struct iwl_fw_runtime *fwrt,
229 struct iwl_fw_error_dump_data **dump_data)
231 struct iwl_fwrt_shared_mem_cfg *cfg = &fwrt->smem_cfg;
234 IWL_DEBUG_INFO(fwrt, "WRT RX FIFO dump\n");
236 if (!iwl_trans_grab_nic_access(fwrt->trans, &flags))
239 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_RXF)) {
241 iwl_fwrt_dump_rxf(fwrt, dump_data,
242 cfg->lmac[0].rxfifo1_size, 0, 0);
244 iwl_fwrt_dump_rxf(fwrt, dump_data, cfg->rxfifo2_size,
246 fwrt->trans->cfg->umac_prph_offset, 1);
247 /* Pull LMAC2 RXF1 */
248 if (fwrt->smem_cfg.num_lmacs > 1)
249 iwl_fwrt_dump_rxf(fwrt, dump_data,
250 cfg->lmac[1].rxfifo1_size,
251 LMAC2_PRPH_OFFSET, 2);
254 iwl_trans_release_nic_access(fwrt->trans, &flags);
257 static void iwl_fw_dump_txf(struct iwl_fw_runtime *fwrt,
258 struct iwl_fw_error_dump_data **dump_data)
260 struct iwl_fw_error_dump_fifo *fifo_hdr;
261 struct iwl_fwrt_shared_mem_cfg *cfg = &fwrt->smem_cfg;
267 IWL_DEBUG_INFO(fwrt, "WRT TX FIFO dump\n");
269 if (!iwl_trans_grab_nic_access(fwrt->trans, &flags))
272 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_TXF)) {
273 /* Pull TXF data from LMAC1 */
274 for (i = 0; i < fwrt->smem_cfg.num_txfifo_entries; i++) {
275 /* Mark the number of TXF we're pulling now */
276 iwl_trans_write_prph(fwrt->trans, TXF_LARC_NUM, i);
277 iwl_fwrt_dump_txf(fwrt, dump_data,
278 cfg->lmac[0].txfifo_size[i], 0, i);
281 /* Pull TXF data from LMAC2 */
282 if (fwrt->smem_cfg.num_lmacs > 1) {
283 for (i = 0; i < fwrt->smem_cfg.num_txfifo_entries;
285 /* Mark the number of TXF we're pulling now */
286 iwl_trans_write_prph(fwrt->trans,
288 LMAC2_PRPH_OFFSET, i);
289 iwl_fwrt_dump_txf(fwrt, dump_data,
290 cfg->lmac[1].txfifo_size[i],
292 i + cfg->num_txfifo_entries);
297 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_INTERNAL_TXF) &&
298 fw_has_capa(&fwrt->fw->ucode_capa,
299 IWL_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG)) {
300 /* Pull UMAC internal TXF data from all TXFs */
302 i < ARRAY_SIZE(fwrt->smem_cfg.internal_txfifo_size);
304 fifo_hdr = (void *)(*dump_data)->data;
305 fifo_data = (void *)fifo_hdr->data;
306 fifo_len = fwrt->smem_cfg.internal_txfifo_size[i];
308 /* No need to try to read the data if the length is 0 */
312 /* Add a TLV for the internal FIFOs */
314 cpu_to_le32(IWL_FW_ERROR_DUMP_INTERNAL_TXF);
316 cpu_to_le32(fifo_len + sizeof(*fifo_hdr));
318 fifo_hdr->fifo_num = cpu_to_le32(i);
320 /* Mark the number of TXF we're pulling now */
321 iwl_trans_write_prph(fwrt->trans, TXF_CPU2_NUM, i +
322 fwrt->smem_cfg.num_txfifo_entries);
324 fifo_hdr->available_bytes =
325 cpu_to_le32(iwl_trans_read_prph(fwrt->trans,
326 TXF_CPU2_FIFO_ITEM_CNT));
328 cpu_to_le32(iwl_trans_read_prph(fwrt->trans,
331 cpu_to_le32(iwl_trans_read_prph(fwrt->trans,
333 fifo_hdr->fence_ptr =
334 cpu_to_le32(iwl_trans_read_prph(fwrt->trans,
335 TXF_CPU2_FENCE_PTR));
336 fifo_hdr->fence_mode =
337 cpu_to_le32(iwl_trans_read_prph(fwrt->trans,
338 TXF_CPU2_LOCK_FENCE));
340 /* Set TXF_CPU2_READ_MODIFY_ADDR to TXF_CPU2_WR_PTR */
341 iwl_trans_write_prph(fwrt->trans,
342 TXF_CPU2_READ_MODIFY_ADDR,
345 /* Dummy-read to advance the read pointer to head */
346 iwl_trans_read_prph(fwrt->trans,
347 TXF_CPU2_READ_MODIFY_DATA);
350 fifo_len /= sizeof(u32); /* Size in DWORDS */
351 for (j = 0; j < fifo_len; j++)
353 iwl_trans_read_prph(fwrt->trans,
354 TXF_CPU2_READ_MODIFY_DATA);
355 *dump_data = iwl_fw_error_next_data(*dump_data);
359 iwl_trans_release_nic_access(fwrt->trans, &flags);
362 #define IWL8260_ICCM_OFFSET 0x44000 /* Only for B-step */
363 #define IWL8260_ICCM_LEN 0xC000 /* Only for B-step */
365 struct iwl_prph_range {
369 static const struct iwl_prph_range iwl_prph_dump_addr_comm[] = {
370 { .start = 0x00a00000, .end = 0x00a00000 },
371 { .start = 0x00a0000c, .end = 0x00a00024 },
372 { .start = 0x00a0002c, .end = 0x00a0003c },
373 { .start = 0x00a00410, .end = 0x00a00418 },
374 { .start = 0x00a00420, .end = 0x00a00420 },
375 { .start = 0x00a00428, .end = 0x00a00428 },
376 { .start = 0x00a00430, .end = 0x00a0043c },
377 { .start = 0x00a00444, .end = 0x00a00444 },
378 { .start = 0x00a004c0, .end = 0x00a004cc },
379 { .start = 0x00a004d8, .end = 0x00a004d8 },
380 { .start = 0x00a004e0, .end = 0x00a004f0 },
381 { .start = 0x00a00840, .end = 0x00a00840 },
382 { .start = 0x00a00850, .end = 0x00a00858 },
383 { .start = 0x00a01004, .end = 0x00a01008 },
384 { .start = 0x00a01010, .end = 0x00a01010 },
385 { .start = 0x00a01018, .end = 0x00a01018 },
386 { .start = 0x00a01024, .end = 0x00a01024 },
387 { .start = 0x00a0102c, .end = 0x00a01034 },
388 { .start = 0x00a0103c, .end = 0x00a01040 },
389 { .start = 0x00a01048, .end = 0x00a01094 },
390 { .start = 0x00a01c00, .end = 0x00a01c20 },
391 { .start = 0x00a01c58, .end = 0x00a01c58 },
392 { .start = 0x00a01c7c, .end = 0x00a01c7c },
393 { .start = 0x00a01c28, .end = 0x00a01c54 },
394 { .start = 0x00a01c5c, .end = 0x00a01c5c },
395 { .start = 0x00a01c60, .end = 0x00a01cdc },
396 { .start = 0x00a01ce0, .end = 0x00a01d0c },
397 { .start = 0x00a01d18, .end = 0x00a01d20 },
398 { .start = 0x00a01d2c, .end = 0x00a01d30 },
399 { .start = 0x00a01d40, .end = 0x00a01d5c },
400 { .start = 0x00a01d80, .end = 0x00a01d80 },
401 { .start = 0x00a01d98, .end = 0x00a01d9c },
402 { .start = 0x00a01da8, .end = 0x00a01da8 },
403 { .start = 0x00a01db8, .end = 0x00a01df4 },
404 { .start = 0x00a01dc0, .end = 0x00a01dfc },
405 { .start = 0x00a01e00, .end = 0x00a01e2c },
406 { .start = 0x00a01e40, .end = 0x00a01e60 },
407 { .start = 0x00a01e68, .end = 0x00a01e6c },
408 { .start = 0x00a01e74, .end = 0x00a01e74 },
409 { .start = 0x00a01e84, .end = 0x00a01e90 },
410 { .start = 0x00a01e9c, .end = 0x00a01ec4 },
411 { .start = 0x00a01ed0, .end = 0x00a01ee0 },
412 { .start = 0x00a01f00, .end = 0x00a01f1c },
413 { .start = 0x00a01f44, .end = 0x00a01ffc },
414 { .start = 0x00a02000, .end = 0x00a02048 },
415 { .start = 0x00a02068, .end = 0x00a020f0 },
416 { .start = 0x00a02100, .end = 0x00a02118 },
417 { .start = 0x00a02140, .end = 0x00a0214c },
418 { .start = 0x00a02168, .end = 0x00a0218c },
419 { .start = 0x00a021c0, .end = 0x00a021c0 },
420 { .start = 0x00a02400, .end = 0x00a02410 },
421 { .start = 0x00a02418, .end = 0x00a02420 },
422 { .start = 0x00a02428, .end = 0x00a0242c },
423 { .start = 0x00a02434, .end = 0x00a02434 },
424 { .start = 0x00a02440, .end = 0x00a02460 },
425 { .start = 0x00a02468, .end = 0x00a024b0 },
426 { .start = 0x00a024c8, .end = 0x00a024cc },
427 { .start = 0x00a02500, .end = 0x00a02504 },
428 { .start = 0x00a0250c, .end = 0x00a02510 },
429 { .start = 0x00a02540, .end = 0x00a02554 },
430 { .start = 0x00a02580, .end = 0x00a025f4 },
431 { .start = 0x00a02600, .end = 0x00a0260c },
432 { .start = 0x00a02648, .end = 0x00a02650 },
433 { .start = 0x00a02680, .end = 0x00a02680 },
434 { .start = 0x00a026c0, .end = 0x00a026d0 },
435 { .start = 0x00a02700, .end = 0x00a0270c },
436 { .start = 0x00a02804, .end = 0x00a02804 },
437 { .start = 0x00a02818, .end = 0x00a0281c },
438 { .start = 0x00a02c00, .end = 0x00a02db4 },
439 { .start = 0x00a02df4, .end = 0x00a02fb0 },
440 { .start = 0x00a03000, .end = 0x00a03014 },
441 { .start = 0x00a0301c, .end = 0x00a0302c },
442 { .start = 0x00a03034, .end = 0x00a03038 },
443 { .start = 0x00a03040, .end = 0x00a03048 },
444 { .start = 0x00a03060, .end = 0x00a03068 },
445 { .start = 0x00a03070, .end = 0x00a03074 },
446 { .start = 0x00a0307c, .end = 0x00a0307c },
447 { .start = 0x00a03080, .end = 0x00a03084 },
448 { .start = 0x00a0308c, .end = 0x00a03090 },
449 { .start = 0x00a03098, .end = 0x00a03098 },
450 { .start = 0x00a030a0, .end = 0x00a030a0 },
451 { .start = 0x00a030a8, .end = 0x00a030b4 },
452 { .start = 0x00a030bc, .end = 0x00a030bc },
453 { .start = 0x00a030c0, .end = 0x00a0312c },
454 { .start = 0x00a03c00, .end = 0x00a03c5c },
455 { .start = 0x00a04400, .end = 0x00a04454 },
456 { .start = 0x00a04460, .end = 0x00a04474 },
457 { .start = 0x00a044c0, .end = 0x00a044ec },
458 { .start = 0x00a04500, .end = 0x00a04504 },
459 { .start = 0x00a04510, .end = 0x00a04538 },
460 { .start = 0x00a04540, .end = 0x00a04548 },
461 { .start = 0x00a04560, .end = 0x00a0457c },
462 { .start = 0x00a04590, .end = 0x00a04598 },
463 { .start = 0x00a045c0, .end = 0x00a045f4 },
466 static const struct iwl_prph_range iwl_prph_dump_addr_9000[] = {
467 { .start = 0x00a05c00, .end = 0x00a05c18 },
468 { .start = 0x00a05400, .end = 0x00a056e8 },
469 { .start = 0x00a08000, .end = 0x00a098bc },
470 { .start = 0x00a02400, .end = 0x00a02758 },
473 static const struct iwl_prph_range iwl_prph_dump_addr_22000[] = {
474 { .start = 0x00a00000, .end = 0x00a00000 },
475 { .start = 0x00a0000c, .end = 0x00a00024 },
476 { .start = 0x00a0002c, .end = 0x00a00034 },
477 { .start = 0x00a0003c, .end = 0x00a0003c },
478 { .start = 0x00a00410, .end = 0x00a00418 },
479 { .start = 0x00a00420, .end = 0x00a00420 },
480 { .start = 0x00a00428, .end = 0x00a00428 },
481 { .start = 0x00a00430, .end = 0x00a0043c },
482 { .start = 0x00a00444, .end = 0x00a00444 },
483 { .start = 0x00a00840, .end = 0x00a00840 },
484 { .start = 0x00a00850, .end = 0x00a00858 },
485 { .start = 0x00a01004, .end = 0x00a01008 },
486 { .start = 0x00a01010, .end = 0x00a01010 },
487 { .start = 0x00a01018, .end = 0x00a01018 },
488 { .start = 0x00a01024, .end = 0x00a01024 },
489 { .start = 0x00a0102c, .end = 0x00a01034 },
490 { .start = 0x00a0103c, .end = 0x00a01040 },
491 { .start = 0x00a01048, .end = 0x00a01050 },
492 { .start = 0x00a01058, .end = 0x00a01058 },
493 { .start = 0x00a01060, .end = 0x00a01070 },
494 { .start = 0x00a0108c, .end = 0x00a0108c },
495 { .start = 0x00a01c20, .end = 0x00a01c28 },
496 { .start = 0x00a01d10, .end = 0x00a01d10 },
497 { .start = 0x00a01e28, .end = 0x00a01e2c },
498 { .start = 0x00a01e60, .end = 0x00a01e60 },
499 { .start = 0x00a01e80, .end = 0x00a01e80 },
500 { .start = 0x00a01ea0, .end = 0x00a01ea0 },
501 { .start = 0x00a02000, .end = 0x00a0201c },
502 { .start = 0x00a02024, .end = 0x00a02024 },
503 { .start = 0x00a02040, .end = 0x00a02048 },
504 { .start = 0x00a020c0, .end = 0x00a020e0 },
505 { .start = 0x00a02400, .end = 0x00a02404 },
506 { .start = 0x00a0240c, .end = 0x00a02414 },
507 { .start = 0x00a0241c, .end = 0x00a0243c },
508 { .start = 0x00a02448, .end = 0x00a024bc },
509 { .start = 0x00a024c4, .end = 0x00a024cc },
510 { .start = 0x00a02508, .end = 0x00a02508 },
511 { .start = 0x00a02510, .end = 0x00a02514 },
512 { .start = 0x00a0251c, .end = 0x00a0251c },
513 { .start = 0x00a0252c, .end = 0x00a0255c },
514 { .start = 0x00a02564, .end = 0x00a025a0 },
515 { .start = 0x00a025a8, .end = 0x00a025b4 },
516 { .start = 0x00a025c0, .end = 0x00a025c0 },
517 { .start = 0x00a025e8, .end = 0x00a025f4 },
518 { .start = 0x00a02c08, .end = 0x00a02c18 },
519 { .start = 0x00a02c2c, .end = 0x00a02c38 },
520 { .start = 0x00a02c68, .end = 0x00a02c78 },
521 { .start = 0x00a03000, .end = 0x00a03000 },
522 { .start = 0x00a03010, .end = 0x00a03014 },
523 { .start = 0x00a0301c, .end = 0x00a0302c },
524 { .start = 0x00a03034, .end = 0x00a03038 },
525 { .start = 0x00a03040, .end = 0x00a03044 },
526 { .start = 0x00a03060, .end = 0x00a03068 },
527 { .start = 0x00a03070, .end = 0x00a03070 },
528 { .start = 0x00a0307c, .end = 0x00a03084 },
529 { .start = 0x00a0308c, .end = 0x00a03090 },
530 { .start = 0x00a03098, .end = 0x00a03098 },
531 { .start = 0x00a030a0, .end = 0x00a030a0 },
532 { .start = 0x00a030a8, .end = 0x00a030b4 },
533 { .start = 0x00a030bc, .end = 0x00a030c0 },
534 { .start = 0x00a030c8, .end = 0x00a030f4 },
535 { .start = 0x00a03100, .end = 0x00a0312c },
536 { .start = 0x00a03c00, .end = 0x00a03c5c },
537 { .start = 0x00a04400, .end = 0x00a04454 },
538 { .start = 0x00a04460, .end = 0x00a04474 },
539 { .start = 0x00a044c0, .end = 0x00a044ec },
540 { .start = 0x00a04500, .end = 0x00a04504 },
541 { .start = 0x00a04510, .end = 0x00a04538 },
542 { .start = 0x00a04540, .end = 0x00a04548 },
543 { .start = 0x00a04560, .end = 0x00a04560 },
544 { .start = 0x00a04570, .end = 0x00a0457c },
545 { .start = 0x00a04590, .end = 0x00a04590 },
546 { .start = 0x00a04598, .end = 0x00a04598 },
547 { .start = 0x00a045c0, .end = 0x00a045f4 },
548 { .start = 0x00a05c18, .end = 0x00a05c1c },
549 { .start = 0x00a0c000, .end = 0x00a0c018 },
550 { .start = 0x00a0c020, .end = 0x00a0c028 },
551 { .start = 0x00a0c038, .end = 0x00a0c094 },
552 { .start = 0x00a0c0c0, .end = 0x00a0c104 },
553 { .start = 0x00a0c10c, .end = 0x00a0c118 },
554 { .start = 0x00a0c150, .end = 0x00a0c174 },
555 { .start = 0x00a0c17c, .end = 0x00a0c188 },
556 { .start = 0x00a0c190, .end = 0x00a0c198 },
557 { .start = 0x00a0c1a0, .end = 0x00a0c1a8 },
558 { .start = 0x00a0c1b0, .end = 0x00a0c1b8 },
561 static const struct iwl_prph_range iwl_prph_dump_addr_ax210[] = {
562 { .start = 0x00d03c00, .end = 0x00d03c64 },
563 { .start = 0x00d05c18, .end = 0x00d05c1c },
564 { .start = 0x00d0c000, .end = 0x00d0c174 },
567 static void iwl_read_prph_block(struct iwl_trans *trans, u32 start,
568 u32 len_bytes, __le32 *data)
572 for (i = 0; i < len_bytes; i += 4)
573 *data++ = cpu_to_le32(iwl_read_prph_no_grab(trans, start + i));
576 static void iwl_dump_prph(struct iwl_fw_runtime *fwrt,
577 const struct iwl_prph_range *iwl_prph_dump_addr,
578 u32 range_len, void *ptr)
580 struct iwl_fw_error_dump_prph *prph;
581 struct iwl_trans *trans = fwrt->trans;
582 struct iwl_fw_error_dump_data **data =
583 (struct iwl_fw_error_dump_data **)ptr;
590 IWL_DEBUG_INFO(trans, "WRT PRPH dump\n");
592 if (!iwl_trans_grab_nic_access(trans, &flags))
595 for (i = 0; i < range_len; i++) {
596 /* The range includes both boundaries */
597 int num_bytes_in_chunk = iwl_prph_dump_addr[i].end -
598 iwl_prph_dump_addr[i].start + 4;
600 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PRPH);
601 (*data)->len = cpu_to_le32(sizeof(*prph) +
603 prph = (void *)(*data)->data;
604 prph->prph_start = cpu_to_le32(iwl_prph_dump_addr[i].start);
606 iwl_read_prph_block(trans, iwl_prph_dump_addr[i].start,
607 /* our range is inclusive, hence + 4 */
608 iwl_prph_dump_addr[i].end -
609 iwl_prph_dump_addr[i].start + 4,
612 *data = iwl_fw_error_next_data(*data);
615 iwl_trans_release_nic_access(trans, &flags);
619 * alloc_sgtable - allocates scallerlist table in the given size,
620 * fills it with pages and returns it
621 * @size: the size (in bytes) of the table
623 static struct scatterlist *alloc_sgtable(int size)
625 int alloc_size, nents, i;
626 struct page *new_page;
627 struct scatterlist *iter;
628 struct scatterlist *table;
630 nents = DIV_ROUND_UP(size, PAGE_SIZE);
631 table = kcalloc(nents, sizeof(*table), GFP_KERNEL);
634 sg_init_table(table, nents);
636 for_each_sg(table, iter, sg_nents(table), i) {
637 new_page = alloc_page(GFP_KERNEL);
639 /* release all previous allocated pages in the table */
641 for_each_sg(table, iter, sg_nents(table), i) {
642 new_page = sg_page(iter);
644 __free_page(new_page);
648 alloc_size = min_t(int, size, PAGE_SIZE);
650 sg_set_page(iter, new_page, alloc_size, 0);
655 static void iwl_fw_get_prph_len(struct iwl_fw_runtime *fwrt,
656 const struct iwl_prph_range *iwl_prph_dump_addr,
657 u32 range_len, void *ptr)
659 u32 *prph_len = (u32 *)ptr;
660 int i, num_bytes_in_chunk;
665 for (i = 0; i < range_len; i++) {
666 /* The range includes both boundaries */
668 iwl_prph_dump_addr[i].end -
669 iwl_prph_dump_addr[i].start + 4;
671 *prph_len += sizeof(struct iwl_fw_error_dump_data) +
672 sizeof(struct iwl_fw_error_dump_prph) +
677 static void iwl_fw_prph_handler(struct iwl_fw_runtime *fwrt, void *ptr,
678 void (*handler)(struct iwl_fw_runtime *,
679 const struct iwl_prph_range *,
684 if (fwrt->trans->cfg->device_family >= IWL_DEVICE_FAMILY_AX210) {
685 range_len = ARRAY_SIZE(iwl_prph_dump_addr_ax210);
686 handler(fwrt, iwl_prph_dump_addr_ax210, range_len, ptr);
687 } else if (fwrt->trans->cfg->device_family >= IWL_DEVICE_FAMILY_22000) {
688 range_len = ARRAY_SIZE(iwl_prph_dump_addr_22000);
689 handler(fwrt, iwl_prph_dump_addr_22000, range_len, ptr);
691 range_len = ARRAY_SIZE(iwl_prph_dump_addr_comm);
692 handler(fwrt, iwl_prph_dump_addr_comm, range_len, ptr);
694 if (fwrt->trans->cfg->mq_rx_supported) {
695 range_len = ARRAY_SIZE(iwl_prph_dump_addr_9000);
696 handler(fwrt, iwl_prph_dump_addr_9000, range_len, ptr);
701 static void iwl_fw_dump_mem(struct iwl_fw_runtime *fwrt,
702 struct iwl_fw_error_dump_data **dump_data,
703 u32 len, u32 ofs, u32 type)
705 struct iwl_fw_error_dump_mem *dump_mem;
710 (*dump_data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_MEM);
711 (*dump_data)->len = cpu_to_le32(len + sizeof(*dump_mem));
712 dump_mem = (void *)(*dump_data)->data;
713 dump_mem->type = cpu_to_le32(type);
714 dump_mem->offset = cpu_to_le32(ofs);
715 iwl_trans_read_mem_bytes(fwrt->trans, ofs, dump_mem->data, len);
716 *dump_data = iwl_fw_error_next_data(*dump_data);
718 IWL_DEBUG_INFO(fwrt, "WRT memory dump. Type=%u\n", dump_mem->type);
721 #define ADD_LEN(len, item_len, const_len) \
722 do {size_t item = item_len; len += (!!item) * const_len + item; } \
725 static int iwl_fw_rxf_len(struct iwl_fw_runtime *fwrt,
726 struct iwl_fwrt_shared_mem_cfg *mem_cfg)
728 size_t hdr_len = sizeof(struct iwl_fw_error_dump_data) +
729 sizeof(struct iwl_fw_error_dump_fifo);
733 if (!iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_RXF))
736 /* Count RXF2 size */
737 ADD_LEN(fifo_len, mem_cfg->rxfifo2_size, hdr_len);
739 /* Count RXF1 sizes */
740 if (WARN_ON(mem_cfg->num_lmacs > MAX_NUM_LMAC))
741 mem_cfg->num_lmacs = MAX_NUM_LMAC;
743 for (i = 0; i < mem_cfg->num_lmacs; i++)
744 ADD_LEN(fifo_len, mem_cfg->lmac[i].rxfifo1_size, hdr_len);
749 static int iwl_fw_txf_len(struct iwl_fw_runtime *fwrt,
750 struct iwl_fwrt_shared_mem_cfg *mem_cfg)
752 size_t hdr_len = sizeof(struct iwl_fw_error_dump_data) +
753 sizeof(struct iwl_fw_error_dump_fifo);
757 if (!iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_TXF))
758 goto dump_internal_txf;
760 /* Count TXF sizes */
761 if (WARN_ON(mem_cfg->num_lmacs > MAX_NUM_LMAC))
762 mem_cfg->num_lmacs = MAX_NUM_LMAC;
764 for (i = 0; i < mem_cfg->num_lmacs; i++) {
767 for (j = 0; j < mem_cfg->num_txfifo_entries; j++)
768 ADD_LEN(fifo_len, mem_cfg->lmac[i].txfifo_size[j],
773 if (!(iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_INTERNAL_TXF) &&
774 fw_has_capa(&fwrt->fw->ucode_capa,
775 IWL_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG)))
778 for (i = 0; i < ARRAY_SIZE(mem_cfg->internal_txfifo_size); i++)
779 ADD_LEN(fifo_len, mem_cfg->internal_txfifo_size[i], hdr_len);
785 static void iwl_dump_paging(struct iwl_fw_runtime *fwrt,
786 struct iwl_fw_error_dump_data **data)
790 IWL_DEBUG_INFO(fwrt, "WRT paging dump\n");
791 for (i = 1; i < fwrt->num_of_paging_blk + 1; i++) {
792 struct iwl_fw_error_dump_paging *paging;
794 fwrt->fw_paging_db[i].fw_paging_block;
795 dma_addr_t addr = fwrt->fw_paging_db[i].fw_paging_phys;
797 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PAGING);
798 (*data)->len = cpu_to_le32(sizeof(*paging) +
800 paging = (void *)(*data)->data;
801 paging->index = cpu_to_le32(i);
802 dma_sync_single_for_cpu(fwrt->trans->dev, addr,
805 memcpy(paging->data, page_address(pages),
807 dma_sync_single_for_device(fwrt->trans->dev, addr,
810 (*data) = iwl_fw_error_next_data(*data);
814 static struct iwl_fw_error_dump_file *
815 iwl_fw_error_dump_file(struct iwl_fw_runtime *fwrt,
816 struct iwl_fw_dump_ptrs *fw_error_dump)
818 struct iwl_fw_error_dump_file *dump_file;
819 struct iwl_fw_error_dump_data *dump_data;
820 struct iwl_fw_error_dump_info *dump_info;
821 struct iwl_fw_error_dump_smem_cfg *dump_smem_cfg;
822 struct iwl_fw_error_dump_trigger_desc *dump_trig;
823 u32 sram_len, sram_ofs;
824 const struct iwl_fw_dbg_mem_seg_tlv *fw_mem = fwrt->fw->dbg.mem_tlv;
825 struct iwl_fwrt_shared_mem_cfg *mem_cfg = &fwrt->smem_cfg;
826 u32 file_len, fifo_len = 0, prph_len = 0, radio_len = 0;
827 u32 smem_len = fwrt->fw->dbg.n_mem_tlv ? 0 : fwrt->trans->cfg->smem_len;
828 u32 sram2_len = fwrt->fw->dbg.n_mem_tlv ?
829 0 : fwrt->trans->cfg->dccm2_len;
832 /* SRAM - include stack CCM if driver knows the values for it */
833 if (!fwrt->trans->cfg->dccm_offset || !fwrt->trans->cfg->dccm_len) {
834 const struct fw_img *img;
836 if (fwrt->cur_fw_img >= IWL_UCODE_TYPE_MAX)
838 img = &fwrt->fw->img[fwrt->cur_fw_img];
839 sram_ofs = img->sec[IWL_UCODE_SECTION_DATA].offset;
840 sram_len = img->sec[IWL_UCODE_SECTION_DATA].len;
842 sram_ofs = fwrt->trans->cfg->dccm_offset;
843 sram_len = fwrt->trans->cfg->dccm_len;
846 /* reading RXF/TXF sizes */
847 if (test_bit(STATUS_FW_ERROR, &fwrt->trans->status)) {
848 fifo_len = iwl_fw_rxf_len(fwrt, mem_cfg);
849 fifo_len += iwl_fw_txf_len(fwrt, mem_cfg);
851 /* Make room for PRPH registers */
852 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_PRPH))
853 iwl_fw_prph_handler(fwrt, &prph_len,
854 iwl_fw_get_prph_len);
856 if (fwrt->trans->cfg->device_family == IWL_DEVICE_FAMILY_7000 &&
857 iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_RADIO_REG))
858 radio_len = sizeof(*dump_data) + RADIO_REG_MAX_READ;
861 file_len = sizeof(*dump_file) + fifo_len + prph_len + radio_len;
863 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_DEV_FW_INFO))
864 file_len += sizeof(*dump_data) + sizeof(*dump_info);
865 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_MEM_CFG))
866 file_len += sizeof(*dump_data) + sizeof(*dump_smem_cfg);
868 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_MEM)) {
869 size_t hdr_len = sizeof(*dump_data) +
870 sizeof(struct iwl_fw_error_dump_mem);
872 /* Dump SRAM only if no mem_tlvs */
873 if (!fwrt->fw->dbg.n_mem_tlv)
874 ADD_LEN(file_len, sram_len, hdr_len);
876 /* Make room for all mem types that exist */
877 ADD_LEN(file_len, smem_len, hdr_len);
878 ADD_LEN(file_len, sram2_len, hdr_len);
880 for (i = 0; i < fwrt->fw->dbg.n_mem_tlv; i++)
881 ADD_LEN(file_len, le32_to_cpu(fw_mem[i].len), hdr_len);
884 /* Make room for fw's virtual image pages, if it exists */
885 if (iwl_fw_dbg_is_paging_enabled(fwrt))
886 file_len += fwrt->num_of_paging_blk *
887 (sizeof(*dump_data) +
888 sizeof(struct iwl_fw_error_dump_paging) +
891 if (iwl_fw_dbg_is_d3_debug_enabled(fwrt) && fwrt->dump.d3_debug_data) {
892 file_len += sizeof(*dump_data) +
893 fwrt->trans->cfg->d3_debug_data_length * 2;
896 /* If we only want a monitor dump, reset the file length */
897 if (fwrt->dump.monitor_only) {
898 file_len = sizeof(*dump_file) + sizeof(*dump_data) * 2 +
899 sizeof(*dump_info) + sizeof(*dump_smem_cfg);
902 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_ERROR_INFO) &&
904 file_len += sizeof(*dump_data) + sizeof(*dump_trig) +
905 fwrt->dump.desc->len;
907 dump_file = vzalloc(file_len);
911 fw_error_dump->fwrt_ptr = dump_file;
913 dump_file->barker = cpu_to_le32(IWL_FW_ERROR_DUMP_BARKER);
914 dump_data = (void *)dump_file->data;
916 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_DEV_FW_INFO)) {
917 dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_DEV_FW_INFO);
918 dump_data->len = cpu_to_le32(sizeof(*dump_info));
919 dump_info = (void *)dump_data->data;
921 cpu_to_le32(CSR_HW_REV_TYPE(fwrt->trans->hw_rev));
923 cpu_to_le32(CSR_HW_REV_STEP(fwrt->trans->hw_rev));
924 memcpy(dump_info->fw_human_readable, fwrt->fw->human_readable,
925 sizeof(dump_info->fw_human_readable));
926 strncpy(dump_info->dev_human_readable, fwrt->trans->cfg->name,
927 sizeof(dump_info->dev_human_readable) - 1);
928 strncpy(dump_info->bus_human_readable, fwrt->dev->bus->name,
929 sizeof(dump_info->bus_human_readable) - 1);
930 dump_info->num_of_lmacs = fwrt->smem_cfg.num_lmacs;
931 dump_info->lmac_err_id[0] =
932 cpu_to_le32(fwrt->dump.lmac_err_id[0]);
933 if (fwrt->smem_cfg.num_lmacs > 1)
934 dump_info->lmac_err_id[1] =
935 cpu_to_le32(fwrt->dump.lmac_err_id[1]);
936 dump_info->umac_err_id = cpu_to_le32(fwrt->dump.umac_err_id);
938 dump_data = iwl_fw_error_next_data(dump_data);
941 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_MEM_CFG)) {
942 /* Dump shared memory configuration */
943 dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_MEM_CFG);
944 dump_data->len = cpu_to_le32(sizeof(*dump_smem_cfg));
945 dump_smem_cfg = (void *)dump_data->data;
946 dump_smem_cfg->num_lmacs = cpu_to_le32(mem_cfg->num_lmacs);
947 dump_smem_cfg->num_txfifo_entries =
948 cpu_to_le32(mem_cfg->num_txfifo_entries);
949 for (i = 0; i < MAX_NUM_LMAC; i++) {
951 u32 *txf_size = mem_cfg->lmac[i].txfifo_size;
953 for (j = 0; j < TX_FIFO_MAX_NUM; j++)
954 dump_smem_cfg->lmac[i].txfifo_size[j] =
955 cpu_to_le32(txf_size[j]);
956 dump_smem_cfg->lmac[i].rxfifo1_size =
957 cpu_to_le32(mem_cfg->lmac[i].rxfifo1_size);
959 dump_smem_cfg->rxfifo2_size =
960 cpu_to_le32(mem_cfg->rxfifo2_size);
961 dump_smem_cfg->internal_txfifo_addr =
962 cpu_to_le32(mem_cfg->internal_txfifo_addr);
963 for (i = 0; i < TX_FIFO_INTERNAL_MAX_NUM; i++) {
964 dump_smem_cfg->internal_txfifo_size[i] =
965 cpu_to_le32(mem_cfg->internal_txfifo_size[i]);
968 dump_data = iwl_fw_error_next_data(dump_data);
971 /* We only dump the FIFOs if the FW is in error state */
973 iwl_fw_dump_rxf(fwrt, &dump_data);
974 iwl_fw_dump_txf(fwrt, &dump_data);
978 iwl_read_radio_regs(fwrt, &dump_data);
980 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_ERROR_INFO) &&
982 dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_ERROR_INFO);
983 dump_data->len = cpu_to_le32(sizeof(*dump_trig) +
984 fwrt->dump.desc->len);
985 dump_trig = (void *)dump_data->data;
986 memcpy(dump_trig, &fwrt->dump.desc->trig_desc,
987 sizeof(*dump_trig) + fwrt->dump.desc->len);
989 dump_data = iwl_fw_error_next_data(dump_data);
992 /* In case we only want monitor dump, skip to dump trasport data */
993 if (fwrt->dump.monitor_only)
996 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_MEM)) {
997 const struct iwl_fw_dbg_mem_seg_tlv *fw_dbg_mem =
998 fwrt->fw->dbg.mem_tlv;
1000 if (!fwrt->fw->dbg.n_mem_tlv)
1001 iwl_fw_dump_mem(fwrt, &dump_data, sram_len, sram_ofs,
1002 IWL_FW_ERROR_DUMP_MEM_SRAM);
1004 for (i = 0; i < fwrt->fw->dbg.n_mem_tlv; i++) {
1005 u32 len = le32_to_cpu(fw_dbg_mem[i].len);
1006 u32 ofs = le32_to_cpu(fw_dbg_mem[i].ofs);
1008 iwl_fw_dump_mem(fwrt, &dump_data, len, ofs,
1009 le32_to_cpu(fw_dbg_mem[i].data_type));
1012 iwl_fw_dump_mem(fwrt, &dump_data, smem_len,
1013 fwrt->trans->cfg->smem_offset,
1014 IWL_FW_ERROR_DUMP_MEM_SMEM);
1016 iwl_fw_dump_mem(fwrt, &dump_data, sram2_len,
1017 fwrt->trans->cfg->dccm2_offset,
1018 IWL_FW_ERROR_DUMP_MEM_SRAM);
1021 if (iwl_fw_dbg_is_d3_debug_enabled(fwrt) && fwrt->dump.d3_debug_data) {
1022 u32 addr = fwrt->trans->cfg->d3_debug_data_base_addr;
1023 size_t data_size = fwrt->trans->cfg->d3_debug_data_length;
1025 dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_D3_DEBUG_DATA);
1026 dump_data->len = cpu_to_le32(data_size * 2);
1028 memcpy(dump_data->data, fwrt->dump.d3_debug_data, data_size);
1030 kfree(fwrt->dump.d3_debug_data);
1031 fwrt->dump.d3_debug_data = NULL;
1033 iwl_trans_read_mem_bytes(fwrt->trans, addr,
1034 dump_data->data + data_size,
1037 dump_data = iwl_fw_error_next_data(dump_data);
1040 /* Dump fw's virtual image */
1041 if (iwl_fw_dbg_is_paging_enabled(fwrt))
1042 iwl_dump_paging(fwrt, &dump_data);
1045 iwl_fw_prph_handler(fwrt, &dump_data, iwl_dump_prph);
1048 dump_file->file_len = cpu_to_le32(file_len);
1052 static int iwl_dump_ini_prph_iter(struct iwl_fw_runtime *fwrt,
1053 struct iwl_fw_ini_region_cfg *reg,
1054 void *range_ptr, int idx)
1056 struct iwl_fw_ini_error_dump_range *range = range_ptr;
1057 __le32 *val = range->data;
1059 u32 addr = le32_to_cpu(reg->start_addr[idx]) + le32_to_cpu(reg->offset);
1062 range->internal_base_addr = cpu_to_le32(addr);
1063 range->range_data_size = reg->internal.range_data_size;
1064 for (i = 0; i < le32_to_cpu(reg->internal.range_data_size); i += 4) {
1065 prph_val = iwl_read_prph(fwrt->trans, addr + i);
1066 if (prph_val == 0x5a5a5a5a)
1068 *val++ = cpu_to_le32(prph_val);
1071 return sizeof(*range) + le32_to_cpu(range->range_data_size);
1074 static int iwl_dump_ini_csr_iter(struct iwl_fw_runtime *fwrt,
1075 struct iwl_fw_ini_region_cfg *reg,
1076 void *range_ptr, int idx)
1078 struct iwl_fw_ini_error_dump_range *range = range_ptr;
1079 __le32 *val = range->data;
1080 u32 addr = le32_to_cpu(reg->start_addr[idx]) + le32_to_cpu(reg->offset);
1083 range->internal_base_addr = cpu_to_le32(addr);
1084 range->range_data_size = reg->internal.range_data_size;
1085 for (i = 0; i < le32_to_cpu(reg->internal.range_data_size); i += 4)
1086 *val++ = cpu_to_le32(iwl_trans_read32(fwrt->trans, addr + i));
1088 return sizeof(*range) + le32_to_cpu(range->range_data_size);
1091 static int iwl_dump_ini_dev_mem_iter(struct iwl_fw_runtime *fwrt,
1092 struct iwl_fw_ini_region_cfg *reg,
1093 void *range_ptr, int idx)
1095 struct iwl_fw_ini_error_dump_range *range = range_ptr;
1096 u32 addr = le32_to_cpu(reg->start_addr[idx]) + le32_to_cpu(reg->offset);
1098 range->internal_base_addr = cpu_to_le32(addr);
1099 range->range_data_size = reg->internal.range_data_size;
1100 iwl_trans_read_mem_bytes(fwrt->trans, addr, range->data,
1101 le32_to_cpu(reg->internal.range_data_size));
1103 return sizeof(*range) + le32_to_cpu(range->range_data_size);
1107 iwl_dump_ini_paging_gen2_iter(struct iwl_fw_runtime *fwrt,
1108 struct iwl_fw_ini_region_cfg *reg,
1109 void *range_ptr, int idx)
1111 struct iwl_fw_ini_error_dump_range *range = range_ptr;
1112 u32 page_size = fwrt->trans->init_dram.paging[idx].size;
1114 range->page_num = cpu_to_le32(idx);
1115 range->range_data_size = cpu_to_le32(page_size);
1116 memcpy(range->data, fwrt->trans->init_dram.paging[idx].block,
1119 return sizeof(*range) + le32_to_cpu(range->range_data_size);
1122 static int iwl_dump_ini_paging_iter(struct iwl_fw_runtime *fwrt,
1123 struct iwl_fw_ini_region_cfg *reg,
1124 void *range_ptr, int idx)
1126 /* increase idx by 1 since the pages are from 1 to
1127 * fwrt->num_of_paging_blk + 1
1129 struct page *page = fwrt->fw_paging_db[++idx].fw_paging_block;
1130 struct iwl_fw_ini_error_dump_range *range = range_ptr;
1131 dma_addr_t addr = fwrt->fw_paging_db[idx].fw_paging_phys;
1132 u32 page_size = fwrt->fw_paging_db[idx].fw_paging_size;
1134 range->page_num = cpu_to_le32(idx);
1135 range->range_data_size = cpu_to_le32(page_size);
1136 dma_sync_single_for_cpu(fwrt->trans->dev, addr, page_size,
1138 memcpy(range->data, page_address(page), page_size);
1139 dma_sync_single_for_device(fwrt->trans->dev, addr, page_size,
1142 return sizeof(*range) + le32_to_cpu(range->range_data_size);
1146 iwl_dump_ini_mon_dram_iter(struct iwl_fw_runtime *fwrt,
1147 struct iwl_fw_ini_region_cfg *reg, void *range_ptr,
1150 struct iwl_fw_ini_error_dump_range *range = range_ptr;
1151 u32 start_addr = iwl_read_umac_prph(fwrt->trans,
1152 MON_BUFF_BASE_ADDR_VER2);
1154 if (start_addr == 0x5a5a5a5a)
1157 range->dram_base_addr = cpu_to_le64(start_addr);
1158 range->range_data_size = cpu_to_le32(fwrt->trans->dbg.fw_mon[idx].size);
1160 memcpy(range->data, fwrt->trans->dbg.fw_mon[idx].block,
1161 fwrt->trans->dbg.fw_mon[idx].size);
1163 return sizeof(*range) + le32_to_cpu(range->range_data_size);
1166 struct iwl_ini_txf_iter_data {
1174 static bool iwl_ini_txf_iter(struct iwl_fw_runtime *fwrt,
1175 struct iwl_fw_ini_region_cfg *reg)
1177 struct iwl_ini_txf_iter_data *iter = fwrt->dump.fifo_iter;
1178 struct iwl_fwrt_shared_mem_cfg *cfg = &fwrt->smem_cfg;
1179 int txf_num = cfg->num_txfifo_entries;
1180 int int_txf_num = ARRAY_SIZE(cfg->internal_txfifo_size);
1181 u32 lmac_bitmap = le32_to_cpu(reg->fifos.fid1);
1187 if (le32_to_cpu(reg->offset) &&
1188 WARN_ONCE(cfg->num_lmacs == 1,
1189 "Invalid lmac offset: 0x%x\n",
1190 le32_to_cpu(reg->offset)))
1194 iter->internal_txf = false;
1195 iter->fifo_size = 0;
1197 if (le32_to_cpu(reg->offset))
1203 if (!iter->internal_txf)
1204 for (iter->fifo++; iter->fifo < txf_num; iter->fifo++) {
1206 cfg->lmac[iter->lmac].txfifo_size[iter->fifo];
1207 if (iter->fifo_size && (lmac_bitmap & BIT(iter->fifo)))
1211 iter->internal_txf = true;
1213 if (!fw_has_capa(&fwrt->fw->ucode_capa,
1214 IWL_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG))
1217 for (iter->fifo++; iter->fifo < int_txf_num + txf_num; iter->fifo++) {
1219 cfg->internal_txfifo_size[iter->fifo - txf_num];
1220 if (iter->fifo_size && (lmac_bitmap & BIT(iter->fifo)))
1227 static int iwl_dump_ini_txf_iter(struct iwl_fw_runtime *fwrt,
1228 struct iwl_fw_ini_region_cfg *reg,
1229 void *range_ptr, int idx)
1231 struct iwl_fw_ini_error_dump_range *range = range_ptr;
1232 struct iwl_ini_txf_iter_data *iter;
1233 struct iwl_fw_ini_error_dump_register *reg_dump = (void *)range->data;
1234 u32 offs = le32_to_cpu(reg->offset), addr;
1235 u32 registers_size =
1236 le32_to_cpu(reg->fifos.num_of_registers) * sizeof(*reg_dump);
1238 unsigned long flags;
1241 if (!iwl_ini_txf_iter(fwrt, reg))
1244 if (!iwl_trans_grab_nic_access(fwrt->trans, &flags))
1247 iter = fwrt->dump.fifo_iter;
1249 range->fifo_hdr.fifo_num = cpu_to_le32(iter->fifo);
1250 range->fifo_hdr.num_of_registers = reg->fifos.num_of_registers;
1251 range->range_data_size = cpu_to_le32(iter->fifo_size + registers_size);
1253 iwl_write_prph_no_grab(fwrt->trans, TXF_LARC_NUM + offs, iter->fifo);
1256 * read txf registers. for each register, write to the dump the
1257 * register address and its value
1259 for (i = 0; i < le32_to_cpu(reg->fifos.num_of_registers); i++) {
1260 addr = le32_to_cpu(reg->start_addr[i]) + offs;
1262 reg_dump->addr = cpu_to_le32(addr);
1263 reg_dump->data = cpu_to_le32(iwl_read_prph_no_grab(fwrt->trans,
1269 if (reg->fifos.header_only) {
1270 range->range_data_size = cpu_to_le32(registers_size);
1274 /* Set the TXF_READ_MODIFY_ADDR to TXF_WR_PTR */
1275 iwl_write_prph_no_grab(fwrt->trans, TXF_READ_MODIFY_ADDR + offs,
1278 /* Dummy-read to advance the read pointer to the head */
1279 iwl_read_prph_no_grab(fwrt->trans, TXF_READ_MODIFY_DATA + offs);
1282 addr = TXF_READ_MODIFY_DATA + offs;
1283 data = (void *)reg_dump;
1284 for (i = 0; i < iter->fifo_size; i += sizeof(*data))
1285 *data++ = cpu_to_le32(iwl_read_prph_no_grab(fwrt->trans, addr));
1288 iwl_trans_release_nic_access(fwrt->trans, &flags);
1290 return sizeof(*range) + le32_to_cpu(range->range_data_size);
1293 struct iwl_ini_rxf_data {
1299 static void iwl_ini_get_rxf_data(struct iwl_fw_runtime *fwrt,
1300 struct iwl_fw_ini_region_cfg *reg,
1301 struct iwl_ini_rxf_data *data)
1303 u32 fid1 = le32_to_cpu(reg->fifos.fid1);
1304 u32 fid2 = le32_to_cpu(reg->fifos.fid2);
1310 memset(data, 0, sizeof(*data));
1312 if (WARN_ON_ONCE((fid1 && fid2) || (!fid1 && !fid2)))
1315 fifo_idx = ffs(fid1) - 1;
1316 if (fid1 && !WARN_ON_ONCE((~BIT(fifo_idx) & fid1) ||
1317 fifo_idx >= MAX_NUM_LMAC)) {
1318 data->size = fwrt->smem_cfg.lmac[fifo_idx].rxfifo1_size;
1319 data->fifo_num = fifo_idx;
1323 fifo_idx = ffs(fid2) - 1;
1324 if (fid2 && !WARN_ON_ONCE(fifo_idx != 0)) {
1325 data->size = fwrt->smem_cfg.rxfifo2_size;
1326 data->offset = RXF_DIFF_FROM_PREV;
1327 /* use bit 31 to distinguish between umac and lmac rxf while
1330 data->fifo_num = fifo_idx | IWL_RXF_UMAC_BIT;
1335 static int iwl_dump_ini_rxf_iter(struct iwl_fw_runtime *fwrt,
1336 struct iwl_fw_ini_region_cfg *reg,
1337 void *range_ptr, int idx)
1339 struct iwl_fw_ini_error_dump_range *range = range_ptr;
1340 struct iwl_ini_rxf_data rxf_data;
1341 struct iwl_fw_ini_error_dump_register *reg_dump = (void *)range->data;
1342 u32 offs = le32_to_cpu(reg->offset), addr;
1343 u32 registers_size =
1344 le32_to_cpu(reg->fifos.num_of_registers) * sizeof(*reg_dump);
1346 unsigned long flags;
1349 iwl_ini_get_rxf_data(fwrt, reg, &rxf_data);
1353 if (!iwl_trans_grab_nic_access(fwrt->trans, &flags))
1356 range->fifo_hdr.fifo_num = cpu_to_le32(rxf_data.fifo_num);
1357 range->fifo_hdr.num_of_registers = reg->fifos.num_of_registers;
1358 range->range_data_size = cpu_to_le32(rxf_data.size + registers_size);
1361 * read rxf registers. for each register, write to the dump the
1362 * register address and its value
1364 for (i = 0; i < le32_to_cpu(reg->fifos.num_of_registers); i++) {
1365 addr = le32_to_cpu(reg->start_addr[i]) + offs;
1367 reg_dump->addr = cpu_to_le32(addr);
1368 reg_dump->data = cpu_to_le32(iwl_read_prph_no_grab(fwrt->trans,
1374 if (reg->fifos.header_only) {
1375 range->range_data_size = cpu_to_le32(registers_size);
1380 * region register have absolute value so apply rxf offset after
1381 * reading the registers
1383 offs += rxf_data.offset;
1386 iwl_write_prph_no_grab(fwrt->trans, RXF_SET_FENCE_MODE + offs, 0x1);
1387 /* Set fence pointer to the same place like WR pointer */
1388 iwl_write_prph_no_grab(fwrt->trans, RXF_LD_WR2FENCE + offs, 0x1);
1389 /* Set fence offset */
1390 iwl_write_prph_no_grab(fwrt->trans, RXF_LD_FENCE_OFFSET_ADDR + offs,
1394 addr = RXF_FIFO_RD_FENCE_INC + offs;
1395 data = (void *)reg_dump;
1396 for (i = 0; i < rxf_data.size; i += sizeof(*data))
1397 *data++ = cpu_to_le32(iwl_read_prph_no_grab(fwrt->trans, addr));
1400 iwl_trans_release_nic_access(fwrt->trans, &flags);
1402 return sizeof(*range) + le32_to_cpu(range->range_data_size);
1405 static void *iwl_dump_ini_mem_fill_header(struct iwl_fw_runtime *fwrt,
1406 struct iwl_fw_ini_region_cfg *reg,
1409 struct iwl_fw_ini_error_dump *dump = data;
1411 dump->header.version = cpu_to_le32(IWL_INI_DUMP_VER);
1413 return dump->ranges;
1417 *iwl_dump_ini_mon_fill_header(struct iwl_fw_runtime *fwrt,
1418 struct iwl_fw_ini_region_cfg *reg,
1419 struct iwl_fw_ini_monitor_dump *data,
1420 u32 write_ptr_addr, u32 write_ptr_msk,
1421 u32 cycle_cnt_addr, u32 cycle_cnt_msk)
1423 u32 write_ptr, cycle_cnt;
1424 unsigned long flags;
1426 if (!iwl_trans_grab_nic_access(fwrt->trans, &flags)) {
1427 IWL_ERR(fwrt, "Failed to get monitor header\n");
1431 write_ptr = iwl_read_prph_no_grab(fwrt->trans, write_ptr_addr);
1432 cycle_cnt = iwl_read_prph_no_grab(fwrt->trans, cycle_cnt_addr);
1434 iwl_trans_release_nic_access(fwrt->trans, &flags);
1436 data->header.version = cpu_to_le32(IWL_INI_DUMP_VER);
1437 data->write_ptr = cpu_to_le32(write_ptr & write_ptr_msk);
1438 data->cycle_cnt = cpu_to_le32(cycle_cnt & cycle_cnt_msk);
1440 return data->ranges;
1444 *iwl_dump_ini_mon_dram_fill_header(struct iwl_fw_runtime *fwrt,
1445 struct iwl_fw_ini_region_cfg *reg,
1448 struct iwl_fw_ini_monitor_dump *mon_dump = (void *)data;
1449 u32 write_ptr_addr, write_ptr_msk, cycle_cnt_addr, cycle_cnt_msk;
1451 switch (fwrt->trans->cfg->device_family) {
1452 case IWL_DEVICE_FAMILY_9000:
1453 case IWL_DEVICE_FAMILY_22000:
1454 write_ptr_addr = MON_BUFF_WRPTR_VER2;
1456 cycle_cnt_addr = MON_BUFF_CYCLE_CNT_VER2;
1460 IWL_ERR(fwrt, "Unsupported device family %d\n",
1461 fwrt->trans->cfg->device_family);
1465 return iwl_dump_ini_mon_fill_header(fwrt, reg, mon_dump, write_ptr_addr,
1466 write_ptr_msk, cycle_cnt_addr,
1471 *iwl_dump_ini_mon_smem_fill_header(struct iwl_fw_runtime *fwrt,
1472 struct iwl_fw_ini_region_cfg *reg,
1475 struct iwl_fw_ini_monitor_dump *mon_dump = (void *)data;
1476 const struct iwl_cfg *cfg = fwrt->trans->cfg;
1478 if (fwrt->trans->cfg->device_family != IWL_DEVICE_FAMILY_9000 &&
1479 fwrt->trans->cfg->device_family != IWL_DEVICE_FAMILY_22000) {
1480 IWL_ERR(fwrt, "Unsupported device family %d\n",
1481 fwrt->trans->cfg->device_family);
1485 return iwl_dump_ini_mon_fill_header(fwrt, reg, mon_dump,
1486 cfg->fw_mon_smem_write_ptr_addr,
1487 cfg->fw_mon_smem_write_ptr_msk,
1488 cfg->fw_mon_smem_cycle_cnt_ptr_addr,
1489 cfg->fw_mon_smem_cycle_cnt_ptr_msk);
1493 static u32 iwl_dump_ini_mem_ranges(struct iwl_fw_runtime *fwrt,
1494 struct iwl_fw_ini_region_cfg *reg)
1496 return le32_to_cpu(reg->internal.num_of_ranges);
1499 static u32 iwl_dump_ini_paging_gen2_ranges(struct iwl_fw_runtime *fwrt,
1500 struct iwl_fw_ini_region_cfg *reg)
1502 return fwrt->trans->init_dram.paging_cnt;
1505 static u32 iwl_dump_ini_paging_ranges(struct iwl_fw_runtime *fwrt,
1506 struct iwl_fw_ini_region_cfg *reg)
1508 return fwrt->num_of_paging_blk;
1511 static u32 iwl_dump_ini_mon_dram_ranges(struct iwl_fw_runtime *fwrt,
1512 struct iwl_fw_ini_region_cfg *reg)
1517 static u32 iwl_dump_ini_txf_ranges(struct iwl_fw_runtime *fwrt,
1518 struct iwl_fw_ini_region_cfg *reg)
1520 struct iwl_ini_txf_iter_data iter = { .init = true };
1521 void *fifo_iter = fwrt->dump.fifo_iter;
1522 u32 num_of_fifos = 0;
1524 fwrt->dump.fifo_iter = &iter;
1525 while (iwl_ini_txf_iter(fwrt, reg))
1528 fwrt->dump.fifo_iter = fifo_iter;
1530 return num_of_fifos;
1533 static u32 iwl_dump_ini_rxf_ranges(struct iwl_fw_runtime *fwrt,
1534 struct iwl_fw_ini_region_cfg *reg)
1536 /* Each Rx fifo needs a different offset and therefore, it's
1537 * region can contain only one fifo, i.e. 1 memory range.
1542 static u32 iwl_dump_ini_mem_get_size(struct iwl_fw_runtime *fwrt,
1543 struct iwl_fw_ini_region_cfg *reg)
1545 return sizeof(struct iwl_fw_ini_error_dump) +
1546 iwl_dump_ini_mem_ranges(fwrt, reg) *
1547 (sizeof(struct iwl_fw_ini_error_dump_range) +
1548 le32_to_cpu(reg->internal.range_data_size));
1551 static u32 iwl_dump_ini_paging_gen2_get_size(struct iwl_fw_runtime *fwrt,
1552 struct iwl_fw_ini_region_cfg *reg)
1555 u32 range_header_len = sizeof(struct iwl_fw_ini_error_dump_range);
1556 u32 size = sizeof(struct iwl_fw_ini_error_dump);
1558 for (i = 0; i < iwl_dump_ini_paging_gen2_ranges(fwrt, reg); i++)
1559 size += range_header_len +
1560 fwrt->trans->init_dram.paging[i].size;
1565 static u32 iwl_dump_ini_paging_get_size(struct iwl_fw_runtime *fwrt,
1566 struct iwl_fw_ini_region_cfg *reg)
1569 u32 range_header_len = sizeof(struct iwl_fw_ini_error_dump_range);
1570 u32 size = sizeof(struct iwl_fw_ini_error_dump);
1572 for (i = 1; i <= iwl_dump_ini_paging_ranges(fwrt, reg); i++)
1573 size += range_header_len + fwrt->fw_paging_db[i].fw_paging_size;
1578 static u32 iwl_dump_ini_mon_dram_get_size(struct iwl_fw_runtime *fwrt,
1579 struct iwl_fw_ini_region_cfg *reg)
1581 u32 size = sizeof(struct iwl_fw_ini_monitor_dump) +
1582 sizeof(struct iwl_fw_ini_error_dump_range);
1584 if (fwrt->trans->dbg.num_blocks)
1585 size += fwrt->trans->dbg.fw_mon[0].size;
1590 static u32 iwl_dump_ini_mon_smem_get_size(struct iwl_fw_runtime *fwrt,
1591 struct iwl_fw_ini_region_cfg *reg)
1593 return sizeof(struct iwl_fw_ini_monitor_dump) +
1594 iwl_dump_ini_mem_ranges(fwrt, reg) *
1595 (sizeof(struct iwl_fw_ini_error_dump_range) +
1596 le32_to_cpu(reg->internal.range_data_size));
1599 static u32 iwl_dump_ini_txf_get_size(struct iwl_fw_runtime *fwrt,
1600 struct iwl_fw_ini_region_cfg *reg)
1602 struct iwl_ini_txf_iter_data iter = { .init = true };
1603 void *fifo_iter = fwrt->dump.fifo_iter;
1605 u32 fifo_hdr = sizeof(struct iwl_fw_ini_error_dump_range) +
1606 le32_to_cpu(reg->fifos.num_of_registers) *
1607 sizeof(struct iwl_fw_ini_error_dump_register);
1609 fwrt->dump.fifo_iter = &iter;
1610 while (iwl_ini_txf_iter(fwrt, reg)) {
1612 if (!reg->fifos.header_only)
1613 size += iter.fifo_size;
1617 size += sizeof(struct iwl_fw_ini_error_dump);
1619 fwrt->dump.fifo_iter = fifo_iter;
1624 static u32 iwl_dump_ini_rxf_get_size(struct iwl_fw_runtime *fwrt,
1625 struct iwl_fw_ini_region_cfg *reg)
1627 struct iwl_ini_rxf_data rx_data;
1628 u32 size = sizeof(struct iwl_fw_ini_error_dump) +
1629 sizeof(struct iwl_fw_ini_error_dump_range) +
1630 le32_to_cpu(reg->fifos.num_of_registers) *
1631 sizeof(struct iwl_fw_ini_error_dump_register);
1633 if (reg->fifos.header_only)
1636 iwl_ini_get_rxf_data(fwrt, reg, &rx_data);
1637 size += rx_data.size;
1643 * struct iwl_dump_ini_mem_ops - ini memory dump operations
1644 * @get_num_of_ranges: returns the number of memory ranges in the region.
1645 * @get_size: returns the total size of the region.
1646 * @fill_mem_hdr: fills region type specific headers and returns pointer to
1647 * the first range or NULL if failed to fill headers.
1648 * @fill_range: copies a given memory range into the dump.
1649 * Returns the size of the range or negative error value otherwise.
1651 struct iwl_dump_ini_mem_ops {
1652 u32 (*get_num_of_ranges)(struct iwl_fw_runtime *fwrt,
1653 struct iwl_fw_ini_region_cfg *reg);
1654 u32 (*get_size)(struct iwl_fw_runtime *fwrt,
1655 struct iwl_fw_ini_region_cfg *reg);
1656 void *(*fill_mem_hdr)(struct iwl_fw_runtime *fwrt,
1657 struct iwl_fw_ini_region_cfg *reg, void *data);
1658 int (*fill_range)(struct iwl_fw_runtime *fwrt,
1659 struct iwl_fw_ini_region_cfg *reg, void *range,
1664 * iwl_dump_ini_mem - copy a memory region into the dump
1665 * @fwrt: fw runtime struct.
1666 * @data: dump memory data.
1667 * @reg: region to copy to the dump.
1668 * @ops: memory dump operations.
1671 iwl_dump_ini_mem(struct iwl_fw_runtime *fwrt,
1672 struct iwl_fw_error_dump_data **data,
1673 struct iwl_fw_ini_region_cfg *reg,
1674 struct iwl_dump_ini_mem_ops *ops)
1676 struct iwl_fw_ini_error_dump_header *header = (void *)(*data)->data;
1677 u32 num_of_ranges, i, type = le32_to_cpu(reg->region_type), size;
1680 if (WARN_ON(!ops || !ops->get_num_of_ranges || !ops->get_size ||
1681 !ops->fill_mem_hdr || !ops->fill_range))
1684 size = ops->get_size(fwrt, reg);
1688 IWL_DEBUG_FW(fwrt, "WRT: collecting region: id=%d, type=%d\n",
1689 le32_to_cpu(reg->region_id), type);
1691 num_of_ranges = ops->get_num_of_ranges(fwrt, reg);
1693 (*data)->type = cpu_to_le32(type);
1694 (*data)->len = cpu_to_le32(size);
1696 header->region_id = reg->region_id;
1697 header->num_of_ranges = cpu_to_le32(num_of_ranges);
1698 header->name_len = cpu_to_le32(min_t(int, IWL_FW_INI_MAX_NAME,
1699 le32_to_cpu(reg->name_len)));
1700 memcpy(header->name, reg->name, le32_to_cpu(header->name_len));
1702 range = ops->fill_mem_hdr(fwrt, reg, header);
1705 "WRT: failed to fill region header: id=%d, type=%d\n",
1706 le32_to_cpu(reg->region_id), type);
1707 memset(*data, 0, size);
1711 for (i = 0; i < num_of_ranges; i++) {
1712 int range_size = ops->fill_range(fwrt, reg, range, i);
1714 if (range_size < 0) {
1716 "WRT: failed to dump region: id=%d, type=%d\n",
1717 le32_to_cpu(reg->region_id), type);
1718 memset(*data, 0, size);
1721 range = range + range_size;
1723 *data = iwl_fw_error_next_data(*data);
1726 static void iwl_dump_ini_info(struct iwl_fw_runtime *fwrt,
1727 struct iwl_fw_ini_trigger *trigger,
1728 struct iwl_fw_error_dump_data **data)
1730 struct iwl_fw_ini_dump_info *dump = (void *)(*data)->data;
1731 u32 reg_ids_size = le32_to_cpu(trigger->num_regions) * sizeof(__le32);
1733 (*data)->type = cpu_to_le32(IWL_INI_DUMP_INFO_TYPE);
1734 (*data)->len = cpu_to_le32(sizeof(*dump) + reg_ids_size);
1736 dump->version = cpu_to_le32(IWL_INI_DUMP_VER);
1737 dump->trigger_id = trigger->trigger_id;
1738 dump->is_external_cfg =
1739 cpu_to_le32(fwrt->trans->dbg.external_ini_loaded);
1741 dump->ver_type = cpu_to_le32(fwrt->dump.fw_ver.type);
1742 dump->ver_subtype = cpu_to_le32(fwrt->dump.fw_ver.subtype);
1744 dump->hw_step = cpu_to_le32(CSR_HW_REV_STEP(fwrt->trans->hw_rev));
1745 dump->hw_type = cpu_to_le32(CSR_HW_REV_TYPE(fwrt->trans->hw_rev));
1747 dump->rf_id_flavor =
1748 cpu_to_le32(CSR_HW_RFID_FLAVOR(fwrt->trans->hw_rf_id));
1749 dump->rf_id_dash = cpu_to_le32(CSR_HW_RFID_DASH(fwrt->trans->hw_rf_id));
1750 dump->rf_id_step = cpu_to_le32(CSR_HW_RFID_STEP(fwrt->trans->hw_rf_id));
1751 dump->rf_id_type = cpu_to_le32(CSR_HW_RFID_TYPE(fwrt->trans->hw_rf_id));
1753 dump->lmac_major = cpu_to_le32(fwrt->dump.fw_ver.lmac_major);
1754 dump->lmac_minor = cpu_to_le32(fwrt->dump.fw_ver.lmac_minor);
1755 dump->umac_major = cpu_to_le32(fwrt->dump.fw_ver.umac_major);
1756 dump->umac_minor = cpu_to_le32(fwrt->dump.fw_ver.umac_minor);
1758 dump->build_tag_len = cpu_to_le32(sizeof(dump->build_tag));
1759 memcpy(dump->build_tag, fwrt->fw->human_readable,
1760 sizeof(dump->build_tag));
1762 dump->img_name_len = cpu_to_le32(sizeof(dump->img_name));
1763 memcpy(dump->img_name, fwrt->dump.img_name, sizeof(dump->img_name));
1765 dump->internal_dbg_cfg_name_len =
1766 cpu_to_le32(sizeof(dump->internal_dbg_cfg_name));
1767 memcpy(dump->internal_dbg_cfg_name, fwrt->dump.internal_dbg_cfg_name,
1768 sizeof(dump->internal_dbg_cfg_name));
1770 dump->external_dbg_cfg_name_len =
1771 cpu_to_le32(sizeof(dump->external_dbg_cfg_name));
1773 /* dump info size is allocated in iwl_fw_ini_get_trigger_len.
1774 * The driver allocates (sizeof(*dump) + reg_ids_size) so it is safe to
1777 memcpy(dump->external_dbg_cfg_name, fwrt->dump.external_dbg_cfg_name,
1778 sizeof(dump->external_dbg_cfg_name));
1780 dump->regions_num = trigger->num_regions;
1781 memcpy(dump->region_ids, trigger->data, reg_ids_size);
1783 *data = iwl_fw_error_next_data(*data);
1786 static int iwl_fw_ini_get_trigger_len(struct iwl_fw_runtime *fwrt,
1787 struct iwl_fw_ini_trigger *trigger)
1789 int i, ret_size = 0, hdr_len = sizeof(struct iwl_fw_error_dump_data);
1792 if (!trigger || !trigger->num_regions)
1795 for (i = 0; i < le32_to_cpu(trigger->num_regions); i++) {
1796 u32 reg_id = le32_to_cpu(trigger->data[i]);
1797 struct iwl_fw_ini_region_cfg *reg;
1799 if (WARN_ON(reg_id >= ARRAY_SIZE(fwrt->dump.active_regs)))
1802 reg = fwrt->dump.active_regs[reg_id];
1805 "WRT: unassigned region id %d, skipping\n",
1810 /* currently the driver supports always on domain only */
1811 if (le32_to_cpu(reg->domain) != IWL_FW_INI_DBG_DOMAIN_ALWAYS_ON)
1814 switch (le32_to_cpu(reg->region_type)) {
1815 case IWL_FW_INI_REGION_DEVICE_MEMORY:
1816 case IWL_FW_INI_REGION_PERIPHERY_MAC:
1817 case IWL_FW_INI_REGION_PERIPHERY_PHY:
1818 case IWL_FW_INI_REGION_PERIPHERY_AUX:
1819 case IWL_FW_INI_REGION_CSR:
1820 case IWL_FW_INI_REGION_LMAC_ERROR_TABLE:
1821 case IWL_FW_INI_REGION_UMAC_ERROR_TABLE:
1822 size = iwl_dump_ini_mem_get_size(fwrt, reg);
1824 ret_size += hdr_len + size;
1826 case IWL_FW_INI_REGION_TXF:
1827 size = iwl_dump_ini_txf_get_size(fwrt, reg);
1829 ret_size += hdr_len + size;
1831 case IWL_FW_INI_REGION_RXF:
1832 size = iwl_dump_ini_rxf_get_size(fwrt, reg);
1834 ret_size += hdr_len + size;
1836 case IWL_FW_INI_REGION_PAGING:
1837 if (iwl_fw_dbg_is_paging_enabled(fwrt))
1838 size = iwl_dump_ini_paging_get_size(fwrt, reg);
1840 size = iwl_dump_ini_paging_gen2_get_size(fwrt,
1843 ret_size += hdr_len + size;
1845 case IWL_FW_INI_REGION_DRAM_BUFFER:
1846 if (!fwrt->trans->dbg.num_blocks)
1848 size = iwl_dump_ini_mon_dram_get_size(fwrt, reg);
1850 ret_size += hdr_len + size;
1852 case IWL_FW_INI_REGION_INTERNAL_BUFFER:
1853 size = iwl_dump_ini_mon_smem_get_size(fwrt, reg);
1855 ret_size += hdr_len + size;
1857 case IWL_FW_INI_REGION_DRAM_IMR:
1864 /* add dump info size */
1866 ret_size += hdr_len + sizeof(struct iwl_fw_ini_dump_info) +
1867 (le32_to_cpu(trigger->num_regions) * sizeof(__le32));
1872 static void iwl_fw_ini_dump_trigger(struct iwl_fw_runtime *fwrt,
1873 struct iwl_fw_ini_trigger *trigger,
1874 struct iwl_fw_error_dump_data **data)
1876 int i, num = le32_to_cpu(trigger->num_regions);
1878 iwl_dump_ini_info(fwrt, trigger, data);
1880 for (i = 0; i < num; i++) {
1881 u32 reg_id = le32_to_cpu(trigger->data[i]);
1882 struct iwl_fw_ini_region_cfg *reg;
1883 struct iwl_dump_ini_mem_ops ops;
1885 if (reg_id >= ARRAY_SIZE(fwrt->dump.active_regs))
1888 reg = fwrt->dump.active_regs[reg_id];
1889 /* Don't warn, get_trigger_len already warned */
1893 /* currently the driver supports always on domain only */
1894 if (le32_to_cpu(reg->domain) != IWL_FW_INI_DBG_DOMAIN_ALWAYS_ON)
1897 switch (le32_to_cpu(reg->region_type)) {
1898 case IWL_FW_INI_REGION_DEVICE_MEMORY:
1899 case IWL_FW_INI_REGION_LMAC_ERROR_TABLE:
1900 case IWL_FW_INI_REGION_UMAC_ERROR_TABLE:
1901 ops.get_num_of_ranges = iwl_dump_ini_mem_ranges;
1902 ops.get_size = iwl_dump_ini_mem_get_size;
1903 ops.fill_mem_hdr = iwl_dump_ini_mem_fill_header;
1904 ops.fill_range = iwl_dump_ini_dev_mem_iter;
1905 iwl_dump_ini_mem(fwrt, data, reg, &ops);
1907 case IWL_FW_INI_REGION_PERIPHERY_MAC:
1908 case IWL_FW_INI_REGION_PERIPHERY_PHY:
1909 case IWL_FW_INI_REGION_PERIPHERY_AUX:
1910 ops.get_num_of_ranges = iwl_dump_ini_mem_ranges;
1911 ops.get_size = iwl_dump_ini_mem_get_size;
1912 ops.fill_mem_hdr = iwl_dump_ini_mem_fill_header;
1913 ops.fill_range = iwl_dump_ini_prph_iter;
1914 iwl_dump_ini_mem(fwrt, data, reg, &ops);
1916 case IWL_FW_INI_REGION_DRAM_BUFFER:
1917 ops.get_num_of_ranges = iwl_dump_ini_mon_dram_ranges;
1918 ops.get_size = iwl_dump_ini_mon_dram_get_size;
1919 ops.fill_mem_hdr = iwl_dump_ini_mon_dram_fill_header;
1920 ops.fill_range = iwl_dump_ini_mon_dram_iter;
1921 iwl_dump_ini_mem(fwrt, data, reg, &ops);
1923 case IWL_FW_INI_REGION_INTERNAL_BUFFER:
1924 ops.get_num_of_ranges = iwl_dump_ini_mem_ranges;
1925 ops.get_size = iwl_dump_ini_mon_smem_get_size;
1926 ops.fill_mem_hdr = iwl_dump_ini_mon_smem_fill_header;
1927 ops.fill_range = iwl_dump_ini_dev_mem_iter;
1928 iwl_dump_ini_mem(fwrt, data, reg, &ops);
1930 case IWL_FW_INI_REGION_PAGING:
1931 ops.fill_mem_hdr = iwl_dump_ini_mem_fill_header;
1932 if (iwl_fw_dbg_is_paging_enabled(fwrt)) {
1933 ops.get_num_of_ranges =
1934 iwl_dump_ini_paging_ranges;
1935 ops.get_size = iwl_dump_ini_paging_get_size;
1936 ops.fill_range = iwl_dump_ini_paging_iter;
1938 ops.get_num_of_ranges =
1939 iwl_dump_ini_paging_gen2_ranges;
1941 iwl_dump_ini_paging_gen2_get_size;
1942 ops.fill_range = iwl_dump_ini_paging_gen2_iter;
1945 iwl_dump_ini_mem(fwrt, data, reg, &ops);
1947 case IWL_FW_INI_REGION_TXF: {
1948 struct iwl_ini_txf_iter_data iter = { .init = true };
1949 void *fifo_iter = fwrt->dump.fifo_iter;
1951 fwrt->dump.fifo_iter = &iter;
1952 ops.get_num_of_ranges = iwl_dump_ini_txf_ranges;
1953 ops.get_size = iwl_dump_ini_txf_get_size;
1954 ops.fill_mem_hdr = iwl_dump_ini_mem_fill_header;
1955 ops.fill_range = iwl_dump_ini_txf_iter;
1956 iwl_dump_ini_mem(fwrt, data, reg, &ops);
1957 fwrt->dump.fifo_iter = fifo_iter;
1960 case IWL_FW_INI_REGION_RXF:
1961 ops.get_num_of_ranges = iwl_dump_ini_rxf_ranges;
1962 ops.get_size = iwl_dump_ini_rxf_get_size;
1963 ops.fill_mem_hdr = iwl_dump_ini_mem_fill_header;
1964 ops.fill_range = iwl_dump_ini_rxf_iter;
1965 iwl_dump_ini_mem(fwrt, data, reg, &ops);
1967 case IWL_FW_INI_REGION_CSR:
1968 ops.get_num_of_ranges = iwl_dump_ini_mem_ranges;
1969 ops.get_size = iwl_dump_ini_mem_get_size;
1970 ops.fill_mem_hdr = iwl_dump_ini_mem_fill_header;
1971 ops.fill_range = iwl_dump_ini_csr_iter;
1972 iwl_dump_ini_mem(fwrt, data, reg, &ops);
1974 case IWL_FW_INI_REGION_DRAM_IMR:
1975 /* This is undefined yet */
1982 static struct iwl_fw_error_dump_file *
1983 iwl_fw_error_ini_dump_file(struct iwl_fw_runtime *fwrt,
1984 enum iwl_fw_ini_trigger_id trig_id)
1987 struct iwl_fw_error_dump_data *dump_data;
1988 struct iwl_fw_error_dump_file *dump_file;
1989 struct iwl_fw_ini_trigger *trigger;
1991 if (!iwl_fw_ini_trigger_on(fwrt, trig_id))
1994 trigger = fwrt->dump.active_trigs[trig_id].trig;
1996 size = iwl_fw_ini_get_trigger_len(fwrt, trigger);
2000 size += sizeof(*dump_file);
2002 dump_file = vzalloc(size);
2006 dump_file->barker = cpu_to_le32(IWL_FW_INI_ERROR_DUMP_BARKER);
2007 dump_data = (void *)dump_file->data;
2008 dump_file->file_len = cpu_to_le32(size);
2010 iwl_fw_ini_dump_trigger(fwrt, trigger, &dump_data);
2015 static void iwl_fw_error_dump(struct iwl_fw_runtime *fwrt)
2017 struct iwl_fw_dump_ptrs fw_error_dump = {};
2018 struct iwl_fw_error_dump_file *dump_file;
2019 struct scatterlist *sg_dump_data;
2021 u32 dump_mask = fwrt->fw->dbg.dump_mask;
2023 dump_file = iwl_fw_error_dump_file(fwrt, &fw_error_dump);
2027 if (fwrt->dump.monitor_only)
2028 dump_mask &= IWL_FW_ERROR_DUMP_FW_MONITOR;
2030 fw_error_dump.trans_ptr = iwl_trans_dump_data(fwrt->trans, dump_mask);
2031 file_len = le32_to_cpu(dump_file->file_len);
2032 fw_error_dump.fwrt_len = file_len;
2034 if (fw_error_dump.trans_ptr) {
2035 file_len += fw_error_dump.trans_ptr->len;
2036 dump_file->file_len = cpu_to_le32(file_len);
2039 sg_dump_data = alloc_sgtable(file_len);
2041 sg_pcopy_from_buffer(sg_dump_data,
2042 sg_nents(sg_dump_data),
2043 fw_error_dump.fwrt_ptr,
2044 fw_error_dump.fwrt_len, 0);
2045 if (fw_error_dump.trans_ptr)
2046 sg_pcopy_from_buffer(sg_dump_data,
2047 sg_nents(sg_dump_data),
2048 fw_error_dump.trans_ptr->data,
2049 fw_error_dump.trans_ptr->len,
2050 fw_error_dump.fwrt_len);
2051 dev_coredumpsg(fwrt->trans->dev, sg_dump_data, file_len,
2054 vfree(fw_error_dump.fwrt_ptr);
2055 vfree(fw_error_dump.trans_ptr);
2058 iwl_fw_free_dump_desc(fwrt);
2061 static void iwl_fw_error_ini_dump(struct iwl_fw_runtime *fwrt, u8 wk_idx)
2063 enum iwl_fw_ini_trigger_id trig_id = fwrt->dump.wks[wk_idx].ini_trig_id;
2064 struct iwl_fw_error_dump_file *dump_file;
2065 struct scatterlist *sg_dump_data;
2068 dump_file = iwl_fw_error_ini_dump_file(fwrt, trig_id);
2072 file_len = le32_to_cpu(dump_file->file_len);
2074 sg_dump_data = alloc_sgtable(file_len);
2076 sg_pcopy_from_buffer(sg_dump_data, sg_nents(sg_dump_data),
2077 dump_file, file_len, 0);
2078 dev_coredumpsg(fwrt->trans->dev, sg_dump_data, file_len,
2083 fwrt->dump.wks[wk_idx].ini_trig_id = IWL_FW_TRIGGER_ID_INVALID;
2086 const struct iwl_fw_dump_desc iwl_dump_desc_assert = {
2088 .type = cpu_to_le32(FW_DBG_TRIGGER_FW_ASSERT),
2091 IWL_EXPORT_SYMBOL(iwl_dump_desc_assert);
2093 int iwl_fw_dbg_collect_desc(struct iwl_fw_runtime *fwrt,
2094 const struct iwl_fw_dump_desc *desc,
2098 u32 trig_type = le32_to_cpu(desc->trig_desc.type);
2101 if (fwrt->trans->dbg.ini_valid) {
2102 ret = iwl_fw_dbg_ini_collect(fwrt, trig_type);
2104 iwl_fw_free_dump_desc(fwrt);
2109 /* use wks[0] since dump flow prior to ini does not need to support
2110 * consecutive triggers collection
2112 if (test_and_set_bit(fwrt->dump.wks[0].idx, &fwrt->dump.active_wks))
2115 if (WARN_ON(fwrt->dump.desc))
2116 iwl_fw_free_dump_desc(fwrt);
2118 IWL_WARN(fwrt, "Collecting data: trigger %d fired.\n",
2119 le32_to_cpu(desc->trig_desc.type));
2121 fwrt->dump.desc = desc;
2122 fwrt->dump.monitor_only = monitor_only;
2124 schedule_delayed_work(&fwrt->dump.wks[0].wk, usecs_to_jiffies(delay));
2128 IWL_EXPORT_SYMBOL(iwl_fw_dbg_collect_desc);
2130 int iwl_fw_dbg_error_collect(struct iwl_fw_runtime *fwrt,
2131 enum iwl_fw_dbg_trigger trig_type)
2134 struct iwl_fw_dump_desc *iwl_dump_error_desc;
2136 if (!test_bit(STATUS_DEVICE_ENABLED, &fwrt->trans->status))
2139 iwl_dump_error_desc = kmalloc(sizeof(*iwl_dump_error_desc), GFP_KERNEL);
2140 if (!iwl_dump_error_desc)
2143 iwl_dump_error_desc->trig_desc.type = cpu_to_le32(trig_type);
2144 iwl_dump_error_desc->len = 0;
2146 ret = iwl_fw_dbg_collect_desc(fwrt, iwl_dump_error_desc, false, 0);
2148 kfree(iwl_dump_error_desc);
2150 iwl_trans_sync_nmi(fwrt->trans);
2154 IWL_EXPORT_SYMBOL(iwl_fw_dbg_error_collect);
2156 int iwl_fw_dbg_collect(struct iwl_fw_runtime *fwrt,
2157 enum iwl_fw_dbg_trigger trig,
2158 const char *str, size_t len,
2159 struct iwl_fw_dbg_trigger_tlv *trigger)
2161 struct iwl_fw_dump_desc *desc;
2162 unsigned int delay = 0;
2163 bool monitor_only = false;
2166 u16 occurrences = le16_to_cpu(trigger->occurrences) - 1;
2168 if (!le16_to_cpu(trigger->occurrences))
2171 if (trigger->flags & IWL_FW_DBG_FORCE_RESTART) {
2172 IWL_WARN(fwrt, "Force restart: trigger %d fired.\n",
2174 iwl_force_nmi(fwrt->trans);
2178 trigger->occurrences = cpu_to_le16(occurrences);
2179 monitor_only = trigger->mode & IWL_FW_DBG_TRIGGER_MONITOR_ONLY;
2181 /* convert msec to usec */
2182 delay = le32_to_cpu(trigger->stop_delay) * USEC_PER_MSEC;
2185 desc = kzalloc(sizeof(*desc) + len, GFP_ATOMIC);
2191 desc->trig_desc.type = cpu_to_le32(trig);
2192 memcpy(desc->trig_desc.data, str, len);
2194 return iwl_fw_dbg_collect_desc(fwrt, desc, monitor_only, delay);
2196 IWL_EXPORT_SYMBOL(iwl_fw_dbg_collect);
2198 int _iwl_fw_dbg_ini_collect(struct iwl_fw_runtime *fwrt,
2199 enum iwl_fw_ini_trigger_id id)
2201 struct iwl_fw_ini_active_triggers *active;
2205 if (WARN_ON(!iwl_fw_ini_trigger_on(fwrt, id)))
2208 if (!iwl_fw_ini_trigger_on(fwrt, id)) {
2209 IWL_WARN(fwrt, "WRT: Trigger %d is not active, aborting dump\n",
2214 active = &fwrt->dump.active_trigs[id];
2215 delay = le32_to_cpu(active->trig->dump_delay);
2216 occur = le32_to_cpu(active->trig->occurrences);
2220 active->trig->occurrences = cpu_to_le32(--occur);
2222 if (le32_to_cpu(active->trig->force_restart)) {
2223 IWL_WARN(fwrt, "WRT: force restart: trigger %d fired.\n", id);
2224 iwl_force_nmi(fwrt->trans);
2228 /* Check there is an available worker.
2229 * ffz return value is undefined if no zero exists,
2230 * so check against ~0UL first.
2232 if (fwrt->dump.active_wks == ~0UL)
2235 idx = ffz(fwrt->dump.active_wks);
2237 if (idx >= IWL_FW_RUNTIME_DUMP_WK_NUM ||
2238 test_and_set_bit(fwrt->dump.wks[idx].idx, &fwrt->dump.active_wks))
2241 fwrt->dump.wks[idx].ini_trig_id = id;
2243 IWL_WARN(fwrt, "WRT: collecting data: ini trigger %d fired.\n", id);
2245 schedule_delayed_work(&fwrt->dump.wks[idx].wk, usecs_to_jiffies(delay));
2249 IWL_EXPORT_SYMBOL(_iwl_fw_dbg_ini_collect);
2251 int iwl_fw_dbg_ini_collect(struct iwl_fw_runtime *fwrt, u32 legacy_trigger_id)
2255 switch (legacy_trigger_id) {
2256 case FW_DBG_TRIGGER_FW_ASSERT:
2257 case FW_DBG_TRIGGER_ALIVE_TIMEOUT:
2258 case FW_DBG_TRIGGER_DRIVER:
2259 id = IWL_FW_TRIGGER_ID_FW_ASSERT;
2261 case FW_DBG_TRIGGER_USER:
2262 id = IWL_FW_TRIGGER_ID_USER_TRIGGER;
2268 return _iwl_fw_dbg_ini_collect(fwrt, id);
2270 IWL_EXPORT_SYMBOL(iwl_fw_dbg_ini_collect);
2272 int iwl_fw_dbg_collect_trig(struct iwl_fw_runtime *fwrt,
2273 struct iwl_fw_dbg_trigger_tlv *trigger,
2274 const char *fmt, ...)
2282 buf[sizeof(buf) - 1] = '\0';
2285 vsnprintf(buf, sizeof(buf), fmt, ap);
2288 /* check for truncation */
2289 if (WARN_ON_ONCE(buf[sizeof(buf) - 1]))
2290 buf[sizeof(buf) - 1] = '\0';
2292 len = strlen(buf) + 1;
2295 ret = iwl_fw_dbg_collect(fwrt, le32_to_cpu(trigger->id), buf, len,
2303 IWL_EXPORT_SYMBOL(iwl_fw_dbg_collect_trig);
2305 int iwl_fw_start_dbg_conf(struct iwl_fw_runtime *fwrt, u8 conf_id)
2311 if (WARN_ONCE(conf_id >= ARRAY_SIZE(fwrt->fw->dbg.conf_tlv),
2312 "Invalid configuration %d\n", conf_id))
2315 /* EARLY START - firmware's configuration is hard coded */
2316 if ((!fwrt->fw->dbg.conf_tlv[conf_id] ||
2317 !fwrt->fw->dbg.conf_tlv[conf_id]->num_of_hcmds) &&
2318 conf_id == FW_DBG_START_FROM_ALIVE)
2321 if (!fwrt->fw->dbg.conf_tlv[conf_id])
2324 if (fwrt->dump.conf != FW_DBG_INVALID)
2325 IWL_WARN(fwrt, "FW already configured (%d) - re-configuring\n",
2328 /* Send all HCMDs for configuring the FW debug */
2329 ptr = (void *)&fwrt->fw->dbg.conf_tlv[conf_id]->hcmd;
2330 for (i = 0; i < fwrt->fw->dbg.conf_tlv[conf_id]->num_of_hcmds; i++) {
2331 struct iwl_fw_dbg_conf_hcmd *cmd = (void *)ptr;
2332 struct iwl_host_cmd hcmd = {
2334 .len = { le16_to_cpu(cmd->len), },
2335 .data = { cmd->data, },
2338 ret = iwl_trans_send_cmd(fwrt->trans, &hcmd);
2342 ptr += sizeof(*cmd);
2343 ptr += le16_to_cpu(cmd->len);
2346 fwrt->dump.conf = conf_id;
2350 IWL_EXPORT_SYMBOL(iwl_fw_start_dbg_conf);
2352 /* this function assumes dump_start was called beforehand and dump_end will be
2355 static void iwl_fw_dbg_collect_sync(struct iwl_fw_runtime *fwrt, u8 wk_idx)
2357 struct iwl_fw_dbg_params params = {0};
2359 if (!test_bit(wk_idx, &fwrt->dump.active_wks))
2362 if (fwrt->ops && fwrt->ops->fw_running &&
2363 !fwrt->ops->fw_running(fwrt->ops_ctx)) {
2364 IWL_ERR(fwrt, "Firmware not running - cannot dump error\n");
2365 iwl_fw_free_dump_desc(fwrt);
2369 /* there's no point in fw dump if the bus is dead */
2370 if (test_bit(STATUS_TRANS_DEAD, &fwrt->trans->status)) {
2371 IWL_ERR(fwrt, "Skip fw error dump since bus is dead\n");
2375 iwl_fw_dbg_stop_recording(fwrt->trans, ¶ms);
2377 IWL_DEBUG_FW_INFO(fwrt, "WRT: data collection start\n");
2378 if (fwrt->trans->dbg.ini_valid)
2379 iwl_fw_error_ini_dump(fwrt, wk_idx);
2381 iwl_fw_error_dump(fwrt);
2382 IWL_DEBUG_FW_INFO(fwrt, "WRT: data collection done\n");
2384 iwl_fw_dbg_restart_recording(fwrt, ¶ms);
2387 clear_bit(wk_idx, &fwrt->dump.active_wks);
2390 void iwl_fw_error_dump_wk(struct work_struct *work)
2392 struct iwl_fw_runtime *fwrt;
2393 typeof(fwrt->dump.wks[0]) *wks;
2395 wks = container_of(work, typeof(fwrt->dump.wks[0]), wk.work);
2396 fwrt = container_of(wks, struct iwl_fw_runtime, dump.wks[wks->idx]);
2398 /* assumes the op mode mutex is locked in dump_start since
2399 * iwl_fw_dbg_collect_sync can't run in parallel
2401 if (fwrt->ops && fwrt->ops->dump_start &&
2402 fwrt->ops->dump_start(fwrt->ops_ctx))
2405 iwl_fw_dbg_collect_sync(fwrt, wks->idx);
2407 if (fwrt->ops && fwrt->ops->dump_end)
2408 fwrt->ops->dump_end(fwrt->ops_ctx);
2411 void iwl_fw_dbg_read_d3_debug_data(struct iwl_fw_runtime *fwrt)
2413 const struct iwl_cfg *cfg = fwrt->trans->cfg;
2415 if (!iwl_fw_dbg_is_d3_debug_enabled(fwrt))
2418 if (!fwrt->dump.d3_debug_data) {
2419 fwrt->dump.d3_debug_data = kmalloc(cfg->d3_debug_data_length,
2421 if (!fwrt->dump.d3_debug_data) {
2423 "failed to allocate memory for D3 debug data\n");
2428 /* if the buffer holds previous debug data it is overwritten */
2429 iwl_trans_read_mem_bytes(fwrt->trans, cfg->d3_debug_data_base_addr,
2430 fwrt->dump.d3_debug_data,
2431 cfg->d3_debug_data_length);
2433 IWL_EXPORT_SYMBOL(iwl_fw_dbg_read_d3_debug_data);
2435 static void iwl_fw_dbg_info_apply(struct iwl_fw_runtime *fwrt,
2436 struct iwl_fw_ini_debug_info_tlv *dbg_info,
2437 bool ext, enum iwl_fw_ini_apply_point pnt)
2439 u32 img_name_len = le32_to_cpu(dbg_info->img_name_len);
2440 u32 dbg_cfg_name_len = le32_to_cpu(dbg_info->dbg_cfg_name_len);
2441 const char err_str[] =
2442 "WRT: ext=%d. Invalid %s name length %d, expected %d\n";
2444 if (img_name_len != IWL_FW_INI_MAX_IMG_NAME_LEN) {
2445 IWL_WARN(fwrt, err_str, ext, "image", img_name_len,
2446 IWL_FW_INI_MAX_IMG_NAME_LEN);
2450 if (dbg_cfg_name_len != IWL_FW_INI_MAX_DBG_CFG_NAME_LEN) {
2451 IWL_WARN(fwrt, err_str, ext, "debug cfg", dbg_cfg_name_len,
2452 IWL_FW_INI_MAX_DBG_CFG_NAME_LEN);
2457 memcpy(fwrt->dump.external_dbg_cfg_name, dbg_info->dbg_cfg_name,
2458 sizeof(fwrt->dump.external_dbg_cfg_name));
2460 memcpy(fwrt->dump.img_name, dbg_info->img_name,
2461 sizeof(fwrt->dump.img_name));
2462 memcpy(fwrt->dump.internal_dbg_cfg_name, dbg_info->dbg_cfg_name,
2463 sizeof(fwrt->dump.internal_dbg_cfg_name));
2468 iwl_fw_dbg_buffer_allocation(struct iwl_fw_runtime *fwrt, u32 size)
2470 struct iwl_trans *trans = fwrt->trans;
2471 void *virtual_addr = NULL;
2472 dma_addr_t phys_addr;
2474 if (WARN_ON_ONCE(trans->dbg.num_blocks ==
2475 ARRAY_SIZE(trans->dbg.fw_mon)))
2479 dma_alloc_coherent(fwrt->trans->dev, size, &phys_addr,
2480 GFP_KERNEL | __GFP_NOWARN | __GFP_ZERO |
2483 /* TODO: alloc fragments if needed */
2485 IWL_ERR(fwrt, "Failed to allocate debug memory\n");
2488 "Allocated DRAM buffer[%d], size=0x%x\n",
2489 trans->dbg.num_blocks, size);
2491 trans->dbg.fw_mon[trans->dbg.num_blocks].block = virtual_addr;
2492 trans->dbg.fw_mon[trans->dbg.num_blocks].physical = phys_addr;
2493 trans->dbg.fw_mon[trans->dbg.num_blocks].size = size;
2494 trans->dbg.num_blocks++;
2497 static void iwl_fw_dbg_buffer_apply(struct iwl_fw_runtime *fwrt,
2498 struct iwl_fw_ini_allocation_data *alloc,
2499 enum iwl_fw_ini_apply_point pnt)
2501 struct iwl_trans *trans = fwrt->trans;
2502 struct iwl_ldbg_config_cmd ldbg_cmd = {
2503 .type = cpu_to_le32(BUFFER_ALLOCATION),
2505 struct iwl_buffer_allocation_cmd *cmd = &ldbg_cmd.buffer_allocation;
2506 struct iwl_host_cmd hcmd = {
2507 .id = LDBG_CONFIG_CMD,
2509 .data[0] = &ldbg_cmd,
2510 .len[0] = sizeof(ldbg_cmd),
2512 int block_idx = trans->dbg.num_blocks;
2513 u32 buf_location = le32_to_cpu(alloc->tlv.buffer_location);
2515 if (fwrt->trans->dbg.ini_dest == IWL_FW_INI_LOCATION_INVALID)
2516 fwrt->trans->dbg.ini_dest = buf_location;
2518 if (buf_location != fwrt->trans->dbg.ini_dest) {
2520 "WRT: attempt to override buffer location on apply point %d\n",
2526 if (buf_location == IWL_FW_INI_LOCATION_SRAM_PATH) {
2527 IWL_DEBUG_FW(trans, "WRT: applying SMEM buffer destination\n");
2528 /* set sram monitor by enabling bit 7 */
2529 iwl_set_bit(fwrt->trans, CSR_HW_IF_CONFIG_REG,
2530 CSR_HW_IF_CONFIG_REG_BIT_MONITOR_SRAM);
2535 if (buf_location != IWL_FW_INI_LOCATION_DRAM_PATH)
2538 if (!alloc->is_alloc) {
2539 iwl_fw_dbg_buffer_allocation(fwrt,
2540 le32_to_cpu(alloc->tlv.size));
2541 if (block_idx == trans->dbg.num_blocks)
2543 alloc->is_alloc = 1;
2546 /* First block is assigned via registers / context info */
2547 if (trans->dbg.num_blocks == 1)
2551 "WRT: applying DRAM buffer[%d] destination\n", block_idx);
2553 cmd->num_frags = cpu_to_le32(1);
2554 cmd->fragments[0].address =
2555 cpu_to_le64(trans->dbg.fw_mon[block_idx].physical);
2556 cmd->fragments[0].size = alloc->tlv.size;
2557 cmd->allocation_id = alloc->tlv.allocation_id;
2558 cmd->buffer_location = alloc->tlv.buffer_location;
2560 iwl_trans_send_cmd(trans, &hcmd);
2563 static void iwl_fw_dbg_send_hcmd(struct iwl_fw_runtime *fwrt,
2564 struct iwl_ucode_tlv *tlv,
2567 struct iwl_fw_ini_hcmd_tlv *hcmd_tlv = (void *)&tlv->data[0];
2568 struct iwl_fw_ini_hcmd *data = &hcmd_tlv->hcmd;
2569 u16 len = le32_to_cpu(tlv->length) - sizeof(*hcmd_tlv);
2571 struct iwl_host_cmd hcmd = {
2572 .id = WIDE_ID(data->group, data->id),
2574 .data = { data->data, },
2577 /* currently the driver supports always on domain only */
2578 if (le32_to_cpu(hcmd_tlv->domain) != IWL_FW_INI_DBG_DOMAIN_ALWAYS_ON)
2582 "WRT: ext=%d. Sending host command id=0x%x, group=0x%x\n",
2583 ext, data->id, data->group);
2585 iwl_trans_send_cmd(fwrt->trans, &hcmd);
2588 static void iwl_fw_dbg_update_regions(struct iwl_fw_runtime *fwrt,
2589 struct iwl_fw_ini_region_tlv *tlv,
2590 bool ext, enum iwl_fw_ini_apply_point pnt)
2592 void *iter = (void *)tlv->region_config;
2593 int i, size = le32_to_cpu(tlv->num_regions);
2594 const char *err_st =
2595 "WRT: ext=%d. Invalid region %s %d for apply point %d\n";
2597 for (i = 0; i < size; i++) {
2598 struct iwl_fw_ini_region_cfg *reg = iter, **active;
2599 int id = le32_to_cpu(reg->region_id);
2600 u32 type = le32_to_cpu(reg->region_type);
2602 if (WARN(id >= ARRAY_SIZE(fwrt->dump.active_regs), err_st, ext,
2606 if (WARN(type == 0 || type >= IWL_FW_INI_REGION_NUM, err_st,
2607 ext, "type", type, pnt))
2610 active = &fwrt->dump.active_regs[id];
2613 IWL_WARN(fwrt->trans,
2614 "WRT: ext=%d. Region id %d override\n",
2618 "WRT: ext=%d. Activating region id %d\n",
2623 if (type == IWL_FW_INI_REGION_TXF ||
2624 type == IWL_FW_INI_REGION_RXF)
2625 iter += le32_to_cpu(reg->fifos.num_of_registers) *
2627 else if (type == IWL_FW_INI_REGION_DEVICE_MEMORY ||
2628 type == IWL_FW_INI_REGION_PERIPHERY_MAC ||
2629 type == IWL_FW_INI_REGION_PERIPHERY_PHY ||
2630 type == IWL_FW_INI_REGION_PERIPHERY_AUX ||
2631 type == IWL_FW_INI_REGION_INTERNAL_BUFFER ||
2632 type == IWL_FW_INI_REGION_PAGING ||
2633 type == IWL_FW_INI_REGION_CSR ||
2634 type == IWL_FW_INI_REGION_LMAC_ERROR_TABLE ||
2635 type == IWL_FW_INI_REGION_UMAC_ERROR_TABLE)
2636 iter += le32_to_cpu(reg->internal.num_of_ranges) *
2639 iter += sizeof(*reg);
2643 static int iwl_fw_dbg_trig_realloc(struct iwl_fw_runtime *fwrt,
2644 struct iwl_fw_ini_active_triggers *active,
2649 if (size <= active->size)
2652 ptr = krealloc(active->trig, size, GFP_KERNEL);
2654 IWL_ERR(fwrt, "WRT: Failed to allocate memory for trigger %d\n",
2659 active->size = size;
2664 static void iwl_fw_dbg_update_triggers(struct iwl_fw_runtime *fwrt,
2665 struct iwl_fw_ini_trigger_tlv *tlv,
2667 enum iwl_fw_ini_apply_point apply_point)
2669 int i, size = le32_to_cpu(tlv->num_triggers);
2670 void *iter = (void *)tlv->trigger_config;
2672 for (i = 0; i < size; i++) {
2673 struct iwl_fw_ini_trigger *trig = iter;
2674 struct iwl_fw_ini_active_triggers *active;
2675 int id = le32_to_cpu(trig->trigger_id);
2676 u32 trig_regs_size = le32_to_cpu(trig->num_regions) *
2679 if (WARN(id >= ARRAY_SIZE(fwrt->dump.active_trigs),
2680 "WRT: ext=%d. Invalid trigger id %d for apply point %d\n",
2681 ext, id, apply_point))
2684 active = &fwrt->dump.active_trigs[id];
2686 if (!active->active) {
2687 size_t trig_size = sizeof(*trig) + trig_regs_size;
2690 "WRT: ext=%d. Activating trigger %d\n",
2693 if (iwl_fw_dbg_trig_realloc(fwrt, active, id,
2697 memcpy(active->trig, trig, trig_size);
2701 !(le32_to_cpu(trig->override_trig) & 0xff);
2702 u32 region_override =
2703 !(le32_to_cpu(trig->override_trig) & 0xff00);
2706 le32_to_cpu(active->trig->num_regions);
2707 u32 new_regs = le32_to_cpu(trig->num_regions);
2708 int mem_to_add = trig_regs_size;
2710 if (region_override) {
2712 "WRT: ext=%d. Trigger %d regions override\n",
2715 mem_to_add -= active_regs * sizeof(__le32);
2718 "WRT: ext=%d. Trigger %d regions appending\n",
2721 offset += active_regs;
2722 new_regs += active_regs;
2725 if (iwl_fw_dbg_trig_realloc(fwrt, active, id,
2726 active->size + mem_to_add))
2729 if (conf_override) {
2731 "WRT: ext=%d. Trigger %d configuration override\n",
2734 memcpy(active->trig, trig, sizeof(*trig));
2737 memcpy(active->trig->data + offset, trig->data,
2739 active->trig->num_regions = cpu_to_le32(new_regs);
2742 /* Since zero means infinity - just set to -1 */
2743 if (!le32_to_cpu(active->trig->occurrences))
2744 active->trig->occurrences = cpu_to_le32(-1);
2746 active->active = true;
2748 if (id == IWL_FW_TRIGGER_ID_PERIODIC_TRIGGER) {
2749 u32 collect_interval = le32_to_cpu(trig->trigger_data);
2751 /* the minimum allowed interval is 50ms */
2752 if (collect_interval < 50) {
2753 collect_interval = 50;
2754 trig->trigger_data =
2755 cpu_to_le32(collect_interval);
2758 mod_timer(&fwrt->dump.periodic_trig,
2759 jiffies + msecs_to_jiffies(collect_interval));
2762 iter += sizeof(*trig) + trig_regs_size;
2767 static void _iwl_fw_dbg_apply_point(struct iwl_fw_runtime *fwrt,
2768 struct iwl_apply_point_data *data,
2769 enum iwl_fw_ini_apply_point pnt,
2772 void *iter = data->data;
2774 while (iter && iter < data->data + data->size) {
2775 struct iwl_ucode_tlv *tlv = iter;
2776 void *ini_tlv = (void *)tlv->data;
2777 u32 type = le32_to_cpu(tlv->type);
2778 const char invalid_ap_str[] =
2779 "WRT: ext=%d. Invalid apply point %d for %s\n";
2782 case IWL_UCODE_TLV_TYPE_DEBUG_INFO:
2783 iwl_fw_dbg_info_apply(fwrt, ini_tlv, ext, pnt);
2785 case IWL_UCODE_TLV_TYPE_BUFFER_ALLOCATION: {
2786 struct iwl_fw_ini_allocation_data *buf_alloc = ini_tlv;
2788 if (pnt != IWL_FW_INI_APPLY_EARLY) {
2789 IWL_ERR(fwrt, invalid_ap_str, ext, pnt,
2790 "buffer allocation");
2794 iwl_fw_dbg_buffer_apply(fwrt, ini_tlv, pnt);
2795 iter += sizeof(buf_alloc->is_alloc);
2798 case IWL_UCODE_TLV_TYPE_HCMD:
2799 if (pnt < IWL_FW_INI_APPLY_AFTER_ALIVE) {
2800 IWL_ERR(fwrt, invalid_ap_str, ext, pnt,
2804 iwl_fw_dbg_send_hcmd(fwrt, tlv, ext);
2806 case IWL_UCODE_TLV_TYPE_REGIONS:
2807 iwl_fw_dbg_update_regions(fwrt, ini_tlv, ext, pnt);
2809 case IWL_UCODE_TLV_TYPE_TRIGGERS:
2810 iwl_fw_dbg_update_triggers(fwrt, ini_tlv, ext, pnt);
2812 case IWL_UCODE_TLV_TYPE_DEBUG_FLOW:
2816 "WRT: ext=%d. Invalid TLV 0x%x for apply point\n",
2821 iter += sizeof(*tlv) + le32_to_cpu(tlv->length);
2825 static void iwl_fw_dbg_ini_reset_cfg(struct iwl_fw_runtime *fwrt)
2829 for (i = 0; i < IWL_FW_INI_MAX_REGION_ID; i++)
2830 fwrt->dump.active_regs[i] = NULL;
2832 /* disable the triggers, used in recovery flow */
2833 for (i = 0; i < IWL_FW_TRIGGER_ID_NUM; i++)
2834 fwrt->dump.active_trigs[i].active = false;
2836 memset(fwrt->dump.img_name, 0,
2837 sizeof(fwrt->dump.img_name));
2838 memset(fwrt->dump.internal_dbg_cfg_name, 0,
2839 sizeof(fwrt->dump.internal_dbg_cfg_name));
2840 memset(fwrt->dump.external_dbg_cfg_name, 0,
2841 sizeof(fwrt->dump.external_dbg_cfg_name));
2843 fwrt->trans->dbg.ini_dest = IWL_FW_INI_LOCATION_INVALID;
2846 void iwl_fw_dbg_apply_point(struct iwl_fw_runtime *fwrt,
2847 enum iwl_fw_ini_apply_point apply_point)
2849 void *data = &fwrt->trans->dbg.apply_points[apply_point];
2851 IWL_DEBUG_FW(fwrt, "WRT: enabling apply point %d\n", apply_point);
2853 if (apply_point == IWL_FW_INI_APPLY_EARLY)
2854 iwl_fw_dbg_ini_reset_cfg(fwrt);
2856 _iwl_fw_dbg_apply_point(fwrt, data, apply_point, false);
2858 data = &fwrt->trans->dbg.apply_points_ext[apply_point];
2859 _iwl_fw_dbg_apply_point(fwrt, data, apply_point, true);
2861 IWL_EXPORT_SYMBOL(iwl_fw_dbg_apply_point);
2863 void iwl_fwrt_stop_device(struct iwl_fw_runtime *fwrt)
2867 del_timer(&fwrt->dump.periodic_trig);
2868 for (i = 0; i < IWL_FW_RUNTIME_DUMP_WK_NUM; i++)
2869 iwl_fw_dbg_collect_sync(fwrt, i);
2871 iwl_trans_stop_device(fwrt->trans);
2873 IWL_EXPORT_SYMBOL(iwl_fwrt_stop_device);
2875 void iwl_fw_dbg_periodic_trig_handler(struct timer_list *t)
2877 struct iwl_fw_runtime *fwrt;
2878 enum iwl_fw_ini_trigger_id id = IWL_FW_TRIGGER_ID_PERIODIC_TRIGGER;
2880 typeof(fwrt->dump) *dump_ptr = container_of(t, typeof(fwrt->dump),
2883 fwrt = container_of(dump_ptr, typeof(*fwrt), dump);
2885 ret = _iwl_fw_dbg_ini_collect(fwrt, id);
2886 if (!ret || ret == -EBUSY) {
2887 struct iwl_fw_ini_trigger *trig =
2888 fwrt->dump.active_trigs[id].trig;
2889 u32 occur = le32_to_cpu(trig->occurrences);
2890 u32 collect_interval = le32_to_cpu(trig->trigger_data);
2895 mod_timer(&fwrt->dump.periodic_trig,
2896 jiffies + msecs_to_jiffies(collect_interval));
2900 #define FSEQ_REG(x) { .addr = (x), .str = #x, }
2902 void iwl_fw_error_print_fseq_regs(struct iwl_fw_runtime *fwrt)
2904 struct iwl_trans *trans = fwrt->trans;
2905 unsigned long flags;
2911 FSEQ_REG(FSEQ_ERROR_CODE),
2912 FSEQ_REG(FSEQ_TOP_INIT_VERSION),
2913 FSEQ_REG(FSEQ_CNVIO_INIT_VERSION),
2914 FSEQ_REG(FSEQ_OTP_VERSION),
2915 FSEQ_REG(FSEQ_TOP_CONTENT_VERSION),
2916 FSEQ_REG(FSEQ_ALIVE_TOKEN),
2917 FSEQ_REG(FSEQ_CNVI_ID),
2918 FSEQ_REG(FSEQ_CNVR_ID),
2919 FSEQ_REG(CNVI_AUX_MISC_CHIP),
2920 FSEQ_REG(CNVR_AUX_MISC_CHIP),
2921 FSEQ_REG(CNVR_SCU_SD_REGS_SD_REG_DIG_DCDC_VTRIM),
2922 FSEQ_REG(CNVR_SCU_SD_REGS_SD_REG_ACTIVE_VDIG_MIRROR),
2925 if (!iwl_trans_grab_nic_access(trans, &flags))
2928 IWL_ERR(fwrt, "Fseq Registers:\n");
2930 for (i = 0; i < ARRAY_SIZE(fseq_regs); i++)
2931 IWL_ERR(fwrt, "0x%08X | %s\n",
2932 iwl_read_prph_no_grab(trans, fseq_regs[i].addr),
2935 iwl_trans_release_nic_access(trans, &flags);
2937 IWL_EXPORT_SYMBOL(iwl_fw_error_print_fseq_regs);