drivers/net/wireless/intel/iwlwifi/pcie/ctxt-info-gen3.c

   1 /******************************************************************************
   2  *
   3  * This file is provided under a dual BSD/GPLv2 license.  When using or
   4  * redistributing this file, you may do so under either license.
   5  *
   6  * GPL LICENSE SUMMARY
   7  *
   8  * Copyright(c) 2018 - 2019 Intel Corporation
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of version 2 of the GNU General Public License as
  12  * published by the Free Software Foundation.
  13  *
  14  * This program is distributed in the hope that it will be useful, but
  15  * WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  17  * General Public License for more details.
  18  *
  19  * BSD LICENSE
  20  *
  21  * Copyright(c) 2018 - 2019 Intel Corporation
  22  * All rights reserved.
  23  *
  24  * Redistribution and use in source and binary forms, with or without
  25  * modification, are permitted provided that the following conditions
  26  * are met:
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  29  *    notice, this list of conditions and the following disclaimer.
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  31  *    notice, this list of conditions and the following disclaimer in
  32  *    the documentation and/or other materials provided with the
  33  *    distribution.
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  35  *    contributors may be used to endorse or promote products derived
  36  *    from this software without specific prior written permission.
  37  *
  38  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  39  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  40  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  41  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  42  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  43  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  44  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  45  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  46  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  47  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  48  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  49  *
  50  *****************************************************************************/
  51
  52 #include "iwl-trans.h"
  53 #include "iwl-fh.h"
  54 #include "iwl-context-info-gen3.h"
  55 #include "internal.h"
  56 #include "iwl-prph.h"
  57
  58 static void
  59 iwl_pcie_ctxt_info_dbg_enable(struct iwl_trans *trans,
  60                               struct iwl_prph_scratch_hwm_cfg *dbg_cfg,
  61                               u32 *control_flags)
  62 {
  63         enum iwl_fw_ini_allocation_id alloc_id = IWL_FW_INI_ALLOCATION_ID_DBGC1;
  64         struct iwl_fw_ini_allocation_tlv *fw_mon_cfg;
  65         u32 dbg_flags = 0;
  66
  67         if (!iwl_trans_dbg_ini_valid(trans)) {
  68                 struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon;
  69
  70                 iwl_pcie_alloc_fw_monitor(trans, 0);
  71
  72                 if (fw_mon->size) {
  73                         dbg_flags |= IWL_PRPH_SCRATCH_EDBG_DEST_DRAM;
  74
  75                         IWL_DEBUG_FW(trans,
  76                                      "WRT: Applying DRAM buffer destination\n");
  77
  78                         dbg_cfg->hwm_base_addr = cpu_to_le64(fw_mon->physical);
  79                         dbg_cfg->hwm_size = cpu_to_le32(fw_mon->size);
  80                 }
  81
  82                 goto out;
  83         }
  84
  85         fw_mon_cfg = &trans->dbg.fw_mon_cfg[alloc_id];
  86
  87         if (le32_to_cpu(fw_mon_cfg->buf_location) ==
  88             IWL_FW_INI_LOCATION_SRAM_PATH) {
  89                 dbg_flags |= IWL_PRPH_SCRATCH_EDBG_DEST_INTERNAL;
  90
  91                 IWL_DEBUG_FW(trans,
  92                              "WRT: Applying SMEM buffer destination\n");
  93
  94                 goto out;
  95         }
  96
  97         if (le32_to_cpu(fw_mon_cfg->buf_location) ==
  98             IWL_FW_INI_LOCATION_DRAM_PATH &&
  99             trans->dbg.fw_mon_ini[alloc_id].num_frags) {
 100                 struct iwl_dram_data *frag =
 101                         &trans->dbg.fw_mon_ini[alloc_id].frags[0];
 102
 103                 dbg_flags |= IWL_PRPH_SCRATCH_EDBG_DEST_DRAM;
 104
 105                 IWL_DEBUG_FW(trans,
 106                              "WRT: Applying DRAM destination (alloc_id=%u)\n",
 107                              alloc_id);
 108
 109                 dbg_cfg->hwm_base_addr = cpu_to_le64(frag->physical);
 110                 dbg_cfg->hwm_size = cpu_to_le32(frag->size);
 111         }
 112
 113 out:
 114         if (dbg_flags)
 115                 *control_flags |= IWL_PRPH_SCRATCH_EARLY_DEBUG_EN | dbg_flags;
 116 }
 117
 118 int iwl_pcie_ctxt_info_gen3_init(struct iwl_trans *trans,
 119                                  const struct fw_img *fw)
 120 {
 121         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 122         struct iwl_context_info_gen3 *ctxt_info_gen3;
 123         struct iwl_prph_scratch *prph_scratch;
 124         struct iwl_prph_scratch_ctrl_cfg *prph_sc_ctrl;
 125         struct iwl_prph_info *prph_info;
 126         void *iml_img;
 127         u32 control_flags = 0;
 128         int ret;
 129         int cmdq_size = max_t(u32, IWL_CMD_QUEUE_SIZE,
 130                               trans->cfg->min_txq_size);
 131
 132         /* Allocate prph scratch */
 133         prph_scratch = dma_alloc_coherent(trans->dev, sizeof(*prph_scratch),
 134                                           &trans_pcie->prph_scratch_dma_addr,
 135                                           GFP_KERNEL);
 136         if (!prph_scratch)
 137                 return -ENOMEM;
 138
 139         prph_sc_ctrl = &prph_scratch->ctrl_cfg;
 140
 141         prph_sc_ctrl->version.version = 0;
 142         prph_sc_ctrl->version.mac_id =
 143                 cpu_to_le16((u16)iwl_read32(trans, CSR_HW_REV));
 144         prph_sc_ctrl->version.size = cpu_to_le16(sizeof(*prph_scratch) / 4);
 145
 146         control_flags = IWL_PRPH_SCRATCH_RB_SIZE_4K |
 147                         IWL_PRPH_SCRATCH_MTR_MODE |
 148                         (IWL_PRPH_MTR_FORMAT_256B &
 149                          IWL_PRPH_SCRATCH_MTR_FORMAT);
 150
 151         /* initialize RX default queue */
 152         prph_sc_ctrl->rbd_cfg.free_rbd_addr =
 153                 cpu_to_le64(trans_pcie->rxq->bd_dma);
 154
 155         iwl_pcie_ctxt_info_dbg_enable(trans, &prph_sc_ctrl->hwm_cfg,
 156                                       &control_flags);
 157         prph_sc_ctrl->control.control_flags = cpu_to_le32(control_flags);
 158
 159         /* allocate ucode sections in dram and set addresses */
 160         ret = iwl_pcie_init_fw_sec(trans, fw, &prph_scratch->dram);
 161         if (ret)
 162                 goto err_free_prph_scratch;
 163
 164
 165         /* Allocate prph information
 166          * currently we don't assign to the prph info anything, but it would get
 167          * assigned later */
 168         prph_info = dma_alloc_coherent(trans->dev, sizeof(*prph_info),
 169                                        &trans_pcie->prph_info_dma_addr,
 170                                        GFP_KERNEL);
 171         if (!prph_info) {
 172                 ret = -ENOMEM;
 173                 goto err_free_prph_scratch;
 174         }
 175
 176         /* Allocate context info */
 177         ctxt_info_gen3 = dma_alloc_coherent(trans->dev,
 178                                             sizeof(*ctxt_info_gen3),
 179                                             &trans_pcie->ctxt_info_dma_addr,
 180                                             GFP_KERNEL);
 181         if (!ctxt_info_gen3) {
 182                 ret = -ENOMEM;
 183                 goto err_free_prph_info;
 184         }
 185
 186         ctxt_info_gen3->prph_info_base_addr =
 187                 cpu_to_le64(trans_pcie->prph_info_dma_addr);
 188         ctxt_info_gen3->prph_scratch_base_addr =
 189                 cpu_to_le64(trans_pcie->prph_scratch_dma_addr);
 190         ctxt_info_gen3->prph_scratch_size =
 191                 cpu_to_le32(sizeof(*prph_scratch));
 192         ctxt_info_gen3->cr_head_idx_arr_base_addr =
 193                 cpu_to_le64(trans_pcie->rxq->rb_stts_dma);
 194         ctxt_info_gen3->tr_tail_idx_arr_base_addr =
 195                 cpu_to_le64(trans_pcie->rxq->tr_tail_dma);
 196         ctxt_info_gen3->cr_tail_idx_arr_base_addr =
 197                 cpu_to_le64(trans_pcie->rxq->cr_tail_dma);
 198         ctxt_info_gen3->cr_idx_arr_size =
 199                 cpu_to_le16(IWL_NUM_OF_COMPLETION_RINGS);
 200         ctxt_info_gen3->tr_idx_arr_size =
 201                 cpu_to_le16(IWL_NUM_OF_TRANSFER_RINGS);
 202         ctxt_info_gen3->mtr_base_addr =
 203                 cpu_to_le64(trans_pcie->txq[trans_pcie->cmd_queue]->dma_addr);
 204         ctxt_info_gen3->mcr_base_addr =
 205                 cpu_to_le64(trans_pcie->rxq->used_bd_dma);
 206         ctxt_info_gen3->mtr_size =
 207                 cpu_to_le16(TFD_QUEUE_CB_SIZE(cmdq_size));
 208         ctxt_info_gen3->mcr_size =
 209                 cpu_to_le16(RX_QUEUE_CB_SIZE(trans->cfg->num_rbds));
 210
 211         trans_pcie->ctxt_info_gen3 = ctxt_info_gen3;
 212         trans_pcie->prph_info = prph_info;
 213         trans_pcie->prph_scratch = prph_scratch;
 214
 215         /* Allocate IML */
 216         iml_img = dma_alloc_coherent(trans->dev, trans->iml_len,
 217                                      &trans_pcie->iml_dma_addr, GFP_KERNEL);
 218         if (!iml_img)
 219                 return -ENOMEM;
 220
 221         memcpy(iml_img, trans->iml, trans->iml_len);
 222
 223         iwl_enable_fw_load_int_ctx_info(trans);
 224
 225         /* kick FW self load */
 226         iwl_write64(trans, CSR_CTXT_INFO_ADDR,
 227                     trans_pcie->ctxt_info_dma_addr);
 228         iwl_write64(trans, CSR_IML_DATA_ADDR,
 229                     trans_pcie->iml_dma_addr);
 230         iwl_write32(trans, CSR_IML_SIZE_ADDR, trans->iml_len);
 231
 232         iwl_set_bit(trans, CSR_CTXT_INFO_BOOT_CTRL,
 233                     CSR_AUTO_FUNC_BOOT_ENA);
 234         if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210)
 235                 iwl_write_umac_prph(trans, UREG_CPU_INIT_RUN, 1);
 236         else
 237                 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_AUTO_FUNC_INIT);
 238
 239         return 0;
 240
 241 err_free_prph_info:
 242         dma_free_coherent(trans->dev,
 243                           sizeof(*prph_info),
 244                         prph_info,
 245                         trans_pcie->prph_info_dma_addr);
 246
 247 err_free_prph_scratch:
 248         dma_free_coherent(trans->dev,
 249                           sizeof(*prph_scratch),
 250                         prph_scratch,
 251                         trans_pcie->prph_scratch_dma_addr);
 252         return ret;
 253
 254 }
 255
 256 void iwl_pcie_ctxt_info_gen3_free(struct iwl_trans *trans)
 257 {
 258         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 259
 260         if (!trans_pcie->ctxt_info_gen3)
 261                 return;
 262
 263         dma_free_coherent(trans->dev, sizeof(*trans_pcie->ctxt_info_gen3),
 264                           trans_pcie->ctxt_info_gen3,
 265                           trans_pcie->ctxt_info_dma_addr);
 266         trans_pcie->ctxt_info_dma_addr = 0;
 267         trans_pcie->ctxt_info_gen3 = NULL;
 268
 269         iwl_pcie_ctxt_info_free_fw_img(trans);
 270
 271         dma_free_coherent(trans->dev, sizeof(*trans_pcie->prph_scratch),
 272                           trans_pcie->prph_scratch,
 273                           trans_pcie->prph_scratch_dma_addr);
 274         trans_pcie->prph_scratch_dma_addr = 0;
 275         trans_pcie->prph_scratch = NULL;
 276
 277         dma_free_coherent(trans->dev, sizeof(*trans_pcie->prph_info),
 278                           trans_pcie->prph_info,
 279                           trans_pcie->prph_info_dma_addr);
 280         trans_pcie->prph_info_dma_addr = 0;
 281         trans_pcie->prph_info = NULL;
 282 }