1 /******************************************************************************
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
8 * Copyright(c) 2003 - 2014 Intel Corporation. All rights reserved.
9 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
10 * Copyright(c) 2016 - 2017 Intel Deutschland GmbH
11 * Copyright(c) 2018 Intel Corporation
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of version 2 of the GNU General Public License as
15 * published by the Free Software Foundation.
17 * This program is distributed in the hope that it will be useful, but WITHOUT
18 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
19 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
22 * The full GNU General Public License is included in this distribution in the
23 * file called COPYING.
25 * Contact Information:
26 * Intel Linux Wireless <linuxwifi@intel.com>
27 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
31 * Copyright(c) 2003 - 2014 Intel Corporation. All rights reserved.
32 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
33 * Copyright(c) 2016 - 2017 Intel Deutschland GmbH
34 * Copyright(c) 2018 Intel Corporation
35 * All rights reserved.
37 * Redistribution and use in source and binary forms, with or without
38 * modification, are permitted provided that the following conditions
41 * * Redistributions of source code must retain the above copyright
42 * notice, this list of conditions and the following disclaimer.
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44 * notice, this list of conditions and the following disclaimer in
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49 * from this software without specific prior written permission.
51 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
52 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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61 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
63 *****************************************************************************/
64 #include <linux/sched.h>
65 #include <linux/wait.h>
66 #include <linux/gfp.h>
71 #include "iwl-op-mode.h"
72 #include "iwl-context-info-gen3.h"
74 /******************************************************************************
78 ******************************************************************************/
81 * Rx theory of operation
83 * Driver allocates a circular buffer of Receive Buffer Descriptors (RBDs),
84 * each of which point to Receive Buffers to be filled by the NIC. These get
85 * used not only for Rx frames, but for any command response or notification
86 * from the NIC. The driver and NIC manage the Rx buffers by means
87 * of indexes into the circular buffer.
90 * The host/firmware share two index registers for managing the Rx buffers.
92 * The READ index maps to the first position that the firmware may be writing
93 * to -- the driver can read up to (but not including) this position and get
95 * The READ index is managed by the firmware once the card is enabled.
97 * The WRITE index maps to the last position the driver has read from -- the
98 * position preceding WRITE is the last slot the firmware can place a packet.
100 * The queue is empty (no good data) if WRITE = READ - 1, and is full if
103 * During initialization, the host sets up the READ queue position to the first
104 * INDEX position, and WRITE to the last (READ - 1 wrapped)
106 * When the firmware places a packet in a buffer, it will advance the READ index
107 * and fire the RX interrupt. The driver can then query the READ index and
108 * process as many packets as possible, moving the WRITE index forward as it
109 * resets the Rx queue buffers with new memory.
111 * The management in the driver is as follows:
112 * + A list of pre-allocated RBDs is stored in iwl->rxq->rx_free.
113 * When the interrupt handler is called, the request is processed.
114 * The page is either stolen - transferred to the upper layer
115 * or reused - added immediately to the iwl->rxq->rx_free list.
116 * + When the page is stolen - the driver updates the matching queue's used
117 * count, detaches the RBD and transfers it to the queue used list.
118 * When there are two used RBDs - they are transferred to the allocator empty
119 * list. Work is then scheduled for the allocator to start allocating
121 * When there are another 6 used RBDs - they are transferred to the allocator
122 * empty list and the driver tries to claim the pre-allocated buffers and
123 * add them to iwl->rxq->rx_free. If it fails - it continues to claim them
125 * When there are 8+ buffers in the free list - either from allocation or from
126 * 8 reused unstolen pages - restock is called to update the FW and indexes.
127 * + In order to make sure the allocator always has RBDs to use for allocation
128 * the allocator has initial pool in the size of num_queues*(8-2) - the
129 * maximum missing RBDs per allocation request (request posted with 2
130 * empty RBDs, there is no guarantee when the other 6 RBDs are supplied).
131 * The queues supplies the recycle of the rest of the RBDs.
132 * + A received packet is processed and handed to the kernel network stack,
133 * detached from the iwl->rxq. The driver 'processed' index is updated.
134 * + If there are no allocated buffers in iwl->rxq->rx_free,
135 * the READ INDEX is not incremented and iwl->status(RX_STALLED) is set.
136 * If there were enough free buffers and RX_STALLED is set it is cleared.
141 * iwl_rxq_alloc() Allocates rx_free
142 * iwl_pcie_rx_replenish() Replenishes rx_free list from rx_used, and calls
143 * iwl_pcie_rxq_restock.
144 * Used only during initialization.
145 * iwl_pcie_rxq_restock() Moves available buffers from rx_free into Rx
146 * queue, updates firmware pointers, and updates
148 * iwl_pcie_rx_allocator() Background work for allocating pages.
150 * -- enable interrupts --
151 * ISR - iwl_rx() Detach iwl_rx_mem_buffers from pool up to the
152 * READ INDEX, detaching the SKB from the pool.
153 * Moves the packet buffer from queue to rx_used.
154 * Posts and claims requests to the allocator.
155 * Calls iwl_pcie_rxq_restock to refill any empty
161 * rxq.pool -> rxq.rx_used -> rxq.rx_free -> rxq.queue
163 * Regular Receive interrupt:
165 * rxq.queue -> rxq.rx_used -> allocator.rbd_empty ->
166 * allocator.rbd_allocated -> rxq.rx_free -> rxq.queue
168 * rxq.queue -> rxq.rx_free -> rxq.queue
174 * iwl_rxq_space - Return number of free slots available in queue.
176 static int iwl_rxq_space(const struct iwl_rxq *rxq)
178 /* Make sure rx queue size is a power of 2 */
179 WARN_ON(rxq->queue_size & (rxq->queue_size - 1));
182 * There can be up to (RX_QUEUE_SIZE - 1) free slots, to avoid ambiguity
183 * between empty and completely full queues.
184 * The following is equivalent to modulo by RX_QUEUE_SIZE and is well
185 * defined for negative dividends.
187 return (rxq->read - rxq->write - 1) & (rxq->queue_size - 1);
191 * iwl_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
193 static inline __le32 iwl_pcie_dma_addr2rbd_ptr(dma_addr_t dma_addr)
195 return cpu_to_le32((u32)(dma_addr >> 8));
199 * iwl_pcie_rx_stop - stops the Rx DMA
201 int iwl_pcie_rx_stop(struct iwl_trans *trans)
203 if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_22560) {
204 /* TODO: remove this for 22560 once fw does it */
205 iwl_write_prph(trans, RFH_RXF_DMA_CFG_GEN3, 0);
206 return iwl_poll_prph_bit(trans, RFH_GEN_STATUS_GEN3,
207 RXF_DMA_IDLE, RXF_DMA_IDLE, 1000);
208 } else if (trans->cfg->mq_rx_supported) {
209 iwl_write_prph(trans, RFH_RXF_DMA_CFG, 0);
210 return iwl_poll_prph_bit(trans, RFH_GEN_STATUS,
211 RXF_DMA_IDLE, RXF_DMA_IDLE, 1000);
213 iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
214 return iwl_poll_direct_bit(trans, FH_MEM_RSSR_RX_STATUS_REG,
215 FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE,
221 * iwl_pcie_rxq_inc_wr_ptr - Update the write pointer for the RX queue
223 static void iwl_pcie_rxq_inc_wr_ptr(struct iwl_trans *trans,
228 lockdep_assert_held(&rxq->lock);
231 * explicitly wake up the NIC if:
232 * 1. shadow registers aren't enabled
233 * 2. there is a chance that the NIC is asleep
235 if (!trans->cfg->base_params->shadow_reg_enable &&
236 test_bit(STATUS_TPOWER_PMI, &trans->status)) {
237 reg = iwl_read32(trans, CSR_UCODE_DRV_GP1);
239 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
240 IWL_DEBUG_INFO(trans, "Rx queue requesting wakeup, GP1 = 0x%x\n",
242 iwl_set_bit(trans, CSR_GP_CNTRL,
243 BIT(trans->cfg->csr->flag_mac_access_req));
244 rxq->need_update = true;
249 rxq->write_actual = round_down(rxq->write, 8);
250 if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_22560)
251 iwl_write32(trans, HBUS_TARG_WRPTR,
253 ((FIRST_RX_QUEUE + rxq->id) << 16)));
254 else if (trans->cfg->mq_rx_supported)
255 iwl_write32(trans, RFH_Q_FRBDCB_WIDX_TRG(rxq->id),
258 iwl_write32(trans, FH_RSCSR_CHNL0_WPTR, rxq->write_actual);
261 static void iwl_pcie_rxq_check_wrptr(struct iwl_trans *trans)
263 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
266 for (i = 0; i < trans->num_rx_queues; i++) {
267 struct iwl_rxq *rxq = &trans_pcie->rxq[i];
269 if (!rxq->need_update)
271 spin_lock(&rxq->lock);
272 iwl_pcie_rxq_inc_wr_ptr(trans, rxq);
273 rxq->need_update = false;
274 spin_unlock(&rxq->lock);
278 static void iwl_pcie_restock_bd(struct iwl_trans *trans,
280 struct iwl_rx_mem_buffer *rxb)
282 if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_22560) {
283 struct iwl_rx_transfer_desc *bd = rxq->bd;
285 bd[rxq->write].type_n_size =
286 cpu_to_le32((IWL_RX_TD_TYPE & IWL_RX_TD_TYPE_MSK) |
287 ((IWL_RX_TD_SIZE_2K >> 8) & IWL_RX_TD_SIZE_MSK));
288 bd[rxq->write].addr = cpu_to_le64(rxb->page_dma);
289 bd[rxq->write].rbid = cpu_to_le16(rxb->vid);
291 __le64 *bd = rxq->bd;
293 bd[rxq->write] = cpu_to_le64(rxb->page_dma | rxb->vid);
296 IWL_DEBUG_RX(trans, "Assigned virtual RB ID %u to queue %d index %d\n",
297 (u32)rxb->vid, rxq->id, rxq->write);
301 * iwl_pcie_rxmq_restock - restock implementation for multi-queue rx
303 static void iwl_pcie_rxmq_restock(struct iwl_trans *trans,
306 struct iwl_rx_mem_buffer *rxb;
309 * If the device isn't enabled - no need to try to add buffers...
310 * This can happen when we stop the device and still have an interrupt
311 * pending. We stop the APM before we sync the interrupts because we
312 * have to (see comment there). On the other hand, since the APM is
313 * stopped, we cannot access the HW (in particular not prph).
314 * So don't try to restock if the APM has been already stopped.
316 if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status))
319 spin_lock(&rxq->lock);
320 while (rxq->free_count) {
321 /* Get next free Rx buffer, remove from free list */
322 rxb = list_first_entry(&rxq->rx_free, struct iwl_rx_mem_buffer,
324 list_del(&rxb->list);
325 rxb->invalid = false;
326 /* 12 first bits are expected to be empty */
327 WARN_ON(rxb->page_dma & DMA_BIT_MASK(12));
328 /* Point to Rx buffer via next RBD in circular buffer */
329 iwl_pcie_restock_bd(trans, rxq, rxb);
330 rxq->write = (rxq->write + 1) & MQ_RX_TABLE_MASK;
333 spin_unlock(&rxq->lock);
336 * If we've added more space for the firmware to place data, tell it.
337 * Increment device's write pointer in multiples of 8.
339 if (rxq->write_actual != (rxq->write & ~0x7)) {
340 spin_lock(&rxq->lock);
341 iwl_pcie_rxq_inc_wr_ptr(trans, rxq);
342 spin_unlock(&rxq->lock);
347 * iwl_pcie_rxsq_restock - restock implementation for single queue rx
349 static void iwl_pcie_rxsq_restock(struct iwl_trans *trans,
352 struct iwl_rx_mem_buffer *rxb;
355 * If the device isn't enabled - not need to try to add buffers...
356 * This can happen when we stop the device and still have an interrupt
357 * pending. We stop the APM before we sync the interrupts because we
358 * have to (see comment there). On the other hand, since the APM is
359 * stopped, we cannot access the HW (in particular not prph).
360 * So don't try to restock if the APM has been already stopped.
362 if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status))
365 spin_lock(&rxq->lock);
366 while ((iwl_rxq_space(rxq) > 0) && (rxq->free_count)) {
367 __le32 *bd = (__le32 *)rxq->bd;
368 /* The overwritten rxb must be a used one */
369 rxb = rxq->queue[rxq->write];
370 BUG_ON(rxb && rxb->page);
372 /* Get next free Rx buffer, remove from free list */
373 rxb = list_first_entry(&rxq->rx_free, struct iwl_rx_mem_buffer,
375 list_del(&rxb->list);
376 rxb->invalid = false;
378 /* Point to Rx buffer via next RBD in circular buffer */
379 bd[rxq->write] = iwl_pcie_dma_addr2rbd_ptr(rxb->page_dma);
380 rxq->queue[rxq->write] = rxb;
381 rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
384 spin_unlock(&rxq->lock);
386 /* If we've added more space for the firmware to place data, tell it.
387 * Increment device's write pointer in multiples of 8. */
388 if (rxq->write_actual != (rxq->write & ~0x7)) {
389 spin_lock(&rxq->lock);
390 iwl_pcie_rxq_inc_wr_ptr(trans, rxq);
391 spin_unlock(&rxq->lock);
396 * iwl_pcie_rxq_restock - refill RX queue from pre-allocated pool
398 * If there are slots in the RX queue that need to be restocked,
399 * and we have free pre-allocated buffers, fill the ranks as much
400 * as we can, pulling from rx_free.
402 * This moves the 'write' index forward to catch up with 'processed', and
403 * also updates the memory address in the firmware to reference the new
407 void iwl_pcie_rxq_restock(struct iwl_trans *trans, struct iwl_rxq *rxq)
409 if (trans->cfg->mq_rx_supported)
410 iwl_pcie_rxmq_restock(trans, rxq);
412 iwl_pcie_rxsq_restock(trans, rxq);
416 * iwl_pcie_rx_alloc_page - allocates and returns a page.
419 static struct page *iwl_pcie_rx_alloc_page(struct iwl_trans *trans,
422 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
424 gfp_t gfp_mask = priority;
426 if (trans_pcie->rx_page_order > 0)
427 gfp_mask |= __GFP_COMP;
429 /* Alloc a new receive buffer */
430 page = alloc_pages(gfp_mask, trans_pcie->rx_page_order);
433 IWL_DEBUG_INFO(trans, "alloc_pages failed, order: %d\n",
434 trans_pcie->rx_page_order);
436 * Issue an error if we don't have enough pre-allocated
439 if (!(gfp_mask & __GFP_NOWARN) && net_ratelimit())
441 "Failed to alloc_pages\n");
448 * iwl_pcie_rxq_alloc_rbs - allocate a page for each used RBD
450 * A used RBD is an Rx buffer that has been given to the stack. To use it again
451 * a page must be allocated and the RBD must point to the page. This function
452 * doesn't change the HW pointer but handles the list of pages that is used by
453 * iwl_pcie_rxq_restock. The latter function will update the HW to use the newly
456 void iwl_pcie_rxq_alloc_rbs(struct iwl_trans *trans, gfp_t priority,
459 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
460 struct iwl_rx_mem_buffer *rxb;
464 spin_lock(&rxq->lock);
465 if (list_empty(&rxq->rx_used)) {
466 spin_unlock(&rxq->lock);
469 spin_unlock(&rxq->lock);
471 /* Alloc a new receive buffer */
472 page = iwl_pcie_rx_alloc_page(trans, priority);
476 spin_lock(&rxq->lock);
478 if (list_empty(&rxq->rx_used)) {
479 spin_unlock(&rxq->lock);
480 __free_pages(page, trans_pcie->rx_page_order);
483 rxb = list_first_entry(&rxq->rx_used, struct iwl_rx_mem_buffer,
485 list_del(&rxb->list);
486 spin_unlock(&rxq->lock);
490 /* Get physical address of the RB */
492 dma_map_page(trans->dev, page, 0,
493 PAGE_SIZE << trans_pcie->rx_page_order,
495 if (dma_mapping_error(trans->dev, rxb->page_dma)) {
497 spin_lock(&rxq->lock);
498 list_add(&rxb->list, &rxq->rx_used);
499 spin_unlock(&rxq->lock);
500 __free_pages(page, trans_pcie->rx_page_order);
504 spin_lock(&rxq->lock);
506 list_add_tail(&rxb->list, &rxq->rx_free);
509 spin_unlock(&rxq->lock);
513 void iwl_pcie_free_rbs_pool(struct iwl_trans *trans)
515 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
518 for (i = 0; i < RX_POOL_SIZE; i++) {
519 if (!trans_pcie->rx_pool[i].page)
521 dma_unmap_page(trans->dev, trans_pcie->rx_pool[i].page_dma,
522 PAGE_SIZE << trans_pcie->rx_page_order,
524 __free_pages(trans_pcie->rx_pool[i].page,
525 trans_pcie->rx_page_order);
526 trans_pcie->rx_pool[i].page = NULL;
531 * iwl_pcie_rx_allocator - Allocates pages in the background for RX queues
533 * Allocates for each received request 8 pages
534 * Called as a scheduled work item.
536 static void iwl_pcie_rx_allocator(struct iwl_trans *trans)
538 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
539 struct iwl_rb_allocator *rba = &trans_pcie->rba;
540 struct list_head local_empty;
541 int pending = atomic_read(&rba->req_pending);
543 IWL_DEBUG_TPT(trans, "Pending allocation requests = %d\n", pending);
545 /* If we were scheduled - there is at least one request */
546 spin_lock(&rba->lock);
547 /* swap out the rba->rbd_empty to a local list */
548 list_replace_init(&rba->rbd_empty, &local_empty);
549 spin_unlock(&rba->lock);
553 LIST_HEAD(local_allocated);
554 gfp_t gfp_mask = GFP_KERNEL;
556 /* Do not post a warning if there are only a few requests */
557 if (pending < RX_PENDING_WATERMARK)
558 gfp_mask |= __GFP_NOWARN;
560 for (i = 0; i < RX_CLAIM_REQ_ALLOC;) {
561 struct iwl_rx_mem_buffer *rxb;
564 /* List should never be empty - each reused RBD is
565 * returned to the list, and initial pool covers any
566 * possible gap between the time the page is allocated
567 * to the time the RBD is added.
569 BUG_ON(list_empty(&local_empty));
570 /* Get the first rxb from the rbd list */
571 rxb = list_first_entry(&local_empty,
572 struct iwl_rx_mem_buffer, list);
575 /* Alloc a new receive buffer */
576 page = iwl_pcie_rx_alloc_page(trans, gfp_mask);
581 /* Get physical address of the RB */
582 rxb->page_dma = dma_map_page(trans->dev, page, 0,
583 PAGE_SIZE << trans_pcie->rx_page_order,
585 if (dma_mapping_error(trans->dev, rxb->page_dma)) {
587 __free_pages(page, trans_pcie->rx_page_order);
591 /* move the allocated entry to the out list */
592 list_move(&rxb->list, &local_allocated);
596 atomic_dec(&rba->req_pending);
600 pending = atomic_read(&rba->req_pending);
603 "Got more pending allocation requests = %d\n",
607 spin_lock(&rba->lock);
608 /* add the allocated rbds to the allocator allocated list */
609 list_splice_tail(&local_allocated, &rba->rbd_allocated);
610 /* get more empty RBDs for current pending requests */
611 list_splice_tail_init(&rba->rbd_empty, &local_empty);
612 spin_unlock(&rba->lock);
614 atomic_inc(&rba->req_ready);
618 spin_lock(&rba->lock);
619 /* return unused rbds to the allocator empty list */
620 list_splice_tail(&local_empty, &rba->rbd_empty);
621 spin_unlock(&rba->lock);
623 IWL_DEBUG_TPT(trans, "%s, exit.\n", __func__);
627 * iwl_pcie_rx_allocator_get - returns the pre-allocated pages
629 .* Called by queue when the queue posted allocation request and
630 * has freed 8 RBDs in order to restock itself.
631 * This function directly moves the allocated RBs to the queue's ownership
632 * and updates the relevant counters.
634 static void iwl_pcie_rx_allocator_get(struct iwl_trans *trans,
637 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
638 struct iwl_rb_allocator *rba = &trans_pcie->rba;
641 lockdep_assert_held(&rxq->lock);
644 * atomic_dec_if_positive returns req_ready - 1 for any scenario.
645 * If req_ready is 0 atomic_dec_if_positive will return -1 and this
646 * function will return early, as there are no ready requests.
647 * atomic_dec_if_positive will perofrm the *actual* decrement only if
648 * req_ready > 0, i.e. - there are ready requests and the function
649 * hands one request to the caller.
651 if (atomic_dec_if_positive(&rba->req_ready) < 0)
654 spin_lock(&rba->lock);
655 for (i = 0; i < RX_CLAIM_REQ_ALLOC; i++) {
656 /* Get next free Rx buffer, remove it from free list */
657 struct iwl_rx_mem_buffer *rxb =
658 list_first_entry(&rba->rbd_allocated,
659 struct iwl_rx_mem_buffer, list);
661 list_move(&rxb->list, &rxq->rx_free);
663 spin_unlock(&rba->lock);
665 rxq->used_count -= RX_CLAIM_REQ_ALLOC;
666 rxq->free_count += RX_CLAIM_REQ_ALLOC;
669 void iwl_pcie_rx_allocator_work(struct work_struct *data)
671 struct iwl_rb_allocator *rba_p =
672 container_of(data, struct iwl_rb_allocator, rx_alloc);
673 struct iwl_trans_pcie *trans_pcie =
674 container_of(rba_p, struct iwl_trans_pcie, rba);
676 iwl_pcie_rx_allocator(trans_pcie->trans);
679 static int iwl_pcie_free_bd_size(struct iwl_trans *trans, bool use_rx_td)
681 struct iwl_rx_transfer_desc *rx_td;
684 return sizeof(*rx_td);
686 return trans->cfg->mq_rx_supported ? sizeof(__le64) :
690 static void iwl_pcie_free_rxq_dma(struct iwl_trans *trans,
693 struct device *dev = trans->dev;
694 bool use_rx_td = (trans->cfg->device_family >=
695 IWL_DEVICE_FAMILY_22560);
696 int free_size = iwl_pcie_free_bd_size(trans, use_rx_td);
699 dma_free_coherent(trans->dev,
700 free_size * rxq->queue_size,
701 rxq->bd, rxq->bd_dma);
706 dma_free_coherent(trans->dev,
707 use_rx_td ? sizeof(__le16) :
708 sizeof(struct iwl_rb_status),
709 rxq->rb_stts, rxq->rb_stts_dma);
710 rxq->rb_stts_dma = 0;
714 dma_free_coherent(trans->dev,
715 (use_rx_td ? sizeof(*rxq->cd) :
716 sizeof(__le32)) * rxq->queue_size,
717 rxq->used_bd, rxq->used_bd_dma);
718 rxq->used_bd_dma = 0;
721 if (trans->cfg->device_family < IWL_DEVICE_FAMILY_22560)
725 dma_free_coherent(dev, sizeof(__le16),
726 rxq->tr_tail, rxq->tr_tail_dma);
727 rxq->tr_tail_dma = 0;
731 dma_free_coherent(dev, sizeof(__le16),
732 rxq->cr_tail, rxq->cr_tail_dma);
733 rxq->cr_tail_dma = 0;
737 static int iwl_pcie_alloc_rxq_dma(struct iwl_trans *trans,
740 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
741 struct device *dev = trans->dev;
744 bool use_rx_td = (trans->cfg->device_family >=
745 IWL_DEVICE_FAMILY_22560);
747 spin_lock_init(&rxq->lock);
748 if (trans->cfg->mq_rx_supported)
749 rxq->queue_size = MQ_RX_TABLE_SIZE;
751 rxq->queue_size = RX_QUEUE_SIZE;
753 free_size = iwl_pcie_free_bd_size(trans, use_rx_td);
756 * Allocate the circular buffer of Read Buffer Descriptors
759 rxq->bd = dma_alloc_coherent(dev, free_size * rxq->queue_size,
760 &rxq->bd_dma, GFP_KERNEL);
764 if (trans->cfg->mq_rx_supported) {
765 rxq->used_bd = dma_alloc_coherent(dev,
766 (use_rx_td ? sizeof(*rxq->cd) : sizeof(__le32)) * rxq->queue_size,
773 /* Allocate the driver's pointer to receive buffer status */
774 rxq->rb_stts = dma_alloc_coherent(dev,
775 use_rx_td ? sizeof(__le16) : sizeof(struct iwl_rb_status),
776 &rxq->rb_stts_dma, GFP_KERNEL);
783 /* Allocate the driver's pointer to TR tail */
784 rxq->tr_tail = dma_alloc_coherent(dev, sizeof(__le16),
785 &rxq->tr_tail_dma, GFP_KERNEL);
789 /* Allocate the driver's pointer to CR tail */
790 rxq->cr_tail = dma_alloc_coherent(dev, sizeof(__le16),
791 &rxq->cr_tail_dma, GFP_KERNEL);
795 * W/A 22560 device step Z0 must be non zero bug
796 * TODO: remove this when stop supporting Z0
798 *rxq->cr_tail = cpu_to_le16(500);
803 for (i = 0; i < trans->num_rx_queues; i++) {
804 struct iwl_rxq *rxq = &trans_pcie->rxq[i];
806 iwl_pcie_free_rxq_dma(trans, rxq);
808 kfree(trans_pcie->rxq);
813 int iwl_pcie_rx_alloc(struct iwl_trans *trans)
815 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
816 struct iwl_rb_allocator *rba = &trans_pcie->rba;
819 if (WARN_ON(trans_pcie->rxq))
822 trans_pcie->rxq = kcalloc(trans->num_rx_queues, sizeof(struct iwl_rxq),
824 if (!trans_pcie->rxq)
827 spin_lock_init(&rba->lock);
829 for (i = 0; i < trans->num_rx_queues; i++) {
830 struct iwl_rxq *rxq = &trans_pcie->rxq[i];
832 ret = iwl_pcie_alloc_rxq_dma(trans, rxq);
839 static void iwl_pcie_rx_hw_init(struct iwl_trans *trans, struct iwl_rxq *rxq)
841 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
844 const u32 rfdnlog = RX_QUEUE_SIZE_LOG; /* 256 RBDs */
846 switch (trans_pcie->rx_buf_size) {
848 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K;
851 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K;
854 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_12K;
858 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K;
861 if (!iwl_trans_grab_nic_access(trans, &flags))
865 iwl_write32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
866 /* reset and flush pointers */
867 iwl_write32(trans, FH_MEM_RCSR_CHNL0_RBDCB_WPTR, 0);
868 iwl_write32(trans, FH_MEM_RCSR_CHNL0_FLUSH_RB_REQ, 0);
869 iwl_write32(trans, FH_RSCSR_CHNL0_RDPTR, 0);
871 /* Reset driver's Rx queue write index */
872 iwl_write32(trans, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
874 /* Tell device where to find RBD circular buffer in DRAM */
875 iwl_write32(trans, FH_RSCSR_CHNL0_RBDCB_BASE_REG,
876 (u32)(rxq->bd_dma >> 8));
878 /* Tell device where in DRAM to update its Rx status */
879 iwl_write32(trans, FH_RSCSR_CHNL0_STTS_WPTR_REG,
880 rxq->rb_stts_dma >> 4);
883 * FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY is set because of HW bug in
884 * the credit mechanism in 5000 HW RX FIFO
885 * Direct rx interrupts to hosts
886 * Rx buffer size 4 or 8k or 12k
890 iwl_write32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG,
891 FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |
892 FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY |
893 FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |
895 (RX_RB_TIMEOUT << FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS) |
896 (rfdnlog << FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS));
898 iwl_trans_release_nic_access(trans, &flags);
900 /* Set interrupt coalescing timer to default (2048 usecs) */
901 iwl_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF);
903 /* W/A for interrupt coalescing bug in 7260 and 3160 */
904 if (trans->cfg->host_interrupt_operation_mode)
905 iwl_set_bit(trans, CSR_INT_COALESCING, IWL_HOST_INT_OPER_MODE);
908 static void iwl_pcie_rx_mq_hw_init(struct iwl_trans *trans)
910 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
911 u32 rb_size, enabled = 0;
915 switch (trans_pcie->rx_buf_size) {
917 rb_size = RFH_RXF_DMA_RB_SIZE_2K;
920 rb_size = RFH_RXF_DMA_RB_SIZE_4K;
923 rb_size = RFH_RXF_DMA_RB_SIZE_8K;
926 rb_size = RFH_RXF_DMA_RB_SIZE_12K;
930 rb_size = RFH_RXF_DMA_RB_SIZE_4K;
933 if (!iwl_trans_grab_nic_access(trans, &flags))
937 iwl_write_prph_no_grab(trans, RFH_RXF_DMA_CFG, 0);
938 /* disable free amd used rx queue operation */
939 iwl_write_prph_no_grab(trans, RFH_RXF_RXQ_ACTIVE, 0);
941 for (i = 0; i < trans->num_rx_queues; i++) {
942 /* Tell device where to find RBD free table in DRAM */
943 iwl_write_prph64_no_grab(trans,
944 RFH_Q_FRBDCB_BA_LSB(i),
945 trans_pcie->rxq[i].bd_dma);
946 /* Tell device where to find RBD used table in DRAM */
947 iwl_write_prph64_no_grab(trans,
948 RFH_Q_URBDCB_BA_LSB(i),
949 trans_pcie->rxq[i].used_bd_dma);
950 /* Tell device where in DRAM to update its Rx status */
951 iwl_write_prph64_no_grab(trans,
952 RFH_Q_URBD_STTS_WPTR_LSB(i),
953 trans_pcie->rxq[i].rb_stts_dma);
954 /* Reset device indice tables */
955 iwl_write_prph_no_grab(trans, RFH_Q_FRBDCB_WIDX(i), 0);
956 iwl_write_prph_no_grab(trans, RFH_Q_FRBDCB_RIDX(i), 0);
957 iwl_write_prph_no_grab(trans, RFH_Q_URBDCB_WIDX(i), 0);
959 enabled |= BIT(i) | BIT(i + 16);
964 * Rx buffer size 4 or 8k or 12k
966 * Drop frames that exceed RB size
969 iwl_write_prph_no_grab(trans, RFH_RXF_DMA_CFG,
970 RFH_DMA_EN_ENABLE_VAL | rb_size |
971 RFH_RXF_DMA_MIN_RB_4_8 |
972 RFH_RXF_DMA_DROP_TOO_LARGE_MASK |
973 RFH_RXF_DMA_RBDCB_SIZE_512);
976 * Activate DMA snooping.
977 * Set RX DMA chunk size to 64B for IOSF and 128B for PCIe
980 iwl_write_prph_no_grab(trans, RFH_GEN_CFG,
981 RFH_GEN_CFG_RFH_DMA_SNOOP |
982 RFH_GEN_CFG_VAL(DEFAULT_RXQ_NUM, 0) |
983 RFH_GEN_CFG_SERVICE_DMA_SNOOP |
984 RFH_GEN_CFG_VAL(RB_CHUNK_SIZE,
985 trans->cfg->integrated ?
986 RFH_GEN_CFG_RB_CHUNK_SIZE_64 :
987 RFH_GEN_CFG_RB_CHUNK_SIZE_128));
988 /* Enable the relevant rx queues */
989 iwl_write_prph_no_grab(trans, RFH_RXF_RXQ_ACTIVE, enabled);
991 iwl_trans_release_nic_access(trans, &flags);
993 /* Set interrupt coalescing timer to default (2048 usecs) */
994 iwl_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF);
997 void iwl_pcie_rx_init_rxb_lists(struct iwl_rxq *rxq)
999 lockdep_assert_held(&rxq->lock);
1001 INIT_LIST_HEAD(&rxq->rx_free);
1002 INIT_LIST_HEAD(&rxq->rx_used);
1003 rxq->free_count = 0;
1004 rxq->used_count = 0;
1007 int iwl_pcie_dummy_napi_poll(struct napi_struct *napi, int budget)
1013 int _iwl_pcie_rx_init(struct iwl_trans *trans)
1015 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1016 struct iwl_rxq *def_rxq;
1017 struct iwl_rb_allocator *rba = &trans_pcie->rba;
1018 int i, err, queue_size, allocator_pool_size, num_alloc;
1020 if (!trans_pcie->rxq) {
1021 err = iwl_pcie_rx_alloc(trans);
1025 def_rxq = trans_pcie->rxq;
1027 cancel_work_sync(&rba->rx_alloc);
1029 spin_lock(&rba->lock);
1030 atomic_set(&rba->req_pending, 0);
1031 atomic_set(&rba->req_ready, 0);
1032 INIT_LIST_HEAD(&rba->rbd_allocated);
1033 INIT_LIST_HEAD(&rba->rbd_empty);
1034 spin_unlock(&rba->lock);
1036 /* free all first - we might be reconfigured for a different size */
1037 iwl_pcie_free_rbs_pool(trans);
1039 for (i = 0; i < RX_QUEUE_SIZE; i++)
1040 def_rxq->queue[i] = NULL;
1042 for (i = 0; i < trans->num_rx_queues; i++) {
1043 struct iwl_rxq *rxq = &trans_pcie->rxq[i];
1047 spin_lock(&rxq->lock);
1049 * Set read write pointer to reflect that we have processed
1050 * and used all buffers, but have not restocked the Rx queue
1051 * with fresh buffers
1055 rxq->write_actual = 0;
1056 memset(rxq->rb_stts, 0,
1057 (trans->cfg->device_family >= IWL_DEVICE_FAMILY_22560) ?
1058 sizeof(__le16) : sizeof(struct iwl_rb_status));
1060 iwl_pcie_rx_init_rxb_lists(rxq);
1062 if (!rxq->napi.poll)
1063 netif_napi_add(&trans_pcie->napi_dev, &rxq->napi,
1064 iwl_pcie_dummy_napi_poll, 64);
1066 spin_unlock(&rxq->lock);
1069 /* move the pool to the default queue and allocator ownerships */
1070 queue_size = trans->cfg->mq_rx_supported ?
1071 MQ_RX_NUM_RBDS : RX_QUEUE_SIZE;
1072 allocator_pool_size = trans->num_rx_queues *
1073 (RX_CLAIM_REQ_ALLOC - RX_POST_REQ_ALLOC);
1074 num_alloc = queue_size + allocator_pool_size;
1075 BUILD_BUG_ON(ARRAY_SIZE(trans_pcie->global_table) !=
1076 ARRAY_SIZE(trans_pcie->rx_pool));
1077 for (i = 0; i < num_alloc; i++) {
1078 struct iwl_rx_mem_buffer *rxb = &trans_pcie->rx_pool[i];
1080 if (i < allocator_pool_size)
1081 list_add(&rxb->list, &rba->rbd_empty);
1083 list_add(&rxb->list, &def_rxq->rx_used);
1084 trans_pcie->global_table[i] = rxb;
1085 rxb->vid = (u16)(i + 1);
1086 rxb->invalid = true;
1089 iwl_pcie_rxq_alloc_rbs(trans, GFP_KERNEL, def_rxq);
1094 int iwl_pcie_rx_init(struct iwl_trans *trans)
1096 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1097 int ret = _iwl_pcie_rx_init(trans);
1102 if (trans->cfg->mq_rx_supported)
1103 iwl_pcie_rx_mq_hw_init(trans);
1105 iwl_pcie_rx_hw_init(trans, trans_pcie->rxq);
1107 iwl_pcie_rxq_restock(trans, trans_pcie->rxq);
1109 spin_lock(&trans_pcie->rxq->lock);
1110 iwl_pcie_rxq_inc_wr_ptr(trans, trans_pcie->rxq);
1111 spin_unlock(&trans_pcie->rxq->lock);
1116 int iwl_pcie_gen2_rx_init(struct iwl_trans *trans)
1118 /* Set interrupt coalescing timer to default (2048 usecs) */
1119 iwl_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF);
1122 * We don't configure the RFH.
1123 * Restock will be done at alive, after firmware configured the RFH.
1125 return _iwl_pcie_rx_init(trans);
1128 void iwl_pcie_rx_free(struct iwl_trans *trans)
1130 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1131 struct iwl_rb_allocator *rba = &trans_pcie->rba;
1135 * if rxq is NULL, it means that nothing has been allocated,
1138 if (!trans_pcie->rxq) {
1139 IWL_DEBUG_INFO(trans, "Free NULL rx context\n");
1143 cancel_work_sync(&rba->rx_alloc);
1145 iwl_pcie_free_rbs_pool(trans);
1147 for (i = 0; i < trans->num_rx_queues; i++) {
1148 struct iwl_rxq *rxq = &trans_pcie->rxq[i];
1150 iwl_pcie_free_rxq_dma(trans, rxq);
1153 netif_napi_del(&rxq->napi);
1155 kfree(trans_pcie->rxq);
1158 static void iwl_pcie_rx_move_to_allocator(struct iwl_rxq *rxq,
1159 struct iwl_rb_allocator *rba)
1161 spin_lock(&rba->lock);
1162 list_splice_tail_init(&rxq->rx_used, &rba->rbd_empty);
1163 spin_unlock(&rba->lock);
1167 * iwl_pcie_rx_reuse_rbd - Recycle used RBDs
1169 * Called when a RBD can be reused. The RBD is transferred to the allocator.
1170 * When there are 2 empty RBDs - a request for allocation is posted
1172 static void iwl_pcie_rx_reuse_rbd(struct iwl_trans *trans,
1173 struct iwl_rx_mem_buffer *rxb,
1174 struct iwl_rxq *rxq, bool emergency)
1176 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1177 struct iwl_rb_allocator *rba = &trans_pcie->rba;
1179 /* Move the RBD to the used list, will be moved to allocator in batches
1180 * before claiming or posting a request*/
1181 list_add_tail(&rxb->list, &rxq->rx_used);
1183 if (unlikely(emergency))
1186 /* Count the allocator owned RBDs */
1189 /* If we have RX_POST_REQ_ALLOC new released rx buffers -
1190 * issue a request for allocator. Modulo RX_CLAIM_REQ_ALLOC is
1191 * used for the case we failed to claim RX_CLAIM_REQ_ALLOC,
1192 * after but we still need to post another request.
1194 if ((rxq->used_count % RX_CLAIM_REQ_ALLOC) == RX_POST_REQ_ALLOC) {
1195 /* Move the 2 RBDs to the allocator ownership.
1196 Allocator has another 6 from pool for the request completion*/
1197 iwl_pcie_rx_move_to_allocator(rxq, rba);
1199 atomic_inc(&rba->req_pending);
1200 queue_work(rba->alloc_wq, &rba->rx_alloc);
1204 static void iwl_pcie_rx_handle_rb(struct iwl_trans *trans,
1205 struct iwl_rxq *rxq,
1206 struct iwl_rx_mem_buffer *rxb,
1210 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1211 struct iwl_txq *txq = trans_pcie->txq[trans_pcie->cmd_queue];
1212 bool page_stolen = false;
1213 int max_len = PAGE_SIZE << trans_pcie->rx_page_order;
1219 dma_unmap_page(trans->dev, rxb->page_dma, max_len, DMA_FROM_DEVICE);
1221 while (offset + sizeof(u32) + sizeof(struct iwl_cmd_header) < max_len) {
1222 struct iwl_rx_packet *pkt;
1225 int index, cmd_index, len;
1226 struct iwl_rx_cmd_buffer rxcb = {
1228 ._rx_page_order = trans_pcie->rx_page_order,
1230 ._page_stolen = false,
1231 .truesize = max_len,
1234 if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_22560)
1235 rxcb.status = rxq->cd[i].status;
1237 pkt = rxb_addr(&rxcb);
1239 if (pkt->len_n_flags == cpu_to_le32(FH_RSCSR_FRAME_INVALID)) {
1241 "Q %d: RB end marker at offset %d\n",
1246 WARN((le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_RXQ_MASK) >>
1247 FH_RSCSR_RXQ_POS != rxq->id,
1248 "frame on invalid queue - is on %d and indicates %d\n",
1250 (le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_RXQ_MASK) >>
1254 "Q %d: cmd at offset %d: %s (%.2x.%2x, seq 0x%x)\n",
1256 iwl_get_cmd_string(trans,
1257 iwl_cmd_id(pkt->hdr.cmd,
1260 pkt->hdr.group_id, pkt->hdr.cmd,
1261 le16_to_cpu(pkt->hdr.sequence));
1263 len = iwl_rx_packet_len(pkt);
1264 len += sizeof(u32); /* account for status word */
1265 trace_iwlwifi_dev_rx(trans->dev, trans, pkt, len);
1266 trace_iwlwifi_dev_rx_data(trans->dev, trans, pkt, len);
1268 /* Reclaim a command buffer only if this packet is a response
1269 * to a (driver-originated) command.
1270 * If the packet (e.g. Rx frame) originated from uCode,
1271 * there is no command buffer to reclaim.
1272 * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
1273 * but apparently a few don't get set; catch them here. */
1274 reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME);
1275 if (reclaim && !pkt->hdr.group_id) {
1278 for (i = 0; i < trans_pcie->n_no_reclaim_cmds; i++) {
1279 if (trans_pcie->no_reclaim_cmds[i] ==
1287 sequence = le16_to_cpu(pkt->hdr.sequence);
1288 index = SEQ_TO_INDEX(sequence);
1289 cmd_index = iwl_pcie_get_cmd_index(txq, index);
1291 if (rxq->id == trans_pcie->def_rx_queue)
1292 iwl_op_mode_rx(trans->op_mode, &rxq->napi,
1295 iwl_op_mode_rx_rss(trans->op_mode, &rxq->napi,
1299 kzfree(txq->entries[cmd_index].free_buf);
1300 txq->entries[cmd_index].free_buf = NULL;
1304 * After here, we should always check rxcb._page_stolen,
1305 * if it is true then one of the handlers took the page.
1309 /* Invoke any callbacks, transfer the buffer to caller,
1310 * and fire off the (possibly) blocking
1311 * iwl_trans_send_cmd()
1312 * as we reclaim the driver command queue */
1313 if (!rxcb._page_stolen)
1314 iwl_pcie_hcmd_complete(trans, &rxcb);
1316 IWL_WARN(trans, "Claim null rxb?\n");
1319 page_stolen |= rxcb._page_stolen;
1320 if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_22560)
1322 offset += ALIGN(len, FH_RSCSR_FRAME_ALIGN);
1325 /* page was stolen from us -- free our reference */
1327 __free_pages(rxb->page, trans_pcie->rx_page_order);
1331 /* Reuse the page if possible. For notification packets and
1332 * SKBs that fail to Rx correctly, add them back into the
1333 * rx_free list for reuse later. */
1334 if (rxb->page != NULL) {
1336 dma_map_page(trans->dev, rxb->page, 0,
1337 PAGE_SIZE << trans_pcie->rx_page_order,
1339 if (dma_mapping_error(trans->dev, rxb->page_dma)) {
1341 * free the page(s) as well to not break
1342 * the invariant that the items on the used
1343 * list have no page(s)
1345 __free_pages(rxb->page, trans_pcie->rx_page_order);
1347 iwl_pcie_rx_reuse_rbd(trans, rxb, rxq, emergency);
1349 list_add_tail(&rxb->list, &rxq->rx_free);
1353 iwl_pcie_rx_reuse_rbd(trans, rxb, rxq, emergency);
1356 static struct iwl_rx_mem_buffer *iwl_pcie_get_rxb(struct iwl_trans *trans,
1357 struct iwl_rxq *rxq, int i)
1359 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1360 struct iwl_rx_mem_buffer *rxb;
1363 if (!trans->cfg->mq_rx_supported) {
1364 rxb = rxq->queue[i];
1365 rxq->queue[i] = NULL;
1369 /* used_bd is a 32/16 bit but only 12 are used to retrieve the vid */
1370 if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_22560)
1371 vid = le16_to_cpu(rxq->cd[i].rbid) & 0x0FFF;
1373 vid = le32_to_cpu(rxq->bd_32[i]) & 0x0FFF;
1375 if (!vid || vid > ARRAY_SIZE(trans_pcie->global_table))
1378 rxb = trans_pcie->global_table[vid - 1];
1382 IWL_DEBUG_RX(trans, "Got virtual RB ID %u\n", (u32)rxb->vid);
1384 if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_22560)
1385 rxb->size = le32_to_cpu(rxq->cd[i].size) & IWL_RX_CD_SIZE;
1387 rxb->invalid = true;
1392 WARN(1, "Invalid rxb from HW %u\n", (u32)vid);
1393 iwl_force_nmi(trans);
1398 * iwl_pcie_rx_handle - Main entry function for receiving responses from fw
1400 static void iwl_pcie_rx_handle(struct iwl_trans *trans, int queue)
1402 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1403 struct iwl_rxq *rxq = &trans_pcie->rxq[queue];
1404 u32 r, i, count = 0;
1405 bool emergency = false;
1408 spin_lock(&rxq->lock);
1409 /* uCode's read index (stored in shared DRAM) indicates the last Rx
1410 * buffer that the driver may process (last buffer filled by ucode). */
1411 r = le16_to_cpu(iwl_get_closed_rb_stts(trans, rxq)) & 0x0FFF;
1414 /* W/A 9000 device step A0 wrap-around bug */
1415 r &= (rxq->queue_size - 1);
1417 /* Rx interrupt, but nothing sent from uCode */
1419 IWL_DEBUG_RX(trans, "Q %d: HW = SW = %d\n", rxq->id, r);
1422 struct iwl_rb_allocator *rba = &trans_pcie->rba;
1423 struct iwl_rx_mem_buffer *rxb;
1424 /* number of RBDs still waiting for page allocation */
1425 u32 rb_pending_alloc =
1426 atomic_read(&trans_pcie->rba.req_pending) *
1429 if (unlikely(rb_pending_alloc >= rxq->queue_size / 2 &&
1431 iwl_pcie_rx_move_to_allocator(rxq, rba);
1433 IWL_DEBUG_TPT(trans,
1434 "RX path is in emergency. Pending allocations %d\n",
1438 IWL_DEBUG_RX(trans, "Q %d: HW = %d, SW = %d\n", rxq->id, r, i);
1440 rxb = iwl_pcie_get_rxb(trans, rxq, i);
1444 iwl_pcie_rx_handle_rb(trans, rxq, rxb, emergency, i);
1446 i = (i + 1) & (rxq->queue_size - 1);
1449 * If we have RX_CLAIM_REQ_ALLOC released rx buffers -
1450 * try to claim the pre-allocated buffers from the allocator.
1451 * If not ready - will try to reclaim next time.
1452 * There is no need to reschedule work - allocator exits only
1455 if (rxq->used_count >= RX_CLAIM_REQ_ALLOC)
1456 iwl_pcie_rx_allocator_get(trans, rxq);
1458 if (rxq->used_count % RX_CLAIM_REQ_ALLOC == 0 && !emergency) {
1459 /* Add the remaining empty RBDs for allocator use */
1460 iwl_pcie_rx_move_to_allocator(rxq, rba);
1461 } else if (emergency) {
1465 if (rb_pending_alloc < rxq->queue_size / 3) {
1466 IWL_DEBUG_TPT(trans,
1467 "RX path exited emergency. Pending allocations %d\n",
1473 spin_unlock(&rxq->lock);
1474 iwl_pcie_rxq_alloc_rbs(trans, GFP_ATOMIC, rxq);
1475 iwl_pcie_rxq_restock(trans, rxq);
1481 /* Backtrack one entry */
1483 /* update cr tail with the rxq read pointer */
1484 if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_22560)
1485 *rxq->cr_tail = cpu_to_le16(r);
1486 spin_unlock(&rxq->lock);
1489 * handle a case where in emergency there are some unallocated RBDs.
1490 * those RBDs are in the used list, but are not tracked by the queue's
1491 * used_count which counts allocator owned RBDs.
1492 * unallocated emergency RBDs must be allocated on exit, otherwise
1493 * when called again the function may not be in emergency mode and
1494 * they will be handed to the allocator with no tracking in the RBD
1495 * allocator counters, which will lead to them never being claimed back
1497 * by allocating them here, they are now in the queue free list, and
1498 * will be restocked by the next call of iwl_pcie_rxq_restock.
1500 if (unlikely(emergency && count))
1501 iwl_pcie_rxq_alloc_rbs(trans, GFP_ATOMIC, rxq);
1504 napi_gro_flush(&rxq->napi, false);
1506 iwl_pcie_rxq_restock(trans, rxq);
1509 static struct iwl_trans_pcie *iwl_pcie_get_trans_pcie(struct msix_entry *entry)
1511 u8 queue = entry->entry;
1512 struct msix_entry *entries = entry - queue;
1514 return container_of(entries, struct iwl_trans_pcie, msix_entries[0]);
1518 * iwl_pcie_rx_msix_handle - Main entry function for receiving responses from fw
1519 * This interrupt handler should be used with RSS queue only.
1521 irqreturn_t iwl_pcie_irq_rx_msix_handler(int irq, void *dev_id)
1523 struct msix_entry *entry = dev_id;
1524 struct iwl_trans_pcie *trans_pcie = iwl_pcie_get_trans_pcie(entry);
1525 struct iwl_trans *trans = trans_pcie->trans;
1527 trace_iwlwifi_dev_irq_msix(trans->dev, entry, false, 0, 0);
1529 if (WARN_ON(entry->entry >= trans->num_rx_queues))
1532 lock_map_acquire(&trans->sync_cmd_lockdep_map);
1535 iwl_pcie_rx_handle(trans, entry->entry);
1538 iwl_pcie_clear_irq(trans, entry);
1540 lock_map_release(&trans->sync_cmd_lockdep_map);
1546 * iwl_pcie_irq_handle_error - called for HW or SW error interrupt from card
1548 static void iwl_pcie_irq_handle_error(struct iwl_trans *trans)
1550 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1553 /* W/A for WiFi/WiMAX coex and WiMAX own the RF */
1554 if (trans->cfg->internal_wimax_coex &&
1555 !trans->cfg->apmg_not_supported &&
1556 (!(iwl_read_prph(trans, APMG_CLK_CTRL_REG) &
1557 APMS_CLK_VAL_MRB_FUNC_MODE) ||
1558 (iwl_read_prph(trans, APMG_PS_CTRL_REG) &
1559 APMG_PS_CTRL_VAL_RESET_REQ))) {
1560 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
1561 iwl_op_mode_wimax_active(trans->op_mode);
1562 wake_up(&trans_pcie->wait_command_queue);
1566 for (i = 0; i < trans->cfg->base_params->num_of_queues; i++) {
1567 if (!trans_pcie->txq[i])
1569 del_timer(&trans_pcie->txq[i]->stuck_timer);
1572 /* The STATUS_FW_ERROR bit is set in this function. This must happen
1573 * before we wake up the command caller, to ensure a proper cleanup. */
1574 iwl_trans_fw_error(trans);
1576 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
1577 wake_up(&trans_pcie->wait_command_queue);
1580 static u32 iwl_pcie_int_cause_non_ict(struct iwl_trans *trans)
1584 lockdep_assert_held(&IWL_TRANS_GET_PCIE_TRANS(trans)->irq_lock);
1586 trace_iwlwifi_dev_irq(trans->dev);
1588 /* Discover which interrupts are active/pending */
1589 inta = iwl_read32(trans, CSR_INT);
1591 /* the thread will service interrupts and re-enable them */
1595 /* a device (PCI-E) page is 4096 bytes long */
1596 #define ICT_SHIFT 12
1597 #define ICT_SIZE (1 << ICT_SHIFT)
1598 #define ICT_COUNT (ICT_SIZE / sizeof(u32))
1600 /* interrupt handler using ict table, with this interrupt driver will
1601 * stop using INTA register to get device's interrupt, reading this register
1602 * is expensive, device will write interrupts in ICT dram table, increment
1603 * index then will fire interrupt to driver, driver will OR all ICT table
1604 * entries from current index up to table entry with 0 value. the result is
1605 * the interrupt we need to service, driver will set the entries back to 0 and
1608 static u32 iwl_pcie_int_cause_ict(struct iwl_trans *trans)
1610 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1615 trace_iwlwifi_dev_irq(trans->dev);
1617 /* Ignore interrupt if there's nothing in NIC to service.
1618 * This may be due to IRQ shared with another device,
1619 * or due to sporadic interrupts thrown from our NIC. */
1620 read = le32_to_cpu(trans_pcie->ict_tbl[trans_pcie->ict_index]);
1621 trace_iwlwifi_dev_ict_read(trans->dev, trans_pcie->ict_index, read);
1626 * Collect all entries up to the first 0, starting from ict_index;
1627 * note we already read at ict_index.
1631 IWL_DEBUG_ISR(trans, "ICT index %d value 0x%08X\n",
1632 trans_pcie->ict_index, read);
1633 trans_pcie->ict_tbl[trans_pcie->ict_index] = 0;
1634 trans_pcie->ict_index =
1635 ((trans_pcie->ict_index + 1) & (ICT_COUNT - 1));
1637 read = le32_to_cpu(trans_pcie->ict_tbl[trans_pcie->ict_index]);
1638 trace_iwlwifi_dev_ict_read(trans->dev, trans_pcie->ict_index,
1642 /* We should not get this value, just ignore it. */
1643 if (val == 0xffffffff)
1647 * this is a w/a for a h/w bug. the h/w bug may cause the Rx bit
1648 * (bit 15 before shifting it to 31) to clear when using interrupt
1649 * coalescing. fortunately, bits 18 and 19 stay set when this happens
1650 * so we use them to decide on the real state of the Rx bit.
1651 * In order words, bit 15 is set if bit 18 or bit 19 are set.
1656 inta = (0xff & val) | ((0xff00 & val) << 16);
1660 void iwl_pcie_handle_rfkill_irq(struct iwl_trans *trans)
1662 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1663 struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1664 bool hw_rfkill, prev, report;
1666 mutex_lock(&trans_pcie->mutex);
1667 prev = test_bit(STATUS_RFKILL_OPMODE, &trans->status);
1668 hw_rfkill = iwl_is_rfkill_set(trans);
1670 set_bit(STATUS_RFKILL_OPMODE, &trans->status);
1671 set_bit(STATUS_RFKILL_HW, &trans->status);
1673 if (trans_pcie->opmode_down)
1676 report = test_bit(STATUS_RFKILL_OPMODE, &trans->status);
1678 IWL_WARN(trans, "RF_KILL bit toggled to %s.\n",
1679 hw_rfkill ? "disable radio" : "enable radio");
1681 isr_stats->rfkill++;
1684 iwl_trans_pcie_rf_kill(trans, report);
1685 mutex_unlock(&trans_pcie->mutex);
1688 if (test_and_clear_bit(STATUS_SYNC_HCMD_ACTIVE,
1690 IWL_DEBUG_RF_KILL(trans,
1691 "Rfkill while SYNC HCMD in flight\n");
1692 wake_up(&trans_pcie->wait_command_queue);
1694 clear_bit(STATUS_RFKILL_HW, &trans->status);
1695 if (trans_pcie->opmode_down)
1696 clear_bit(STATUS_RFKILL_OPMODE, &trans->status);
1700 irqreturn_t iwl_pcie_irq_handler(int irq, void *dev_id)
1702 struct iwl_trans *trans = dev_id;
1703 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1704 struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1708 lock_map_acquire(&trans->sync_cmd_lockdep_map);
1710 spin_lock(&trans_pcie->irq_lock);
1712 /* dram interrupt table not set yet,
1713 * use legacy interrupt.
1715 if (likely(trans_pcie->use_ict))
1716 inta = iwl_pcie_int_cause_ict(trans);
1718 inta = iwl_pcie_int_cause_non_ict(trans);
1720 if (iwl_have_debug_level(IWL_DL_ISR)) {
1721 IWL_DEBUG_ISR(trans,
1722 "ISR inta 0x%08x, enabled 0x%08x(sw), enabled(hw) 0x%08x, fh 0x%08x\n",
1723 inta, trans_pcie->inta_mask,
1724 iwl_read32(trans, CSR_INT_MASK),
1725 iwl_read32(trans, CSR_FH_INT_STATUS));
1726 if (inta & (~trans_pcie->inta_mask))
1727 IWL_DEBUG_ISR(trans,
1728 "We got a masked interrupt (0x%08x)\n",
1729 inta & (~trans_pcie->inta_mask));
1732 inta &= trans_pcie->inta_mask;
1735 * Ignore interrupt if there's nothing in NIC to service.
1736 * This may be due to IRQ shared with another device,
1737 * or due to sporadic interrupts thrown from our NIC.
1739 if (unlikely(!inta)) {
1740 IWL_DEBUG_ISR(trans, "Ignore interrupt, inta == 0\n");
1742 * Re-enable interrupts here since we don't
1743 * have anything to service
1745 if (test_bit(STATUS_INT_ENABLED, &trans->status))
1746 _iwl_enable_interrupts(trans);
1747 spin_unlock(&trans_pcie->irq_lock);
1748 lock_map_release(&trans->sync_cmd_lockdep_map);
1752 if (unlikely(inta == 0xFFFFFFFF || (inta & 0xFFFFFFF0) == 0xa5a5a5a0)) {
1754 * Hardware disappeared. It might have
1755 * already raised an interrupt.
1757 IWL_WARN(trans, "HARDWARE GONE?? INTA == 0x%08x\n", inta);
1758 spin_unlock(&trans_pcie->irq_lock);
1762 /* Ack/clear/reset pending uCode interrupts.
1763 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
1765 /* There is a hardware bug in the interrupt mask function that some
1766 * interrupts (i.e. CSR_INT_BIT_SCD) can still be generated even if
1767 * they are disabled in the CSR_INT_MASK register. Furthermore the
1768 * ICT interrupt handling mechanism has another bug that might cause
1769 * these unmasked interrupts fail to be detected. We workaround the
1770 * hardware bugs here by ACKing all the possible interrupts so that
1771 * interrupt coalescing can still be achieved.
1773 iwl_write32(trans, CSR_INT, inta | ~trans_pcie->inta_mask);
1775 if (iwl_have_debug_level(IWL_DL_ISR))
1776 IWL_DEBUG_ISR(trans, "inta 0x%08x, enabled 0x%08x\n",
1777 inta, iwl_read32(trans, CSR_INT_MASK));
1779 spin_unlock(&trans_pcie->irq_lock);
1781 /* Now service all interrupt bits discovered above. */
1782 if (inta & CSR_INT_BIT_HW_ERR) {
1783 IWL_ERR(trans, "Hardware error detected. Restarting.\n");
1785 /* Tell the device to stop sending interrupts */
1786 iwl_disable_interrupts(trans);
1789 iwl_pcie_irq_handle_error(trans);
1791 handled |= CSR_INT_BIT_HW_ERR;
1796 if (iwl_have_debug_level(IWL_DL_ISR)) {
1797 /* NIC fires this, but we don't use it, redundant with WAKEUP */
1798 if (inta & CSR_INT_BIT_SCD) {
1799 IWL_DEBUG_ISR(trans,
1800 "Scheduler finished to transmit the frame/frames.\n");
1804 /* Alive notification via Rx interrupt will do the real work */
1805 if (inta & CSR_INT_BIT_ALIVE) {
1806 IWL_DEBUG_ISR(trans, "Alive interrupt\n");
1808 if (trans->cfg->gen2) {
1810 * We can restock, since firmware configured
1813 iwl_pcie_rxmq_restock(trans, trans_pcie->rxq);
1818 /* Safely ignore these bits for debug checks below */
1819 inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
1821 /* HW RF KILL switch toggled */
1822 if (inta & CSR_INT_BIT_RF_KILL) {
1823 iwl_pcie_handle_rfkill_irq(trans);
1824 handled |= CSR_INT_BIT_RF_KILL;
1827 /* Chip got too hot and stopped itself */
1828 if (inta & CSR_INT_BIT_CT_KILL) {
1829 IWL_ERR(trans, "Microcode CT kill error detected.\n");
1830 isr_stats->ctkill++;
1831 handled |= CSR_INT_BIT_CT_KILL;
1834 /* Error detected by uCode */
1835 if (inta & CSR_INT_BIT_SW_ERR) {
1836 IWL_ERR(trans, "Microcode SW error detected. "
1837 " Restarting 0x%X.\n", inta);
1839 iwl_pcie_irq_handle_error(trans);
1840 handled |= CSR_INT_BIT_SW_ERR;
1843 /* uCode wakes up after power-down sleep */
1844 if (inta & CSR_INT_BIT_WAKEUP) {
1845 IWL_DEBUG_ISR(trans, "Wakeup interrupt\n");
1846 iwl_pcie_rxq_check_wrptr(trans);
1847 iwl_pcie_txq_check_wrptrs(trans);
1849 isr_stats->wakeup++;
1851 handled |= CSR_INT_BIT_WAKEUP;
1854 /* All uCode command responses, including Tx command responses,
1855 * Rx "responses" (frame-received notification), and other
1856 * notifications from uCode come through here*/
1857 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX |
1858 CSR_INT_BIT_RX_PERIODIC)) {
1859 IWL_DEBUG_ISR(trans, "Rx interrupt\n");
1860 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
1861 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
1862 iwl_write32(trans, CSR_FH_INT_STATUS,
1863 CSR_FH_INT_RX_MASK);
1865 if (inta & CSR_INT_BIT_RX_PERIODIC) {
1866 handled |= CSR_INT_BIT_RX_PERIODIC;
1868 CSR_INT, CSR_INT_BIT_RX_PERIODIC);
1870 /* Sending RX interrupt require many steps to be done in the
1872 * 1- write interrupt to current index in ICT table.
1874 * 3- update RX shared data to indicate last write index.
1875 * 4- send interrupt.
1876 * This could lead to RX race, driver could receive RX interrupt
1877 * but the shared data changes does not reflect this;
1878 * periodic interrupt will detect any dangling Rx activity.
1881 /* Disable periodic interrupt; we use it as just a one-shot. */
1882 iwl_write8(trans, CSR_INT_PERIODIC_REG,
1883 CSR_INT_PERIODIC_DIS);
1886 * Enable periodic interrupt in 8 msec only if we received
1887 * real RX interrupt (instead of just periodic int), to catch
1888 * any dangling Rx interrupt. If it was just the periodic
1889 * interrupt, there was no dangling Rx activity, and no need
1890 * to extend the periodic interrupt; one-shot is enough.
1892 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX))
1893 iwl_write8(trans, CSR_INT_PERIODIC_REG,
1894 CSR_INT_PERIODIC_ENA);
1899 iwl_pcie_rx_handle(trans, 0);
1903 /* This "Tx" DMA channel is used only for loading uCode */
1904 if (inta & CSR_INT_BIT_FH_TX) {
1905 iwl_write32(trans, CSR_FH_INT_STATUS, CSR_FH_INT_TX_MASK);
1906 IWL_DEBUG_ISR(trans, "uCode load interrupt\n");
1908 handled |= CSR_INT_BIT_FH_TX;
1909 /* Wake up uCode load routine, now that load is complete */
1910 trans_pcie->ucode_write_complete = true;
1911 wake_up(&trans_pcie->ucode_write_waitq);
1914 if (inta & ~handled) {
1915 IWL_ERR(trans, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
1916 isr_stats->unhandled++;
1919 if (inta & ~(trans_pcie->inta_mask)) {
1920 IWL_WARN(trans, "Disabled INTA bits 0x%08x were pending\n",
1921 inta & ~trans_pcie->inta_mask);
1924 spin_lock(&trans_pcie->irq_lock);
1925 /* only Re-enable all interrupt if disabled by irq */
1926 if (test_bit(STATUS_INT_ENABLED, &trans->status))
1927 _iwl_enable_interrupts(trans);
1928 /* we are loading the firmware, enable FH_TX interrupt only */
1929 else if (handled & CSR_INT_BIT_FH_TX)
1930 iwl_enable_fw_load_int(trans);
1931 /* Re-enable RF_KILL if it occurred */
1932 else if (handled & CSR_INT_BIT_RF_KILL)
1933 iwl_enable_rfkill_int(trans);
1934 spin_unlock(&trans_pcie->irq_lock);
1937 lock_map_release(&trans->sync_cmd_lockdep_map);
1941 /******************************************************************************
1945 ******************************************************************************/
1947 /* Free dram table */
1948 void iwl_pcie_free_ict(struct iwl_trans *trans)
1950 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1952 if (trans_pcie->ict_tbl) {
1953 dma_free_coherent(trans->dev, ICT_SIZE,
1954 trans_pcie->ict_tbl,
1955 trans_pcie->ict_tbl_dma);
1956 trans_pcie->ict_tbl = NULL;
1957 trans_pcie->ict_tbl_dma = 0;
1962 * allocate dram shared table, it is an aligned memory
1963 * block of ICT_SIZE.
1964 * also reset all data related to ICT table interrupt.
1966 int iwl_pcie_alloc_ict(struct iwl_trans *trans)
1968 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1970 trans_pcie->ict_tbl =
1971 dma_alloc_coherent(trans->dev, ICT_SIZE,
1972 &trans_pcie->ict_tbl_dma, GFP_KERNEL);
1973 if (!trans_pcie->ict_tbl)
1976 /* just an API sanity check ... it is guaranteed to be aligned */
1977 if (WARN_ON(trans_pcie->ict_tbl_dma & (ICT_SIZE - 1))) {
1978 iwl_pcie_free_ict(trans);
1985 /* Device is going up inform it about using ICT interrupt table,
1986 * also we need to tell the driver to start using ICT interrupt.
1988 void iwl_pcie_reset_ict(struct iwl_trans *trans)
1990 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1993 if (!trans_pcie->ict_tbl)
1996 spin_lock(&trans_pcie->irq_lock);
1997 _iwl_disable_interrupts(trans);
1999 memset(trans_pcie->ict_tbl, 0, ICT_SIZE);
2001 val = trans_pcie->ict_tbl_dma >> ICT_SHIFT;
2003 val |= CSR_DRAM_INT_TBL_ENABLE |
2004 CSR_DRAM_INIT_TBL_WRAP_CHECK |
2005 CSR_DRAM_INIT_TBL_WRITE_POINTER;
2007 IWL_DEBUG_ISR(trans, "CSR_DRAM_INT_TBL_REG =0x%x\n", val);
2009 iwl_write32(trans, CSR_DRAM_INT_TBL_REG, val);
2010 trans_pcie->use_ict = true;
2011 trans_pcie->ict_index = 0;
2012 iwl_write32(trans, CSR_INT, trans_pcie->inta_mask);
2013 _iwl_enable_interrupts(trans);
2014 spin_unlock(&trans_pcie->irq_lock);
2017 /* Device is going down disable ict interrupt usage */
2018 void iwl_pcie_disable_ict(struct iwl_trans *trans)
2020 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2022 spin_lock(&trans_pcie->irq_lock);
2023 trans_pcie->use_ict = false;
2024 spin_unlock(&trans_pcie->irq_lock);
2027 irqreturn_t iwl_pcie_isr(int irq, void *data)
2029 struct iwl_trans *trans = data;
2034 /* Disable (but don't clear!) interrupts here to avoid
2035 * back-to-back ISRs and sporadic interrupts from our NIC.
2036 * If we have something to service, the tasklet will re-enable ints.
2037 * If we *don't* have something, we'll re-enable before leaving here.
2039 iwl_write32(trans, CSR_INT_MASK, 0x00000000);
2041 return IRQ_WAKE_THREAD;
2044 irqreturn_t iwl_pcie_msix_isr(int irq, void *data)
2046 return IRQ_WAKE_THREAD;
2049 irqreturn_t iwl_pcie_irq_msix_handler(int irq, void *dev_id)
2051 struct msix_entry *entry = dev_id;
2052 struct iwl_trans_pcie *trans_pcie = iwl_pcie_get_trans_pcie(entry);
2053 struct iwl_trans *trans = trans_pcie->trans;
2054 struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
2055 u32 inta_fh, inta_hw;
2057 lock_map_acquire(&trans->sync_cmd_lockdep_map);
2059 spin_lock(&trans_pcie->irq_lock);
2060 inta_fh = iwl_read32(trans, CSR_MSIX_FH_INT_CAUSES_AD);
2061 inta_hw = iwl_read32(trans, CSR_MSIX_HW_INT_CAUSES_AD);
2063 * Clear causes registers to avoid being handling the same cause.
2065 iwl_write32(trans, CSR_MSIX_FH_INT_CAUSES_AD, inta_fh);
2066 iwl_write32(trans, CSR_MSIX_HW_INT_CAUSES_AD, inta_hw);
2067 spin_unlock(&trans_pcie->irq_lock);
2069 trace_iwlwifi_dev_irq_msix(trans->dev, entry, true, inta_fh, inta_hw);
2071 if (unlikely(!(inta_fh | inta_hw))) {
2072 IWL_DEBUG_ISR(trans, "Ignore interrupt, inta == 0\n");
2073 lock_map_release(&trans->sync_cmd_lockdep_map);
2077 if (iwl_have_debug_level(IWL_DL_ISR))
2078 IWL_DEBUG_ISR(trans, "ISR inta_fh 0x%08x, enabled 0x%08x\n",
2080 iwl_read32(trans, CSR_MSIX_FH_INT_MASK_AD));
2082 if ((trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_NON_RX) &&
2083 inta_fh & MSIX_FH_INT_CAUSES_Q0) {
2085 iwl_pcie_rx_handle(trans, 0);
2089 if ((trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS) &&
2090 inta_fh & MSIX_FH_INT_CAUSES_Q1) {
2092 iwl_pcie_rx_handle(trans, 1);
2096 /* This "Tx" DMA channel is used only for loading uCode */
2097 if (inta_fh & MSIX_FH_INT_CAUSES_D2S_CH0_NUM) {
2098 IWL_DEBUG_ISR(trans, "uCode load interrupt\n");
2101 * Wake up uCode load routine,
2102 * now that load is complete
2104 trans_pcie->ucode_write_complete = true;
2105 wake_up(&trans_pcie->ucode_write_waitq);
2108 /* Error detected by uCode */
2109 if ((inta_fh & MSIX_FH_INT_CAUSES_FH_ERR) ||
2110 (inta_hw & MSIX_HW_INT_CAUSES_REG_SW_ERR) ||
2111 (inta_hw & MSIX_HW_INT_CAUSES_REG_SW_ERR_V2)) {
2113 "Microcode SW error detected. Restarting 0x%X.\n",
2116 iwl_pcie_irq_handle_error(trans);
2119 /* After checking FH register check HW register */
2120 if (iwl_have_debug_level(IWL_DL_ISR))
2121 IWL_DEBUG_ISR(trans,
2122 "ISR inta_hw 0x%08x, enabled 0x%08x\n",
2124 iwl_read32(trans, CSR_MSIX_HW_INT_MASK_AD));
2126 /* Alive notification via Rx interrupt will do the real work */
2127 if (inta_hw & MSIX_HW_INT_CAUSES_REG_ALIVE) {
2128 IWL_DEBUG_ISR(trans, "Alive interrupt\n");
2130 if (trans->cfg->gen2) {
2131 /* We can restock, since firmware configured the RFH */
2132 iwl_pcie_rxmq_restock(trans, trans_pcie->rxq);
2136 if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_22560 &&
2137 inta_hw & MSIX_HW_INT_CAUSES_REG_IPC) {
2138 /* Reflect IML transfer status */
2139 int res = iwl_read32(trans, CSR_IML_RESP_ADDR);
2141 IWL_DEBUG_ISR(trans, "IML transfer status: %d\n", res);
2142 if (res == IWL_IMAGE_RESP_FAIL) {
2144 iwl_pcie_irq_handle_error(trans);
2146 } else if (inta_hw & MSIX_HW_INT_CAUSES_REG_WAKEUP) {
2147 /* uCode wakes up after power-down sleep */
2148 IWL_DEBUG_ISR(trans, "Wakeup interrupt\n");
2149 iwl_pcie_rxq_check_wrptr(trans);
2150 iwl_pcie_txq_check_wrptrs(trans);
2152 isr_stats->wakeup++;
2155 /* Chip got too hot and stopped itself */
2156 if (inta_hw & MSIX_HW_INT_CAUSES_REG_CT_KILL) {
2157 IWL_ERR(trans, "Microcode CT kill error detected.\n");
2158 isr_stats->ctkill++;
2161 /* HW RF KILL switch toggled */
2162 if (inta_hw & MSIX_HW_INT_CAUSES_REG_RF_KILL)
2163 iwl_pcie_handle_rfkill_irq(trans);
2165 if (inta_hw & MSIX_HW_INT_CAUSES_REG_HW_ERR) {
2167 "Hardware error detected. Restarting.\n");
2170 iwl_pcie_irq_handle_error(trans);
2173 iwl_pcie_clear_irq(trans, entry);
2175 lock_map_release(&trans->sync_cmd_lockdep_map);