1 /******************************************************************************
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
8 * Copyright(c) 2017 Intel Deutschland GmbH
9 * Copyright(c) 2018 Intel Corporation
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of version 2 of the GNU General Public License as
13 * published by the Free Software Foundation.
15 * This program is distributed in the hope that it will be useful, but
16 * WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 * General Public License for more details.
22 * Copyright(c) 2017 Intel Deutschland GmbH
23 * Copyright(c) 2018 Intel Corporation
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27 * modification, are permitted provided that the following conditions
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52 *****************************************************************************/
53 #include "iwl-trans.h"
55 #include "iwl-context-info.h"
56 #include "iwl-context-info-gen3.h"
61 * Start up NIC's basic functionality after it has been reset
62 * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop())
63 * NOTE: This does not load uCode nor start the embedded processor
65 int iwl_pcie_gen2_apm_init(struct iwl_trans *trans)
69 IWL_DEBUG_INFO(trans, "Init card's basic functions\n");
72 * Use "set_bit" below rather than "write", to preserve any hardware
73 * bits already set by default after reset.
77 * Disable L0s without affecting L1;
78 * don't wait for ICH L0s (ICH bug W/A)
80 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
81 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
83 /* Set FH wait threshold to maximum (HW error during stress W/A) */
84 iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
87 * Enable HAP INTA (interrupt from management bus) to
88 * wake device's PCI Express link L1a -> L0s
90 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
91 CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
93 iwl_pcie_apm_config(trans);
96 * Set "initialization complete" bit to move adapter from
97 * D0U* --> D0A* (powered-up active) state.
99 iwl_set_bit(trans, CSR_GP_CNTRL,
100 BIT(trans->cfg->csr->flag_init_done));
103 * Wait for clock stabilization; once stabilized, access to
104 * device-internal resources is supported, e.g. iwl_write_prph()
105 * and accesses to uCode SRAM.
107 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
108 BIT(trans->cfg->csr->flag_mac_clock_ready),
109 BIT(trans->cfg->csr->flag_mac_clock_ready),
112 IWL_DEBUG_INFO(trans, "Failed to init the card\n");
116 set_bit(STATUS_DEVICE_ENABLED, &trans->status);
121 static void iwl_pcie_gen2_apm_stop(struct iwl_trans *trans, bool op_mode_leave)
123 IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n");
126 if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status))
127 iwl_pcie_gen2_apm_init(trans);
129 /* inform ME that we are leaving */
130 iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
131 CSR_RESET_LINK_PWR_MGMT_DISABLED);
132 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
133 CSR_HW_IF_CONFIG_REG_PREPARE |
134 CSR_HW_IF_CONFIG_REG_ENABLE_PME);
136 iwl_clear_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
137 CSR_RESET_LINK_PWR_MGMT_DISABLED);
141 clear_bit(STATUS_DEVICE_ENABLED, &trans->status);
143 /* Stop device's DMA activity */
144 iwl_pcie_apm_stop_master(trans);
146 iwl_trans_sw_reset(trans);
149 * Clear "initialization complete" bit to move adapter from
150 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
152 iwl_clear_bit(trans, CSR_GP_CNTRL,
153 BIT(trans->cfg->csr->flag_init_done));
156 void _iwl_trans_pcie_gen2_stop_device(struct iwl_trans *trans, bool low_power)
158 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
160 lockdep_assert_held(&trans_pcie->mutex);
162 if (trans_pcie->is_down)
165 trans_pcie->is_down = true;
167 /* Stop dbgc before stopping device */
168 _iwl_fw_dbg_stop_recording(trans, NULL);
170 /* tell the device to stop sending interrupts */
171 iwl_disable_interrupts(trans);
173 /* device going down, Stop using ICT table */
174 iwl_pcie_disable_ict(trans);
177 * If a HW restart happens during firmware loading,
178 * then the firmware loading might call this function
179 * and later it might be called again due to the
180 * restart. So don't process again if the device is
183 if (test_and_clear_bit(STATUS_DEVICE_ENABLED, &trans->status)) {
184 IWL_DEBUG_INFO(trans,
185 "DEVICE_ENABLED bit was set and is now cleared\n");
186 iwl_pcie_gen2_tx_stop(trans);
187 iwl_pcie_rx_stop(trans);
190 iwl_pcie_ctxt_info_free_paging(trans);
191 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_22560)
192 iwl_pcie_ctxt_info_gen3_free(trans);
194 iwl_pcie_ctxt_info_free(trans);
196 /* Make sure (redundant) we've released our request to stay awake */
197 iwl_clear_bit(trans, CSR_GP_CNTRL,
198 BIT(trans->cfg->csr->flag_mac_access_req));
200 /* Stop the device, and put it in low power state */
201 iwl_pcie_gen2_apm_stop(trans, false);
203 iwl_trans_sw_reset(trans);
206 * Upon stop, the IVAR table gets erased, so msi-x won't
207 * work. This causes a bug in RF-KILL flows, since the interrupt
208 * that enables radio won't fire on the correct irq, and the
209 * driver won't be able to handle the interrupt.
210 * Configure the IVAR table again after reset.
212 iwl_pcie_conf_msix_hw(trans_pcie);
215 * Upon stop, the APM issues an interrupt if HW RF kill is set.
216 * This is a bug in certain verions of the hardware.
217 * Certain devices also keep sending HW RF kill interrupt all
218 * the time, unless the interrupt is ACKed even if the interrupt
219 * should be masked. Re-ACK all the interrupts here.
221 iwl_disable_interrupts(trans);
223 /* clear all status bits */
224 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
225 clear_bit(STATUS_INT_ENABLED, &trans->status);
226 clear_bit(STATUS_TPOWER_PMI, &trans->status);
229 * Even if we stop the HW, we still want the RF kill
232 iwl_enable_rfkill_int(trans);
234 /* re-take ownership to prevent other users from stealing the device */
235 iwl_pcie_prepare_card_hw(trans);
238 void iwl_trans_pcie_gen2_stop_device(struct iwl_trans *trans, bool low_power)
240 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
243 mutex_lock(&trans_pcie->mutex);
244 trans_pcie->opmode_down = true;
245 was_in_rfkill = test_bit(STATUS_RFKILL_OPMODE, &trans->status);
246 _iwl_trans_pcie_gen2_stop_device(trans, low_power);
247 iwl_trans_pcie_handle_stop_rfkill(trans, was_in_rfkill);
248 mutex_unlock(&trans_pcie->mutex);
251 static int iwl_pcie_gen2_nic_init(struct iwl_trans *trans)
253 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
255 /* TODO: most of the logic can be removed in A0 - but not in Z0 */
256 spin_lock(&trans_pcie->irq_lock);
257 iwl_pcie_gen2_apm_init(trans);
258 spin_unlock(&trans_pcie->irq_lock);
260 iwl_op_mode_nic_config(trans->op_mode);
262 /* Allocate the RX queue, or reset if it is already allocated */
263 if (iwl_pcie_gen2_rx_init(trans))
266 /* Allocate or reset and init all Tx and Command queues */
267 if (iwl_pcie_gen2_tx_init(trans, trans_pcie->cmd_queue, TFD_CMD_SLOTS))
270 /* enable shadow regs in HW */
271 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF);
272 IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n");
277 void iwl_trans_pcie_gen2_fw_alive(struct iwl_trans *trans, u32 scd_addr)
279 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
281 iwl_pcie_reset_ict(trans);
283 /* make sure all queue are not stopped/used */
284 memset(trans_pcie->queue_stopped, 0, sizeof(trans_pcie->queue_stopped));
285 memset(trans_pcie->queue_used, 0, sizeof(trans_pcie->queue_used));
287 /* now that we got alive we can free the fw image & the context info.
288 * paging memory cannot be freed included since FW will still use it
290 iwl_pcie_ctxt_info_free(trans);
293 int iwl_trans_pcie_gen2_start_fw(struct iwl_trans *trans,
294 const struct fw_img *fw, bool run_in_rfkill)
296 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
300 /* This may fail if AMT took ownership of the device */
301 if (iwl_pcie_prepare_card_hw(trans)) {
302 IWL_WARN(trans, "Exit HW not ready\n");
307 iwl_enable_rfkill_int(trans);
309 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
312 * We enabled the RF-Kill interrupt and the handler may very
313 * well be running. Disable the interrupts to make sure no other
314 * interrupt can be fired.
316 iwl_disable_interrupts(trans);
318 /* Make sure it finished running */
319 iwl_pcie_synchronize_irqs(trans);
321 mutex_lock(&trans_pcie->mutex);
323 /* If platform's RF_KILL switch is NOT set to KILL */
324 hw_rfkill = iwl_pcie_check_hw_rf_kill(trans);
325 if (hw_rfkill && !run_in_rfkill) {
330 /* Someone called stop_device, don't try to start_fw */
331 if (trans_pcie->is_down) {
333 "Can't start_fw since the HW hasn't been started\n");
338 /* make sure rfkill handshake bits are cleared */
339 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
340 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR,
341 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
343 /* clear (again), then enable host interrupts */
344 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
346 ret = iwl_pcie_gen2_nic_init(trans);
348 IWL_ERR(trans, "Unable to init nic\n");
352 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_22560)
353 ret = iwl_pcie_ctxt_info_gen3_init(trans, fw);
355 ret = iwl_pcie_ctxt_info_init(trans, fw);
359 /* re-check RF-Kill state since we may have missed the interrupt */
360 hw_rfkill = iwl_pcie_check_hw_rf_kill(trans);
361 if (hw_rfkill && !run_in_rfkill)
365 mutex_unlock(&trans_pcie->mutex);