1 /******************************************************************************
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
8 * Copyright(c) 2017 Intel Deutschland GmbH
9 * Copyright(c) 2018 Intel Corporation
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of version 2 of the GNU General Public License as
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15 * This program is distributed in the hope that it will be useful, but
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18 * General Public License for more details.
22 * Copyright(c) 2017 Intel Deutschland GmbH
23 * Copyright(c) 2018 Intel Corporation
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52 *****************************************************************************/
53 #include "iwl-trans.h"
55 #include "iwl-context-info.h"
59 * Start up NIC's basic functionality after it has been reset
60 * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop())
61 * NOTE: This does not load uCode nor start the embedded processor
63 static int iwl_pcie_gen2_apm_init(struct iwl_trans *trans)
67 IWL_DEBUG_INFO(trans, "Init card's basic functions\n");
70 * Use "set_bit" below rather than "write", to preserve any hardware
71 * bits already set by default after reset.
75 * Disable L0s without affecting L1;
76 * don't wait for ICH L0s (ICH bug W/A)
78 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
79 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
81 /* Set FH wait threshold to maximum (HW error during stress W/A) */
82 iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
85 * Enable HAP INTA (interrupt from management bus) to
86 * wake device's PCI Express link L1a -> L0s
88 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
89 CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
91 iwl_pcie_apm_config(trans);
94 * Set "initialization complete" bit to move adapter from
95 * D0U* --> D0A* (powered-up active) state.
97 iwl_set_bit(trans, CSR_GP_CNTRL,
98 BIT(trans->cfg->csr->flag_init_done));
101 * Wait for clock stabilization; once stabilized, access to
102 * device-internal resources is supported, e.g. iwl_write_prph()
103 * and accesses to uCode SRAM.
105 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
106 BIT(trans->cfg->csr->flag_mac_clock_ready),
107 BIT(trans->cfg->csr->flag_mac_clock_ready),
110 IWL_DEBUG_INFO(trans, "Failed to init the card\n");
114 set_bit(STATUS_DEVICE_ENABLED, &trans->status);
119 static void iwl_pcie_gen2_apm_stop(struct iwl_trans *trans, bool op_mode_leave)
121 IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n");
124 if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status))
125 iwl_pcie_gen2_apm_init(trans);
127 /* inform ME that we are leaving */
128 iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
129 CSR_RESET_LINK_PWR_MGMT_DISABLED);
130 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
131 CSR_HW_IF_CONFIG_REG_PREPARE |
132 CSR_HW_IF_CONFIG_REG_ENABLE_PME);
134 iwl_clear_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
135 CSR_RESET_LINK_PWR_MGMT_DISABLED);
139 clear_bit(STATUS_DEVICE_ENABLED, &trans->status);
141 /* Stop device's DMA activity */
142 iwl_pcie_apm_stop_master(trans);
144 iwl_trans_sw_reset(trans);
147 * Clear "initialization complete" bit to move adapter from
148 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
150 iwl_clear_bit(trans, CSR_GP_CNTRL,
151 BIT(trans->cfg->csr->flag_init_done));
154 void _iwl_trans_pcie_gen2_stop_device(struct iwl_trans *trans, bool low_power)
156 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
158 lockdep_assert_held(&trans_pcie->mutex);
160 if (trans_pcie->is_down)
163 trans_pcie->is_down = true;
165 /* Stop dbgc before stopping device */
166 iwl_write_prph(trans, DBGC_IN_SAMPLE, 0);
168 iwl_write_prph(trans, DBGC_OUT_CTRL, 0);
170 /* tell the device to stop sending interrupts */
171 iwl_disable_interrupts(trans);
173 /* device going down, Stop using ICT table */
174 iwl_pcie_disable_ict(trans);
177 * If a HW restart happens during firmware loading,
178 * then the firmware loading might call this function
179 * and later it might be called again due to the
180 * restart. So don't process again if the device is
183 if (test_and_clear_bit(STATUS_DEVICE_ENABLED, &trans->status)) {
184 IWL_DEBUG_INFO(trans,
185 "DEVICE_ENABLED bit was set and is now cleared\n");
186 iwl_pcie_gen2_tx_stop(trans);
187 iwl_pcie_rx_stop(trans);
190 iwl_pcie_ctxt_info_free_paging(trans);
191 iwl_pcie_ctxt_info_free(trans);
193 /* Make sure (redundant) we've released our request to stay awake */
194 iwl_clear_bit(trans, CSR_GP_CNTRL,
195 BIT(trans->cfg->csr->flag_mac_access_req));
197 /* Stop the device, and put it in low power state */
198 iwl_pcie_gen2_apm_stop(trans, false);
200 iwl_trans_sw_reset(trans);
203 * Upon stop, the IVAR table gets erased, so msi-x won't
204 * work. This causes a bug in RF-KILL flows, since the interrupt
205 * that enables radio won't fire on the correct irq, and the
206 * driver won't be able to handle the interrupt.
207 * Configure the IVAR table again after reset.
209 iwl_pcie_conf_msix_hw(trans_pcie);
212 * Upon stop, the APM issues an interrupt if HW RF kill is set.
213 * This is a bug in certain verions of the hardware.
214 * Certain devices also keep sending HW RF kill interrupt all
215 * the time, unless the interrupt is ACKed even if the interrupt
216 * should be masked. Re-ACK all the interrupts here.
218 iwl_disable_interrupts(trans);
220 /* clear all status bits */
221 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
222 clear_bit(STATUS_INT_ENABLED, &trans->status);
223 clear_bit(STATUS_TPOWER_PMI, &trans->status);
226 * Even if we stop the HW, we still want the RF kill
229 iwl_enable_rfkill_int(trans);
231 /* re-take ownership to prevent other users from stealing the device */
232 iwl_pcie_prepare_card_hw(trans);
235 void iwl_trans_pcie_gen2_stop_device(struct iwl_trans *trans, bool low_power)
237 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
240 mutex_lock(&trans_pcie->mutex);
241 trans_pcie->opmode_down = true;
242 was_in_rfkill = test_bit(STATUS_RFKILL_OPMODE, &trans->status);
243 _iwl_trans_pcie_gen2_stop_device(trans, low_power);
244 iwl_trans_pcie_handle_stop_rfkill(trans, was_in_rfkill);
245 mutex_unlock(&trans_pcie->mutex);
248 static int iwl_pcie_gen2_nic_init(struct iwl_trans *trans)
250 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
252 /* TODO: most of the logic can be removed in A0 - but not in Z0 */
253 spin_lock(&trans_pcie->irq_lock);
254 iwl_pcie_gen2_apm_init(trans);
255 spin_unlock(&trans_pcie->irq_lock);
257 iwl_op_mode_nic_config(trans->op_mode);
259 /* Allocate the RX queue, or reset if it is already allocated */
260 if (iwl_pcie_gen2_rx_init(trans))
263 /* Allocate or reset and init all Tx and Command queues */
264 if (iwl_pcie_gen2_tx_init(trans))
267 /* enable shadow regs in HW */
268 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF);
269 IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n");
274 void iwl_trans_pcie_gen2_fw_alive(struct iwl_trans *trans, u32 scd_addr)
276 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
278 iwl_pcie_reset_ict(trans);
280 /* make sure all queue are not stopped/used */
281 memset(trans_pcie->queue_stopped, 0, sizeof(trans_pcie->queue_stopped));
282 memset(trans_pcie->queue_used, 0, sizeof(trans_pcie->queue_used));
284 /* now that we got alive we can free the fw image & the context info.
285 * paging memory cannot be freed included since FW will still use it
287 iwl_pcie_ctxt_info_free(trans);
290 int iwl_trans_pcie_gen2_start_fw(struct iwl_trans *trans,
291 const struct fw_img *fw, bool run_in_rfkill)
293 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
297 /* This may fail if AMT took ownership of the device */
298 if (iwl_pcie_prepare_card_hw(trans)) {
299 IWL_WARN(trans, "Exit HW not ready\n");
304 iwl_enable_rfkill_int(trans);
306 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
309 * We enabled the RF-Kill interrupt and the handler may very
310 * well be running. Disable the interrupts to make sure no other
311 * interrupt can be fired.
313 iwl_disable_interrupts(trans);
315 /* Make sure it finished running */
316 iwl_pcie_synchronize_irqs(trans);
318 mutex_lock(&trans_pcie->mutex);
320 /* If platform's RF_KILL switch is NOT set to KILL */
321 hw_rfkill = iwl_pcie_check_hw_rf_kill(trans);
322 if (hw_rfkill && !run_in_rfkill) {
327 /* Someone called stop_device, don't try to start_fw */
328 if (trans_pcie->is_down) {
330 "Can't start_fw since the HW hasn't been started\n");
335 /* make sure rfkill handshake bits are cleared */
336 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
337 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR,
338 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
340 /* clear (again), then enable host interrupts */
341 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
343 ret = iwl_pcie_gen2_nic_init(trans);
345 IWL_ERR(trans, "Unable to init nic\n");
349 ret = iwl_pcie_ctxt_info_init(trans, fw);
353 /* re-check RF-Kill state since we may have missed the interrupt */
354 hw_rfkill = iwl_pcie_check_hw_rf_kill(trans);
355 if (hw_rfkill && !run_in_rfkill)
359 mutex_unlock(&trans_pcie->mutex);