drivers/net/wireless/intel/iwlwifi/pcie/trans.c

   1 /******************************************************************************
   2  *
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   4  * redistributing this file, you may do so under either license.
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   6  * GPL LICENSE SUMMARY
   7  *
   8  * Copyright(c) 2007 - 2015 Intel Corporation. All rights reserved.
   9  * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
  10  * Copyright(c) 2016 - 2017 Intel Deutschland GmbH
  11  * Copyright(c) 2018 Intel Corporation
  12  *
  13  * This program is free software; you can redistribute it and/or modify
  14  * it under the terms of version 2 of the GNU General Public License as
  15  * published by the Free Software Foundation.
  16  *
  17  * This program is distributed in the hope that it will be useful, but
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  31  *  Intel Linux Wireless <linuxwifi@intel.com>
  32  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
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  35  *
  36  * Copyright(c) 2005 - 2015 Intel Corporation. All rights reserved.
  37  * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
  38  * Copyright(c) 2016 - 2017 Intel Deutschland GmbH
  39  * Copyright(c) 2018 Intel Corporation
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  43  * modification, are permitted provided that the following conditions
  44  * are met:
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  51  *    distribution.
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  53  *    contributors may be used to endorse or promote products derived
  54  *    from this software without specific prior written permission.
  55  *
  56  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  57  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  58  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  59  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  60  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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  66  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  67  *
  68  *****************************************************************************/
  69 #include <linux/pci.h>
  70 #include <linux/pci-aspm.h>
  71 #include <linux/interrupt.h>
  72 #include <linux/debugfs.h>
  73 #include <linux/sched.h>
  74 #include <linux/bitops.h>
  75 #include <linux/gfp.h>
  76 #include <linux/vmalloc.h>
  77 #include <linux/pm_runtime.h>
  78
  79 #include "iwl-drv.h"
  80 #include "iwl-trans.h"
  81 #include "iwl-csr.h"
  82 #include "iwl-prph.h"
  83 #include "iwl-scd.h"
  84 #include "iwl-agn-hw.h"
  85 #include "fw/error-dump.h"
  86 #include "internal.h"
  87 #include "iwl-fh.h"
  88
  89 /* extended range in FW SRAM */
  90 #define IWL_FW_MEM_EXTENDED_START       0x40000
  91 #define IWL_FW_MEM_EXTENDED_END         0x57FFF
  92
  93 static void iwl_trans_pcie_dump_regs(struct iwl_trans *trans)
  94 {
  95 #define PCI_DUMP_SIZE   64
  96 #define PREFIX_LEN      32
  97         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
  98         struct pci_dev *pdev = trans_pcie->pci_dev;
  99         u32 i, pos, alloc_size, *ptr, *buf;
 100         char *prefix;
 101
 102         if (trans_pcie->pcie_dbg_dumped_once)
 103                 return;
 104
 105         /* Should be a multiple of 4 */
 106         BUILD_BUG_ON(PCI_DUMP_SIZE > 4096 || PCI_DUMP_SIZE & 0x3);
 107         /* Alloc a max size buffer */
 108         if (PCI_ERR_ROOT_ERR_SRC +  4 > PCI_DUMP_SIZE)
 109                 alloc_size = PCI_ERR_ROOT_ERR_SRC +  4 + PREFIX_LEN;
 110         else
 111                 alloc_size = PCI_DUMP_SIZE + PREFIX_LEN;
 112         buf = kmalloc(alloc_size, GFP_ATOMIC);
 113         if (!buf)
 114                 return;
 115         prefix = (char *)buf + alloc_size - PREFIX_LEN;
 116
 117         IWL_ERR(trans, "iwlwifi transaction failed, dumping registers\n");
 118
 119         /* Print wifi device registers */
 120         sprintf(prefix, "iwlwifi %s: ", pci_name(pdev));
 121         IWL_ERR(trans, "iwlwifi device config registers:\n");
 122         for (i = 0, ptr = buf; i < PCI_DUMP_SIZE; i += 4, ptr++)
 123                 if (pci_read_config_dword(pdev, i, ptr))
 124                         goto err_read;
 125         print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0);
 126
 127         IWL_ERR(trans, "iwlwifi device memory mapped registers:\n");
 128         for (i = 0, ptr = buf; i < PCI_DUMP_SIZE; i += 4, ptr++)
 129                 *ptr = iwl_read32(trans, i);
 130         print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0);
 131
 132         pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR);
 133         if (pos) {
 134                 IWL_ERR(trans, "iwlwifi device AER capability structure:\n");
 135                 for (i = 0, ptr = buf; i < PCI_ERR_ROOT_COMMAND; i += 4, ptr++)
 136                         if (pci_read_config_dword(pdev, pos + i, ptr))
 137                                 goto err_read;
 138                 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET,
 139                                32, 4, buf, i, 0);
 140         }
 141
 142         /* Print parent device registers next */
 143         if (!pdev->bus->self)
 144                 goto out;
 145
 146         pdev = pdev->bus->self;
 147         sprintf(prefix, "iwlwifi %s: ", pci_name(pdev));
 148
 149         IWL_ERR(trans, "iwlwifi parent port (%s) config registers:\n",
 150                 pci_name(pdev));
 151         for (i = 0, ptr = buf; i < PCI_DUMP_SIZE; i += 4, ptr++)
 152                 if (pci_read_config_dword(pdev, i, ptr))
 153                         goto err_read;
 154         print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0);
 155
 156         /* Print root port AER registers */
 157         pos = 0;
 158         pdev = pcie_find_root_port(pdev);
 159         if (pdev)
 160                 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR);
 161         if (pos) {
 162                 IWL_ERR(trans, "iwlwifi root port (%s) AER cap structure:\n",
 163                         pci_name(pdev));
 164                 sprintf(prefix, "iwlwifi %s: ", pci_name(pdev));
 165                 for (i = 0, ptr = buf; i <= PCI_ERR_ROOT_ERR_SRC; i += 4, ptr++)
 166                         if (pci_read_config_dword(pdev, pos + i, ptr))
 167                                 goto err_read;
 168                 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32,
 169                                4, buf, i, 0);
 170         }
 171         goto out;
 172
 173 err_read:
 174         print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0);
 175         IWL_ERR(trans, "Read failed at 0x%X\n", i);
 176 out:
 177         trans_pcie->pcie_dbg_dumped_once = 1;
 178         kfree(buf);
 179 }
 180
 181 static void iwl_trans_pcie_sw_reset(struct iwl_trans *trans)
 182 {
 183         /* Reset entire device - do controller reset (results in SHRD_HW_RST) */
 184         iwl_set_bit(trans, trans->cfg->csr->addr_sw_reset,
 185                     BIT(trans->cfg->csr->flag_sw_reset));
 186         usleep_range(5000, 6000);
 187 }
 188
 189 static void iwl_pcie_free_fw_monitor(struct iwl_trans *trans)
 190 {
 191         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 192
 193         if (!trans_pcie->fw_mon_page)
 194                 return;
 195
 196         dma_unmap_page(trans->dev, trans_pcie->fw_mon_phys,
 197                        trans_pcie->fw_mon_size, DMA_FROM_DEVICE);
 198         __free_pages(trans_pcie->fw_mon_page,
 199                      get_order(trans_pcie->fw_mon_size));
 200         trans_pcie->fw_mon_page = NULL;
 201         trans_pcie->fw_mon_phys = 0;
 202         trans_pcie->fw_mon_size = 0;
 203 }
 204
 205 static void iwl_pcie_alloc_fw_monitor(struct iwl_trans *trans, u8 max_power)
 206 {
 207         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 208         struct page *page = NULL;
 209         dma_addr_t phys;
 210         u32 size = 0;
 211         u8 power;
 212
 213         if (!max_power) {
 214                 /* default max_power is maximum */
 215                 max_power = 26;
 216         } else {
 217                 max_power += 11;
 218         }
 219
 220         if (WARN(max_power > 26,
 221                  "External buffer size for monitor is too big %d, check the FW TLV\n",
 222                  max_power))
 223                 return;
 224
 225         if (trans_pcie->fw_mon_page) {
 226                 dma_sync_single_for_device(trans->dev, trans_pcie->fw_mon_phys,
 227                                            trans_pcie->fw_mon_size,
 228                                            DMA_FROM_DEVICE);
 229                 return;
 230         }
 231
 232         phys = 0;
 233         for (power = max_power; power >= 11; power--) {
 234                 int order;
 235
 236                 size = BIT(power);
 237                 order = get_order(size);
 238                 page = alloc_pages(__GFP_COMP | __GFP_NOWARN | __GFP_ZERO,
 239                                    order);
 240                 if (!page)
 241                         continue;
 242
 243                 phys = dma_map_page(trans->dev, page, 0, PAGE_SIZE << order,
 244                                     DMA_FROM_DEVICE);
 245                 if (dma_mapping_error(trans->dev, phys)) {
 246                         __free_pages(page, order);
 247                         page = NULL;
 248                         continue;
 249                 }
 250                 IWL_INFO(trans,
 251                          "Allocated 0x%08x bytes (order %d) for firmware monitor.\n",
 252                          size, order);
 253                 break;
 254         }
 255
 256         if (WARN_ON_ONCE(!page))
 257                 return;
 258
 259         if (power != max_power)
 260                 IWL_ERR(trans,
 261                         "Sorry - debug buffer is only %luK while you requested %luK\n",
 262                         (unsigned long)BIT(power - 10),
 263                         (unsigned long)BIT(max_power - 10));
 264
 265         trans_pcie->fw_mon_page = page;
 266         trans_pcie->fw_mon_phys = phys;
 267         trans_pcie->fw_mon_size = size;
 268 }
 269
 270 static u32 iwl_trans_pcie_read_shr(struct iwl_trans *trans, u32 reg)
 271 {
 272         iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
 273                     ((reg & 0x0000ffff) | (2 << 28)));
 274         return iwl_read32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG);
 275 }
 276
 277 static void iwl_trans_pcie_write_shr(struct iwl_trans *trans, u32 reg, u32 val)
 278 {
 279         iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG, val);
 280         iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
 281                     ((reg & 0x0000ffff) | (3 << 28)));
 282 }
 283
 284 static void iwl_pcie_set_pwr(struct iwl_trans *trans, bool vaux)
 285 {
 286         if (trans->cfg->apmg_not_supported)
 287                 return;
 288
 289         if (vaux && pci_pme_capable(to_pci_dev(trans->dev), PCI_D3cold))
 290                 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
 291                                        APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
 292                                        ~APMG_PS_CTRL_MSK_PWR_SRC);
 293         else
 294                 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
 295                                        APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
 296                                        ~APMG_PS_CTRL_MSK_PWR_SRC);
 297 }
 298
 299 /* PCI registers */
 300 #define PCI_CFG_RETRY_TIMEOUT   0x041
 301
 302 void iwl_pcie_apm_config(struct iwl_trans *trans)
 303 {
 304         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 305         u16 lctl;
 306         u16 cap;
 307
 308         /*
 309          * HW bug W/A for instability in PCIe bus L0S->L1 transition.
 310          * Check if BIOS (or OS) enabled L1-ASPM on this device.
 311          * If so (likely), disable L0S, so device moves directly L0->L1;
 312          *    costs negligible amount of power savings.
 313          * If not (unlikely), enable L0S, so there is at least some
 314          *    power savings, even without L1.
 315          */
 316         pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl);
 317         if (lctl & PCI_EXP_LNKCTL_ASPM_L1)
 318                 iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
 319         else
 320                 iwl_clear_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
 321         trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S);
 322
 323         pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_DEVCTL2, &cap);
 324         trans->ltr_enabled = cap & PCI_EXP_DEVCTL2_LTR_EN;
 325         IWL_DEBUG_POWER(trans, "L1 %sabled - LTR %sabled\n",
 326                         (lctl & PCI_EXP_LNKCTL_ASPM_L1) ? "En" : "Dis",
 327                         trans->ltr_enabled ? "En" : "Dis");
 328 }
 329
 330 /*
 331  * Start up NIC's basic functionality after it has been reset
 332  * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop())
 333  * NOTE:  This does not load uCode nor start the embedded processor
 334  */
 335 static int iwl_pcie_apm_init(struct iwl_trans *trans)
 336 {
 337         int ret;
 338
 339         IWL_DEBUG_INFO(trans, "Init card's basic functions\n");
 340
 341         /*
 342          * Use "set_bit" below rather than "write", to preserve any hardware
 343          * bits already set by default after reset.
 344          */
 345
 346         /* Disable L0S exit timer (platform NMI Work/Around) */
 347         if (trans->cfg->device_family < IWL_DEVICE_FAMILY_8000)
 348                 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
 349                             CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
 350
 351         /*
 352          * Disable L0s without affecting L1;
 353          *  don't wait for ICH L0s (ICH bug W/A)
 354          */
 355         iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
 356                     CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
 357
 358         /* Set FH wait threshold to maximum (HW error during stress W/A) */
 359         iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
 360
 361         /*
 362          * Enable HAP INTA (interrupt from management bus) to
 363          * wake device's PCI Express link L1a -> L0s
 364          */
 365         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 366                     CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
 367
 368         iwl_pcie_apm_config(trans);
 369
 370         /* Configure analog phase-lock-loop before activating to D0A */
 371         if (trans->cfg->base_params->pll_cfg)
 372                 iwl_set_bit(trans, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL);
 373
 374         /*
 375          * Set "initialization complete" bit to move adapter from
 376          * D0U* --> D0A* (powered-up active) state.
 377          */
 378         iwl_set_bit(trans, CSR_GP_CNTRL,
 379                     BIT(trans->cfg->csr->flag_init_done));
 380
 381         /*
 382          * Wait for clock stabilization; once stabilized, access to
 383          * device-internal resources is supported, e.g. iwl_write_prph()
 384          * and accesses to uCode SRAM.
 385          */
 386         ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
 387                            BIT(trans->cfg->csr->flag_mac_clock_ready),
 388                            BIT(trans->cfg->csr->flag_mac_clock_ready),
 389                            25000);
 390         if (ret < 0) {
 391                 IWL_ERR(trans, "Failed to init the card\n");
 392                 return ret;
 393         }
 394
 395         if (trans->cfg->host_interrupt_operation_mode) {
 396                 /*
 397                  * This is a bit of an abuse - This is needed for 7260 / 3160
 398                  * only check host_interrupt_operation_mode even if this is
 399                  * not related to host_interrupt_operation_mode.
 400                  *
 401                  * Enable the oscillator to count wake up time for L1 exit. This
 402                  * consumes slightly more power (100uA) - but allows to be sure
 403                  * that we wake up from L1 on time.
 404                  *
 405                  * This looks weird: read twice the same register, discard the
 406                  * value, set a bit, and yet again, read that same register
 407                  * just to discard the value. But that's the way the hardware
 408                  * seems to like it.
 409                  */
 410                 iwl_read_prph(trans, OSC_CLK);
 411                 iwl_read_prph(trans, OSC_CLK);
 412                 iwl_set_bits_prph(trans, OSC_CLK, OSC_CLK_FORCE_CONTROL);
 413                 iwl_read_prph(trans, OSC_CLK);
 414                 iwl_read_prph(trans, OSC_CLK);
 415         }
 416
 417         /*
 418          * Enable DMA clock and wait for it to stabilize.
 419          *
 420          * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0"
 421          * bits do not disable clocks.  This preserves any hardware
 422          * bits already set by default in "CLK_CTRL_REG" after reset.
 423          */
 424         if (!trans->cfg->apmg_not_supported) {
 425                 iwl_write_prph(trans, APMG_CLK_EN_REG,
 426                                APMG_CLK_VAL_DMA_CLK_RQT);
 427                 udelay(20);
 428
 429                 /* Disable L1-Active */
 430                 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
 431                                   APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
 432
 433                 /* Clear the interrupt in APMG if the NIC is in RFKILL */
 434                 iwl_write_prph(trans, APMG_RTC_INT_STT_REG,
 435                                APMG_RTC_INT_STT_RFKILL);
 436         }
 437
 438         set_bit(STATUS_DEVICE_ENABLED, &trans->status);
 439
 440         return 0;
 441 }
 442
 443 /*
 444  * Enable LP XTAL to avoid HW bug where device may consume much power if
 445  * FW is not loaded after device reset. LP XTAL is disabled by default
 446  * after device HW reset. Do it only if XTAL is fed by internal source.
 447  * Configure device's "persistence" mode to avoid resetting XTAL again when
 448  * SHRD_HW_RST occurs in S3.
 449  */
 450 static void iwl_pcie_apm_lp_xtal_enable(struct iwl_trans *trans)
 451 {
 452         int ret;
 453         u32 apmg_gp1_reg;
 454         u32 apmg_xtal_cfg_reg;
 455         u32 dl_cfg_reg;
 456
 457         /* Force XTAL ON */
 458         __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
 459                                  CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
 460
 461         iwl_trans_pcie_sw_reset(trans);
 462
 463         /*
 464          * Set "initialization complete" bit to move adapter from
 465          * D0U* --> D0A* (powered-up active) state.
 466          */
 467         iwl_set_bit(trans, CSR_GP_CNTRL,
 468                     BIT(trans->cfg->csr->flag_init_done));
 469
 470         /*
 471          * Wait for clock stabilization; once stabilized, access to
 472          * device-internal resources is possible.
 473          */
 474         ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
 475                            BIT(trans->cfg->csr->flag_mac_clock_ready),
 476                            BIT(trans->cfg->csr->flag_mac_clock_ready),
 477                            25000);
 478         if (WARN_ON(ret < 0)) {
 479                 IWL_ERR(trans, "Access time out - failed to enable LP XTAL\n");
 480                 /* Release XTAL ON request */
 481                 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
 482                                            CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
 483                 return;
 484         }
 485
 486         /*
 487          * Clear "disable persistence" to avoid LP XTAL resetting when
 488          * SHRD_HW_RST is applied in S3.
 489          */
 490         iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG,
 491                                     APMG_PCIDEV_STT_VAL_PERSIST_DIS);
 492
 493         /*
 494          * Force APMG XTAL to be active to prevent its disabling by HW
 495          * caused by APMG idle state.
 496          */
 497         apmg_xtal_cfg_reg = iwl_trans_pcie_read_shr(trans,
 498                                                     SHR_APMG_XTAL_CFG_REG);
 499         iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG,
 500                                  apmg_xtal_cfg_reg |
 501                                  SHR_APMG_XTAL_CFG_XTAL_ON_REQ);
 502
 503         iwl_trans_pcie_sw_reset(trans);
 504
 505         /* Enable LP XTAL by indirect access through CSR */
 506         apmg_gp1_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_GP1_REG);
 507         iwl_trans_pcie_write_shr(trans, SHR_APMG_GP1_REG, apmg_gp1_reg |
 508                                  SHR_APMG_GP1_WF_XTAL_LP_EN |
 509                                  SHR_APMG_GP1_CHICKEN_BIT_SELECT);
 510
 511         /* Clear delay line clock power up */
 512         dl_cfg_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_DL_CFG_REG);
 513         iwl_trans_pcie_write_shr(trans, SHR_APMG_DL_CFG_REG, dl_cfg_reg &
 514                                  ~SHR_APMG_DL_CFG_DL_CLOCK_POWER_UP);
 515
 516         /*
 517          * Enable persistence mode to avoid LP XTAL resetting when
 518          * SHRD_HW_RST is applied in S3.
 519          */
 520         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 521                     CSR_HW_IF_CONFIG_REG_PERSIST_MODE);
 522
 523         /*
 524          * Clear "initialization complete" bit to move adapter from
 525          * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
 526          */
 527         iwl_clear_bit(trans, CSR_GP_CNTRL,
 528                       BIT(trans->cfg->csr->flag_init_done));
 529
 530         /* Activates XTAL resources monitor */
 531         __iwl_trans_pcie_set_bit(trans, CSR_MONITOR_CFG_REG,
 532                                  CSR_MONITOR_XTAL_RESOURCES);
 533
 534         /* Release XTAL ON request */
 535         __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
 536                                    CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
 537         udelay(10);
 538
 539         /* Release APMG XTAL */
 540         iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG,
 541                                  apmg_xtal_cfg_reg &
 542                                  ~SHR_APMG_XTAL_CFG_XTAL_ON_REQ);
 543 }
 544
 545 void iwl_pcie_apm_stop_master(struct iwl_trans *trans)
 546 {
 547         int ret;
 548
 549         /* stop device's busmaster DMA activity */
 550         iwl_set_bit(trans, trans->cfg->csr->addr_sw_reset,
 551                     BIT(trans->cfg->csr->flag_stop_master));
 552
 553         ret = iwl_poll_bit(trans, trans->cfg->csr->addr_sw_reset,
 554                            BIT(trans->cfg->csr->flag_master_dis),
 555                            BIT(trans->cfg->csr->flag_master_dis), 100);
 556         if (ret < 0)
 557                 IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n");
 558
 559         IWL_DEBUG_INFO(trans, "stop master\n");
 560 }
 561
 562 static void iwl_pcie_apm_stop(struct iwl_trans *trans, bool op_mode_leave)
 563 {
 564         IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n");
 565
 566         if (op_mode_leave) {
 567                 if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status))
 568                         iwl_pcie_apm_init(trans);
 569
 570                 /* inform ME that we are leaving */
 571                 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_7000)
 572                         iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
 573                                           APMG_PCIDEV_STT_VAL_WAKE_ME);
 574                 else if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000) {
 575                         iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
 576                                     CSR_RESET_LINK_PWR_MGMT_DISABLED);
 577                         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 578                                     CSR_HW_IF_CONFIG_REG_PREPARE |
 579                                     CSR_HW_IF_CONFIG_REG_ENABLE_PME);
 580                         mdelay(1);
 581                         iwl_clear_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
 582                                       CSR_RESET_LINK_PWR_MGMT_DISABLED);
 583                 }
 584                 mdelay(5);
 585         }
 586
 587         clear_bit(STATUS_DEVICE_ENABLED, &trans->status);
 588
 589         /* Stop device's DMA activity */
 590         iwl_pcie_apm_stop_master(trans);
 591
 592         if (trans->cfg->lp_xtal_workaround) {
 593                 iwl_pcie_apm_lp_xtal_enable(trans);
 594                 return;
 595         }
 596
 597         iwl_trans_pcie_sw_reset(trans);
 598
 599         /*
 600          * Clear "initialization complete" bit to move adapter from
 601          * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
 602          */
 603         iwl_clear_bit(trans, CSR_GP_CNTRL,
 604                       BIT(trans->cfg->csr->flag_init_done));
 605 }
 606
 607 static int iwl_pcie_nic_init(struct iwl_trans *trans)
 608 {
 609         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 610         int ret;
 611
 612         /* nic_init */
 613         spin_lock(&trans_pcie->irq_lock);
 614         ret = iwl_pcie_apm_init(trans);
 615         spin_unlock(&trans_pcie->irq_lock);
 616
 617         if (ret)
 618                 return ret;
 619
 620         iwl_pcie_set_pwr(trans, false);
 621
 622         iwl_op_mode_nic_config(trans->op_mode);
 623
 624         /* Allocate the RX queue, or reset if it is already allocated */
 625         iwl_pcie_rx_init(trans);
 626
 627         /* Allocate or reset and init all Tx and Command queues */
 628         if (iwl_pcie_tx_init(trans))
 629                 return -ENOMEM;
 630
 631         if (trans->cfg->base_params->shadow_reg_enable) {
 632                 /* enable shadow regs in HW */
 633                 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF);
 634                 IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n");
 635         }
 636
 637         return 0;
 638 }
 639
 640 #define HW_READY_TIMEOUT (50)
 641
 642 /* Note: returns poll_bit return value, which is >= 0 if success */
 643 static int iwl_pcie_set_hw_ready(struct iwl_trans *trans)
 644 {
 645         int ret;
 646
 647         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 648                     CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
 649
 650         /* See if we got it */
 651         ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
 652                            CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
 653                            CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
 654                            HW_READY_TIMEOUT);
 655
 656         if (ret >= 0)
 657                 iwl_set_bit(trans, CSR_MBOX_SET_REG, CSR_MBOX_SET_REG_OS_ALIVE);
 658
 659         IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : "");
 660         return ret;
 661 }
 662
 663 /* Note: returns standard 0/-ERROR code */
 664 int iwl_pcie_prepare_card_hw(struct iwl_trans *trans)
 665 {
 666         int ret;
 667         int t = 0;
 668         int iter;
 669
 670         IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n");
 671
 672         ret = iwl_pcie_set_hw_ready(trans);
 673         /* If the card is ready, exit 0 */
 674         if (ret >= 0)
 675                 return 0;
 676
 677         iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
 678                     CSR_RESET_LINK_PWR_MGMT_DISABLED);
 679         usleep_range(1000, 2000);
 680
 681         for (iter = 0; iter < 10; iter++) {
 682                 /* If HW is not ready, prepare the conditions to check again */
 683                 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 684                             CSR_HW_IF_CONFIG_REG_PREPARE);
 685
 686                 do {
 687                         ret = iwl_pcie_set_hw_ready(trans);
 688                         if (ret >= 0)
 689                                 return 0;
 690
 691                         usleep_range(200, 1000);
 692                         t += 200;
 693                 } while (t < 150000);
 694                 msleep(25);
 695         }
 696
 697         IWL_ERR(trans, "Couldn't prepare the card\n");
 698
 699         return ret;
 700 }
 701
 702 /*
 703  * ucode
 704  */
 705 static void iwl_pcie_load_firmware_chunk_fh(struct iwl_trans *trans,
 706                                             u32 dst_addr, dma_addr_t phy_addr,
 707                                             u32 byte_cnt)
 708 {
 709         iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
 710                     FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
 711
 712         iwl_write32(trans, FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL),
 713                     dst_addr);
 714
 715         iwl_write32(trans, FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
 716                     phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
 717
 718         iwl_write32(trans, FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
 719                     (iwl_get_dma_hi_addr(phy_addr)
 720                         << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
 721
 722         iwl_write32(trans, FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
 723                     BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM) |
 724                     BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX) |
 725                     FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
 726
 727         iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
 728                     FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
 729                     FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE |
 730                     FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
 731 }
 732
 733 static int iwl_pcie_load_firmware_chunk(struct iwl_trans *trans,
 734                                         u32 dst_addr, dma_addr_t phy_addr,
 735                                         u32 byte_cnt)
 736 {
 737         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 738         unsigned long flags;
 739         int ret;
 740
 741         trans_pcie->ucode_write_complete = false;
 742
 743         if (!iwl_trans_grab_nic_access(trans, &flags))
 744                 return -EIO;
 745
 746         iwl_pcie_load_firmware_chunk_fh(trans, dst_addr, phy_addr,
 747                                         byte_cnt);
 748         iwl_trans_release_nic_access(trans, &flags);
 749
 750         ret = wait_event_timeout(trans_pcie->ucode_write_waitq,
 751                                  trans_pcie->ucode_write_complete, 5 * HZ);
 752         if (!ret) {
 753                 IWL_ERR(trans, "Failed to load firmware chunk!\n");
 754                 iwl_trans_pcie_dump_regs(trans);
 755                 return -ETIMEDOUT;
 756         }
 757
 758         return 0;
 759 }
 760
 761 static int iwl_pcie_load_section(struct iwl_trans *trans, u8 section_num,
 762                             const struct fw_desc *section)
 763 {
 764         u8 *v_addr;
 765         dma_addr_t p_addr;
 766         u32 offset, chunk_sz = min_t(u32, FH_MEM_TB_MAX_LENGTH, section->len);
 767         int ret = 0;
 768
 769         IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n",
 770                      section_num);
 771
 772         v_addr = dma_alloc_coherent(trans->dev, chunk_sz, &p_addr,
 773                                     GFP_KERNEL | __GFP_NOWARN);
 774         if (!v_addr) {
 775                 IWL_DEBUG_INFO(trans, "Falling back to small chunks of DMA\n");
 776                 chunk_sz = PAGE_SIZE;
 777                 v_addr = dma_alloc_coherent(trans->dev, chunk_sz,
 778                                             &p_addr, GFP_KERNEL);
 779                 if (!v_addr)
 780                         return -ENOMEM;
 781         }
 782
 783         for (offset = 0; offset < section->len; offset += chunk_sz) {
 784                 u32 copy_size, dst_addr;
 785                 bool extended_addr = false;
 786
 787                 copy_size = min_t(u32, chunk_sz, section->len - offset);
 788                 dst_addr = section->offset + offset;
 789
 790                 if (dst_addr >= IWL_FW_MEM_EXTENDED_START &&
 791                     dst_addr <= IWL_FW_MEM_EXTENDED_END)
 792                         extended_addr = true;
 793
 794                 if (extended_addr)
 795                         iwl_set_bits_prph(trans, LMPM_CHICK,
 796                                           LMPM_CHICK_EXTENDED_ADDR_SPACE);
 797
 798                 memcpy(v_addr, (u8 *)section->data + offset, copy_size);
 799                 ret = iwl_pcie_load_firmware_chunk(trans, dst_addr, p_addr,
 800                                                    copy_size);
 801
 802                 if (extended_addr)
 803                         iwl_clear_bits_prph(trans, LMPM_CHICK,
 804                                             LMPM_CHICK_EXTENDED_ADDR_SPACE);
 805
 806                 if (ret) {
 807                         IWL_ERR(trans,
 808                                 "Could not load the [%d] uCode section\n",
 809                                 section_num);
 810                         break;
 811                 }
 812         }
 813
 814         dma_free_coherent(trans->dev, chunk_sz, v_addr, p_addr);
 815         return ret;
 816 }
 817
 818 static int iwl_pcie_load_cpu_sections_8000(struct iwl_trans *trans,
 819                                            const struct fw_img *image,
 820                                            int cpu,
 821                                            int *first_ucode_section)
 822 {
 823         int shift_param;
 824         int i, ret = 0, sec_num = 0x1;
 825         u32 val, last_read_idx = 0;
 826
 827         if (cpu == 1) {
 828                 shift_param = 0;
 829                 *first_ucode_section = 0;
 830         } else {
 831                 shift_param = 16;
 832                 (*first_ucode_section)++;
 833         }
 834
 835         for (i = *first_ucode_section; i < image->num_sec; i++) {
 836                 last_read_idx = i;
 837
 838                 /*
 839                  * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between
 840                  * CPU1 to CPU2.
 841                  * PAGING_SEPARATOR_SECTION delimiter - separate between
 842                  * CPU2 non paged to CPU2 paging sec.
 843                  */
 844                 if (!image->sec[i].data ||
 845                     image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION ||
 846                     image->sec[i].offset == PAGING_SEPARATOR_SECTION) {
 847                         IWL_DEBUG_FW(trans,
 848                                      "Break since Data not valid or Empty section, sec = %d\n",
 849                                      i);
 850                         break;
 851                 }
 852
 853                 ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
 854                 if (ret)
 855                         return ret;
 856
 857                 /* Notify ucode of loaded section number and status */
 858                 val = iwl_read_direct32(trans, FH_UCODE_LOAD_STATUS);
 859                 val = val | (sec_num << shift_param);
 860                 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, val);
 861
 862                 sec_num = (sec_num << 1) | 0x1;
 863         }
 864
 865         *first_ucode_section = last_read_idx;
 866
 867         iwl_enable_interrupts(trans);
 868
 869         if (trans->cfg->use_tfh) {
 870                 if (cpu == 1)
 871                         iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS,
 872                                        0xFFFF);
 873                 else
 874                         iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS,
 875                                        0xFFFFFFFF);
 876         } else {
 877                 if (cpu == 1)
 878                         iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS,
 879                                            0xFFFF);
 880                 else
 881                         iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS,
 882                                            0xFFFFFFFF);
 883         }
 884
 885         return 0;
 886 }
 887
 888 static int iwl_pcie_load_cpu_sections(struct iwl_trans *trans,
 889                                       const struct fw_img *image,
 890                                       int cpu,
 891                                       int *first_ucode_section)
 892 {
 893         int i, ret = 0;
 894         u32 last_read_idx = 0;
 895
 896         if (cpu == 1)
 897                 *first_ucode_section = 0;
 898         else
 899                 (*first_ucode_section)++;
 900
 901         for (i = *first_ucode_section; i < image->num_sec; i++) {
 902                 last_read_idx = i;
 903
 904                 /*
 905                  * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between
 906                  * CPU1 to CPU2.
 907                  * PAGING_SEPARATOR_SECTION delimiter - separate between
 908                  * CPU2 non paged to CPU2 paging sec.
 909                  */
 910                 if (!image->sec[i].data ||
 911                     image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION ||
 912                     image->sec[i].offset == PAGING_SEPARATOR_SECTION) {
 913                         IWL_DEBUG_FW(trans,
 914                                      "Break since Data not valid or Empty section, sec = %d\n",
 915                                      i);
 916                         break;
 917                 }
 918
 919                 ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
 920                 if (ret)
 921                         return ret;
 922         }
 923
 924         *first_ucode_section = last_read_idx;
 925
 926         return 0;
 927 }
 928
 929 void iwl_pcie_apply_destination(struct iwl_trans *trans)
 930 {
 931         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 932         const struct iwl_fw_dbg_dest_tlv_v1 *dest = trans->dbg_dest_tlv;
 933         int i;
 934
 935         IWL_INFO(trans, "Applying debug destination %s\n",
 936                  get_fw_dbg_mode_string(dest->monitor_mode));
 937
 938         if (dest->monitor_mode == EXTERNAL_MODE)
 939                 iwl_pcie_alloc_fw_monitor(trans, dest->size_power);
 940         else
 941                 IWL_WARN(trans, "PCI should have external buffer debug\n");
 942
 943         for (i = 0; i < trans->dbg_dest_reg_num; i++) {
 944                 u32 addr = le32_to_cpu(dest->reg_ops[i].addr);
 945                 u32 val = le32_to_cpu(dest->reg_ops[i].val);
 946
 947                 switch (dest->reg_ops[i].op) {
 948                 case CSR_ASSIGN:
 949                         iwl_write32(trans, addr, val);
 950                         break;
 951                 case CSR_SETBIT:
 952                         iwl_set_bit(trans, addr, BIT(val));
 953                         break;
 954                 case CSR_CLEARBIT:
 955                         iwl_clear_bit(trans, addr, BIT(val));
 956                         break;
 957                 case PRPH_ASSIGN:
 958                         iwl_write_prph(trans, addr, val);
 959                         break;
 960                 case PRPH_SETBIT:
 961                         iwl_set_bits_prph(trans, addr, BIT(val));
 962                         break;
 963                 case PRPH_CLEARBIT:
 964                         iwl_clear_bits_prph(trans, addr, BIT(val));
 965                         break;
 966                 case PRPH_BLOCKBIT:
 967                         if (iwl_read_prph(trans, addr) & BIT(val)) {
 968                                 IWL_ERR(trans,
 969                                         "BIT(%u) in address 0x%x is 1, stopping FW configuration\n",
 970                                         val, addr);
 971                                 goto monitor;
 972                         }
 973                         break;
 974                 default:
 975                         IWL_ERR(trans, "FW debug - unknown OP %d\n",
 976                                 dest->reg_ops[i].op);
 977                         break;
 978                 }
 979         }
 980
 981 monitor:
 982         if (dest->monitor_mode == EXTERNAL_MODE && trans_pcie->fw_mon_size) {
 983                 iwl_write_prph(trans, le32_to_cpu(dest->base_reg),
 984                                trans_pcie->fw_mon_phys >> dest->base_shift);
 985                 if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000)
 986                         iwl_write_prph(trans, le32_to_cpu(dest->end_reg),
 987                                        (trans_pcie->fw_mon_phys +
 988                                         trans_pcie->fw_mon_size - 256) >>
 989                                                 dest->end_shift);
 990                 else
 991                         iwl_write_prph(trans, le32_to_cpu(dest->end_reg),
 992                                        (trans_pcie->fw_mon_phys +
 993                                         trans_pcie->fw_mon_size) >>
 994                                                 dest->end_shift);
 995         }
 996 }
 997
 998 static int iwl_pcie_load_given_ucode(struct iwl_trans *trans,
 999                                 const struct fw_img *image)
1000 {
1001         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1002         int ret = 0;
1003         int first_ucode_section;
1004
1005         IWL_DEBUG_FW(trans, "working with %s CPU\n",
1006                      image->is_dual_cpus ? "Dual" : "Single");
1007
1008         /* load to FW the binary non secured sections of CPU1 */
1009         ret = iwl_pcie_load_cpu_sections(trans, image, 1, &first_ucode_section);
1010         if (ret)
1011                 return ret;
1012
1013         if (image->is_dual_cpus) {
1014                 /* set CPU2 header address */
1015                 iwl_write_prph(trans,
1016                                LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR,
1017                                LMPM_SECURE_CPU2_HDR_MEM_SPACE);
1018
1019                 /* load to FW the binary sections of CPU2 */
1020                 ret = iwl_pcie_load_cpu_sections(trans, image, 2,
1021                                                  &first_ucode_section);
1022                 if (ret)
1023                         return ret;
1024         }
1025
1026         /* supported for 7000 only for the moment */
1027         if (iwlwifi_mod_params.fw_monitor &&
1028             trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) {
1029                 iwl_pcie_alloc_fw_monitor(trans, 0);
1030
1031                 if (trans_pcie->fw_mon_size) {
1032                         iwl_write_prph(trans, MON_BUFF_BASE_ADDR,
1033                                        trans_pcie->fw_mon_phys >> 4);
1034                         iwl_write_prph(trans, MON_BUFF_END_ADDR,
1035                                        (trans_pcie->fw_mon_phys +
1036                                         trans_pcie->fw_mon_size) >> 4);
1037                 }
1038         } else if (trans->dbg_dest_tlv) {
1039                 iwl_pcie_apply_destination(trans);
1040         }
1041
1042         iwl_enable_interrupts(trans);
1043
1044         /* release CPU reset */
1045         iwl_write32(trans, CSR_RESET, 0);
1046
1047         return 0;
1048 }
1049
1050 static int iwl_pcie_load_given_ucode_8000(struct iwl_trans *trans,
1051                                           const struct fw_img *image)
1052 {
1053         int ret = 0;
1054         int first_ucode_section;
1055
1056         IWL_DEBUG_FW(trans, "working with %s CPU\n",
1057                      image->is_dual_cpus ? "Dual" : "Single");
1058
1059         if (trans->dbg_dest_tlv)
1060                 iwl_pcie_apply_destination(trans);
1061
1062         IWL_DEBUG_POWER(trans, "Original WFPM value = 0x%08X\n",
1063                         iwl_read_prph(trans, WFPM_GP2));
1064
1065         /*
1066          * Set default value. On resume reading the values that were
1067          * zeored can provide debug data on the resume flow.
1068          * This is for debugging only and has no functional impact.
1069          */
1070         iwl_write_prph(trans, WFPM_GP2, 0x01010101);
1071
1072         /* configure the ucode to be ready to get the secured image */
1073         /* release CPU reset */
1074         iwl_write_prph(trans, RELEASE_CPU_RESET, RELEASE_CPU_RESET_BIT);
1075
1076         /* load to FW the binary Secured sections of CPU1 */
1077         ret = iwl_pcie_load_cpu_sections_8000(trans, image, 1,
1078                                               &first_ucode_section);
1079         if (ret)
1080                 return ret;
1081
1082         /* load to FW the binary sections of CPU2 */
1083         return iwl_pcie_load_cpu_sections_8000(trans, image, 2,
1084                                                &first_ucode_section);
1085 }
1086
1087 bool iwl_pcie_check_hw_rf_kill(struct iwl_trans *trans)
1088 {
1089         struct iwl_trans_pcie *trans_pcie =  IWL_TRANS_GET_PCIE_TRANS(trans);
1090         bool hw_rfkill = iwl_is_rfkill_set(trans);
1091         bool prev = test_bit(STATUS_RFKILL_OPMODE, &trans->status);
1092         bool report;
1093
1094         if (hw_rfkill) {
1095                 set_bit(STATUS_RFKILL_HW, &trans->status);
1096                 set_bit(STATUS_RFKILL_OPMODE, &trans->status);
1097         } else {
1098                 clear_bit(STATUS_RFKILL_HW, &trans->status);
1099                 if (trans_pcie->opmode_down)
1100                         clear_bit(STATUS_RFKILL_OPMODE, &trans->status);
1101         }
1102
1103         report = test_bit(STATUS_RFKILL_OPMODE, &trans->status);
1104
1105         if (prev != report)
1106                 iwl_trans_pcie_rf_kill(trans, report);
1107
1108         return hw_rfkill;
1109 }
1110
1111 struct iwl_causes_list {
1112         u32 cause_num;
1113         u32 mask_reg;
1114         u8 addr;
1115 };
1116
1117 static struct iwl_causes_list causes_list[] = {
1118         {MSIX_FH_INT_CAUSES_D2S_CH0_NUM,        CSR_MSIX_FH_INT_MASK_AD, 0},
1119         {MSIX_FH_INT_CAUSES_D2S_CH1_NUM,        CSR_MSIX_FH_INT_MASK_AD, 0x1},
1120         {MSIX_FH_INT_CAUSES_S2D,                CSR_MSIX_FH_INT_MASK_AD, 0x3},
1121         {MSIX_FH_INT_CAUSES_FH_ERR,             CSR_MSIX_FH_INT_MASK_AD, 0x5},
1122         {MSIX_HW_INT_CAUSES_REG_ALIVE,          CSR_MSIX_HW_INT_MASK_AD, 0x10},
1123         {MSIX_HW_INT_CAUSES_REG_WAKEUP,         CSR_MSIX_HW_INT_MASK_AD, 0x11},
1124         {MSIX_HW_INT_CAUSES_REG_CT_KILL,        CSR_MSIX_HW_INT_MASK_AD, 0x16},
1125         {MSIX_HW_INT_CAUSES_REG_RF_KILL,        CSR_MSIX_HW_INT_MASK_AD, 0x17},
1126         {MSIX_HW_INT_CAUSES_REG_PERIODIC,       CSR_MSIX_HW_INT_MASK_AD, 0x18},
1127         {MSIX_HW_INT_CAUSES_REG_SW_ERR,         CSR_MSIX_HW_INT_MASK_AD, 0x29},
1128         {MSIX_HW_INT_CAUSES_REG_SCD,            CSR_MSIX_HW_INT_MASK_AD, 0x2A},
1129         {MSIX_HW_INT_CAUSES_REG_FH_TX,          CSR_MSIX_HW_INT_MASK_AD, 0x2B},
1130         {MSIX_HW_INT_CAUSES_REG_HW_ERR,         CSR_MSIX_HW_INT_MASK_AD, 0x2D},
1131         {MSIX_HW_INT_CAUSES_REG_HAP,            CSR_MSIX_HW_INT_MASK_AD, 0x2E},
1132 };
1133
1134 static void iwl_pcie_map_non_rx_causes(struct iwl_trans *trans)
1135 {
1136         struct iwl_trans_pcie *trans_pcie =  IWL_TRANS_GET_PCIE_TRANS(trans);
1137         int val = trans_pcie->def_irq | MSIX_NON_AUTO_CLEAR_CAUSE;
1138         int i;
1139
1140         /*
1141          * Access all non RX causes and map them to the default irq.
1142          * In case we are missing at least one interrupt vector,
1143          * the first interrupt vector will serve non-RX and FBQ causes.
1144          */
1145         for (i = 0; i < ARRAY_SIZE(causes_list); i++) {
1146                 iwl_write8(trans, CSR_MSIX_IVAR(causes_list[i].addr), val);
1147                 iwl_clear_bit(trans, causes_list[i].mask_reg,
1148                               causes_list[i].cause_num);
1149         }
1150 }
1151
1152 static void iwl_pcie_map_rx_causes(struct iwl_trans *trans)
1153 {
1154         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1155         u32 offset =
1156                 trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS ? 1 : 0;
1157         u32 val, idx;
1158
1159         /*
1160          * The first RX queue - fallback queue, which is designated for
1161          * management frame, command responses etc, is always mapped to the
1162          * first interrupt vector. The other RX queues are mapped to
1163          * the other (N - 2) interrupt vectors.
1164          */
1165         val = BIT(MSIX_FH_INT_CAUSES_Q(0));
1166         for (idx = 1; idx < trans->num_rx_queues; idx++) {
1167                 iwl_write8(trans, CSR_MSIX_RX_IVAR(idx),
1168                            MSIX_FH_INT_CAUSES_Q(idx - offset));
1169                 val |= BIT(MSIX_FH_INT_CAUSES_Q(idx));
1170         }
1171         iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, ~val);
1172
1173         val = MSIX_FH_INT_CAUSES_Q(0);
1174         if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_NON_RX)
1175                 val |= MSIX_NON_AUTO_CLEAR_CAUSE;
1176         iwl_write8(trans, CSR_MSIX_RX_IVAR(0), val);
1177
1178         if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS)
1179                 iwl_write8(trans, CSR_MSIX_RX_IVAR(1), val);
1180 }
1181
1182 void iwl_pcie_conf_msix_hw(struct iwl_trans_pcie *trans_pcie)
1183 {
1184         struct iwl_trans *trans = trans_pcie->trans;
1185
1186         if (!trans_pcie->msix_enabled) {
1187                 if (trans->cfg->mq_rx_supported &&
1188                     test_bit(STATUS_DEVICE_ENABLED, &trans->status))
1189                         iwl_write_prph(trans, UREG_CHICK,
1190                                        UREG_CHICK_MSI_ENABLE);
1191                 return;
1192         }
1193         /*
1194          * The IVAR table needs to be configured again after reset,
1195          * but if the device is disabled, we can't write to
1196          * prph.
1197          */
1198         if (test_bit(STATUS_DEVICE_ENABLED, &trans->status))
1199                 iwl_write_prph(trans, UREG_CHICK, UREG_CHICK_MSIX_ENABLE);
1200
1201         /*
1202          * Each cause from the causes list above and the RX causes is
1203          * represented as a byte in the IVAR table. The first nibble
1204          * represents the bound interrupt vector of the cause, the second
1205          * represents no auto clear for this cause. This will be set if its
1206          * interrupt vector is bound to serve other causes.
1207          */
1208         iwl_pcie_map_rx_causes(trans);
1209
1210         iwl_pcie_map_non_rx_causes(trans);
1211 }
1212
1213 static void iwl_pcie_init_msix(struct iwl_trans_pcie *trans_pcie)
1214 {
1215         struct iwl_trans *trans = trans_pcie->trans;
1216
1217         iwl_pcie_conf_msix_hw(trans_pcie);
1218
1219         if (!trans_pcie->msix_enabled)
1220                 return;
1221
1222         trans_pcie->fh_init_mask = ~iwl_read32(trans, CSR_MSIX_FH_INT_MASK_AD);
1223         trans_pcie->fh_mask = trans_pcie->fh_init_mask;
1224         trans_pcie->hw_init_mask = ~iwl_read32(trans, CSR_MSIX_HW_INT_MASK_AD);
1225         trans_pcie->hw_mask = trans_pcie->hw_init_mask;
1226 }
1227
1228 static void _iwl_trans_pcie_stop_device(struct iwl_trans *trans, bool low_power)
1229 {
1230         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1231
1232         lockdep_assert_held(&trans_pcie->mutex);
1233
1234         if (trans_pcie->is_down)
1235                 return;
1236
1237         trans_pcie->is_down = true;
1238
1239         /* Stop dbgc before stopping device */
1240         if (trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) {
1241                 iwl_set_bits_prph(trans, MON_BUFF_SAMPLE_CTL, 0x100);
1242         } else {
1243                 iwl_write_prph(trans, DBGC_IN_SAMPLE, 0);
1244                 udelay(100);
1245                 iwl_write_prph(trans, DBGC_OUT_CTRL, 0);
1246         }
1247
1248         /* tell the device to stop sending interrupts */
1249         iwl_disable_interrupts(trans);
1250
1251         /* device going down, Stop using ICT table */
1252         iwl_pcie_disable_ict(trans);
1253
1254         /*
1255          * If a HW restart happens during firmware loading,
1256          * then the firmware loading might call this function
1257          * and later it might be called again due to the
1258          * restart. So don't process again if the device is
1259          * already dead.
1260          */
1261         if (test_and_clear_bit(STATUS_DEVICE_ENABLED, &trans->status)) {
1262                 IWL_DEBUG_INFO(trans,
1263                                "DEVICE_ENABLED bit was set and is now cleared\n");
1264                 iwl_pcie_tx_stop(trans);
1265                 iwl_pcie_rx_stop(trans);
1266
1267                 /* Power-down device's busmaster DMA clocks */
1268                 if (!trans->cfg->apmg_not_supported) {
1269                         iwl_write_prph(trans, APMG_CLK_DIS_REG,
1270                                        APMG_CLK_VAL_DMA_CLK_RQT);
1271                         udelay(5);
1272                 }
1273         }
1274
1275         /* Make sure (redundant) we've released our request to stay awake */
1276         iwl_clear_bit(trans, CSR_GP_CNTRL,
1277                       BIT(trans->cfg->csr->flag_mac_access_req));
1278
1279         /* Stop the device, and put it in low power state */
1280         iwl_pcie_apm_stop(trans, false);
1281
1282         iwl_trans_pcie_sw_reset(trans);
1283
1284         /*
1285          * Upon stop, the IVAR table gets erased, so msi-x won't
1286          * work. This causes a bug in RF-KILL flows, since the interrupt
1287          * that enables radio won't fire on the correct irq, and the
1288          * driver won't be able to handle the interrupt.
1289          * Configure the IVAR table again after reset.
1290          */
1291         iwl_pcie_conf_msix_hw(trans_pcie);
1292
1293         /*
1294          * Upon stop, the APM issues an interrupt if HW RF kill is set.
1295          * This is a bug in certain verions of the hardware.
1296          * Certain devices also keep sending HW RF kill interrupt all
1297          * the time, unless the interrupt is ACKed even if the interrupt
1298          * should be masked. Re-ACK all the interrupts here.
1299          */
1300         iwl_disable_interrupts(trans);
1301
1302         /* clear all status bits */
1303         clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
1304         clear_bit(STATUS_INT_ENABLED, &trans->status);
1305         clear_bit(STATUS_TPOWER_PMI, &trans->status);
1306
1307         /*
1308          * Even if we stop the HW, we still want the RF kill
1309          * interrupt
1310          */
1311         iwl_enable_rfkill_int(trans);
1312
1313         /* re-take ownership to prevent other users from stealing the device */
1314         iwl_pcie_prepare_card_hw(trans);
1315 }
1316
1317 void iwl_pcie_synchronize_irqs(struct iwl_trans *trans)
1318 {
1319         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1320
1321         if (trans_pcie->msix_enabled) {
1322                 int i;
1323
1324                 for (i = 0; i < trans_pcie->alloc_vecs; i++)
1325                         synchronize_irq(trans_pcie->msix_entries[i].vector);
1326         } else {
1327                 synchronize_irq(trans_pcie->pci_dev->irq);
1328         }
1329 }
1330
1331 static int iwl_trans_pcie_start_fw(struct iwl_trans *trans,
1332                                    const struct fw_img *fw, bool run_in_rfkill)
1333 {
1334         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1335         bool hw_rfkill;
1336         int ret;
1337
1338         /* This may fail if AMT took ownership of the device */
1339         if (iwl_pcie_prepare_card_hw(trans)) {
1340                 IWL_WARN(trans, "Exit HW not ready\n");
1341                 ret = -EIO;
1342                 goto out;
1343         }
1344
1345         iwl_enable_rfkill_int(trans);
1346
1347         iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1348
1349         /*
1350          * We enabled the RF-Kill interrupt and the handler may very
1351          * well be running. Disable the interrupts to make sure no other
1352          * interrupt can be fired.
1353          */
1354         iwl_disable_interrupts(trans);
1355
1356         /* Make sure it finished running */
1357         iwl_pcie_synchronize_irqs(trans);
1358
1359         mutex_lock(&trans_pcie->mutex);
1360
1361         /* If platform's RF_KILL switch is NOT set to KILL */
1362         hw_rfkill = iwl_pcie_check_hw_rf_kill(trans);
1363         if (hw_rfkill && !run_in_rfkill) {
1364                 ret = -ERFKILL;
1365                 goto out;
1366         }
1367
1368         /* Someone called stop_device, don't try to start_fw */
1369         if (trans_pcie->is_down) {
1370                 IWL_WARN(trans,
1371                          "Can't start_fw since the HW hasn't been started\n");
1372                 ret = -EIO;
1373                 goto out;
1374         }
1375
1376         /* make sure rfkill handshake bits are cleared */
1377         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1378         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR,
1379                     CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
1380
1381         /* clear (again), then enable host interrupts */
1382         iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1383
1384         ret = iwl_pcie_nic_init(trans);
1385         if (ret) {
1386                 IWL_ERR(trans, "Unable to init nic\n");
1387                 goto out;
1388         }
1389
1390         /*
1391          * Now, we load the firmware and don't want to be interrupted, even
1392          * by the RF-Kill interrupt (hence mask all the interrupt besides the
1393          * FH_TX interrupt which is needed to load the firmware). If the
1394          * RF-Kill switch is toggled, we will find out after having loaded
1395          * the firmware and return the proper value to the caller.
1396          */
1397         iwl_enable_fw_load_int(trans);
1398
1399         /* really make sure rfkill handshake bits are cleared */
1400         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1401         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1402
1403         /* Load the given image to the HW */
1404         if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000)
1405                 ret = iwl_pcie_load_given_ucode_8000(trans, fw);
1406         else
1407                 ret = iwl_pcie_load_given_ucode(trans, fw);
1408
1409         /* re-check RF-Kill state since we may have missed the interrupt */
1410         hw_rfkill = iwl_pcie_check_hw_rf_kill(trans);
1411         if (hw_rfkill && !run_in_rfkill)
1412                 ret = -ERFKILL;
1413
1414 out:
1415         mutex_unlock(&trans_pcie->mutex);
1416         return ret;
1417 }
1418
1419 static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans, u32 scd_addr)
1420 {
1421         iwl_pcie_reset_ict(trans);
1422         iwl_pcie_tx_start(trans, scd_addr);
1423 }
1424
1425 void iwl_trans_pcie_handle_stop_rfkill(struct iwl_trans *trans,
1426                                        bool was_in_rfkill)
1427 {
1428         bool hw_rfkill;
1429
1430         /*
1431          * Check again since the RF kill state may have changed while
1432          * all the interrupts were disabled, in this case we couldn't
1433          * receive the RF kill interrupt and update the state in the
1434          * op_mode.
1435          * Don't call the op_mode if the rkfill state hasn't changed.
1436          * This allows the op_mode to call stop_device from the rfkill
1437          * notification without endless recursion. Under very rare
1438          * circumstances, we might have a small recursion if the rfkill
1439          * state changed exactly now while we were called from stop_device.
1440          * This is very unlikely but can happen and is supported.
1441          */
1442         hw_rfkill = iwl_is_rfkill_set(trans);
1443         if (hw_rfkill) {
1444                 set_bit(STATUS_RFKILL_HW, &trans->status);
1445                 set_bit(STATUS_RFKILL_OPMODE, &trans->status);
1446         } else {
1447                 clear_bit(STATUS_RFKILL_HW, &trans->status);
1448                 clear_bit(STATUS_RFKILL_OPMODE, &trans->status);
1449         }
1450         if (hw_rfkill != was_in_rfkill)
1451                 iwl_trans_pcie_rf_kill(trans, hw_rfkill);
1452 }
1453
1454 static void iwl_trans_pcie_stop_device(struct iwl_trans *trans, bool low_power)
1455 {
1456         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1457         bool was_in_rfkill;
1458
1459         mutex_lock(&trans_pcie->mutex);
1460         trans_pcie->opmode_down = true;
1461         was_in_rfkill = test_bit(STATUS_RFKILL_OPMODE, &trans->status);
1462         _iwl_trans_pcie_stop_device(trans, low_power);
1463         iwl_trans_pcie_handle_stop_rfkill(trans, was_in_rfkill);
1464         mutex_unlock(&trans_pcie->mutex);
1465 }
1466
1467 void iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state)
1468 {
1469         struct iwl_trans_pcie __maybe_unused *trans_pcie =
1470                 IWL_TRANS_GET_PCIE_TRANS(trans);
1471
1472         lockdep_assert_held(&trans_pcie->mutex);
1473
1474         IWL_WARN(trans, "reporting RF_KILL (radio %s)\n",
1475                  state ? "disabled" : "enabled");
1476         if (iwl_op_mode_hw_rf_kill(trans->op_mode, state)) {
1477                 if (trans->cfg->gen2)
1478                         _iwl_trans_pcie_gen2_stop_device(trans, true);
1479                 else
1480                         _iwl_trans_pcie_stop_device(trans, true);
1481         }
1482 }
1483
1484 static void iwl_trans_pcie_d3_suspend(struct iwl_trans *trans, bool test,
1485                                       bool reset)
1486 {
1487         if (!reset) {
1488                 /* Enable persistence mode to avoid reset */
1489                 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
1490                             CSR_HW_IF_CONFIG_REG_PERSIST_MODE);
1491         }
1492
1493         iwl_disable_interrupts(trans);
1494
1495         /*
1496          * in testing mode, the host stays awake and the
1497          * hardware won't be reset (not even partially)
1498          */
1499         if (test)
1500                 return;
1501
1502         iwl_pcie_disable_ict(trans);
1503
1504         iwl_pcie_synchronize_irqs(trans);
1505
1506         iwl_clear_bit(trans, CSR_GP_CNTRL,
1507                       BIT(trans->cfg->csr->flag_mac_access_req));
1508         iwl_clear_bit(trans, CSR_GP_CNTRL,
1509                       BIT(trans->cfg->csr->flag_init_done));
1510
1511         iwl_pcie_enable_rx_wake(trans, false);
1512
1513         if (reset) {
1514                 /*
1515                  * reset TX queues -- some of their registers reset during S3
1516                  * so if we don't reset everything here the D3 image would try
1517                  * to execute some invalid memory upon resume
1518                  */
1519                 iwl_trans_pcie_tx_reset(trans);
1520         }
1521
1522         iwl_pcie_set_pwr(trans, true);
1523 }
1524
1525 static int iwl_trans_pcie_d3_resume(struct iwl_trans *trans,
1526                                     enum iwl_d3_status *status,
1527                                     bool test,  bool reset)
1528 {
1529         struct iwl_trans_pcie *trans_pcie =  IWL_TRANS_GET_PCIE_TRANS(trans);
1530         u32 val;
1531         int ret;
1532
1533         if (test) {
1534                 iwl_enable_interrupts(trans);
1535                 *status = IWL_D3_STATUS_ALIVE;
1536                 return 0;
1537         }
1538
1539         iwl_pcie_enable_rx_wake(trans, true);
1540
1541         /*
1542          * Reconfigure IVAR table in case of MSIX or reset ict table in
1543          * MSI mode since HW reset erased it.
1544          * Also enables interrupts - none will happen as
1545          * the device doesn't know we're waking it up, only when
1546          * the opmode actually tells it after this call.
1547          */
1548         iwl_pcie_conf_msix_hw(trans_pcie);
1549         if (!trans_pcie->msix_enabled)
1550                 iwl_pcie_reset_ict(trans);
1551         iwl_enable_interrupts(trans);
1552
1553         iwl_set_bit(trans, CSR_GP_CNTRL,
1554                     BIT(trans->cfg->csr->flag_mac_access_req));
1555         iwl_set_bit(trans, CSR_GP_CNTRL,
1556                     BIT(trans->cfg->csr->flag_init_done));
1557
1558         if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000)
1559                 udelay(2);
1560
1561         ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
1562                            BIT(trans->cfg->csr->flag_mac_clock_ready),
1563                            BIT(trans->cfg->csr->flag_mac_clock_ready),
1564                            25000);
1565         if (ret < 0) {
1566                 IWL_ERR(trans, "Failed to resume the device (mac ready)\n");
1567                 return ret;
1568         }
1569
1570         iwl_pcie_set_pwr(trans, false);
1571
1572         if (!reset) {
1573                 iwl_clear_bit(trans, CSR_GP_CNTRL,
1574                               BIT(trans->cfg->csr->flag_mac_access_req));
1575         } else {
1576                 iwl_trans_pcie_tx_reset(trans);
1577
1578                 ret = iwl_pcie_rx_init(trans);
1579                 if (ret) {
1580                         IWL_ERR(trans,
1581                                 "Failed to resume the device (RX reset)\n");
1582                         return ret;
1583                 }
1584         }
1585
1586         IWL_DEBUG_POWER(trans, "WFPM value upon resume = 0x%08X\n",
1587                         iwl_read_prph(trans, WFPM_GP2));
1588
1589         val = iwl_read32(trans, CSR_RESET);
1590         if (val & CSR_RESET_REG_FLAG_NEVO_RESET)
1591                 *status = IWL_D3_STATUS_RESET;
1592         else
1593                 *status = IWL_D3_STATUS_ALIVE;
1594
1595         return 0;
1596 }
1597
1598 static void iwl_pcie_set_interrupt_capa(struct pci_dev *pdev,
1599                                         struct iwl_trans *trans)
1600 {
1601         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1602         int max_irqs, num_irqs, i, ret, nr_online_cpus;
1603         u16 pci_cmd;
1604
1605         if (!trans->cfg->mq_rx_supported)
1606                 goto enable_msi;
1607
1608         nr_online_cpus = num_online_cpus();
1609         max_irqs = min_t(u32, nr_online_cpus + 2, IWL_MAX_RX_HW_QUEUES);
1610         for (i = 0; i < max_irqs; i++)
1611                 trans_pcie->msix_entries[i].entry = i;
1612
1613         num_irqs = pci_enable_msix_range(pdev, trans_pcie->msix_entries,
1614                                          MSIX_MIN_INTERRUPT_VECTORS,
1615                                          max_irqs);
1616         if (num_irqs < 0) {
1617                 IWL_DEBUG_INFO(trans,
1618                                "Failed to enable msi-x mode (ret %d). Moving to msi mode.\n",
1619                                num_irqs);
1620                 goto enable_msi;
1621         }
1622         trans_pcie->def_irq = (num_irqs == max_irqs) ? num_irqs - 1 : 0;
1623
1624         IWL_DEBUG_INFO(trans,
1625                        "MSI-X enabled. %d interrupt vectors were allocated\n",
1626                        num_irqs);
1627
1628         /*
1629          * In case the OS provides fewer interrupts than requested, different
1630          * causes will share the same interrupt vector as follows:
1631          * One interrupt less: non rx causes shared with FBQ.
1632          * Two interrupts less: non rx causes shared with FBQ and RSS.
1633          * More than two interrupts: we will use fewer RSS queues.
1634          */
1635         if (num_irqs <= nr_online_cpus) {
1636                 trans_pcie->trans->num_rx_queues = num_irqs + 1;
1637                 trans_pcie->shared_vec_mask = IWL_SHARED_IRQ_NON_RX |
1638                         IWL_SHARED_IRQ_FIRST_RSS;
1639         } else if (num_irqs == nr_online_cpus + 1) {
1640                 trans_pcie->trans->num_rx_queues = num_irqs;
1641                 trans_pcie->shared_vec_mask = IWL_SHARED_IRQ_NON_RX;
1642         } else {
1643                 trans_pcie->trans->num_rx_queues = num_irqs - 1;
1644         }
1645
1646         trans_pcie->alloc_vecs = num_irqs;
1647         trans_pcie->msix_enabled = true;
1648         return;
1649
1650 enable_msi:
1651         ret = pci_enable_msi(pdev);
1652         if (ret) {
1653                 dev_err(&pdev->dev, "pci_enable_msi failed - %d\n", ret);
1654                 /* enable rfkill interrupt: hw bug w/a */
1655                 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
1656                 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
1657                         pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
1658                         pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
1659                 }
1660         }
1661 }
1662
1663 static void iwl_pcie_irq_set_affinity(struct iwl_trans *trans)
1664 {
1665         int iter_rx_q, i, ret, cpu, offset;
1666         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1667
1668         i = trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS ? 0 : 1;
1669         iter_rx_q = trans_pcie->trans->num_rx_queues - 1 + i;
1670         offset = 1 + i;
1671         for (; i < iter_rx_q ; i++) {
1672                 /*
1673                  * Get the cpu prior to the place to search
1674                  * (i.e. return will be > i - 1).
1675                  */
1676                 cpu = cpumask_next(i - offset, cpu_online_mask);
1677                 cpumask_set_cpu(cpu, &trans_pcie->affinity_mask[i]);
1678                 ret = irq_set_affinity_hint(trans_pcie->msix_entries[i].vector,
1679                                             &trans_pcie->affinity_mask[i]);
1680                 if (ret)
1681                         IWL_ERR(trans_pcie->trans,
1682                                 "Failed to set affinity mask for IRQ %d\n",
1683                                 i);
1684         }
1685 }
1686
1687 static const char *queue_name(struct device *dev,
1688                               struct iwl_trans_pcie *trans_p, int i)
1689 {
1690         if (trans_p->shared_vec_mask) {
1691                 int vec = trans_p->shared_vec_mask &
1692                           IWL_SHARED_IRQ_FIRST_RSS ? 1 : 0;
1693
1694                 if (i == 0)
1695                         return DRV_NAME ": shared IRQ";
1696
1697                 return devm_kasprintf(dev, GFP_KERNEL,
1698                                       DRV_NAME ": queue %d", i + vec);
1699         }
1700         if (i == 0)
1701                 return DRV_NAME ": default queue";
1702
1703         if (i == trans_p->alloc_vecs - 1)
1704                 return DRV_NAME ": exception";
1705
1706         return devm_kasprintf(dev, GFP_KERNEL,
1707                               DRV_NAME  ": queue %d", i);
1708 }
1709
1710 static int iwl_pcie_init_msix_handler(struct pci_dev *pdev,
1711                                       struct iwl_trans_pcie *trans_pcie)
1712 {
1713         int i;
1714
1715         for (i = 0; i < trans_pcie->alloc_vecs; i++) {
1716                 int ret;
1717                 struct msix_entry *msix_entry;
1718                 const char *qname = queue_name(&pdev->dev, trans_pcie, i);
1719
1720                 if (!qname)
1721                         return -ENOMEM;
1722
1723                 msix_entry = &trans_pcie->msix_entries[i];
1724                 ret = devm_request_threaded_irq(&pdev->dev,
1725                                                 msix_entry->vector,
1726                                                 iwl_pcie_msix_isr,
1727                                                 (i == trans_pcie->def_irq) ?
1728                                                 iwl_pcie_irq_msix_handler :
1729                                                 iwl_pcie_irq_rx_msix_handler,
1730                                                 IRQF_SHARED,
1731                                                 qname,
1732                                                 msix_entry);
1733                 if (ret) {
1734                         IWL_ERR(trans_pcie->trans,
1735                                 "Error allocating IRQ %d\n", i);
1736
1737                         return ret;
1738                 }
1739         }
1740         iwl_pcie_irq_set_affinity(trans_pcie->trans);
1741
1742         return 0;
1743 }
1744
1745 static int _iwl_trans_pcie_start_hw(struct iwl_trans *trans, bool low_power)
1746 {
1747         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1748         int err;
1749
1750         lockdep_assert_held(&trans_pcie->mutex);
1751
1752         err = iwl_pcie_prepare_card_hw(trans);
1753         if (err) {
1754                 IWL_ERR(trans, "Error while preparing HW: %d\n", err);
1755                 return err;
1756         }
1757
1758         iwl_trans_pcie_sw_reset(trans);
1759
1760         err = iwl_pcie_apm_init(trans);
1761         if (err)
1762                 return err;
1763
1764         iwl_pcie_init_msix(trans_pcie);
1765
1766         /* From now on, the op_mode will be kept updated about RF kill state */
1767         iwl_enable_rfkill_int(trans);
1768
1769         trans_pcie->opmode_down = false;
1770
1771         /* Set is_down to false here so that...*/
1772         trans_pcie->is_down = false;
1773
1774         /* ...rfkill can call stop_device and set it false if needed */
1775         iwl_pcie_check_hw_rf_kill(trans);
1776
1777         /* Make sure we sync here, because we'll need full access later */
1778         if (low_power)
1779                 pm_runtime_resume(trans->dev);
1780
1781         return 0;
1782 }
1783
1784 static int iwl_trans_pcie_start_hw(struct iwl_trans *trans, bool low_power)
1785 {
1786         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1787         int ret;
1788
1789         mutex_lock(&trans_pcie->mutex);
1790         ret = _iwl_trans_pcie_start_hw(trans, low_power);
1791         mutex_unlock(&trans_pcie->mutex);
1792
1793         return ret;
1794 }
1795
1796 static void iwl_trans_pcie_op_mode_leave(struct iwl_trans *trans)
1797 {
1798         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1799
1800         mutex_lock(&trans_pcie->mutex);
1801
1802         /* disable interrupts - don't enable HW RF kill interrupt */
1803         iwl_disable_interrupts(trans);
1804
1805         iwl_pcie_apm_stop(trans, true);
1806
1807         iwl_disable_interrupts(trans);
1808
1809         iwl_pcie_disable_ict(trans);
1810
1811         mutex_unlock(&trans_pcie->mutex);
1812
1813         iwl_pcie_synchronize_irqs(trans);
1814 }
1815
1816 static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val)
1817 {
1818         writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1819 }
1820
1821 static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val)
1822 {
1823         writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1824 }
1825
1826 static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs)
1827 {
1828         return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1829 }
1830
1831 static u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg)
1832 {
1833         iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_RADDR,
1834                                ((reg & 0x000FFFFF) | (3 << 24)));
1835         return iwl_trans_pcie_read32(trans, HBUS_TARG_PRPH_RDAT);
1836 }
1837
1838 static void iwl_trans_pcie_write_prph(struct iwl_trans *trans, u32 addr,
1839                                       u32 val)
1840 {
1841         iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WADDR,
1842                                ((addr & 0x000FFFFF) | (3 << 24)));
1843         iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WDAT, val);
1844 }
1845
1846 static void iwl_trans_pcie_configure(struct iwl_trans *trans,
1847                                      const struct iwl_trans_config *trans_cfg)
1848 {
1849         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1850
1851         trans_pcie->cmd_queue = trans_cfg->cmd_queue;
1852         trans_pcie->cmd_fifo = trans_cfg->cmd_fifo;
1853         trans_pcie->cmd_q_wdg_timeout = trans_cfg->cmd_q_wdg_timeout;
1854         if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS))
1855                 trans_pcie->n_no_reclaim_cmds = 0;
1856         else
1857                 trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds;
1858         if (trans_pcie->n_no_reclaim_cmds)
1859                 memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds,
1860                        trans_pcie->n_no_reclaim_cmds * sizeof(u8));
1861
1862         trans_pcie->rx_buf_size = trans_cfg->rx_buf_size;
1863         trans_pcie->rx_page_order =
1864                 iwl_trans_get_rb_size_order(trans_pcie->rx_buf_size);
1865
1866         trans_pcie->bc_table_dword = trans_cfg->bc_table_dword;
1867         trans_pcie->scd_set_active = trans_cfg->scd_set_active;
1868         trans_pcie->sw_csum_tx = trans_cfg->sw_csum_tx;
1869
1870         trans_pcie->page_offs = trans_cfg->cb_data_offs;
1871         trans_pcie->dev_cmd_offs = trans_cfg->cb_data_offs + sizeof(void *);
1872
1873         trans->command_groups = trans_cfg->command_groups;
1874         trans->command_groups_size = trans_cfg->command_groups_size;
1875
1876         /* Initialize NAPI here - it should be before registering to mac80211
1877          * in the opmode but after the HW struct is allocated.
1878          * As this function may be called again in some corner cases don't
1879          * do anything if NAPI was already initialized.
1880          */
1881         if (trans_pcie->napi_dev.reg_state != NETREG_DUMMY)
1882                 init_dummy_netdev(&trans_pcie->napi_dev);
1883 }
1884
1885 void iwl_trans_pcie_free(struct iwl_trans *trans)
1886 {
1887         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1888         int i;
1889
1890         iwl_pcie_synchronize_irqs(trans);
1891
1892         if (trans->cfg->gen2)
1893                 iwl_pcie_gen2_tx_free(trans);
1894         else
1895                 iwl_pcie_tx_free(trans);
1896         iwl_pcie_rx_free(trans);
1897
1898         if (trans_pcie->rba.alloc_wq) {
1899                 destroy_workqueue(trans_pcie->rba.alloc_wq);
1900                 trans_pcie->rba.alloc_wq = NULL;
1901         }
1902
1903         if (trans_pcie->msix_enabled) {
1904                 for (i = 0; i < trans_pcie->alloc_vecs; i++) {
1905                         irq_set_affinity_hint(
1906                                 trans_pcie->msix_entries[i].vector,
1907                                 NULL);
1908                 }
1909
1910                 trans_pcie->msix_enabled = false;
1911         } else {
1912                 iwl_pcie_free_ict(trans);
1913         }
1914
1915         iwl_pcie_free_fw_monitor(trans);
1916
1917         for_each_possible_cpu(i) {
1918                 struct iwl_tso_hdr_page *p =
1919                         per_cpu_ptr(trans_pcie->tso_hdr_page, i);
1920
1921                 if (p->page)
1922                         __free_page(p->page);
1923         }
1924
1925         free_percpu(trans_pcie->tso_hdr_page);
1926         mutex_destroy(&trans_pcie->mutex);
1927         iwl_trans_free(trans);
1928 }
1929
1930 static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state)
1931 {
1932         if (state)
1933                 set_bit(STATUS_TPOWER_PMI, &trans->status);
1934         else
1935                 clear_bit(STATUS_TPOWER_PMI, &trans->status);
1936 }
1937
1938 static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans,
1939                                            unsigned long *flags)
1940 {
1941         int ret;
1942         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1943
1944         spin_lock_irqsave(&trans_pcie->reg_lock, *flags);
1945
1946         if (trans_pcie->cmd_hold_nic_awake)
1947                 goto out;
1948
1949         /* this bit wakes up the NIC */
1950         __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
1951                                  BIT(trans->cfg->csr->flag_mac_access_req));
1952         if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000)
1953                 udelay(2);
1954
1955         /*
1956          * These bits say the device is running, and should keep running for
1957          * at least a short while (at least as long as MAC_ACCESS_REQ stays 1),
1958          * but they do not indicate that embedded SRAM is restored yet;
1959          * HW with volatile SRAM must save/restore contents to/from
1960          * host DRAM when sleeping/waking for power-saving.
1961          * Each direction takes approximately 1/4 millisecond; with this
1962          * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a
1963          * series of register accesses are expected (e.g. reading Event Log),
1964          * to keep device from sleeping.
1965          *
1966          * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that
1967          * SRAM is okay/restored.  We don't check that here because this call
1968          * is just for hardware register access; but GP1 MAC_SLEEP
1969          * check is a good idea before accessing the SRAM of HW with
1970          * volatile SRAM (e.g. reading Event Log).
1971          *
1972          * 5000 series and later (including 1000 series) have non-volatile SRAM,
1973          * and do not save/restore SRAM when power cycling.
1974          */
1975         ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
1976                            BIT(trans->cfg->csr->flag_val_mac_access_en),
1977                            (BIT(trans->cfg->csr->flag_mac_clock_ready) |
1978                             CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000);
1979         if (unlikely(ret < 0)) {
1980                 iwl_trans_pcie_dump_regs(trans);
1981                 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_FORCE_NMI);
1982                 WARN_ONCE(1,
1983                           "Timeout waiting for hardware access (CSR_GP_CNTRL 0x%08x)\n",
1984                           iwl_read32(trans, CSR_GP_CNTRL));
1985                 spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
1986                 return false;
1987         }
1988
1989 out:
1990         /*
1991          * Fool sparse by faking we release the lock - sparse will
1992          * track nic_access anyway.
1993          */
1994         __release(&trans_pcie->reg_lock);
1995         return true;
1996 }
1997
1998 static void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans,
1999                                               unsigned long *flags)
2000 {
2001         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2002
2003         lockdep_assert_held(&trans_pcie->reg_lock);
2004
2005         /*
2006          * Fool sparse by faking we acquiring the lock - sparse will
2007          * track nic_access anyway.
2008          */
2009         __acquire(&trans_pcie->reg_lock);
2010
2011         if (trans_pcie->cmd_hold_nic_awake)
2012                 goto out;
2013
2014         __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
2015                                    BIT(trans->cfg->csr->flag_mac_access_req));
2016         /*
2017          * Above we read the CSR_GP_CNTRL register, which will flush
2018          * any previous writes, but we need the write that clears the
2019          * MAC_ACCESS_REQ bit to be performed before any other writes
2020          * scheduled on different CPUs (after we drop reg_lock).
2021          */
2022         mmiowb();
2023 out:
2024         spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
2025 }
2026
2027 static int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr,
2028                                    void *buf, int dwords)
2029 {
2030         unsigned long flags;
2031         int offs, ret = 0;
2032         u32 *vals = buf;
2033
2034         if (iwl_trans_grab_nic_access(trans, &flags)) {
2035                 iwl_write32(trans, HBUS_TARG_MEM_RADDR, addr);
2036                 for (offs = 0; offs < dwords; offs++)
2037                         vals[offs] = iwl_read32(trans, HBUS_TARG_MEM_RDAT);
2038                 iwl_trans_release_nic_access(trans, &flags);
2039         } else {
2040                 ret = -EBUSY;
2041         }
2042         return ret;
2043 }
2044
2045 static int iwl_trans_pcie_write_mem(struct iwl_trans *trans, u32 addr,
2046                                     const void *buf, int dwords)
2047 {
2048         unsigned long flags;
2049         int offs, ret = 0;
2050         const u32 *vals = buf;
2051
2052         if (iwl_trans_grab_nic_access(trans, &flags)) {
2053                 iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr);
2054                 for (offs = 0; offs < dwords; offs++)
2055                         iwl_write32(trans, HBUS_TARG_MEM_WDAT,
2056                                     vals ? vals[offs] : 0);
2057                 iwl_trans_release_nic_access(trans, &flags);
2058         } else {
2059                 ret = -EBUSY;
2060         }
2061         return ret;
2062 }
2063
2064 static void iwl_trans_pcie_freeze_txq_timer(struct iwl_trans *trans,
2065                                             unsigned long txqs,
2066                                             bool freeze)
2067 {
2068         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2069         int queue;
2070
2071         for_each_set_bit(queue, &txqs, BITS_PER_LONG) {
2072                 struct iwl_txq *txq = trans_pcie->txq[queue];
2073                 unsigned long now;
2074
2075                 spin_lock_bh(&txq->lock);
2076
2077                 now = jiffies;
2078
2079                 if (txq->frozen == freeze)
2080                         goto next_queue;
2081
2082                 IWL_DEBUG_TX_QUEUES(trans, "%s TXQ %d\n",
2083                                     freeze ? "Freezing" : "Waking", queue);
2084
2085                 txq->frozen = freeze;
2086
2087                 if (txq->read_ptr == txq->write_ptr)
2088                         goto next_queue;
2089
2090                 if (freeze) {
2091                         if (unlikely(time_after(now,
2092                                                 txq->stuck_timer.expires))) {
2093                                 /*
2094                                  * The timer should have fired, maybe it is
2095                                  * spinning right now on the lock.
2096                                  */
2097                                 goto next_queue;
2098                         }
2099                         /* remember how long until the timer fires */
2100                         txq->frozen_expiry_remainder =
2101                                 txq->stuck_timer.expires - now;
2102                         del_timer(&txq->stuck_timer);
2103                         goto next_queue;
2104                 }
2105
2106                 /*
2107                  * Wake a non-empty queue -> arm timer with the
2108                  * remainder before it froze
2109                  */
2110                 mod_timer(&txq->stuck_timer,
2111                           now + txq->frozen_expiry_remainder);
2112
2113 next_queue:
2114                 spin_unlock_bh(&txq->lock);
2115         }
2116 }
2117
2118 static void iwl_trans_pcie_block_txq_ptrs(struct iwl_trans *trans, bool block)
2119 {
2120         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2121         int i;
2122
2123         for (i = 0; i < trans->cfg->base_params->num_of_queues; i++) {
2124                 struct iwl_txq *txq = trans_pcie->txq[i];
2125
2126                 if (i == trans_pcie->cmd_queue)
2127                         continue;
2128
2129                 spin_lock_bh(&txq->lock);
2130
2131                 if (!block && !(WARN_ON_ONCE(!txq->block))) {
2132                         txq->block--;
2133                         if (!txq->block) {
2134                                 iwl_write32(trans, HBUS_TARG_WRPTR,
2135                                             txq->write_ptr | (i << 8));
2136                         }
2137                 } else if (block) {
2138                         txq->block++;
2139                 }
2140
2141                 spin_unlock_bh(&txq->lock);
2142         }
2143 }
2144
2145 #define IWL_FLUSH_WAIT_MS       2000
2146
2147 void iwl_trans_pcie_log_scd_error(struct iwl_trans *trans, struct iwl_txq *txq)
2148 {
2149         u32 txq_id = txq->id;
2150         u32 status;
2151         bool active;
2152         u8 fifo;
2153
2154         if (trans->cfg->use_tfh) {
2155                 IWL_ERR(trans, "Queue %d is stuck %d %d\n", txq_id,
2156                         txq->read_ptr, txq->write_ptr);
2157                 /* TODO: access new SCD registers and dump them */
2158                 return;
2159         }
2160
2161         status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(txq_id));
2162         fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7;
2163         active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE));
2164
2165         IWL_ERR(trans,
2166                 "Queue %d is %sactive on fifo %d and stuck for %u ms. SW [%d, %d] HW [%d, %d] FH TRB=0x0%x\n",
2167                 txq_id, active ? "" : "in", fifo,
2168                 jiffies_to_msecs(txq->wd_timeout),
2169                 txq->read_ptr, txq->write_ptr,
2170                 iwl_read_prph(trans, SCD_QUEUE_RDPTR(txq_id)) &
2171                         (TFD_QUEUE_SIZE_MAX - 1),
2172                 iwl_read_prph(trans, SCD_QUEUE_WRPTR(txq_id)) &
2173                         (TFD_QUEUE_SIZE_MAX - 1),
2174                 iwl_read_direct32(trans, FH_TX_TRB_REG(fifo)));
2175 }
2176
2177 static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans, int txq_idx)
2178 {
2179         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2180         struct iwl_txq *txq;
2181         unsigned long now = jiffies;
2182         u8 wr_ptr;
2183
2184         if (!test_bit(txq_idx, trans_pcie->queue_used))
2185                 return -EINVAL;
2186
2187         IWL_DEBUG_TX_QUEUES(trans, "Emptying queue %d...\n", txq_idx);
2188         txq = trans_pcie->txq[txq_idx];
2189         wr_ptr = READ_ONCE(txq->write_ptr);
2190
2191         while (txq->read_ptr != READ_ONCE(txq->write_ptr) &&
2192                !time_after(jiffies,
2193                            now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS))) {
2194                 u8 write_ptr = READ_ONCE(txq->write_ptr);
2195
2196                 if (WARN_ONCE(wr_ptr != write_ptr,
2197                               "WR pointer moved while flushing %d -> %d\n",
2198                               wr_ptr, write_ptr))
2199                         return -ETIMEDOUT;
2200                 usleep_range(1000, 2000);
2201         }
2202
2203         if (txq->read_ptr != txq->write_ptr) {
2204                 IWL_ERR(trans,
2205                         "fail to flush all tx fifo queues Q %d\n", txq_idx);
2206                 iwl_trans_pcie_log_scd_error(trans, txq);
2207                 return -ETIMEDOUT;
2208         }
2209
2210         IWL_DEBUG_TX_QUEUES(trans, "Queue %d is now empty.\n", txq_idx);
2211
2212         return 0;
2213 }
2214
2215 static int iwl_trans_pcie_wait_txqs_empty(struct iwl_trans *trans, u32 txq_bm)
2216 {
2217         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2218         int cnt;
2219         int ret = 0;
2220
2221         /* waiting for all the tx frames complete might take a while */
2222         for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
2223
2224                 if (cnt == trans_pcie->cmd_queue)
2225                         continue;
2226                 if (!test_bit(cnt, trans_pcie->queue_used))
2227                         continue;
2228                 if (!(BIT(cnt) & txq_bm))
2229                         continue;
2230
2231                 ret = iwl_trans_pcie_wait_txq_empty(trans, cnt);
2232                 if (ret)
2233                         break;
2234         }
2235
2236         return ret;
2237 }
2238
2239 static void iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, u32 reg,
2240                                          u32 mask, u32 value)
2241 {
2242         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2243         unsigned long flags;
2244
2245         spin_lock_irqsave(&trans_pcie->reg_lock, flags);
2246         __iwl_trans_pcie_set_bits_mask(trans, reg, mask, value);
2247         spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
2248 }
2249
2250 static void iwl_trans_pcie_ref(struct iwl_trans *trans)
2251 {
2252         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2253
2254         if (iwlwifi_mod_params.d0i3_disable)
2255                 return;
2256
2257         pm_runtime_get(&trans_pcie->pci_dev->dev);
2258
2259 #ifdef CONFIG_PM
2260         IWL_DEBUG_RPM(trans, "runtime usage count: %d\n",
2261                       atomic_read(&trans_pcie->pci_dev->dev.power.usage_count));
2262 #endif /* CONFIG_PM */
2263 }
2264
2265 static void iwl_trans_pcie_unref(struct iwl_trans *trans)
2266 {
2267         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2268
2269         if (iwlwifi_mod_params.d0i3_disable)
2270                 return;
2271
2272         pm_runtime_mark_last_busy(&trans_pcie->pci_dev->dev);
2273         pm_runtime_put_autosuspend(&trans_pcie->pci_dev->dev);
2274
2275 #ifdef CONFIG_PM
2276         IWL_DEBUG_RPM(trans, "runtime usage count: %d\n",
2277                       atomic_read(&trans_pcie->pci_dev->dev.power.usage_count));
2278 #endif /* CONFIG_PM */
2279 }
2280
2281 static const char *get_csr_string(int cmd)
2282 {
2283 #define IWL_CMD(x) case x: return #x
2284         switch (cmd) {
2285         IWL_CMD(CSR_HW_IF_CONFIG_REG);
2286         IWL_CMD(CSR_INT_COALESCING);
2287         IWL_CMD(CSR_INT);
2288         IWL_CMD(CSR_INT_MASK);
2289         IWL_CMD(CSR_FH_INT_STATUS);
2290         IWL_CMD(CSR_GPIO_IN);
2291         IWL_CMD(CSR_RESET);
2292         IWL_CMD(CSR_GP_CNTRL);
2293         IWL_CMD(CSR_HW_REV);
2294         IWL_CMD(CSR_EEPROM_REG);
2295         IWL_CMD(CSR_EEPROM_GP);
2296         IWL_CMD(CSR_OTP_GP_REG);
2297         IWL_CMD(CSR_GIO_REG);
2298         IWL_CMD(CSR_GP_UCODE_REG);
2299         IWL_CMD(CSR_GP_DRIVER_REG);
2300         IWL_CMD(CSR_UCODE_DRV_GP1);
2301         IWL_CMD(CSR_UCODE_DRV_GP2);
2302         IWL_CMD(CSR_LED_REG);
2303         IWL_CMD(CSR_DRAM_INT_TBL_REG);
2304         IWL_CMD(CSR_GIO_CHICKEN_BITS);
2305         IWL_CMD(CSR_ANA_PLL_CFG);
2306         IWL_CMD(CSR_HW_REV_WA_REG);
2307         IWL_CMD(CSR_MONITOR_STATUS_REG);
2308         IWL_CMD(CSR_DBG_HPET_MEM_REG);
2309         default:
2310                 return "UNKNOWN";
2311         }
2312 #undef IWL_CMD
2313 }
2314
2315 void iwl_pcie_dump_csr(struct iwl_trans *trans)
2316 {
2317         int i;
2318         static const u32 csr_tbl[] = {
2319                 CSR_HW_IF_CONFIG_REG,
2320                 CSR_INT_COALESCING,
2321                 CSR_INT,
2322                 CSR_INT_MASK,
2323                 CSR_FH_INT_STATUS,
2324                 CSR_GPIO_IN,
2325                 CSR_RESET,
2326                 CSR_GP_CNTRL,
2327                 CSR_HW_REV,
2328                 CSR_EEPROM_REG,
2329                 CSR_EEPROM_GP,
2330                 CSR_OTP_GP_REG,
2331                 CSR_GIO_REG,
2332                 CSR_GP_UCODE_REG,
2333                 CSR_GP_DRIVER_REG,
2334                 CSR_UCODE_DRV_GP1,
2335                 CSR_UCODE_DRV_GP2,
2336                 CSR_LED_REG,
2337                 CSR_DRAM_INT_TBL_REG,
2338                 CSR_GIO_CHICKEN_BITS,
2339                 CSR_ANA_PLL_CFG,
2340                 CSR_MONITOR_STATUS_REG,
2341                 CSR_HW_REV_WA_REG,
2342                 CSR_DBG_HPET_MEM_REG
2343         };
2344         IWL_ERR(trans, "CSR values:\n");
2345         IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is "
2346                 "CSR_INT_PERIODIC_REG)\n");
2347         for (i = 0; i <  ARRAY_SIZE(csr_tbl); i++) {
2348                 IWL_ERR(trans, "  %25s: 0X%08x\n",
2349                         get_csr_string(csr_tbl[i]),
2350                         iwl_read32(trans, csr_tbl[i]));
2351         }
2352 }
2353
2354 #ifdef CONFIG_IWLWIFI_DEBUGFS
2355 /* create and remove of files */
2356 #define DEBUGFS_ADD_FILE(name, parent, mode) do {                       \
2357         if (!debugfs_create_file(#name, mode, parent, trans,            \
2358                                  &iwl_dbgfs_##name##_ops))              \
2359                 goto err;                                               \
2360 } while (0)
2361
2362 /* file operation */
2363 #define DEBUGFS_READ_FILE_OPS(name)                                     \
2364 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
2365         .read = iwl_dbgfs_##name##_read,                                \
2366         .open = simple_open,                                            \
2367         .llseek = generic_file_llseek,                                  \
2368 };
2369
2370 #define DEBUGFS_WRITE_FILE_OPS(name)                                    \
2371 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
2372         .write = iwl_dbgfs_##name##_write,                              \
2373         .open = simple_open,                                            \
2374         .llseek = generic_file_llseek,                                  \
2375 };
2376
2377 #define DEBUGFS_READ_WRITE_FILE_OPS(name)                               \
2378 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
2379         .write = iwl_dbgfs_##name##_write,                              \
2380         .read = iwl_dbgfs_##name##_read,                                \
2381         .open = simple_open,                                            \
2382         .llseek = generic_file_llseek,                                  \
2383 };
2384
2385 static ssize_t iwl_dbgfs_tx_queue_read(struct file *file,
2386                                        char __user *user_buf,
2387                                        size_t count, loff_t *ppos)
2388 {
2389         struct iwl_trans *trans = file->private_data;
2390         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2391         struct iwl_txq *txq;
2392         char *buf;
2393         int pos = 0;
2394         int cnt;
2395         int ret;
2396         size_t bufsz;
2397
2398         bufsz = sizeof(char) * 75 * trans->cfg->base_params->num_of_queues;
2399
2400         if (!trans_pcie->txq_memory)
2401                 return -EAGAIN;
2402
2403         buf = kzalloc(bufsz, GFP_KERNEL);
2404         if (!buf)
2405                 return -ENOMEM;
2406
2407         for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
2408                 txq = trans_pcie->txq[cnt];
2409                 pos += scnprintf(buf + pos, bufsz - pos,
2410                                 "hwq %.2d: read=%u write=%u use=%d stop=%d need_update=%d frozen=%d%s\n",
2411                                 cnt, txq->read_ptr, txq->write_ptr,
2412                                 !!test_bit(cnt, trans_pcie->queue_used),
2413                                  !!test_bit(cnt, trans_pcie->queue_stopped),
2414                                  txq->need_update, txq->frozen,
2415                                  (cnt == trans_pcie->cmd_queue ? " HCMD" : ""));
2416         }
2417         ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2418         kfree(buf);
2419         return ret;
2420 }
2421
2422 static ssize_t iwl_dbgfs_rx_queue_read(struct file *file,
2423                                        char __user *user_buf,
2424                                        size_t count, loff_t *ppos)
2425 {
2426         struct iwl_trans *trans = file->private_data;
2427         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2428         char *buf;
2429         int pos = 0, i, ret;
2430         size_t bufsz = sizeof(buf);
2431
2432         bufsz = sizeof(char) * 121 * trans->num_rx_queues;
2433
2434         if (!trans_pcie->rxq)
2435                 return -EAGAIN;
2436
2437         buf = kzalloc(bufsz, GFP_KERNEL);
2438         if (!buf)
2439                 return -ENOMEM;
2440
2441         for (i = 0; i < trans->num_rx_queues && pos < bufsz; i++) {
2442                 struct iwl_rxq *rxq = &trans_pcie->rxq[i];
2443
2444                 pos += scnprintf(buf + pos, bufsz - pos, "queue#: %2d\n",
2445                                  i);
2446                 pos += scnprintf(buf + pos, bufsz - pos, "\tread: %u\n",
2447                                  rxq->read);
2448                 pos += scnprintf(buf + pos, bufsz - pos, "\twrite: %u\n",
2449                                  rxq->write);
2450                 pos += scnprintf(buf + pos, bufsz - pos, "\twrite_actual: %u\n",
2451                                  rxq->write_actual);
2452                 pos += scnprintf(buf + pos, bufsz - pos, "\tneed_update: %2d\n",
2453                                  rxq->need_update);
2454                 pos += scnprintf(buf + pos, bufsz - pos, "\tfree_count: %u\n",
2455                                  rxq->free_count);
2456                 if (rxq->rb_stts) {
2457                         pos += scnprintf(buf + pos, bufsz - pos,
2458                                          "\tclosed_rb_num: %u\n",
2459                                          le16_to_cpu(rxq->rb_stts->closed_rb_num) &
2460                                          0x0FFF);
2461                 } else {
2462                         pos += scnprintf(buf + pos, bufsz - pos,
2463                                          "\tclosed_rb_num: Not Allocated\n");
2464                 }
2465         }
2466         ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2467         kfree(buf);
2468
2469         return ret;
2470 }
2471
2472 static ssize_t iwl_dbgfs_interrupt_read(struct file *file,
2473                                         char __user *user_buf,
2474                                         size_t count, loff_t *ppos)
2475 {
2476         struct iwl_trans *trans = file->private_data;
2477         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2478         struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
2479
2480         int pos = 0;
2481         char *buf;
2482         int bufsz = 24 * 64; /* 24 items * 64 char per item */
2483         ssize_t ret;
2484
2485         buf = kzalloc(bufsz, GFP_KERNEL);
2486         if (!buf)
2487                 return -ENOMEM;
2488
2489         pos += scnprintf(buf + pos, bufsz - pos,
2490                         "Interrupt Statistics Report:\n");
2491
2492         pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n",
2493                 isr_stats->hw);
2494         pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n",
2495                 isr_stats->sw);
2496         if (isr_stats->sw || isr_stats->hw) {
2497                 pos += scnprintf(buf + pos, bufsz - pos,
2498                         "\tLast Restarting Code:  0x%X\n",
2499                         isr_stats->err_code);
2500         }
2501 #ifdef CONFIG_IWLWIFI_DEBUG
2502         pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n",
2503                 isr_stats->sch);
2504         pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n",
2505                 isr_stats->alive);
2506 #endif
2507         pos += scnprintf(buf + pos, bufsz - pos,
2508                 "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill);
2509
2510         pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n",
2511                 isr_stats->ctkill);
2512
2513         pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n",
2514                 isr_stats->wakeup);
2515
2516         pos += scnprintf(buf + pos, bufsz - pos,
2517                 "Rx command responses:\t\t %u\n", isr_stats->rx);
2518
2519         pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n",
2520                 isr_stats->tx);
2521
2522         pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n",
2523                 isr_stats->unhandled);
2524
2525         ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2526         kfree(buf);
2527         return ret;
2528 }
2529
2530 static ssize_t iwl_dbgfs_interrupt_write(struct file *file,
2531                                          const char __user *user_buf,
2532                                          size_t count, loff_t *ppos)
2533 {
2534         struct iwl_trans *trans = file->private_data;
2535         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2536         struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
2537         u32 reset_flag;
2538         int ret;
2539
2540         ret = kstrtou32_from_user(user_buf, count, 16, &reset_flag);
2541         if (ret)
2542                 return ret;
2543         if (reset_flag == 0)
2544                 memset(isr_stats, 0, sizeof(*isr_stats));
2545
2546         return count;
2547 }
2548
2549 static ssize_t iwl_dbgfs_csr_write(struct file *file,
2550                                    const char __user *user_buf,
2551                                    size_t count, loff_t *ppos)
2552 {
2553         struct iwl_trans *trans = file->private_data;
2554
2555         iwl_pcie_dump_csr(trans);
2556
2557         return count;
2558 }
2559
2560 static ssize_t iwl_dbgfs_fh_reg_read(struct file *file,
2561                                      char __user *user_buf,
2562                                      size_t count, loff_t *ppos)
2563 {
2564         struct iwl_trans *trans = file->private_data;
2565         char *buf = NULL;
2566         ssize_t ret;
2567
2568         ret = iwl_dump_fh(trans, &buf);
2569         if (ret < 0)
2570                 return ret;
2571         if (!buf)
2572                 return -EINVAL;
2573         ret = simple_read_from_buffer(user_buf, count, ppos, buf, ret);
2574         kfree(buf);
2575         return ret;
2576 }
2577
2578 static ssize_t iwl_dbgfs_rfkill_read(struct file *file,
2579                                      char __user *user_buf,
2580                                      size_t count, loff_t *ppos)
2581 {
2582         struct iwl_trans *trans = file->private_data;
2583         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2584         char buf[100];
2585         int pos;
2586
2587         pos = scnprintf(buf, sizeof(buf), "debug: %d\nhw: %d\n",
2588                         trans_pcie->debug_rfkill,
2589                         !(iwl_read32(trans, CSR_GP_CNTRL) &
2590                                 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW));
2591
2592         return simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2593 }
2594
2595 static ssize_t iwl_dbgfs_rfkill_write(struct file *file,
2596                                       const char __user *user_buf,
2597                                       size_t count, loff_t *ppos)
2598 {
2599         struct iwl_trans *trans = file->private_data;
2600         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2601         bool old = trans_pcie->debug_rfkill;
2602         int ret;
2603
2604         ret = kstrtobool_from_user(user_buf, count, &trans_pcie->debug_rfkill);
2605         if (ret)
2606                 return ret;
2607         if (old == trans_pcie->debug_rfkill)
2608                 return count;
2609         IWL_WARN(trans, "changing debug rfkill %d->%d\n",
2610                  old, trans_pcie->debug_rfkill);
2611         iwl_pcie_handle_rfkill_irq(trans);
2612
2613         return count;
2614 }
2615
2616 DEBUGFS_READ_WRITE_FILE_OPS(interrupt);
2617 DEBUGFS_READ_FILE_OPS(fh_reg);
2618 DEBUGFS_READ_FILE_OPS(rx_queue);
2619 DEBUGFS_READ_FILE_OPS(tx_queue);
2620 DEBUGFS_WRITE_FILE_OPS(csr);
2621 DEBUGFS_READ_WRITE_FILE_OPS(rfkill);
2622
2623 /* Create the debugfs files and directories */
2624 int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans)
2625 {
2626         struct dentry *dir = trans->dbgfs_dir;
2627
2628         DEBUGFS_ADD_FILE(rx_queue, dir, 0400);
2629         DEBUGFS_ADD_FILE(tx_queue, dir, 0400);
2630         DEBUGFS_ADD_FILE(interrupt, dir, 0600);
2631         DEBUGFS_ADD_FILE(csr, dir, 0200);
2632         DEBUGFS_ADD_FILE(fh_reg, dir, 0400);
2633         DEBUGFS_ADD_FILE(rfkill, dir, 0600);
2634         return 0;
2635
2636 err:
2637         IWL_ERR(trans, "failed to create the trans debugfs entry\n");
2638         return -ENOMEM;
2639 }
2640 #endif /*CONFIG_IWLWIFI_DEBUGFS */
2641
2642 static u32 iwl_trans_pcie_get_cmdlen(struct iwl_trans *trans, void *tfd)
2643 {
2644         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2645         u32 cmdlen = 0;
2646         int i;
2647
2648         for (i = 0; i < trans_pcie->max_tbs; i++)
2649                 cmdlen += iwl_pcie_tfd_tb_get_len(trans, tfd, i);
2650
2651         return cmdlen;
2652 }
2653
2654 static u32 iwl_trans_pcie_dump_rbs(struct iwl_trans *trans,
2655                                    struct iwl_fw_error_dump_data **data,
2656                                    int allocated_rb_nums)
2657 {
2658         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2659         int max_len = PAGE_SIZE << trans_pcie->rx_page_order;
2660         /* Dump RBs is supported only for pre-9000 devices (1 queue) */
2661         struct iwl_rxq *rxq = &trans_pcie->rxq[0];
2662         u32 i, r, j, rb_len = 0;
2663
2664         spin_lock(&rxq->lock);
2665
2666         r = le16_to_cpu(READ_ONCE(rxq->rb_stts->closed_rb_num)) & 0x0FFF;
2667
2668         for (i = rxq->read, j = 0;
2669              i != r && j < allocated_rb_nums;
2670              i = (i + 1) & RX_QUEUE_MASK, j++) {
2671                 struct iwl_rx_mem_buffer *rxb = rxq->queue[i];
2672                 struct iwl_fw_error_dump_rb *rb;
2673
2674                 dma_unmap_page(trans->dev, rxb->page_dma, max_len,
2675                                DMA_FROM_DEVICE);
2676
2677                 rb_len += sizeof(**data) + sizeof(*rb) + max_len;
2678
2679                 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RB);
2680                 (*data)->len = cpu_to_le32(sizeof(*rb) + max_len);
2681                 rb = (void *)(*data)->data;
2682                 rb->index = cpu_to_le32(i);
2683                 memcpy(rb->data, page_address(rxb->page), max_len);
2684                 /* remap the page for the free benefit */
2685                 rxb->page_dma = dma_map_page(trans->dev, rxb->page, 0,
2686                                                      max_len,
2687                                                      DMA_FROM_DEVICE);
2688
2689                 *data = iwl_fw_error_next_data(*data);
2690         }
2691
2692         spin_unlock(&rxq->lock);
2693
2694         return rb_len;
2695 }
2696 #define IWL_CSR_TO_DUMP (0x250)
2697
2698 static u32 iwl_trans_pcie_dump_csr(struct iwl_trans *trans,
2699                                    struct iwl_fw_error_dump_data **data)
2700 {
2701         u32 csr_len = sizeof(**data) + IWL_CSR_TO_DUMP;
2702         __le32 *val;
2703         int i;
2704
2705         (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_CSR);
2706         (*data)->len = cpu_to_le32(IWL_CSR_TO_DUMP);
2707         val = (void *)(*data)->data;
2708
2709         for (i = 0; i < IWL_CSR_TO_DUMP; i += 4)
2710                 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i));
2711
2712         *data = iwl_fw_error_next_data(*data);
2713
2714         return csr_len;
2715 }
2716
2717 static u32 iwl_trans_pcie_fh_regs_dump(struct iwl_trans *trans,
2718                                        struct iwl_fw_error_dump_data **data)
2719 {
2720         u32 fh_regs_len = FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND;
2721         unsigned long flags;
2722         __le32 *val;
2723         int i;
2724
2725         if (!iwl_trans_grab_nic_access(trans, &flags))
2726                 return 0;
2727
2728         (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FH_REGS);
2729         (*data)->len = cpu_to_le32(fh_regs_len);
2730         val = (void *)(*data)->data;
2731
2732         if (!trans->cfg->gen2)
2733                 for (i = FH_MEM_LOWER_BOUND; i < FH_MEM_UPPER_BOUND;
2734                      i += sizeof(u32))
2735                         *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i));
2736         else
2737                 for (i = FH_MEM_LOWER_BOUND_GEN2; i < FH_MEM_UPPER_BOUND_GEN2;
2738                      i += sizeof(u32))
2739                         *val++ = cpu_to_le32(iwl_trans_pcie_read_prph(trans,
2740                                                                       i));
2741
2742         iwl_trans_release_nic_access(trans, &flags);
2743
2744         *data = iwl_fw_error_next_data(*data);
2745
2746         return sizeof(**data) + fh_regs_len;
2747 }
2748
2749 static u32
2750 iwl_trans_pci_dump_marbh_monitor(struct iwl_trans *trans,
2751                                  struct iwl_fw_error_dump_fw_mon *fw_mon_data,
2752                                  u32 monitor_len)
2753 {
2754         u32 buf_size_in_dwords = (monitor_len >> 2);
2755         u32 *buffer = (u32 *)fw_mon_data->data;
2756         unsigned long flags;
2757         u32 i;
2758
2759         if (!iwl_trans_grab_nic_access(trans, &flags))
2760                 return 0;
2761
2762         iwl_write_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x1);
2763         for (i = 0; i < buf_size_in_dwords; i++)
2764                 buffer[i] = iwl_read_prph_no_grab(trans,
2765                                 MON_DMARB_RD_DATA_ADDR);
2766         iwl_write_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x0);
2767
2768         iwl_trans_release_nic_access(trans, &flags);
2769
2770         return monitor_len;
2771 }
2772
2773 static u32
2774 iwl_trans_pcie_dump_monitor(struct iwl_trans *trans,
2775                             struct iwl_fw_error_dump_data **data,
2776                             u32 monitor_len)
2777 {
2778         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2779         u32 len = 0;
2780
2781         if ((trans_pcie->fw_mon_page &&
2782              trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) ||
2783             trans->dbg_dest_tlv) {
2784                 struct iwl_fw_error_dump_fw_mon *fw_mon_data;
2785                 u32 base, write_ptr, wrap_cnt;
2786
2787                 /* If there was a dest TLV - use the values from there */
2788                 if (trans->dbg_dest_tlv) {
2789                         write_ptr =
2790                                 le32_to_cpu(trans->dbg_dest_tlv->write_ptr_reg);
2791                         wrap_cnt = le32_to_cpu(trans->dbg_dest_tlv->wrap_count);
2792                         base = le32_to_cpu(trans->dbg_dest_tlv->base_reg);
2793                 } else {
2794                         base = MON_BUFF_BASE_ADDR;
2795                         write_ptr = MON_BUFF_WRPTR;
2796                         wrap_cnt = MON_BUFF_CYCLE_CNT;
2797                 }
2798
2799                 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FW_MONITOR);
2800                 fw_mon_data = (void *)(*data)->data;
2801                 fw_mon_data->fw_mon_wr_ptr =
2802                         cpu_to_le32(iwl_read_prph(trans, write_ptr));
2803                 fw_mon_data->fw_mon_cycle_cnt =
2804                         cpu_to_le32(iwl_read_prph(trans, wrap_cnt));
2805                 fw_mon_data->fw_mon_base_ptr =
2806                         cpu_to_le32(iwl_read_prph(trans, base));
2807
2808                 len += sizeof(**data) + sizeof(*fw_mon_data);
2809                 if (trans_pcie->fw_mon_page) {
2810                         /*
2811                          * The firmware is now asserted, it won't write anything
2812                          * to the buffer. CPU can take ownership to fetch the
2813                          * data. The buffer will be handed back to the device
2814                          * before the firmware will be restarted.
2815                          */
2816                         dma_sync_single_for_cpu(trans->dev,
2817                                                 trans_pcie->fw_mon_phys,
2818                                                 trans_pcie->fw_mon_size,
2819                                                 DMA_FROM_DEVICE);
2820                         memcpy(fw_mon_data->data,
2821                                page_address(trans_pcie->fw_mon_page),
2822                                trans_pcie->fw_mon_size);
2823
2824                         monitor_len = trans_pcie->fw_mon_size;
2825                 } else if (trans->dbg_dest_tlv->monitor_mode == SMEM_MODE) {
2826                         /*
2827                          * Update pointers to reflect actual values after
2828                          * shifting
2829                          */
2830                         if (trans->dbg_dest_tlv->version) {
2831                                 base = (iwl_read_prph(trans, base) &
2832                                         IWL_LDBG_M2S_BUF_BA_MSK) <<
2833                                        trans->dbg_dest_tlv->base_shift;
2834                                 base *= IWL_M2S_UNIT_SIZE;
2835                                 base += trans->cfg->smem_offset;
2836                         } else {
2837                                 base = iwl_read_prph(trans, base) <<
2838                                        trans->dbg_dest_tlv->base_shift;
2839                         }
2840
2841                         iwl_trans_read_mem(trans, base, fw_mon_data->data,
2842                                            monitor_len / sizeof(u32));
2843                 } else if (trans->dbg_dest_tlv->monitor_mode == MARBH_MODE) {
2844                         monitor_len =
2845                                 iwl_trans_pci_dump_marbh_monitor(trans,
2846                                                                  fw_mon_data,
2847                                                                  monitor_len);
2848                 } else {
2849                         /* Didn't match anything - output no monitor data */
2850                         monitor_len = 0;
2851                 }
2852
2853                 len += monitor_len;
2854                 (*data)->len = cpu_to_le32(monitor_len + sizeof(*fw_mon_data));
2855         }
2856
2857         return len;
2858 }
2859
2860 static struct iwl_trans_dump_data
2861 *iwl_trans_pcie_dump_data(struct iwl_trans *trans,
2862                           const struct iwl_fw_dbg_trigger_tlv *trigger)
2863 {
2864         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2865         struct iwl_fw_error_dump_data *data;
2866         struct iwl_txq *cmdq = trans_pcie->txq[trans_pcie->cmd_queue];
2867         struct iwl_fw_error_dump_txcmd *txcmd;
2868         struct iwl_trans_dump_data *dump_data;
2869         u32 len, num_rbs;
2870         u32 monitor_len;
2871         int i, ptr;
2872         bool dump_rbs = test_bit(STATUS_FW_ERROR, &trans->status) &&
2873                         !trans->cfg->mq_rx_supported;
2874
2875         /* transport dump header */
2876         len = sizeof(*dump_data);
2877
2878         /* host commands */
2879         len += sizeof(*data) +
2880                 cmdq->n_window * (sizeof(*txcmd) + TFD_MAX_PAYLOAD_SIZE);
2881
2882         /* FW monitor */
2883         if (trans_pcie->fw_mon_page) {
2884                 len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_fw_mon) +
2885                        trans_pcie->fw_mon_size;
2886                 monitor_len = trans_pcie->fw_mon_size;
2887         } else if (trans->dbg_dest_tlv) {
2888                 u32 base, end, cfg_reg;
2889
2890                 if (trans->dbg_dest_tlv->version == 1) {
2891                         cfg_reg = le32_to_cpu(trans->dbg_dest_tlv->base_reg);
2892                         cfg_reg = iwl_read_prph(trans, cfg_reg);
2893                         base = (cfg_reg & IWL_LDBG_M2S_BUF_BA_MSK) <<
2894                                 trans->dbg_dest_tlv->base_shift;
2895                         base *= IWL_M2S_UNIT_SIZE;
2896                         base += trans->cfg->smem_offset;
2897
2898                         monitor_len =
2899                                 (cfg_reg & IWL_LDBG_M2S_BUF_SIZE_MSK) >>
2900                                 trans->dbg_dest_tlv->end_shift;
2901                         monitor_len *= IWL_M2S_UNIT_SIZE;
2902                 } else {
2903                         base = le32_to_cpu(trans->dbg_dest_tlv->base_reg);
2904                         end = le32_to_cpu(trans->dbg_dest_tlv->end_reg);
2905
2906                         base = iwl_read_prph(trans, base) <<
2907                                trans->dbg_dest_tlv->base_shift;
2908                         end = iwl_read_prph(trans, end) <<
2909                               trans->dbg_dest_tlv->end_shift;
2910
2911                         /* Make "end" point to the actual end */
2912                         if (trans->cfg->device_family >=
2913                             IWL_DEVICE_FAMILY_8000 ||
2914                             trans->dbg_dest_tlv->monitor_mode == MARBH_MODE)
2915                                 end += (1 << trans->dbg_dest_tlv->end_shift);
2916                         monitor_len = end - base;
2917                 }
2918                 len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_fw_mon) +
2919                        monitor_len;
2920         } else {
2921                 monitor_len = 0;
2922         }
2923
2924         if (trigger && (trigger->mode & IWL_FW_DBG_TRIGGER_MONITOR_ONLY)) {
2925                 dump_data = vzalloc(len);
2926                 if (!dump_data)
2927                         return NULL;
2928
2929                 data = (void *)dump_data->data;
2930                 len = iwl_trans_pcie_dump_monitor(trans, &data, monitor_len);
2931                 dump_data->len = len;
2932
2933                 return dump_data;
2934         }
2935
2936         /* CSR registers */
2937         len += sizeof(*data) + IWL_CSR_TO_DUMP;
2938
2939         /* FH registers */
2940         if (trans->cfg->gen2)
2941                 len += sizeof(*data) +
2942                        (FH_MEM_UPPER_BOUND_GEN2 - FH_MEM_LOWER_BOUND_GEN2);
2943         else
2944                 len += sizeof(*data) +
2945                        (FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND);
2946
2947         if (dump_rbs) {
2948                 /* Dump RBs is supported only for pre-9000 devices (1 queue) */
2949                 struct iwl_rxq *rxq = &trans_pcie->rxq[0];
2950                 /* RBs */
2951                 num_rbs = le16_to_cpu(READ_ONCE(rxq->rb_stts->closed_rb_num))
2952                                       & 0x0FFF;
2953                 num_rbs = (num_rbs - rxq->read) & RX_QUEUE_MASK;
2954                 len += num_rbs * (sizeof(*data) +
2955                                   sizeof(struct iwl_fw_error_dump_rb) +
2956                                   (PAGE_SIZE << trans_pcie->rx_page_order));
2957         }
2958
2959         /* Paged memory for gen2 HW */
2960         if (trans->cfg->gen2)
2961                 for (i = 0; i < trans_pcie->init_dram.paging_cnt; i++)
2962                         len += sizeof(*data) +
2963                                sizeof(struct iwl_fw_error_dump_paging) +
2964                                trans_pcie->init_dram.paging[i].size;
2965
2966         dump_data = vzalloc(len);
2967         if (!dump_data)
2968                 return NULL;
2969
2970         len = 0;
2971         data = (void *)dump_data->data;
2972         data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_TXCMD);
2973         txcmd = (void *)data->data;
2974         spin_lock_bh(&cmdq->lock);
2975         ptr = cmdq->write_ptr;
2976         for (i = 0; i < cmdq->n_window; i++) {
2977                 u8 idx = iwl_pcie_get_cmd_index(cmdq, ptr);
2978                 u32 caplen, cmdlen;
2979
2980                 cmdlen = iwl_trans_pcie_get_cmdlen(trans, cmdq->tfds +
2981                                                    trans_pcie->tfd_size * ptr);
2982                 caplen = min_t(u32, TFD_MAX_PAYLOAD_SIZE, cmdlen);
2983
2984                 if (cmdlen) {
2985                         len += sizeof(*txcmd) + caplen;
2986                         txcmd->cmdlen = cpu_to_le32(cmdlen);
2987                         txcmd->caplen = cpu_to_le32(caplen);
2988                         memcpy(txcmd->data, cmdq->entries[idx].cmd, caplen);
2989                         txcmd = (void *)((u8 *)txcmd->data + caplen);
2990                 }
2991
2992                 ptr = iwl_queue_dec_wrap(ptr);
2993         }
2994         spin_unlock_bh(&cmdq->lock);
2995
2996         data->len = cpu_to_le32(len);
2997         len += sizeof(*data);
2998         data = iwl_fw_error_next_data(data);
2999
3000         len += iwl_trans_pcie_dump_csr(trans, &data);
3001         len += iwl_trans_pcie_fh_regs_dump(trans, &data);
3002         if (dump_rbs)
3003                 len += iwl_trans_pcie_dump_rbs(trans, &data, num_rbs);
3004
3005         /* Paged memory for gen2 HW */
3006         if (trans->cfg->gen2) {
3007                 for (i = 0; i < trans_pcie->init_dram.paging_cnt; i++) {
3008                         struct iwl_fw_error_dump_paging *paging;
3009                         dma_addr_t addr =
3010                                 trans_pcie->init_dram.paging[i].physical;
3011                         u32 page_len = trans_pcie->init_dram.paging[i].size;
3012
3013                         data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PAGING);
3014                         data->len = cpu_to_le32(sizeof(*paging) + page_len);
3015                         paging = (void *)data->data;
3016                         paging->index = cpu_to_le32(i);
3017                         dma_sync_single_for_cpu(trans->dev, addr, page_len,
3018                                                 DMA_BIDIRECTIONAL);
3019                         memcpy(paging->data,
3020                                trans_pcie->init_dram.paging[i].block, page_len);
3021                         data = iwl_fw_error_next_data(data);
3022
3023                         len += sizeof(*data) + sizeof(*paging) + page_len;
3024                 }
3025         }
3026
3027         len += iwl_trans_pcie_dump_monitor(trans, &data, monitor_len);
3028
3029         dump_data->len = len;
3030
3031         return dump_data;
3032 }
3033
3034 #ifdef CONFIG_PM_SLEEP
3035 static int iwl_trans_pcie_suspend(struct iwl_trans *trans)
3036 {
3037         if (trans->runtime_pm_mode == IWL_PLAT_PM_MODE_D0I3 &&
3038             (trans->system_pm_mode == IWL_PLAT_PM_MODE_D0I3))
3039                 return iwl_pci_fw_enter_d0i3(trans);
3040
3041         return 0;
3042 }
3043
3044 static void iwl_trans_pcie_resume(struct iwl_trans *trans)
3045 {
3046         if (trans->runtime_pm_mode == IWL_PLAT_PM_MODE_D0I3 &&
3047             (trans->system_pm_mode == IWL_PLAT_PM_MODE_D0I3))
3048                 iwl_pci_fw_exit_d0i3(trans);
3049 }
3050 #endif /* CONFIG_PM_SLEEP */
3051
3052 #define IWL_TRANS_COMMON_OPS                                            \
3053         .op_mode_leave = iwl_trans_pcie_op_mode_leave,                  \
3054         .write8 = iwl_trans_pcie_write8,                                \
3055         .write32 = iwl_trans_pcie_write32,                              \
3056         .read32 = iwl_trans_pcie_read32,                                \
3057         .read_prph = iwl_trans_pcie_read_prph,                          \
3058         .write_prph = iwl_trans_pcie_write_prph,                        \
3059         .read_mem = iwl_trans_pcie_read_mem,                            \
3060         .write_mem = iwl_trans_pcie_write_mem,                          \
3061         .configure = iwl_trans_pcie_configure,                          \
3062         .set_pmi = iwl_trans_pcie_set_pmi,                              \
3063         .sw_reset = iwl_trans_pcie_sw_reset,                            \
3064         .grab_nic_access = iwl_trans_pcie_grab_nic_access,              \
3065         .release_nic_access = iwl_trans_pcie_release_nic_access,        \
3066         .set_bits_mask = iwl_trans_pcie_set_bits_mask,                  \
3067         .ref = iwl_trans_pcie_ref,                                      \
3068         .unref = iwl_trans_pcie_unref,                                  \
3069         .dump_data = iwl_trans_pcie_dump_data,                          \
3070         .dump_regs = iwl_trans_pcie_dump_regs,                          \
3071         .d3_suspend = iwl_trans_pcie_d3_suspend,                        \
3072         .d3_resume = iwl_trans_pcie_d3_resume
3073
3074 #ifdef CONFIG_PM_SLEEP
3075 #define IWL_TRANS_PM_OPS                                                \
3076         .suspend = iwl_trans_pcie_suspend,                              \
3077         .resume = iwl_trans_pcie_resume,
3078 #else
3079 #define IWL_TRANS_PM_OPS
3080 #endif /* CONFIG_PM_SLEEP */
3081
3082 static const struct iwl_trans_ops trans_ops_pcie = {
3083         IWL_TRANS_COMMON_OPS,
3084         IWL_TRANS_PM_OPS
3085         .start_hw = iwl_trans_pcie_start_hw,
3086         .fw_alive = iwl_trans_pcie_fw_alive,
3087         .start_fw = iwl_trans_pcie_start_fw,
3088         .stop_device = iwl_trans_pcie_stop_device,
3089
3090         .send_cmd = iwl_trans_pcie_send_hcmd,
3091
3092         .tx = iwl_trans_pcie_tx,
3093         .reclaim = iwl_trans_pcie_reclaim,
3094
3095         .txq_disable = iwl_trans_pcie_txq_disable,
3096         .txq_enable = iwl_trans_pcie_txq_enable,
3097
3098         .txq_set_shared_mode = iwl_trans_pcie_txq_set_shared_mode,
3099
3100         .wait_tx_queues_empty = iwl_trans_pcie_wait_txqs_empty,
3101
3102         .freeze_txq_timer = iwl_trans_pcie_freeze_txq_timer,
3103         .block_txq_ptrs = iwl_trans_pcie_block_txq_ptrs,
3104 };
3105
3106 static const struct iwl_trans_ops trans_ops_pcie_gen2 = {
3107         IWL_TRANS_COMMON_OPS,
3108         IWL_TRANS_PM_OPS
3109         .start_hw = iwl_trans_pcie_start_hw,
3110         .fw_alive = iwl_trans_pcie_gen2_fw_alive,
3111         .start_fw = iwl_trans_pcie_gen2_start_fw,
3112         .stop_device = iwl_trans_pcie_gen2_stop_device,
3113
3114         .send_cmd = iwl_trans_pcie_gen2_send_hcmd,
3115
3116         .tx = iwl_trans_pcie_gen2_tx,
3117         .reclaim = iwl_trans_pcie_reclaim,
3118
3119         .txq_alloc = iwl_trans_pcie_dyn_txq_alloc,
3120         .txq_free = iwl_trans_pcie_dyn_txq_free,
3121         .wait_txq_empty = iwl_trans_pcie_wait_txq_empty,
3122 };
3123
3124 struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev,
3125                                        const struct pci_device_id *ent,
3126                                        const struct iwl_cfg *cfg)
3127 {
3128         struct iwl_trans_pcie *trans_pcie;
3129         struct iwl_trans *trans;
3130         int ret, addr_size;
3131
3132         ret = pcim_enable_device(pdev);
3133         if (ret)
3134                 return ERR_PTR(ret);
3135
3136         if (cfg->gen2)
3137                 trans = iwl_trans_alloc(sizeof(struct iwl_trans_pcie),
3138                                         &pdev->dev, cfg, &trans_ops_pcie_gen2);
3139         else
3140                 trans = iwl_trans_alloc(sizeof(struct iwl_trans_pcie),
3141                                         &pdev->dev, cfg, &trans_ops_pcie);
3142         if (!trans)
3143                 return ERR_PTR(-ENOMEM);
3144
3145         trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
3146
3147         trans_pcie->trans = trans;
3148         trans_pcie->opmode_down = true;
3149         spin_lock_init(&trans_pcie->irq_lock);
3150         spin_lock_init(&trans_pcie->reg_lock);
3151         mutex_init(&trans_pcie->mutex);
3152         init_waitqueue_head(&trans_pcie->ucode_write_waitq);
3153         trans_pcie->tso_hdr_page = alloc_percpu(struct iwl_tso_hdr_page);
3154         if (!trans_pcie->tso_hdr_page) {
3155                 ret = -ENOMEM;
3156                 goto out_no_pci;
3157         }
3158
3159
3160         if (!cfg->base_params->pcie_l1_allowed) {
3161                 /*
3162                  * W/A - seems to solve weird behavior. We need to remove this
3163                  * if we don't want to stay in L1 all the time. This wastes a
3164                  * lot of power.
3165                  */
3166                 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S |
3167                                        PCIE_LINK_STATE_L1 |
3168                                        PCIE_LINK_STATE_CLKPM);
3169         }
3170
3171         if (cfg->use_tfh) {
3172                 addr_size = 64;
3173                 trans_pcie->max_tbs = IWL_TFH_NUM_TBS;
3174                 trans_pcie->tfd_size = sizeof(struct iwl_tfh_tfd);
3175         } else {
3176                 addr_size = 36;
3177                 trans_pcie->max_tbs = IWL_NUM_OF_TBS;
3178                 trans_pcie->tfd_size = sizeof(struct iwl_tfd);
3179         }
3180         trans->max_skb_frags = IWL_PCIE_MAX_FRAGS(trans_pcie);
3181
3182         pci_set_master(pdev);
3183
3184         ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(addr_size));
3185         if (!ret)
3186                 ret = pci_set_consistent_dma_mask(pdev,
3187                                                   DMA_BIT_MASK(addr_size));
3188         if (ret) {
3189                 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
3190                 if (!ret)
3191                         ret = pci_set_consistent_dma_mask(pdev,
3192                                                           DMA_BIT_MASK(32));
3193                 /* both attempts failed: */
3194                 if (ret) {
3195                         dev_err(&pdev->dev, "No suitable DMA available\n");
3196                         goto out_no_pci;
3197                 }
3198         }
3199
3200         ret = pcim_iomap_regions_request_all(pdev, BIT(0), DRV_NAME);
3201         if (ret) {
3202                 dev_err(&pdev->dev, "pcim_iomap_regions_request_all failed\n");
3203                 goto out_no_pci;
3204         }
3205
3206         trans_pcie->hw_base = pcim_iomap_table(pdev)[0];
3207         if (!trans_pcie->hw_base) {
3208                 dev_err(&pdev->dev, "pcim_iomap_table failed\n");
3209                 ret = -ENODEV;
3210                 goto out_no_pci;
3211         }
3212
3213         /* We disable the RETRY_TIMEOUT register (0x41) to keep
3214          * PCI Tx retries from interfering with C3 CPU state */
3215         pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
3216
3217         trans_pcie->pci_dev = pdev;
3218         iwl_disable_interrupts(trans);
3219
3220         trans->hw_rev = iwl_read32(trans, CSR_HW_REV);
3221         /*
3222          * In the 8000 HW family the format of the 4 bytes of CSR_HW_REV have
3223          * changed, and now the revision step also includes bit 0-1 (no more
3224          * "dash" value). To keep hw_rev backwards compatible - we'll store it
3225          * in the old format.
3226          */
3227         if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000) {
3228                 unsigned long flags;
3229
3230                 trans->hw_rev = (trans->hw_rev & 0xfff0) |
3231                                 (CSR_HW_REV_STEP(trans->hw_rev << 2) << 2);
3232
3233                 ret = iwl_pcie_prepare_card_hw(trans);
3234                 if (ret) {
3235                         IWL_WARN(trans, "Exit HW not ready\n");
3236                         goto out_no_pci;
3237                 }
3238
3239                 /*
3240                  * in-order to recognize C step driver should read chip version
3241                  * id located at the AUX bus MISC address space.
3242                  */
3243                 iwl_set_bit(trans, CSR_GP_CNTRL,
3244                             BIT(trans->cfg->csr->flag_init_done));
3245                 udelay(2);
3246
3247                 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
3248                                    BIT(trans->cfg->csr->flag_mac_clock_ready),
3249                                    BIT(trans->cfg->csr->flag_mac_clock_ready),
3250                                    25000);
3251                 if (ret < 0) {
3252                         IWL_DEBUG_INFO(trans, "Failed to wake up the nic\n");
3253                         goto out_no_pci;
3254                 }
3255
3256                 if (iwl_trans_grab_nic_access(trans, &flags)) {
3257                         u32 hw_step;
3258
3259                         hw_step = iwl_read_prph_no_grab(trans, WFPM_CTRL_REG);
3260                         hw_step |= ENABLE_WFPM;
3261                         iwl_write_prph_no_grab(trans, WFPM_CTRL_REG, hw_step);
3262                         hw_step = iwl_read_prph_no_grab(trans, AUX_MISC_REG);
3263                         hw_step = (hw_step >> HW_STEP_LOCATION_BITS) & 0xF;
3264                         if (hw_step == 0x3)
3265                                 trans->hw_rev = (trans->hw_rev & 0xFFFFFFF3) |
3266                                                 (SILICON_C_STEP << 2);
3267                         iwl_trans_release_nic_access(trans, &flags);
3268                 }
3269         }
3270
3271         /*
3272          * 9000-series integrated A-step has a problem with suspend/resume
3273          * and sometimes even causes the whole platform to get stuck. This
3274          * workaround makes the hardware not go into the problematic state.
3275          */
3276         if (trans->cfg->integrated &&
3277             trans->cfg->device_family == IWL_DEVICE_FAMILY_9000 &&
3278             CSR_HW_REV_STEP(trans->hw_rev) == SILICON_A_STEP)
3279                 iwl_set_bit(trans, CSR_HOST_CHICKEN,
3280                             CSR_HOST_CHICKEN_PM_IDLE_SRC_DIS_SB_PME);
3281
3282 #if IS_ENABLED(CONFIG_IWLMVM)
3283         trans->hw_rf_id = iwl_read32(trans, CSR_HW_RF_ID);
3284         if (trans->hw_rf_id == CSR_HW_RF_ID_TYPE_HR) {
3285                 u32 hw_status;
3286
3287                 hw_status = iwl_read_prph(trans, UMAG_GEN_HW_STATUS);
3288                 if (hw_status & UMAG_GEN_HW_IS_FPGA)
3289                         trans->cfg = &iwl22000_2ax_cfg_qnj_hr_f0;
3290                 else
3291                         trans->cfg = &iwl22000_2ac_cfg_hr;
3292         }
3293 #endif
3294
3295         iwl_pcie_set_interrupt_capa(pdev, trans);
3296         trans->hw_id = (pdev->device << 16) + pdev->subsystem_device;
3297         snprintf(trans->hw_id_str, sizeof(trans->hw_id_str),
3298                  "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device);
3299
3300         /* Initialize the wait queue for commands */
3301         init_waitqueue_head(&trans_pcie->wait_command_queue);
3302
3303         init_waitqueue_head(&trans_pcie->d0i3_waitq);
3304
3305         if (trans_pcie->msix_enabled) {
3306                 ret = iwl_pcie_init_msix_handler(pdev, trans_pcie);
3307                 if (ret)
3308                         goto out_no_pci;
3309          } else {
3310                 ret = iwl_pcie_alloc_ict(trans);
3311                 if (ret)
3312                         goto out_no_pci;
3313
3314                 ret = devm_request_threaded_irq(&pdev->dev, pdev->irq,
3315                                                 iwl_pcie_isr,
3316                                                 iwl_pcie_irq_handler,
3317                                                 IRQF_SHARED, DRV_NAME, trans);
3318                 if (ret) {
3319                         IWL_ERR(trans, "Error allocating IRQ %d\n", pdev->irq);
3320                         goto out_free_ict;
3321                 }
3322                 trans_pcie->inta_mask = CSR_INI_SET_MASK;
3323          }
3324
3325         trans_pcie->rba.alloc_wq = alloc_workqueue("rb_allocator",
3326                                                    WQ_HIGHPRI | WQ_UNBOUND, 1);
3327         INIT_WORK(&trans_pcie->rba.rx_alloc, iwl_pcie_rx_allocator_work);
3328
3329 #ifdef CONFIG_IWLWIFI_PCIE_RTPM
3330         trans->runtime_pm_mode = IWL_PLAT_PM_MODE_D0I3;
3331 #else
3332         trans->runtime_pm_mode = IWL_PLAT_PM_MODE_DISABLED;
3333 #endif /* CONFIG_IWLWIFI_PCIE_RTPM */
3334
3335         return trans;
3336
3337 out_free_ict:
3338         iwl_pcie_free_ict(trans);
3339 out_no_pci:
3340         free_percpu(trans_pcie->tso_hdr_page);
3341         iwl_trans_free(trans);
3342         return ERR_PTR(ret);
3343 }